imsttfb.c 43 KB

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  1. /*
  2. * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
  3. *
  4. * This file is derived from the powermac console "imstt" driver:
  5. * Copyright (C) 1997 Sigurdur Asgeirsson
  6. * With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu)
  7. * Modified by Danilo Beuche 1998
  8. * Some register values added by Damien Doligez, INRIA Rocquencourt
  9. * Various cleanups by Paul Mundt (lethal@chaoticdreams.org)
  10. *
  11. * This file was written by Ryan Nielsen (ran@krazynet.com)
  12. * Most of the frame buffer device stuff was copied from atyfb.c
  13. *
  14. * This file is subject to the terms and conditions of the GNU General Public
  15. * License. See the file COPYING in the main directory of this archive for
  16. * more details.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/kernel.h>
  20. #include <linux/errno.h>
  21. #include <linux/string.h>
  22. #include <linux/mm.h>
  23. #include <linux/vmalloc.h>
  24. #include <linux/delay.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/fb.h>
  27. #include <linux/init.h>
  28. #include <linux/pci.h>
  29. #include <asm/io.h>
  30. #include <linux/uaccess.h>
  31. #if defined(CONFIG_PPC)
  32. #include <linux/nvram.h>
  33. #include <asm/prom.h>
  34. #include "macmodes.h"
  35. #endif
  36. #ifndef __powerpc__
  37. #define eieio() /* Enforce In-order Execution of I/O */
  38. #endif
  39. /* TwinTurbo (Cosmo) registers */
  40. enum {
  41. S1SA = 0, /* 0x00 */
  42. S2SA = 1, /* 0x04 */
  43. SP = 2, /* 0x08 */
  44. DSA = 3, /* 0x0C */
  45. CNT = 4, /* 0x10 */
  46. DP_OCTL = 5, /* 0x14 */
  47. CLR = 6, /* 0x18 */
  48. BI = 8, /* 0x20 */
  49. MBC = 9, /* 0x24 */
  50. BLTCTL = 10, /* 0x28 */
  51. /* Scan Timing Generator Registers */
  52. HES = 12, /* 0x30 */
  53. HEB = 13, /* 0x34 */
  54. HSB = 14, /* 0x38 */
  55. HT = 15, /* 0x3C */
  56. VES = 16, /* 0x40 */
  57. VEB = 17, /* 0x44 */
  58. VSB = 18, /* 0x48 */
  59. VT = 19, /* 0x4C */
  60. HCIV = 20, /* 0x50 */
  61. VCIV = 21, /* 0x54 */
  62. TCDR = 22, /* 0x58 */
  63. VIL = 23, /* 0x5C */
  64. STGCTL = 24, /* 0x60 */
  65. /* Screen Refresh Generator Registers */
  66. SSR = 25, /* 0x64 */
  67. HRIR = 26, /* 0x68 */
  68. SPR = 27, /* 0x6C */
  69. CMR = 28, /* 0x70 */
  70. SRGCTL = 29, /* 0x74 */
  71. /* RAM Refresh Generator Registers */
  72. RRCIV = 30, /* 0x78 */
  73. RRSC = 31, /* 0x7C */
  74. RRCR = 34, /* 0x88 */
  75. /* System Registers */
  76. GIOE = 32, /* 0x80 */
  77. GIO = 33, /* 0x84 */
  78. SCR = 35, /* 0x8C */
  79. SSTATUS = 36, /* 0x90 */
  80. PRC = 37, /* 0x94 */
  81. #if 0
  82. /* PCI Registers */
  83. DVID = 0x00000000L,
  84. SC = 0x00000004L,
  85. CCR = 0x00000008L,
  86. OG = 0x0000000CL,
  87. BARM = 0x00000010L,
  88. BARER = 0x00000030L,
  89. #endif
  90. };
  91. /* IBM 624 RAMDAC Direct Registers */
  92. enum {
  93. PADDRW = 0x00,
  94. PDATA = 0x04,
  95. PPMASK = 0x08,
  96. PADDRR = 0x0c,
  97. PIDXLO = 0x10,
  98. PIDXHI = 0x14,
  99. PIDXDATA= 0x18,
  100. PIDXCTL = 0x1c
  101. };
  102. /* IBM 624 RAMDAC Indirect Registers */
  103. enum {
  104. CLKCTL = 0x02, /* (0x01) Miscellaneous Clock Control */
  105. SYNCCTL = 0x03, /* (0x00) Sync Control */
  106. HSYNCPOS = 0x04, /* (0x00) Horizontal Sync Position */
  107. PWRMNGMT = 0x05, /* (0x00) Power Management */
  108. DACOP = 0x06, /* (0x02) DAC Operation */
  109. PALETCTL = 0x07, /* (0x00) Palette Control */
  110. SYSCLKCTL = 0x08, /* (0x01) System Clock Control */
  111. PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
  112. BPP8 = 0x0b, /* () 8 Bits/Pixel Control */
  113. BPP16 = 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */
  114. BPP24 = 0x0d, /* () 24 Bits/Pixel Control */
  115. BPP32 = 0x0e, /* () 32 Bits/Pixel Control */
  116. PIXCTL1 = 0x10, /* (0x05) Pixel PLL Control 1 */
  117. PIXCTL2 = 0x11, /* (0x00) Pixel PLL Control 2 */
  118. SYSCLKN = 0x15, /* () System Clock N (System PLL Reference Divider) */
  119. SYSCLKM = 0x16, /* () System Clock M (System PLL VCO Divider) */
  120. SYSCLKP = 0x17, /* () System Clock P */
  121. SYSCLKC = 0x18, /* () System Clock C */
  122. /*
  123. * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
  124. * c is charge pump bias which depends on the VCO frequency
  125. */
  126. PIXM0 = 0x20, /* () Pixel M 0 */
  127. PIXN0 = 0x21, /* () Pixel N 0 */
  128. PIXP0 = 0x22, /* () Pixel P 0 */
  129. PIXC0 = 0x23, /* () Pixel C 0 */
  130. CURSCTL = 0x30, /* (0x00) Cursor Control */
  131. CURSXLO = 0x31, /* () Cursor X position, low 8 bits */
  132. CURSXHI = 0x32, /* () Cursor X position, high 8 bits */
  133. CURSYLO = 0x33, /* () Cursor Y position, low 8 bits */
  134. CURSYHI = 0x34, /* () Cursor Y position, high 8 bits */
  135. CURSHOTX = 0x35, /* () Cursor Hot Spot X */
  136. CURSHOTY = 0x36, /* () Cursor Hot Spot Y */
  137. CURSACCTL = 0x37, /* () Advanced Cursor Control Enable */
  138. CURSACATTR = 0x38, /* () Advanced Cursor Attribute */
  139. CURS1R = 0x40, /* () Cursor 1 Red */
  140. CURS1G = 0x41, /* () Cursor 1 Green */
  141. CURS1B = 0x42, /* () Cursor 1 Blue */
  142. CURS2R = 0x43, /* () Cursor 2 Red */
  143. CURS2G = 0x44, /* () Cursor 2 Green */
  144. CURS2B = 0x45, /* () Cursor 2 Blue */
  145. CURS3R = 0x46, /* () Cursor 3 Red */
  146. CURS3G = 0x47, /* () Cursor 3 Green */
  147. CURS3B = 0x48, /* () Cursor 3 Blue */
  148. BORDR = 0x60, /* () Border Color Red */
  149. BORDG = 0x61, /* () Border Color Green */
  150. BORDB = 0x62, /* () Border Color Blue */
  151. MISCTL1 = 0x70, /* (0x00) Miscellaneous Control 1 */
  152. MISCTL2 = 0x71, /* (0x00) Miscellaneous Control 2 */
  153. MISCTL3 = 0x72, /* (0x00) Miscellaneous Control 3 */
  154. KEYCTL = 0x78 /* (0x00) Key Control/DB Operation */
  155. };
  156. /* TI TVP 3030 RAMDAC Direct Registers */
  157. enum {
  158. TVPADDRW = 0x00, /* 0 Palette/Cursor RAM Write Address/Index */
  159. TVPPDATA = 0x04, /* 1 Palette Data RAM Data */
  160. TVPPMASK = 0x08, /* 2 Pixel Read-Mask */
  161. TVPPADRR = 0x0c, /* 3 Palette/Cursor RAM Read Address */
  162. TVPCADRW = 0x10, /* 4 Cursor/Overscan Color Write Address */
  163. TVPCDATA = 0x14, /* 5 Cursor/Overscan Color Data */
  164. /* 6 reserved */
  165. TVPCADRR = 0x1c, /* 7 Cursor/Overscan Color Read Address */
  166. /* 8 reserved */
  167. TVPDCCTL = 0x24, /* 9 Direct Cursor Control */
  168. TVPIDATA = 0x28, /* 10 Index Data */
  169. TVPCRDAT = 0x2c, /* 11 Cursor RAM Data */
  170. TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */
  171. TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */
  172. TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */
  173. TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */
  174. };
  175. /* TI TVP 3030 RAMDAC Indirect Registers */
  176. enum {
  177. TVPIRREV = 0x01, /* Silicon Revision [RO] */
  178. TVPIRICC = 0x06, /* Indirect Cursor Control (0x00) */
  179. TVPIRBRC = 0x07, /* Byte Router Control (0xe4) */
  180. TVPIRLAC = 0x0f, /* Latch Control (0x06) */
  181. TVPIRTCC = 0x18, /* True Color Control (0x80) */
  182. TVPIRMXC = 0x19, /* Multiplex Control (0x98) */
  183. TVPIRCLS = 0x1a, /* Clock Selection (0x07) */
  184. TVPIRPPG = 0x1c, /* Palette Page (0x00) */
  185. TVPIRGEC = 0x1d, /* General Control (0x00) */
  186. TVPIRMIC = 0x1e, /* Miscellaneous Control (0x00) */
  187. TVPIRPLA = 0x2c, /* PLL Address */
  188. TVPIRPPD = 0x2d, /* Pixel Clock PLL Data */
  189. TVPIRMPD = 0x2e, /* Memory Clock PLL Data */
  190. TVPIRLPD = 0x2f, /* Loop Clock PLL Data */
  191. TVPIRCKL = 0x30, /* Color-Key Overlay Low */
  192. TVPIRCKH = 0x31, /* Color-Key Overlay High */
  193. TVPIRCRL = 0x32, /* Color-Key Red Low */
  194. TVPIRCRH = 0x33, /* Color-Key Red High */
  195. TVPIRCGL = 0x34, /* Color-Key Green Low */
  196. TVPIRCGH = 0x35, /* Color-Key Green High */
  197. TVPIRCBL = 0x36, /* Color-Key Blue Low */
  198. TVPIRCBH = 0x37, /* Color-Key Blue High */
  199. TVPIRCKC = 0x38, /* Color-Key Control (0x00) */
  200. TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */
  201. TVPIRSEN = 0x3a, /* Sense Test (0x00) */
  202. TVPIRTMD = 0x3b, /* Test Mode Data */
  203. TVPIRRML = 0x3c, /* CRC Remainder LSB [RO] */
  204. TVPIRRMM = 0x3d, /* CRC Remainder MSB [RO] */
  205. TVPIRRMS = 0x3e, /* CRC Bit Select [WO] */
  206. TVPIRDID = 0x3f, /* Device ID [RO] (0x30) */
  207. TVPIRRES = 0xff /* Software Reset [WO] */
  208. };
  209. struct initvalues {
  210. __u8 addr, value;
  211. };
  212. static struct initvalues ibm_initregs[] = {
  213. { CLKCTL, 0x21 },
  214. { SYNCCTL, 0x00 },
  215. { HSYNCPOS, 0x00 },
  216. { PWRMNGMT, 0x00 },
  217. { DACOP, 0x02 },
  218. { PALETCTL, 0x00 },
  219. { SYSCLKCTL, 0x01 },
  220. /*
  221. * Note that colors in X are correct only if all video data is
  222. * passed through the palette in the DAC. That is, "indirect
  223. * color" must be configured. This is the case for the IBM DAC
  224. * used in the 2MB and 4MB cards, at least.
  225. */
  226. { BPP8, 0x00 },
  227. { BPP16, 0x01 },
  228. { BPP24, 0x00 },
  229. { BPP32, 0x00 },
  230. { PIXCTL1, 0x05 },
  231. { PIXCTL2, 0x00 },
  232. { SYSCLKN, 0x08 },
  233. { SYSCLKM, 0x4f },
  234. { SYSCLKP, 0x00 },
  235. { SYSCLKC, 0x00 },
  236. { CURSCTL, 0x00 },
  237. { CURSACCTL, 0x01 },
  238. { CURSACATTR, 0xa8 },
  239. { CURS1R, 0xff },
  240. { CURS1G, 0xff },
  241. { CURS1B, 0xff },
  242. { CURS2R, 0xff },
  243. { CURS2G, 0xff },
  244. { CURS2B, 0xff },
  245. { CURS3R, 0xff },
  246. { CURS3G, 0xff },
  247. { CURS3B, 0xff },
  248. { BORDR, 0xff },
  249. { BORDG, 0xff },
  250. { BORDB, 0xff },
  251. { MISCTL1, 0x01 },
  252. { MISCTL2, 0x45 },
  253. { MISCTL3, 0x00 },
  254. { KEYCTL, 0x00 }
  255. };
  256. static struct initvalues tvp_initregs[] = {
  257. { TVPIRICC, 0x00 },
  258. { TVPIRBRC, 0xe4 },
  259. { TVPIRLAC, 0x06 },
  260. { TVPIRTCC, 0x80 },
  261. { TVPIRMXC, 0x4d },
  262. { TVPIRCLS, 0x05 },
  263. { TVPIRPPG, 0x00 },
  264. { TVPIRGEC, 0x00 },
  265. { TVPIRMIC, 0x08 },
  266. { TVPIRCKL, 0xff },
  267. { TVPIRCKH, 0xff },
  268. { TVPIRCRL, 0xff },
  269. { TVPIRCRH, 0xff },
  270. { TVPIRCGL, 0xff },
  271. { TVPIRCGH, 0xff },
  272. { TVPIRCBL, 0xff },
  273. { TVPIRCBH, 0xff },
  274. { TVPIRCKC, 0x00 },
  275. { TVPIRPLA, 0x00 },
  276. { TVPIRPPD, 0xc0 },
  277. { TVPIRPPD, 0xd5 },
  278. { TVPIRPPD, 0xea },
  279. { TVPIRPLA, 0x00 },
  280. { TVPIRMPD, 0xb9 },
  281. { TVPIRMPD, 0x3a },
  282. { TVPIRMPD, 0xb1 },
  283. { TVPIRPLA, 0x00 },
  284. { TVPIRLPD, 0xc1 },
  285. { TVPIRLPD, 0x3d },
  286. { TVPIRLPD, 0xf3 },
  287. };
  288. struct imstt_regvals {
  289. __u32 pitch;
  290. __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil;
  291. __u8 pclk_m, pclk_n, pclk_p;
  292. /* Values of the tvp which change depending on colormode x resolution */
  293. __u8 mlc[3]; /* Memory Loop Config 0x39 */
  294. __u8 lckl_p[3]; /* P value of LCKL PLL */
  295. };
  296. struct imstt_par {
  297. struct imstt_regvals init;
  298. __u32 __iomem *dc_regs;
  299. unsigned long cmap_regs_phys;
  300. __u8 *cmap_regs;
  301. __u32 ramdac;
  302. __u32 palette[16];
  303. };
  304. enum {
  305. IBM = 0,
  306. TVP = 1
  307. };
  308. #define USE_NV_MODES 1
  309. #define INIT_BPP 8
  310. #define INIT_XRES 640
  311. #define INIT_YRES 480
  312. static int inverse = 0;
  313. static char fontname[40] __initdata = { 0 };
  314. #if defined(CONFIG_PPC)
  315. static signed char init_vmode = -1, init_cmode = -1;
  316. #endif
  317. static struct imstt_regvals tvp_reg_init_2 = {
  318. 512,
  319. 0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
  320. 0xec, 0x2a, 0xf3,
  321. { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
  322. };
  323. static struct imstt_regvals tvp_reg_init_6 = {
  324. 640,
  325. 0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
  326. 0xef, 0x2e, 0xb2,
  327. { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
  328. };
  329. static struct imstt_regvals tvp_reg_init_12 = {
  330. 800,
  331. 0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
  332. 0xf6, 0x2e, 0xf2,
  333. { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
  334. };
  335. static struct imstt_regvals tvp_reg_init_13 = {
  336. 832,
  337. 0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
  338. 0xfe, 0x3e, 0xf1,
  339. { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
  340. };
  341. static struct imstt_regvals tvp_reg_init_17 = {
  342. 1024,
  343. 0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
  344. 0xfc, 0x3a, 0xf1,
  345. { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
  346. };
  347. static struct imstt_regvals tvp_reg_init_18 = {
  348. 1152,
  349. 0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
  350. 0xfd, 0x3a, 0xf1,
  351. { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
  352. };
  353. static struct imstt_regvals tvp_reg_init_19 = {
  354. 1280,
  355. 0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
  356. 0xf7, 0x36, 0xf0,
  357. { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
  358. };
  359. static struct imstt_regvals tvp_reg_init_20 = {
  360. 1280,
  361. 0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
  362. 0xf0, 0x2d, 0xf0,
  363. { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
  364. };
  365. /*
  366. * PCI driver prototypes
  367. */
  368. static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  369. static void imsttfb_remove(struct pci_dev *pdev);
  370. /*
  371. * Register access
  372. */
  373. static inline u32 read_reg_le32(volatile u32 __iomem *base, int regindex)
  374. {
  375. #ifdef __powerpc__
  376. return in_le32(base + regindex);
  377. #else
  378. return readl(base + regindex);
  379. #endif
  380. }
  381. static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val)
  382. {
  383. #ifdef __powerpc__
  384. out_le32(base + regindex, val);
  385. #else
  386. writel(val, base + regindex);
  387. #endif
  388. }
  389. static __u32
  390. getclkMHz(struct imstt_par *par)
  391. {
  392. __u32 clk_m, clk_n, clk_p;
  393. clk_m = par->init.pclk_m;
  394. clk_n = par->init.pclk_n;
  395. clk_p = par->init.pclk_p;
  396. return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
  397. }
  398. static void
  399. setclkMHz(struct imstt_par *par, __u32 MHz)
  400. {
  401. __u32 clk_m, clk_n, x, stage, spilled;
  402. clk_m = clk_n = 0;
  403. stage = spilled = 0;
  404. for (;;) {
  405. switch (stage) {
  406. case 0:
  407. clk_m++;
  408. break;
  409. case 1:
  410. clk_n++;
  411. break;
  412. }
  413. x = 20 * (clk_m + 1) / (clk_n + 1);
  414. if (x == MHz)
  415. break;
  416. if (x > MHz) {
  417. spilled = 1;
  418. stage = 1;
  419. } else if (spilled && x < MHz) {
  420. stage = 0;
  421. }
  422. }
  423. par->init.pclk_m = clk_m;
  424. par->init.pclk_n = clk_n;
  425. par->init.pclk_p = 0;
  426. }
  427. static struct imstt_regvals *
  428. compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres)
  429. {
  430. struct imstt_regvals *init = &par->init;
  431. __u32 MHz, hes, heb, veb, htp, vtp;
  432. switch (xres) {
  433. case 640:
  434. hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2;
  435. MHz = 30 /* .25 */ ;
  436. break;
  437. case 832:
  438. hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3;
  439. MHz = 57 /* .27_ */ ;
  440. break;
  441. case 1024:
  442. hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3;
  443. MHz = 80;
  444. break;
  445. case 1152:
  446. hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3;
  447. MHz = 101 /* .6_ */ ;
  448. break;
  449. case 1280:
  450. hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1;
  451. MHz = yres == 960 ? 126 : 135;
  452. break;
  453. case 1600:
  454. hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3;
  455. MHz = 200;
  456. break;
  457. default:
  458. return NULL;
  459. }
  460. setclkMHz(par, MHz);
  461. init->hes = hes;
  462. init->heb = heb;
  463. init->hsb = init->heb + (xres >> 3);
  464. init->ht = init->hsb + htp;
  465. init->ves = 0x0003;
  466. init->veb = veb;
  467. init->vsb = init->veb + yres;
  468. init->vt = init->vsb + vtp;
  469. init->vil = init->vsb;
  470. init->pitch = xres;
  471. return init;
  472. }
  473. static struct imstt_regvals *
  474. compute_imstt_regvals_tvp(struct imstt_par *par, int xres, int yres)
  475. {
  476. struct imstt_regvals *init;
  477. switch (xres) {
  478. case 512:
  479. init = &tvp_reg_init_2;
  480. break;
  481. case 640:
  482. init = &tvp_reg_init_6;
  483. break;
  484. case 800:
  485. init = &tvp_reg_init_12;
  486. break;
  487. case 832:
  488. init = &tvp_reg_init_13;
  489. break;
  490. case 1024:
  491. init = &tvp_reg_init_17;
  492. break;
  493. case 1152:
  494. init = &tvp_reg_init_18;
  495. break;
  496. case 1280:
  497. init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20;
  498. break;
  499. default:
  500. return NULL;
  501. }
  502. par->init = *init;
  503. return init;
  504. }
  505. static struct imstt_regvals *
  506. compute_imstt_regvals (struct imstt_par *par, u_int xres, u_int yres)
  507. {
  508. if (par->ramdac == IBM)
  509. return compute_imstt_regvals_ibm(par, xres, yres);
  510. else
  511. return compute_imstt_regvals_tvp(par, xres, yres);
  512. }
  513. static void
  514. set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp)
  515. {
  516. struct imstt_regvals *init = &par->init;
  517. __u8 pformat = (bpp >> 3) + 2;
  518. par->cmap_regs[PIDXHI] = 0; eieio();
  519. par->cmap_regs[PIDXLO] = PIXM0; eieio();
  520. par->cmap_regs[PIDXDATA] = init->pclk_m;eieio();
  521. par->cmap_regs[PIDXLO] = PIXN0; eieio();
  522. par->cmap_regs[PIDXDATA] = init->pclk_n;eieio();
  523. par->cmap_regs[PIDXLO] = PIXP0; eieio();
  524. par->cmap_regs[PIDXDATA] = init->pclk_p;eieio();
  525. par->cmap_regs[PIDXLO] = PIXC0; eieio();
  526. par->cmap_regs[PIDXDATA] = 0x02; eieio();
  527. par->cmap_regs[PIDXLO] = PIXFMT; eieio();
  528. par->cmap_regs[PIDXDATA] = pformat; eieio();
  529. }
  530. static void
  531. set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp)
  532. {
  533. struct imstt_regvals *init = &par->init;
  534. __u8 tcc, mxc, lckl_n, mic;
  535. __u8 mlc, lckl_p;
  536. switch (bpp) {
  537. default:
  538. case 8:
  539. tcc = 0x80;
  540. mxc = 0x4d;
  541. lckl_n = 0xc1;
  542. mlc = init->mlc[0];
  543. lckl_p = init->lckl_p[0];
  544. break;
  545. case 16:
  546. tcc = 0x44;
  547. mxc = 0x55;
  548. lckl_n = 0xe1;
  549. mlc = init->mlc[1];
  550. lckl_p = init->lckl_p[1];
  551. break;
  552. case 24:
  553. tcc = 0x5e;
  554. mxc = 0x5d;
  555. lckl_n = 0xf1;
  556. mlc = init->mlc[2];
  557. lckl_p = init->lckl_p[2];
  558. break;
  559. case 32:
  560. tcc = 0x46;
  561. mxc = 0x5d;
  562. lckl_n = 0xf1;
  563. mlc = init->mlc[2];
  564. lckl_p = init->lckl_p[2];
  565. break;
  566. }
  567. mic = 0x08;
  568. par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
  569. par->cmap_regs[TVPIDATA] = 0x00; eieio();
  570. par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
  571. par->cmap_regs[TVPIDATA] = init->pclk_m; eieio();
  572. par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
  573. par->cmap_regs[TVPIDATA] = init->pclk_n; eieio();
  574. par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
  575. par->cmap_regs[TVPIDATA] = init->pclk_p; eieio();
  576. par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
  577. par->cmap_regs[TVPIDATA] = tcc; eieio();
  578. par->cmap_regs[TVPADDRW] = TVPIRMXC; eieio();
  579. par->cmap_regs[TVPIDATA] = mxc; eieio();
  580. par->cmap_regs[TVPADDRW] = TVPIRMIC; eieio();
  581. par->cmap_regs[TVPIDATA] = mic; eieio();
  582. par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
  583. par->cmap_regs[TVPIDATA] = 0x00; eieio();
  584. par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
  585. par->cmap_regs[TVPIDATA] = lckl_n; eieio();
  586. par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
  587. par->cmap_regs[TVPIDATA] = 0x15; eieio();
  588. par->cmap_regs[TVPADDRW] = TVPIRMLC; eieio();
  589. par->cmap_regs[TVPIDATA] = mlc; eieio();
  590. par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
  591. par->cmap_regs[TVPIDATA] = 0x2a; eieio();
  592. par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
  593. par->cmap_regs[TVPIDATA] = lckl_p; eieio();
  594. }
  595. static void
  596. set_imstt_regvals (struct fb_info *info, u_int bpp)
  597. {
  598. struct imstt_par *par = info->par;
  599. struct imstt_regvals *init = &par->init;
  600. __u32 ctl, pitch, byteswap, scr;
  601. if (par->ramdac == IBM)
  602. set_imstt_regvals_ibm(par, bpp);
  603. else
  604. set_imstt_regvals_tvp(par, bpp);
  605. /*
  606. * From what I (jsk) can gather poking around with MacsBug,
  607. * bits 8 and 9 in the SCR register control endianness
  608. * correction (byte swapping). These bits must be set according
  609. * to the color depth as follows:
  610. * Color depth Bit 9 Bit 8
  611. * ========== ===== =====
  612. * 8bpp 0 0
  613. * 16bpp 0 1
  614. * 32bpp 1 1
  615. */
  616. switch (bpp) {
  617. default:
  618. case 8:
  619. ctl = 0x17b1;
  620. pitch = init->pitch >> 2;
  621. byteswap = 0x000;
  622. break;
  623. case 16:
  624. ctl = 0x17b3;
  625. pitch = init->pitch >> 1;
  626. byteswap = 0x100;
  627. break;
  628. case 24:
  629. ctl = 0x17b9;
  630. pitch = init->pitch - (init->pitch >> 2);
  631. byteswap = 0x200;
  632. break;
  633. case 32:
  634. ctl = 0x17b5;
  635. pitch = init->pitch;
  636. byteswap = 0x300;
  637. break;
  638. }
  639. if (par->ramdac == TVP)
  640. ctl -= 0x30;
  641. write_reg_le32(par->dc_regs, HES, init->hes);
  642. write_reg_le32(par->dc_regs, HEB, init->heb);
  643. write_reg_le32(par->dc_regs, HSB, init->hsb);
  644. write_reg_le32(par->dc_regs, HT, init->ht);
  645. write_reg_le32(par->dc_regs, VES, init->ves);
  646. write_reg_le32(par->dc_regs, VEB, init->veb);
  647. write_reg_le32(par->dc_regs, VSB, init->vsb);
  648. write_reg_le32(par->dc_regs, VT, init->vt);
  649. write_reg_le32(par->dc_regs, VIL, init->vil);
  650. write_reg_le32(par->dc_regs, HCIV, 1);
  651. write_reg_le32(par->dc_regs, VCIV, 1);
  652. write_reg_le32(par->dc_regs, TCDR, 4);
  653. write_reg_le32(par->dc_regs, RRCIV, 1);
  654. write_reg_le32(par->dc_regs, RRSC, 0x980);
  655. write_reg_le32(par->dc_regs, RRCR, 0x11);
  656. if (par->ramdac == IBM) {
  657. write_reg_le32(par->dc_regs, HRIR, 0x0100);
  658. write_reg_le32(par->dc_regs, CMR, 0x00ff);
  659. write_reg_le32(par->dc_regs, SRGCTL, 0x0073);
  660. } else {
  661. write_reg_le32(par->dc_regs, HRIR, 0x0200);
  662. write_reg_le32(par->dc_regs, CMR, 0x01ff);
  663. write_reg_le32(par->dc_regs, SRGCTL, 0x0003);
  664. }
  665. switch (info->fix.smem_len) {
  666. case 0x200000:
  667. scr = 0x059d | byteswap;
  668. break;
  669. /* case 0x400000:
  670. case 0x800000: */
  671. default:
  672. pitch >>= 1;
  673. scr = 0x150dd | byteswap;
  674. break;
  675. }
  676. write_reg_le32(par->dc_regs, SCR, scr);
  677. write_reg_le32(par->dc_regs, SPR, pitch);
  678. write_reg_le32(par->dc_regs, STGCTL, ctl);
  679. }
  680. static inline void
  681. set_offset (struct fb_var_screeninfo *var, struct fb_info *info)
  682. {
  683. struct imstt_par *par = info->par;
  684. __u32 off = var->yoffset * (info->fix.line_length >> 3)
  685. + ((var->xoffset * (info->var.bits_per_pixel >> 3)) >> 3);
  686. write_reg_le32(par->dc_regs, SSR, off);
  687. }
  688. static inline void
  689. set_555 (struct imstt_par *par)
  690. {
  691. if (par->ramdac == IBM) {
  692. par->cmap_regs[PIDXHI] = 0; eieio();
  693. par->cmap_regs[PIDXLO] = BPP16; eieio();
  694. par->cmap_regs[PIDXDATA] = 0x01; eieio();
  695. } else {
  696. par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
  697. par->cmap_regs[TVPIDATA] = 0x44; eieio();
  698. }
  699. }
  700. static inline void
  701. set_565 (struct imstt_par *par)
  702. {
  703. if (par->ramdac == IBM) {
  704. par->cmap_regs[PIDXHI] = 0; eieio();
  705. par->cmap_regs[PIDXLO] = BPP16; eieio();
  706. par->cmap_regs[PIDXDATA] = 0x03; eieio();
  707. } else {
  708. par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
  709. par->cmap_regs[TVPIDATA] = 0x45; eieio();
  710. }
  711. }
  712. static int
  713. imsttfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  714. {
  715. if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16
  716. && var->bits_per_pixel != 24 && var->bits_per_pixel != 32)
  717. || var->xres_virtual < var->xres || var->yres_virtual < var->yres
  718. || var->nonstd
  719. || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
  720. return -EINVAL;
  721. if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > info->fix.smem_len
  722. || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > info->fix.smem_len)
  723. return -EINVAL;
  724. switch (var->bits_per_pixel) {
  725. case 8:
  726. var->red.offset = 0;
  727. var->red.length = 8;
  728. var->green.offset = 0;
  729. var->green.length = 8;
  730. var->blue.offset = 0;
  731. var->blue.length = 8;
  732. var->transp.offset = 0;
  733. var->transp.length = 0;
  734. break;
  735. case 16: /* RGB 555 or 565 */
  736. if (var->green.length != 6)
  737. var->red.offset = 10;
  738. var->red.length = 5;
  739. var->green.offset = 5;
  740. if (var->green.length != 6)
  741. var->green.length = 5;
  742. var->blue.offset = 0;
  743. var->blue.length = 5;
  744. var->transp.offset = 0;
  745. var->transp.length = 0;
  746. break;
  747. case 24: /* RGB 888 */
  748. var->red.offset = 16;
  749. var->red.length = 8;
  750. var->green.offset = 8;
  751. var->green.length = 8;
  752. var->blue.offset = 0;
  753. var->blue.length = 8;
  754. var->transp.offset = 0;
  755. var->transp.length = 0;
  756. break;
  757. case 32: /* RGBA 8888 */
  758. var->red.offset = 16;
  759. var->red.length = 8;
  760. var->green.offset = 8;
  761. var->green.length = 8;
  762. var->blue.offset = 0;
  763. var->blue.length = 8;
  764. var->transp.offset = 24;
  765. var->transp.length = 8;
  766. break;
  767. }
  768. if (var->yres == var->yres_virtual) {
  769. __u32 vram = (info->fix.smem_len - (PAGE_SIZE << 2));
  770. var->yres_virtual = ((vram << 3) / var->bits_per_pixel) / var->xres_virtual;
  771. if (var->yres_virtual < var->yres)
  772. var->yres_virtual = var->yres;
  773. }
  774. var->red.msb_right = 0;
  775. var->green.msb_right = 0;
  776. var->blue.msb_right = 0;
  777. var->transp.msb_right = 0;
  778. var->height = -1;
  779. var->width = -1;
  780. var->vmode = FB_VMODE_NONINTERLACED;
  781. var->left_margin = var->right_margin = 16;
  782. var->upper_margin = var->lower_margin = 16;
  783. var->hsync_len = var->vsync_len = 8;
  784. return 0;
  785. }
  786. static int
  787. imsttfb_set_par(struct fb_info *info)
  788. {
  789. struct imstt_par *par = info->par;
  790. if (!compute_imstt_regvals(par, info->var.xres, info->var.yres))
  791. return -EINVAL;
  792. if (info->var.green.length == 6)
  793. set_565(par);
  794. else
  795. set_555(par);
  796. set_imstt_regvals(info, info->var.bits_per_pixel);
  797. info->var.pixclock = 1000000 / getclkMHz(par);
  798. return 0;
  799. }
  800. static int
  801. imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue,
  802. u_int transp, struct fb_info *info)
  803. {
  804. struct imstt_par *par = info->par;
  805. u_int bpp = info->var.bits_per_pixel;
  806. if (regno > 255)
  807. return 1;
  808. red >>= 8;
  809. green >>= 8;
  810. blue >>= 8;
  811. /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
  812. if (0 && bpp == 16) /* screws up X */
  813. par->cmap_regs[PADDRW] = regno << 3;
  814. else
  815. par->cmap_regs[PADDRW] = regno;
  816. eieio();
  817. par->cmap_regs[PDATA] = red; eieio();
  818. par->cmap_regs[PDATA] = green; eieio();
  819. par->cmap_regs[PDATA] = blue; eieio();
  820. if (regno < 16)
  821. switch (bpp) {
  822. case 16:
  823. par->palette[regno] =
  824. (regno << (info->var.green.length ==
  825. 5 ? 10 : 11)) | (regno << 5) | regno;
  826. break;
  827. case 24:
  828. par->palette[regno] =
  829. (regno << 16) | (regno << 8) | regno;
  830. break;
  831. case 32: {
  832. int i = (regno << 8) | regno;
  833. par->palette[regno] = (i << 16) |i;
  834. break;
  835. }
  836. }
  837. return 0;
  838. }
  839. static int
  840. imsttfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  841. {
  842. if (var->xoffset + info->var.xres > info->var.xres_virtual
  843. || var->yoffset + info->var.yres > info->var.yres_virtual)
  844. return -EINVAL;
  845. info->var.xoffset = var->xoffset;
  846. info->var.yoffset = var->yoffset;
  847. set_offset(var, info);
  848. return 0;
  849. }
  850. static int
  851. imsttfb_blank(int blank, struct fb_info *info)
  852. {
  853. struct imstt_par *par = info->par;
  854. __u32 ctrl;
  855. ctrl = read_reg_le32(par->dc_regs, STGCTL);
  856. if (blank > 0) {
  857. switch (blank) {
  858. case FB_BLANK_NORMAL:
  859. case FB_BLANK_POWERDOWN:
  860. ctrl &= ~0x00000380;
  861. if (par->ramdac == IBM) {
  862. par->cmap_regs[PIDXHI] = 0; eieio();
  863. par->cmap_regs[PIDXLO] = MISCTL2; eieio();
  864. par->cmap_regs[PIDXDATA] = 0x55; eieio();
  865. par->cmap_regs[PIDXLO] = MISCTL1; eieio();
  866. par->cmap_regs[PIDXDATA] = 0x11; eieio();
  867. par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
  868. par->cmap_regs[PIDXDATA] = 0x0f; eieio();
  869. par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
  870. par->cmap_regs[PIDXDATA] = 0x1f; eieio();
  871. par->cmap_regs[PIDXLO] = CLKCTL; eieio();
  872. par->cmap_regs[PIDXDATA] = 0xc0;
  873. }
  874. break;
  875. case FB_BLANK_VSYNC_SUSPEND:
  876. ctrl &= ~0x00000020;
  877. break;
  878. case FB_BLANK_HSYNC_SUSPEND:
  879. ctrl &= ~0x00000010;
  880. break;
  881. }
  882. } else {
  883. if (par->ramdac == IBM) {
  884. ctrl |= 0x000017b0;
  885. par->cmap_regs[PIDXHI] = 0; eieio();
  886. par->cmap_regs[PIDXLO] = CLKCTL; eieio();
  887. par->cmap_regs[PIDXDATA] = 0x01; eieio();
  888. par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
  889. par->cmap_regs[PIDXDATA] = 0x00; eieio();
  890. par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
  891. par->cmap_regs[PIDXDATA] = 0x00; eieio();
  892. par->cmap_regs[PIDXLO] = MISCTL1; eieio();
  893. par->cmap_regs[PIDXDATA] = 0x01; eieio();
  894. par->cmap_regs[PIDXLO] = MISCTL2; eieio();
  895. par->cmap_regs[PIDXDATA] = 0x45; eieio();
  896. } else
  897. ctrl |= 0x00001780;
  898. }
  899. write_reg_le32(par->dc_regs, STGCTL, ctrl);
  900. return 0;
  901. }
  902. static void
  903. imsttfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  904. {
  905. struct imstt_par *par = info->par;
  906. __u32 Bpp, line_pitch, bgc, dx, dy, width, height;
  907. bgc = rect->color;
  908. bgc |= (bgc << 8);
  909. bgc |= (bgc << 16);
  910. Bpp = info->var.bits_per_pixel >> 3,
  911. line_pitch = info->fix.line_length;
  912. dy = rect->dy * line_pitch;
  913. dx = rect->dx * Bpp;
  914. height = rect->height;
  915. height--;
  916. width = rect->width * Bpp;
  917. width--;
  918. if (rect->rop == ROP_COPY) {
  919. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  920. write_reg_le32(par->dc_regs, DSA, dy + dx);
  921. write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
  922. write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
  923. write_reg_le32(par->dc_regs, BI, 0xffffffff);
  924. write_reg_le32(par->dc_regs, MBC, 0xffffffff);
  925. write_reg_le32(par->dc_regs, CLR, bgc);
  926. write_reg_le32(par->dc_regs, BLTCTL, 0x840); /* 0x200000 */
  927. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  928. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
  929. } else {
  930. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  931. write_reg_le32(par->dc_regs, DSA, dy + dx);
  932. write_reg_le32(par->dc_regs, S1SA, dy + dx);
  933. write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
  934. write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
  935. write_reg_le32(par->dc_regs, SP, line_pitch);
  936. write_reg_le32(par->dc_regs, BLTCTL, 0x40005);
  937. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  938. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
  939. }
  940. }
  941. static void
  942. imsttfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  943. {
  944. struct imstt_par *par = info->par;
  945. __u32 Bpp, line_pitch, fb_offset_old, fb_offset_new, sp, dp_octl;
  946. __u32 cnt, bltctl, sx, sy, dx, dy, height, width;
  947. Bpp = info->var.bits_per_pixel >> 3,
  948. sx = area->sx * Bpp;
  949. sy = area->sy;
  950. dx = area->dx * Bpp;
  951. dy = area->dy;
  952. height = area->height;
  953. height--;
  954. width = area->width * Bpp;
  955. width--;
  956. line_pitch = info->fix.line_length;
  957. bltctl = 0x05;
  958. sp = line_pitch << 16;
  959. cnt = height << 16;
  960. if (sy < dy) {
  961. sy += height;
  962. dy += height;
  963. sp |= -(line_pitch) & 0xffff;
  964. dp_octl = -(line_pitch) & 0xffff;
  965. } else {
  966. sp |= line_pitch;
  967. dp_octl = line_pitch;
  968. }
  969. if (sx < dx) {
  970. sx += width;
  971. dx += width;
  972. bltctl |= 0x80;
  973. cnt |= -(width) & 0xffff;
  974. } else {
  975. cnt |= width;
  976. }
  977. fb_offset_old = sy * line_pitch + sx;
  978. fb_offset_new = dy * line_pitch + dx;
  979. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  980. write_reg_le32(par->dc_regs, S1SA, fb_offset_old);
  981. write_reg_le32(par->dc_regs, SP, sp);
  982. write_reg_le32(par->dc_regs, DSA, fb_offset_new);
  983. write_reg_le32(par->dc_regs, CNT, cnt);
  984. write_reg_le32(par->dc_regs, DP_OCTL, dp_octl);
  985. write_reg_le32(par->dc_regs, BLTCTL, bltctl);
  986. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  987. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
  988. }
  989. #if 0
  990. static int
  991. imsttfb_load_cursor_image(struct imstt_par *par, int width, int height, __u8 fgc)
  992. {
  993. u_int x, y;
  994. if (width > 32 || height > 32)
  995. return -EINVAL;
  996. if (par->ramdac == IBM) {
  997. par->cmap_regs[PIDXHI] = 1; eieio();
  998. for (x = 0; x < 0x100; x++) {
  999. par->cmap_regs[PIDXLO] = x; eieio();
  1000. par->cmap_regs[PIDXDATA] = 0x00; eieio();
  1001. }
  1002. par->cmap_regs[PIDXHI] = 1; eieio();
  1003. for (y = 0; y < height; y++)
  1004. for (x = 0; x < width >> 2; x++) {
  1005. par->cmap_regs[PIDXLO] = x + y * 8; eieio();
  1006. par->cmap_regs[PIDXDATA] = 0xff; eieio();
  1007. }
  1008. par->cmap_regs[PIDXHI] = 0; eieio();
  1009. par->cmap_regs[PIDXLO] = CURS1R; eieio();
  1010. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1011. par->cmap_regs[PIDXLO] = CURS1G; eieio();
  1012. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1013. par->cmap_regs[PIDXLO] = CURS1B; eieio();
  1014. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1015. par->cmap_regs[PIDXLO] = CURS2R; eieio();
  1016. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1017. par->cmap_regs[PIDXLO] = CURS2G; eieio();
  1018. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1019. par->cmap_regs[PIDXLO] = CURS2B; eieio();
  1020. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1021. par->cmap_regs[PIDXLO] = CURS3R; eieio();
  1022. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1023. par->cmap_regs[PIDXLO] = CURS3G; eieio();
  1024. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1025. par->cmap_regs[PIDXLO] = CURS3B; eieio();
  1026. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1027. } else {
  1028. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1029. par->cmap_regs[TVPIDATA] &= 0x03; eieio();
  1030. par->cmap_regs[TVPADDRW] = 0; eieio();
  1031. for (x = 0; x < 0x200; x++) {
  1032. par->cmap_regs[TVPCRDAT] = 0x00; eieio();
  1033. }
  1034. for (x = 0; x < 0x200; x++) {
  1035. par->cmap_regs[TVPCRDAT] = 0xff; eieio();
  1036. }
  1037. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1038. par->cmap_regs[TVPIDATA] &= 0x03; eieio();
  1039. for (y = 0; y < height; y++)
  1040. for (x = 0; x < width >> 3; x++) {
  1041. par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
  1042. par->cmap_regs[TVPCRDAT] = 0xff; eieio();
  1043. }
  1044. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1045. par->cmap_regs[TVPIDATA] |= 0x08; eieio();
  1046. for (y = 0; y < height; y++)
  1047. for (x = 0; x < width >> 3; x++) {
  1048. par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
  1049. par->cmap_regs[TVPCRDAT] = 0xff; eieio();
  1050. }
  1051. par->cmap_regs[TVPCADRW] = 0x00; eieio();
  1052. for (x = 0; x < 12; x++) {
  1053. par->cmap_regs[TVPCDATA] = fgc;
  1054. eieio();
  1055. }
  1056. }
  1057. return 1;
  1058. }
  1059. static void
  1060. imstt_set_cursor(struct imstt_par *par, struct fb_image *d, int on)
  1061. {
  1062. if (par->ramdac == IBM) {
  1063. par->cmap_regs[PIDXHI] = 0; eieio();
  1064. if (!on) {
  1065. par->cmap_regs[PIDXLO] = CURSCTL; eieio();
  1066. par->cmap_regs[PIDXDATA] = 0x00; eieio();
  1067. } else {
  1068. par->cmap_regs[PIDXLO] = CURSXHI; eieio();
  1069. par->cmap_regs[PIDXDATA] = d->dx >> 8; eieio();
  1070. par->cmap_regs[PIDXLO] = CURSXLO; eieio();
  1071. par->cmap_regs[PIDXDATA] = d->dx & 0xff;eieio();
  1072. par->cmap_regs[PIDXLO] = CURSYHI; eieio();
  1073. par->cmap_regs[PIDXDATA] = d->dy >> 8; eieio();
  1074. par->cmap_regs[PIDXLO] = CURSYLO; eieio();
  1075. par->cmap_regs[PIDXDATA] = d->dy & 0xff;eieio();
  1076. par->cmap_regs[PIDXLO] = CURSCTL; eieio();
  1077. par->cmap_regs[PIDXDATA] = 0x02; eieio();
  1078. }
  1079. } else {
  1080. if (!on) {
  1081. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1082. par->cmap_regs[TVPIDATA] = 0x00; eieio();
  1083. } else {
  1084. __u16 x = d->dx + 0x40, y = d->dy + 0x40;
  1085. par->cmap_regs[TVPCXPOH] = x >> 8; eieio();
  1086. par->cmap_regs[TVPCXPOL] = x & 0xff; eieio();
  1087. par->cmap_regs[TVPCYPOH] = y >> 8; eieio();
  1088. par->cmap_regs[TVPCYPOL] = y & 0xff; eieio();
  1089. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1090. par->cmap_regs[TVPIDATA] = 0x02; eieio();
  1091. }
  1092. }
  1093. }
  1094. static int
  1095. imsttfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  1096. {
  1097. struct imstt_par *par = info->par;
  1098. u32 flags = cursor->set, fg, bg, xx, yy;
  1099. if (cursor->dest == NULL && cursor->rop == ROP_XOR)
  1100. return 1;
  1101. imstt_set_cursor(info, cursor, 0);
  1102. if (flags & FB_CUR_SETPOS) {
  1103. xx = cursor->image.dx - info->var.xoffset;
  1104. yy = cursor->image.dy - info->var.yoffset;
  1105. }
  1106. if (flags & FB_CUR_SETSIZE) {
  1107. }
  1108. if (flags & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP)) {
  1109. int fg_idx = cursor->image.fg_color;
  1110. int width = (cursor->image.width+7)/8;
  1111. u8 *dat = (u8 *) cursor->image.data;
  1112. u8 *dst = (u8 *) cursor->dest;
  1113. u8 *msk = (u8 *) cursor->mask;
  1114. switch (cursor->rop) {
  1115. case ROP_XOR:
  1116. for (i = 0; i < cursor->image.height; i++) {
  1117. for (j = 0; j < width; j++) {
  1118. d_idx = i * MAX_CURS/8 + j;
  1119. data[d_idx] = byte_rev[dat[s_idx] ^
  1120. dst[s_idx]];
  1121. mask[d_idx] = byte_rev[msk[s_idx]];
  1122. s_idx++;
  1123. }
  1124. }
  1125. break;
  1126. case ROP_COPY:
  1127. default:
  1128. for (i = 0; i < cursor->image.height; i++) {
  1129. for (j = 0; j < width; j++) {
  1130. d_idx = i * MAX_CURS/8 + j;
  1131. data[d_idx] = byte_rev[dat[s_idx]];
  1132. mask[d_idx] = byte_rev[msk[s_idx]];
  1133. s_idx++;
  1134. }
  1135. }
  1136. break;
  1137. }
  1138. fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
  1139. ((info->cmap.green[fg_idx] & 0xf8) << 2) |
  1140. ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
  1141. imsttfb_load_cursor_image(par, xx, yy, fgc);
  1142. }
  1143. if (cursor->enable)
  1144. imstt_set_cursor(info, cursor, 1);
  1145. return 0;
  1146. }
  1147. #endif
  1148. #define FBIMSTT_SETREG 0x545401
  1149. #define FBIMSTT_GETREG 0x545402
  1150. #define FBIMSTT_SETCMAPREG 0x545403
  1151. #define FBIMSTT_GETCMAPREG 0x545404
  1152. #define FBIMSTT_SETIDXREG 0x545405
  1153. #define FBIMSTT_GETIDXREG 0x545406
  1154. static int
  1155. imsttfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
  1156. {
  1157. struct imstt_par *par = info->par;
  1158. void __user *argp = (void __user *)arg;
  1159. __u32 reg[2];
  1160. __u8 idx[2];
  1161. switch (cmd) {
  1162. case FBIMSTT_SETREG:
  1163. if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
  1164. return -EFAULT;
  1165. write_reg_le32(par->dc_regs, reg[0], reg[1]);
  1166. return 0;
  1167. case FBIMSTT_GETREG:
  1168. if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
  1169. return -EFAULT;
  1170. reg[1] = read_reg_le32(par->dc_regs, reg[0]);
  1171. if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
  1172. return -EFAULT;
  1173. return 0;
  1174. case FBIMSTT_SETCMAPREG:
  1175. if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
  1176. return -EFAULT;
  1177. write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]);
  1178. return 0;
  1179. case FBIMSTT_GETCMAPREG:
  1180. if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
  1181. return -EFAULT;
  1182. reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]);
  1183. if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
  1184. return -EFAULT;
  1185. return 0;
  1186. case FBIMSTT_SETIDXREG:
  1187. if (copy_from_user(idx, argp, 2))
  1188. return -EFAULT;
  1189. par->cmap_regs[PIDXHI] = 0; eieio();
  1190. par->cmap_regs[PIDXLO] = idx[0]; eieio();
  1191. par->cmap_regs[PIDXDATA] = idx[1]; eieio();
  1192. return 0;
  1193. case FBIMSTT_GETIDXREG:
  1194. if (copy_from_user(idx, argp, 1))
  1195. return -EFAULT;
  1196. par->cmap_regs[PIDXHI] = 0; eieio();
  1197. par->cmap_regs[PIDXLO] = idx[0]; eieio();
  1198. idx[1] = par->cmap_regs[PIDXDATA];
  1199. if (copy_to_user((void __user *)(arg + 1), &idx[1], 1))
  1200. return -EFAULT;
  1201. return 0;
  1202. default:
  1203. return -ENOIOCTLCMD;
  1204. }
  1205. }
  1206. static struct pci_device_id imsttfb_pci_tbl[] = {
  1207. { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT128,
  1208. PCI_ANY_ID, PCI_ANY_ID, 0, 0, IBM },
  1209. { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT3D,
  1210. PCI_ANY_ID, PCI_ANY_ID, 0, 0, TVP },
  1211. { 0, }
  1212. };
  1213. MODULE_DEVICE_TABLE(pci, imsttfb_pci_tbl);
  1214. static struct pci_driver imsttfb_pci_driver = {
  1215. .name = "imsttfb",
  1216. .id_table = imsttfb_pci_tbl,
  1217. .probe = imsttfb_probe,
  1218. .remove = imsttfb_remove,
  1219. };
  1220. static struct fb_ops imsttfb_ops = {
  1221. .owner = THIS_MODULE,
  1222. .fb_check_var = imsttfb_check_var,
  1223. .fb_set_par = imsttfb_set_par,
  1224. .fb_setcolreg = imsttfb_setcolreg,
  1225. .fb_pan_display = imsttfb_pan_display,
  1226. .fb_blank = imsttfb_blank,
  1227. .fb_fillrect = imsttfb_fillrect,
  1228. .fb_copyarea = imsttfb_copyarea,
  1229. .fb_imageblit = cfb_imageblit,
  1230. .fb_ioctl = imsttfb_ioctl,
  1231. };
  1232. static void init_imstt(struct fb_info *info)
  1233. {
  1234. struct imstt_par *par = info->par;
  1235. __u32 i, tmp, *ip, *end;
  1236. tmp = read_reg_le32(par->dc_regs, PRC);
  1237. if (par->ramdac == IBM)
  1238. info->fix.smem_len = (tmp & 0x0004) ? 0x400000 : 0x200000;
  1239. else
  1240. info->fix.smem_len = 0x800000;
  1241. ip = (__u32 *)info->screen_base;
  1242. end = (__u32 *)(info->screen_base + info->fix.smem_len);
  1243. while (ip < end)
  1244. *ip++ = 0;
  1245. /* initialize the card */
  1246. tmp = read_reg_le32(par->dc_regs, STGCTL);
  1247. write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1);
  1248. write_reg_le32(par->dc_regs, SSR, 0);
  1249. /* set default values for DAC registers */
  1250. if (par->ramdac == IBM) {
  1251. par->cmap_regs[PPMASK] = 0xff;
  1252. eieio();
  1253. par->cmap_regs[PIDXHI] = 0;
  1254. eieio();
  1255. for (i = 0; i < ARRAY_SIZE(ibm_initregs); i++) {
  1256. par->cmap_regs[PIDXLO] = ibm_initregs[i].addr;
  1257. eieio();
  1258. par->cmap_regs[PIDXDATA] = ibm_initregs[i].value;
  1259. eieio();
  1260. }
  1261. } else {
  1262. for (i = 0; i < ARRAY_SIZE(tvp_initregs); i++) {
  1263. par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;
  1264. eieio();
  1265. par->cmap_regs[TVPIDATA] = tvp_initregs[i].value;
  1266. eieio();
  1267. }
  1268. }
  1269. #if USE_NV_MODES && defined(CONFIG_PPC32)
  1270. {
  1271. int vmode = init_vmode, cmode = init_cmode;
  1272. if (vmode == -1) {
  1273. vmode = nvram_read_byte(NV_VMODE);
  1274. if (vmode <= 0 || vmode > VMODE_MAX)
  1275. vmode = VMODE_640_480_67;
  1276. }
  1277. if (cmode == -1) {
  1278. cmode = nvram_read_byte(NV_CMODE);
  1279. if (cmode < CMODE_8 || cmode > CMODE_32)
  1280. cmode = CMODE_8;
  1281. }
  1282. if (mac_vmode_to_var(vmode, cmode, &info->var)) {
  1283. info->var.xres = info->var.xres_virtual = INIT_XRES;
  1284. info->var.yres = info->var.yres_virtual = INIT_YRES;
  1285. info->var.bits_per_pixel = INIT_BPP;
  1286. }
  1287. }
  1288. #else
  1289. info->var.xres = info->var.xres_virtual = INIT_XRES;
  1290. info->var.yres = info->var.yres_virtual = INIT_YRES;
  1291. info->var.bits_per_pixel = INIT_BPP;
  1292. #endif
  1293. if ((info->var.xres * info->var.yres) * (info->var.bits_per_pixel >> 3) > info->fix.smem_len
  1294. || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) {
  1295. printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
  1296. framebuffer_release(info);
  1297. return;
  1298. }
  1299. sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP");
  1300. info->fix.mmio_len = 0x1000;
  1301. info->fix.accel = FB_ACCEL_IMS_TWINTURBO;
  1302. info->fix.type = FB_TYPE_PACKED_PIXELS;
  1303. info->fix.visual = info->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
  1304. : FB_VISUAL_DIRECTCOLOR;
  1305. info->fix.line_length = info->var.xres * (info->var.bits_per_pixel >> 3);
  1306. info->fix.xpanstep = 8;
  1307. info->fix.ypanstep = 1;
  1308. info->fix.ywrapstep = 0;
  1309. info->var.accel_flags = FB_ACCELF_TEXT;
  1310. // if (par->ramdac == IBM)
  1311. // imstt_cursor_init(info);
  1312. if (info->var.green.length == 6)
  1313. set_565(par);
  1314. else
  1315. set_555(par);
  1316. set_imstt_regvals(info, info->var.bits_per_pixel);
  1317. info->var.pixclock = 1000000 / getclkMHz(par);
  1318. info->fbops = &imsttfb_ops;
  1319. info->flags = FBINFO_DEFAULT |
  1320. FBINFO_HWACCEL_COPYAREA |
  1321. FBINFO_HWACCEL_FILLRECT |
  1322. FBINFO_HWACCEL_YPAN;
  1323. fb_alloc_cmap(&info->cmap, 0, 0);
  1324. if (register_framebuffer(info) < 0) {
  1325. framebuffer_release(info);
  1326. return;
  1327. }
  1328. tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8;
  1329. fb_info(info, "%s frame buffer; %uMB vram; chip version %u\n",
  1330. info->fix.id, info->fix.smem_len >> 20, tmp);
  1331. }
  1332. static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1333. {
  1334. unsigned long addr, size;
  1335. struct imstt_par *par;
  1336. struct fb_info *info;
  1337. struct device_node *dp;
  1338. dp = pci_device_to_OF_node(pdev);
  1339. if(dp)
  1340. printk(KERN_INFO "%s: OF name %s\n",__func__, dp->name);
  1341. else if (IS_ENABLED(CONFIG_OF))
  1342. printk(KERN_ERR "imsttfb: no OF node for pci device\n");
  1343. info = framebuffer_alloc(sizeof(struct imstt_par), &pdev->dev);
  1344. if (!info) {
  1345. printk(KERN_ERR "imsttfb: Can't allocate memory\n");
  1346. return -ENOMEM;
  1347. }
  1348. par = info->par;
  1349. addr = pci_resource_start (pdev, 0);
  1350. size = pci_resource_len (pdev, 0);
  1351. if (!request_mem_region(addr, size, "imsttfb")) {
  1352. printk(KERN_ERR "imsttfb: Can't reserve memory region\n");
  1353. framebuffer_release(info);
  1354. return -ENODEV;
  1355. }
  1356. switch (pdev->device) {
  1357. case PCI_DEVICE_ID_IMS_TT128: /* IMS,tt128mbA */
  1358. par->ramdac = IBM;
  1359. if (dp && ((strcmp(dp->name, "IMS,tt128mb8") == 0) ||
  1360. (strcmp(dp->name, "IMS,tt128mb8A") == 0)))
  1361. par->ramdac = TVP;
  1362. break;
  1363. case PCI_DEVICE_ID_IMS_TT3D: /* IMS,tt3d */
  1364. par->ramdac = TVP;
  1365. break;
  1366. default:
  1367. printk(KERN_INFO "imsttfb: Device 0x%x unknown, "
  1368. "contact maintainer.\n", pdev->device);
  1369. release_mem_region(addr, size);
  1370. framebuffer_release(info);
  1371. return -ENODEV;
  1372. }
  1373. info->fix.smem_start = addr;
  1374. info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ?
  1375. 0x400000 : 0x800000);
  1376. info->fix.mmio_start = addr + 0x800000;
  1377. par->dc_regs = ioremap(addr + 0x800000, 0x1000);
  1378. par->cmap_regs_phys = addr + 0x840000;
  1379. par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
  1380. info->pseudo_palette = par->palette;
  1381. init_imstt(info);
  1382. pci_set_drvdata(pdev, info);
  1383. return 0;
  1384. }
  1385. static void imsttfb_remove(struct pci_dev *pdev)
  1386. {
  1387. struct fb_info *info = pci_get_drvdata(pdev);
  1388. struct imstt_par *par = info->par;
  1389. int size = pci_resource_len(pdev, 0);
  1390. unregister_framebuffer(info);
  1391. iounmap(par->cmap_regs);
  1392. iounmap(par->dc_regs);
  1393. iounmap(info->screen_base);
  1394. release_mem_region(info->fix.smem_start, size);
  1395. framebuffer_release(info);
  1396. }
  1397. #ifndef MODULE
  1398. static int __init
  1399. imsttfb_setup(char *options)
  1400. {
  1401. char *this_opt;
  1402. if (!options || !*options)
  1403. return 0;
  1404. while ((this_opt = strsep(&options, ",")) != NULL) {
  1405. if (!strncmp(this_opt, "font:", 5)) {
  1406. char *p;
  1407. int i;
  1408. p = this_opt + 5;
  1409. for (i = 0; i < sizeof(fontname) - 1; i++)
  1410. if (!*p || *p == ' ' || *p == ',')
  1411. break;
  1412. memcpy(fontname, this_opt + 5, i);
  1413. fontname[i] = 0;
  1414. } else if (!strncmp(this_opt, "inverse", 7)) {
  1415. inverse = 1;
  1416. fb_invert_cmaps();
  1417. }
  1418. #if defined(CONFIG_PPC)
  1419. else if (!strncmp(this_opt, "vmode:", 6)) {
  1420. int vmode = simple_strtoul(this_opt+6, NULL, 0);
  1421. if (vmode > 0 && vmode <= VMODE_MAX)
  1422. init_vmode = vmode;
  1423. } else if (!strncmp(this_opt, "cmode:", 6)) {
  1424. int cmode = simple_strtoul(this_opt+6, NULL, 0);
  1425. switch (cmode) {
  1426. case CMODE_8:
  1427. case 8:
  1428. init_cmode = CMODE_8;
  1429. break;
  1430. case CMODE_16:
  1431. case 15:
  1432. case 16:
  1433. init_cmode = CMODE_16;
  1434. break;
  1435. case CMODE_32:
  1436. case 24:
  1437. case 32:
  1438. init_cmode = CMODE_32;
  1439. break;
  1440. }
  1441. }
  1442. #endif
  1443. }
  1444. return 0;
  1445. }
  1446. #endif /* MODULE */
  1447. static int __init imsttfb_init(void)
  1448. {
  1449. #ifndef MODULE
  1450. char *option = NULL;
  1451. if (fb_get_options("imsttfb", &option))
  1452. return -ENODEV;
  1453. imsttfb_setup(option);
  1454. #endif
  1455. return pci_register_driver(&imsttfb_pci_driver);
  1456. }
  1457. static void __exit imsttfb_exit(void)
  1458. {
  1459. pci_unregister_driver(&imsttfb_pci_driver);
  1460. }
  1461. MODULE_LICENSE("GPL");
  1462. module_init(imsttfb_init);
  1463. module_exit(imsttfb_exit);