dwc3-pci.c 8.3 KB

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  1. /**
  2. * dwc3-pci.c - PCI Specific glue layer
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * This program is free software: you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 of
  11. * the License as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/slab.h>
  21. #include <linux/pci.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/acpi.h>
  26. #include <linux/delay.h>
  27. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
  28. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
  29. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
  30. #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
  31. #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
  32. #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
  33. #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
  34. #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
  35. #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
  36. #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
  37. #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
  38. #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
  39. #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
  40. static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  41. static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  42. static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  43. { "reset-gpios", &reset_gpios, 1 },
  44. { "cs-gpios", &cs_gpios, 1 },
  45. { },
  46. };
  47. static int dwc3_pci_quirks(struct pci_dev *pdev, struct platform_device *dwc3)
  48. {
  49. int ret;
  50. struct property_entry sysdev_property[] = {
  51. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  52. { },
  53. };
  54. ret = platform_device_add_properties(dwc3, sysdev_property);
  55. if (ret)
  56. return ret;
  57. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  58. pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
  59. struct property_entry properties[] = {
  60. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  61. PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
  62. PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
  63. PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
  64. PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
  65. PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
  66. PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
  67. PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
  68. PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
  69. PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
  70. PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
  71. /*
  72. * FIXME these quirks should be removed when AMD NL
  73. * tapes out
  74. */
  75. PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
  76. PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
  77. PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
  78. { },
  79. };
  80. return platform_device_add_properties(dwc3, properties);
  81. }
  82. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  83. int ret;
  84. struct property_entry properties[] = {
  85. PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
  86. { }
  87. };
  88. ret = platform_device_add_properties(dwc3, properties);
  89. if (ret < 0)
  90. return ret;
  91. if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
  92. struct gpio_desc *gpio;
  93. acpi_dev_add_driver_gpios(ACPI_COMPANION(&pdev->dev),
  94. acpi_dwc3_byt_gpios);
  95. /*
  96. * These GPIOs will turn on the USB2 PHY. Note that we have to
  97. * put the gpio descriptors again here because the phy driver
  98. * might want to grab them, too.
  99. */
  100. gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
  101. if (IS_ERR(gpio))
  102. return PTR_ERR(gpio);
  103. gpiod_set_value_cansleep(gpio, 1);
  104. gpiod_put(gpio);
  105. gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
  106. if (IS_ERR(gpio))
  107. return PTR_ERR(gpio);
  108. if (gpio) {
  109. gpiod_set_value_cansleep(gpio, 1);
  110. gpiod_put(gpio);
  111. usleep_range(10000, 11000);
  112. }
  113. }
  114. }
  115. if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
  116. (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
  117. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
  118. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
  119. struct property_entry properties[] = {
  120. PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
  121. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  122. PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
  123. { },
  124. };
  125. return platform_device_add_properties(dwc3, properties);
  126. }
  127. return 0;
  128. }
  129. static int dwc3_pci_probe(struct pci_dev *pci,
  130. const struct pci_device_id *id)
  131. {
  132. struct resource res[2];
  133. struct platform_device *dwc3;
  134. int ret;
  135. struct device *dev = &pci->dev;
  136. ret = pcim_enable_device(pci);
  137. if (ret) {
  138. dev_err(dev, "failed to enable pci device\n");
  139. return -ENODEV;
  140. }
  141. pci_set_master(pci);
  142. dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
  143. if (!dwc3) {
  144. dev_err(dev, "couldn't allocate dwc3 device\n");
  145. return -ENOMEM;
  146. }
  147. memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
  148. res[0].start = pci_resource_start(pci, 0);
  149. res[0].end = pci_resource_end(pci, 0);
  150. res[0].name = "dwc_usb3";
  151. res[0].flags = IORESOURCE_MEM;
  152. res[1].start = pci->irq;
  153. res[1].name = "dwc_usb3";
  154. res[1].flags = IORESOURCE_IRQ;
  155. ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
  156. if (ret) {
  157. dev_err(dev, "couldn't add resources to dwc3 device\n");
  158. return ret;
  159. }
  160. dwc3->dev.parent = dev;
  161. ACPI_COMPANION_SET(&dwc3->dev, ACPI_COMPANION(dev));
  162. ret = dwc3_pci_quirks(pci, dwc3);
  163. if (ret)
  164. goto err;
  165. ret = platform_device_add(dwc3);
  166. if (ret) {
  167. dev_err(dev, "failed to register dwc3 device\n");
  168. goto err;
  169. }
  170. device_init_wakeup(dev, true);
  171. device_set_run_wake(dev, true);
  172. pci_set_drvdata(pci, dwc3);
  173. pm_runtime_put(dev);
  174. return 0;
  175. err:
  176. platform_device_put(dwc3);
  177. return ret;
  178. }
  179. static void dwc3_pci_remove(struct pci_dev *pci)
  180. {
  181. device_init_wakeup(&pci->dev, false);
  182. pm_runtime_get(&pci->dev);
  183. acpi_dev_remove_driver_gpios(ACPI_COMPANION(&pci->dev));
  184. platform_device_unregister(pci_get_drvdata(pci));
  185. }
  186. static const struct pci_device_id dwc3_pci_id_table[] = {
  187. {
  188. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  189. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
  190. },
  191. {
  192. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  193. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
  194. },
  195. {
  196. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  197. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
  198. },
  199. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
  200. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
  201. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
  202. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
  203. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
  204. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
  205. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
  206. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
  207. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), },
  208. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK), },
  209. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
  210. { } /* Terminating Entry */
  211. };
  212. MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
  213. #ifdef CONFIG_PM
  214. static int dwc3_pci_runtime_suspend(struct device *dev)
  215. {
  216. if (device_run_wake(dev))
  217. return 0;
  218. return -EBUSY;
  219. }
  220. static int dwc3_pci_runtime_resume(struct device *dev)
  221. {
  222. struct platform_device *dwc3 = dev_get_drvdata(dev);
  223. return pm_runtime_get(&dwc3->dev);
  224. }
  225. #endif /* CONFIG_PM */
  226. #ifdef CONFIG_PM_SLEEP
  227. static int dwc3_pci_pm_dummy(struct device *dev)
  228. {
  229. /*
  230. * There's nothing to do here. No, seriously. Everything is either taken
  231. * care either by PCI subsystem or dwc3/core.c, so we have nothing
  232. * missing here.
  233. *
  234. * So you'd think we didn't need this at all, but PCI subsystem will
  235. * bail out if we don't have a valid callback :-s
  236. */
  237. return 0;
  238. }
  239. #endif /* CONFIG_PM_SLEEP */
  240. static struct dev_pm_ops dwc3_pci_dev_pm_ops = {
  241. SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_pm_dummy, dwc3_pci_pm_dummy)
  242. SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
  243. NULL)
  244. };
  245. static struct pci_driver dwc3_pci_driver = {
  246. .name = "dwc3-pci",
  247. .id_table = dwc3_pci_id_table,
  248. .probe = dwc3_pci_probe,
  249. .remove = dwc3_pci_remove,
  250. .driver = {
  251. .pm = &dwc3_pci_dev_pm_ops,
  252. }
  253. };
  254. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  255. MODULE_LICENSE("GPL v2");
  256. MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
  257. module_pci_driver(dwc3_pci_driver);