pm33xx.c 12 KB

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  1. /*
  2. * AM33XX Power Management Routines
  3. *
  4. * Copyright (C) 2012-2016 Texas Instruments Incorporated - http://www.ti.com/
  5. * Vaibhav Bedia, Dave Gerlach
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/err.h>
  18. #include <linux/genalloc.h>
  19. #include <linux/kernel.h>
  20. #include <linux/init.h>
  21. #include <linux/io.h>
  22. #include <linux/module.h>
  23. #include <linux/of.h>
  24. #include <linux/platform_data/pm33xx.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/rtc.h>
  27. #include <linux/sizes.h>
  28. #include <linux/sram.h>
  29. #include <linux/suspend.h>
  30. #include <linux/ti-emif-sram.h>
  31. #include <linux/wkup_m3_ipc.h>
  32. #include <asm/fncpy.h>
  33. #include <asm/proc-fns.h>
  34. #include <asm/suspend.h>
  35. #include <asm/system_misc.h>
  36. #define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
  37. (unsigned long)pm_sram->do_wfi)
  38. #define RTC_SCRATCH_RESUME_REG 0
  39. #define RTC_SCRATCH_MAGIC_REG 1
  40. #define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */
  41. #define GIC_INT_SET_PENDING_BASE 0x200
  42. #define AM43XX_GIC_DIST_BASE 0x48241000
  43. static u32 rtc_magic_val;
  44. static int (*am33xx_do_wfi_sram)(unsigned long unused);
  45. static phys_addr_t am33xx_do_wfi_sram_phys;
  46. static struct gen_pool *sram_pool, *sram_pool_data;
  47. static phys_addr_t ocmcram_location, ocmcram_location_data;
  48. static struct rtc_device *omap_rtc;
  49. static void __iomem *gic_dist_base;
  50. static struct am33xx_pm_platform_data *pm_ops;
  51. static struct am33xx_pm_sram_addr *pm_sram;
  52. static struct wkup_m3_ipc *m3_ipc;
  53. #ifdef CONFIG_SUSPEND
  54. static int rtc_only_idle;
  55. static int retrigger_irq;
  56. static unsigned long suspend_wfi_flags;
  57. static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
  58. .src = "Unknown",
  59. };
  60. static struct wkup_m3_wakeup_src rtc_alarm_wakeup = {
  61. .irq_nr = 108, .src = "RTC Alarm",
  62. };
  63. static struct wkup_m3_wakeup_src rtc_ext_wakeup = {
  64. .irq_nr = 0, .src = "Ext wakeup",
  65. };
  66. #endif /* CONFIG_SUSPEND */
  67. static u32 sram_suspend_address(unsigned long addr)
  68. {
  69. return ((unsigned long)am33xx_do_wfi_sram +
  70. AMX3_PM_SRAM_SYMBOL_OFFSET(addr));
  71. }
  72. /*
  73. * Push the minimal suspend-resume code to SRAM
  74. */
  75. static int am33xx_prepare_push_sram_idle(void)
  76. {
  77. struct device_node *np;
  78. np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
  79. if (!np) {
  80. np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
  81. if (!np) {
  82. pr_warn("PM: %s: Unable to find device node for mpu\n",
  83. __func__);
  84. return -ENODEV;
  85. }
  86. }
  87. sram_pool = of_gen_pool_get(np, "pm-sram", 0);
  88. if (!sram_pool) {
  89. pr_warn("PM: %s: Unable to get sram pool for ocmcram\n",
  90. __func__);
  91. return -ENODEV;
  92. }
  93. sram_pool_data = of_gen_pool_get(np, "pm-sram", 1);
  94. if (!sram_pool_data) {
  95. pr_warn("PM: %s: Unable to get sram data pool for ocmcram\n",
  96. __func__);
  97. return -ENODEV;
  98. }
  99. ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz);
  100. if (!ocmcram_location) {
  101. pr_warn("PM: %s: Unable to allocate memory from ocmcram\n",
  102. __func__);
  103. return -ENOMEM;
  104. }
  105. ocmcram_location_data = gen_pool_alloc(sram_pool_data,
  106. sizeof(struct emif_regs_amx3));
  107. if (!ocmcram_location_data) {
  108. pr_err("PM: Unable to allocate memory from ocmcram\n");
  109. gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
  110. return -ENOMEM;
  111. }
  112. return 0;
  113. }
  114. static int am33xx_push_sram_idle(void)
  115. {
  116. struct am33xx_pm_ro_sram_data ro_sram_data;
  117. int ret;
  118. ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
  119. ro_sram_data.amx3_pm_sram_data_phys =
  120. gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
  121. ro_sram_data.rtc_base_virt = pm_ops->get_rtc_base_addr();
  122. /* Save physical address to calculate resume offset during pm init */
  123. am33xx_do_wfi_sram = (void *)ocmcram_location;
  124. am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
  125. ocmcram_location);
  126. ret = sram_exec_copy(sram_pool, am33xx_do_wfi_sram, pm_sram->do_wfi,
  127. *pm_sram->do_wfi_sz);
  128. if (ret) {
  129. pr_err("PM: %s: am33xx_do_wfi copy to sram failed\n", __func__);
  130. return ret;
  131. }
  132. ret = ti_emif_copy_pm_function_table(sram_pool,
  133. (void *)sram_suspend_address((unsigned long)pm_sram->emif_sram_table));
  134. if (ret) {
  135. pr_warn("PM: %s: EMIF function copy failed\n", __func__);
  136. ret = -EPROBE_DEFER;
  137. return ret;
  138. }
  139. ret = sram_exec_copy(sram_pool,
  140. (void *)sram_suspend_address((unsigned long)pm_sram->ro_sram_data),
  141. &ro_sram_data,
  142. sizeof(ro_sram_data));
  143. if (ret) {
  144. pr_err("PM: %s: ro_sram_data copy to sram failed\n", __func__);
  145. return ret;
  146. }
  147. return 0;
  148. }
  149. static int am33xx_do_sram_idle(u32 wfi_flags)
  150. {
  151. int ret = 0;
  152. if (!m3_ipc || !pm_ops)
  153. return 0;
  154. if (wfi_flags & WFI_FLAG_WAKE_M3)
  155. ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE);
  156. return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags);
  157. }
  158. static int __init am43xx_map_gic(void)
  159. {
  160. gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
  161. if (!gic_dist_base)
  162. return -ENOMEM;
  163. return 0;
  164. }
  165. #ifdef CONFIG_SUSPEND
  166. struct wkup_m3_wakeup_src rtc_wake_src(void)
  167. {
  168. u32 i;
  169. i = __raw_readl(pm_ops->get_rtc_base_addr() + 0x44) & 0x40;
  170. if (i) {
  171. retrigger_irq = rtc_alarm_wakeup.irq_nr;
  172. return rtc_alarm_wakeup;
  173. }
  174. retrigger_irq = rtc_ext_wakeup.irq_nr;
  175. return rtc_ext_wakeup;
  176. }
  177. int am33xx_rtc_only_idle(unsigned long wfi_flags)
  178. {
  179. rtc_power_off_program(omap_rtc);
  180. am33xx_do_wfi_sram(wfi_flags);
  181. return 0;
  182. }
  183. static int am33xx_pm_suspend(suspend_state_t suspend_state)
  184. {
  185. int i, ret = 0;
  186. if (suspend_state == PM_SUSPEND_MEM &&
  187. pm_ops->check_off_mode_enable()) {
  188. pm_ops->prepare_rtc_suspend();
  189. pm_ops->save_context();
  190. suspend_wfi_flags |= WFI_FLAG_RTC_ONLY;
  191. ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle,
  192. suspend_wfi_flags);
  193. suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
  194. if (!ret) {
  195. pm_ops->restore_context();
  196. m3_ipc->ops->set_rtc_only(m3_ipc);
  197. am33xx_push_sram_idle();
  198. }
  199. } else {
  200. ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram,
  201. suspend_wfi_flags);
  202. }
  203. if (ret) {
  204. pr_err("PM: Kernel suspend failure\n");
  205. } else {
  206. i = m3_ipc->ops->request_pm_status(m3_ipc);
  207. switch (i) {
  208. case 0:
  209. pr_info("PM: Successfully put all powerdomains to target state\n");
  210. break;
  211. case 1:
  212. pr_err("PM: Could not transition all powerdomains to target state\n");
  213. ret = -1;
  214. break;
  215. default:
  216. pr_err("PM: CM3 returned unknown result = %d\n", i);
  217. ret = -1;
  218. }
  219. /* print the wakeup reason */
  220. if (rtc_only_idle) {
  221. wakeup_src = rtc_wake_src();
  222. pr_info("PM: Wakeup source %s\n", wakeup_src.src);
  223. } else {
  224. pr_info("PM: Wakeup source %s\n",
  225. m3_ipc->ops->request_wake_src(m3_ipc));
  226. }
  227. }
  228. if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
  229. pm_ops->prepare_rtc_resume();
  230. return ret;
  231. }
  232. static int am33xx_pm_enter(suspend_state_t suspend_state)
  233. {
  234. int ret = 0;
  235. switch (suspend_state) {
  236. case PM_SUSPEND_MEM:
  237. case PM_SUSPEND_STANDBY:
  238. ret = am33xx_pm_suspend(suspend_state);
  239. break;
  240. default:
  241. ret = -EINVAL;
  242. }
  243. return ret;
  244. }
  245. static int am33xx_pm_begin(suspend_state_t state)
  246. {
  247. int ret = -EINVAL;
  248. if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) {
  249. rtc_write_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG,
  250. rtc_magic_val);
  251. rtc_only_idle = 1;
  252. } else {
  253. rtc_only_idle = 0;
  254. }
  255. cpu_idle_poll_ctrl(true);
  256. switch (state) {
  257. case PM_SUSPEND_MEM:
  258. ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP);
  259. break;
  260. case PM_SUSPEND_STANDBY:
  261. ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY);
  262. break;
  263. }
  264. return ret;
  265. }
  266. static void am33xx_pm_end(void)
  267. {
  268. m3_ipc->ops->finish_low_power(m3_ipc);
  269. if (rtc_only_idle) {
  270. if (retrigger_irq)
  271. /*
  272. * 32 bits of Interrupt Set-Pending correspond to 32
  273. * 32 interupts. Compute the bit offset of the
  274. * Interrupt and set that particular bit.
  275. * Compute the register offset by dividing interrupt
  276. * number by 32 and mutiplying by 4
  277. */
  278. writel_relaxed(1 << (retrigger_irq & 31),
  279. gic_dist_base + GIC_INT_SET_PENDING_BASE
  280. + retrigger_irq / 32 * 4);
  281. rtc_write_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG, 0);
  282. }
  283. rtc_only_idle = 0;
  284. cpu_idle_poll_ctrl(false);
  285. }
  286. static int am33xx_pm_valid(suspend_state_t state)
  287. {
  288. switch (state) {
  289. case PM_SUSPEND_STANDBY:
  290. case PM_SUSPEND_MEM:
  291. return 1;
  292. default:
  293. return 0;
  294. }
  295. }
  296. static const struct platform_suspend_ops am33xx_pm_ops = {
  297. .begin = am33xx_pm_begin,
  298. .end = am33xx_pm_end,
  299. .enter = am33xx_pm_enter,
  300. .valid = am33xx_pm_valid,
  301. };
  302. #endif /* CONFIG_SUSPEND */
  303. static void am33xx_pm_set_ipc_ops(void)
  304. {
  305. void *resume_address;
  306. int temp;
  307. temp = ti_emif_get_mem_type();
  308. if (temp < 0) {
  309. pr_err("PM: Cannot determine memory type, no PM available\n");
  310. return;
  311. }
  312. m3_ipc->ops->set_mem_type(m3_ipc, temp);
  313. /* Physical resume address to be used by ROM code */
  314. resume_address = (void *)am33xx_do_wfi_sram_phys +
  315. *pm_sram->resume_offset + 0x4;
  316. m3_ipc->ops->set_resume_address(m3_ipc, resume_address);
  317. }
  318. static void am33xx_pm_free_sram(void)
  319. {
  320. gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
  321. gen_pool_free(sram_pool_data, ocmcram_location_data,
  322. sizeof(struct am33xx_pm_ro_sram_data));
  323. }
  324. static int am33xx_pm_rtc_setup(void)
  325. {
  326. struct device_node *np;
  327. np = of_find_node_by_name(NULL, "rtc");
  328. if (of_device_is_available(np)) {
  329. omap_rtc = rtc_class_open("rtc0");
  330. if (!omap_rtc) {
  331. pr_warn("PM: rtc0 not available");
  332. return -EPROBE_DEFER;
  333. }
  334. rtc_read_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG,
  335. &rtc_magic_val);
  336. if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
  337. pr_warn("PM: bootloader does not support rtc-only!\n");
  338. rtc_write_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG, 0);
  339. rtc_write_scratch(omap_rtc, RTC_SCRATCH_RESUME_REG,
  340. pm_sram->resume_address);
  341. } else {
  342. pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
  343. }
  344. return 0;
  345. }
  346. static int am33xx_pm_probe(struct platform_device *pdev)
  347. {
  348. struct device *dev = &pdev->dev;
  349. int ret;
  350. if (!of_machine_is_compatible("ti,am33xx") &&
  351. !of_machine_is_compatible("ti,am43"))
  352. return -ENODEV;
  353. pm_ops = dev->platform_data;
  354. if (!pm_ops) {
  355. pr_err("PM: Cannot get core PM ops!\n");
  356. return -ENODEV;
  357. }
  358. ret = am43xx_map_gic();
  359. if (ret) {
  360. pr_err("PM: Could not ioremap GIC base\n");
  361. return ret;
  362. }
  363. pm_sram = pm_ops->get_sram_addrs();
  364. if (!pm_sram) {
  365. pr_err("PM: Cannot get PM asm function addresses!!\n");
  366. return -ENODEV;
  367. }
  368. m3_ipc = wkup_m3_ipc_get();
  369. if (!m3_ipc) {
  370. pr_err("PM: Cannot get wkup_m3_ipc handle\n");
  371. return -EPROBE_DEFER;
  372. }
  373. ret = am33xx_prepare_push_sram_idle();
  374. if (ret)
  375. return ret;
  376. ret = am33xx_pm_rtc_setup();
  377. if (ret)
  378. goto err_free_sram;
  379. am33xx_push_sram_idle();
  380. if (ret)
  381. goto err_free_sram;
  382. am33xx_pm_set_ipc_ops();
  383. #ifdef CONFIG_SUSPEND
  384. suspend_set_ops(&am33xx_pm_ops);
  385. /*
  386. * For a system suspend we must flush the caches, we want
  387. * the DDR in self-refresh, we want to save the context
  388. * of the EMIF, and we want the wkup_m3 to handle low-power
  389. * transition.
  390. */
  391. suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE;
  392. suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
  393. suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
  394. suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
  395. #endif /* CONFIG_SUSPEND */
  396. ret = pm_ops->init(am33xx_do_sram_idle);
  397. if (ret) {
  398. pr_err("Unable to call core pm init!\n");
  399. ret = -ENODEV;
  400. goto err_put_wkup_m3_ipc;
  401. }
  402. return 0;
  403. err_put_wkup_m3_ipc:
  404. wkup_m3_ipc_put(m3_ipc);
  405. err_free_sram:
  406. am33xx_pm_free_sram();
  407. return ret;
  408. }
  409. static int am33xx_pm_remove(struct platform_device *pdev)
  410. {
  411. if (pm_ops->deinit)
  412. pm_ops->deinit();
  413. suspend_set_ops(NULL);
  414. wkup_m3_ipc_put(m3_ipc);
  415. am33xx_pm_free_sram();
  416. return 0;
  417. }
  418. static struct platform_driver am33xx_pm_driver = {
  419. .driver = {
  420. .name = "pm33xx",
  421. },
  422. .probe = am33xx_pm_probe,
  423. .remove = am33xx_pm_remove,
  424. };
  425. module_platform_driver(am33xx_pm_driver);
  426. MODULE_ALIAS("platform:pm33xx");
  427. MODULE_LICENSE("GPL v2");
  428. MODULE_DESCRIPTION("am33xx power management driver");