ufshcd.c 175 KB

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  1. /*
  2. * Universal Flash Storage Host controller driver Core
  3. *
  4. * This code is based on drivers/scsi/ufs/ufshcd.c
  5. * Copyright (C) 2011-2013 Samsung India Software Operations
  6. * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
  7. *
  8. * Authors:
  9. * Santosh Yaraganavi <santosh.sy@samsung.com>
  10. * Vinayak Holikatti <h.vinayak@samsung.com>
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; either version 2
  15. * of the License, or (at your option) any later version.
  16. * See the COPYING file in the top-level directory or visit
  17. * <http://www.gnu.org/licenses/gpl-2.0.html>
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * This program is provided "AS IS" and "WITH ALL FAULTS" and
  25. * without warranty of any kind. You are solely responsible for
  26. * determining the appropriateness of using and distributing
  27. * the program and assume all risks associated with your exercise
  28. * of rights with respect to the program, including but not limited
  29. * to infringement of third party rights, the risks and costs of
  30. * program errors, damage to or loss of data, programs or equipment,
  31. * and unavailability or interruption of operations. Under no
  32. * circumstances will the contributor of this Program be liable for
  33. * any damages of any kind arising from your use or distribution of
  34. * this program.
  35. *
  36. * The Linux Foundation chooses to take subject only to the GPLv2
  37. * license terms, and distributes only under these terms.
  38. */
  39. #include <linux/async.h>
  40. #include <linux/devfreq.h>
  41. #include <linux/nls.h>
  42. #include <linux/of.h>
  43. #include "ufshcd.h"
  44. #include "ufs_quirks.h"
  45. #include "unipro.h"
  46. #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
  47. UTP_TASK_REQ_COMPL |\
  48. UFSHCD_ERROR_MASK)
  49. /* UIC command timeout, unit: ms */
  50. #define UIC_CMD_TIMEOUT 500
  51. /* NOP OUT retries waiting for NOP IN response */
  52. #define NOP_OUT_RETRIES 10
  53. /* Timeout after 30 msecs if NOP OUT hangs without response */
  54. #define NOP_OUT_TIMEOUT 30 /* msecs */
  55. /* Query request retries */
  56. #define QUERY_REQ_RETRIES 10
  57. /* Query request timeout */
  58. #define QUERY_REQ_TIMEOUT 30 /* msec */
  59. /*
  60. * Query request timeout for fDeviceInit flag
  61. * fDeviceInit query response time for some devices is too large that default
  62. * QUERY_REQ_TIMEOUT may not be enough for such devices.
  63. */
  64. #define QUERY_FDEVICEINIT_REQ_TIMEOUT 600 /* msec */
  65. /* Task management command timeout */
  66. #define TM_CMD_TIMEOUT 100 /* msecs */
  67. /* maximum number of retries for a general UIC command */
  68. #define UFS_UIC_COMMAND_RETRIES 3
  69. /* maximum number of link-startup retries */
  70. #define DME_LINKSTARTUP_RETRIES 3
  71. /* Maximum retries for Hibern8 enter */
  72. #define UIC_HIBERN8_ENTER_RETRIES 3
  73. /* maximum number of reset retries before giving up */
  74. #define MAX_HOST_RESET_RETRIES 5
  75. /* Expose the flag value from utp_upiu_query.value */
  76. #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  77. /* Interrupt aggregation default timeout, unit: 40us */
  78. #define INT_AGGR_DEF_TO 0x02
  79. #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
  80. ({ \
  81. int _ret; \
  82. if (_on) \
  83. _ret = ufshcd_enable_vreg(_dev, _vreg); \
  84. else \
  85. _ret = ufshcd_disable_vreg(_dev, _vreg); \
  86. _ret; \
  87. })
  88. static u32 ufs_query_desc_max_size[] = {
  89. QUERY_DESC_DEVICE_MAX_SIZE,
  90. QUERY_DESC_CONFIGURAION_MAX_SIZE,
  91. QUERY_DESC_UNIT_MAX_SIZE,
  92. QUERY_DESC_RFU_MAX_SIZE,
  93. QUERY_DESC_INTERCONNECT_MAX_SIZE,
  94. QUERY_DESC_STRING_MAX_SIZE,
  95. QUERY_DESC_RFU_MAX_SIZE,
  96. QUERY_DESC_GEOMETRY_MAX_SIZE,
  97. QUERY_DESC_POWER_MAX_SIZE,
  98. QUERY_DESC_RFU_MAX_SIZE,
  99. };
  100. enum {
  101. UFSHCD_MAX_CHANNEL = 0,
  102. UFSHCD_MAX_ID = 1,
  103. UFSHCD_CMD_PER_LUN = 32,
  104. UFSHCD_CAN_QUEUE = 32,
  105. };
  106. /* UFSHCD states */
  107. enum {
  108. UFSHCD_STATE_RESET,
  109. UFSHCD_STATE_ERROR,
  110. UFSHCD_STATE_OPERATIONAL,
  111. UFSHCD_STATE_EH_SCHEDULED,
  112. };
  113. /* UFSHCD error handling flags */
  114. enum {
  115. UFSHCD_EH_IN_PROGRESS = (1 << 0),
  116. };
  117. /* UFSHCD UIC layer error flags */
  118. enum {
  119. UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
  120. UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
  121. UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
  122. UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
  123. UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
  124. UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
  125. };
  126. /* Interrupt configuration options */
  127. enum {
  128. UFSHCD_INT_DISABLE,
  129. UFSHCD_INT_ENABLE,
  130. UFSHCD_INT_CLEAR,
  131. };
  132. #define ufshcd_set_eh_in_progress(h) \
  133. (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
  134. #define ufshcd_eh_in_progress(h) \
  135. (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
  136. #define ufshcd_clear_eh_in_progress(h) \
  137. (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
  138. #define ufshcd_set_ufs_dev_active(h) \
  139. ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
  140. #define ufshcd_set_ufs_dev_sleep(h) \
  141. ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
  142. #define ufshcd_set_ufs_dev_poweroff(h) \
  143. ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
  144. #define ufshcd_is_ufs_dev_active(h) \
  145. ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
  146. #define ufshcd_is_ufs_dev_sleep(h) \
  147. ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
  148. #define ufshcd_is_ufs_dev_poweroff(h) \
  149. ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
  150. static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
  151. {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  152. {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  153. {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  154. {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  155. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  156. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
  157. };
  158. static inline enum ufs_dev_pwr_mode
  159. ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
  160. {
  161. return ufs_pm_lvl_states[lvl].dev_state;
  162. }
  163. static inline enum uic_link_state
  164. ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
  165. {
  166. return ufs_pm_lvl_states[lvl].link_state;
  167. }
  168. static struct ufs_dev_fix ufs_fixups[] = {
  169. /* UFS cards deviations table */
  170. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  171. UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
  172. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
  173. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  174. UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
  175. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  176. UFS_DEVICE_NO_FASTAUTO),
  177. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  178. UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
  179. UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
  180. UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
  181. UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
  182. UFS_DEVICE_QUIRK_PA_TACTIVATE),
  183. UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
  184. UFS_DEVICE_QUIRK_PA_TACTIVATE),
  185. UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
  186. UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
  187. UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
  188. END_FIX
  189. };
  190. static void ufshcd_tmc_handler(struct ufs_hba *hba);
  191. static void ufshcd_async_scan(void *data, async_cookie_t cookie);
  192. static int ufshcd_reset_and_restore(struct ufs_hba *hba);
  193. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
  194. static void ufshcd_hba_exit(struct ufs_hba *hba);
  195. static int ufshcd_probe_hba(struct ufs_hba *hba);
  196. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  197. bool skip_ref_clk);
  198. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
  199. static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
  200. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
  201. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
  202. static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
  203. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
  204. static irqreturn_t ufshcd_intr(int irq, void *__hba);
  205. static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
  206. struct ufs_pa_layer_attr *desired_pwr_mode);
  207. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  208. struct ufs_pa_layer_attr *pwr_mode);
  209. static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
  210. {
  211. return tag >= 0 && tag < hba->nutrs;
  212. }
  213. static inline int ufshcd_enable_irq(struct ufs_hba *hba)
  214. {
  215. int ret = 0;
  216. if (!hba->is_irq_enabled) {
  217. ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
  218. hba);
  219. if (ret)
  220. dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
  221. __func__, ret);
  222. hba->is_irq_enabled = true;
  223. }
  224. return ret;
  225. }
  226. static inline void ufshcd_disable_irq(struct ufs_hba *hba)
  227. {
  228. if (hba->is_irq_enabled) {
  229. free_irq(hba->irq, hba);
  230. hba->is_irq_enabled = false;
  231. }
  232. }
  233. /* replace non-printable or non-ASCII characters with spaces */
  234. static inline void ufshcd_remove_non_printable(char *val)
  235. {
  236. if (!val)
  237. return;
  238. if (*val < 0x20 || *val > 0x7e)
  239. *val = ' ';
  240. }
  241. /*
  242. * ufshcd_wait_for_register - wait for register value to change
  243. * @hba - per-adapter interface
  244. * @reg - mmio register offset
  245. * @mask - mask to apply to read register value
  246. * @val - wait condition
  247. * @interval_us - polling interval in microsecs
  248. * @timeout_ms - timeout in millisecs
  249. * @can_sleep - perform sleep or just spin
  250. *
  251. * Returns -ETIMEDOUT on error, zero on success
  252. */
  253. int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
  254. u32 val, unsigned long interval_us,
  255. unsigned long timeout_ms, bool can_sleep)
  256. {
  257. int err = 0;
  258. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  259. /* ignore bits that we don't intend to wait on */
  260. val = val & mask;
  261. while ((ufshcd_readl(hba, reg) & mask) != val) {
  262. if (can_sleep)
  263. usleep_range(interval_us, interval_us + 50);
  264. else
  265. udelay(interval_us);
  266. if (time_after(jiffies, timeout)) {
  267. if ((ufshcd_readl(hba, reg) & mask) != val)
  268. err = -ETIMEDOUT;
  269. break;
  270. }
  271. }
  272. return err;
  273. }
  274. /**
  275. * ufshcd_get_intr_mask - Get the interrupt bit mask
  276. * @hba - Pointer to adapter instance
  277. *
  278. * Returns interrupt bit mask per version
  279. */
  280. static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
  281. {
  282. if (hba->ufs_version == UFSHCI_VERSION_10)
  283. return INTERRUPT_MASK_ALL_VER_10;
  284. else
  285. return INTERRUPT_MASK_ALL_VER_11;
  286. }
  287. /**
  288. * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
  289. * @hba - Pointer to adapter instance
  290. *
  291. * Returns UFSHCI version supported by the controller
  292. */
  293. static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
  294. {
  295. if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
  296. return ufshcd_vops_get_ufs_hci_version(hba);
  297. return ufshcd_readl(hba, REG_UFS_VERSION);
  298. }
  299. /**
  300. * ufshcd_is_device_present - Check if any device connected to
  301. * the host controller
  302. * @hba: pointer to adapter instance
  303. *
  304. * Returns 1 if device present, 0 if no device detected
  305. */
  306. static inline int ufshcd_is_device_present(struct ufs_hba *hba)
  307. {
  308. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
  309. DEVICE_PRESENT) ? 1 : 0;
  310. }
  311. /**
  312. * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
  313. * @lrb: pointer to local command reference block
  314. *
  315. * This function is used to get the OCS field from UTRD
  316. * Returns the OCS field in the UTRD
  317. */
  318. static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
  319. {
  320. return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
  321. }
  322. /**
  323. * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
  324. * @task_req_descp: pointer to utp_task_req_desc structure
  325. *
  326. * This function is used to get the OCS field from UTMRD
  327. * Returns the OCS field in the UTMRD
  328. */
  329. static inline int
  330. ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
  331. {
  332. return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
  333. }
  334. /**
  335. * ufshcd_get_tm_free_slot - get a free slot for task management request
  336. * @hba: per adapter instance
  337. * @free_slot: pointer to variable with available slot value
  338. *
  339. * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
  340. * Returns 0 if free slot is not available, else return 1 with tag value
  341. * in @free_slot.
  342. */
  343. static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
  344. {
  345. int tag;
  346. bool ret = false;
  347. if (!free_slot)
  348. goto out;
  349. do {
  350. tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
  351. if (tag >= hba->nutmrs)
  352. goto out;
  353. } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
  354. *free_slot = tag;
  355. ret = true;
  356. out:
  357. return ret;
  358. }
  359. static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
  360. {
  361. clear_bit_unlock(slot, &hba->tm_slots_in_use);
  362. }
  363. /**
  364. * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
  365. * @hba: per adapter instance
  366. * @pos: position of the bit to be cleared
  367. */
  368. static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
  369. {
  370. ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
  371. }
  372. /**
  373. * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
  374. * @hba: per adapter instance
  375. * @tag: position of the bit to be cleared
  376. */
  377. static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
  378. {
  379. __clear_bit(tag, &hba->outstanding_reqs);
  380. }
  381. /**
  382. * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
  383. * @reg: Register value of host controller status
  384. *
  385. * Returns integer, 0 on Success and positive value if failed
  386. */
  387. static inline int ufshcd_get_lists_status(u32 reg)
  388. {
  389. /*
  390. * The mask 0xFF is for the following HCS register bits
  391. * Bit Description
  392. * 0 Device Present
  393. * 1 UTRLRDY
  394. * 2 UTMRLRDY
  395. * 3 UCRDY
  396. * 4-7 reserved
  397. */
  398. return ((reg & 0xFF) >> 1) ^ 0x07;
  399. }
  400. /**
  401. * ufshcd_get_uic_cmd_result - Get the UIC command result
  402. * @hba: Pointer to adapter instance
  403. *
  404. * This function gets the result of UIC command completion
  405. * Returns 0 on success, non zero value on error
  406. */
  407. static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
  408. {
  409. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
  410. MASK_UIC_COMMAND_RESULT;
  411. }
  412. /**
  413. * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
  414. * @hba: Pointer to adapter instance
  415. *
  416. * This function gets UIC command argument3
  417. * Returns 0 on success, non zero value on error
  418. */
  419. static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
  420. {
  421. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
  422. }
  423. /**
  424. * ufshcd_get_req_rsp - returns the TR response transaction type
  425. * @ucd_rsp_ptr: pointer to response UPIU
  426. */
  427. static inline int
  428. ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
  429. {
  430. return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
  431. }
  432. /**
  433. * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
  434. * @ucd_rsp_ptr: pointer to response UPIU
  435. *
  436. * This function gets the response status and scsi_status from response UPIU
  437. * Returns the response result code.
  438. */
  439. static inline int
  440. ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
  441. {
  442. return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
  443. }
  444. /*
  445. * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
  446. * from response UPIU
  447. * @ucd_rsp_ptr: pointer to response UPIU
  448. *
  449. * Return the data segment length.
  450. */
  451. static inline unsigned int
  452. ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
  453. {
  454. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  455. MASK_RSP_UPIU_DATA_SEG_LEN;
  456. }
  457. /**
  458. * ufshcd_is_exception_event - Check if the device raised an exception event
  459. * @ucd_rsp_ptr: pointer to response UPIU
  460. *
  461. * The function checks if the device raised an exception event indicated in
  462. * the Device Information field of response UPIU.
  463. *
  464. * Returns true if exception is raised, false otherwise.
  465. */
  466. static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
  467. {
  468. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  469. MASK_RSP_EXCEPTION_EVENT ? true : false;
  470. }
  471. /**
  472. * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
  473. * @hba: per adapter instance
  474. */
  475. static inline void
  476. ufshcd_reset_intr_aggr(struct ufs_hba *hba)
  477. {
  478. ufshcd_writel(hba, INT_AGGR_ENABLE |
  479. INT_AGGR_COUNTER_AND_TIMER_RESET,
  480. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  481. }
  482. /**
  483. * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
  484. * @hba: per adapter instance
  485. * @cnt: Interrupt aggregation counter threshold
  486. * @tmout: Interrupt aggregation timeout value
  487. */
  488. static inline void
  489. ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
  490. {
  491. ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
  492. INT_AGGR_COUNTER_THLD_VAL(cnt) |
  493. INT_AGGR_TIMEOUT_VAL(tmout),
  494. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  495. }
  496. /**
  497. * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
  498. * @hba: per adapter instance
  499. */
  500. static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
  501. {
  502. ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  503. }
  504. /**
  505. * ufshcd_enable_run_stop_reg - Enable run-stop registers,
  506. * When run-stop registers are set to 1, it indicates the
  507. * host controller that it can process the requests
  508. * @hba: per adapter instance
  509. */
  510. static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
  511. {
  512. ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
  513. REG_UTP_TASK_REQ_LIST_RUN_STOP);
  514. ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
  515. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
  516. }
  517. /**
  518. * ufshcd_hba_start - Start controller initialization sequence
  519. * @hba: per adapter instance
  520. */
  521. static inline void ufshcd_hba_start(struct ufs_hba *hba)
  522. {
  523. ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
  524. }
  525. /**
  526. * ufshcd_is_hba_active - Get controller state
  527. * @hba: per adapter instance
  528. *
  529. * Returns zero if controller is active, 1 otherwise
  530. */
  531. static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
  532. {
  533. return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
  534. }
  535. u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
  536. {
  537. /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
  538. if ((hba->ufs_version == UFSHCI_VERSION_10) ||
  539. (hba->ufs_version == UFSHCI_VERSION_11))
  540. return UFS_UNIPRO_VER_1_41;
  541. else
  542. return UFS_UNIPRO_VER_1_6;
  543. }
  544. EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
  545. static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
  546. {
  547. /*
  548. * If both host and device support UniPro ver1.6 or later, PA layer
  549. * parameters tuning happens during link startup itself.
  550. *
  551. * We can manually tune PA layer parameters if either host or device
  552. * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
  553. * logic simple, we will only do manual tuning if local unipro version
  554. * doesn't support ver1.6 or later.
  555. */
  556. if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
  557. return true;
  558. else
  559. return false;
  560. }
  561. static void ufshcd_ungate_work(struct work_struct *work)
  562. {
  563. int ret;
  564. unsigned long flags;
  565. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  566. clk_gating.ungate_work);
  567. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  568. spin_lock_irqsave(hba->host->host_lock, flags);
  569. if (hba->clk_gating.state == CLKS_ON) {
  570. spin_unlock_irqrestore(hba->host->host_lock, flags);
  571. goto unblock_reqs;
  572. }
  573. spin_unlock_irqrestore(hba->host->host_lock, flags);
  574. ufshcd_setup_clocks(hba, true);
  575. /* Exit from hibern8 */
  576. if (ufshcd_can_hibern8_during_gating(hba)) {
  577. /* Prevent gating in this path */
  578. hba->clk_gating.is_suspended = true;
  579. if (ufshcd_is_link_hibern8(hba)) {
  580. ret = ufshcd_uic_hibern8_exit(hba);
  581. if (ret)
  582. dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
  583. __func__, ret);
  584. else
  585. ufshcd_set_link_active(hba);
  586. }
  587. hba->clk_gating.is_suspended = false;
  588. }
  589. unblock_reqs:
  590. if (ufshcd_is_clkscaling_enabled(hba))
  591. devfreq_resume_device(hba->devfreq);
  592. scsi_unblock_requests(hba->host);
  593. }
  594. /**
  595. * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
  596. * Also, exit from hibern8 mode and set the link as active.
  597. * @hba: per adapter instance
  598. * @async: This indicates whether caller should ungate clocks asynchronously.
  599. */
  600. int ufshcd_hold(struct ufs_hba *hba, bool async)
  601. {
  602. int rc = 0;
  603. unsigned long flags;
  604. if (!ufshcd_is_clkgating_allowed(hba))
  605. goto out;
  606. spin_lock_irqsave(hba->host->host_lock, flags);
  607. hba->clk_gating.active_reqs++;
  608. if (ufshcd_eh_in_progress(hba)) {
  609. spin_unlock_irqrestore(hba->host->host_lock, flags);
  610. return 0;
  611. }
  612. start:
  613. switch (hba->clk_gating.state) {
  614. case CLKS_ON:
  615. break;
  616. case REQ_CLKS_OFF:
  617. if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
  618. hba->clk_gating.state = CLKS_ON;
  619. break;
  620. }
  621. /*
  622. * If we here, it means gating work is either done or
  623. * currently running. Hence, fall through to cancel gating
  624. * work and to enable clocks.
  625. */
  626. case CLKS_OFF:
  627. scsi_block_requests(hba->host);
  628. hba->clk_gating.state = REQ_CLKS_ON;
  629. schedule_work(&hba->clk_gating.ungate_work);
  630. /*
  631. * fall through to check if we should wait for this
  632. * work to be done or not.
  633. */
  634. case REQ_CLKS_ON:
  635. if (async) {
  636. rc = -EAGAIN;
  637. hba->clk_gating.active_reqs--;
  638. break;
  639. }
  640. spin_unlock_irqrestore(hba->host->host_lock, flags);
  641. flush_work(&hba->clk_gating.ungate_work);
  642. /* Make sure state is CLKS_ON before returning */
  643. spin_lock_irqsave(hba->host->host_lock, flags);
  644. goto start;
  645. default:
  646. dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
  647. __func__, hba->clk_gating.state);
  648. break;
  649. }
  650. spin_unlock_irqrestore(hba->host->host_lock, flags);
  651. out:
  652. return rc;
  653. }
  654. EXPORT_SYMBOL_GPL(ufshcd_hold);
  655. static void ufshcd_gate_work(struct work_struct *work)
  656. {
  657. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  658. clk_gating.gate_work.work);
  659. unsigned long flags;
  660. spin_lock_irqsave(hba->host->host_lock, flags);
  661. if (hba->clk_gating.is_suspended) {
  662. hba->clk_gating.state = CLKS_ON;
  663. goto rel_lock;
  664. }
  665. if (hba->clk_gating.active_reqs
  666. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  667. || hba->lrb_in_use || hba->outstanding_tasks
  668. || hba->active_uic_cmd || hba->uic_async_done)
  669. goto rel_lock;
  670. spin_unlock_irqrestore(hba->host->host_lock, flags);
  671. /* put the link into hibern8 mode before turning off clocks */
  672. if (ufshcd_can_hibern8_during_gating(hba)) {
  673. if (ufshcd_uic_hibern8_enter(hba)) {
  674. hba->clk_gating.state = CLKS_ON;
  675. goto out;
  676. }
  677. ufshcd_set_link_hibern8(hba);
  678. }
  679. if (ufshcd_is_clkscaling_enabled(hba)) {
  680. devfreq_suspend_device(hba->devfreq);
  681. hba->clk_scaling.window_start_t = 0;
  682. }
  683. if (!ufshcd_is_link_active(hba))
  684. ufshcd_setup_clocks(hba, false);
  685. else
  686. /* If link is active, device ref_clk can't be switched off */
  687. __ufshcd_setup_clocks(hba, false, true);
  688. /*
  689. * In case you are here to cancel this work the gating state
  690. * would be marked as REQ_CLKS_ON. In this case keep the state
  691. * as REQ_CLKS_ON which would anyway imply that clocks are off
  692. * and a request to turn them on is pending. By doing this way,
  693. * we keep the state machine in tact and this would ultimately
  694. * prevent from doing cancel work multiple times when there are
  695. * new requests arriving before the current cancel work is done.
  696. */
  697. spin_lock_irqsave(hba->host->host_lock, flags);
  698. if (hba->clk_gating.state == REQ_CLKS_OFF)
  699. hba->clk_gating.state = CLKS_OFF;
  700. rel_lock:
  701. spin_unlock_irqrestore(hba->host->host_lock, flags);
  702. out:
  703. return;
  704. }
  705. /* host lock must be held before calling this variant */
  706. static void __ufshcd_release(struct ufs_hba *hba)
  707. {
  708. if (!ufshcd_is_clkgating_allowed(hba))
  709. return;
  710. hba->clk_gating.active_reqs--;
  711. if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
  712. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  713. || hba->lrb_in_use || hba->outstanding_tasks
  714. || hba->active_uic_cmd || hba->uic_async_done
  715. || ufshcd_eh_in_progress(hba))
  716. return;
  717. hba->clk_gating.state = REQ_CLKS_OFF;
  718. schedule_delayed_work(&hba->clk_gating.gate_work,
  719. msecs_to_jiffies(hba->clk_gating.delay_ms));
  720. }
  721. void ufshcd_release(struct ufs_hba *hba)
  722. {
  723. unsigned long flags;
  724. spin_lock_irqsave(hba->host->host_lock, flags);
  725. __ufshcd_release(hba);
  726. spin_unlock_irqrestore(hba->host->host_lock, flags);
  727. }
  728. EXPORT_SYMBOL_GPL(ufshcd_release);
  729. static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
  730. struct device_attribute *attr, char *buf)
  731. {
  732. struct ufs_hba *hba = dev_get_drvdata(dev);
  733. return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
  734. }
  735. static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
  736. struct device_attribute *attr, const char *buf, size_t count)
  737. {
  738. struct ufs_hba *hba = dev_get_drvdata(dev);
  739. unsigned long flags, value;
  740. if (kstrtoul(buf, 0, &value))
  741. return -EINVAL;
  742. spin_lock_irqsave(hba->host->host_lock, flags);
  743. hba->clk_gating.delay_ms = value;
  744. spin_unlock_irqrestore(hba->host->host_lock, flags);
  745. return count;
  746. }
  747. static void ufshcd_init_clk_gating(struct ufs_hba *hba)
  748. {
  749. if (!ufshcd_is_clkgating_allowed(hba))
  750. return;
  751. hba->clk_gating.delay_ms = 150;
  752. INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
  753. INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
  754. hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
  755. hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
  756. sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
  757. hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
  758. hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
  759. if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
  760. dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
  761. }
  762. static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
  763. {
  764. if (!ufshcd_is_clkgating_allowed(hba))
  765. return;
  766. device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
  767. cancel_work_sync(&hba->clk_gating.ungate_work);
  768. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  769. }
  770. /* Must be called with host lock acquired */
  771. static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
  772. {
  773. if (!ufshcd_is_clkscaling_enabled(hba))
  774. return;
  775. if (!hba->clk_scaling.is_busy_started) {
  776. hba->clk_scaling.busy_start_t = ktime_get();
  777. hba->clk_scaling.is_busy_started = true;
  778. }
  779. }
  780. static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
  781. {
  782. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  783. if (!ufshcd_is_clkscaling_enabled(hba))
  784. return;
  785. if (!hba->outstanding_reqs && scaling->is_busy_started) {
  786. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  787. scaling->busy_start_t));
  788. scaling->busy_start_t = ktime_set(0, 0);
  789. scaling->is_busy_started = false;
  790. }
  791. }
  792. /**
  793. * ufshcd_send_command - Send SCSI or device management commands
  794. * @hba: per adapter instance
  795. * @task_tag: Task tag of the command
  796. */
  797. static inline
  798. void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
  799. {
  800. ufshcd_clk_scaling_start_busy(hba);
  801. __set_bit(task_tag, &hba->outstanding_reqs);
  802. ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  803. }
  804. /**
  805. * ufshcd_copy_sense_data - Copy sense data in case of check condition
  806. * @lrb - pointer to local reference block
  807. */
  808. static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
  809. {
  810. int len;
  811. if (lrbp->sense_buffer &&
  812. ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
  813. len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
  814. memcpy(lrbp->sense_buffer,
  815. lrbp->ucd_rsp_ptr->sr.sense_data,
  816. min_t(int, len, SCSI_SENSE_BUFFERSIZE));
  817. }
  818. }
  819. /**
  820. * ufshcd_copy_query_response() - Copy the Query Response and the data
  821. * descriptor
  822. * @hba: per adapter instance
  823. * @lrb - pointer to local reference block
  824. */
  825. static
  826. int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  827. {
  828. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  829. memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
  830. /* Get the descriptor */
  831. if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
  832. u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
  833. GENERAL_UPIU_REQUEST_SIZE;
  834. u16 resp_len;
  835. u16 buf_len;
  836. /* data segment length */
  837. resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
  838. MASK_QUERY_DATA_SEG_LEN;
  839. buf_len = be16_to_cpu(
  840. hba->dev_cmd.query.request.upiu_req.length);
  841. if (likely(buf_len >= resp_len)) {
  842. memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
  843. } else {
  844. dev_warn(hba->dev,
  845. "%s: Response size is bigger than buffer",
  846. __func__);
  847. return -EINVAL;
  848. }
  849. }
  850. return 0;
  851. }
  852. /**
  853. * ufshcd_hba_capabilities - Read controller capabilities
  854. * @hba: per adapter instance
  855. */
  856. static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
  857. {
  858. hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
  859. /* nutrs and nutmrs are 0 based values */
  860. hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
  861. hba->nutmrs =
  862. ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
  863. }
  864. /**
  865. * ufshcd_ready_for_uic_cmd - Check if controller is ready
  866. * to accept UIC commands
  867. * @hba: per adapter instance
  868. * Return true on success, else false
  869. */
  870. static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
  871. {
  872. if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
  873. return true;
  874. else
  875. return false;
  876. }
  877. /**
  878. * ufshcd_get_upmcrs - Get the power mode change request status
  879. * @hba: Pointer to adapter instance
  880. *
  881. * This function gets the UPMCRS field of HCS register
  882. * Returns value of UPMCRS field
  883. */
  884. static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
  885. {
  886. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
  887. }
  888. /**
  889. * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
  890. * @hba: per adapter instance
  891. * @uic_cmd: UIC command
  892. *
  893. * Mutex must be held.
  894. */
  895. static inline void
  896. ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  897. {
  898. WARN_ON(hba->active_uic_cmd);
  899. hba->active_uic_cmd = uic_cmd;
  900. /* Write Args */
  901. ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
  902. ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
  903. ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
  904. /* Write UIC Cmd */
  905. ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
  906. REG_UIC_COMMAND);
  907. }
  908. /**
  909. * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
  910. * @hba: per adapter instance
  911. * @uic_command: UIC command
  912. *
  913. * Must be called with mutex held.
  914. * Returns 0 only if success.
  915. */
  916. static int
  917. ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  918. {
  919. int ret;
  920. unsigned long flags;
  921. if (wait_for_completion_timeout(&uic_cmd->done,
  922. msecs_to_jiffies(UIC_CMD_TIMEOUT)))
  923. ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
  924. else
  925. ret = -ETIMEDOUT;
  926. spin_lock_irqsave(hba->host->host_lock, flags);
  927. hba->active_uic_cmd = NULL;
  928. spin_unlock_irqrestore(hba->host->host_lock, flags);
  929. return ret;
  930. }
  931. /**
  932. * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  933. * @hba: per adapter instance
  934. * @uic_cmd: UIC command
  935. * @completion: initialize the completion only if this is set to true
  936. *
  937. * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
  938. * with mutex held and host_lock locked.
  939. * Returns 0 only if success.
  940. */
  941. static int
  942. __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
  943. bool completion)
  944. {
  945. if (!ufshcd_ready_for_uic_cmd(hba)) {
  946. dev_err(hba->dev,
  947. "Controller not ready to accept UIC commands\n");
  948. return -EIO;
  949. }
  950. if (completion)
  951. init_completion(&uic_cmd->done);
  952. ufshcd_dispatch_uic_cmd(hba, uic_cmd);
  953. return 0;
  954. }
  955. /**
  956. * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  957. * @hba: per adapter instance
  958. * @uic_cmd: UIC command
  959. *
  960. * Returns 0 only if success.
  961. */
  962. static int
  963. ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  964. {
  965. int ret;
  966. unsigned long flags;
  967. ufshcd_hold(hba, false);
  968. mutex_lock(&hba->uic_cmd_mutex);
  969. ufshcd_add_delay_before_dme_cmd(hba);
  970. spin_lock_irqsave(hba->host->host_lock, flags);
  971. ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
  972. spin_unlock_irqrestore(hba->host->host_lock, flags);
  973. if (!ret)
  974. ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
  975. mutex_unlock(&hba->uic_cmd_mutex);
  976. ufshcd_release(hba);
  977. return ret;
  978. }
  979. /**
  980. * ufshcd_map_sg - Map scatter-gather list to prdt
  981. * @lrbp - pointer to local reference block
  982. *
  983. * Returns 0 in case of success, non-zero value in case of failure
  984. */
  985. static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  986. {
  987. struct ufshcd_sg_entry *prd_table;
  988. struct scatterlist *sg;
  989. struct scsi_cmnd *cmd;
  990. int sg_segments;
  991. int i;
  992. cmd = lrbp->cmd;
  993. sg_segments = scsi_dma_map(cmd);
  994. if (sg_segments < 0)
  995. return sg_segments;
  996. if (sg_segments) {
  997. if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
  998. lrbp->utr_descriptor_ptr->prd_table_length =
  999. cpu_to_le16((u16)(sg_segments *
  1000. sizeof(struct ufshcd_sg_entry)));
  1001. else
  1002. lrbp->utr_descriptor_ptr->prd_table_length =
  1003. cpu_to_le16((u16) (sg_segments));
  1004. prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
  1005. scsi_for_each_sg(cmd, sg, sg_segments, i) {
  1006. prd_table[i].size =
  1007. cpu_to_le32(((u32) sg_dma_len(sg))-1);
  1008. prd_table[i].base_addr =
  1009. cpu_to_le32(lower_32_bits(sg->dma_address));
  1010. prd_table[i].upper_addr =
  1011. cpu_to_le32(upper_32_bits(sg->dma_address));
  1012. prd_table[i].reserved = 0;
  1013. }
  1014. } else {
  1015. lrbp->utr_descriptor_ptr->prd_table_length = 0;
  1016. }
  1017. return 0;
  1018. }
  1019. /**
  1020. * ufshcd_enable_intr - enable interrupts
  1021. * @hba: per adapter instance
  1022. * @intrs: interrupt bits
  1023. */
  1024. static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
  1025. {
  1026. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  1027. if (hba->ufs_version == UFSHCI_VERSION_10) {
  1028. u32 rw;
  1029. rw = set & INTERRUPT_MASK_RW_VER_10;
  1030. set = rw | ((set ^ intrs) & intrs);
  1031. } else {
  1032. set |= intrs;
  1033. }
  1034. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  1035. }
  1036. /**
  1037. * ufshcd_disable_intr - disable interrupts
  1038. * @hba: per adapter instance
  1039. * @intrs: interrupt bits
  1040. */
  1041. static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
  1042. {
  1043. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  1044. if (hba->ufs_version == UFSHCI_VERSION_10) {
  1045. u32 rw;
  1046. rw = (set & INTERRUPT_MASK_RW_VER_10) &
  1047. ~(intrs & INTERRUPT_MASK_RW_VER_10);
  1048. set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
  1049. } else {
  1050. set &= ~intrs;
  1051. }
  1052. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  1053. }
  1054. /**
  1055. * ufshcd_prepare_req_desc_hdr() - Fills the requests header
  1056. * descriptor according to request
  1057. * @lrbp: pointer to local reference block
  1058. * @upiu_flags: flags required in the header
  1059. * @cmd_dir: requests data direction
  1060. */
  1061. static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
  1062. u32 *upiu_flags, enum dma_data_direction cmd_dir)
  1063. {
  1064. struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
  1065. u32 data_direction;
  1066. u32 dword_0;
  1067. if (cmd_dir == DMA_FROM_DEVICE) {
  1068. data_direction = UTP_DEVICE_TO_HOST;
  1069. *upiu_flags = UPIU_CMD_FLAGS_READ;
  1070. } else if (cmd_dir == DMA_TO_DEVICE) {
  1071. data_direction = UTP_HOST_TO_DEVICE;
  1072. *upiu_flags = UPIU_CMD_FLAGS_WRITE;
  1073. } else {
  1074. data_direction = UTP_NO_DATA_TRANSFER;
  1075. *upiu_flags = UPIU_CMD_FLAGS_NONE;
  1076. }
  1077. dword_0 = data_direction | (lrbp->command_type
  1078. << UPIU_COMMAND_TYPE_OFFSET);
  1079. if (lrbp->intr_cmd)
  1080. dword_0 |= UTP_REQ_DESC_INT_CMD;
  1081. /* Transfer request descriptor header fields */
  1082. req_desc->header.dword_0 = cpu_to_le32(dword_0);
  1083. /* dword_1 is reserved, hence it is set to 0 */
  1084. req_desc->header.dword_1 = 0;
  1085. /*
  1086. * assigning invalid value for command status. Controller
  1087. * updates OCS on command completion, with the command
  1088. * status
  1089. */
  1090. req_desc->header.dword_2 =
  1091. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  1092. /* dword_3 is reserved, hence it is set to 0 */
  1093. req_desc->header.dword_3 = 0;
  1094. req_desc->prd_table_length = 0;
  1095. }
  1096. /**
  1097. * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
  1098. * for scsi commands
  1099. * @lrbp - local reference block pointer
  1100. * @upiu_flags - flags
  1101. */
  1102. static
  1103. void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
  1104. {
  1105. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1106. unsigned short cdb_len;
  1107. /* command descriptor fields */
  1108. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  1109. UPIU_TRANSACTION_COMMAND, upiu_flags,
  1110. lrbp->lun, lrbp->task_tag);
  1111. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  1112. UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
  1113. /* Total EHS length and Data segment length will be zero */
  1114. ucd_req_ptr->header.dword_2 = 0;
  1115. ucd_req_ptr->sc.exp_data_transfer_len =
  1116. cpu_to_be32(lrbp->cmd->sdb.length);
  1117. cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
  1118. memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
  1119. memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
  1120. memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  1121. }
  1122. /**
  1123. * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
  1124. * for query requsts
  1125. * @hba: UFS hba
  1126. * @lrbp: local reference block pointer
  1127. * @upiu_flags: flags
  1128. */
  1129. static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
  1130. struct ufshcd_lrb *lrbp, u32 upiu_flags)
  1131. {
  1132. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1133. struct ufs_query *query = &hba->dev_cmd.query;
  1134. u16 len = be16_to_cpu(query->request.upiu_req.length);
  1135. u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
  1136. /* Query request header */
  1137. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  1138. UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
  1139. lrbp->lun, lrbp->task_tag);
  1140. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  1141. 0, query->request.query_func, 0, 0);
  1142. /* Data segment length only need for WRITE_DESC */
  1143. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  1144. ucd_req_ptr->header.dword_2 =
  1145. UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
  1146. else
  1147. ucd_req_ptr->header.dword_2 = 0;
  1148. /* Copy the Query Request buffer as is */
  1149. memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
  1150. QUERY_OSF_SIZE);
  1151. /* Copy the Descriptor */
  1152. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  1153. memcpy(descp, query->descriptor, len);
  1154. memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  1155. }
  1156. static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
  1157. {
  1158. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1159. memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
  1160. /* command descriptor fields */
  1161. ucd_req_ptr->header.dword_0 =
  1162. UPIU_HEADER_DWORD(
  1163. UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
  1164. /* clear rest of the fields of basic header */
  1165. ucd_req_ptr->header.dword_1 = 0;
  1166. ucd_req_ptr->header.dword_2 = 0;
  1167. memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  1168. }
  1169. /**
  1170. * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
  1171. * for Device Management Purposes
  1172. * @hba - per adapter instance
  1173. * @lrb - pointer to local reference block
  1174. */
  1175. static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1176. {
  1177. u32 upiu_flags;
  1178. int ret = 0;
  1179. if (hba->ufs_version == UFSHCI_VERSION_20)
  1180. lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
  1181. else
  1182. lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
  1183. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
  1184. if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
  1185. ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
  1186. else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
  1187. ufshcd_prepare_utp_nop_upiu(lrbp);
  1188. else
  1189. ret = -EINVAL;
  1190. return ret;
  1191. }
  1192. /**
  1193. * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
  1194. * for SCSI Purposes
  1195. * @hba - per adapter instance
  1196. * @lrb - pointer to local reference block
  1197. */
  1198. static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1199. {
  1200. u32 upiu_flags;
  1201. int ret = 0;
  1202. if (hba->ufs_version == UFSHCI_VERSION_20)
  1203. lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
  1204. else
  1205. lrbp->command_type = UTP_CMD_TYPE_SCSI;
  1206. if (likely(lrbp->cmd)) {
  1207. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
  1208. lrbp->cmd->sc_data_direction);
  1209. ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
  1210. } else {
  1211. ret = -EINVAL;
  1212. }
  1213. return ret;
  1214. }
  1215. /*
  1216. * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
  1217. * @scsi_lun: scsi LUN id
  1218. *
  1219. * Returns UPIU LUN id
  1220. */
  1221. static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
  1222. {
  1223. if (scsi_is_wlun(scsi_lun))
  1224. return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
  1225. | UFS_UPIU_WLUN_ID;
  1226. else
  1227. return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
  1228. }
  1229. /**
  1230. * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
  1231. * @scsi_lun: UPIU W-LUN id
  1232. *
  1233. * Returns SCSI W-LUN id
  1234. */
  1235. static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
  1236. {
  1237. return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
  1238. }
  1239. /**
  1240. * ufshcd_queuecommand - main entry point for SCSI requests
  1241. * @cmd: command from SCSI Midlayer
  1242. * @done: call back function
  1243. *
  1244. * Returns 0 for success, non-zero in case of failure
  1245. */
  1246. static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  1247. {
  1248. struct ufshcd_lrb *lrbp;
  1249. struct ufs_hba *hba;
  1250. unsigned long flags;
  1251. int tag;
  1252. int err = 0;
  1253. hba = shost_priv(host);
  1254. tag = cmd->request->tag;
  1255. if (!ufshcd_valid_tag(hba, tag)) {
  1256. dev_err(hba->dev,
  1257. "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
  1258. __func__, tag, cmd, cmd->request);
  1259. BUG();
  1260. }
  1261. spin_lock_irqsave(hba->host->host_lock, flags);
  1262. switch (hba->ufshcd_state) {
  1263. case UFSHCD_STATE_OPERATIONAL:
  1264. break;
  1265. case UFSHCD_STATE_EH_SCHEDULED:
  1266. case UFSHCD_STATE_RESET:
  1267. err = SCSI_MLQUEUE_HOST_BUSY;
  1268. goto out_unlock;
  1269. case UFSHCD_STATE_ERROR:
  1270. set_host_byte(cmd, DID_ERROR);
  1271. cmd->scsi_done(cmd);
  1272. goto out_unlock;
  1273. default:
  1274. dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
  1275. __func__, hba->ufshcd_state);
  1276. set_host_byte(cmd, DID_BAD_TARGET);
  1277. cmd->scsi_done(cmd);
  1278. goto out_unlock;
  1279. }
  1280. /* if error handling is in progress, don't issue commands */
  1281. if (ufshcd_eh_in_progress(hba)) {
  1282. set_host_byte(cmd, DID_ERROR);
  1283. cmd->scsi_done(cmd);
  1284. goto out_unlock;
  1285. }
  1286. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1287. /* acquire the tag to make sure device cmds don't use it */
  1288. if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
  1289. /*
  1290. * Dev manage command in progress, requeue the command.
  1291. * Requeuing the command helps in cases where the request *may*
  1292. * find different tag instead of waiting for dev manage command
  1293. * completion.
  1294. */
  1295. err = SCSI_MLQUEUE_HOST_BUSY;
  1296. goto out;
  1297. }
  1298. err = ufshcd_hold(hba, true);
  1299. if (err) {
  1300. err = SCSI_MLQUEUE_HOST_BUSY;
  1301. clear_bit_unlock(tag, &hba->lrb_in_use);
  1302. goto out;
  1303. }
  1304. WARN_ON(hba->clk_gating.state != CLKS_ON);
  1305. lrbp = &hba->lrb[tag];
  1306. WARN_ON(lrbp->cmd);
  1307. lrbp->cmd = cmd;
  1308. lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  1309. lrbp->sense_buffer = cmd->sense_buffer;
  1310. lrbp->task_tag = tag;
  1311. lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
  1312. lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
  1313. ufshcd_comp_scsi_upiu(hba, lrbp);
  1314. err = ufshcd_map_sg(hba, lrbp);
  1315. if (err) {
  1316. lrbp->cmd = NULL;
  1317. clear_bit_unlock(tag, &hba->lrb_in_use);
  1318. goto out;
  1319. }
  1320. /* issue command to the controller */
  1321. spin_lock_irqsave(hba->host->host_lock, flags);
  1322. ufshcd_send_command(hba, tag);
  1323. out_unlock:
  1324. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1325. out:
  1326. return err;
  1327. }
  1328. static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
  1329. struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
  1330. {
  1331. lrbp->cmd = NULL;
  1332. lrbp->sense_bufflen = 0;
  1333. lrbp->sense_buffer = NULL;
  1334. lrbp->task_tag = tag;
  1335. lrbp->lun = 0; /* device management cmd is not specific to any LUN */
  1336. lrbp->intr_cmd = true; /* No interrupt aggregation */
  1337. hba->dev_cmd.type = cmd_type;
  1338. return ufshcd_comp_devman_upiu(hba, lrbp);
  1339. }
  1340. static int
  1341. ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
  1342. {
  1343. int err = 0;
  1344. unsigned long flags;
  1345. u32 mask = 1 << tag;
  1346. /* clear outstanding transaction before retry */
  1347. spin_lock_irqsave(hba->host->host_lock, flags);
  1348. ufshcd_utrl_clear(hba, tag);
  1349. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1350. /*
  1351. * wait for for h/w to clear corresponding bit in door-bell.
  1352. * max. wait is 1 sec.
  1353. */
  1354. err = ufshcd_wait_for_register(hba,
  1355. REG_UTP_TRANSFER_REQ_DOOR_BELL,
  1356. mask, ~mask, 1000, 1000, true);
  1357. return err;
  1358. }
  1359. static int
  1360. ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1361. {
  1362. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  1363. /* Get the UPIU response */
  1364. query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
  1365. UPIU_RSP_CODE_OFFSET;
  1366. return query_res->response;
  1367. }
  1368. /**
  1369. * ufshcd_dev_cmd_completion() - handles device management command responses
  1370. * @hba: per adapter instance
  1371. * @lrbp: pointer to local reference block
  1372. */
  1373. static int
  1374. ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1375. {
  1376. int resp;
  1377. int err = 0;
  1378. resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  1379. switch (resp) {
  1380. case UPIU_TRANSACTION_NOP_IN:
  1381. if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
  1382. err = -EINVAL;
  1383. dev_err(hba->dev, "%s: unexpected response %x\n",
  1384. __func__, resp);
  1385. }
  1386. break;
  1387. case UPIU_TRANSACTION_QUERY_RSP:
  1388. err = ufshcd_check_query_response(hba, lrbp);
  1389. if (!err)
  1390. err = ufshcd_copy_query_response(hba, lrbp);
  1391. break;
  1392. case UPIU_TRANSACTION_REJECT_UPIU:
  1393. /* TODO: handle Reject UPIU Response */
  1394. err = -EPERM;
  1395. dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
  1396. __func__);
  1397. break;
  1398. default:
  1399. err = -EINVAL;
  1400. dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
  1401. __func__, resp);
  1402. break;
  1403. }
  1404. return err;
  1405. }
  1406. static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
  1407. struct ufshcd_lrb *lrbp, int max_timeout)
  1408. {
  1409. int err = 0;
  1410. unsigned long time_left;
  1411. unsigned long flags;
  1412. time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
  1413. msecs_to_jiffies(max_timeout));
  1414. spin_lock_irqsave(hba->host->host_lock, flags);
  1415. hba->dev_cmd.complete = NULL;
  1416. if (likely(time_left)) {
  1417. err = ufshcd_get_tr_ocs(lrbp);
  1418. if (!err)
  1419. err = ufshcd_dev_cmd_completion(hba, lrbp);
  1420. }
  1421. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1422. if (!time_left) {
  1423. err = -ETIMEDOUT;
  1424. dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
  1425. __func__, lrbp->task_tag);
  1426. if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
  1427. /* successfully cleared the command, retry if needed */
  1428. err = -EAGAIN;
  1429. /*
  1430. * in case of an error, after clearing the doorbell,
  1431. * we also need to clear the outstanding_request
  1432. * field in hba
  1433. */
  1434. ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
  1435. }
  1436. return err;
  1437. }
  1438. /**
  1439. * ufshcd_get_dev_cmd_tag - Get device management command tag
  1440. * @hba: per-adapter instance
  1441. * @tag: pointer to variable with available slot value
  1442. *
  1443. * Get a free slot and lock it until device management command
  1444. * completes.
  1445. *
  1446. * Returns false if free slot is unavailable for locking, else
  1447. * return true with tag value in @tag.
  1448. */
  1449. static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
  1450. {
  1451. int tag;
  1452. bool ret = false;
  1453. unsigned long tmp;
  1454. if (!tag_out)
  1455. goto out;
  1456. do {
  1457. tmp = ~hba->lrb_in_use;
  1458. tag = find_last_bit(&tmp, hba->nutrs);
  1459. if (tag >= hba->nutrs)
  1460. goto out;
  1461. } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
  1462. *tag_out = tag;
  1463. ret = true;
  1464. out:
  1465. return ret;
  1466. }
  1467. static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
  1468. {
  1469. clear_bit_unlock(tag, &hba->lrb_in_use);
  1470. }
  1471. /**
  1472. * ufshcd_exec_dev_cmd - API for sending device management requests
  1473. * @hba - UFS hba
  1474. * @cmd_type - specifies the type (NOP, Query...)
  1475. * @timeout - time in seconds
  1476. *
  1477. * NOTE: Since there is only one available tag for device management commands,
  1478. * it is expected you hold the hba->dev_cmd.lock mutex.
  1479. */
  1480. static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
  1481. enum dev_cmd_type cmd_type, int timeout)
  1482. {
  1483. struct ufshcd_lrb *lrbp;
  1484. int err;
  1485. int tag;
  1486. struct completion wait;
  1487. unsigned long flags;
  1488. /*
  1489. * Get free slot, sleep if slots are unavailable.
  1490. * Even though we use wait_event() which sleeps indefinitely,
  1491. * the maximum wait time is bounded by SCSI request timeout.
  1492. */
  1493. wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
  1494. init_completion(&wait);
  1495. lrbp = &hba->lrb[tag];
  1496. WARN_ON(lrbp->cmd);
  1497. err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
  1498. if (unlikely(err))
  1499. goto out_put_tag;
  1500. hba->dev_cmd.complete = &wait;
  1501. /* Make sure descriptors are ready before ringing the doorbell */
  1502. wmb();
  1503. spin_lock_irqsave(hba->host->host_lock, flags);
  1504. ufshcd_send_command(hba, tag);
  1505. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1506. err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
  1507. out_put_tag:
  1508. ufshcd_put_dev_cmd_tag(hba, tag);
  1509. wake_up(&hba->dev_cmd.tag_wq);
  1510. return err;
  1511. }
  1512. /**
  1513. * ufshcd_init_query() - init the query response and request parameters
  1514. * @hba: per-adapter instance
  1515. * @request: address of the request pointer to be initialized
  1516. * @response: address of the response pointer to be initialized
  1517. * @opcode: operation to perform
  1518. * @idn: flag idn to access
  1519. * @index: LU number to access
  1520. * @selector: query/flag/descriptor further identification
  1521. */
  1522. static inline void ufshcd_init_query(struct ufs_hba *hba,
  1523. struct ufs_query_req **request, struct ufs_query_res **response,
  1524. enum query_opcode opcode, u8 idn, u8 index, u8 selector)
  1525. {
  1526. *request = &hba->dev_cmd.query.request;
  1527. *response = &hba->dev_cmd.query.response;
  1528. memset(*request, 0, sizeof(struct ufs_query_req));
  1529. memset(*response, 0, sizeof(struct ufs_query_res));
  1530. (*request)->upiu_req.opcode = opcode;
  1531. (*request)->upiu_req.idn = idn;
  1532. (*request)->upiu_req.index = index;
  1533. (*request)->upiu_req.selector = selector;
  1534. }
  1535. static int ufshcd_query_flag_retry(struct ufs_hba *hba,
  1536. enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
  1537. {
  1538. int ret;
  1539. int retries;
  1540. for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
  1541. ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
  1542. if (ret)
  1543. dev_dbg(hba->dev,
  1544. "%s: failed with error %d, retries %d\n",
  1545. __func__, ret, retries);
  1546. else
  1547. break;
  1548. }
  1549. if (ret)
  1550. dev_err(hba->dev,
  1551. "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
  1552. __func__, opcode, idn, ret, retries);
  1553. return ret;
  1554. }
  1555. /**
  1556. * ufshcd_query_flag() - API function for sending flag query requests
  1557. * hba: per-adapter instance
  1558. * query_opcode: flag query to perform
  1559. * idn: flag idn to access
  1560. * flag_res: the flag value after the query request completes
  1561. *
  1562. * Returns 0 for success, non-zero in case of failure
  1563. */
  1564. int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
  1565. enum flag_idn idn, bool *flag_res)
  1566. {
  1567. struct ufs_query_req *request = NULL;
  1568. struct ufs_query_res *response = NULL;
  1569. int err, index = 0, selector = 0;
  1570. int timeout = QUERY_REQ_TIMEOUT;
  1571. BUG_ON(!hba);
  1572. ufshcd_hold(hba, false);
  1573. mutex_lock(&hba->dev_cmd.lock);
  1574. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  1575. selector);
  1576. switch (opcode) {
  1577. case UPIU_QUERY_OPCODE_SET_FLAG:
  1578. case UPIU_QUERY_OPCODE_CLEAR_FLAG:
  1579. case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
  1580. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  1581. break;
  1582. case UPIU_QUERY_OPCODE_READ_FLAG:
  1583. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  1584. if (!flag_res) {
  1585. /* No dummy reads */
  1586. dev_err(hba->dev, "%s: Invalid argument for read request\n",
  1587. __func__);
  1588. err = -EINVAL;
  1589. goto out_unlock;
  1590. }
  1591. break;
  1592. default:
  1593. dev_err(hba->dev,
  1594. "%s: Expected query flag opcode but got = %d\n",
  1595. __func__, opcode);
  1596. err = -EINVAL;
  1597. goto out_unlock;
  1598. }
  1599. if (idn == QUERY_FLAG_IDN_FDEVICEINIT)
  1600. timeout = QUERY_FDEVICEINIT_REQ_TIMEOUT;
  1601. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
  1602. if (err) {
  1603. dev_err(hba->dev,
  1604. "%s: Sending flag query for idn %d failed, err = %d\n",
  1605. __func__, idn, err);
  1606. goto out_unlock;
  1607. }
  1608. if (flag_res)
  1609. *flag_res = (be32_to_cpu(response->upiu_res.value) &
  1610. MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
  1611. out_unlock:
  1612. mutex_unlock(&hba->dev_cmd.lock);
  1613. ufshcd_release(hba);
  1614. return err;
  1615. }
  1616. /**
  1617. * ufshcd_query_attr - API function for sending attribute requests
  1618. * hba: per-adapter instance
  1619. * opcode: attribute opcode
  1620. * idn: attribute idn to access
  1621. * index: index field
  1622. * selector: selector field
  1623. * attr_val: the attribute value after the query request completes
  1624. *
  1625. * Returns 0 for success, non-zero in case of failure
  1626. */
  1627. static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
  1628. enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
  1629. {
  1630. struct ufs_query_req *request = NULL;
  1631. struct ufs_query_res *response = NULL;
  1632. int err;
  1633. BUG_ON(!hba);
  1634. ufshcd_hold(hba, false);
  1635. if (!attr_val) {
  1636. dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
  1637. __func__, opcode);
  1638. err = -EINVAL;
  1639. goto out;
  1640. }
  1641. mutex_lock(&hba->dev_cmd.lock);
  1642. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  1643. selector);
  1644. switch (opcode) {
  1645. case UPIU_QUERY_OPCODE_WRITE_ATTR:
  1646. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  1647. request->upiu_req.value = cpu_to_be32(*attr_val);
  1648. break;
  1649. case UPIU_QUERY_OPCODE_READ_ATTR:
  1650. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  1651. break;
  1652. default:
  1653. dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
  1654. __func__, opcode);
  1655. err = -EINVAL;
  1656. goto out_unlock;
  1657. }
  1658. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  1659. if (err) {
  1660. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
  1661. __func__, opcode, idn, err);
  1662. goto out_unlock;
  1663. }
  1664. *attr_val = be32_to_cpu(response->upiu_res.value);
  1665. out_unlock:
  1666. mutex_unlock(&hba->dev_cmd.lock);
  1667. out:
  1668. ufshcd_release(hba);
  1669. return err;
  1670. }
  1671. /**
  1672. * ufshcd_query_attr_retry() - API function for sending query
  1673. * attribute with retries
  1674. * @hba: per-adapter instance
  1675. * @opcode: attribute opcode
  1676. * @idn: attribute idn to access
  1677. * @index: index field
  1678. * @selector: selector field
  1679. * @attr_val: the attribute value after the query request
  1680. * completes
  1681. *
  1682. * Returns 0 for success, non-zero in case of failure
  1683. */
  1684. static int ufshcd_query_attr_retry(struct ufs_hba *hba,
  1685. enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
  1686. u32 *attr_val)
  1687. {
  1688. int ret = 0;
  1689. u32 retries;
  1690. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  1691. ret = ufshcd_query_attr(hba, opcode, idn, index,
  1692. selector, attr_val);
  1693. if (ret)
  1694. dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
  1695. __func__, ret, retries);
  1696. else
  1697. break;
  1698. }
  1699. if (ret)
  1700. dev_err(hba->dev,
  1701. "%s: query attribute, idn %d, failed with error %d after %d retires\n",
  1702. __func__, idn, ret, QUERY_REQ_RETRIES);
  1703. return ret;
  1704. }
  1705. static int __ufshcd_query_descriptor(struct ufs_hba *hba,
  1706. enum query_opcode opcode, enum desc_idn idn, u8 index,
  1707. u8 selector, u8 *desc_buf, int *buf_len)
  1708. {
  1709. struct ufs_query_req *request = NULL;
  1710. struct ufs_query_res *response = NULL;
  1711. int err;
  1712. BUG_ON(!hba);
  1713. ufshcd_hold(hba, false);
  1714. if (!desc_buf) {
  1715. dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
  1716. __func__, opcode);
  1717. err = -EINVAL;
  1718. goto out;
  1719. }
  1720. if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
  1721. dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
  1722. __func__, *buf_len);
  1723. err = -EINVAL;
  1724. goto out;
  1725. }
  1726. mutex_lock(&hba->dev_cmd.lock);
  1727. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  1728. selector);
  1729. hba->dev_cmd.query.descriptor = desc_buf;
  1730. request->upiu_req.length = cpu_to_be16(*buf_len);
  1731. switch (opcode) {
  1732. case UPIU_QUERY_OPCODE_WRITE_DESC:
  1733. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  1734. break;
  1735. case UPIU_QUERY_OPCODE_READ_DESC:
  1736. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  1737. break;
  1738. default:
  1739. dev_err(hba->dev,
  1740. "%s: Expected query descriptor opcode but got = 0x%.2x\n",
  1741. __func__, opcode);
  1742. err = -EINVAL;
  1743. goto out_unlock;
  1744. }
  1745. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  1746. if (err) {
  1747. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
  1748. __func__, opcode, idn, err);
  1749. goto out_unlock;
  1750. }
  1751. hba->dev_cmd.query.descriptor = NULL;
  1752. *buf_len = be16_to_cpu(response->upiu_res.length);
  1753. out_unlock:
  1754. mutex_unlock(&hba->dev_cmd.lock);
  1755. out:
  1756. ufshcd_release(hba);
  1757. return err;
  1758. }
  1759. /**
  1760. * ufshcd_query_descriptor_retry - API function for sending descriptor
  1761. * requests
  1762. * hba: per-adapter instance
  1763. * opcode: attribute opcode
  1764. * idn: attribute idn to access
  1765. * index: index field
  1766. * selector: selector field
  1767. * desc_buf: the buffer that contains the descriptor
  1768. * buf_len: length parameter passed to the device
  1769. *
  1770. * Returns 0 for success, non-zero in case of failure.
  1771. * The buf_len parameter will contain, on return, the length parameter
  1772. * received on the response.
  1773. */
  1774. int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
  1775. enum query_opcode opcode, enum desc_idn idn, u8 index,
  1776. u8 selector, u8 *desc_buf, int *buf_len)
  1777. {
  1778. int err;
  1779. int retries;
  1780. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  1781. err = __ufshcd_query_descriptor(hba, opcode, idn, index,
  1782. selector, desc_buf, buf_len);
  1783. if (!err || err == -EINVAL)
  1784. break;
  1785. }
  1786. return err;
  1787. }
  1788. EXPORT_SYMBOL(ufshcd_query_descriptor_retry);
  1789. /**
  1790. * ufshcd_read_desc_param - read the specified descriptor parameter
  1791. * @hba: Pointer to adapter instance
  1792. * @desc_id: descriptor idn value
  1793. * @desc_index: descriptor index
  1794. * @param_offset: offset of the parameter to read
  1795. * @param_read_buf: pointer to buffer where parameter would be read
  1796. * @param_size: sizeof(param_read_buf)
  1797. *
  1798. * Return 0 in case of success, non-zero otherwise
  1799. */
  1800. static int ufshcd_read_desc_param(struct ufs_hba *hba,
  1801. enum desc_idn desc_id,
  1802. int desc_index,
  1803. u32 param_offset,
  1804. u8 *param_read_buf,
  1805. u32 param_size)
  1806. {
  1807. int ret;
  1808. u8 *desc_buf;
  1809. u32 buff_len;
  1810. bool is_kmalloc = true;
  1811. /* safety checks */
  1812. if (desc_id >= QUERY_DESC_IDN_MAX)
  1813. return -EINVAL;
  1814. buff_len = ufs_query_desc_max_size[desc_id];
  1815. if ((param_offset + param_size) > buff_len)
  1816. return -EINVAL;
  1817. if (!param_offset && (param_size == buff_len)) {
  1818. /* memory space already available to hold full descriptor */
  1819. desc_buf = param_read_buf;
  1820. is_kmalloc = false;
  1821. } else {
  1822. /* allocate memory to hold full descriptor */
  1823. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  1824. if (!desc_buf)
  1825. return -ENOMEM;
  1826. }
  1827. ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
  1828. desc_id, desc_index, 0, desc_buf,
  1829. &buff_len);
  1830. if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
  1831. (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
  1832. ufs_query_desc_max_size[desc_id])
  1833. || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
  1834. dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
  1835. __func__, desc_id, param_offset, buff_len, ret);
  1836. if (!ret)
  1837. ret = -EINVAL;
  1838. goto out;
  1839. }
  1840. if (is_kmalloc)
  1841. memcpy(param_read_buf, &desc_buf[param_offset], param_size);
  1842. out:
  1843. if (is_kmalloc)
  1844. kfree(desc_buf);
  1845. return ret;
  1846. }
  1847. static inline int ufshcd_read_desc(struct ufs_hba *hba,
  1848. enum desc_idn desc_id,
  1849. int desc_index,
  1850. u8 *buf,
  1851. u32 size)
  1852. {
  1853. return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
  1854. }
  1855. static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
  1856. u8 *buf,
  1857. u32 size)
  1858. {
  1859. return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
  1860. }
  1861. int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
  1862. {
  1863. return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
  1864. }
  1865. EXPORT_SYMBOL(ufshcd_read_device_desc);
  1866. /**
  1867. * ufshcd_read_string_desc - read string descriptor
  1868. * @hba: pointer to adapter instance
  1869. * @desc_index: descriptor index
  1870. * @buf: pointer to buffer where descriptor would be read
  1871. * @size: size of buf
  1872. * @ascii: if true convert from unicode to ascii characters
  1873. *
  1874. * Return 0 in case of success, non-zero otherwise
  1875. */
  1876. int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf,
  1877. u32 size, bool ascii)
  1878. {
  1879. int err = 0;
  1880. err = ufshcd_read_desc(hba,
  1881. QUERY_DESC_IDN_STRING, desc_index, buf, size);
  1882. if (err) {
  1883. dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
  1884. __func__, QUERY_REQ_RETRIES, err);
  1885. goto out;
  1886. }
  1887. if (ascii) {
  1888. int desc_len;
  1889. int ascii_len;
  1890. int i;
  1891. char *buff_ascii;
  1892. desc_len = buf[0];
  1893. /* remove header and divide by 2 to move from UTF16 to UTF8 */
  1894. ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
  1895. if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
  1896. dev_err(hba->dev, "%s: buffer allocated size is too small\n",
  1897. __func__);
  1898. err = -ENOMEM;
  1899. goto out;
  1900. }
  1901. buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
  1902. if (!buff_ascii) {
  1903. err = -ENOMEM;
  1904. goto out;
  1905. }
  1906. /*
  1907. * the descriptor contains string in UTF16 format
  1908. * we need to convert to utf-8 so it can be displayed
  1909. */
  1910. utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
  1911. desc_len - QUERY_DESC_HDR_SIZE,
  1912. UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
  1913. /* replace non-printable or non-ASCII characters with spaces */
  1914. for (i = 0; i < ascii_len; i++)
  1915. ufshcd_remove_non_printable(&buff_ascii[i]);
  1916. memset(buf + QUERY_DESC_HDR_SIZE, 0,
  1917. size - QUERY_DESC_HDR_SIZE);
  1918. memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
  1919. buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
  1920. kfree(buff_ascii);
  1921. }
  1922. out:
  1923. return err;
  1924. }
  1925. EXPORT_SYMBOL(ufshcd_read_string_desc);
  1926. /**
  1927. * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
  1928. * @hba: Pointer to adapter instance
  1929. * @lun: lun id
  1930. * @param_offset: offset of the parameter to read
  1931. * @param_read_buf: pointer to buffer where parameter would be read
  1932. * @param_size: sizeof(param_read_buf)
  1933. *
  1934. * Return 0 in case of success, non-zero otherwise
  1935. */
  1936. static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
  1937. int lun,
  1938. enum unit_desc_param param_offset,
  1939. u8 *param_read_buf,
  1940. u32 param_size)
  1941. {
  1942. /*
  1943. * Unit descriptors are only available for general purpose LUs (LUN id
  1944. * from 0 to 7) and RPMB Well known LU.
  1945. */
  1946. if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
  1947. return -EOPNOTSUPP;
  1948. return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
  1949. param_offset, param_read_buf, param_size);
  1950. }
  1951. /**
  1952. * ufshcd_memory_alloc - allocate memory for host memory space data structures
  1953. * @hba: per adapter instance
  1954. *
  1955. * 1. Allocate DMA memory for Command Descriptor array
  1956. * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
  1957. * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
  1958. * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
  1959. * (UTMRDL)
  1960. * 4. Allocate memory for local reference block(lrb).
  1961. *
  1962. * Returns 0 for success, non-zero in case of failure
  1963. */
  1964. static int ufshcd_memory_alloc(struct ufs_hba *hba)
  1965. {
  1966. size_t utmrdl_size, utrdl_size, ucdl_size;
  1967. /* Allocate memory for UTP command descriptors */
  1968. ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
  1969. hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
  1970. ucdl_size,
  1971. &hba->ucdl_dma_addr,
  1972. GFP_KERNEL);
  1973. /*
  1974. * UFSHCI requires UTP command descriptor to be 128 byte aligned.
  1975. * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
  1976. * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
  1977. * be aligned to 128 bytes as well
  1978. */
  1979. if (!hba->ucdl_base_addr ||
  1980. WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
  1981. dev_err(hba->dev,
  1982. "Command Descriptor Memory allocation failed\n");
  1983. goto out;
  1984. }
  1985. /*
  1986. * Allocate memory for UTP Transfer descriptors
  1987. * UFSHCI requires 1024 byte alignment of UTRD
  1988. */
  1989. utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
  1990. hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
  1991. utrdl_size,
  1992. &hba->utrdl_dma_addr,
  1993. GFP_KERNEL);
  1994. if (!hba->utrdl_base_addr ||
  1995. WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
  1996. dev_err(hba->dev,
  1997. "Transfer Descriptor Memory allocation failed\n");
  1998. goto out;
  1999. }
  2000. /*
  2001. * Allocate memory for UTP Task Management descriptors
  2002. * UFSHCI requires 1024 byte alignment of UTMRD
  2003. */
  2004. utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
  2005. hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
  2006. utmrdl_size,
  2007. &hba->utmrdl_dma_addr,
  2008. GFP_KERNEL);
  2009. if (!hba->utmrdl_base_addr ||
  2010. WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
  2011. dev_err(hba->dev,
  2012. "Task Management Descriptor Memory allocation failed\n");
  2013. goto out;
  2014. }
  2015. /* Allocate memory for local reference block */
  2016. hba->lrb = devm_kzalloc(hba->dev,
  2017. hba->nutrs * sizeof(struct ufshcd_lrb),
  2018. GFP_KERNEL);
  2019. if (!hba->lrb) {
  2020. dev_err(hba->dev, "LRB Memory allocation failed\n");
  2021. goto out;
  2022. }
  2023. return 0;
  2024. out:
  2025. return -ENOMEM;
  2026. }
  2027. /**
  2028. * ufshcd_host_memory_configure - configure local reference block with
  2029. * memory offsets
  2030. * @hba: per adapter instance
  2031. *
  2032. * Configure Host memory space
  2033. * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
  2034. * address.
  2035. * 2. Update each UTRD with Response UPIU offset, Response UPIU length
  2036. * and PRDT offset.
  2037. * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
  2038. * into local reference block.
  2039. */
  2040. static void ufshcd_host_memory_configure(struct ufs_hba *hba)
  2041. {
  2042. struct utp_transfer_cmd_desc *cmd_descp;
  2043. struct utp_transfer_req_desc *utrdlp;
  2044. dma_addr_t cmd_desc_dma_addr;
  2045. dma_addr_t cmd_desc_element_addr;
  2046. u16 response_offset;
  2047. u16 prdt_offset;
  2048. int cmd_desc_size;
  2049. int i;
  2050. utrdlp = hba->utrdl_base_addr;
  2051. cmd_descp = hba->ucdl_base_addr;
  2052. response_offset =
  2053. offsetof(struct utp_transfer_cmd_desc, response_upiu);
  2054. prdt_offset =
  2055. offsetof(struct utp_transfer_cmd_desc, prd_table);
  2056. cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
  2057. cmd_desc_dma_addr = hba->ucdl_dma_addr;
  2058. for (i = 0; i < hba->nutrs; i++) {
  2059. /* Configure UTRD with command descriptor base address */
  2060. cmd_desc_element_addr =
  2061. (cmd_desc_dma_addr + (cmd_desc_size * i));
  2062. utrdlp[i].command_desc_base_addr_lo =
  2063. cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
  2064. utrdlp[i].command_desc_base_addr_hi =
  2065. cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
  2066. /* Response upiu and prdt offset should be in double words */
  2067. if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
  2068. utrdlp[i].response_upiu_offset =
  2069. cpu_to_le16(response_offset);
  2070. utrdlp[i].prd_table_offset =
  2071. cpu_to_le16(prdt_offset);
  2072. utrdlp[i].response_upiu_length =
  2073. cpu_to_le16(ALIGNED_UPIU_SIZE);
  2074. } else {
  2075. utrdlp[i].response_upiu_offset =
  2076. cpu_to_le16((response_offset >> 2));
  2077. utrdlp[i].prd_table_offset =
  2078. cpu_to_le16((prdt_offset >> 2));
  2079. utrdlp[i].response_upiu_length =
  2080. cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
  2081. }
  2082. hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
  2083. hba->lrb[i].ucd_req_ptr =
  2084. (struct utp_upiu_req *)(cmd_descp + i);
  2085. hba->lrb[i].ucd_rsp_ptr =
  2086. (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
  2087. hba->lrb[i].ucd_prdt_ptr =
  2088. (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
  2089. }
  2090. }
  2091. /**
  2092. * ufshcd_dme_link_startup - Notify Unipro to perform link startup
  2093. * @hba: per adapter instance
  2094. *
  2095. * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
  2096. * in order to initialize the Unipro link startup procedure.
  2097. * Once the Unipro links are up, the device connected to the controller
  2098. * is detected.
  2099. *
  2100. * Returns 0 on success, non-zero value on failure
  2101. */
  2102. static int ufshcd_dme_link_startup(struct ufs_hba *hba)
  2103. {
  2104. struct uic_command uic_cmd = {0};
  2105. int ret;
  2106. uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
  2107. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  2108. if (ret)
  2109. dev_err(hba->dev,
  2110. "dme-link-startup: error code %d\n", ret);
  2111. return ret;
  2112. }
  2113. static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
  2114. {
  2115. #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
  2116. unsigned long min_sleep_time_us;
  2117. if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
  2118. return;
  2119. /*
  2120. * last_dme_cmd_tstamp will be 0 only for 1st call to
  2121. * this function
  2122. */
  2123. if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
  2124. min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
  2125. } else {
  2126. unsigned long delta =
  2127. (unsigned long) ktime_to_us(
  2128. ktime_sub(ktime_get(),
  2129. hba->last_dme_cmd_tstamp));
  2130. if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
  2131. min_sleep_time_us =
  2132. MIN_DELAY_BEFORE_DME_CMDS_US - delta;
  2133. else
  2134. return; /* no more delay required */
  2135. }
  2136. /* allow sleep for extra 50us if needed */
  2137. usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
  2138. }
  2139. /**
  2140. * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
  2141. * @hba: per adapter instance
  2142. * @attr_sel: uic command argument1
  2143. * @attr_set: attribute set type as uic command argument2
  2144. * @mib_val: setting value as uic command argument3
  2145. * @peer: indicate whether peer or local
  2146. *
  2147. * Returns 0 on success, non-zero value on failure
  2148. */
  2149. int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
  2150. u8 attr_set, u32 mib_val, u8 peer)
  2151. {
  2152. struct uic_command uic_cmd = {0};
  2153. static const char *const action[] = {
  2154. "dme-set",
  2155. "dme-peer-set"
  2156. };
  2157. const char *set = action[!!peer];
  2158. int ret;
  2159. int retries = UFS_UIC_COMMAND_RETRIES;
  2160. uic_cmd.command = peer ?
  2161. UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
  2162. uic_cmd.argument1 = attr_sel;
  2163. uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
  2164. uic_cmd.argument3 = mib_val;
  2165. do {
  2166. /* for peer attributes we retry upon failure */
  2167. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  2168. if (ret)
  2169. dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
  2170. set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
  2171. } while (ret && peer && --retries);
  2172. if (!retries)
  2173. dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
  2174. set, UIC_GET_ATTR_ID(attr_sel), mib_val,
  2175. retries);
  2176. return ret;
  2177. }
  2178. EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
  2179. /**
  2180. * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
  2181. * @hba: per adapter instance
  2182. * @attr_sel: uic command argument1
  2183. * @mib_val: the value of the attribute as returned by the UIC command
  2184. * @peer: indicate whether peer or local
  2185. *
  2186. * Returns 0 on success, non-zero value on failure
  2187. */
  2188. int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
  2189. u32 *mib_val, u8 peer)
  2190. {
  2191. struct uic_command uic_cmd = {0};
  2192. static const char *const action[] = {
  2193. "dme-get",
  2194. "dme-peer-get"
  2195. };
  2196. const char *get = action[!!peer];
  2197. int ret;
  2198. int retries = UFS_UIC_COMMAND_RETRIES;
  2199. struct ufs_pa_layer_attr orig_pwr_info;
  2200. struct ufs_pa_layer_attr temp_pwr_info;
  2201. bool pwr_mode_change = false;
  2202. if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
  2203. orig_pwr_info = hba->pwr_info;
  2204. temp_pwr_info = orig_pwr_info;
  2205. if (orig_pwr_info.pwr_tx == FAST_MODE ||
  2206. orig_pwr_info.pwr_rx == FAST_MODE) {
  2207. temp_pwr_info.pwr_tx = FASTAUTO_MODE;
  2208. temp_pwr_info.pwr_rx = FASTAUTO_MODE;
  2209. pwr_mode_change = true;
  2210. } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
  2211. orig_pwr_info.pwr_rx == SLOW_MODE) {
  2212. temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
  2213. temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
  2214. pwr_mode_change = true;
  2215. }
  2216. if (pwr_mode_change) {
  2217. ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
  2218. if (ret)
  2219. goto out;
  2220. }
  2221. }
  2222. uic_cmd.command = peer ?
  2223. UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
  2224. uic_cmd.argument1 = attr_sel;
  2225. do {
  2226. /* for peer attributes we retry upon failure */
  2227. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  2228. if (ret)
  2229. dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
  2230. get, UIC_GET_ATTR_ID(attr_sel), ret);
  2231. } while (ret && peer && --retries);
  2232. if (!retries)
  2233. dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
  2234. get, UIC_GET_ATTR_ID(attr_sel), retries);
  2235. if (mib_val && !ret)
  2236. *mib_val = uic_cmd.argument3;
  2237. if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
  2238. && pwr_mode_change)
  2239. ufshcd_change_power_mode(hba, &orig_pwr_info);
  2240. out:
  2241. return ret;
  2242. }
  2243. EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
  2244. /**
  2245. * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
  2246. * state) and waits for it to take effect.
  2247. *
  2248. * @hba: per adapter instance
  2249. * @cmd: UIC command to execute
  2250. *
  2251. * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
  2252. * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
  2253. * and device UniPro link and hence it's final completion would be indicated by
  2254. * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
  2255. * addition to normal UIC command completion Status (UCCS). This function only
  2256. * returns after the relevant status bits indicate the completion.
  2257. *
  2258. * Returns 0 on success, non-zero value on failure
  2259. */
  2260. static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
  2261. {
  2262. struct completion uic_async_done;
  2263. unsigned long flags;
  2264. u8 status;
  2265. int ret;
  2266. bool reenable_intr = false;
  2267. mutex_lock(&hba->uic_cmd_mutex);
  2268. init_completion(&uic_async_done);
  2269. ufshcd_add_delay_before_dme_cmd(hba);
  2270. spin_lock_irqsave(hba->host->host_lock, flags);
  2271. hba->uic_async_done = &uic_async_done;
  2272. if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
  2273. ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
  2274. /*
  2275. * Make sure UIC command completion interrupt is disabled before
  2276. * issuing UIC command.
  2277. */
  2278. wmb();
  2279. reenable_intr = true;
  2280. }
  2281. ret = __ufshcd_send_uic_cmd(hba, cmd, false);
  2282. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2283. if (ret) {
  2284. dev_err(hba->dev,
  2285. "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
  2286. cmd->command, cmd->argument3, ret);
  2287. goto out;
  2288. }
  2289. if (!wait_for_completion_timeout(hba->uic_async_done,
  2290. msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
  2291. dev_err(hba->dev,
  2292. "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
  2293. cmd->command, cmd->argument3);
  2294. ret = -ETIMEDOUT;
  2295. goto out;
  2296. }
  2297. status = ufshcd_get_upmcrs(hba);
  2298. if (status != PWR_LOCAL) {
  2299. dev_err(hba->dev,
  2300. "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
  2301. cmd->command, status);
  2302. ret = (status != PWR_OK) ? status : -1;
  2303. }
  2304. out:
  2305. spin_lock_irqsave(hba->host->host_lock, flags);
  2306. hba->active_uic_cmd = NULL;
  2307. hba->uic_async_done = NULL;
  2308. if (reenable_intr)
  2309. ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
  2310. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2311. mutex_unlock(&hba->uic_cmd_mutex);
  2312. return ret;
  2313. }
  2314. /**
  2315. * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
  2316. * using DME_SET primitives.
  2317. * @hba: per adapter instance
  2318. * @mode: powr mode value
  2319. *
  2320. * Returns 0 on success, non-zero value on failure
  2321. */
  2322. static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
  2323. {
  2324. struct uic_command uic_cmd = {0};
  2325. int ret;
  2326. if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
  2327. ret = ufshcd_dme_set(hba,
  2328. UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
  2329. if (ret) {
  2330. dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
  2331. __func__, ret);
  2332. goto out;
  2333. }
  2334. }
  2335. uic_cmd.command = UIC_CMD_DME_SET;
  2336. uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
  2337. uic_cmd.argument3 = mode;
  2338. ufshcd_hold(hba, false);
  2339. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  2340. ufshcd_release(hba);
  2341. out:
  2342. return ret;
  2343. }
  2344. static int ufshcd_link_recovery(struct ufs_hba *hba)
  2345. {
  2346. int ret;
  2347. unsigned long flags;
  2348. spin_lock_irqsave(hba->host->host_lock, flags);
  2349. hba->ufshcd_state = UFSHCD_STATE_RESET;
  2350. ufshcd_set_eh_in_progress(hba);
  2351. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2352. ret = ufshcd_host_reset_and_restore(hba);
  2353. spin_lock_irqsave(hba->host->host_lock, flags);
  2354. if (ret)
  2355. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  2356. ufshcd_clear_eh_in_progress(hba);
  2357. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2358. if (ret)
  2359. dev_err(hba->dev, "%s: link recovery failed, err %d",
  2360. __func__, ret);
  2361. return ret;
  2362. }
  2363. static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
  2364. {
  2365. int ret;
  2366. struct uic_command uic_cmd = {0};
  2367. uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
  2368. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  2369. if (ret) {
  2370. dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
  2371. __func__, ret);
  2372. /*
  2373. * If link recovery fails then return error so that caller
  2374. * don't retry the hibern8 enter again.
  2375. */
  2376. if (ufshcd_link_recovery(hba))
  2377. ret = -ENOLINK;
  2378. }
  2379. return ret;
  2380. }
  2381. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
  2382. {
  2383. int ret = 0, retries;
  2384. for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
  2385. ret = __ufshcd_uic_hibern8_enter(hba);
  2386. if (!ret || ret == -ENOLINK)
  2387. goto out;
  2388. }
  2389. out:
  2390. return ret;
  2391. }
  2392. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
  2393. {
  2394. struct uic_command uic_cmd = {0};
  2395. int ret;
  2396. uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
  2397. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  2398. if (ret) {
  2399. dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
  2400. __func__, ret);
  2401. ret = ufshcd_link_recovery(hba);
  2402. }
  2403. return ret;
  2404. }
  2405. /**
  2406. * ufshcd_init_pwr_info - setting the POR (power on reset)
  2407. * values in hba power info
  2408. * @hba: per-adapter instance
  2409. */
  2410. static void ufshcd_init_pwr_info(struct ufs_hba *hba)
  2411. {
  2412. hba->pwr_info.gear_rx = UFS_PWM_G1;
  2413. hba->pwr_info.gear_tx = UFS_PWM_G1;
  2414. hba->pwr_info.lane_rx = 1;
  2415. hba->pwr_info.lane_tx = 1;
  2416. hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
  2417. hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
  2418. hba->pwr_info.hs_rate = 0;
  2419. }
  2420. /**
  2421. * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
  2422. * @hba: per-adapter instance
  2423. */
  2424. static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
  2425. {
  2426. struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
  2427. if (hba->max_pwr_info.is_valid)
  2428. return 0;
  2429. pwr_info->pwr_tx = FASTAUTO_MODE;
  2430. pwr_info->pwr_rx = FASTAUTO_MODE;
  2431. pwr_info->hs_rate = PA_HS_MODE_B;
  2432. /* Get the connected lane count */
  2433. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
  2434. &pwr_info->lane_rx);
  2435. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  2436. &pwr_info->lane_tx);
  2437. if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
  2438. dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
  2439. __func__,
  2440. pwr_info->lane_rx,
  2441. pwr_info->lane_tx);
  2442. return -EINVAL;
  2443. }
  2444. /*
  2445. * First, get the maximum gears of HS speed.
  2446. * If a zero value, it means there is no HSGEAR capability.
  2447. * Then, get the maximum gears of PWM speed.
  2448. */
  2449. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
  2450. if (!pwr_info->gear_rx) {
  2451. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  2452. &pwr_info->gear_rx);
  2453. if (!pwr_info->gear_rx) {
  2454. dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
  2455. __func__, pwr_info->gear_rx);
  2456. return -EINVAL;
  2457. }
  2458. pwr_info->pwr_rx = SLOWAUTO_MODE;
  2459. }
  2460. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
  2461. &pwr_info->gear_tx);
  2462. if (!pwr_info->gear_tx) {
  2463. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  2464. &pwr_info->gear_tx);
  2465. if (!pwr_info->gear_tx) {
  2466. dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
  2467. __func__, pwr_info->gear_tx);
  2468. return -EINVAL;
  2469. }
  2470. pwr_info->pwr_tx = SLOWAUTO_MODE;
  2471. }
  2472. hba->max_pwr_info.is_valid = true;
  2473. return 0;
  2474. }
  2475. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  2476. struct ufs_pa_layer_attr *pwr_mode)
  2477. {
  2478. int ret;
  2479. /* if already configured to the requested pwr_mode */
  2480. if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
  2481. pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
  2482. pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
  2483. pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
  2484. pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
  2485. pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
  2486. pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
  2487. dev_dbg(hba->dev, "%s: power already configured\n", __func__);
  2488. return 0;
  2489. }
  2490. /*
  2491. * Configure attributes for power mode change with below.
  2492. * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
  2493. * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
  2494. * - PA_HSSERIES
  2495. */
  2496. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
  2497. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
  2498. pwr_mode->lane_rx);
  2499. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  2500. pwr_mode->pwr_rx == FAST_MODE)
  2501. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
  2502. else
  2503. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
  2504. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
  2505. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
  2506. pwr_mode->lane_tx);
  2507. if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
  2508. pwr_mode->pwr_tx == FAST_MODE)
  2509. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
  2510. else
  2511. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
  2512. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  2513. pwr_mode->pwr_tx == FASTAUTO_MODE ||
  2514. pwr_mode->pwr_rx == FAST_MODE ||
  2515. pwr_mode->pwr_tx == FAST_MODE)
  2516. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
  2517. pwr_mode->hs_rate);
  2518. ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
  2519. | pwr_mode->pwr_tx);
  2520. if (ret) {
  2521. dev_err(hba->dev,
  2522. "%s: power mode change failed %d\n", __func__, ret);
  2523. } else {
  2524. ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
  2525. pwr_mode);
  2526. memcpy(&hba->pwr_info, pwr_mode,
  2527. sizeof(struct ufs_pa_layer_attr));
  2528. }
  2529. return ret;
  2530. }
  2531. /**
  2532. * ufshcd_config_pwr_mode - configure a new power mode
  2533. * @hba: per-adapter instance
  2534. * @desired_pwr_mode: desired power configuration
  2535. */
  2536. static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
  2537. struct ufs_pa_layer_attr *desired_pwr_mode)
  2538. {
  2539. struct ufs_pa_layer_attr final_params = { 0 };
  2540. int ret;
  2541. ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
  2542. desired_pwr_mode, &final_params);
  2543. if (ret)
  2544. memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
  2545. ret = ufshcd_change_power_mode(hba, &final_params);
  2546. return ret;
  2547. }
  2548. /**
  2549. * ufshcd_complete_dev_init() - checks device readiness
  2550. * hba: per-adapter instance
  2551. *
  2552. * Set fDeviceInit flag and poll until device toggles it.
  2553. */
  2554. static int ufshcd_complete_dev_init(struct ufs_hba *hba)
  2555. {
  2556. int i;
  2557. int err;
  2558. bool flag_res = 1;
  2559. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  2560. QUERY_FLAG_IDN_FDEVICEINIT, NULL);
  2561. if (err) {
  2562. dev_err(hba->dev,
  2563. "%s setting fDeviceInit flag failed with error %d\n",
  2564. __func__, err);
  2565. goto out;
  2566. }
  2567. /* poll for max. 1000 iterations for fDeviceInit flag to clear */
  2568. for (i = 0; i < 1000 && !err && flag_res; i++)
  2569. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  2570. QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
  2571. if (err)
  2572. dev_err(hba->dev,
  2573. "%s reading fDeviceInit flag failed with error %d\n",
  2574. __func__, err);
  2575. else if (flag_res)
  2576. dev_err(hba->dev,
  2577. "%s fDeviceInit was not cleared by the device\n",
  2578. __func__);
  2579. out:
  2580. return err;
  2581. }
  2582. /**
  2583. * ufshcd_make_hba_operational - Make UFS controller operational
  2584. * @hba: per adapter instance
  2585. *
  2586. * To bring UFS host controller to operational state,
  2587. * 1. Enable required interrupts
  2588. * 2. Configure interrupt aggregation
  2589. * 3. Program UTRL and UTMRL base address
  2590. * 4. Configure run-stop-registers
  2591. *
  2592. * Returns 0 on success, non-zero value on failure
  2593. */
  2594. static int ufshcd_make_hba_operational(struct ufs_hba *hba)
  2595. {
  2596. int err = 0;
  2597. u32 reg;
  2598. /* Enable required interrupts */
  2599. ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
  2600. /* Configure interrupt aggregation */
  2601. if (ufshcd_is_intr_aggr_allowed(hba))
  2602. ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
  2603. else
  2604. ufshcd_disable_intr_aggr(hba);
  2605. /* Configure UTRL and UTMRL base address registers */
  2606. ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
  2607. REG_UTP_TRANSFER_REQ_LIST_BASE_L);
  2608. ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
  2609. REG_UTP_TRANSFER_REQ_LIST_BASE_H);
  2610. ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
  2611. REG_UTP_TASK_REQ_LIST_BASE_L);
  2612. ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
  2613. REG_UTP_TASK_REQ_LIST_BASE_H);
  2614. /*
  2615. * Make sure base address and interrupt setup are updated before
  2616. * enabling the run/stop registers below.
  2617. */
  2618. wmb();
  2619. /*
  2620. * UCRDY, UTMRLDY and UTRLRDY bits must be 1
  2621. */
  2622. reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
  2623. if (!(ufshcd_get_lists_status(reg))) {
  2624. ufshcd_enable_run_stop_reg(hba);
  2625. } else {
  2626. dev_err(hba->dev,
  2627. "Host controller not ready to process requests");
  2628. err = -EIO;
  2629. goto out;
  2630. }
  2631. out:
  2632. return err;
  2633. }
  2634. /**
  2635. * ufshcd_hba_stop - Send controller to reset state
  2636. * @hba: per adapter instance
  2637. * @can_sleep: perform sleep or just spin
  2638. */
  2639. static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
  2640. {
  2641. int err;
  2642. ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
  2643. err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
  2644. CONTROLLER_ENABLE, CONTROLLER_DISABLE,
  2645. 10, 1, can_sleep);
  2646. if (err)
  2647. dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
  2648. }
  2649. /**
  2650. * ufshcd_hba_enable - initialize the controller
  2651. * @hba: per adapter instance
  2652. *
  2653. * The controller resets itself and controller firmware initialization
  2654. * sequence kicks off. When controller is ready it will set
  2655. * the Host Controller Enable bit to 1.
  2656. *
  2657. * Returns 0 on success, non-zero value on failure
  2658. */
  2659. static int ufshcd_hba_enable(struct ufs_hba *hba)
  2660. {
  2661. int retry;
  2662. /*
  2663. * msleep of 1 and 5 used in this function might result in msleep(20),
  2664. * but it was necessary to send the UFS FPGA to reset mode during
  2665. * development and testing of this driver. msleep can be changed to
  2666. * mdelay and retry count can be reduced based on the controller.
  2667. */
  2668. if (!ufshcd_is_hba_active(hba))
  2669. /* change controller state to "reset state" */
  2670. ufshcd_hba_stop(hba, true);
  2671. /* UniPro link is disabled at this point */
  2672. ufshcd_set_link_off(hba);
  2673. ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
  2674. /* start controller initialization sequence */
  2675. ufshcd_hba_start(hba);
  2676. /*
  2677. * To initialize a UFS host controller HCE bit must be set to 1.
  2678. * During initialization the HCE bit value changes from 1->0->1.
  2679. * When the host controller completes initialization sequence
  2680. * it sets the value of HCE bit to 1. The same HCE bit is read back
  2681. * to check if the controller has completed initialization sequence.
  2682. * So without this delay the value HCE = 1, set in the previous
  2683. * instruction might be read back.
  2684. * This delay can be changed based on the controller.
  2685. */
  2686. msleep(1);
  2687. /* wait for the host controller to complete initialization */
  2688. retry = 10;
  2689. while (ufshcd_is_hba_active(hba)) {
  2690. if (retry) {
  2691. retry--;
  2692. } else {
  2693. dev_err(hba->dev,
  2694. "Controller enable failed\n");
  2695. return -EIO;
  2696. }
  2697. msleep(5);
  2698. }
  2699. /* enable UIC related interrupts */
  2700. ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
  2701. ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
  2702. return 0;
  2703. }
  2704. static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
  2705. {
  2706. int tx_lanes, i, err = 0;
  2707. if (!peer)
  2708. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  2709. &tx_lanes);
  2710. else
  2711. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  2712. &tx_lanes);
  2713. for (i = 0; i < tx_lanes; i++) {
  2714. if (!peer)
  2715. err = ufshcd_dme_set(hba,
  2716. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  2717. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  2718. 0);
  2719. else
  2720. err = ufshcd_dme_peer_set(hba,
  2721. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  2722. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  2723. 0);
  2724. if (err) {
  2725. dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
  2726. __func__, peer, i, err);
  2727. break;
  2728. }
  2729. }
  2730. return err;
  2731. }
  2732. static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
  2733. {
  2734. return ufshcd_disable_tx_lcc(hba, true);
  2735. }
  2736. /**
  2737. * ufshcd_link_startup - Initialize unipro link startup
  2738. * @hba: per adapter instance
  2739. *
  2740. * Returns 0 for success, non-zero in case of failure
  2741. */
  2742. static int ufshcd_link_startup(struct ufs_hba *hba)
  2743. {
  2744. int ret;
  2745. int retries = DME_LINKSTARTUP_RETRIES;
  2746. bool link_startup_again = false;
  2747. /*
  2748. * If UFS device isn't active then we will have to issue link startup
  2749. * 2 times to make sure the device state move to active.
  2750. */
  2751. if (!ufshcd_is_ufs_dev_active(hba))
  2752. link_startup_again = true;
  2753. link_startup:
  2754. do {
  2755. ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
  2756. ret = ufshcd_dme_link_startup(hba);
  2757. /* check if device is detected by inter-connect layer */
  2758. if (!ret && !ufshcd_is_device_present(hba)) {
  2759. dev_err(hba->dev, "%s: Device not present\n", __func__);
  2760. ret = -ENXIO;
  2761. goto out;
  2762. }
  2763. /*
  2764. * DME link lost indication is only received when link is up,
  2765. * but we can't be sure if the link is up until link startup
  2766. * succeeds. So reset the local Uni-Pro and try again.
  2767. */
  2768. if (ret && ufshcd_hba_enable(hba))
  2769. goto out;
  2770. } while (ret && retries--);
  2771. if (ret)
  2772. /* failed to get the link up... retire */
  2773. goto out;
  2774. if (link_startup_again) {
  2775. link_startup_again = false;
  2776. retries = DME_LINKSTARTUP_RETRIES;
  2777. goto link_startup;
  2778. }
  2779. if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
  2780. ret = ufshcd_disable_device_tx_lcc(hba);
  2781. if (ret)
  2782. goto out;
  2783. }
  2784. /* Include any host controller configuration via UIC commands */
  2785. ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
  2786. if (ret)
  2787. goto out;
  2788. ret = ufshcd_make_hba_operational(hba);
  2789. out:
  2790. if (ret)
  2791. dev_err(hba->dev, "link startup failed %d\n", ret);
  2792. return ret;
  2793. }
  2794. /**
  2795. * ufshcd_verify_dev_init() - Verify device initialization
  2796. * @hba: per-adapter instance
  2797. *
  2798. * Send NOP OUT UPIU and wait for NOP IN response to check whether the
  2799. * device Transport Protocol (UTP) layer is ready after a reset.
  2800. * If the UTP layer at the device side is not initialized, it may
  2801. * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
  2802. * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
  2803. */
  2804. static int ufshcd_verify_dev_init(struct ufs_hba *hba)
  2805. {
  2806. int err = 0;
  2807. int retries;
  2808. ufshcd_hold(hba, false);
  2809. mutex_lock(&hba->dev_cmd.lock);
  2810. for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
  2811. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
  2812. NOP_OUT_TIMEOUT);
  2813. if (!err || err == -ETIMEDOUT)
  2814. break;
  2815. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  2816. }
  2817. mutex_unlock(&hba->dev_cmd.lock);
  2818. ufshcd_release(hba);
  2819. if (err)
  2820. dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
  2821. return err;
  2822. }
  2823. /**
  2824. * ufshcd_set_queue_depth - set lun queue depth
  2825. * @sdev: pointer to SCSI device
  2826. *
  2827. * Read bLUQueueDepth value and activate scsi tagged command
  2828. * queueing. For WLUN, queue depth is set to 1. For best-effort
  2829. * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
  2830. * value that host can queue.
  2831. */
  2832. static void ufshcd_set_queue_depth(struct scsi_device *sdev)
  2833. {
  2834. int ret = 0;
  2835. u8 lun_qdepth;
  2836. struct ufs_hba *hba;
  2837. hba = shost_priv(sdev->host);
  2838. lun_qdepth = hba->nutrs;
  2839. ret = ufshcd_read_unit_desc_param(hba,
  2840. ufshcd_scsi_to_upiu_lun(sdev->lun),
  2841. UNIT_DESC_PARAM_LU_Q_DEPTH,
  2842. &lun_qdepth,
  2843. sizeof(lun_qdepth));
  2844. /* Some WLUN doesn't support unit descriptor */
  2845. if (ret == -EOPNOTSUPP)
  2846. lun_qdepth = 1;
  2847. else if (!lun_qdepth)
  2848. /* eventually, we can figure out the real queue depth */
  2849. lun_qdepth = hba->nutrs;
  2850. else
  2851. lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
  2852. dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
  2853. __func__, lun_qdepth);
  2854. scsi_change_queue_depth(sdev, lun_qdepth);
  2855. }
  2856. /*
  2857. * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
  2858. * @hba: per-adapter instance
  2859. * @lun: UFS device lun id
  2860. * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
  2861. *
  2862. * Returns 0 in case of success and b_lu_write_protect status would be returned
  2863. * @b_lu_write_protect parameter.
  2864. * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
  2865. * Returns -EINVAL in case of invalid parameters passed to this function.
  2866. */
  2867. static int ufshcd_get_lu_wp(struct ufs_hba *hba,
  2868. u8 lun,
  2869. u8 *b_lu_write_protect)
  2870. {
  2871. int ret;
  2872. if (!b_lu_write_protect)
  2873. ret = -EINVAL;
  2874. /*
  2875. * According to UFS device spec, RPMB LU can't be write
  2876. * protected so skip reading bLUWriteProtect parameter for
  2877. * it. For other W-LUs, UNIT DESCRIPTOR is not available.
  2878. */
  2879. else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
  2880. ret = -ENOTSUPP;
  2881. else
  2882. ret = ufshcd_read_unit_desc_param(hba,
  2883. lun,
  2884. UNIT_DESC_PARAM_LU_WR_PROTECT,
  2885. b_lu_write_protect,
  2886. sizeof(*b_lu_write_protect));
  2887. return ret;
  2888. }
  2889. /**
  2890. * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
  2891. * status
  2892. * @hba: per-adapter instance
  2893. * @sdev: pointer to SCSI device
  2894. *
  2895. */
  2896. static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
  2897. struct scsi_device *sdev)
  2898. {
  2899. if (hba->dev_info.f_power_on_wp_en &&
  2900. !hba->dev_info.is_lu_power_on_wp) {
  2901. u8 b_lu_write_protect;
  2902. if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
  2903. &b_lu_write_protect) &&
  2904. (b_lu_write_protect == UFS_LU_POWER_ON_WP))
  2905. hba->dev_info.is_lu_power_on_wp = true;
  2906. }
  2907. }
  2908. /**
  2909. * ufshcd_slave_alloc - handle initial SCSI device configurations
  2910. * @sdev: pointer to SCSI device
  2911. *
  2912. * Returns success
  2913. */
  2914. static int ufshcd_slave_alloc(struct scsi_device *sdev)
  2915. {
  2916. struct ufs_hba *hba;
  2917. hba = shost_priv(sdev->host);
  2918. /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
  2919. sdev->use_10_for_ms = 1;
  2920. /* allow SCSI layer to restart the device in case of errors */
  2921. sdev->allow_restart = 1;
  2922. /* REPORT SUPPORTED OPERATION CODES is not supported */
  2923. sdev->no_report_opcodes = 1;
  2924. ufshcd_set_queue_depth(sdev);
  2925. ufshcd_get_lu_power_on_wp_status(hba, sdev);
  2926. return 0;
  2927. }
  2928. /**
  2929. * ufshcd_change_queue_depth - change queue depth
  2930. * @sdev: pointer to SCSI device
  2931. * @depth: required depth to set
  2932. *
  2933. * Change queue depth and make sure the max. limits are not crossed.
  2934. */
  2935. static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
  2936. {
  2937. struct ufs_hba *hba = shost_priv(sdev->host);
  2938. if (depth > hba->nutrs)
  2939. depth = hba->nutrs;
  2940. return scsi_change_queue_depth(sdev, depth);
  2941. }
  2942. /**
  2943. * ufshcd_slave_configure - adjust SCSI device configurations
  2944. * @sdev: pointer to SCSI device
  2945. */
  2946. static int ufshcd_slave_configure(struct scsi_device *sdev)
  2947. {
  2948. struct request_queue *q = sdev->request_queue;
  2949. blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
  2950. blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
  2951. return 0;
  2952. }
  2953. /**
  2954. * ufshcd_slave_destroy - remove SCSI device configurations
  2955. * @sdev: pointer to SCSI device
  2956. */
  2957. static void ufshcd_slave_destroy(struct scsi_device *sdev)
  2958. {
  2959. struct ufs_hba *hba;
  2960. hba = shost_priv(sdev->host);
  2961. /* Drop the reference as it won't be needed anymore */
  2962. if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
  2963. unsigned long flags;
  2964. spin_lock_irqsave(hba->host->host_lock, flags);
  2965. hba->sdev_ufs_device = NULL;
  2966. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2967. }
  2968. }
  2969. /**
  2970. * ufshcd_task_req_compl - handle task management request completion
  2971. * @hba: per adapter instance
  2972. * @index: index of the completed request
  2973. * @resp: task management service response
  2974. *
  2975. * Returns non-zero value on error, zero on success
  2976. */
  2977. static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
  2978. {
  2979. struct utp_task_req_desc *task_req_descp;
  2980. struct utp_upiu_task_rsp *task_rsp_upiup;
  2981. unsigned long flags;
  2982. int ocs_value;
  2983. int task_result;
  2984. spin_lock_irqsave(hba->host->host_lock, flags);
  2985. /* Clear completed tasks from outstanding_tasks */
  2986. __clear_bit(index, &hba->outstanding_tasks);
  2987. task_req_descp = hba->utmrdl_base_addr;
  2988. ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
  2989. if (ocs_value == OCS_SUCCESS) {
  2990. task_rsp_upiup = (struct utp_upiu_task_rsp *)
  2991. task_req_descp[index].task_rsp_upiu;
  2992. task_result = be32_to_cpu(task_rsp_upiup->output_param1);
  2993. task_result = task_result & MASK_TM_SERVICE_RESP;
  2994. if (resp)
  2995. *resp = (u8)task_result;
  2996. } else {
  2997. dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
  2998. __func__, ocs_value);
  2999. }
  3000. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3001. return ocs_value;
  3002. }
  3003. /**
  3004. * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
  3005. * @lrb: pointer to local reference block of completed command
  3006. * @scsi_status: SCSI command status
  3007. *
  3008. * Returns value base on SCSI command status
  3009. */
  3010. static inline int
  3011. ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
  3012. {
  3013. int result = 0;
  3014. switch (scsi_status) {
  3015. case SAM_STAT_CHECK_CONDITION:
  3016. ufshcd_copy_sense_data(lrbp);
  3017. case SAM_STAT_GOOD:
  3018. result |= DID_OK << 16 |
  3019. COMMAND_COMPLETE << 8 |
  3020. scsi_status;
  3021. break;
  3022. case SAM_STAT_TASK_SET_FULL:
  3023. case SAM_STAT_BUSY:
  3024. case SAM_STAT_TASK_ABORTED:
  3025. ufshcd_copy_sense_data(lrbp);
  3026. result |= scsi_status;
  3027. break;
  3028. default:
  3029. result |= DID_ERROR << 16;
  3030. break;
  3031. } /* end of switch */
  3032. return result;
  3033. }
  3034. /**
  3035. * ufshcd_transfer_rsp_status - Get overall status of the response
  3036. * @hba: per adapter instance
  3037. * @lrb: pointer to local reference block of completed command
  3038. *
  3039. * Returns result of the command to notify SCSI midlayer
  3040. */
  3041. static inline int
  3042. ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  3043. {
  3044. int result = 0;
  3045. int scsi_status;
  3046. int ocs;
  3047. /* overall command status of utrd */
  3048. ocs = ufshcd_get_tr_ocs(lrbp);
  3049. switch (ocs) {
  3050. case OCS_SUCCESS:
  3051. result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  3052. switch (result) {
  3053. case UPIU_TRANSACTION_RESPONSE:
  3054. /*
  3055. * get the response UPIU result to extract
  3056. * the SCSI command status
  3057. */
  3058. result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
  3059. /*
  3060. * get the result based on SCSI status response
  3061. * to notify the SCSI midlayer of the command status
  3062. */
  3063. scsi_status = result & MASK_SCSI_STATUS;
  3064. result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
  3065. /*
  3066. * Currently we are only supporting BKOPs exception
  3067. * events hence we can ignore BKOPs exception event
  3068. * during power management callbacks. BKOPs exception
  3069. * event is not expected to be raised in runtime suspend
  3070. * callback as it allows the urgent bkops.
  3071. * During system suspend, we are anyway forcefully
  3072. * disabling the bkops and if urgent bkops is needed
  3073. * it will be enabled on system resume. Long term
  3074. * solution could be to abort the system suspend if
  3075. * UFS device needs urgent BKOPs.
  3076. */
  3077. if (!hba->pm_op_in_progress &&
  3078. ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
  3079. schedule_work(&hba->eeh_work);
  3080. break;
  3081. case UPIU_TRANSACTION_REJECT_UPIU:
  3082. /* TODO: handle Reject UPIU Response */
  3083. result = DID_ERROR << 16;
  3084. dev_err(hba->dev,
  3085. "Reject UPIU not fully implemented\n");
  3086. break;
  3087. default:
  3088. result = DID_ERROR << 16;
  3089. dev_err(hba->dev,
  3090. "Unexpected request response code = %x\n",
  3091. result);
  3092. break;
  3093. }
  3094. break;
  3095. case OCS_ABORTED:
  3096. result |= DID_ABORT << 16;
  3097. break;
  3098. case OCS_INVALID_COMMAND_STATUS:
  3099. result |= DID_REQUEUE << 16;
  3100. break;
  3101. case OCS_INVALID_CMD_TABLE_ATTR:
  3102. case OCS_INVALID_PRDT_ATTR:
  3103. case OCS_MISMATCH_DATA_BUF_SIZE:
  3104. case OCS_MISMATCH_RESP_UPIU_SIZE:
  3105. case OCS_PEER_COMM_FAILURE:
  3106. case OCS_FATAL_ERROR:
  3107. default:
  3108. result |= DID_ERROR << 16;
  3109. dev_err(hba->dev,
  3110. "OCS error from controller = %x\n", ocs);
  3111. break;
  3112. } /* end of switch */
  3113. return result;
  3114. }
  3115. /**
  3116. * ufshcd_uic_cmd_compl - handle completion of uic command
  3117. * @hba: per adapter instance
  3118. * @intr_status: interrupt status generated by the controller
  3119. */
  3120. static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
  3121. {
  3122. if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
  3123. hba->active_uic_cmd->argument2 |=
  3124. ufshcd_get_uic_cmd_result(hba);
  3125. hba->active_uic_cmd->argument3 =
  3126. ufshcd_get_dme_attr_val(hba);
  3127. complete(&hba->active_uic_cmd->done);
  3128. }
  3129. if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
  3130. complete(hba->uic_async_done);
  3131. }
  3132. /**
  3133. * __ufshcd_transfer_req_compl - handle SCSI and query command completion
  3134. * @hba: per adapter instance
  3135. * @completed_reqs: requests to complete
  3136. */
  3137. static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
  3138. unsigned long completed_reqs)
  3139. {
  3140. struct ufshcd_lrb *lrbp;
  3141. struct scsi_cmnd *cmd;
  3142. int result;
  3143. int index;
  3144. for_each_set_bit(index, &completed_reqs, hba->nutrs) {
  3145. lrbp = &hba->lrb[index];
  3146. cmd = lrbp->cmd;
  3147. if (cmd) {
  3148. result = ufshcd_transfer_rsp_status(hba, lrbp);
  3149. scsi_dma_unmap(cmd);
  3150. cmd->result = result;
  3151. /* Mark completed command as NULL in LRB */
  3152. lrbp->cmd = NULL;
  3153. clear_bit_unlock(index, &hba->lrb_in_use);
  3154. /* Do not touch lrbp after scsi done */
  3155. cmd->scsi_done(cmd);
  3156. __ufshcd_release(hba);
  3157. } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
  3158. lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
  3159. if (hba->dev_cmd.complete)
  3160. complete(hba->dev_cmd.complete);
  3161. }
  3162. }
  3163. /* clear corresponding bits of completed commands */
  3164. hba->outstanding_reqs ^= completed_reqs;
  3165. ufshcd_clk_scaling_update_busy(hba);
  3166. /* we might have free'd some tags above */
  3167. wake_up(&hba->dev_cmd.tag_wq);
  3168. }
  3169. /**
  3170. * ufshcd_transfer_req_compl - handle SCSI and query command completion
  3171. * @hba: per adapter instance
  3172. */
  3173. static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
  3174. {
  3175. unsigned long completed_reqs;
  3176. u32 tr_doorbell;
  3177. /* Resetting interrupt aggregation counters first and reading the
  3178. * DOOR_BELL afterward allows us to handle all the completed requests.
  3179. * In order to prevent other interrupts starvation the DB is read once
  3180. * after reset. The down side of this solution is the possibility of
  3181. * false interrupt if device completes another request after resetting
  3182. * aggregation and before reading the DB.
  3183. */
  3184. if (ufshcd_is_intr_aggr_allowed(hba))
  3185. ufshcd_reset_intr_aggr(hba);
  3186. tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  3187. completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
  3188. __ufshcd_transfer_req_compl(hba, completed_reqs);
  3189. }
  3190. /**
  3191. * ufshcd_disable_ee - disable exception event
  3192. * @hba: per-adapter instance
  3193. * @mask: exception event to disable
  3194. *
  3195. * Disables exception event in the device so that the EVENT_ALERT
  3196. * bit is not set.
  3197. *
  3198. * Returns zero on success, non-zero error value on failure.
  3199. */
  3200. static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
  3201. {
  3202. int err = 0;
  3203. u32 val;
  3204. if (!(hba->ee_ctrl_mask & mask))
  3205. goto out;
  3206. val = hba->ee_ctrl_mask & ~mask;
  3207. val &= 0xFFFF; /* 2 bytes */
  3208. err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  3209. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  3210. if (!err)
  3211. hba->ee_ctrl_mask &= ~mask;
  3212. out:
  3213. return err;
  3214. }
  3215. /**
  3216. * ufshcd_enable_ee - enable exception event
  3217. * @hba: per-adapter instance
  3218. * @mask: exception event to enable
  3219. *
  3220. * Enable corresponding exception event in the device to allow
  3221. * device to alert host in critical scenarios.
  3222. *
  3223. * Returns zero on success, non-zero error value on failure.
  3224. */
  3225. static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
  3226. {
  3227. int err = 0;
  3228. u32 val;
  3229. if (hba->ee_ctrl_mask & mask)
  3230. goto out;
  3231. val = hba->ee_ctrl_mask | mask;
  3232. val &= 0xFFFF; /* 2 bytes */
  3233. err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  3234. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  3235. if (!err)
  3236. hba->ee_ctrl_mask |= mask;
  3237. out:
  3238. return err;
  3239. }
  3240. /**
  3241. * ufshcd_enable_auto_bkops - Allow device managed BKOPS
  3242. * @hba: per-adapter instance
  3243. *
  3244. * Allow device to manage background operations on its own. Enabling
  3245. * this might lead to inconsistent latencies during normal data transfers
  3246. * as the device is allowed to manage its own way of handling background
  3247. * operations.
  3248. *
  3249. * Returns zero on success, non-zero on failure.
  3250. */
  3251. static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
  3252. {
  3253. int err = 0;
  3254. if (hba->auto_bkops_enabled)
  3255. goto out;
  3256. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  3257. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  3258. if (err) {
  3259. dev_err(hba->dev, "%s: failed to enable bkops %d\n",
  3260. __func__, err);
  3261. goto out;
  3262. }
  3263. hba->auto_bkops_enabled = true;
  3264. /* No need of URGENT_BKOPS exception from the device */
  3265. err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  3266. if (err)
  3267. dev_err(hba->dev, "%s: failed to disable exception event %d\n",
  3268. __func__, err);
  3269. out:
  3270. return err;
  3271. }
  3272. /**
  3273. * ufshcd_disable_auto_bkops - block device in doing background operations
  3274. * @hba: per-adapter instance
  3275. *
  3276. * Disabling background operations improves command response latency but
  3277. * has drawback of device moving into critical state where the device is
  3278. * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
  3279. * host is idle so that BKOPS are managed effectively without any negative
  3280. * impacts.
  3281. *
  3282. * Returns zero on success, non-zero on failure.
  3283. */
  3284. static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
  3285. {
  3286. int err = 0;
  3287. if (!hba->auto_bkops_enabled)
  3288. goto out;
  3289. /*
  3290. * If host assisted BKOPs is to be enabled, make sure
  3291. * urgent bkops exception is allowed.
  3292. */
  3293. err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
  3294. if (err) {
  3295. dev_err(hba->dev, "%s: failed to enable exception event %d\n",
  3296. __func__, err);
  3297. goto out;
  3298. }
  3299. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
  3300. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  3301. if (err) {
  3302. dev_err(hba->dev, "%s: failed to disable bkops %d\n",
  3303. __func__, err);
  3304. ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  3305. goto out;
  3306. }
  3307. hba->auto_bkops_enabled = false;
  3308. out:
  3309. return err;
  3310. }
  3311. /**
  3312. * ufshcd_force_reset_auto_bkops - force enable of auto bkops
  3313. * @hba: per adapter instance
  3314. *
  3315. * After a device reset the device may toggle the BKOPS_EN flag
  3316. * to default value. The s/w tracking variables should be updated
  3317. * as well. Do this by forcing enable of auto bkops.
  3318. */
  3319. static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
  3320. {
  3321. hba->auto_bkops_enabled = false;
  3322. hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
  3323. ufshcd_enable_auto_bkops(hba);
  3324. }
  3325. static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
  3326. {
  3327. return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  3328. QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
  3329. }
  3330. /**
  3331. * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
  3332. * @hba: per-adapter instance
  3333. * @status: bkops_status value
  3334. *
  3335. * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
  3336. * flag in the device to permit background operations if the device
  3337. * bkops_status is greater than or equal to "status" argument passed to
  3338. * this function, disable otherwise.
  3339. *
  3340. * Returns 0 for success, non-zero in case of failure.
  3341. *
  3342. * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
  3343. * to know whether auto bkops is enabled or disabled after this function
  3344. * returns control to it.
  3345. */
  3346. static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
  3347. enum bkops_status status)
  3348. {
  3349. int err;
  3350. u32 curr_status = 0;
  3351. err = ufshcd_get_bkops_status(hba, &curr_status);
  3352. if (err) {
  3353. dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
  3354. __func__, err);
  3355. goto out;
  3356. } else if (curr_status > BKOPS_STATUS_MAX) {
  3357. dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
  3358. __func__, curr_status);
  3359. err = -EINVAL;
  3360. goto out;
  3361. }
  3362. if (curr_status >= status)
  3363. err = ufshcd_enable_auto_bkops(hba);
  3364. else
  3365. err = ufshcd_disable_auto_bkops(hba);
  3366. out:
  3367. return err;
  3368. }
  3369. /**
  3370. * ufshcd_urgent_bkops - handle urgent bkops exception event
  3371. * @hba: per-adapter instance
  3372. *
  3373. * Enable fBackgroundOpsEn flag in the device to permit background
  3374. * operations.
  3375. *
  3376. * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
  3377. * and negative error value for any other failure.
  3378. */
  3379. static int ufshcd_urgent_bkops(struct ufs_hba *hba)
  3380. {
  3381. return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
  3382. }
  3383. static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
  3384. {
  3385. return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  3386. QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
  3387. }
  3388. static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
  3389. {
  3390. int err;
  3391. u32 curr_status = 0;
  3392. if (hba->is_urgent_bkops_lvl_checked)
  3393. goto enable_auto_bkops;
  3394. err = ufshcd_get_bkops_status(hba, &curr_status);
  3395. if (err) {
  3396. dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
  3397. __func__, err);
  3398. goto out;
  3399. }
  3400. /*
  3401. * We are seeing that some devices are raising the urgent bkops
  3402. * exception events even when BKOPS status doesn't indicate performace
  3403. * impacted or critical. Handle these device by determining their urgent
  3404. * bkops status at runtime.
  3405. */
  3406. if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
  3407. dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
  3408. __func__, curr_status);
  3409. /* update the current status as the urgent bkops level */
  3410. hba->urgent_bkops_lvl = curr_status;
  3411. hba->is_urgent_bkops_lvl_checked = true;
  3412. }
  3413. enable_auto_bkops:
  3414. err = ufshcd_enable_auto_bkops(hba);
  3415. out:
  3416. if (err < 0)
  3417. dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
  3418. __func__, err);
  3419. }
  3420. /**
  3421. * ufshcd_exception_event_handler - handle exceptions raised by device
  3422. * @work: pointer to work data
  3423. *
  3424. * Read bExceptionEventStatus attribute from the device and handle the
  3425. * exception event accordingly.
  3426. */
  3427. static void ufshcd_exception_event_handler(struct work_struct *work)
  3428. {
  3429. struct ufs_hba *hba;
  3430. int err;
  3431. u32 status = 0;
  3432. hba = container_of(work, struct ufs_hba, eeh_work);
  3433. pm_runtime_get_sync(hba->dev);
  3434. err = ufshcd_get_ee_status(hba, &status);
  3435. if (err) {
  3436. dev_err(hba->dev, "%s: failed to get exception status %d\n",
  3437. __func__, err);
  3438. goto out;
  3439. }
  3440. status &= hba->ee_ctrl_mask;
  3441. if (status & MASK_EE_URGENT_BKOPS)
  3442. ufshcd_bkops_exception_event_handler(hba);
  3443. out:
  3444. pm_runtime_put_sync(hba->dev);
  3445. return;
  3446. }
  3447. /* Complete requests that have door-bell cleared */
  3448. static void ufshcd_complete_requests(struct ufs_hba *hba)
  3449. {
  3450. ufshcd_transfer_req_compl(hba);
  3451. ufshcd_tmc_handler(hba);
  3452. }
  3453. /**
  3454. * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
  3455. * to recover from the DL NAC errors or not.
  3456. * @hba: per-adapter instance
  3457. *
  3458. * Returns true if error handling is required, false otherwise
  3459. */
  3460. static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
  3461. {
  3462. unsigned long flags;
  3463. bool err_handling = true;
  3464. spin_lock_irqsave(hba->host->host_lock, flags);
  3465. /*
  3466. * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
  3467. * device fatal error and/or DL NAC & REPLAY timeout errors.
  3468. */
  3469. if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
  3470. goto out;
  3471. if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
  3472. ((hba->saved_err & UIC_ERROR) &&
  3473. (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
  3474. goto out;
  3475. if ((hba->saved_err & UIC_ERROR) &&
  3476. (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
  3477. int err;
  3478. /*
  3479. * wait for 50ms to see if we can get any other errors or not.
  3480. */
  3481. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3482. msleep(50);
  3483. spin_lock_irqsave(hba->host->host_lock, flags);
  3484. /*
  3485. * now check if we have got any other severe errors other than
  3486. * DL NAC error?
  3487. */
  3488. if ((hba->saved_err & INT_FATAL_ERRORS) ||
  3489. ((hba->saved_err & UIC_ERROR) &&
  3490. (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
  3491. goto out;
  3492. /*
  3493. * As DL NAC is the only error received so far, send out NOP
  3494. * command to confirm if link is still active or not.
  3495. * - If we don't get any response then do error recovery.
  3496. * - If we get response then clear the DL NAC error bit.
  3497. */
  3498. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3499. err = ufshcd_verify_dev_init(hba);
  3500. spin_lock_irqsave(hba->host->host_lock, flags);
  3501. if (err)
  3502. goto out;
  3503. /* Link seems to be alive hence ignore the DL NAC errors */
  3504. if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
  3505. hba->saved_err &= ~UIC_ERROR;
  3506. /* clear NAC error */
  3507. hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
  3508. if (!hba->saved_uic_err) {
  3509. err_handling = false;
  3510. goto out;
  3511. }
  3512. }
  3513. out:
  3514. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3515. return err_handling;
  3516. }
  3517. /**
  3518. * ufshcd_err_handler - handle UFS errors that require s/w attention
  3519. * @work: pointer to work structure
  3520. */
  3521. static void ufshcd_err_handler(struct work_struct *work)
  3522. {
  3523. struct ufs_hba *hba;
  3524. unsigned long flags;
  3525. u32 err_xfer = 0;
  3526. u32 err_tm = 0;
  3527. int err = 0;
  3528. int tag;
  3529. bool needs_reset = false;
  3530. hba = container_of(work, struct ufs_hba, eh_work);
  3531. pm_runtime_get_sync(hba->dev);
  3532. ufshcd_hold(hba, false);
  3533. spin_lock_irqsave(hba->host->host_lock, flags);
  3534. if (hba->ufshcd_state == UFSHCD_STATE_RESET)
  3535. goto out;
  3536. hba->ufshcd_state = UFSHCD_STATE_RESET;
  3537. ufshcd_set_eh_in_progress(hba);
  3538. /* Complete requests that have door-bell cleared by h/w */
  3539. ufshcd_complete_requests(hba);
  3540. if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
  3541. bool ret;
  3542. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3543. /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
  3544. ret = ufshcd_quirk_dl_nac_errors(hba);
  3545. spin_lock_irqsave(hba->host->host_lock, flags);
  3546. if (!ret)
  3547. goto skip_err_handling;
  3548. }
  3549. if ((hba->saved_err & INT_FATAL_ERRORS) ||
  3550. ((hba->saved_err & UIC_ERROR) &&
  3551. (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
  3552. UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
  3553. UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
  3554. needs_reset = true;
  3555. /*
  3556. * if host reset is required then skip clearing the pending
  3557. * transfers forcefully because they will automatically get
  3558. * cleared after link startup.
  3559. */
  3560. if (needs_reset)
  3561. goto skip_pending_xfer_clear;
  3562. /* release lock as clear command might sleep */
  3563. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3564. /* Clear pending transfer requests */
  3565. for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
  3566. if (ufshcd_clear_cmd(hba, tag)) {
  3567. err_xfer = true;
  3568. goto lock_skip_pending_xfer_clear;
  3569. }
  3570. }
  3571. /* Clear pending task management requests */
  3572. for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
  3573. if (ufshcd_clear_tm_cmd(hba, tag)) {
  3574. err_tm = true;
  3575. goto lock_skip_pending_xfer_clear;
  3576. }
  3577. }
  3578. lock_skip_pending_xfer_clear:
  3579. spin_lock_irqsave(hba->host->host_lock, flags);
  3580. /* Complete the requests that are cleared by s/w */
  3581. ufshcd_complete_requests(hba);
  3582. if (err_xfer || err_tm)
  3583. needs_reset = true;
  3584. skip_pending_xfer_clear:
  3585. /* Fatal errors need reset */
  3586. if (needs_reset) {
  3587. unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
  3588. /*
  3589. * ufshcd_reset_and_restore() does the link reinitialization
  3590. * which will need atleast one empty doorbell slot to send the
  3591. * device management commands (NOP and query commands).
  3592. * If there is no slot empty at this moment then free up last
  3593. * slot forcefully.
  3594. */
  3595. if (hba->outstanding_reqs == max_doorbells)
  3596. __ufshcd_transfer_req_compl(hba,
  3597. (1UL << (hba->nutrs - 1)));
  3598. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3599. err = ufshcd_reset_and_restore(hba);
  3600. spin_lock_irqsave(hba->host->host_lock, flags);
  3601. if (err) {
  3602. dev_err(hba->dev, "%s: reset and restore failed\n",
  3603. __func__);
  3604. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  3605. }
  3606. /*
  3607. * Inform scsi mid-layer that we did reset and allow to handle
  3608. * Unit Attention properly.
  3609. */
  3610. scsi_report_bus_reset(hba->host, 0);
  3611. hba->saved_err = 0;
  3612. hba->saved_uic_err = 0;
  3613. }
  3614. skip_err_handling:
  3615. if (!needs_reset) {
  3616. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  3617. if (hba->saved_err || hba->saved_uic_err)
  3618. dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
  3619. __func__, hba->saved_err, hba->saved_uic_err);
  3620. }
  3621. ufshcd_clear_eh_in_progress(hba);
  3622. out:
  3623. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3624. scsi_unblock_requests(hba->host);
  3625. ufshcd_release(hba);
  3626. pm_runtime_put_sync(hba->dev);
  3627. }
  3628. /**
  3629. * ufshcd_update_uic_error - check and set fatal UIC error flags.
  3630. * @hba: per-adapter instance
  3631. */
  3632. static void ufshcd_update_uic_error(struct ufs_hba *hba)
  3633. {
  3634. u32 reg;
  3635. /* PA_INIT_ERROR is fatal and needs UIC reset */
  3636. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
  3637. if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
  3638. hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
  3639. else if (hba->dev_quirks &
  3640. UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
  3641. if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
  3642. hba->uic_error |=
  3643. UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
  3644. else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
  3645. hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
  3646. }
  3647. /* UIC NL/TL/DME errors needs software retry */
  3648. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
  3649. if (reg)
  3650. hba->uic_error |= UFSHCD_UIC_NL_ERROR;
  3651. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
  3652. if (reg)
  3653. hba->uic_error |= UFSHCD_UIC_TL_ERROR;
  3654. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
  3655. if (reg)
  3656. hba->uic_error |= UFSHCD_UIC_DME_ERROR;
  3657. dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
  3658. __func__, hba->uic_error);
  3659. }
  3660. /**
  3661. * ufshcd_check_errors - Check for errors that need s/w attention
  3662. * @hba: per-adapter instance
  3663. */
  3664. static void ufshcd_check_errors(struct ufs_hba *hba)
  3665. {
  3666. bool queue_eh_work = false;
  3667. if (hba->errors & INT_FATAL_ERRORS)
  3668. queue_eh_work = true;
  3669. if (hba->errors & UIC_ERROR) {
  3670. hba->uic_error = 0;
  3671. ufshcd_update_uic_error(hba);
  3672. if (hba->uic_error)
  3673. queue_eh_work = true;
  3674. }
  3675. if (queue_eh_work) {
  3676. /*
  3677. * update the transfer error masks to sticky bits, let's do this
  3678. * irrespective of current ufshcd_state.
  3679. */
  3680. hba->saved_err |= hba->errors;
  3681. hba->saved_uic_err |= hba->uic_error;
  3682. /* handle fatal errors only when link is functional */
  3683. if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
  3684. /* block commands from scsi mid-layer */
  3685. scsi_block_requests(hba->host);
  3686. hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
  3687. schedule_work(&hba->eh_work);
  3688. }
  3689. }
  3690. /*
  3691. * if (!queue_eh_work) -
  3692. * Other errors are either non-fatal where host recovers
  3693. * itself without s/w intervention or errors that will be
  3694. * handled by the SCSI core layer.
  3695. */
  3696. }
  3697. /**
  3698. * ufshcd_tmc_handler - handle task management function completion
  3699. * @hba: per adapter instance
  3700. */
  3701. static void ufshcd_tmc_handler(struct ufs_hba *hba)
  3702. {
  3703. u32 tm_doorbell;
  3704. tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
  3705. hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
  3706. wake_up(&hba->tm_wq);
  3707. }
  3708. /**
  3709. * ufshcd_sl_intr - Interrupt service routine
  3710. * @hba: per adapter instance
  3711. * @intr_status: contains interrupts generated by the controller
  3712. */
  3713. static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
  3714. {
  3715. hba->errors = UFSHCD_ERROR_MASK & intr_status;
  3716. if (hba->errors)
  3717. ufshcd_check_errors(hba);
  3718. if (intr_status & UFSHCD_UIC_MASK)
  3719. ufshcd_uic_cmd_compl(hba, intr_status);
  3720. if (intr_status & UTP_TASK_REQ_COMPL)
  3721. ufshcd_tmc_handler(hba);
  3722. if (intr_status & UTP_TRANSFER_REQ_COMPL)
  3723. ufshcd_transfer_req_compl(hba);
  3724. }
  3725. /**
  3726. * ufshcd_intr - Main interrupt service routine
  3727. * @irq: irq number
  3728. * @__hba: pointer to adapter instance
  3729. *
  3730. * Returns IRQ_HANDLED - If interrupt is valid
  3731. * IRQ_NONE - If invalid interrupt
  3732. */
  3733. static irqreturn_t ufshcd_intr(int irq, void *__hba)
  3734. {
  3735. u32 intr_status, enabled_intr_status;
  3736. irqreturn_t retval = IRQ_NONE;
  3737. struct ufs_hba *hba = __hba;
  3738. spin_lock(hba->host->host_lock);
  3739. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  3740. enabled_intr_status =
  3741. intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  3742. if (intr_status)
  3743. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  3744. if (enabled_intr_status) {
  3745. ufshcd_sl_intr(hba, enabled_intr_status);
  3746. retval = IRQ_HANDLED;
  3747. }
  3748. spin_unlock(hba->host->host_lock);
  3749. return retval;
  3750. }
  3751. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
  3752. {
  3753. int err = 0;
  3754. u32 mask = 1 << tag;
  3755. unsigned long flags;
  3756. if (!test_bit(tag, &hba->outstanding_tasks))
  3757. goto out;
  3758. spin_lock_irqsave(hba->host->host_lock, flags);
  3759. ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
  3760. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3761. /* poll for max. 1 sec to clear door bell register by h/w */
  3762. err = ufshcd_wait_for_register(hba,
  3763. REG_UTP_TASK_REQ_DOOR_BELL,
  3764. mask, 0, 1000, 1000, true);
  3765. out:
  3766. return err;
  3767. }
  3768. /**
  3769. * ufshcd_issue_tm_cmd - issues task management commands to controller
  3770. * @hba: per adapter instance
  3771. * @lun_id: LUN ID to which TM command is sent
  3772. * @task_id: task ID to which the TM command is applicable
  3773. * @tm_function: task management function opcode
  3774. * @tm_response: task management service response return value
  3775. *
  3776. * Returns non-zero value on error, zero on success.
  3777. */
  3778. static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
  3779. u8 tm_function, u8 *tm_response)
  3780. {
  3781. struct utp_task_req_desc *task_req_descp;
  3782. struct utp_upiu_task_req *task_req_upiup;
  3783. struct Scsi_Host *host;
  3784. unsigned long flags;
  3785. int free_slot;
  3786. int err;
  3787. int task_tag;
  3788. host = hba->host;
  3789. /*
  3790. * Get free slot, sleep if slots are unavailable.
  3791. * Even though we use wait_event() which sleeps indefinitely,
  3792. * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
  3793. */
  3794. wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
  3795. ufshcd_hold(hba, false);
  3796. spin_lock_irqsave(host->host_lock, flags);
  3797. task_req_descp = hba->utmrdl_base_addr;
  3798. task_req_descp += free_slot;
  3799. /* Configure task request descriptor */
  3800. task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
  3801. task_req_descp->header.dword_2 =
  3802. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  3803. /* Configure task request UPIU */
  3804. task_req_upiup =
  3805. (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
  3806. task_tag = hba->nutrs + free_slot;
  3807. task_req_upiup->header.dword_0 =
  3808. UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
  3809. lun_id, task_tag);
  3810. task_req_upiup->header.dword_1 =
  3811. UPIU_HEADER_DWORD(0, tm_function, 0, 0);
  3812. /*
  3813. * The host shall provide the same value for LUN field in the basic
  3814. * header and for Input Parameter.
  3815. */
  3816. task_req_upiup->input_param1 = cpu_to_be32(lun_id);
  3817. task_req_upiup->input_param2 = cpu_to_be32(task_id);
  3818. /* send command to the controller */
  3819. __set_bit(free_slot, &hba->outstanding_tasks);
  3820. /* Make sure descriptors are ready before ringing the task doorbell */
  3821. wmb();
  3822. ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
  3823. spin_unlock_irqrestore(host->host_lock, flags);
  3824. /* wait until the task management command is completed */
  3825. err = wait_event_timeout(hba->tm_wq,
  3826. test_bit(free_slot, &hba->tm_condition),
  3827. msecs_to_jiffies(TM_CMD_TIMEOUT));
  3828. if (!err) {
  3829. dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
  3830. __func__, tm_function);
  3831. if (ufshcd_clear_tm_cmd(hba, free_slot))
  3832. dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
  3833. __func__, free_slot);
  3834. err = -ETIMEDOUT;
  3835. } else {
  3836. err = ufshcd_task_req_compl(hba, free_slot, tm_response);
  3837. }
  3838. clear_bit(free_slot, &hba->tm_condition);
  3839. ufshcd_put_tm_slot(hba, free_slot);
  3840. wake_up(&hba->tm_tag_wq);
  3841. ufshcd_release(hba);
  3842. return err;
  3843. }
  3844. /**
  3845. * ufshcd_eh_device_reset_handler - device reset handler registered to
  3846. * scsi layer.
  3847. * @cmd: SCSI command pointer
  3848. *
  3849. * Returns SUCCESS/FAILED
  3850. */
  3851. static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
  3852. {
  3853. struct Scsi_Host *host;
  3854. struct ufs_hba *hba;
  3855. unsigned int tag;
  3856. u32 pos;
  3857. int err;
  3858. u8 resp = 0xF;
  3859. struct ufshcd_lrb *lrbp;
  3860. unsigned long flags;
  3861. host = cmd->device->host;
  3862. hba = shost_priv(host);
  3863. tag = cmd->request->tag;
  3864. lrbp = &hba->lrb[tag];
  3865. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
  3866. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  3867. if (!err)
  3868. err = resp;
  3869. goto out;
  3870. }
  3871. /* clear the commands that were pending for corresponding LUN */
  3872. for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
  3873. if (hba->lrb[pos].lun == lrbp->lun) {
  3874. err = ufshcd_clear_cmd(hba, pos);
  3875. if (err)
  3876. break;
  3877. }
  3878. }
  3879. spin_lock_irqsave(host->host_lock, flags);
  3880. ufshcd_transfer_req_compl(hba);
  3881. spin_unlock_irqrestore(host->host_lock, flags);
  3882. out:
  3883. if (!err) {
  3884. err = SUCCESS;
  3885. } else {
  3886. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  3887. err = FAILED;
  3888. }
  3889. return err;
  3890. }
  3891. /**
  3892. * ufshcd_abort - abort a specific command
  3893. * @cmd: SCSI command pointer
  3894. *
  3895. * Abort the pending command in device by sending UFS_ABORT_TASK task management
  3896. * command, and in host controller by clearing the door-bell register. There can
  3897. * be race between controller sending the command to the device while abort is
  3898. * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
  3899. * really issued and then try to abort it.
  3900. *
  3901. * Returns SUCCESS/FAILED
  3902. */
  3903. static int ufshcd_abort(struct scsi_cmnd *cmd)
  3904. {
  3905. struct Scsi_Host *host;
  3906. struct ufs_hba *hba;
  3907. unsigned long flags;
  3908. unsigned int tag;
  3909. int err = 0;
  3910. int poll_cnt;
  3911. u8 resp = 0xF;
  3912. struct ufshcd_lrb *lrbp;
  3913. u32 reg;
  3914. host = cmd->device->host;
  3915. hba = shost_priv(host);
  3916. tag = cmd->request->tag;
  3917. if (!ufshcd_valid_tag(hba, tag)) {
  3918. dev_err(hba->dev,
  3919. "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
  3920. __func__, tag, cmd, cmd->request);
  3921. BUG();
  3922. }
  3923. ufshcd_hold(hba, false);
  3924. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  3925. /* If command is already aborted/completed, return SUCCESS */
  3926. if (!(test_bit(tag, &hba->outstanding_reqs))) {
  3927. dev_err(hba->dev,
  3928. "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
  3929. __func__, tag, hba->outstanding_reqs, reg);
  3930. goto out;
  3931. }
  3932. if (!(reg & (1 << tag))) {
  3933. dev_err(hba->dev,
  3934. "%s: cmd was completed, but without a notifying intr, tag = %d",
  3935. __func__, tag);
  3936. }
  3937. lrbp = &hba->lrb[tag];
  3938. for (poll_cnt = 100; poll_cnt; poll_cnt--) {
  3939. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  3940. UFS_QUERY_TASK, &resp);
  3941. if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
  3942. /* cmd pending in the device */
  3943. break;
  3944. } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  3945. /*
  3946. * cmd not pending in the device, check if it is
  3947. * in transition.
  3948. */
  3949. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  3950. if (reg & (1 << tag)) {
  3951. /* sleep for max. 200us to stabilize */
  3952. usleep_range(100, 200);
  3953. continue;
  3954. }
  3955. /* command completed already */
  3956. goto out;
  3957. } else {
  3958. if (!err)
  3959. err = resp; /* service response error */
  3960. goto out;
  3961. }
  3962. }
  3963. if (!poll_cnt) {
  3964. err = -EBUSY;
  3965. goto out;
  3966. }
  3967. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  3968. UFS_ABORT_TASK, &resp);
  3969. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  3970. if (!err)
  3971. err = resp; /* service response error */
  3972. goto out;
  3973. }
  3974. err = ufshcd_clear_cmd(hba, tag);
  3975. if (err)
  3976. goto out;
  3977. scsi_dma_unmap(cmd);
  3978. spin_lock_irqsave(host->host_lock, flags);
  3979. ufshcd_outstanding_req_clear(hba, tag);
  3980. hba->lrb[tag].cmd = NULL;
  3981. spin_unlock_irqrestore(host->host_lock, flags);
  3982. clear_bit_unlock(tag, &hba->lrb_in_use);
  3983. wake_up(&hba->dev_cmd.tag_wq);
  3984. out:
  3985. if (!err) {
  3986. err = SUCCESS;
  3987. } else {
  3988. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  3989. err = FAILED;
  3990. }
  3991. /*
  3992. * This ufshcd_release() corresponds to the original scsi cmd that got
  3993. * aborted here (as we won't get any IRQ for it).
  3994. */
  3995. ufshcd_release(hba);
  3996. return err;
  3997. }
  3998. /**
  3999. * ufshcd_host_reset_and_restore - reset and restore host controller
  4000. * @hba: per-adapter instance
  4001. *
  4002. * Note that host controller reset may issue DME_RESET to
  4003. * local and remote (device) Uni-Pro stack and the attributes
  4004. * are reset to default state.
  4005. *
  4006. * Returns zero on success, non-zero on failure
  4007. */
  4008. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
  4009. {
  4010. int err;
  4011. unsigned long flags;
  4012. /* Reset the host controller */
  4013. spin_lock_irqsave(hba->host->host_lock, flags);
  4014. ufshcd_hba_stop(hba, false);
  4015. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4016. err = ufshcd_hba_enable(hba);
  4017. if (err)
  4018. goto out;
  4019. /* Establish the link again and restore the device */
  4020. err = ufshcd_probe_hba(hba);
  4021. if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
  4022. err = -EIO;
  4023. out:
  4024. if (err)
  4025. dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
  4026. return err;
  4027. }
  4028. /**
  4029. * ufshcd_reset_and_restore - reset and re-initialize host/device
  4030. * @hba: per-adapter instance
  4031. *
  4032. * Reset and recover device, host and re-establish link. This
  4033. * is helpful to recover the communication in fatal error conditions.
  4034. *
  4035. * Returns zero on success, non-zero on failure
  4036. */
  4037. static int ufshcd_reset_and_restore(struct ufs_hba *hba)
  4038. {
  4039. int err = 0;
  4040. unsigned long flags;
  4041. int retries = MAX_HOST_RESET_RETRIES;
  4042. do {
  4043. err = ufshcd_host_reset_and_restore(hba);
  4044. } while (err && --retries);
  4045. /*
  4046. * After reset the door-bell might be cleared, complete
  4047. * outstanding requests in s/w here.
  4048. */
  4049. spin_lock_irqsave(hba->host->host_lock, flags);
  4050. ufshcd_transfer_req_compl(hba);
  4051. ufshcd_tmc_handler(hba);
  4052. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4053. return err;
  4054. }
  4055. /**
  4056. * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
  4057. * @cmd - SCSI command pointer
  4058. *
  4059. * Returns SUCCESS/FAILED
  4060. */
  4061. static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
  4062. {
  4063. int err;
  4064. unsigned long flags;
  4065. struct ufs_hba *hba;
  4066. hba = shost_priv(cmd->device->host);
  4067. ufshcd_hold(hba, false);
  4068. /*
  4069. * Check if there is any race with fatal error handling.
  4070. * If so, wait for it to complete. Even though fatal error
  4071. * handling does reset and restore in some cases, don't assume
  4072. * anything out of it. We are just avoiding race here.
  4073. */
  4074. do {
  4075. spin_lock_irqsave(hba->host->host_lock, flags);
  4076. if (!(work_pending(&hba->eh_work) ||
  4077. hba->ufshcd_state == UFSHCD_STATE_RESET))
  4078. break;
  4079. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4080. dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
  4081. flush_work(&hba->eh_work);
  4082. } while (1);
  4083. hba->ufshcd_state = UFSHCD_STATE_RESET;
  4084. ufshcd_set_eh_in_progress(hba);
  4085. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4086. err = ufshcd_reset_and_restore(hba);
  4087. spin_lock_irqsave(hba->host->host_lock, flags);
  4088. if (!err) {
  4089. err = SUCCESS;
  4090. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  4091. } else {
  4092. err = FAILED;
  4093. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  4094. }
  4095. ufshcd_clear_eh_in_progress(hba);
  4096. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4097. ufshcd_release(hba);
  4098. return err;
  4099. }
  4100. /**
  4101. * ufshcd_get_max_icc_level - calculate the ICC level
  4102. * @sup_curr_uA: max. current supported by the regulator
  4103. * @start_scan: row at the desc table to start scan from
  4104. * @buff: power descriptor buffer
  4105. *
  4106. * Returns calculated max ICC level for specific regulator
  4107. */
  4108. static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
  4109. {
  4110. int i;
  4111. int curr_uA;
  4112. u16 data;
  4113. u16 unit;
  4114. for (i = start_scan; i >= 0; i--) {
  4115. data = be16_to_cpu(*((u16 *)(buff + 2*i)));
  4116. unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
  4117. ATTR_ICC_LVL_UNIT_OFFSET;
  4118. curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
  4119. switch (unit) {
  4120. case UFSHCD_NANO_AMP:
  4121. curr_uA = curr_uA / 1000;
  4122. break;
  4123. case UFSHCD_MILI_AMP:
  4124. curr_uA = curr_uA * 1000;
  4125. break;
  4126. case UFSHCD_AMP:
  4127. curr_uA = curr_uA * 1000 * 1000;
  4128. break;
  4129. case UFSHCD_MICRO_AMP:
  4130. default:
  4131. break;
  4132. }
  4133. if (sup_curr_uA >= curr_uA)
  4134. break;
  4135. }
  4136. if (i < 0) {
  4137. i = 0;
  4138. pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
  4139. }
  4140. return (u32)i;
  4141. }
  4142. /**
  4143. * ufshcd_calc_icc_level - calculate the max ICC level
  4144. * In case regulators are not initialized we'll return 0
  4145. * @hba: per-adapter instance
  4146. * @desc_buf: power descriptor buffer to extract ICC levels from.
  4147. * @len: length of desc_buff
  4148. *
  4149. * Returns calculated ICC level
  4150. */
  4151. static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
  4152. u8 *desc_buf, int len)
  4153. {
  4154. u32 icc_level = 0;
  4155. if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
  4156. !hba->vreg_info.vccq2) {
  4157. dev_err(hba->dev,
  4158. "%s: Regulator capability was not set, actvIccLevel=%d",
  4159. __func__, icc_level);
  4160. goto out;
  4161. }
  4162. if (hba->vreg_info.vcc)
  4163. icc_level = ufshcd_get_max_icc_level(
  4164. hba->vreg_info.vcc->max_uA,
  4165. POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
  4166. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
  4167. if (hba->vreg_info.vccq)
  4168. icc_level = ufshcd_get_max_icc_level(
  4169. hba->vreg_info.vccq->max_uA,
  4170. icc_level,
  4171. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
  4172. if (hba->vreg_info.vccq2)
  4173. icc_level = ufshcd_get_max_icc_level(
  4174. hba->vreg_info.vccq2->max_uA,
  4175. icc_level,
  4176. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
  4177. out:
  4178. return icc_level;
  4179. }
  4180. static void ufshcd_init_icc_levels(struct ufs_hba *hba)
  4181. {
  4182. int ret;
  4183. int buff_len = QUERY_DESC_POWER_MAX_SIZE;
  4184. u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
  4185. ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
  4186. if (ret) {
  4187. dev_err(hba->dev,
  4188. "%s: Failed reading power descriptor.len = %d ret = %d",
  4189. __func__, buff_len, ret);
  4190. return;
  4191. }
  4192. hba->init_prefetch_data.icc_level =
  4193. ufshcd_find_max_sup_active_icc_level(hba,
  4194. desc_buf, buff_len);
  4195. dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
  4196. __func__, hba->init_prefetch_data.icc_level);
  4197. ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  4198. QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
  4199. &hba->init_prefetch_data.icc_level);
  4200. if (ret)
  4201. dev_err(hba->dev,
  4202. "%s: Failed configuring bActiveICCLevel = %d ret = %d",
  4203. __func__, hba->init_prefetch_data.icc_level , ret);
  4204. }
  4205. /**
  4206. * ufshcd_scsi_add_wlus - Adds required W-LUs
  4207. * @hba: per-adapter instance
  4208. *
  4209. * UFS device specification requires the UFS devices to support 4 well known
  4210. * logical units:
  4211. * "REPORT_LUNS" (address: 01h)
  4212. * "UFS Device" (address: 50h)
  4213. * "RPMB" (address: 44h)
  4214. * "BOOT" (address: 30h)
  4215. * UFS device's power management needs to be controlled by "POWER CONDITION"
  4216. * field of SSU (START STOP UNIT) command. But this "power condition" field
  4217. * will take effect only when its sent to "UFS device" well known logical unit
  4218. * hence we require the scsi_device instance to represent this logical unit in
  4219. * order for the UFS host driver to send the SSU command for power management.
  4220. * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
  4221. * Block) LU so user space process can control this LU. User space may also
  4222. * want to have access to BOOT LU.
  4223. * This function adds scsi device instances for each of all well known LUs
  4224. * (except "REPORT LUNS" LU).
  4225. *
  4226. * Returns zero on success (all required W-LUs are added successfully),
  4227. * non-zero error value on failure (if failed to add any of the required W-LU).
  4228. */
  4229. static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
  4230. {
  4231. int ret = 0;
  4232. struct scsi_device *sdev_rpmb;
  4233. struct scsi_device *sdev_boot;
  4234. hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
  4235. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
  4236. if (IS_ERR(hba->sdev_ufs_device)) {
  4237. ret = PTR_ERR(hba->sdev_ufs_device);
  4238. hba->sdev_ufs_device = NULL;
  4239. goto out;
  4240. }
  4241. scsi_device_put(hba->sdev_ufs_device);
  4242. sdev_boot = __scsi_add_device(hba->host, 0, 0,
  4243. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
  4244. if (IS_ERR(sdev_boot)) {
  4245. ret = PTR_ERR(sdev_boot);
  4246. goto remove_sdev_ufs_device;
  4247. }
  4248. scsi_device_put(sdev_boot);
  4249. sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
  4250. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
  4251. if (IS_ERR(sdev_rpmb)) {
  4252. ret = PTR_ERR(sdev_rpmb);
  4253. goto remove_sdev_boot;
  4254. }
  4255. scsi_device_put(sdev_rpmb);
  4256. goto out;
  4257. remove_sdev_boot:
  4258. scsi_remove_device(sdev_boot);
  4259. remove_sdev_ufs_device:
  4260. scsi_remove_device(hba->sdev_ufs_device);
  4261. out:
  4262. return ret;
  4263. }
  4264. static int ufs_get_device_info(struct ufs_hba *hba,
  4265. struct ufs_device_info *card_data)
  4266. {
  4267. int err;
  4268. u8 model_index;
  4269. u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
  4270. u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
  4271. err = ufshcd_read_device_desc(hba, desc_buf,
  4272. QUERY_DESC_DEVICE_MAX_SIZE);
  4273. if (err) {
  4274. dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
  4275. __func__, err);
  4276. goto out;
  4277. }
  4278. /*
  4279. * getting vendor (manufacturerID) and Bank Index in big endian
  4280. * format
  4281. */
  4282. card_data->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
  4283. desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
  4284. model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
  4285. err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
  4286. QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
  4287. if (err) {
  4288. dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
  4289. __func__, err);
  4290. goto out;
  4291. }
  4292. str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
  4293. strlcpy(card_data->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
  4294. min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
  4295. MAX_MODEL_LEN));
  4296. /* Null terminate the model string */
  4297. card_data->model[MAX_MODEL_LEN] = '\0';
  4298. out:
  4299. return err;
  4300. }
  4301. void ufs_advertise_fixup_device(struct ufs_hba *hba)
  4302. {
  4303. int err;
  4304. struct ufs_dev_fix *f;
  4305. struct ufs_device_info card_data;
  4306. card_data.wmanufacturerid = 0;
  4307. err = ufs_get_device_info(hba, &card_data);
  4308. if (err) {
  4309. dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
  4310. __func__, err);
  4311. return;
  4312. }
  4313. for (f = ufs_fixups; f->quirk; f++) {
  4314. if (((f->card.wmanufacturerid == card_data.wmanufacturerid) ||
  4315. (f->card.wmanufacturerid == UFS_ANY_VENDOR)) &&
  4316. (STR_PRFX_EQUAL(f->card.model, card_data.model) ||
  4317. !strcmp(f->card.model, UFS_ANY_MODEL)))
  4318. hba->dev_quirks |= f->quirk;
  4319. }
  4320. }
  4321. /**
  4322. * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
  4323. * @hba: per-adapter instance
  4324. *
  4325. * PA_TActivate parameter can be tuned manually if UniPro version is less than
  4326. * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
  4327. * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
  4328. * the hibern8 exit latency.
  4329. *
  4330. * Returns zero on success, non-zero error value on failure.
  4331. */
  4332. static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
  4333. {
  4334. int ret = 0;
  4335. u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
  4336. ret = ufshcd_dme_peer_get(hba,
  4337. UIC_ARG_MIB_SEL(
  4338. RX_MIN_ACTIVATETIME_CAPABILITY,
  4339. UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
  4340. &peer_rx_min_activatetime);
  4341. if (ret)
  4342. goto out;
  4343. /* make sure proper unit conversion is applied */
  4344. tuned_pa_tactivate =
  4345. ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
  4346. / PA_TACTIVATE_TIME_UNIT_US);
  4347. ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
  4348. tuned_pa_tactivate);
  4349. out:
  4350. return ret;
  4351. }
  4352. /**
  4353. * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
  4354. * @hba: per-adapter instance
  4355. *
  4356. * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
  4357. * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
  4358. * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
  4359. * This optimal value can help reduce the hibern8 exit latency.
  4360. *
  4361. * Returns zero on success, non-zero error value on failure.
  4362. */
  4363. static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
  4364. {
  4365. int ret = 0;
  4366. u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
  4367. u32 max_hibern8_time, tuned_pa_hibern8time;
  4368. ret = ufshcd_dme_get(hba,
  4369. UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
  4370. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
  4371. &local_tx_hibern8_time_cap);
  4372. if (ret)
  4373. goto out;
  4374. ret = ufshcd_dme_peer_get(hba,
  4375. UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
  4376. UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
  4377. &peer_rx_hibern8_time_cap);
  4378. if (ret)
  4379. goto out;
  4380. max_hibern8_time = max(local_tx_hibern8_time_cap,
  4381. peer_rx_hibern8_time_cap);
  4382. /* make sure proper unit conversion is applied */
  4383. tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
  4384. / PA_HIBERN8_TIME_UNIT_US);
  4385. ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
  4386. tuned_pa_hibern8time);
  4387. out:
  4388. return ret;
  4389. }
  4390. /**
  4391. * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
  4392. * less than device PA_TACTIVATE time.
  4393. * @hba: per-adapter instance
  4394. *
  4395. * Some UFS devices require host PA_TACTIVATE to be lower than device
  4396. * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
  4397. * for such devices.
  4398. *
  4399. * Returns zero on success, non-zero error value on failure.
  4400. */
  4401. static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
  4402. {
  4403. int ret = 0;
  4404. u32 granularity, peer_granularity;
  4405. u32 pa_tactivate, peer_pa_tactivate;
  4406. u32 pa_tactivate_us, peer_pa_tactivate_us;
  4407. u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
  4408. ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
  4409. &granularity);
  4410. if (ret)
  4411. goto out;
  4412. ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
  4413. &peer_granularity);
  4414. if (ret)
  4415. goto out;
  4416. if ((granularity < PA_GRANULARITY_MIN_VAL) ||
  4417. (granularity > PA_GRANULARITY_MAX_VAL)) {
  4418. dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
  4419. __func__, granularity);
  4420. return -EINVAL;
  4421. }
  4422. if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
  4423. (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
  4424. dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
  4425. __func__, peer_granularity);
  4426. return -EINVAL;
  4427. }
  4428. ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
  4429. if (ret)
  4430. goto out;
  4431. ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
  4432. &peer_pa_tactivate);
  4433. if (ret)
  4434. goto out;
  4435. pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
  4436. peer_pa_tactivate_us = peer_pa_tactivate *
  4437. gran_to_us_table[peer_granularity - 1];
  4438. if (pa_tactivate_us > peer_pa_tactivate_us) {
  4439. u32 new_peer_pa_tactivate;
  4440. new_peer_pa_tactivate = pa_tactivate_us /
  4441. gran_to_us_table[peer_granularity - 1];
  4442. new_peer_pa_tactivate++;
  4443. ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
  4444. new_peer_pa_tactivate);
  4445. }
  4446. out:
  4447. return ret;
  4448. }
  4449. static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
  4450. {
  4451. if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
  4452. ufshcd_tune_pa_tactivate(hba);
  4453. ufshcd_tune_pa_hibern8time(hba);
  4454. }
  4455. if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
  4456. /* set 1ms timeout for PA_TACTIVATE */
  4457. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
  4458. if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
  4459. ufshcd_quirk_tune_host_pa_tactivate(hba);
  4460. ufshcd_vops_apply_dev_quirks(hba);
  4461. }
  4462. /**
  4463. * ufshcd_probe_hba - probe hba to detect device and initialize
  4464. * @hba: per-adapter instance
  4465. *
  4466. * Execute link-startup and verify device initialization
  4467. */
  4468. static int ufshcd_probe_hba(struct ufs_hba *hba)
  4469. {
  4470. int ret;
  4471. ret = ufshcd_link_startup(hba);
  4472. if (ret)
  4473. goto out;
  4474. ufshcd_init_pwr_info(hba);
  4475. /* set the default level for urgent bkops */
  4476. hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
  4477. hba->is_urgent_bkops_lvl_checked = false;
  4478. /* UniPro link is active now */
  4479. ufshcd_set_link_active(hba);
  4480. ret = ufshcd_verify_dev_init(hba);
  4481. if (ret)
  4482. goto out;
  4483. ret = ufshcd_complete_dev_init(hba);
  4484. if (ret)
  4485. goto out;
  4486. ufs_advertise_fixup_device(hba);
  4487. ufshcd_tune_unipro_params(hba);
  4488. ret = ufshcd_set_vccq_rail_unused(hba,
  4489. (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
  4490. if (ret)
  4491. goto out;
  4492. /* UFS device is also active now */
  4493. ufshcd_set_ufs_dev_active(hba);
  4494. ufshcd_force_reset_auto_bkops(hba);
  4495. hba->wlun_dev_clr_ua = true;
  4496. if (ufshcd_get_max_pwr_mode(hba)) {
  4497. dev_err(hba->dev,
  4498. "%s: Failed getting max supported power mode\n",
  4499. __func__);
  4500. } else {
  4501. ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
  4502. if (ret)
  4503. dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
  4504. __func__, ret);
  4505. }
  4506. /* set the state as operational after switching to desired gear */
  4507. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  4508. /*
  4509. * If we are in error handling context or in power management callbacks
  4510. * context, no need to scan the host
  4511. */
  4512. if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  4513. bool flag;
  4514. /* clear any previous UFS device information */
  4515. memset(&hba->dev_info, 0, sizeof(hba->dev_info));
  4516. if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  4517. QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
  4518. hba->dev_info.f_power_on_wp_en = flag;
  4519. if (!hba->is_init_prefetch)
  4520. ufshcd_init_icc_levels(hba);
  4521. /* Add required well known logical units to scsi mid layer */
  4522. if (ufshcd_scsi_add_wlus(hba))
  4523. goto out;
  4524. scsi_scan_host(hba->host);
  4525. pm_runtime_put_sync(hba->dev);
  4526. }
  4527. if (!hba->is_init_prefetch)
  4528. hba->is_init_prefetch = true;
  4529. /* Resume devfreq after UFS device is detected */
  4530. if (ufshcd_is_clkscaling_enabled(hba))
  4531. devfreq_resume_device(hba->devfreq);
  4532. out:
  4533. /*
  4534. * If we failed to initialize the device or the device is not
  4535. * present, turn off the power/clocks etc.
  4536. */
  4537. if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  4538. pm_runtime_put_sync(hba->dev);
  4539. ufshcd_hba_exit(hba);
  4540. }
  4541. return ret;
  4542. }
  4543. /**
  4544. * ufshcd_async_scan - asynchronous execution for probing hba
  4545. * @data: data pointer to pass to this function
  4546. * @cookie: cookie data
  4547. */
  4548. static void ufshcd_async_scan(void *data, async_cookie_t cookie)
  4549. {
  4550. struct ufs_hba *hba = (struct ufs_hba *)data;
  4551. ufshcd_probe_hba(hba);
  4552. }
  4553. static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
  4554. {
  4555. unsigned long flags;
  4556. struct Scsi_Host *host;
  4557. struct ufs_hba *hba;
  4558. int index;
  4559. bool found = false;
  4560. if (!scmd || !scmd->device || !scmd->device->host)
  4561. return BLK_EH_NOT_HANDLED;
  4562. host = scmd->device->host;
  4563. hba = shost_priv(host);
  4564. if (!hba)
  4565. return BLK_EH_NOT_HANDLED;
  4566. spin_lock_irqsave(host->host_lock, flags);
  4567. for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
  4568. if (hba->lrb[index].cmd == scmd) {
  4569. found = true;
  4570. break;
  4571. }
  4572. }
  4573. spin_unlock_irqrestore(host->host_lock, flags);
  4574. /*
  4575. * Bypass SCSI error handling and reset the block layer timer if this
  4576. * SCSI command was not actually dispatched to UFS driver, otherwise
  4577. * let SCSI layer handle the error as usual.
  4578. */
  4579. return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
  4580. }
  4581. static struct scsi_host_template ufshcd_driver_template = {
  4582. .module = THIS_MODULE,
  4583. .name = UFSHCD,
  4584. .proc_name = UFSHCD,
  4585. .queuecommand = ufshcd_queuecommand,
  4586. .slave_alloc = ufshcd_slave_alloc,
  4587. .slave_configure = ufshcd_slave_configure,
  4588. .slave_destroy = ufshcd_slave_destroy,
  4589. .change_queue_depth = ufshcd_change_queue_depth,
  4590. .eh_abort_handler = ufshcd_abort,
  4591. .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
  4592. .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
  4593. .eh_timed_out = ufshcd_eh_timed_out,
  4594. .this_id = -1,
  4595. .sg_tablesize = SG_ALL,
  4596. .cmd_per_lun = UFSHCD_CMD_PER_LUN,
  4597. .can_queue = UFSHCD_CAN_QUEUE,
  4598. .max_host_blocked = 1,
  4599. .track_queue_depth = 1,
  4600. };
  4601. static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
  4602. int ua)
  4603. {
  4604. int ret;
  4605. if (!vreg)
  4606. return 0;
  4607. ret = regulator_set_load(vreg->reg, ua);
  4608. if (ret < 0) {
  4609. dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
  4610. __func__, vreg->name, ua, ret);
  4611. }
  4612. return ret;
  4613. }
  4614. static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
  4615. struct ufs_vreg *vreg)
  4616. {
  4617. if (!vreg)
  4618. return 0;
  4619. else if (vreg->unused)
  4620. return 0;
  4621. else
  4622. return ufshcd_config_vreg_load(hba->dev, vreg,
  4623. UFS_VREG_LPM_LOAD_UA);
  4624. }
  4625. static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
  4626. struct ufs_vreg *vreg)
  4627. {
  4628. if (!vreg)
  4629. return 0;
  4630. else if (vreg->unused)
  4631. return 0;
  4632. else
  4633. return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
  4634. }
  4635. static int ufshcd_config_vreg(struct device *dev,
  4636. struct ufs_vreg *vreg, bool on)
  4637. {
  4638. int ret = 0;
  4639. struct regulator *reg = vreg->reg;
  4640. const char *name = vreg->name;
  4641. int min_uV, uA_load;
  4642. BUG_ON(!vreg);
  4643. if (regulator_count_voltages(reg) > 0) {
  4644. min_uV = on ? vreg->min_uV : 0;
  4645. ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
  4646. if (ret) {
  4647. dev_err(dev, "%s: %s set voltage failed, err=%d\n",
  4648. __func__, name, ret);
  4649. goto out;
  4650. }
  4651. uA_load = on ? vreg->max_uA : 0;
  4652. ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
  4653. if (ret)
  4654. goto out;
  4655. }
  4656. out:
  4657. return ret;
  4658. }
  4659. static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
  4660. {
  4661. int ret = 0;
  4662. if (!vreg)
  4663. goto out;
  4664. else if (vreg->enabled || vreg->unused)
  4665. goto out;
  4666. ret = ufshcd_config_vreg(dev, vreg, true);
  4667. if (!ret)
  4668. ret = regulator_enable(vreg->reg);
  4669. if (!ret)
  4670. vreg->enabled = true;
  4671. else
  4672. dev_err(dev, "%s: %s enable failed, err=%d\n",
  4673. __func__, vreg->name, ret);
  4674. out:
  4675. return ret;
  4676. }
  4677. static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
  4678. {
  4679. int ret = 0;
  4680. if (!vreg)
  4681. goto out;
  4682. else if (!vreg->enabled || vreg->unused)
  4683. goto out;
  4684. ret = regulator_disable(vreg->reg);
  4685. if (!ret) {
  4686. /* ignore errors on applying disable config */
  4687. ufshcd_config_vreg(dev, vreg, false);
  4688. vreg->enabled = false;
  4689. } else {
  4690. dev_err(dev, "%s: %s disable failed, err=%d\n",
  4691. __func__, vreg->name, ret);
  4692. }
  4693. out:
  4694. return ret;
  4695. }
  4696. static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
  4697. {
  4698. int ret = 0;
  4699. struct device *dev = hba->dev;
  4700. struct ufs_vreg_info *info = &hba->vreg_info;
  4701. if (!info)
  4702. goto out;
  4703. ret = ufshcd_toggle_vreg(dev, info->vcc, on);
  4704. if (ret)
  4705. goto out;
  4706. ret = ufshcd_toggle_vreg(dev, info->vccq, on);
  4707. if (ret)
  4708. goto out;
  4709. ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
  4710. if (ret)
  4711. goto out;
  4712. out:
  4713. if (ret) {
  4714. ufshcd_toggle_vreg(dev, info->vccq2, false);
  4715. ufshcd_toggle_vreg(dev, info->vccq, false);
  4716. ufshcd_toggle_vreg(dev, info->vcc, false);
  4717. }
  4718. return ret;
  4719. }
  4720. static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
  4721. {
  4722. struct ufs_vreg_info *info = &hba->vreg_info;
  4723. if (info)
  4724. return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
  4725. return 0;
  4726. }
  4727. static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
  4728. {
  4729. int ret = 0;
  4730. if (!vreg)
  4731. goto out;
  4732. vreg->reg = devm_regulator_get(dev, vreg->name);
  4733. if (IS_ERR(vreg->reg)) {
  4734. ret = PTR_ERR(vreg->reg);
  4735. dev_err(dev, "%s: %s get failed, err=%d\n",
  4736. __func__, vreg->name, ret);
  4737. }
  4738. out:
  4739. return ret;
  4740. }
  4741. static int ufshcd_init_vreg(struct ufs_hba *hba)
  4742. {
  4743. int ret = 0;
  4744. struct device *dev = hba->dev;
  4745. struct ufs_vreg_info *info = &hba->vreg_info;
  4746. if (!info)
  4747. goto out;
  4748. ret = ufshcd_get_vreg(dev, info->vcc);
  4749. if (ret)
  4750. goto out;
  4751. ret = ufshcd_get_vreg(dev, info->vccq);
  4752. if (ret)
  4753. goto out;
  4754. ret = ufshcd_get_vreg(dev, info->vccq2);
  4755. out:
  4756. return ret;
  4757. }
  4758. static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
  4759. {
  4760. struct ufs_vreg_info *info = &hba->vreg_info;
  4761. if (info)
  4762. return ufshcd_get_vreg(hba->dev, info->vdd_hba);
  4763. return 0;
  4764. }
  4765. static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
  4766. {
  4767. int ret = 0;
  4768. struct ufs_vreg_info *info = &hba->vreg_info;
  4769. if (!info)
  4770. goto out;
  4771. else if (!info->vccq)
  4772. goto out;
  4773. if (unused) {
  4774. /* shut off the rail here */
  4775. ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
  4776. /*
  4777. * Mark this rail as no longer used, so it doesn't get enabled
  4778. * later by mistake
  4779. */
  4780. if (!ret)
  4781. info->vccq->unused = true;
  4782. } else {
  4783. /*
  4784. * rail should have been already enabled hence just make sure
  4785. * that unused flag is cleared.
  4786. */
  4787. info->vccq->unused = false;
  4788. }
  4789. out:
  4790. return ret;
  4791. }
  4792. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  4793. bool skip_ref_clk)
  4794. {
  4795. int ret = 0;
  4796. struct ufs_clk_info *clki;
  4797. struct list_head *head = &hba->clk_list_head;
  4798. unsigned long flags;
  4799. if (!head || list_empty(head))
  4800. goto out;
  4801. list_for_each_entry(clki, head, list) {
  4802. if (!IS_ERR_OR_NULL(clki->clk)) {
  4803. if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
  4804. continue;
  4805. if (on && !clki->enabled) {
  4806. ret = clk_prepare_enable(clki->clk);
  4807. if (ret) {
  4808. dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
  4809. __func__, clki->name, ret);
  4810. goto out;
  4811. }
  4812. } else if (!on && clki->enabled) {
  4813. clk_disable_unprepare(clki->clk);
  4814. }
  4815. clki->enabled = on;
  4816. dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
  4817. clki->name, on ? "en" : "dis");
  4818. }
  4819. }
  4820. ret = ufshcd_vops_setup_clocks(hba, on);
  4821. out:
  4822. if (ret) {
  4823. list_for_each_entry(clki, head, list) {
  4824. if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
  4825. clk_disable_unprepare(clki->clk);
  4826. }
  4827. } else if (on) {
  4828. spin_lock_irqsave(hba->host->host_lock, flags);
  4829. hba->clk_gating.state = CLKS_ON;
  4830. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4831. }
  4832. return ret;
  4833. }
  4834. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
  4835. {
  4836. return __ufshcd_setup_clocks(hba, on, false);
  4837. }
  4838. static int ufshcd_init_clocks(struct ufs_hba *hba)
  4839. {
  4840. int ret = 0;
  4841. struct ufs_clk_info *clki;
  4842. struct device *dev = hba->dev;
  4843. struct list_head *head = &hba->clk_list_head;
  4844. if (!head || list_empty(head))
  4845. goto out;
  4846. list_for_each_entry(clki, head, list) {
  4847. if (!clki->name)
  4848. continue;
  4849. clki->clk = devm_clk_get(dev, clki->name);
  4850. if (IS_ERR(clki->clk)) {
  4851. ret = PTR_ERR(clki->clk);
  4852. dev_err(dev, "%s: %s clk get failed, %d\n",
  4853. __func__, clki->name, ret);
  4854. goto out;
  4855. }
  4856. if (clki->max_freq) {
  4857. ret = clk_set_rate(clki->clk, clki->max_freq);
  4858. if (ret) {
  4859. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  4860. __func__, clki->name,
  4861. clki->max_freq, ret);
  4862. goto out;
  4863. }
  4864. clki->curr_freq = clki->max_freq;
  4865. }
  4866. dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
  4867. clki->name, clk_get_rate(clki->clk));
  4868. }
  4869. out:
  4870. return ret;
  4871. }
  4872. static int ufshcd_variant_hba_init(struct ufs_hba *hba)
  4873. {
  4874. int err = 0;
  4875. if (!hba->vops)
  4876. goto out;
  4877. err = ufshcd_vops_init(hba);
  4878. if (err)
  4879. goto out;
  4880. err = ufshcd_vops_setup_regulators(hba, true);
  4881. if (err)
  4882. goto out_exit;
  4883. goto out;
  4884. out_exit:
  4885. ufshcd_vops_exit(hba);
  4886. out:
  4887. if (err)
  4888. dev_err(hba->dev, "%s: variant %s init failed err %d\n",
  4889. __func__, ufshcd_get_var_name(hba), err);
  4890. return err;
  4891. }
  4892. static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
  4893. {
  4894. if (!hba->vops)
  4895. return;
  4896. ufshcd_vops_setup_clocks(hba, false);
  4897. ufshcd_vops_setup_regulators(hba, false);
  4898. ufshcd_vops_exit(hba);
  4899. }
  4900. static int ufshcd_hba_init(struct ufs_hba *hba)
  4901. {
  4902. int err;
  4903. /*
  4904. * Handle host controller power separately from the UFS device power
  4905. * rails as it will help controlling the UFS host controller power
  4906. * collapse easily which is different than UFS device power collapse.
  4907. * Also, enable the host controller power before we go ahead with rest
  4908. * of the initialization here.
  4909. */
  4910. err = ufshcd_init_hba_vreg(hba);
  4911. if (err)
  4912. goto out;
  4913. err = ufshcd_setup_hba_vreg(hba, true);
  4914. if (err)
  4915. goto out;
  4916. err = ufshcd_init_clocks(hba);
  4917. if (err)
  4918. goto out_disable_hba_vreg;
  4919. err = ufshcd_setup_clocks(hba, true);
  4920. if (err)
  4921. goto out_disable_hba_vreg;
  4922. err = ufshcd_init_vreg(hba);
  4923. if (err)
  4924. goto out_disable_clks;
  4925. err = ufshcd_setup_vreg(hba, true);
  4926. if (err)
  4927. goto out_disable_clks;
  4928. err = ufshcd_variant_hba_init(hba);
  4929. if (err)
  4930. goto out_disable_vreg;
  4931. hba->is_powered = true;
  4932. goto out;
  4933. out_disable_vreg:
  4934. ufshcd_setup_vreg(hba, false);
  4935. out_disable_clks:
  4936. ufshcd_setup_clocks(hba, false);
  4937. out_disable_hba_vreg:
  4938. ufshcd_setup_hba_vreg(hba, false);
  4939. out:
  4940. return err;
  4941. }
  4942. static void ufshcd_hba_exit(struct ufs_hba *hba)
  4943. {
  4944. if (hba->is_powered) {
  4945. ufshcd_variant_hba_exit(hba);
  4946. ufshcd_setup_vreg(hba, false);
  4947. ufshcd_setup_clocks(hba, false);
  4948. ufshcd_setup_hba_vreg(hba, false);
  4949. hba->is_powered = false;
  4950. }
  4951. }
  4952. static int
  4953. ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
  4954. {
  4955. unsigned char cmd[6] = {REQUEST_SENSE,
  4956. 0,
  4957. 0,
  4958. 0,
  4959. SCSI_SENSE_BUFFERSIZE,
  4960. 0};
  4961. char *buffer;
  4962. int ret;
  4963. buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  4964. if (!buffer) {
  4965. ret = -ENOMEM;
  4966. goto out;
  4967. }
  4968. ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
  4969. SCSI_SENSE_BUFFERSIZE, NULL,
  4970. msecs_to_jiffies(1000), 3, NULL, REQ_PM);
  4971. if (ret)
  4972. pr_err("%s: failed with err %d\n", __func__, ret);
  4973. kfree(buffer);
  4974. out:
  4975. return ret;
  4976. }
  4977. /**
  4978. * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
  4979. * power mode
  4980. * @hba: per adapter instance
  4981. * @pwr_mode: device power mode to set
  4982. *
  4983. * Returns 0 if requested power mode is set successfully
  4984. * Returns non-zero if failed to set the requested power mode
  4985. */
  4986. static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
  4987. enum ufs_dev_pwr_mode pwr_mode)
  4988. {
  4989. unsigned char cmd[6] = { START_STOP };
  4990. struct scsi_sense_hdr sshdr;
  4991. struct scsi_device *sdp;
  4992. unsigned long flags;
  4993. int ret;
  4994. spin_lock_irqsave(hba->host->host_lock, flags);
  4995. sdp = hba->sdev_ufs_device;
  4996. if (sdp) {
  4997. ret = scsi_device_get(sdp);
  4998. if (!ret && !scsi_device_online(sdp)) {
  4999. ret = -ENODEV;
  5000. scsi_device_put(sdp);
  5001. }
  5002. } else {
  5003. ret = -ENODEV;
  5004. }
  5005. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5006. if (ret)
  5007. return ret;
  5008. /*
  5009. * If scsi commands fail, the scsi mid-layer schedules scsi error-
  5010. * handling, which would wait for host to be resumed. Since we know
  5011. * we are functional while we are here, skip host resume in error
  5012. * handling context.
  5013. */
  5014. hba->host->eh_noresume = 1;
  5015. if (hba->wlun_dev_clr_ua) {
  5016. ret = ufshcd_send_request_sense(hba, sdp);
  5017. if (ret)
  5018. goto out;
  5019. /* Unit attention condition is cleared now */
  5020. hba->wlun_dev_clr_ua = false;
  5021. }
  5022. cmd[4] = pwr_mode << 4;
  5023. /*
  5024. * Current function would be generally called from the power management
  5025. * callbacks hence set the REQ_PM flag so that it doesn't resume the
  5026. * already suspended childs.
  5027. */
  5028. ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
  5029. START_STOP_TIMEOUT, 0, NULL, REQ_PM);
  5030. if (ret) {
  5031. sdev_printk(KERN_WARNING, sdp,
  5032. "START_STOP failed for power mode: %d, result %x\n",
  5033. pwr_mode, ret);
  5034. if (driver_byte(ret) & DRIVER_SENSE)
  5035. scsi_print_sense_hdr(sdp, NULL, &sshdr);
  5036. }
  5037. if (!ret)
  5038. hba->curr_dev_pwr_mode = pwr_mode;
  5039. out:
  5040. scsi_device_put(sdp);
  5041. hba->host->eh_noresume = 0;
  5042. return ret;
  5043. }
  5044. static int ufshcd_link_state_transition(struct ufs_hba *hba,
  5045. enum uic_link_state req_link_state,
  5046. int check_for_bkops)
  5047. {
  5048. int ret = 0;
  5049. if (req_link_state == hba->uic_link_state)
  5050. return 0;
  5051. if (req_link_state == UIC_LINK_HIBERN8_STATE) {
  5052. ret = ufshcd_uic_hibern8_enter(hba);
  5053. if (!ret)
  5054. ufshcd_set_link_hibern8(hba);
  5055. else
  5056. goto out;
  5057. }
  5058. /*
  5059. * If autobkops is enabled, link can't be turned off because
  5060. * turning off the link would also turn off the device.
  5061. */
  5062. else if ((req_link_state == UIC_LINK_OFF_STATE) &&
  5063. (!check_for_bkops || (check_for_bkops &&
  5064. !hba->auto_bkops_enabled))) {
  5065. /*
  5066. * Let's make sure that link is in low power mode, we are doing
  5067. * this currently by putting the link in Hibern8. Otherway to
  5068. * put the link in low power mode is to send the DME end point
  5069. * to device and then send the DME reset command to local
  5070. * unipro. But putting the link in hibern8 is much faster.
  5071. */
  5072. ret = ufshcd_uic_hibern8_enter(hba);
  5073. if (ret)
  5074. goto out;
  5075. /*
  5076. * Change controller state to "reset state" which
  5077. * should also put the link in off/reset state
  5078. */
  5079. ufshcd_hba_stop(hba, true);
  5080. /*
  5081. * TODO: Check if we need any delay to make sure that
  5082. * controller is reset
  5083. */
  5084. ufshcd_set_link_off(hba);
  5085. }
  5086. out:
  5087. return ret;
  5088. }
  5089. static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
  5090. {
  5091. /*
  5092. * It seems some UFS devices may keep drawing more than sleep current
  5093. * (atleast for 500us) from UFS rails (especially from VCCQ rail).
  5094. * To avoid this situation, add 2ms delay before putting these UFS
  5095. * rails in LPM mode.
  5096. */
  5097. if (!ufshcd_is_link_active(hba) &&
  5098. hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
  5099. usleep_range(2000, 2100);
  5100. /*
  5101. * If UFS device is either in UFS_Sleep turn off VCC rail to save some
  5102. * power.
  5103. *
  5104. * If UFS device and link is in OFF state, all power supplies (VCC,
  5105. * VCCQ, VCCQ2) can be turned off if power on write protect is not
  5106. * required. If UFS link is inactive (Hibern8 or OFF state) and device
  5107. * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
  5108. *
  5109. * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
  5110. * in low power state which would save some power.
  5111. */
  5112. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  5113. !hba->dev_info.is_lu_power_on_wp) {
  5114. ufshcd_setup_vreg(hba, false);
  5115. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  5116. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  5117. if (!ufshcd_is_link_active(hba)) {
  5118. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  5119. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
  5120. }
  5121. }
  5122. }
  5123. static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
  5124. {
  5125. int ret = 0;
  5126. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  5127. !hba->dev_info.is_lu_power_on_wp) {
  5128. ret = ufshcd_setup_vreg(hba, true);
  5129. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  5130. ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
  5131. if (!ret && !ufshcd_is_link_active(hba)) {
  5132. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
  5133. if (ret)
  5134. goto vcc_disable;
  5135. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
  5136. if (ret)
  5137. goto vccq_lpm;
  5138. }
  5139. }
  5140. goto out;
  5141. vccq_lpm:
  5142. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  5143. vcc_disable:
  5144. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  5145. out:
  5146. return ret;
  5147. }
  5148. static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
  5149. {
  5150. if (ufshcd_is_link_off(hba))
  5151. ufshcd_setup_hba_vreg(hba, false);
  5152. }
  5153. static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
  5154. {
  5155. if (ufshcd_is_link_off(hba))
  5156. ufshcd_setup_hba_vreg(hba, true);
  5157. }
  5158. /**
  5159. * ufshcd_suspend - helper function for suspend operations
  5160. * @hba: per adapter instance
  5161. * @pm_op: desired low power operation type
  5162. *
  5163. * This function will try to put the UFS device and link into low power
  5164. * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
  5165. * (System PM level).
  5166. *
  5167. * If this function is called during shutdown, it will make sure that
  5168. * both UFS device and UFS link is powered off.
  5169. *
  5170. * NOTE: UFS device & link must be active before we enter in this function.
  5171. *
  5172. * Returns 0 for success and non-zero for failure
  5173. */
  5174. static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  5175. {
  5176. int ret = 0;
  5177. enum ufs_pm_level pm_lvl;
  5178. enum ufs_dev_pwr_mode req_dev_pwr_mode;
  5179. enum uic_link_state req_link_state;
  5180. hba->pm_op_in_progress = 1;
  5181. if (!ufshcd_is_shutdown_pm(pm_op)) {
  5182. pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
  5183. hba->rpm_lvl : hba->spm_lvl;
  5184. req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
  5185. req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
  5186. } else {
  5187. req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
  5188. req_link_state = UIC_LINK_OFF_STATE;
  5189. }
  5190. /*
  5191. * If we can't transition into any of the low power modes
  5192. * just gate the clocks.
  5193. */
  5194. ufshcd_hold(hba, false);
  5195. hba->clk_gating.is_suspended = true;
  5196. if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
  5197. req_link_state == UIC_LINK_ACTIVE_STATE) {
  5198. goto disable_clks;
  5199. }
  5200. if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
  5201. (req_link_state == hba->uic_link_state))
  5202. goto out;
  5203. /* UFS device & link must be active before we enter in this function */
  5204. if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
  5205. ret = -EINVAL;
  5206. goto out;
  5207. }
  5208. if (ufshcd_is_runtime_pm(pm_op)) {
  5209. if (ufshcd_can_autobkops_during_suspend(hba)) {
  5210. /*
  5211. * The device is idle with no requests in the queue,
  5212. * allow background operations if bkops status shows
  5213. * that performance might be impacted.
  5214. */
  5215. ret = ufshcd_urgent_bkops(hba);
  5216. if (ret)
  5217. goto enable_gating;
  5218. } else {
  5219. /* make sure that auto bkops is disabled */
  5220. ufshcd_disable_auto_bkops(hba);
  5221. }
  5222. }
  5223. if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
  5224. ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
  5225. !ufshcd_is_runtime_pm(pm_op))) {
  5226. /* ensure that bkops is disabled */
  5227. ufshcd_disable_auto_bkops(hba);
  5228. ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
  5229. if (ret)
  5230. goto enable_gating;
  5231. }
  5232. ret = ufshcd_link_state_transition(hba, req_link_state, 1);
  5233. if (ret)
  5234. goto set_dev_active;
  5235. ufshcd_vreg_set_lpm(hba);
  5236. disable_clks:
  5237. /*
  5238. * The clock scaling needs access to controller registers. Hence, Wait
  5239. * for pending clock scaling work to be done before clocks are
  5240. * turned off.
  5241. */
  5242. if (ufshcd_is_clkscaling_enabled(hba)) {
  5243. devfreq_suspend_device(hba->devfreq);
  5244. hba->clk_scaling.window_start_t = 0;
  5245. }
  5246. /*
  5247. * Call vendor specific suspend callback. As these callbacks may access
  5248. * vendor specific host controller register space call them before the
  5249. * host clocks are ON.
  5250. */
  5251. ret = ufshcd_vops_suspend(hba, pm_op);
  5252. if (ret)
  5253. goto set_link_active;
  5254. ret = ufshcd_vops_setup_clocks(hba, false);
  5255. if (ret)
  5256. goto vops_resume;
  5257. if (!ufshcd_is_link_active(hba))
  5258. ufshcd_setup_clocks(hba, false);
  5259. else
  5260. /* If link is active, device ref_clk can't be switched off */
  5261. __ufshcd_setup_clocks(hba, false, true);
  5262. hba->clk_gating.state = CLKS_OFF;
  5263. /*
  5264. * Disable the host irq as host controller as there won't be any
  5265. * host controller transaction expected till resume.
  5266. */
  5267. ufshcd_disable_irq(hba);
  5268. /* Put the host controller in low power mode if possible */
  5269. ufshcd_hba_vreg_set_lpm(hba);
  5270. goto out;
  5271. vops_resume:
  5272. ufshcd_vops_resume(hba, pm_op);
  5273. set_link_active:
  5274. ufshcd_vreg_set_hpm(hba);
  5275. if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
  5276. ufshcd_set_link_active(hba);
  5277. else if (ufshcd_is_link_off(hba))
  5278. ufshcd_host_reset_and_restore(hba);
  5279. set_dev_active:
  5280. if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
  5281. ufshcd_disable_auto_bkops(hba);
  5282. enable_gating:
  5283. hba->clk_gating.is_suspended = false;
  5284. ufshcd_release(hba);
  5285. out:
  5286. hba->pm_op_in_progress = 0;
  5287. return ret;
  5288. }
  5289. /**
  5290. * ufshcd_resume - helper function for resume operations
  5291. * @hba: per adapter instance
  5292. * @pm_op: runtime PM or system PM
  5293. *
  5294. * This function basically brings the UFS device, UniPro link and controller
  5295. * to active state.
  5296. *
  5297. * Returns 0 for success and non-zero for failure
  5298. */
  5299. static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  5300. {
  5301. int ret;
  5302. enum uic_link_state old_link_state;
  5303. hba->pm_op_in_progress = 1;
  5304. old_link_state = hba->uic_link_state;
  5305. ufshcd_hba_vreg_set_hpm(hba);
  5306. /* Make sure clocks are enabled before accessing controller */
  5307. ret = ufshcd_setup_clocks(hba, true);
  5308. if (ret)
  5309. goto out;
  5310. /* enable the host irq as host controller would be active soon */
  5311. ret = ufshcd_enable_irq(hba);
  5312. if (ret)
  5313. goto disable_irq_and_vops_clks;
  5314. ret = ufshcd_vreg_set_hpm(hba);
  5315. if (ret)
  5316. goto disable_irq_and_vops_clks;
  5317. /*
  5318. * Call vendor specific resume callback. As these callbacks may access
  5319. * vendor specific host controller register space call them when the
  5320. * host clocks are ON.
  5321. */
  5322. ret = ufshcd_vops_resume(hba, pm_op);
  5323. if (ret)
  5324. goto disable_vreg;
  5325. if (ufshcd_is_link_hibern8(hba)) {
  5326. ret = ufshcd_uic_hibern8_exit(hba);
  5327. if (!ret)
  5328. ufshcd_set_link_active(hba);
  5329. else
  5330. goto vendor_suspend;
  5331. } else if (ufshcd_is_link_off(hba)) {
  5332. ret = ufshcd_host_reset_and_restore(hba);
  5333. /*
  5334. * ufshcd_host_reset_and_restore() should have already
  5335. * set the link state as active
  5336. */
  5337. if (ret || !ufshcd_is_link_active(hba))
  5338. goto vendor_suspend;
  5339. }
  5340. if (!ufshcd_is_ufs_dev_active(hba)) {
  5341. ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
  5342. if (ret)
  5343. goto set_old_link_state;
  5344. }
  5345. /*
  5346. * If BKOPs operations are urgently needed at this moment then
  5347. * keep auto-bkops enabled or else disable it.
  5348. */
  5349. ufshcd_urgent_bkops(hba);
  5350. hba->clk_gating.is_suspended = false;
  5351. if (ufshcd_is_clkscaling_enabled(hba))
  5352. devfreq_resume_device(hba->devfreq);
  5353. /* Schedule clock gating in case of no access to UFS device yet */
  5354. ufshcd_release(hba);
  5355. goto out;
  5356. set_old_link_state:
  5357. ufshcd_link_state_transition(hba, old_link_state, 0);
  5358. vendor_suspend:
  5359. ufshcd_vops_suspend(hba, pm_op);
  5360. disable_vreg:
  5361. ufshcd_vreg_set_lpm(hba);
  5362. disable_irq_and_vops_clks:
  5363. ufshcd_disable_irq(hba);
  5364. ufshcd_setup_clocks(hba, false);
  5365. out:
  5366. hba->pm_op_in_progress = 0;
  5367. return ret;
  5368. }
  5369. /**
  5370. * ufshcd_system_suspend - system suspend routine
  5371. * @hba: per adapter instance
  5372. * @pm_op: runtime PM or system PM
  5373. *
  5374. * Check the description of ufshcd_suspend() function for more details.
  5375. *
  5376. * Returns 0 for success and non-zero for failure
  5377. */
  5378. int ufshcd_system_suspend(struct ufs_hba *hba)
  5379. {
  5380. int ret = 0;
  5381. if (!hba || !hba->is_powered)
  5382. return 0;
  5383. if (pm_runtime_suspended(hba->dev)) {
  5384. if (hba->rpm_lvl == hba->spm_lvl)
  5385. /*
  5386. * There is possibility that device may still be in
  5387. * active state during the runtime suspend.
  5388. */
  5389. if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
  5390. hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
  5391. goto out;
  5392. /*
  5393. * UFS device and/or UFS link low power states during runtime
  5394. * suspend seems to be different than what is expected during
  5395. * system suspend. Hence runtime resume the devic & link and
  5396. * let the system suspend low power states to take effect.
  5397. * TODO: If resume takes longer time, we might have optimize
  5398. * it in future by not resuming everything if possible.
  5399. */
  5400. ret = ufshcd_runtime_resume(hba);
  5401. if (ret)
  5402. goto out;
  5403. }
  5404. ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
  5405. out:
  5406. if (!ret)
  5407. hba->is_sys_suspended = true;
  5408. return ret;
  5409. }
  5410. EXPORT_SYMBOL(ufshcd_system_suspend);
  5411. /**
  5412. * ufshcd_system_resume - system resume routine
  5413. * @hba: per adapter instance
  5414. *
  5415. * Returns 0 for success and non-zero for failure
  5416. */
  5417. int ufshcd_system_resume(struct ufs_hba *hba)
  5418. {
  5419. if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev))
  5420. /*
  5421. * Let the runtime resume take care of resuming
  5422. * if runtime suspended.
  5423. */
  5424. return 0;
  5425. return ufshcd_resume(hba, UFS_SYSTEM_PM);
  5426. }
  5427. EXPORT_SYMBOL(ufshcd_system_resume);
  5428. /**
  5429. * ufshcd_runtime_suspend - runtime suspend routine
  5430. * @hba: per adapter instance
  5431. *
  5432. * Check the description of ufshcd_suspend() function for more details.
  5433. *
  5434. * Returns 0 for success and non-zero for failure
  5435. */
  5436. int ufshcd_runtime_suspend(struct ufs_hba *hba)
  5437. {
  5438. if (!hba || !hba->is_powered)
  5439. return 0;
  5440. return ufshcd_suspend(hba, UFS_RUNTIME_PM);
  5441. }
  5442. EXPORT_SYMBOL(ufshcd_runtime_suspend);
  5443. /**
  5444. * ufshcd_runtime_resume - runtime resume routine
  5445. * @hba: per adapter instance
  5446. *
  5447. * This function basically brings the UFS device, UniPro link and controller
  5448. * to active state. Following operations are done in this function:
  5449. *
  5450. * 1. Turn on all the controller related clocks
  5451. * 2. Bring the UniPro link out of Hibernate state
  5452. * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
  5453. * to active state.
  5454. * 4. If auto-bkops is enabled on the device, disable it.
  5455. *
  5456. * So following would be the possible power state after this function return
  5457. * successfully:
  5458. * S1: UFS device in Active state with VCC rail ON
  5459. * UniPro link in Active state
  5460. * All the UFS/UniPro controller clocks are ON
  5461. *
  5462. * Returns 0 for success and non-zero for failure
  5463. */
  5464. int ufshcd_runtime_resume(struct ufs_hba *hba)
  5465. {
  5466. if (!hba || !hba->is_powered)
  5467. return 0;
  5468. else
  5469. return ufshcd_resume(hba, UFS_RUNTIME_PM);
  5470. }
  5471. EXPORT_SYMBOL(ufshcd_runtime_resume);
  5472. int ufshcd_runtime_idle(struct ufs_hba *hba)
  5473. {
  5474. return 0;
  5475. }
  5476. EXPORT_SYMBOL(ufshcd_runtime_idle);
  5477. /**
  5478. * ufshcd_shutdown - shutdown routine
  5479. * @hba: per adapter instance
  5480. *
  5481. * This function would power off both UFS device and UFS link.
  5482. *
  5483. * Returns 0 always to allow force shutdown even in case of errors.
  5484. */
  5485. int ufshcd_shutdown(struct ufs_hba *hba)
  5486. {
  5487. int ret = 0;
  5488. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
  5489. goto out;
  5490. if (pm_runtime_suspended(hba->dev)) {
  5491. ret = ufshcd_runtime_resume(hba);
  5492. if (ret)
  5493. goto out;
  5494. }
  5495. ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
  5496. out:
  5497. if (ret)
  5498. dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
  5499. /* allow force shutdown even in case of errors */
  5500. return 0;
  5501. }
  5502. EXPORT_SYMBOL(ufshcd_shutdown);
  5503. /**
  5504. * ufshcd_remove - de-allocate SCSI host and host memory space
  5505. * data structure memory
  5506. * @hba - per adapter instance
  5507. */
  5508. void ufshcd_remove(struct ufs_hba *hba)
  5509. {
  5510. scsi_remove_host(hba->host);
  5511. /* disable interrupts */
  5512. ufshcd_disable_intr(hba, hba->intr_mask);
  5513. ufshcd_hba_stop(hba, true);
  5514. scsi_host_put(hba->host);
  5515. ufshcd_exit_clk_gating(hba);
  5516. if (ufshcd_is_clkscaling_enabled(hba))
  5517. devfreq_remove_device(hba->devfreq);
  5518. ufshcd_hba_exit(hba);
  5519. }
  5520. EXPORT_SYMBOL_GPL(ufshcd_remove);
  5521. /**
  5522. * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
  5523. * @hba: pointer to Host Bus Adapter (HBA)
  5524. */
  5525. void ufshcd_dealloc_host(struct ufs_hba *hba)
  5526. {
  5527. scsi_host_put(hba->host);
  5528. }
  5529. EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
  5530. /**
  5531. * ufshcd_set_dma_mask - Set dma mask based on the controller
  5532. * addressing capability
  5533. * @hba: per adapter instance
  5534. *
  5535. * Returns 0 for success, non-zero for failure
  5536. */
  5537. static int ufshcd_set_dma_mask(struct ufs_hba *hba)
  5538. {
  5539. if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
  5540. if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
  5541. return 0;
  5542. }
  5543. return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
  5544. }
  5545. /**
  5546. * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
  5547. * @dev: pointer to device handle
  5548. * @hba_handle: driver private handle
  5549. * Returns 0 on success, non-zero value on failure
  5550. */
  5551. int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
  5552. {
  5553. struct Scsi_Host *host;
  5554. struct ufs_hba *hba;
  5555. int err = 0;
  5556. if (!dev) {
  5557. dev_err(dev,
  5558. "Invalid memory reference for dev is NULL\n");
  5559. err = -ENODEV;
  5560. goto out_error;
  5561. }
  5562. host = scsi_host_alloc(&ufshcd_driver_template,
  5563. sizeof(struct ufs_hba));
  5564. if (!host) {
  5565. dev_err(dev, "scsi_host_alloc failed\n");
  5566. err = -ENOMEM;
  5567. goto out_error;
  5568. }
  5569. hba = shost_priv(host);
  5570. hba->host = host;
  5571. hba->dev = dev;
  5572. *hba_handle = hba;
  5573. out_error:
  5574. return err;
  5575. }
  5576. EXPORT_SYMBOL(ufshcd_alloc_host);
  5577. static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
  5578. {
  5579. int ret = 0;
  5580. struct ufs_clk_info *clki;
  5581. struct list_head *head = &hba->clk_list_head;
  5582. if (!head || list_empty(head))
  5583. goto out;
  5584. ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
  5585. if (ret)
  5586. return ret;
  5587. list_for_each_entry(clki, head, list) {
  5588. if (!IS_ERR_OR_NULL(clki->clk)) {
  5589. if (scale_up && clki->max_freq) {
  5590. if (clki->curr_freq == clki->max_freq)
  5591. continue;
  5592. ret = clk_set_rate(clki->clk, clki->max_freq);
  5593. if (ret) {
  5594. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  5595. __func__, clki->name,
  5596. clki->max_freq, ret);
  5597. break;
  5598. }
  5599. clki->curr_freq = clki->max_freq;
  5600. } else if (!scale_up && clki->min_freq) {
  5601. if (clki->curr_freq == clki->min_freq)
  5602. continue;
  5603. ret = clk_set_rate(clki->clk, clki->min_freq);
  5604. if (ret) {
  5605. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  5606. __func__, clki->name,
  5607. clki->min_freq, ret);
  5608. break;
  5609. }
  5610. clki->curr_freq = clki->min_freq;
  5611. }
  5612. }
  5613. dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
  5614. clki->name, clk_get_rate(clki->clk));
  5615. }
  5616. ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
  5617. out:
  5618. return ret;
  5619. }
  5620. static int ufshcd_devfreq_target(struct device *dev,
  5621. unsigned long *freq, u32 flags)
  5622. {
  5623. int err = 0;
  5624. struct ufs_hba *hba = dev_get_drvdata(dev);
  5625. if (!ufshcd_is_clkscaling_enabled(hba))
  5626. return -EINVAL;
  5627. if (*freq == UINT_MAX)
  5628. err = ufshcd_scale_clks(hba, true);
  5629. else if (*freq == 0)
  5630. err = ufshcd_scale_clks(hba, false);
  5631. return err;
  5632. }
  5633. static int ufshcd_devfreq_get_dev_status(struct device *dev,
  5634. struct devfreq_dev_status *stat)
  5635. {
  5636. struct ufs_hba *hba = dev_get_drvdata(dev);
  5637. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  5638. unsigned long flags;
  5639. if (!ufshcd_is_clkscaling_enabled(hba))
  5640. return -EINVAL;
  5641. memset(stat, 0, sizeof(*stat));
  5642. spin_lock_irqsave(hba->host->host_lock, flags);
  5643. if (!scaling->window_start_t)
  5644. goto start_window;
  5645. if (scaling->is_busy_started)
  5646. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  5647. scaling->busy_start_t));
  5648. stat->total_time = jiffies_to_usecs((long)jiffies -
  5649. (long)scaling->window_start_t);
  5650. stat->busy_time = scaling->tot_busy_t;
  5651. start_window:
  5652. scaling->window_start_t = jiffies;
  5653. scaling->tot_busy_t = 0;
  5654. if (hba->outstanding_reqs) {
  5655. scaling->busy_start_t = ktime_get();
  5656. scaling->is_busy_started = true;
  5657. } else {
  5658. scaling->busy_start_t = ktime_set(0, 0);
  5659. scaling->is_busy_started = false;
  5660. }
  5661. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5662. return 0;
  5663. }
  5664. static struct devfreq_dev_profile ufs_devfreq_profile = {
  5665. .polling_ms = 100,
  5666. .target = ufshcd_devfreq_target,
  5667. .get_dev_status = ufshcd_devfreq_get_dev_status,
  5668. };
  5669. /**
  5670. * ufshcd_init - Driver initialization routine
  5671. * @hba: per-adapter instance
  5672. * @mmio_base: base register address
  5673. * @irq: Interrupt line of device
  5674. * Returns 0 on success, non-zero value on failure
  5675. */
  5676. int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
  5677. {
  5678. int err;
  5679. struct Scsi_Host *host = hba->host;
  5680. struct device *dev = hba->dev;
  5681. if (!mmio_base) {
  5682. dev_err(hba->dev,
  5683. "Invalid memory reference for mmio_base is NULL\n");
  5684. err = -ENODEV;
  5685. goto out_error;
  5686. }
  5687. hba->mmio_base = mmio_base;
  5688. hba->irq = irq;
  5689. err = ufshcd_hba_init(hba);
  5690. if (err)
  5691. goto out_error;
  5692. /* Read capabilities registers */
  5693. ufshcd_hba_capabilities(hba);
  5694. /* Get UFS version supported by the controller */
  5695. hba->ufs_version = ufshcd_get_ufs_version(hba);
  5696. /* Get Interrupt bit mask per version */
  5697. hba->intr_mask = ufshcd_get_intr_mask(hba);
  5698. err = ufshcd_set_dma_mask(hba);
  5699. if (err) {
  5700. dev_err(hba->dev, "set dma mask failed\n");
  5701. goto out_disable;
  5702. }
  5703. /* Allocate memory for host memory space */
  5704. err = ufshcd_memory_alloc(hba);
  5705. if (err) {
  5706. dev_err(hba->dev, "Memory allocation failed\n");
  5707. goto out_disable;
  5708. }
  5709. /* Configure LRB */
  5710. ufshcd_host_memory_configure(hba);
  5711. host->can_queue = hba->nutrs;
  5712. host->cmd_per_lun = hba->nutrs;
  5713. host->max_id = UFSHCD_MAX_ID;
  5714. host->max_lun = UFS_MAX_LUNS;
  5715. host->max_channel = UFSHCD_MAX_CHANNEL;
  5716. host->unique_id = host->host_no;
  5717. host->max_cmd_len = MAX_CDB_SIZE;
  5718. hba->max_pwr_info.is_valid = false;
  5719. /* Initailize wait queue for task management */
  5720. init_waitqueue_head(&hba->tm_wq);
  5721. init_waitqueue_head(&hba->tm_tag_wq);
  5722. /* Initialize work queues */
  5723. INIT_WORK(&hba->eh_work, ufshcd_err_handler);
  5724. INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
  5725. /* Initialize UIC command mutex */
  5726. mutex_init(&hba->uic_cmd_mutex);
  5727. /* Initialize mutex for device management commands */
  5728. mutex_init(&hba->dev_cmd.lock);
  5729. /* Initialize device management tag acquire wait queue */
  5730. init_waitqueue_head(&hba->dev_cmd.tag_wq);
  5731. ufshcd_init_clk_gating(hba);
  5732. /*
  5733. * In order to avoid any spurious interrupt immediately after
  5734. * registering UFS controller interrupt handler, clear any pending UFS
  5735. * interrupt status and disable all the UFS interrupts.
  5736. */
  5737. ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
  5738. REG_INTERRUPT_STATUS);
  5739. ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
  5740. /*
  5741. * Make sure that UFS interrupts are disabled and any pending interrupt
  5742. * status is cleared before registering UFS interrupt handler.
  5743. */
  5744. mb();
  5745. /* IRQ registration */
  5746. err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
  5747. if (err) {
  5748. dev_err(hba->dev, "request irq failed\n");
  5749. goto exit_gating;
  5750. } else {
  5751. hba->is_irq_enabled = true;
  5752. }
  5753. err = scsi_add_host(host, hba->dev);
  5754. if (err) {
  5755. dev_err(hba->dev, "scsi_add_host failed\n");
  5756. goto exit_gating;
  5757. }
  5758. /* Host controller enable */
  5759. err = ufshcd_hba_enable(hba);
  5760. if (err) {
  5761. dev_err(hba->dev, "Host controller enable failed\n");
  5762. goto out_remove_scsi_host;
  5763. }
  5764. if (ufshcd_is_clkscaling_enabled(hba)) {
  5765. hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
  5766. "simple_ondemand", NULL);
  5767. if (IS_ERR(hba->devfreq)) {
  5768. dev_err(hba->dev, "Unable to register with devfreq %ld\n",
  5769. PTR_ERR(hba->devfreq));
  5770. err = PTR_ERR(hba->devfreq);
  5771. goto out_remove_scsi_host;
  5772. }
  5773. /* Suspend devfreq until the UFS device is detected */
  5774. devfreq_suspend_device(hba->devfreq);
  5775. hba->clk_scaling.window_start_t = 0;
  5776. }
  5777. /* Hold auto suspend until async scan completes */
  5778. pm_runtime_get_sync(dev);
  5779. /*
  5780. * We are assuming that device wasn't put in sleep/power-down
  5781. * state exclusively during the boot stage before kernel.
  5782. * This assumption helps avoid doing link startup twice during
  5783. * ufshcd_probe_hba().
  5784. */
  5785. ufshcd_set_ufs_dev_active(hba);
  5786. async_schedule(ufshcd_async_scan, hba);
  5787. return 0;
  5788. out_remove_scsi_host:
  5789. scsi_remove_host(hba->host);
  5790. exit_gating:
  5791. ufshcd_exit_clk_gating(hba);
  5792. out_disable:
  5793. hba->is_irq_enabled = false;
  5794. scsi_host_put(host);
  5795. ufshcd_hba_exit(hba);
  5796. out_error:
  5797. return err;
  5798. }
  5799. EXPORT_SYMBOL_GPL(ufshcd_init);
  5800. MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
  5801. MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
  5802. MODULE_DESCRIPTION("Generic UFS host controller driver Core");
  5803. MODULE_LICENSE("GPL");
  5804. MODULE_VERSION(UFSHCD_DRIVER_VERSION);