hpsa.c 280 KB

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  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright 2016 Microsemi Corporation
  4. * Copyright 2014-2015 PMC-Sierra, Inc.
  5. * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  14. * NON INFRINGEMENT. See the GNU General Public License for more details.
  15. *
  16. * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
  17. *
  18. */
  19. #include <linux/module.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/types.h>
  22. #include <linux/pci.h>
  23. #include <linux/pci-aspm.h>
  24. #include <linux/kernel.h>
  25. #include <linux/slab.h>
  26. #include <linux/delay.h>
  27. #include <linux/fs.h>
  28. #include <linux/timer.h>
  29. #include <linux/init.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/compat.h>
  32. #include <linux/blktrace_api.h>
  33. #include <linux/uaccess.h>
  34. #include <linux/io.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/completion.h>
  37. #include <linux/moduleparam.h>
  38. #include <scsi/scsi.h>
  39. #include <scsi/scsi_cmnd.h>
  40. #include <scsi/scsi_device.h>
  41. #include <scsi/scsi_host.h>
  42. #include <scsi/scsi_tcq.h>
  43. #include <scsi/scsi_eh.h>
  44. #include <scsi/scsi_transport_sas.h>
  45. #include <scsi/scsi_dbg.h>
  46. #include <linux/cciss_ioctl.h>
  47. #include <linux/string.h>
  48. #include <linux/bitmap.h>
  49. #include <linux/atomic.h>
  50. #include <linux/jiffies.h>
  51. #include <linux/percpu-defs.h>
  52. #include <linux/percpu.h>
  53. #include <asm/unaligned.h>
  54. #include <asm/div64.h>
  55. #include "hpsa_cmd.h"
  56. #include "hpsa.h"
  57. /*
  58. * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
  59. * with an optional trailing '-' followed by a byte value (0-255).
  60. */
  61. #define HPSA_DRIVER_VERSION "3.4.16-0"
  62. #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
  63. #define HPSA "hpsa"
  64. /* How long to wait for CISS doorbell communication */
  65. #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
  66. #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
  67. #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
  68. #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
  69. #define MAX_IOCTL_CONFIG_WAIT 1000
  70. /*define how many times we will try a command because of bus resets */
  71. #define MAX_CMD_RETRIES 3
  72. /* Embedded module documentation macros - see modules.h */
  73. MODULE_AUTHOR("Hewlett-Packard Company");
  74. MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
  75. HPSA_DRIVER_VERSION);
  76. MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
  77. MODULE_VERSION(HPSA_DRIVER_VERSION);
  78. MODULE_LICENSE("GPL");
  79. static int hpsa_allow_any;
  80. module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
  81. MODULE_PARM_DESC(hpsa_allow_any,
  82. "Allow hpsa driver to access unknown HP Smart Array hardware");
  83. static int hpsa_simple_mode;
  84. module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
  85. MODULE_PARM_DESC(hpsa_simple_mode,
  86. "Use 'simple mode' rather than 'performant mode'");
  87. /* define the PCI info for the cards we can control */
  88. static const struct pci_device_id hpsa_pci_device_id[] = {
  89. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
  90. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
  91. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
  92. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
  93. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
  94. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
  95. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
  96. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
  97. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
  98. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
  99. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
  100. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
  101. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
  102. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
  103. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
  104. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
  105. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
  106. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
  107. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
  108. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
  109. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
  110. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
  111. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
  112. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
  113. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
  114. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
  115. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
  116. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
  117. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
  118. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
  119. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
  120. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
  121. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
  122. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
  123. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
  124. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
  125. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
  126. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
  127. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
  128. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
  129. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
  130. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
  131. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
  132. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
  133. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
  134. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
  135. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
  136. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
  137. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
  138. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
  139. {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
  140. {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  141. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  142. {0,}
  143. };
  144. MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
  145. /* board_id = Subsystem Device ID & Vendor ID
  146. * product = Marketing Name for the board
  147. * access = Address of the struct of function pointers
  148. */
  149. static struct board_type products[] = {
  150. {0x3241103C, "Smart Array P212", &SA5_access},
  151. {0x3243103C, "Smart Array P410", &SA5_access},
  152. {0x3245103C, "Smart Array P410i", &SA5_access},
  153. {0x3247103C, "Smart Array P411", &SA5_access},
  154. {0x3249103C, "Smart Array P812", &SA5_access},
  155. {0x324A103C, "Smart Array P712m", &SA5_access},
  156. {0x324B103C, "Smart Array P711m", &SA5_access},
  157. {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
  158. {0x3350103C, "Smart Array P222", &SA5_access},
  159. {0x3351103C, "Smart Array P420", &SA5_access},
  160. {0x3352103C, "Smart Array P421", &SA5_access},
  161. {0x3353103C, "Smart Array P822", &SA5_access},
  162. {0x3354103C, "Smart Array P420i", &SA5_access},
  163. {0x3355103C, "Smart Array P220i", &SA5_access},
  164. {0x3356103C, "Smart Array P721m", &SA5_access},
  165. {0x1921103C, "Smart Array P830i", &SA5_access},
  166. {0x1922103C, "Smart Array P430", &SA5_access},
  167. {0x1923103C, "Smart Array P431", &SA5_access},
  168. {0x1924103C, "Smart Array P830", &SA5_access},
  169. {0x1926103C, "Smart Array P731m", &SA5_access},
  170. {0x1928103C, "Smart Array P230i", &SA5_access},
  171. {0x1929103C, "Smart Array P530", &SA5_access},
  172. {0x21BD103C, "Smart Array P244br", &SA5_access},
  173. {0x21BE103C, "Smart Array P741m", &SA5_access},
  174. {0x21BF103C, "Smart HBA H240ar", &SA5_access},
  175. {0x21C0103C, "Smart Array P440ar", &SA5_access},
  176. {0x21C1103C, "Smart Array P840ar", &SA5_access},
  177. {0x21C2103C, "Smart Array P440", &SA5_access},
  178. {0x21C3103C, "Smart Array P441", &SA5_access},
  179. {0x21C4103C, "Smart Array", &SA5_access},
  180. {0x21C5103C, "Smart Array P841", &SA5_access},
  181. {0x21C6103C, "Smart HBA H244br", &SA5_access},
  182. {0x21C7103C, "Smart HBA H240", &SA5_access},
  183. {0x21C8103C, "Smart HBA H241", &SA5_access},
  184. {0x21C9103C, "Smart Array", &SA5_access},
  185. {0x21CA103C, "Smart Array P246br", &SA5_access},
  186. {0x21CB103C, "Smart Array P840", &SA5_access},
  187. {0x21CC103C, "Smart Array", &SA5_access},
  188. {0x21CD103C, "Smart Array", &SA5_access},
  189. {0x21CE103C, "Smart HBA", &SA5_access},
  190. {0x05809005, "SmartHBA-SA", &SA5_access},
  191. {0x05819005, "SmartHBA-SA 8i", &SA5_access},
  192. {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
  193. {0x05839005, "SmartHBA-SA 8e", &SA5_access},
  194. {0x05849005, "SmartHBA-SA 16i", &SA5_access},
  195. {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
  196. {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
  197. {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
  198. {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
  199. {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
  200. {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
  201. {0xFFFF103C, "Unknown Smart Array", &SA5_access},
  202. };
  203. static struct scsi_transport_template *hpsa_sas_transport_template;
  204. static int hpsa_add_sas_host(struct ctlr_info *h);
  205. static void hpsa_delete_sas_host(struct ctlr_info *h);
  206. static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
  207. struct hpsa_scsi_dev_t *device);
  208. static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
  209. static struct hpsa_scsi_dev_t
  210. *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
  211. struct sas_rphy *rphy);
  212. #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
  213. static const struct scsi_cmnd hpsa_cmd_busy;
  214. #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
  215. static const struct scsi_cmnd hpsa_cmd_idle;
  216. static int number_of_controllers;
  217. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
  218. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
  219. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
  220. #ifdef CONFIG_COMPAT
  221. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
  222. void __user *arg);
  223. #endif
  224. static void cmd_free(struct ctlr_info *h, struct CommandList *c);
  225. static struct CommandList *cmd_alloc(struct ctlr_info *h);
  226. static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
  227. static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
  228. struct scsi_cmnd *scmd);
  229. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  230. void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
  231. int cmd_type);
  232. static void hpsa_free_cmd_pool(struct ctlr_info *h);
  233. #define VPD_PAGE (1 << 8)
  234. #define HPSA_SIMPLE_ERROR_BITS 0x03
  235. static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  236. static void hpsa_scan_start(struct Scsi_Host *);
  237. static int hpsa_scan_finished(struct Scsi_Host *sh,
  238. unsigned long elapsed_time);
  239. static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
  240. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
  241. static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
  242. static int hpsa_slave_alloc(struct scsi_device *sdev);
  243. static int hpsa_slave_configure(struct scsi_device *sdev);
  244. static void hpsa_slave_destroy(struct scsi_device *sdev);
  245. static void hpsa_update_scsi_devices(struct ctlr_info *h);
  246. static int check_for_unit_attention(struct ctlr_info *h,
  247. struct CommandList *c);
  248. static void check_ioctl_unit_attention(struct ctlr_info *h,
  249. struct CommandList *c);
  250. /* performant mode helper functions */
  251. static void calc_bucket_map(int *bucket, int num_buckets,
  252. int nsgs, int min_blocks, u32 *bucket_map);
  253. static void hpsa_free_performant_mode(struct ctlr_info *h);
  254. static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
  255. static inline u32 next_command(struct ctlr_info *h, u8 q);
  256. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  257. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  258. u64 *cfg_offset);
  259. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  260. unsigned long *memory_bar);
  261. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
  262. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  263. int wait_for_ready);
  264. static inline void finish_cmd(struct CommandList *c);
  265. static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
  266. #define BOARD_NOT_READY 0
  267. #define BOARD_READY 1
  268. static void hpsa_drain_accel_commands(struct ctlr_info *h);
  269. static void hpsa_flush_cache(struct ctlr_info *h);
  270. static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
  271. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  272. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
  273. static void hpsa_command_resubmit_worker(struct work_struct *work);
  274. static u32 lockup_detected(struct ctlr_info *h);
  275. static int detect_controller_lockup(struct ctlr_info *h);
  276. static void hpsa_disable_rld_caching(struct ctlr_info *h);
  277. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  278. struct ReportExtendedLUNdata *buf, int bufsize);
  279. static bool hpsa_vpd_page_supported(struct ctlr_info *h,
  280. unsigned char scsi3addr[], u8 page);
  281. static int hpsa_luns_changed(struct ctlr_info *h);
  282. static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
  283. struct hpsa_scsi_dev_t *dev,
  284. unsigned char *scsi3addr);
  285. static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
  286. {
  287. unsigned long *priv = shost_priv(sdev->host);
  288. return (struct ctlr_info *) *priv;
  289. }
  290. static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
  291. {
  292. unsigned long *priv = shost_priv(sh);
  293. return (struct ctlr_info *) *priv;
  294. }
  295. static inline bool hpsa_is_cmd_idle(struct CommandList *c)
  296. {
  297. return c->scsi_cmd == SCSI_CMD_IDLE;
  298. }
  299. static inline bool hpsa_is_pending_event(struct CommandList *c)
  300. {
  301. return c->abort_pending || c->reset_pending;
  302. }
  303. /* extract sense key, asc, and ascq from sense data. -1 means invalid. */
  304. static void decode_sense_data(const u8 *sense_data, int sense_data_len,
  305. u8 *sense_key, u8 *asc, u8 *ascq)
  306. {
  307. struct scsi_sense_hdr sshdr;
  308. bool rc;
  309. *sense_key = -1;
  310. *asc = -1;
  311. *ascq = -1;
  312. if (sense_data_len < 1)
  313. return;
  314. rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
  315. if (rc) {
  316. *sense_key = sshdr.sense_key;
  317. *asc = sshdr.asc;
  318. *ascq = sshdr.ascq;
  319. }
  320. }
  321. static int check_for_unit_attention(struct ctlr_info *h,
  322. struct CommandList *c)
  323. {
  324. u8 sense_key, asc, ascq;
  325. int sense_len;
  326. if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
  327. sense_len = sizeof(c->err_info->SenseInfo);
  328. else
  329. sense_len = c->err_info->SenseLen;
  330. decode_sense_data(c->err_info->SenseInfo, sense_len,
  331. &sense_key, &asc, &ascq);
  332. if (sense_key != UNIT_ATTENTION || asc == 0xff)
  333. return 0;
  334. switch (asc) {
  335. case STATE_CHANGED:
  336. dev_warn(&h->pdev->dev,
  337. "%s: a state change detected, command retried\n",
  338. h->devname);
  339. break;
  340. case LUN_FAILED:
  341. dev_warn(&h->pdev->dev,
  342. "%s: LUN failure detected\n", h->devname);
  343. break;
  344. case REPORT_LUNS_CHANGED:
  345. dev_warn(&h->pdev->dev,
  346. "%s: report LUN data changed\n", h->devname);
  347. /*
  348. * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
  349. * target (array) devices.
  350. */
  351. break;
  352. case POWER_OR_RESET:
  353. dev_warn(&h->pdev->dev,
  354. "%s: a power on or device reset detected\n",
  355. h->devname);
  356. break;
  357. case UNIT_ATTENTION_CLEARED:
  358. dev_warn(&h->pdev->dev,
  359. "%s: unit attention cleared by another initiator\n",
  360. h->devname);
  361. break;
  362. default:
  363. dev_warn(&h->pdev->dev,
  364. "%s: unknown unit attention detected\n",
  365. h->devname);
  366. break;
  367. }
  368. return 1;
  369. }
  370. static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
  371. {
  372. if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
  373. (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
  374. c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
  375. return 0;
  376. dev_warn(&h->pdev->dev, HPSA "device busy");
  377. return 1;
  378. }
  379. static u32 lockup_detected(struct ctlr_info *h);
  380. static ssize_t host_show_lockup_detected(struct device *dev,
  381. struct device_attribute *attr, char *buf)
  382. {
  383. int ld;
  384. struct ctlr_info *h;
  385. struct Scsi_Host *shost = class_to_shost(dev);
  386. h = shost_to_hba(shost);
  387. ld = lockup_detected(h);
  388. return sprintf(buf, "ld=%d\n", ld);
  389. }
  390. static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
  391. struct device_attribute *attr,
  392. const char *buf, size_t count)
  393. {
  394. int status, len;
  395. struct ctlr_info *h;
  396. struct Scsi_Host *shost = class_to_shost(dev);
  397. char tmpbuf[10];
  398. if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
  399. return -EACCES;
  400. len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
  401. strncpy(tmpbuf, buf, len);
  402. tmpbuf[len] = '\0';
  403. if (sscanf(tmpbuf, "%d", &status) != 1)
  404. return -EINVAL;
  405. h = shost_to_hba(shost);
  406. h->acciopath_status = !!status;
  407. dev_warn(&h->pdev->dev,
  408. "hpsa: HP SSD Smart Path %s via sysfs update.\n",
  409. h->acciopath_status ? "enabled" : "disabled");
  410. return count;
  411. }
  412. static ssize_t host_store_raid_offload_debug(struct device *dev,
  413. struct device_attribute *attr,
  414. const char *buf, size_t count)
  415. {
  416. int debug_level, len;
  417. struct ctlr_info *h;
  418. struct Scsi_Host *shost = class_to_shost(dev);
  419. char tmpbuf[10];
  420. if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
  421. return -EACCES;
  422. len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
  423. strncpy(tmpbuf, buf, len);
  424. tmpbuf[len] = '\0';
  425. if (sscanf(tmpbuf, "%d", &debug_level) != 1)
  426. return -EINVAL;
  427. if (debug_level < 0)
  428. debug_level = 0;
  429. h = shost_to_hba(shost);
  430. h->raid_offload_debug = debug_level;
  431. dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
  432. h->raid_offload_debug);
  433. return count;
  434. }
  435. static ssize_t host_store_rescan(struct device *dev,
  436. struct device_attribute *attr,
  437. const char *buf, size_t count)
  438. {
  439. struct ctlr_info *h;
  440. struct Scsi_Host *shost = class_to_shost(dev);
  441. h = shost_to_hba(shost);
  442. hpsa_scan_start(h->scsi_host);
  443. return count;
  444. }
  445. static ssize_t host_show_firmware_revision(struct device *dev,
  446. struct device_attribute *attr, char *buf)
  447. {
  448. struct ctlr_info *h;
  449. struct Scsi_Host *shost = class_to_shost(dev);
  450. unsigned char *fwrev;
  451. h = shost_to_hba(shost);
  452. if (!h->hba_inquiry_data)
  453. return 0;
  454. fwrev = &h->hba_inquiry_data[32];
  455. return snprintf(buf, 20, "%c%c%c%c\n",
  456. fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
  457. }
  458. static ssize_t host_show_commands_outstanding(struct device *dev,
  459. struct device_attribute *attr, char *buf)
  460. {
  461. struct Scsi_Host *shost = class_to_shost(dev);
  462. struct ctlr_info *h = shost_to_hba(shost);
  463. return snprintf(buf, 20, "%d\n",
  464. atomic_read(&h->commands_outstanding));
  465. }
  466. static ssize_t host_show_transport_mode(struct device *dev,
  467. struct device_attribute *attr, char *buf)
  468. {
  469. struct ctlr_info *h;
  470. struct Scsi_Host *shost = class_to_shost(dev);
  471. h = shost_to_hba(shost);
  472. return snprintf(buf, 20, "%s\n",
  473. h->transMethod & CFGTBL_Trans_Performant ?
  474. "performant" : "simple");
  475. }
  476. static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
  477. struct device_attribute *attr, char *buf)
  478. {
  479. struct ctlr_info *h;
  480. struct Scsi_Host *shost = class_to_shost(dev);
  481. h = shost_to_hba(shost);
  482. return snprintf(buf, 30, "HP SSD Smart Path %s\n",
  483. (h->acciopath_status == 1) ? "enabled" : "disabled");
  484. }
  485. /* List of controllers which cannot be hard reset on kexec with reset_devices */
  486. static u32 unresettable_controller[] = {
  487. 0x324a103C, /* Smart Array P712m */
  488. 0x324b103C, /* Smart Array P711m */
  489. 0x3223103C, /* Smart Array P800 */
  490. 0x3234103C, /* Smart Array P400 */
  491. 0x3235103C, /* Smart Array P400i */
  492. 0x3211103C, /* Smart Array E200i */
  493. 0x3212103C, /* Smart Array E200 */
  494. 0x3213103C, /* Smart Array E200i */
  495. 0x3214103C, /* Smart Array E200i */
  496. 0x3215103C, /* Smart Array E200i */
  497. 0x3237103C, /* Smart Array E500 */
  498. 0x323D103C, /* Smart Array P700m */
  499. 0x40800E11, /* Smart Array 5i */
  500. 0x409C0E11, /* Smart Array 6400 */
  501. 0x409D0E11, /* Smart Array 6400 EM */
  502. 0x40700E11, /* Smart Array 5300 */
  503. 0x40820E11, /* Smart Array 532 */
  504. 0x40830E11, /* Smart Array 5312 */
  505. 0x409A0E11, /* Smart Array 641 */
  506. 0x409B0E11, /* Smart Array 642 */
  507. 0x40910E11, /* Smart Array 6i */
  508. };
  509. /* List of controllers which cannot even be soft reset */
  510. static u32 soft_unresettable_controller[] = {
  511. 0x40800E11, /* Smart Array 5i */
  512. 0x40700E11, /* Smart Array 5300 */
  513. 0x40820E11, /* Smart Array 532 */
  514. 0x40830E11, /* Smart Array 5312 */
  515. 0x409A0E11, /* Smart Array 641 */
  516. 0x409B0E11, /* Smart Array 642 */
  517. 0x40910E11, /* Smart Array 6i */
  518. /* Exclude 640x boards. These are two pci devices in one slot
  519. * which share a battery backed cache module. One controls the
  520. * cache, the other accesses the cache through the one that controls
  521. * it. If we reset the one controlling the cache, the other will
  522. * likely not be happy. Just forbid resetting this conjoined mess.
  523. * The 640x isn't really supported by hpsa anyway.
  524. */
  525. 0x409C0E11, /* Smart Array 6400 */
  526. 0x409D0E11, /* Smart Array 6400 EM */
  527. };
  528. static u32 needs_abort_tags_swizzled[] = {
  529. 0x323D103C, /* Smart Array P700m */
  530. 0x324a103C, /* Smart Array P712m */
  531. 0x324b103C, /* SmartArray P711m */
  532. };
  533. static int board_id_in_array(u32 a[], int nelems, u32 board_id)
  534. {
  535. int i;
  536. for (i = 0; i < nelems; i++)
  537. if (a[i] == board_id)
  538. return 1;
  539. return 0;
  540. }
  541. static int ctlr_is_hard_resettable(u32 board_id)
  542. {
  543. return !board_id_in_array(unresettable_controller,
  544. ARRAY_SIZE(unresettable_controller), board_id);
  545. }
  546. static int ctlr_is_soft_resettable(u32 board_id)
  547. {
  548. return !board_id_in_array(soft_unresettable_controller,
  549. ARRAY_SIZE(soft_unresettable_controller), board_id);
  550. }
  551. static int ctlr_is_resettable(u32 board_id)
  552. {
  553. return ctlr_is_hard_resettable(board_id) ||
  554. ctlr_is_soft_resettable(board_id);
  555. }
  556. static int ctlr_needs_abort_tags_swizzled(u32 board_id)
  557. {
  558. return board_id_in_array(needs_abort_tags_swizzled,
  559. ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
  560. }
  561. static ssize_t host_show_resettable(struct device *dev,
  562. struct device_attribute *attr, char *buf)
  563. {
  564. struct ctlr_info *h;
  565. struct Scsi_Host *shost = class_to_shost(dev);
  566. h = shost_to_hba(shost);
  567. return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
  568. }
  569. static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
  570. {
  571. return (scsi3addr[3] & 0xC0) == 0x40;
  572. }
  573. static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
  574. "1(+0)ADM", "UNKNOWN", "PHYS DRV"
  575. };
  576. #define HPSA_RAID_0 0
  577. #define HPSA_RAID_4 1
  578. #define HPSA_RAID_1 2 /* also used for RAID 10 */
  579. #define HPSA_RAID_5 3 /* also used for RAID 50 */
  580. #define HPSA_RAID_51 4
  581. #define HPSA_RAID_6 5 /* also used for RAID 60 */
  582. #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
  583. #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
  584. #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
  585. static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
  586. {
  587. return !device->physical_device;
  588. }
  589. static ssize_t raid_level_show(struct device *dev,
  590. struct device_attribute *attr, char *buf)
  591. {
  592. ssize_t l = 0;
  593. unsigned char rlevel;
  594. struct ctlr_info *h;
  595. struct scsi_device *sdev;
  596. struct hpsa_scsi_dev_t *hdev;
  597. unsigned long flags;
  598. sdev = to_scsi_device(dev);
  599. h = sdev_to_hba(sdev);
  600. spin_lock_irqsave(&h->lock, flags);
  601. hdev = sdev->hostdata;
  602. if (!hdev) {
  603. spin_unlock_irqrestore(&h->lock, flags);
  604. return -ENODEV;
  605. }
  606. /* Is this even a logical drive? */
  607. if (!is_logical_device(hdev)) {
  608. spin_unlock_irqrestore(&h->lock, flags);
  609. l = snprintf(buf, PAGE_SIZE, "N/A\n");
  610. return l;
  611. }
  612. rlevel = hdev->raid_level;
  613. spin_unlock_irqrestore(&h->lock, flags);
  614. if (rlevel > RAID_UNKNOWN)
  615. rlevel = RAID_UNKNOWN;
  616. l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
  617. return l;
  618. }
  619. static ssize_t lunid_show(struct device *dev,
  620. struct device_attribute *attr, char *buf)
  621. {
  622. struct ctlr_info *h;
  623. struct scsi_device *sdev;
  624. struct hpsa_scsi_dev_t *hdev;
  625. unsigned long flags;
  626. unsigned char lunid[8];
  627. sdev = to_scsi_device(dev);
  628. h = sdev_to_hba(sdev);
  629. spin_lock_irqsave(&h->lock, flags);
  630. hdev = sdev->hostdata;
  631. if (!hdev) {
  632. spin_unlock_irqrestore(&h->lock, flags);
  633. return -ENODEV;
  634. }
  635. memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
  636. spin_unlock_irqrestore(&h->lock, flags);
  637. return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  638. lunid[0], lunid[1], lunid[2], lunid[3],
  639. lunid[4], lunid[5], lunid[6], lunid[7]);
  640. }
  641. static ssize_t unique_id_show(struct device *dev,
  642. struct device_attribute *attr, char *buf)
  643. {
  644. struct ctlr_info *h;
  645. struct scsi_device *sdev;
  646. struct hpsa_scsi_dev_t *hdev;
  647. unsigned long flags;
  648. unsigned char sn[16];
  649. sdev = to_scsi_device(dev);
  650. h = sdev_to_hba(sdev);
  651. spin_lock_irqsave(&h->lock, flags);
  652. hdev = sdev->hostdata;
  653. if (!hdev) {
  654. spin_unlock_irqrestore(&h->lock, flags);
  655. return -ENODEV;
  656. }
  657. memcpy(sn, hdev->device_id, sizeof(sn));
  658. spin_unlock_irqrestore(&h->lock, flags);
  659. return snprintf(buf, 16 * 2 + 2,
  660. "%02X%02X%02X%02X%02X%02X%02X%02X"
  661. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  662. sn[0], sn[1], sn[2], sn[3],
  663. sn[4], sn[5], sn[6], sn[7],
  664. sn[8], sn[9], sn[10], sn[11],
  665. sn[12], sn[13], sn[14], sn[15]);
  666. }
  667. static ssize_t sas_address_show(struct device *dev,
  668. struct device_attribute *attr, char *buf)
  669. {
  670. struct ctlr_info *h;
  671. struct scsi_device *sdev;
  672. struct hpsa_scsi_dev_t *hdev;
  673. unsigned long flags;
  674. u64 sas_address;
  675. sdev = to_scsi_device(dev);
  676. h = sdev_to_hba(sdev);
  677. spin_lock_irqsave(&h->lock, flags);
  678. hdev = sdev->hostdata;
  679. if (!hdev || is_logical_device(hdev) || !hdev->expose_device) {
  680. spin_unlock_irqrestore(&h->lock, flags);
  681. return -ENODEV;
  682. }
  683. sas_address = hdev->sas_address;
  684. spin_unlock_irqrestore(&h->lock, flags);
  685. return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address);
  686. }
  687. static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
  688. struct device_attribute *attr, char *buf)
  689. {
  690. struct ctlr_info *h;
  691. struct scsi_device *sdev;
  692. struct hpsa_scsi_dev_t *hdev;
  693. unsigned long flags;
  694. int offload_enabled;
  695. sdev = to_scsi_device(dev);
  696. h = sdev_to_hba(sdev);
  697. spin_lock_irqsave(&h->lock, flags);
  698. hdev = sdev->hostdata;
  699. if (!hdev) {
  700. spin_unlock_irqrestore(&h->lock, flags);
  701. return -ENODEV;
  702. }
  703. offload_enabled = hdev->offload_enabled;
  704. spin_unlock_irqrestore(&h->lock, flags);
  705. return snprintf(buf, 20, "%d\n", offload_enabled);
  706. }
  707. #define MAX_PATHS 8
  708. static ssize_t path_info_show(struct device *dev,
  709. struct device_attribute *attr, char *buf)
  710. {
  711. struct ctlr_info *h;
  712. struct scsi_device *sdev;
  713. struct hpsa_scsi_dev_t *hdev;
  714. unsigned long flags;
  715. int i;
  716. int output_len = 0;
  717. u8 box;
  718. u8 bay;
  719. u8 path_map_index = 0;
  720. char *active;
  721. unsigned char phys_connector[2];
  722. sdev = to_scsi_device(dev);
  723. h = sdev_to_hba(sdev);
  724. spin_lock_irqsave(&h->devlock, flags);
  725. hdev = sdev->hostdata;
  726. if (!hdev) {
  727. spin_unlock_irqrestore(&h->devlock, flags);
  728. return -ENODEV;
  729. }
  730. bay = hdev->bay;
  731. for (i = 0; i < MAX_PATHS; i++) {
  732. path_map_index = 1<<i;
  733. if (i == hdev->active_path_index)
  734. active = "Active";
  735. else if (hdev->path_map & path_map_index)
  736. active = "Inactive";
  737. else
  738. continue;
  739. output_len += scnprintf(buf + output_len,
  740. PAGE_SIZE - output_len,
  741. "[%d:%d:%d:%d] %20.20s ",
  742. h->scsi_host->host_no,
  743. hdev->bus, hdev->target, hdev->lun,
  744. scsi_device_type(hdev->devtype));
  745. if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) {
  746. output_len += scnprintf(buf + output_len,
  747. PAGE_SIZE - output_len,
  748. "%s\n", active);
  749. continue;
  750. }
  751. box = hdev->box[i];
  752. memcpy(&phys_connector, &hdev->phys_connector[i],
  753. sizeof(phys_connector));
  754. if (phys_connector[0] < '0')
  755. phys_connector[0] = '0';
  756. if (phys_connector[1] < '0')
  757. phys_connector[1] = '0';
  758. output_len += scnprintf(buf + output_len,
  759. PAGE_SIZE - output_len,
  760. "PORT: %.2s ",
  761. phys_connector);
  762. if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) &&
  763. hdev->expose_device) {
  764. if (box == 0 || box == 0xFF) {
  765. output_len += scnprintf(buf + output_len,
  766. PAGE_SIZE - output_len,
  767. "BAY: %hhu %s\n",
  768. bay, active);
  769. } else {
  770. output_len += scnprintf(buf + output_len,
  771. PAGE_SIZE - output_len,
  772. "BOX: %hhu BAY: %hhu %s\n",
  773. box, bay, active);
  774. }
  775. } else if (box != 0 && box != 0xFF) {
  776. output_len += scnprintf(buf + output_len,
  777. PAGE_SIZE - output_len, "BOX: %hhu %s\n",
  778. box, active);
  779. } else
  780. output_len += scnprintf(buf + output_len,
  781. PAGE_SIZE - output_len, "%s\n", active);
  782. }
  783. spin_unlock_irqrestore(&h->devlock, flags);
  784. return output_len;
  785. }
  786. static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
  787. static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
  788. static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
  789. static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
  790. static DEVICE_ATTR(sas_address, S_IRUGO, sas_address_show, NULL);
  791. static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
  792. host_show_hp_ssd_smart_path_enabled, NULL);
  793. static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
  794. static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
  795. host_show_hp_ssd_smart_path_status,
  796. host_store_hp_ssd_smart_path_status);
  797. static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
  798. host_store_raid_offload_debug);
  799. static DEVICE_ATTR(firmware_revision, S_IRUGO,
  800. host_show_firmware_revision, NULL);
  801. static DEVICE_ATTR(commands_outstanding, S_IRUGO,
  802. host_show_commands_outstanding, NULL);
  803. static DEVICE_ATTR(transport_mode, S_IRUGO,
  804. host_show_transport_mode, NULL);
  805. static DEVICE_ATTR(resettable, S_IRUGO,
  806. host_show_resettable, NULL);
  807. static DEVICE_ATTR(lockup_detected, S_IRUGO,
  808. host_show_lockup_detected, NULL);
  809. static struct device_attribute *hpsa_sdev_attrs[] = {
  810. &dev_attr_raid_level,
  811. &dev_attr_lunid,
  812. &dev_attr_unique_id,
  813. &dev_attr_hp_ssd_smart_path_enabled,
  814. &dev_attr_path_info,
  815. &dev_attr_sas_address,
  816. NULL,
  817. };
  818. static struct device_attribute *hpsa_shost_attrs[] = {
  819. &dev_attr_rescan,
  820. &dev_attr_firmware_revision,
  821. &dev_attr_commands_outstanding,
  822. &dev_attr_transport_mode,
  823. &dev_attr_resettable,
  824. &dev_attr_hp_ssd_smart_path_status,
  825. &dev_attr_raid_offload_debug,
  826. &dev_attr_lockup_detected,
  827. NULL,
  828. };
  829. #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
  830. HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
  831. static struct scsi_host_template hpsa_driver_template = {
  832. .module = THIS_MODULE,
  833. .name = HPSA,
  834. .proc_name = HPSA,
  835. .queuecommand = hpsa_scsi_queue_command,
  836. .scan_start = hpsa_scan_start,
  837. .scan_finished = hpsa_scan_finished,
  838. .change_queue_depth = hpsa_change_queue_depth,
  839. .this_id = -1,
  840. .use_clustering = ENABLE_CLUSTERING,
  841. .eh_abort_handler = hpsa_eh_abort_handler,
  842. .eh_device_reset_handler = hpsa_eh_device_reset_handler,
  843. .ioctl = hpsa_ioctl,
  844. .slave_alloc = hpsa_slave_alloc,
  845. .slave_configure = hpsa_slave_configure,
  846. .slave_destroy = hpsa_slave_destroy,
  847. #ifdef CONFIG_COMPAT
  848. .compat_ioctl = hpsa_compat_ioctl,
  849. #endif
  850. .sdev_attrs = hpsa_sdev_attrs,
  851. .shost_attrs = hpsa_shost_attrs,
  852. .max_sectors = 8192,
  853. .no_write_same = 1,
  854. };
  855. static inline u32 next_command(struct ctlr_info *h, u8 q)
  856. {
  857. u32 a;
  858. struct reply_queue_buffer *rq = &h->reply_queue[q];
  859. if (h->transMethod & CFGTBL_Trans_io_accel1)
  860. return h->access.command_completed(h, q);
  861. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  862. return h->access.command_completed(h, q);
  863. if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
  864. a = rq->head[rq->current_entry];
  865. rq->current_entry++;
  866. atomic_dec(&h->commands_outstanding);
  867. } else {
  868. a = FIFO_EMPTY;
  869. }
  870. /* Check for wraparound */
  871. if (rq->current_entry == h->max_commands) {
  872. rq->current_entry = 0;
  873. rq->wraparound ^= 1;
  874. }
  875. return a;
  876. }
  877. /*
  878. * There are some special bits in the bus address of the
  879. * command that we have to set for the controller to know
  880. * how to process the command:
  881. *
  882. * Normal performant mode:
  883. * bit 0: 1 means performant mode, 0 means simple mode.
  884. * bits 1-3 = block fetch table entry
  885. * bits 4-6 = command type (== 0)
  886. *
  887. * ioaccel1 mode:
  888. * bit 0 = "performant mode" bit.
  889. * bits 1-3 = block fetch table entry
  890. * bits 4-6 = command type (== 110)
  891. * (command type is needed because ioaccel1 mode
  892. * commands are submitted through the same register as normal
  893. * mode commands, so this is how the controller knows whether
  894. * the command is normal mode or ioaccel1 mode.)
  895. *
  896. * ioaccel2 mode:
  897. * bit 0 = "performant mode" bit.
  898. * bits 1-4 = block fetch table entry (note extra bit)
  899. * bits 4-6 = not needed, because ioaccel2 mode has
  900. * a separate special register for submitting commands.
  901. */
  902. /*
  903. * set_performant_mode: Modify the tag for cciss performant
  904. * set bit 0 for pull model, bits 3-1 for block fetch
  905. * register number
  906. */
  907. #define DEFAULT_REPLY_QUEUE (-1)
  908. static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
  909. int reply_queue)
  910. {
  911. if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
  912. c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
  913. if (unlikely(!h->msix_vector))
  914. return;
  915. if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
  916. c->Header.ReplyQueue =
  917. raw_smp_processor_id() % h->nreply_queues;
  918. else
  919. c->Header.ReplyQueue = reply_queue % h->nreply_queues;
  920. }
  921. }
  922. static void set_ioaccel1_performant_mode(struct ctlr_info *h,
  923. struct CommandList *c,
  924. int reply_queue)
  925. {
  926. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
  927. /*
  928. * Tell the controller to post the reply to the queue for this
  929. * processor. This seems to give the best I/O throughput.
  930. */
  931. if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
  932. cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
  933. else
  934. cp->ReplyQueue = reply_queue % h->nreply_queues;
  935. /*
  936. * Set the bits in the address sent down to include:
  937. * - performant mode bit (bit 0)
  938. * - pull count (bits 1-3)
  939. * - command type (bits 4-6)
  940. */
  941. c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
  942. IOACCEL1_BUSADDR_CMDTYPE;
  943. }
  944. static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
  945. struct CommandList *c,
  946. int reply_queue)
  947. {
  948. struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
  949. &h->ioaccel2_cmd_pool[c->cmdindex];
  950. /* Tell the controller to post the reply to the queue for this
  951. * processor. This seems to give the best I/O throughput.
  952. */
  953. if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
  954. cp->reply_queue = smp_processor_id() % h->nreply_queues;
  955. else
  956. cp->reply_queue = reply_queue % h->nreply_queues;
  957. /* Set the bits in the address sent down to include:
  958. * - performant mode bit not used in ioaccel mode 2
  959. * - pull count (bits 0-3)
  960. * - command type isn't needed for ioaccel2
  961. */
  962. c->busaddr |= h->ioaccel2_blockFetchTable[0];
  963. }
  964. static void set_ioaccel2_performant_mode(struct ctlr_info *h,
  965. struct CommandList *c,
  966. int reply_queue)
  967. {
  968. struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
  969. /*
  970. * Tell the controller to post the reply to the queue for this
  971. * processor. This seems to give the best I/O throughput.
  972. */
  973. if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
  974. cp->reply_queue = smp_processor_id() % h->nreply_queues;
  975. else
  976. cp->reply_queue = reply_queue % h->nreply_queues;
  977. /*
  978. * Set the bits in the address sent down to include:
  979. * - performant mode bit not used in ioaccel mode 2
  980. * - pull count (bits 0-3)
  981. * - command type isn't needed for ioaccel2
  982. */
  983. c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
  984. }
  985. static int is_firmware_flash_cmd(u8 *cdb)
  986. {
  987. return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
  988. }
  989. /*
  990. * During firmware flash, the heartbeat register may not update as frequently
  991. * as it should. So we dial down lockup detection during firmware flash. and
  992. * dial it back up when firmware flash completes.
  993. */
  994. #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
  995. #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
  996. static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
  997. struct CommandList *c)
  998. {
  999. if (!is_firmware_flash_cmd(c->Request.CDB))
  1000. return;
  1001. atomic_inc(&h->firmware_flash_in_progress);
  1002. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
  1003. }
  1004. static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
  1005. struct CommandList *c)
  1006. {
  1007. if (is_firmware_flash_cmd(c->Request.CDB) &&
  1008. atomic_dec_and_test(&h->firmware_flash_in_progress))
  1009. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  1010. }
  1011. static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
  1012. struct CommandList *c, int reply_queue)
  1013. {
  1014. dial_down_lockup_detection_during_fw_flash(h, c);
  1015. atomic_inc(&h->commands_outstanding);
  1016. switch (c->cmd_type) {
  1017. case CMD_IOACCEL1:
  1018. set_ioaccel1_performant_mode(h, c, reply_queue);
  1019. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  1020. break;
  1021. case CMD_IOACCEL2:
  1022. set_ioaccel2_performant_mode(h, c, reply_queue);
  1023. writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
  1024. break;
  1025. case IOACCEL2_TMF:
  1026. set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
  1027. writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
  1028. break;
  1029. default:
  1030. set_performant_mode(h, c, reply_queue);
  1031. h->access.submit_command(h, c);
  1032. }
  1033. }
  1034. static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
  1035. {
  1036. if (unlikely(hpsa_is_pending_event(c)))
  1037. return finish_cmd(c);
  1038. __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
  1039. }
  1040. static inline int is_hba_lunid(unsigned char scsi3addr[])
  1041. {
  1042. return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
  1043. }
  1044. static inline int is_scsi_rev_5(struct ctlr_info *h)
  1045. {
  1046. if (!h->hba_inquiry_data)
  1047. return 0;
  1048. if ((h->hba_inquiry_data[2] & 0x07) == 5)
  1049. return 1;
  1050. return 0;
  1051. }
  1052. static int hpsa_find_target_lun(struct ctlr_info *h,
  1053. unsigned char scsi3addr[], int bus, int *target, int *lun)
  1054. {
  1055. /* finds an unused bus, target, lun for a new physical device
  1056. * assumes h->devlock is held
  1057. */
  1058. int i, found = 0;
  1059. DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
  1060. bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
  1061. for (i = 0; i < h->ndevices; i++) {
  1062. if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
  1063. __set_bit(h->dev[i]->target, lun_taken);
  1064. }
  1065. i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
  1066. if (i < HPSA_MAX_DEVICES) {
  1067. /* *bus = 1; */
  1068. *target = i;
  1069. *lun = 0;
  1070. found = 1;
  1071. }
  1072. return !found;
  1073. }
  1074. static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
  1075. struct hpsa_scsi_dev_t *dev, char *description)
  1076. {
  1077. #define LABEL_SIZE 25
  1078. char label[LABEL_SIZE];
  1079. if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
  1080. return;
  1081. switch (dev->devtype) {
  1082. case TYPE_RAID:
  1083. snprintf(label, LABEL_SIZE, "controller");
  1084. break;
  1085. case TYPE_ENCLOSURE:
  1086. snprintf(label, LABEL_SIZE, "enclosure");
  1087. break;
  1088. case TYPE_DISK:
  1089. case TYPE_ZBC:
  1090. if (dev->external)
  1091. snprintf(label, LABEL_SIZE, "external");
  1092. else if (!is_logical_dev_addr_mode(dev->scsi3addr))
  1093. snprintf(label, LABEL_SIZE, "%s",
  1094. raid_label[PHYSICAL_DRIVE]);
  1095. else
  1096. snprintf(label, LABEL_SIZE, "RAID-%s",
  1097. dev->raid_level > RAID_UNKNOWN ? "?" :
  1098. raid_label[dev->raid_level]);
  1099. break;
  1100. case TYPE_ROM:
  1101. snprintf(label, LABEL_SIZE, "rom");
  1102. break;
  1103. case TYPE_TAPE:
  1104. snprintf(label, LABEL_SIZE, "tape");
  1105. break;
  1106. case TYPE_MEDIUM_CHANGER:
  1107. snprintf(label, LABEL_SIZE, "changer");
  1108. break;
  1109. default:
  1110. snprintf(label, LABEL_SIZE, "UNKNOWN");
  1111. break;
  1112. }
  1113. dev_printk(level, &h->pdev->dev,
  1114. "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
  1115. h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
  1116. description,
  1117. scsi_device_type(dev->devtype),
  1118. dev->vendor,
  1119. dev->model,
  1120. label,
  1121. dev->offload_config ? '+' : '-',
  1122. dev->offload_enabled ? '+' : '-',
  1123. dev->expose_device);
  1124. }
  1125. /* Add an entry into h->dev[] array. */
  1126. static int hpsa_scsi_add_entry(struct ctlr_info *h,
  1127. struct hpsa_scsi_dev_t *device,
  1128. struct hpsa_scsi_dev_t *added[], int *nadded)
  1129. {
  1130. /* assumes h->devlock is held */
  1131. int n = h->ndevices;
  1132. int i;
  1133. unsigned char addr1[8], addr2[8];
  1134. struct hpsa_scsi_dev_t *sd;
  1135. if (n >= HPSA_MAX_DEVICES) {
  1136. dev_err(&h->pdev->dev, "too many devices, some will be "
  1137. "inaccessible.\n");
  1138. return -1;
  1139. }
  1140. /* physical devices do not have lun or target assigned until now. */
  1141. if (device->lun != -1)
  1142. /* Logical device, lun is already assigned. */
  1143. goto lun_assigned;
  1144. /* If this device a non-zero lun of a multi-lun device
  1145. * byte 4 of the 8-byte LUN addr will contain the logical
  1146. * unit no, zero otherwise.
  1147. */
  1148. if (device->scsi3addr[4] == 0) {
  1149. /* This is not a non-zero lun of a multi-lun device */
  1150. if (hpsa_find_target_lun(h, device->scsi3addr,
  1151. device->bus, &device->target, &device->lun) != 0)
  1152. return -1;
  1153. goto lun_assigned;
  1154. }
  1155. /* This is a non-zero lun of a multi-lun device.
  1156. * Search through our list and find the device which
  1157. * has the same 8 byte LUN address, excepting byte 4 and 5.
  1158. * Assign the same bus and target for this new LUN.
  1159. * Use the logical unit number from the firmware.
  1160. */
  1161. memcpy(addr1, device->scsi3addr, 8);
  1162. addr1[4] = 0;
  1163. addr1[5] = 0;
  1164. for (i = 0; i < n; i++) {
  1165. sd = h->dev[i];
  1166. memcpy(addr2, sd->scsi3addr, 8);
  1167. addr2[4] = 0;
  1168. addr2[5] = 0;
  1169. /* differ only in byte 4 and 5? */
  1170. if (memcmp(addr1, addr2, 8) == 0) {
  1171. device->bus = sd->bus;
  1172. device->target = sd->target;
  1173. device->lun = device->scsi3addr[4];
  1174. break;
  1175. }
  1176. }
  1177. if (device->lun == -1) {
  1178. dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
  1179. " suspect firmware bug or unsupported hardware "
  1180. "configuration.\n");
  1181. return -1;
  1182. }
  1183. lun_assigned:
  1184. h->dev[n] = device;
  1185. h->ndevices++;
  1186. added[*nadded] = device;
  1187. (*nadded)++;
  1188. hpsa_show_dev_msg(KERN_INFO, h, device,
  1189. device->expose_device ? "added" : "masked");
  1190. device->offload_to_be_enabled = device->offload_enabled;
  1191. device->offload_enabled = 0;
  1192. return 0;
  1193. }
  1194. /* Update an entry in h->dev[] array. */
  1195. static void hpsa_scsi_update_entry(struct ctlr_info *h,
  1196. int entry, struct hpsa_scsi_dev_t *new_entry)
  1197. {
  1198. int offload_enabled;
  1199. /* assumes h->devlock is held */
  1200. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1201. /* Raid level changed. */
  1202. h->dev[entry]->raid_level = new_entry->raid_level;
  1203. /* Raid offload parameters changed. Careful about the ordering. */
  1204. if (new_entry->offload_config && new_entry->offload_enabled) {
  1205. /*
  1206. * if drive is newly offload_enabled, we want to copy the
  1207. * raid map data first. If previously offload_enabled and
  1208. * offload_config were set, raid map data had better be
  1209. * the same as it was before. if raid map data is changed
  1210. * then it had better be the case that
  1211. * h->dev[entry]->offload_enabled is currently 0.
  1212. */
  1213. h->dev[entry]->raid_map = new_entry->raid_map;
  1214. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1215. }
  1216. if (new_entry->hba_ioaccel_enabled) {
  1217. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1218. wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
  1219. }
  1220. h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
  1221. h->dev[entry]->offload_config = new_entry->offload_config;
  1222. h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
  1223. h->dev[entry]->queue_depth = new_entry->queue_depth;
  1224. /*
  1225. * We can turn off ioaccel offload now, but need to delay turning
  1226. * it on until we can update h->dev[entry]->phys_disk[], but we
  1227. * can't do that until all the devices are updated.
  1228. */
  1229. h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
  1230. if (!new_entry->offload_enabled)
  1231. h->dev[entry]->offload_enabled = 0;
  1232. offload_enabled = h->dev[entry]->offload_enabled;
  1233. h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
  1234. hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
  1235. h->dev[entry]->offload_enabled = offload_enabled;
  1236. }
  1237. /* Replace an entry from h->dev[] array. */
  1238. static void hpsa_scsi_replace_entry(struct ctlr_info *h,
  1239. int entry, struct hpsa_scsi_dev_t *new_entry,
  1240. struct hpsa_scsi_dev_t *added[], int *nadded,
  1241. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  1242. {
  1243. /* assumes h->devlock is held */
  1244. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1245. removed[*nremoved] = h->dev[entry];
  1246. (*nremoved)++;
  1247. /*
  1248. * New physical devices won't have target/lun assigned yet
  1249. * so we need to preserve the values in the slot we are replacing.
  1250. */
  1251. if (new_entry->target == -1) {
  1252. new_entry->target = h->dev[entry]->target;
  1253. new_entry->lun = h->dev[entry]->lun;
  1254. }
  1255. h->dev[entry] = new_entry;
  1256. added[*nadded] = new_entry;
  1257. (*nadded)++;
  1258. hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
  1259. new_entry->offload_to_be_enabled = new_entry->offload_enabled;
  1260. new_entry->offload_enabled = 0;
  1261. }
  1262. /* Remove an entry from h->dev[] array. */
  1263. static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
  1264. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  1265. {
  1266. /* assumes h->devlock is held */
  1267. int i;
  1268. struct hpsa_scsi_dev_t *sd;
  1269. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1270. sd = h->dev[entry];
  1271. removed[*nremoved] = h->dev[entry];
  1272. (*nremoved)++;
  1273. for (i = entry; i < h->ndevices-1; i++)
  1274. h->dev[i] = h->dev[i+1];
  1275. h->ndevices--;
  1276. hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
  1277. }
  1278. #define SCSI3ADDR_EQ(a, b) ( \
  1279. (a)[7] == (b)[7] && \
  1280. (a)[6] == (b)[6] && \
  1281. (a)[5] == (b)[5] && \
  1282. (a)[4] == (b)[4] && \
  1283. (a)[3] == (b)[3] && \
  1284. (a)[2] == (b)[2] && \
  1285. (a)[1] == (b)[1] && \
  1286. (a)[0] == (b)[0])
  1287. static void fixup_botched_add(struct ctlr_info *h,
  1288. struct hpsa_scsi_dev_t *added)
  1289. {
  1290. /* called when scsi_add_device fails in order to re-adjust
  1291. * h->dev[] to match the mid layer's view.
  1292. */
  1293. unsigned long flags;
  1294. int i, j;
  1295. spin_lock_irqsave(&h->lock, flags);
  1296. for (i = 0; i < h->ndevices; i++) {
  1297. if (h->dev[i] == added) {
  1298. for (j = i; j < h->ndevices-1; j++)
  1299. h->dev[j] = h->dev[j+1];
  1300. h->ndevices--;
  1301. break;
  1302. }
  1303. }
  1304. spin_unlock_irqrestore(&h->lock, flags);
  1305. kfree(added);
  1306. }
  1307. static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
  1308. struct hpsa_scsi_dev_t *dev2)
  1309. {
  1310. /* we compare everything except lun and target as these
  1311. * are not yet assigned. Compare parts likely
  1312. * to differ first
  1313. */
  1314. if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
  1315. sizeof(dev1->scsi3addr)) != 0)
  1316. return 0;
  1317. if (memcmp(dev1->device_id, dev2->device_id,
  1318. sizeof(dev1->device_id)) != 0)
  1319. return 0;
  1320. if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
  1321. return 0;
  1322. if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
  1323. return 0;
  1324. if (dev1->devtype != dev2->devtype)
  1325. return 0;
  1326. if (dev1->bus != dev2->bus)
  1327. return 0;
  1328. return 1;
  1329. }
  1330. static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
  1331. struct hpsa_scsi_dev_t *dev2)
  1332. {
  1333. /* Device attributes that can change, but don't mean
  1334. * that the device is a different device, nor that the OS
  1335. * needs to be told anything about the change.
  1336. */
  1337. if (dev1->raid_level != dev2->raid_level)
  1338. return 1;
  1339. if (dev1->offload_config != dev2->offload_config)
  1340. return 1;
  1341. if (dev1->offload_enabled != dev2->offload_enabled)
  1342. return 1;
  1343. if (!is_logical_dev_addr_mode(dev1->scsi3addr))
  1344. if (dev1->queue_depth != dev2->queue_depth)
  1345. return 1;
  1346. return 0;
  1347. }
  1348. /* Find needle in haystack. If exact match found, return DEVICE_SAME,
  1349. * and return needle location in *index. If scsi3addr matches, but not
  1350. * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
  1351. * location in *index.
  1352. * In the case of a minor device attribute change, such as RAID level, just
  1353. * return DEVICE_UPDATED, along with the updated device's location in index.
  1354. * If needle not found, return DEVICE_NOT_FOUND.
  1355. */
  1356. static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
  1357. struct hpsa_scsi_dev_t *haystack[], int haystack_size,
  1358. int *index)
  1359. {
  1360. int i;
  1361. #define DEVICE_NOT_FOUND 0
  1362. #define DEVICE_CHANGED 1
  1363. #define DEVICE_SAME 2
  1364. #define DEVICE_UPDATED 3
  1365. if (needle == NULL)
  1366. return DEVICE_NOT_FOUND;
  1367. for (i = 0; i < haystack_size; i++) {
  1368. if (haystack[i] == NULL) /* previously removed. */
  1369. continue;
  1370. if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
  1371. *index = i;
  1372. if (device_is_the_same(needle, haystack[i])) {
  1373. if (device_updated(needle, haystack[i]))
  1374. return DEVICE_UPDATED;
  1375. return DEVICE_SAME;
  1376. } else {
  1377. /* Keep offline devices offline */
  1378. if (needle->volume_offline)
  1379. return DEVICE_NOT_FOUND;
  1380. return DEVICE_CHANGED;
  1381. }
  1382. }
  1383. }
  1384. *index = -1;
  1385. return DEVICE_NOT_FOUND;
  1386. }
  1387. static void hpsa_monitor_offline_device(struct ctlr_info *h,
  1388. unsigned char scsi3addr[])
  1389. {
  1390. struct offline_device_entry *device;
  1391. unsigned long flags;
  1392. /* Check to see if device is already on the list */
  1393. spin_lock_irqsave(&h->offline_device_lock, flags);
  1394. list_for_each_entry(device, &h->offline_device_list, offline_list) {
  1395. if (memcmp(device->scsi3addr, scsi3addr,
  1396. sizeof(device->scsi3addr)) == 0) {
  1397. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1398. return;
  1399. }
  1400. }
  1401. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1402. /* Device is not on the list, add it. */
  1403. device = kmalloc(sizeof(*device), GFP_KERNEL);
  1404. if (!device) {
  1405. dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
  1406. return;
  1407. }
  1408. memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
  1409. spin_lock_irqsave(&h->offline_device_lock, flags);
  1410. list_add_tail(&device->offline_list, &h->offline_device_list);
  1411. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1412. }
  1413. /* Print a message explaining various offline volume states */
  1414. static void hpsa_show_volume_status(struct ctlr_info *h,
  1415. struct hpsa_scsi_dev_t *sd)
  1416. {
  1417. if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
  1418. dev_info(&h->pdev->dev,
  1419. "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
  1420. h->scsi_host->host_no,
  1421. sd->bus, sd->target, sd->lun);
  1422. switch (sd->volume_offline) {
  1423. case HPSA_LV_OK:
  1424. break;
  1425. case HPSA_LV_UNDERGOING_ERASE:
  1426. dev_info(&h->pdev->dev,
  1427. "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
  1428. h->scsi_host->host_no,
  1429. sd->bus, sd->target, sd->lun);
  1430. break;
  1431. case HPSA_LV_NOT_AVAILABLE:
  1432. dev_info(&h->pdev->dev,
  1433. "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
  1434. h->scsi_host->host_no,
  1435. sd->bus, sd->target, sd->lun);
  1436. break;
  1437. case HPSA_LV_UNDERGOING_RPI:
  1438. dev_info(&h->pdev->dev,
  1439. "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
  1440. h->scsi_host->host_no,
  1441. sd->bus, sd->target, sd->lun);
  1442. break;
  1443. case HPSA_LV_PENDING_RPI:
  1444. dev_info(&h->pdev->dev,
  1445. "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
  1446. h->scsi_host->host_no,
  1447. sd->bus, sd->target, sd->lun);
  1448. break;
  1449. case HPSA_LV_ENCRYPTED_NO_KEY:
  1450. dev_info(&h->pdev->dev,
  1451. "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
  1452. h->scsi_host->host_no,
  1453. sd->bus, sd->target, sd->lun);
  1454. break;
  1455. case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
  1456. dev_info(&h->pdev->dev,
  1457. "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
  1458. h->scsi_host->host_no,
  1459. sd->bus, sd->target, sd->lun);
  1460. break;
  1461. case HPSA_LV_UNDERGOING_ENCRYPTION:
  1462. dev_info(&h->pdev->dev,
  1463. "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
  1464. h->scsi_host->host_no,
  1465. sd->bus, sd->target, sd->lun);
  1466. break;
  1467. case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
  1468. dev_info(&h->pdev->dev,
  1469. "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
  1470. h->scsi_host->host_no,
  1471. sd->bus, sd->target, sd->lun);
  1472. break;
  1473. case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  1474. dev_info(&h->pdev->dev,
  1475. "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
  1476. h->scsi_host->host_no,
  1477. sd->bus, sd->target, sd->lun);
  1478. break;
  1479. case HPSA_LV_PENDING_ENCRYPTION:
  1480. dev_info(&h->pdev->dev,
  1481. "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
  1482. h->scsi_host->host_no,
  1483. sd->bus, sd->target, sd->lun);
  1484. break;
  1485. case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
  1486. dev_info(&h->pdev->dev,
  1487. "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
  1488. h->scsi_host->host_no,
  1489. sd->bus, sd->target, sd->lun);
  1490. break;
  1491. }
  1492. }
  1493. /*
  1494. * Figure the list of physical drive pointers for a logical drive with
  1495. * raid offload configured.
  1496. */
  1497. static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
  1498. struct hpsa_scsi_dev_t *dev[], int ndevices,
  1499. struct hpsa_scsi_dev_t *logical_drive)
  1500. {
  1501. struct raid_map_data *map = &logical_drive->raid_map;
  1502. struct raid_map_disk_data *dd = &map->data[0];
  1503. int i, j;
  1504. int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
  1505. le16_to_cpu(map->metadata_disks_per_row);
  1506. int nraid_map_entries = le16_to_cpu(map->row_cnt) *
  1507. le16_to_cpu(map->layout_map_count) *
  1508. total_disks_per_row;
  1509. int nphys_disk = le16_to_cpu(map->layout_map_count) *
  1510. total_disks_per_row;
  1511. int qdepth;
  1512. if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
  1513. nraid_map_entries = RAID_MAP_MAX_ENTRIES;
  1514. logical_drive->nphysical_disks = nraid_map_entries;
  1515. qdepth = 0;
  1516. for (i = 0; i < nraid_map_entries; i++) {
  1517. logical_drive->phys_disk[i] = NULL;
  1518. if (!logical_drive->offload_config)
  1519. continue;
  1520. for (j = 0; j < ndevices; j++) {
  1521. if (dev[j] == NULL)
  1522. continue;
  1523. if (dev[j]->devtype != TYPE_DISK &&
  1524. dev[j]->devtype != TYPE_ZBC)
  1525. continue;
  1526. if (is_logical_device(dev[j]))
  1527. continue;
  1528. if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
  1529. continue;
  1530. logical_drive->phys_disk[i] = dev[j];
  1531. if (i < nphys_disk)
  1532. qdepth = min(h->nr_cmds, qdepth +
  1533. logical_drive->phys_disk[i]->queue_depth);
  1534. break;
  1535. }
  1536. /*
  1537. * This can happen if a physical drive is removed and
  1538. * the logical drive is degraded. In that case, the RAID
  1539. * map data will refer to a physical disk which isn't actually
  1540. * present. And in that case offload_enabled should already
  1541. * be 0, but we'll turn it off here just in case
  1542. */
  1543. if (!logical_drive->phys_disk[i]) {
  1544. logical_drive->offload_enabled = 0;
  1545. logical_drive->offload_to_be_enabled = 0;
  1546. logical_drive->queue_depth = 8;
  1547. }
  1548. }
  1549. if (nraid_map_entries)
  1550. /*
  1551. * This is correct for reads, too high for full stripe writes,
  1552. * way too high for partial stripe writes
  1553. */
  1554. logical_drive->queue_depth = qdepth;
  1555. else
  1556. logical_drive->queue_depth = h->nr_cmds;
  1557. }
  1558. static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
  1559. struct hpsa_scsi_dev_t *dev[], int ndevices)
  1560. {
  1561. int i;
  1562. for (i = 0; i < ndevices; i++) {
  1563. if (dev[i] == NULL)
  1564. continue;
  1565. if (dev[i]->devtype != TYPE_DISK &&
  1566. dev[i]->devtype != TYPE_ZBC)
  1567. continue;
  1568. if (!is_logical_device(dev[i]))
  1569. continue;
  1570. /*
  1571. * If offload is currently enabled, the RAID map and
  1572. * phys_disk[] assignment *better* not be changing
  1573. * and since it isn't changing, we do not need to
  1574. * update it.
  1575. */
  1576. if (dev[i]->offload_enabled)
  1577. continue;
  1578. hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
  1579. }
  1580. }
  1581. static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
  1582. {
  1583. int rc = 0;
  1584. if (!h->scsi_host)
  1585. return 1;
  1586. if (is_logical_device(device)) /* RAID */
  1587. rc = scsi_add_device(h->scsi_host, device->bus,
  1588. device->target, device->lun);
  1589. else /* HBA */
  1590. rc = hpsa_add_sas_device(h->sas_host, device);
  1591. return rc;
  1592. }
  1593. static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h,
  1594. struct hpsa_scsi_dev_t *dev)
  1595. {
  1596. int i;
  1597. int count = 0;
  1598. for (i = 0; i < h->nr_cmds; i++) {
  1599. struct CommandList *c = h->cmd_pool + i;
  1600. int refcount = atomic_inc_return(&c->refcount);
  1601. if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev,
  1602. dev->scsi3addr)) {
  1603. unsigned long flags;
  1604. spin_lock_irqsave(&h->lock, flags); /* Implied MB */
  1605. if (!hpsa_is_cmd_idle(c))
  1606. ++count;
  1607. spin_unlock_irqrestore(&h->lock, flags);
  1608. }
  1609. cmd_free(h, c);
  1610. }
  1611. return count;
  1612. }
  1613. static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h,
  1614. struct hpsa_scsi_dev_t *device)
  1615. {
  1616. int cmds = 0;
  1617. int waits = 0;
  1618. while (1) {
  1619. cmds = hpsa_find_outstanding_commands_for_dev(h, device);
  1620. if (cmds == 0)
  1621. break;
  1622. if (++waits > 20)
  1623. break;
  1624. dev_warn(&h->pdev->dev,
  1625. "%s: removing device with %d outstanding commands!\n",
  1626. __func__, cmds);
  1627. msleep(1000);
  1628. }
  1629. }
  1630. static void hpsa_remove_device(struct ctlr_info *h,
  1631. struct hpsa_scsi_dev_t *device)
  1632. {
  1633. struct scsi_device *sdev = NULL;
  1634. if (!h->scsi_host)
  1635. return;
  1636. if (is_logical_device(device)) { /* RAID */
  1637. sdev = scsi_device_lookup(h->scsi_host, device->bus,
  1638. device->target, device->lun);
  1639. if (sdev) {
  1640. scsi_remove_device(sdev);
  1641. scsi_device_put(sdev);
  1642. } else {
  1643. /*
  1644. * We don't expect to get here. Future commands
  1645. * to this device will get a selection timeout as
  1646. * if the device were gone.
  1647. */
  1648. hpsa_show_dev_msg(KERN_WARNING, h, device,
  1649. "didn't find device for removal.");
  1650. }
  1651. } else { /* HBA */
  1652. device->removed = 1;
  1653. hpsa_wait_for_outstanding_commands_for_dev(h, device);
  1654. hpsa_remove_sas_device(device);
  1655. }
  1656. }
  1657. static void adjust_hpsa_scsi_table(struct ctlr_info *h,
  1658. struct hpsa_scsi_dev_t *sd[], int nsds)
  1659. {
  1660. /* sd contains scsi3 addresses and devtypes, and inquiry
  1661. * data. This function takes what's in sd to be the current
  1662. * reality and updates h->dev[] to reflect that reality.
  1663. */
  1664. int i, entry, device_change, changes = 0;
  1665. struct hpsa_scsi_dev_t *csd;
  1666. unsigned long flags;
  1667. struct hpsa_scsi_dev_t **added, **removed;
  1668. int nadded, nremoved;
  1669. /*
  1670. * A reset can cause a device status to change
  1671. * re-schedule the scan to see what happened.
  1672. */
  1673. if (h->reset_in_progress) {
  1674. h->drv_req_rescan = 1;
  1675. return;
  1676. }
  1677. added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
  1678. removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
  1679. if (!added || !removed) {
  1680. dev_warn(&h->pdev->dev, "out of memory in "
  1681. "adjust_hpsa_scsi_table\n");
  1682. goto free_and_out;
  1683. }
  1684. spin_lock_irqsave(&h->devlock, flags);
  1685. /* find any devices in h->dev[] that are not in
  1686. * sd[] and remove them from h->dev[], and for any
  1687. * devices which have changed, remove the old device
  1688. * info and add the new device info.
  1689. * If minor device attributes change, just update
  1690. * the existing device structure.
  1691. */
  1692. i = 0;
  1693. nremoved = 0;
  1694. nadded = 0;
  1695. while (i < h->ndevices) {
  1696. csd = h->dev[i];
  1697. device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
  1698. if (device_change == DEVICE_NOT_FOUND) {
  1699. changes++;
  1700. hpsa_scsi_remove_entry(h, i, removed, &nremoved);
  1701. continue; /* remove ^^^, hence i not incremented */
  1702. } else if (device_change == DEVICE_CHANGED) {
  1703. changes++;
  1704. hpsa_scsi_replace_entry(h, i, sd[entry],
  1705. added, &nadded, removed, &nremoved);
  1706. /* Set it to NULL to prevent it from being freed
  1707. * at the bottom of hpsa_update_scsi_devices()
  1708. */
  1709. sd[entry] = NULL;
  1710. } else if (device_change == DEVICE_UPDATED) {
  1711. hpsa_scsi_update_entry(h, i, sd[entry]);
  1712. }
  1713. i++;
  1714. }
  1715. /* Now, make sure every device listed in sd[] is also
  1716. * listed in h->dev[], adding them if they aren't found
  1717. */
  1718. for (i = 0; i < nsds; i++) {
  1719. if (!sd[i]) /* if already added above. */
  1720. continue;
  1721. /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
  1722. * as the SCSI mid-layer does not handle such devices well.
  1723. * It relentlessly loops sending TUR at 3Hz, then READ(10)
  1724. * at 160Hz, and prevents the system from coming up.
  1725. */
  1726. if (sd[i]->volume_offline) {
  1727. hpsa_show_volume_status(h, sd[i]);
  1728. hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
  1729. continue;
  1730. }
  1731. device_change = hpsa_scsi_find_entry(sd[i], h->dev,
  1732. h->ndevices, &entry);
  1733. if (device_change == DEVICE_NOT_FOUND) {
  1734. changes++;
  1735. if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
  1736. break;
  1737. sd[i] = NULL; /* prevent from being freed later. */
  1738. } else if (device_change == DEVICE_CHANGED) {
  1739. /* should never happen... */
  1740. changes++;
  1741. dev_warn(&h->pdev->dev,
  1742. "device unexpectedly changed.\n");
  1743. /* but if it does happen, we just ignore that device */
  1744. }
  1745. }
  1746. hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
  1747. /* Now that h->dev[]->phys_disk[] is coherent, we can enable
  1748. * any logical drives that need it enabled.
  1749. */
  1750. for (i = 0; i < h->ndevices; i++) {
  1751. if (h->dev[i] == NULL)
  1752. continue;
  1753. h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
  1754. }
  1755. spin_unlock_irqrestore(&h->devlock, flags);
  1756. /* Monitor devices which are in one of several NOT READY states to be
  1757. * brought online later. This must be done without holding h->devlock,
  1758. * so don't touch h->dev[]
  1759. */
  1760. for (i = 0; i < nsds; i++) {
  1761. if (!sd[i]) /* if already added above. */
  1762. continue;
  1763. if (sd[i]->volume_offline)
  1764. hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
  1765. }
  1766. /* Don't notify scsi mid layer of any changes the first time through
  1767. * (or if there are no changes) scsi_scan_host will do it later the
  1768. * first time through.
  1769. */
  1770. if (!changes)
  1771. goto free_and_out;
  1772. /* Notify scsi mid layer of any removed devices */
  1773. for (i = 0; i < nremoved; i++) {
  1774. if (removed[i] == NULL)
  1775. continue;
  1776. if (removed[i]->expose_device)
  1777. hpsa_remove_device(h, removed[i]);
  1778. kfree(removed[i]);
  1779. removed[i] = NULL;
  1780. }
  1781. /* Notify scsi mid layer of any added devices */
  1782. for (i = 0; i < nadded; i++) {
  1783. int rc = 0;
  1784. if (added[i] == NULL)
  1785. continue;
  1786. if (!(added[i]->expose_device))
  1787. continue;
  1788. rc = hpsa_add_device(h, added[i]);
  1789. if (!rc)
  1790. continue;
  1791. dev_warn(&h->pdev->dev,
  1792. "addition failed %d, device not added.", rc);
  1793. /* now we have to remove it from h->dev,
  1794. * since it didn't get added to scsi mid layer
  1795. */
  1796. fixup_botched_add(h, added[i]);
  1797. h->drv_req_rescan = 1;
  1798. }
  1799. free_and_out:
  1800. kfree(added);
  1801. kfree(removed);
  1802. }
  1803. /*
  1804. * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
  1805. * Assume's h->devlock is held.
  1806. */
  1807. static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
  1808. int bus, int target, int lun)
  1809. {
  1810. int i;
  1811. struct hpsa_scsi_dev_t *sd;
  1812. for (i = 0; i < h->ndevices; i++) {
  1813. sd = h->dev[i];
  1814. if (sd->bus == bus && sd->target == target && sd->lun == lun)
  1815. return sd;
  1816. }
  1817. return NULL;
  1818. }
  1819. static int hpsa_slave_alloc(struct scsi_device *sdev)
  1820. {
  1821. struct hpsa_scsi_dev_t *sd = NULL;
  1822. unsigned long flags;
  1823. struct ctlr_info *h;
  1824. h = sdev_to_hba(sdev);
  1825. spin_lock_irqsave(&h->devlock, flags);
  1826. if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
  1827. struct scsi_target *starget;
  1828. struct sas_rphy *rphy;
  1829. starget = scsi_target(sdev);
  1830. rphy = target_to_rphy(starget);
  1831. sd = hpsa_find_device_by_sas_rphy(h, rphy);
  1832. if (sd) {
  1833. sd->target = sdev_id(sdev);
  1834. sd->lun = sdev->lun;
  1835. }
  1836. }
  1837. if (!sd)
  1838. sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
  1839. sdev_id(sdev), sdev->lun);
  1840. if (sd && sd->expose_device) {
  1841. atomic_set(&sd->ioaccel_cmds_out, 0);
  1842. sdev->hostdata = sd;
  1843. } else
  1844. sdev->hostdata = NULL;
  1845. spin_unlock_irqrestore(&h->devlock, flags);
  1846. return 0;
  1847. }
  1848. /* configure scsi device based on internal per-device structure */
  1849. static int hpsa_slave_configure(struct scsi_device *sdev)
  1850. {
  1851. struct hpsa_scsi_dev_t *sd;
  1852. int queue_depth;
  1853. sd = sdev->hostdata;
  1854. sdev->no_uld_attach = !sd || !sd->expose_device;
  1855. if (sd)
  1856. queue_depth = sd->queue_depth != 0 ?
  1857. sd->queue_depth : sdev->host->can_queue;
  1858. else
  1859. queue_depth = sdev->host->can_queue;
  1860. scsi_change_queue_depth(sdev, queue_depth);
  1861. return 0;
  1862. }
  1863. static void hpsa_slave_destroy(struct scsi_device *sdev)
  1864. {
  1865. /* nothing to do. */
  1866. }
  1867. static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
  1868. {
  1869. int i;
  1870. if (!h->ioaccel2_cmd_sg_list)
  1871. return;
  1872. for (i = 0; i < h->nr_cmds; i++) {
  1873. kfree(h->ioaccel2_cmd_sg_list[i]);
  1874. h->ioaccel2_cmd_sg_list[i] = NULL;
  1875. }
  1876. kfree(h->ioaccel2_cmd_sg_list);
  1877. h->ioaccel2_cmd_sg_list = NULL;
  1878. }
  1879. static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
  1880. {
  1881. int i;
  1882. if (h->chainsize <= 0)
  1883. return 0;
  1884. h->ioaccel2_cmd_sg_list =
  1885. kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
  1886. GFP_KERNEL);
  1887. if (!h->ioaccel2_cmd_sg_list)
  1888. return -ENOMEM;
  1889. for (i = 0; i < h->nr_cmds; i++) {
  1890. h->ioaccel2_cmd_sg_list[i] =
  1891. kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
  1892. h->maxsgentries, GFP_KERNEL);
  1893. if (!h->ioaccel2_cmd_sg_list[i])
  1894. goto clean;
  1895. }
  1896. return 0;
  1897. clean:
  1898. hpsa_free_ioaccel2_sg_chain_blocks(h);
  1899. return -ENOMEM;
  1900. }
  1901. static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
  1902. {
  1903. int i;
  1904. if (!h->cmd_sg_list)
  1905. return;
  1906. for (i = 0; i < h->nr_cmds; i++) {
  1907. kfree(h->cmd_sg_list[i]);
  1908. h->cmd_sg_list[i] = NULL;
  1909. }
  1910. kfree(h->cmd_sg_list);
  1911. h->cmd_sg_list = NULL;
  1912. }
  1913. static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
  1914. {
  1915. int i;
  1916. if (h->chainsize <= 0)
  1917. return 0;
  1918. h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
  1919. GFP_KERNEL);
  1920. if (!h->cmd_sg_list) {
  1921. dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
  1922. return -ENOMEM;
  1923. }
  1924. for (i = 0; i < h->nr_cmds; i++) {
  1925. h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
  1926. h->chainsize, GFP_KERNEL);
  1927. if (!h->cmd_sg_list[i]) {
  1928. dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
  1929. goto clean;
  1930. }
  1931. }
  1932. return 0;
  1933. clean:
  1934. hpsa_free_sg_chain_blocks(h);
  1935. return -ENOMEM;
  1936. }
  1937. static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
  1938. struct io_accel2_cmd *cp, struct CommandList *c)
  1939. {
  1940. struct ioaccel2_sg_element *chain_block;
  1941. u64 temp64;
  1942. u32 chain_size;
  1943. chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
  1944. chain_size = le32_to_cpu(cp->sg[0].length);
  1945. temp64 = pci_map_single(h->pdev, chain_block, chain_size,
  1946. PCI_DMA_TODEVICE);
  1947. if (dma_mapping_error(&h->pdev->dev, temp64)) {
  1948. /* prevent subsequent unmapping */
  1949. cp->sg->address = 0;
  1950. return -1;
  1951. }
  1952. cp->sg->address = cpu_to_le64(temp64);
  1953. return 0;
  1954. }
  1955. static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
  1956. struct io_accel2_cmd *cp)
  1957. {
  1958. struct ioaccel2_sg_element *chain_sg;
  1959. u64 temp64;
  1960. u32 chain_size;
  1961. chain_sg = cp->sg;
  1962. temp64 = le64_to_cpu(chain_sg->address);
  1963. chain_size = le32_to_cpu(cp->sg[0].length);
  1964. pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
  1965. }
  1966. static int hpsa_map_sg_chain_block(struct ctlr_info *h,
  1967. struct CommandList *c)
  1968. {
  1969. struct SGDescriptor *chain_sg, *chain_block;
  1970. u64 temp64;
  1971. u32 chain_len;
  1972. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  1973. chain_block = h->cmd_sg_list[c->cmdindex];
  1974. chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
  1975. chain_len = sizeof(*chain_sg) *
  1976. (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
  1977. chain_sg->Len = cpu_to_le32(chain_len);
  1978. temp64 = pci_map_single(h->pdev, chain_block, chain_len,
  1979. PCI_DMA_TODEVICE);
  1980. if (dma_mapping_error(&h->pdev->dev, temp64)) {
  1981. /* prevent subsequent unmapping */
  1982. chain_sg->Addr = cpu_to_le64(0);
  1983. return -1;
  1984. }
  1985. chain_sg->Addr = cpu_to_le64(temp64);
  1986. return 0;
  1987. }
  1988. static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
  1989. struct CommandList *c)
  1990. {
  1991. struct SGDescriptor *chain_sg;
  1992. if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
  1993. return;
  1994. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  1995. pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
  1996. le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
  1997. }
  1998. /* Decode the various types of errors on ioaccel2 path.
  1999. * Return 1 for any error that should generate a RAID path retry.
  2000. * Return 0 for errors that don't require a RAID path retry.
  2001. */
  2002. static int handle_ioaccel_mode2_error(struct ctlr_info *h,
  2003. struct CommandList *c,
  2004. struct scsi_cmnd *cmd,
  2005. struct io_accel2_cmd *c2,
  2006. struct hpsa_scsi_dev_t *dev)
  2007. {
  2008. int data_len;
  2009. int retry = 0;
  2010. u32 ioaccel2_resid = 0;
  2011. switch (c2->error_data.serv_response) {
  2012. case IOACCEL2_SERV_RESPONSE_COMPLETE:
  2013. switch (c2->error_data.status) {
  2014. case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
  2015. break;
  2016. case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
  2017. cmd->result |= SAM_STAT_CHECK_CONDITION;
  2018. if (c2->error_data.data_present !=
  2019. IOACCEL2_SENSE_DATA_PRESENT) {
  2020. memset(cmd->sense_buffer, 0,
  2021. SCSI_SENSE_BUFFERSIZE);
  2022. break;
  2023. }
  2024. /* copy the sense data */
  2025. data_len = c2->error_data.sense_data_len;
  2026. if (data_len > SCSI_SENSE_BUFFERSIZE)
  2027. data_len = SCSI_SENSE_BUFFERSIZE;
  2028. if (data_len > sizeof(c2->error_data.sense_data_buff))
  2029. data_len =
  2030. sizeof(c2->error_data.sense_data_buff);
  2031. memcpy(cmd->sense_buffer,
  2032. c2->error_data.sense_data_buff, data_len);
  2033. retry = 1;
  2034. break;
  2035. case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
  2036. retry = 1;
  2037. break;
  2038. case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
  2039. retry = 1;
  2040. break;
  2041. case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
  2042. retry = 1;
  2043. break;
  2044. case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
  2045. retry = 1;
  2046. break;
  2047. default:
  2048. retry = 1;
  2049. break;
  2050. }
  2051. break;
  2052. case IOACCEL2_SERV_RESPONSE_FAILURE:
  2053. switch (c2->error_data.status) {
  2054. case IOACCEL2_STATUS_SR_IO_ERROR:
  2055. case IOACCEL2_STATUS_SR_IO_ABORTED:
  2056. case IOACCEL2_STATUS_SR_OVERRUN:
  2057. retry = 1;
  2058. break;
  2059. case IOACCEL2_STATUS_SR_UNDERRUN:
  2060. cmd->result = (DID_OK << 16); /* host byte */
  2061. cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
  2062. ioaccel2_resid = get_unaligned_le32(
  2063. &c2->error_data.resid_cnt[0]);
  2064. scsi_set_resid(cmd, ioaccel2_resid);
  2065. break;
  2066. case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
  2067. case IOACCEL2_STATUS_SR_INVALID_DEVICE:
  2068. case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
  2069. /*
  2070. * Did an HBA disk disappear? We will eventually
  2071. * get a state change event from the controller but
  2072. * in the meantime, we need to tell the OS that the
  2073. * HBA disk is no longer there and stop I/O
  2074. * from going down. This allows the potential re-insert
  2075. * of the disk to get the same device node.
  2076. */
  2077. if (dev->physical_device && dev->expose_device) {
  2078. cmd->result = DID_NO_CONNECT << 16;
  2079. dev->removed = 1;
  2080. h->drv_req_rescan = 1;
  2081. dev_warn(&h->pdev->dev,
  2082. "%s: device is gone!\n", __func__);
  2083. } else
  2084. /*
  2085. * Retry by sending down the RAID path.
  2086. * We will get an event from ctlr to
  2087. * trigger rescan regardless.
  2088. */
  2089. retry = 1;
  2090. break;
  2091. default:
  2092. retry = 1;
  2093. }
  2094. break;
  2095. case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
  2096. break;
  2097. case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
  2098. break;
  2099. case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
  2100. retry = 1;
  2101. break;
  2102. case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
  2103. break;
  2104. default:
  2105. retry = 1;
  2106. break;
  2107. }
  2108. return retry; /* retry on raid path? */
  2109. }
  2110. static void hpsa_cmd_resolve_events(struct ctlr_info *h,
  2111. struct CommandList *c)
  2112. {
  2113. bool do_wake = false;
  2114. /*
  2115. * Prevent the following race in the abort handler:
  2116. *
  2117. * 1. LLD is requested to abort a SCSI command
  2118. * 2. The SCSI command completes
  2119. * 3. The struct CommandList associated with step 2 is made available
  2120. * 4. New I/O request to LLD to another LUN re-uses struct CommandList
  2121. * 5. Abort handler follows scsi_cmnd->host_scribble and
  2122. * finds struct CommandList and tries to aborts it
  2123. * Now we have aborted the wrong command.
  2124. *
  2125. * Reset c->scsi_cmd here so that the abort or reset handler will know
  2126. * this command has completed. Then, check to see if the handler is
  2127. * waiting for this command, and, if so, wake it.
  2128. */
  2129. c->scsi_cmd = SCSI_CMD_IDLE;
  2130. mb(); /* Declare command idle before checking for pending events. */
  2131. if (c->abort_pending) {
  2132. do_wake = true;
  2133. c->abort_pending = false;
  2134. }
  2135. if (c->reset_pending) {
  2136. unsigned long flags;
  2137. struct hpsa_scsi_dev_t *dev;
  2138. /*
  2139. * There appears to be a reset pending; lock the lock and
  2140. * reconfirm. If so, then decrement the count of outstanding
  2141. * commands and wake the reset command if this is the last one.
  2142. */
  2143. spin_lock_irqsave(&h->lock, flags);
  2144. dev = c->reset_pending; /* Re-fetch under the lock. */
  2145. if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
  2146. do_wake = true;
  2147. c->reset_pending = NULL;
  2148. spin_unlock_irqrestore(&h->lock, flags);
  2149. }
  2150. if (do_wake)
  2151. wake_up_all(&h->event_sync_wait_queue);
  2152. }
  2153. static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
  2154. struct CommandList *c)
  2155. {
  2156. hpsa_cmd_resolve_events(h, c);
  2157. cmd_tagged_free(h, c);
  2158. }
  2159. static void hpsa_cmd_free_and_done(struct ctlr_info *h,
  2160. struct CommandList *c, struct scsi_cmnd *cmd)
  2161. {
  2162. hpsa_cmd_resolve_and_free(h, c);
  2163. if (cmd && cmd->scsi_done)
  2164. cmd->scsi_done(cmd);
  2165. }
  2166. static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
  2167. {
  2168. INIT_WORK(&c->work, hpsa_command_resubmit_worker);
  2169. queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
  2170. }
  2171. static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
  2172. {
  2173. cmd->result = DID_ABORT << 16;
  2174. }
  2175. static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
  2176. struct scsi_cmnd *cmd)
  2177. {
  2178. hpsa_set_scsi_cmd_aborted(cmd);
  2179. dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
  2180. c->Request.CDB, c->err_info->ScsiStatus);
  2181. hpsa_cmd_resolve_and_free(h, c);
  2182. }
  2183. static void process_ioaccel2_completion(struct ctlr_info *h,
  2184. struct CommandList *c, struct scsi_cmnd *cmd,
  2185. struct hpsa_scsi_dev_t *dev)
  2186. {
  2187. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  2188. /* check for good status */
  2189. if (likely(c2->error_data.serv_response == 0 &&
  2190. c2->error_data.status == 0))
  2191. return hpsa_cmd_free_and_done(h, c, cmd);
  2192. /*
  2193. * Any RAID offload error results in retry which will use
  2194. * the normal I/O path so the controller can handle whatever's
  2195. * wrong.
  2196. */
  2197. if (is_logical_device(dev) &&
  2198. c2->error_data.serv_response ==
  2199. IOACCEL2_SERV_RESPONSE_FAILURE) {
  2200. if (c2->error_data.status ==
  2201. IOACCEL2_STATUS_SR_IOACCEL_DISABLED) {
  2202. dev->offload_enabled = 0;
  2203. dev->offload_to_be_enabled = 0;
  2204. }
  2205. return hpsa_retry_cmd(h, c);
  2206. }
  2207. if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev))
  2208. return hpsa_retry_cmd(h, c);
  2209. return hpsa_cmd_free_and_done(h, c, cmd);
  2210. }
  2211. /* Returns 0 on success, < 0 otherwise. */
  2212. static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
  2213. struct CommandList *cp)
  2214. {
  2215. u8 tmf_status = cp->err_info->ScsiStatus;
  2216. switch (tmf_status) {
  2217. case CISS_TMF_COMPLETE:
  2218. /*
  2219. * CISS_TMF_COMPLETE never happens, instead,
  2220. * ei->CommandStatus == 0 for this case.
  2221. */
  2222. case CISS_TMF_SUCCESS:
  2223. return 0;
  2224. case CISS_TMF_INVALID_FRAME:
  2225. case CISS_TMF_NOT_SUPPORTED:
  2226. case CISS_TMF_FAILED:
  2227. case CISS_TMF_WRONG_LUN:
  2228. case CISS_TMF_OVERLAPPED_TAG:
  2229. break;
  2230. default:
  2231. dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
  2232. tmf_status);
  2233. break;
  2234. }
  2235. return -tmf_status;
  2236. }
  2237. static void complete_scsi_command(struct CommandList *cp)
  2238. {
  2239. struct scsi_cmnd *cmd;
  2240. struct ctlr_info *h;
  2241. struct ErrorInfo *ei;
  2242. struct hpsa_scsi_dev_t *dev;
  2243. struct io_accel2_cmd *c2;
  2244. u8 sense_key;
  2245. u8 asc; /* additional sense code */
  2246. u8 ascq; /* additional sense code qualifier */
  2247. unsigned long sense_data_size;
  2248. ei = cp->err_info;
  2249. cmd = cp->scsi_cmd;
  2250. h = cp->h;
  2251. if (!cmd->device) {
  2252. cmd->result = DID_NO_CONNECT << 16;
  2253. return hpsa_cmd_free_and_done(h, cp, cmd);
  2254. }
  2255. dev = cmd->device->hostdata;
  2256. if (!dev) {
  2257. cmd->result = DID_NO_CONNECT << 16;
  2258. return hpsa_cmd_free_and_done(h, cp, cmd);
  2259. }
  2260. c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
  2261. scsi_dma_unmap(cmd); /* undo the DMA mappings */
  2262. if ((cp->cmd_type == CMD_SCSI) &&
  2263. (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
  2264. hpsa_unmap_sg_chain_block(h, cp);
  2265. if ((cp->cmd_type == CMD_IOACCEL2) &&
  2266. (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
  2267. hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
  2268. cmd->result = (DID_OK << 16); /* host byte */
  2269. cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
  2270. if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) {
  2271. if (dev->physical_device && dev->expose_device &&
  2272. dev->removed) {
  2273. cmd->result = DID_NO_CONNECT << 16;
  2274. return hpsa_cmd_free_and_done(h, cp, cmd);
  2275. }
  2276. if (likely(cp->phys_disk != NULL))
  2277. atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
  2278. }
  2279. /*
  2280. * We check for lockup status here as it may be set for
  2281. * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
  2282. * fail_all_oustanding_cmds()
  2283. */
  2284. if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
  2285. /* DID_NO_CONNECT will prevent a retry */
  2286. cmd->result = DID_NO_CONNECT << 16;
  2287. return hpsa_cmd_free_and_done(h, cp, cmd);
  2288. }
  2289. if ((unlikely(hpsa_is_pending_event(cp)))) {
  2290. if (cp->reset_pending)
  2291. return hpsa_cmd_resolve_and_free(h, cp);
  2292. if (cp->abort_pending)
  2293. return hpsa_cmd_abort_and_free(h, cp, cmd);
  2294. }
  2295. if (cp->cmd_type == CMD_IOACCEL2)
  2296. return process_ioaccel2_completion(h, cp, cmd, dev);
  2297. scsi_set_resid(cmd, ei->ResidualCnt);
  2298. if (ei->CommandStatus == 0)
  2299. return hpsa_cmd_free_and_done(h, cp, cmd);
  2300. /* For I/O accelerator commands, copy over some fields to the normal
  2301. * CISS header used below for error handling.
  2302. */
  2303. if (cp->cmd_type == CMD_IOACCEL1) {
  2304. struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
  2305. cp->Header.SGList = scsi_sg_count(cmd);
  2306. cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
  2307. cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
  2308. IOACCEL1_IOFLAGS_CDBLEN_MASK;
  2309. cp->Header.tag = c->tag;
  2310. memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
  2311. memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
  2312. /* Any RAID offload error results in retry which will use
  2313. * the normal I/O path so the controller can handle whatever's
  2314. * wrong.
  2315. */
  2316. if (is_logical_device(dev)) {
  2317. if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
  2318. dev->offload_enabled = 0;
  2319. return hpsa_retry_cmd(h, cp);
  2320. }
  2321. }
  2322. /* an error has occurred */
  2323. switch (ei->CommandStatus) {
  2324. case CMD_TARGET_STATUS:
  2325. cmd->result |= ei->ScsiStatus;
  2326. /* copy the sense data */
  2327. if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
  2328. sense_data_size = SCSI_SENSE_BUFFERSIZE;
  2329. else
  2330. sense_data_size = sizeof(ei->SenseInfo);
  2331. if (ei->SenseLen < sense_data_size)
  2332. sense_data_size = ei->SenseLen;
  2333. memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
  2334. if (ei->ScsiStatus)
  2335. decode_sense_data(ei->SenseInfo, sense_data_size,
  2336. &sense_key, &asc, &ascq);
  2337. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
  2338. if (sense_key == ABORTED_COMMAND) {
  2339. cmd->result |= DID_SOFT_ERROR << 16;
  2340. break;
  2341. }
  2342. break;
  2343. }
  2344. /* Problem was not a check condition
  2345. * Pass it up to the upper layers...
  2346. */
  2347. if (ei->ScsiStatus) {
  2348. dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
  2349. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  2350. "Returning result: 0x%x\n",
  2351. cp, ei->ScsiStatus,
  2352. sense_key, asc, ascq,
  2353. cmd->result);
  2354. } else { /* scsi status is zero??? How??? */
  2355. dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
  2356. "Returning no connection.\n", cp),
  2357. /* Ordinarily, this case should never happen,
  2358. * but there is a bug in some released firmware
  2359. * revisions that allows it to happen if, for
  2360. * example, a 4100 backplane loses power and
  2361. * the tape drive is in it. We assume that
  2362. * it's a fatal error of some kind because we
  2363. * can't show that it wasn't. We will make it
  2364. * look like selection timeout since that is
  2365. * the most common reason for this to occur,
  2366. * and it's severe enough.
  2367. */
  2368. cmd->result = DID_NO_CONNECT << 16;
  2369. }
  2370. break;
  2371. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  2372. break;
  2373. case CMD_DATA_OVERRUN:
  2374. dev_warn(&h->pdev->dev,
  2375. "CDB %16phN data overrun\n", cp->Request.CDB);
  2376. break;
  2377. case CMD_INVALID: {
  2378. /* print_bytes(cp, sizeof(*cp), 1, 0);
  2379. print_cmd(cp); */
  2380. /* We get CMD_INVALID if you address a non-existent device
  2381. * instead of a selection timeout (no response). You will
  2382. * see this if you yank out a drive, then try to access it.
  2383. * This is kind of a shame because it means that any other
  2384. * CMD_INVALID (e.g. driver bug) will get interpreted as a
  2385. * missing target. */
  2386. cmd->result = DID_NO_CONNECT << 16;
  2387. }
  2388. break;
  2389. case CMD_PROTOCOL_ERR:
  2390. cmd->result = DID_ERROR << 16;
  2391. dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
  2392. cp->Request.CDB);
  2393. break;
  2394. case CMD_HARDWARE_ERR:
  2395. cmd->result = DID_ERROR << 16;
  2396. dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
  2397. cp->Request.CDB);
  2398. break;
  2399. case CMD_CONNECTION_LOST:
  2400. cmd->result = DID_ERROR << 16;
  2401. dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
  2402. cp->Request.CDB);
  2403. break;
  2404. case CMD_ABORTED:
  2405. /* Return now to avoid calling scsi_done(). */
  2406. return hpsa_cmd_abort_and_free(h, cp, cmd);
  2407. case CMD_ABORT_FAILED:
  2408. cmd->result = DID_ERROR << 16;
  2409. dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
  2410. cp->Request.CDB);
  2411. break;
  2412. case CMD_UNSOLICITED_ABORT:
  2413. cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
  2414. dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
  2415. cp->Request.CDB);
  2416. break;
  2417. case CMD_TIMEOUT:
  2418. cmd->result = DID_TIME_OUT << 16;
  2419. dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
  2420. cp->Request.CDB);
  2421. break;
  2422. case CMD_UNABORTABLE:
  2423. cmd->result = DID_ERROR << 16;
  2424. dev_warn(&h->pdev->dev, "Command unabortable\n");
  2425. break;
  2426. case CMD_TMF_STATUS:
  2427. if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
  2428. cmd->result = DID_ERROR << 16;
  2429. break;
  2430. case CMD_IOACCEL_DISABLED:
  2431. /* This only handles the direct pass-through case since RAID
  2432. * offload is handled above. Just attempt a retry.
  2433. */
  2434. cmd->result = DID_SOFT_ERROR << 16;
  2435. dev_warn(&h->pdev->dev,
  2436. "cp %p had HP SSD Smart Path error\n", cp);
  2437. break;
  2438. default:
  2439. cmd->result = DID_ERROR << 16;
  2440. dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
  2441. cp, ei->CommandStatus);
  2442. }
  2443. return hpsa_cmd_free_and_done(h, cp, cmd);
  2444. }
  2445. static void hpsa_pci_unmap(struct pci_dev *pdev,
  2446. struct CommandList *c, int sg_used, int data_direction)
  2447. {
  2448. int i;
  2449. for (i = 0; i < sg_used; i++)
  2450. pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
  2451. le32_to_cpu(c->SG[i].Len),
  2452. data_direction);
  2453. }
  2454. static int hpsa_map_one(struct pci_dev *pdev,
  2455. struct CommandList *cp,
  2456. unsigned char *buf,
  2457. size_t buflen,
  2458. int data_direction)
  2459. {
  2460. u64 addr64;
  2461. if (buflen == 0 || data_direction == PCI_DMA_NONE) {
  2462. cp->Header.SGList = 0;
  2463. cp->Header.SGTotal = cpu_to_le16(0);
  2464. return 0;
  2465. }
  2466. addr64 = pci_map_single(pdev, buf, buflen, data_direction);
  2467. if (dma_mapping_error(&pdev->dev, addr64)) {
  2468. /* Prevent subsequent unmap of something never mapped */
  2469. cp->Header.SGList = 0;
  2470. cp->Header.SGTotal = cpu_to_le16(0);
  2471. return -1;
  2472. }
  2473. cp->SG[0].Addr = cpu_to_le64(addr64);
  2474. cp->SG[0].Len = cpu_to_le32(buflen);
  2475. cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
  2476. cp->Header.SGList = 1; /* no. SGs contig in this cmd */
  2477. cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
  2478. return 0;
  2479. }
  2480. #define NO_TIMEOUT ((unsigned long) -1)
  2481. #define DEFAULT_TIMEOUT 30000 /* milliseconds */
  2482. static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
  2483. struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
  2484. {
  2485. DECLARE_COMPLETION_ONSTACK(wait);
  2486. c->waiting = &wait;
  2487. __enqueue_cmd_and_start_io(h, c, reply_queue);
  2488. if (timeout_msecs == NO_TIMEOUT) {
  2489. /* TODO: get rid of this no-timeout thing */
  2490. wait_for_completion_io(&wait);
  2491. return IO_OK;
  2492. }
  2493. if (!wait_for_completion_io_timeout(&wait,
  2494. msecs_to_jiffies(timeout_msecs))) {
  2495. dev_warn(&h->pdev->dev, "Command timed out.\n");
  2496. return -ETIMEDOUT;
  2497. }
  2498. return IO_OK;
  2499. }
  2500. static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
  2501. int reply_queue, unsigned long timeout_msecs)
  2502. {
  2503. if (unlikely(lockup_detected(h))) {
  2504. c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
  2505. return IO_OK;
  2506. }
  2507. return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
  2508. }
  2509. static u32 lockup_detected(struct ctlr_info *h)
  2510. {
  2511. int cpu;
  2512. u32 rc, *lockup_detected;
  2513. cpu = get_cpu();
  2514. lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
  2515. rc = *lockup_detected;
  2516. put_cpu();
  2517. return rc;
  2518. }
  2519. #define MAX_DRIVER_CMD_RETRIES 25
  2520. static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
  2521. struct CommandList *c, int data_direction, unsigned long timeout_msecs)
  2522. {
  2523. int backoff_time = 10, retry_count = 0;
  2524. int rc;
  2525. do {
  2526. memset(c->err_info, 0, sizeof(*c->err_info));
  2527. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  2528. timeout_msecs);
  2529. if (rc)
  2530. break;
  2531. retry_count++;
  2532. if (retry_count > 3) {
  2533. msleep(backoff_time);
  2534. if (backoff_time < 1000)
  2535. backoff_time *= 2;
  2536. }
  2537. } while ((check_for_unit_attention(h, c) ||
  2538. check_for_busy(h, c)) &&
  2539. retry_count <= MAX_DRIVER_CMD_RETRIES);
  2540. hpsa_pci_unmap(h->pdev, c, 1, data_direction);
  2541. if (retry_count > MAX_DRIVER_CMD_RETRIES)
  2542. rc = -EIO;
  2543. return rc;
  2544. }
  2545. static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
  2546. struct CommandList *c)
  2547. {
  2548. const u8 *cdb = c->Request.CDB;
  2549. const u8 *lun = c->Header.LUN.LunAddrBytes;
  2550. dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
  2551. " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  2552. txt, lun[0], lun[1], lun[2], lun[3],
  2553. lun[4], lun[5], lun[6], lun[7],
  2554. cdb[0], cdb[1], cdb[2], cdb[3],
  2555. cdb[4], cdb[5], cdb[6], cdb[7],
  2556. cdb[8], cdb[9], cdb[10], cdb[11],
  2557. cdb[12], cdb[13], cdb[14], cdb[15]);
  2558. }
  2559. static void hpsa_scsi_interpret_error(struct ctlr_info *h,
  2560. struct CommandList *cp)
  2561. {
  2562. const struct ErrorInfo *ei = cp->err_info;
  2563. struct device *d = &cp->h->pdev->dev;
  2564. u8 sense_key, asc, ascq;
  2565. int sense_len;
  2566. switch (ei->CommandStatus) {
  2567. case CMD_TARGET_STATUS:
  2568. if (ei->SenseLen > sizeof(ei->SenseInfo))
  2569. sense_len = sizeof(ei->SenseInfo);
  2570. else
  2571. sense_len = ei->SenseLen;
  2572. decode_sense_data(ei->SenseInfo, sense_len,
  2573. &sense_key, &asc, &ascq);
  2574. hpsa_print_cmd(h, "SCSI status", cp);
  2575. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
  2576. dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
  2577. sense_key, asc, ascq);
  2578. else
  2579. dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
  2580. if (ei->ScsiStatus == 0)
  2581. dev_warn(d, "SCSI status is abnormally zero. "
  2582. "(probably indicates selection timeout "
  2583. "reported incorrectly due to a known "
  2584. "firmware bug, circa July, 2001.)\n");
  2585. break;
  2586. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  2587. break;
  2588. case CMD_DATA_OVERRUN:
  2589. hpsa_print_cmd(h, "overrun condition", cp);
  2590. break;
  2591. case CMD_INVALID: {
  2592. /* controller unfortunately reports SCSI passthru's
  2593. * to non-existent targets as invalid commands.
  2594. */
  2595. hpsa_print_cmd(h, "invalid command", cp);
  2596. dev_warn(d, "probably means device no longer present\n");
  2597. }
  2598. break;
  2599. case CMD_PROTOCOL_ERR:
  2600. hpsa_print_cmd(h, "protocol error", cp);
  2601. break;
  2602. case CMD_HARDWARE_ERR:
  2603. hpsa_print_cmd(h, "hardware error", cp);
  2604. break;
  2605. case CMD_CONNECTION_LOST:
  2606. hpsa_print_cmd(h, "connection lost", cp);
  2607. break;
  2608. case CMD_ABORTED:
  2609. hpsa_print_cmd(h, "aborted", cp);
  2610. break;
  2611. case CMD_ABORT_FAILED:
  2612. hpsa_print_cmd(h, "abort failed", cp);
  2613. break;
  2614. case CMD_UNSOLICITED_ABORT:
  2615. hpsa_print_cmd(h, "unsolicited abort", cp);
  2616. break;
  2617. case CMD_TIMEOUT:
  2618. hpsa_print_cmd(h, "timed out", cp);
  2619. break;
  2620. case CMD_UNABORTABLE:
  2621. hpsa_print_cmd(h, "unabortable", cp);
  2622. break;
  2623. case CMD_CTLR_LOCKUP:
  2624. hpsa_print_cmd(h, "controller lockup detected", cp);
  2625. break;
  2626. default:
  2627. hpsa_print_cmd(h, "unknown status", cp);
  2628. dev_warn(d, "Unknown command status %x\n",
  2629. ei->CommandStatus);
  2630. }
  2631. }
  2632. static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
  2633. u16 page, unsigned char *buf,
  2634. unsigned char bufsize)
  2635. {
  2636. int rc = IO_OK;
  2637. struct CommandList *c;
  2638. struct ErrorInfo *ei;
  2639. c = cmd_alloc(h);
  2640. if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
  2641. page, scsi3addr, TYPE_CMD)) {
  2642. rc = -1;
  2643. goto out;
  2644. }
  2645. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  2646. PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
  2647. if (rc)
  2648. goto out;
  2649. ei = c->err_info;
  2650. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2651. hpsa_scsi_interpret_error(h, c);
  2652. rc = -1;
  2653. }
  2654. out:
  2655. cmd_free(h, c);
  2656. return rc;
  2657. }
  2658. static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
  2659. u8 reset_type, int reply_queue)
  2660. {
  2661. int rc = IO_OK;
  2662. struct CommandList *c;
  2663. struct ErrorInfo *ei;
  2664. c = cmd_alloc(h);
  2665. /* fill_cmd can't fail here, no data buffer to map. */
  2666. (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
  2667. scsi3addr, TYPE_MSG);
  2668. rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
  2669. if (rc) {
  2670. dev_warn(&h->pdev->dev, "Failed to send reset command\n");
  2671. goto out;
  2672. }
  2673. /* no unmap needed here because no data xfer. */
  2674. ei = c->err_info;
  2675. if (ei->CommandStatus != 0) {
  2676. hpsa_scsi_interpret_error(h, c);
  2677. rc = -1;
  2678. }
  2679. out:
  2680. cmd_free(h, c);
  2681. return rc;
  2682. }
  2683. static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
  2684. struct hpsa_scsi_dev_t *dev,
  2685. unsigned char *scsi3addr)
  2686. {
  2687. int i;
  2688. bool match = false;
  2689. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  2690. struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
  2691. if (hpsa_is_cmd_idle(c))
  2692. return false;
  2693. switch (c->cmd_type) {
  2694. case CMD_SCSI:
  2695. case CMD_IOCTL_PEND:
  2696. match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
  2697. sizeof(c->Header.LUN.LunAddrBytes));
  2698. break;
  2699. case CMD_IOACCEL1:
  2700. case CMD_IOACCEL2:
  2701. if (c->phys_disk == dev) {
  2702. /* HBA mode match */
  2703. match = true;
  2704. } else {
  2705. /* Possible RAID mode -- check each phys dev. */
  2706. /* FIXME: Do we need to take out a lock here? If
  2707. * so, we could just call hpsa_get_pdisk_of_ioaccel2()
  2708. * instead. */
  2709. for (i = 0; i < dev->nphysical_disks && !match; i++) {
  2710. /* FIXME: an alternate test might be
  2711. *
  2712. * match = dev->phys_disk[i]->ioaccel_handle
  2713. * == c2->scsi_nexus; */
  2714. match = dev->phys_disk[i] == c->phys_disk;
  2715. }
  2716. }
  2717. break;
  2718. case IOACCEL2_TMF:
  2719. for (i = 0; i < dev->nphysical_disks && !match; i++) {
  2720. match = dev->phys_disk[i]->ioaccel_handle ==
  2721. le32_to_cpu(ac->it_nexus);
  2722. }
  2723. break;
  2724. case 0: /* The command is in the middle of being initialized. */
  2725. match = false;
  2726. break;
  2727. default:
  2728. dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
  2729. c->cmd_type);
  2730. BUG();
  2731. }
  2732. return match;
  2733. }
  2734. static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
  2735. unsigned char *scsi3addr, u8 reset_type, int reply_queue)
  2736. {
  2737. int i;
  2738. int rc = 0;
  2739. /* We can really only handle one reset at a time */
  2740. if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
  2741. dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
  2742. return -EINTR;
  2743. }
  2744. BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
  2745. for (i = 0; i < h->nr_cmds; i++) {
  2746. struct CommandList *c = h->cmd_pool + i;
  2747. int refcount = atomic_inc_return(&c->refcount);
  2748. if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
  2749. unsigned long flags;
  2750. /*
  2751. * Mark the target command as having a reset pending,
  2752. * then lock a lock so that the command cannot complete
  2753. * while we're considering it. If the command is not
  2754. * idle then count it; otherwise revoke the event.
  2755. */
  2756. c->reset_pending = dev;
  2757. spin_lock_irqsave(&h->lock, flags); /* Implied MB */
  2758. if (!hpsa_is_cmd_idle(c))
  2759. atomic_inc(&dev->reset_cmds_out);
  2760. else
  2761. c->reset_pending = NULL;
  2762. spin_unlock_irqrestore(&h->lock, flags);
  2763. }
  2764. cmd_free(h, c);
  2765. }
  2766. rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
  2767. if (!rc)
  2768. wait_event(h->event_sync_wait_queue,
  2769. atomic_read(&dev->reset_cmds_out) == 0 ||
  2770. lockup_detected(h));
  2771. if (unlikely(lockup_detected(h))) {
  2772. dev_warn(&h->pdev->dev,
  2773. "Controller lockup detected during reset wait\n");
  2774. rc = -ENODEV;
  2775. }
  2776. if (unlikely(rc))
  2777. atomic_set(&dev->reset_cmds_out, 0);
  2778. mutex_unlock(&h->reset_mutex);
  2779. return rc;
  2780. }
  2781. static void hpsa_get_raid_level(struct ctlr_info *h,
  2782. unsigned char *scsi3addr, unsigned char *raid_level)
  2783. {
  2784. int rc;
  2785. unsigned char *buf;
  2786. *raid_level = RAID_UNKNOWN;
  2787. buf = kzalloc(64, GFP_KERNEL);
  2788. if (!buf)
  2789. return;
  2790. if (!hpsa_vpd_page_supported(h, scsi3addr,
  2791. HPSA_VPD_LV_DEVICE_GEOMETRY))
  2792. goto exit;
  2793. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
  2794. HPSA_VPD_LV_DEVICE_GEOMETRY, buf, 64);
  2795. if (rc == 0)
  2796. *raid_level = buf[8];
  2797. if (*raid_level > RAID_UNKNOWN)
  2798. *raid_level = RAID_UNKNOWN;
  2799. exit:
  2800. kfree(buf);
  2801. return;
  2802. }
  2803. #define HPSA_MAP_DEBUG
  2804. #ifdef HPSA_MAP_DEBUG
  2805. static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
  2806. struct raid_map_data *map_buff)
  2807. {
  2808. struct raid_map_disk_data *dd = &map_buff->data[0];
  2809. int map, row, col;
  2810. u16 map_cnt, row_cnt, disks_per_row;
  2811. if (rc != 0)
  2812. return;
  2813. /* Show details only if debugging has been activated. */
  2814. if (h->raid_offload_debug < 2)
  2815. return;
  2816. dev_info(&h->pdev->dev, "structure_size = %u\n",
  2817. le32_to_cpu(map_buff->structure_size));
  2818. dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
  2819. le32_to_cpu(map_buff->volume_blk_size));
  2820. dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
  2821. le64_to_cpu(map_buff->volume_blk_cnt));
  2822. dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
  2823. map_buff->phys_blk_shift);
  2824. dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
  2825. map_buff->parity_rotation_shift);
  2826. dev_info(&h->pdev->dev, "strip_size = %u\n",
  2827. le16_to_cpu(map_buff->strip_size));
  2828. dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
  2829. le64_to_cpu(map_buff->disk_starting_blk));
  2830. dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
  2831. le64_to_cpu(map_buff->disk_blk_cnt));
  2832. dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
  2833. le16_to_cpu(map_buff->data_disks_per_row));
  2834. dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
  2835. le16_to_cpu(map_buff->metadata_disks_per_row));
  2836. dev_info(&h->pdev->dev, "row_cnt = %u\n",
  2837. le16_to_cpu(map_buff->row_cnt));
  2838. dev_info(&h->pdev->dev, "layout_map_count = %u\n",
  2839. le16_to_cpu(map_buff->layout_map_count));
  2840. dev_info(&h->pdev->dev, "flags = 0x%x\n",
  2841. le16_to_cpu(map_buff->flags));
  2842. dev_info(&h->pdev->dev, "encrypytion = %s\n",
  2843. le16_to_cpu(map_buff->flags) &
  2844. RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
  2845. dev_info(&h->pdev->dev, "dekindex = %u\n",
  2846. le16_to_cpu(map_buff->dekindex));
  2847. map_cnt = le16_to_cpu(map_buff->layout_map_count);
  2848. for (map = 0; map < map_cnt; map++) {
  2849. dev_info(&h->pdev->dev, "Map%u:\n", map);
  2850. row_cnt = le16_to_cpu(map_buff->row_cnt);
  2851. for (row = 0; row < row_cnt; row++) {
  2852. dev_info(&h->pdev->dev, " Row%u:\n", row);
  2853. disks_per_row =
  2854. le16_to_cpu(map_buff->data_disks_per_row);
  2855. for (col = 0; col < disks_per_row; col++, dd++)
  2856. dev_info(&h->pdev->dev,
  2857. " D%02u: h=0x%04x xor=%u,%u\n",
  2858. col, dd->ioaccel_handle,
  2859. dd->xor_mult[0], dd->xor_mult[1]);
  2860. disks_per_row =
  2861. le16_to_cpu(map_buff->metadata_disks_per_row);
  2862. for (col = 0; col < disks_per_row; col++, dd++)
  2863. dev_info(&h->pdev->dev,
  2864. " M%02u: h=0x%04x xor=%u,%u\n",
  2865. col, dd->ioaccel_handle,
  2866. dd->xor_mult[0], dd->xor_mult[1]);
  2867. }
  2868. }
  2869. }
  2870. #else
  2871. static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
  2872. __attribute__((unused)) int rc,
  2873. __attribute__((unused)) struct raid_map_data *map_buff)
  2874. {
  2875. }
  2876. #endif
  2877. static int hpsa_get_raid_map(struct ctlr_info *h,
  2878. unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
  2879. {
  2880. int rc = 0;
  2881. struct CommandList *c;
  2882. struct ErrorInfo *ei;
  2883. c = cmd_alloc(h);
  2884. if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
  2885. sizeof(this_device->raid_map), 0,
  2886. scsi3addr, TYPE_CMD)) {
  2887. dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
  2888. cmd_free(h, c);
  2889. return -1;
  2890. }
  2891. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  2892. PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
  2893. if (rc)
  2894. goto out;
  2895. ei = c->err_info;
  2896. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2897. hpsa_scsi_interpret_error(h, c);
  2898. rc = -1;
  2899. goto out;
  2900. }
  2901. cmd_free(h, c);
  2902. /* @todo in the future, dynamically allocate RAID map memory */
  2903. if (le32_to_cpu(this_device->raid_map.structure_size) >
  2904. sizeof(this_device->raid_map)) {
  2905. dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
  2906. rc = -1;
  2907. }
  2908. hpsa_debug_map_buff(h, rc, &this_device->raid_map);
  2909. return rc;
  2910. out:
  2911. cmd_free(h, c);
  2912. return rc;
  2913. }
  2914. static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
  2915. unsigned char scsi3addr[], u16 bmic_device_index,
  2916. struct bmic_sense_subsystem_info *buf, size_t bufsize)
  2917. {
  2918. int rc = IO_OK;
  2919. struct CommandList *c;
  2920. struct ErrorInfo *ei;
  2921. c = cmd_alloc(h);
  2922. rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
  2923. 0, RAID_CTLR_LUNID, TYPE_CMD);
  2924. if (rc)
  2925. goto out;
  2926. c->Request.CDB[2] = bmic_device_index & 0xff;
  2927. c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
  2928. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  2929. PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
  2930. if (rc)
  2931. goto out;
  2932. ei = c->err_info;
  2933. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2934. hpsa_scsi_interpret_error(h, c);
  2935. rc = -1;
  2936. }
  2937. out:
  2938. cmd_free(h, c);
  2939. return rc;
  2940. }
  2941. static int hpsa_bmic_id_controller(struct ctlr_info *h,
  2942. struct bmic_identify_controller *buf, size_t bufsize)
  2943. {
  2944. int rc = IO_OK;
  2945. struct CommandList *c;
  2946. struct ErrorInfo *ei;
  2947. c = cmd_alloc(h);
  2948. rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
  2949. 0, RAID_CTLR_LUNID, TYPE_CMD);
  2950. if (rc)
  2951. goto out;
  2952. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  2953. PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
  2954. if (rc)
  2955. goto out;
  2956. ei = c->err_info;
  2957. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2958. hpsa_scsi_interpret_error(h, c);
  2959. rc = -1;
  2960. }
  2961. out:
  2962. cmd_free(h, c);
  2963. return rc;
  2964. }
  2965. static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
  2966. unsigned char scsi3addr[], u16 bmic_device_index,
  2967. struct bmic_identify_physical_device *buf, size_t bufsize)
  2968. {
  2969. int rc = IO_OK;
  2970. struct CommandList *c;
  2971. struct ErrorInfo *ei;
  2972. c = cmd_alloc(h);
  2973. rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
  2974. 0, RAID_CTLR_LUNID, TYPE_CMD);
  2975. if (rc)
  2976. goto out;
  2977. c->Request.CDB[2] = bmic_device_index & 0xff;
  2978. c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
  2979. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
  2980. DEFAULT_TIMEOUT);
  2981. ei = c->err_info;
  2982. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2983. hpsa_scsi_interpret_error(h, c);
  2984. rc = -1;
  2985. }
  2986. out:
  2987. cmd_free(h, c);
  2988. return rc;
  2989. }
  2990. /*
  2991. * get enclosure information
  2992. * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number
  2993. * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure
  2994. * Uses id_physical_device to determine the box_index.
  2995. */
  2996. static void hpsa_get_enclosure_info(struct ctlr_info *h,
  2997. unsigned char *scsi3addr,
  2998. struct ReportExtendedLUNdata *rlep, int rle_index,
  2999. struct hpsa_scsi_dev_t *encl_dev)
  3000. {
  3001. int rc = -1;
  3002. struct CommandList *c = NULL;
  3003. struct ErrorInfo *ei = NULL;
  3004. struct bmic_sense_storage_box_params *bssbp = NULL;
  3005. struct bmic_identify_physical_device *id_phys = NULL;
  3006. struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
  3007. u16 bmic_device_index = 0;
  3008. bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]);
  3009. if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) {
  3010. rc = IO_OK;
  3011. goto out;
  3012. }
  3013. bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL);
  3014. if (!bssbp)
  3015. goto out;
  3016. id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
  3017. if (!id_phys)
  3018. goto out;
  3019. rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index,
  3020. id_phys, sizeof(*id_phys));
  3021. if (rc) {
  3022. dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n",
  3023. __func__, encl_dev->external, bmic_device_index);
  3024. goto out;
  3025. }
  3026. c = cmd_alloc(h);
  3027. rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp,
  3028. sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD);
  3029. if (rc)
  3030. goto out;
  3031. if (id_phys->phys_connector[1] == 'E')
  3032. c->Request.CDB[5] = id_phys->box_index;
  3033. else
  3034. c->Request.CDB[5] = 0;
  3035. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
  3036. DEFAULT_TIMEOUT);
  3037. if (rc)
  3038. goto out;
  3039. ei = c->err_info;
  3040. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3041. rc = -1;
  3042. goto out;
  3043. }
  3044. encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port;
  3045. memcpy(&encl_dev->phys_connector[id_phys->active_path_number],
  3046. bssbp->phys_connector, sizeof(bssbp->phys_connector));
  3047. rc = IO_OK;
  3048. out:
  3049. kfree(bssbp);
  3050. kfree(id_phys);
  3051. if (c)
  3052. cmd_free(h, c);
  3053. if (rc != IO_OK)
  3054. hpsa_show_dev_msg(KERN_INFO, h, encl_dev,
  3055. "Error, could not get enclosure information\n");
  3056. }
  3057. static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
  3058. unsigned char *scsi3addr)
  3059. {
  3060. struct ReportExtendedLUNdata *physdev;
  3061. u32 nphysicals;
  3062. u64 sa = 0;
  3063. int i;
  3064. physdev = kzalloc(sizeof(*physdev), GFP_KERNEL);
  3065. if (!physdev)
  3066. return 0;
  3067. if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
  3068. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  3069. kfree(physdev);
  3070. return 0;
  3071. }
  3072. nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
  3073. for (i = 0; i < nphysicals; i++)
  3074. if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
  3075. sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
  3076. break;
  3077. }
  3078. kfree(physdev);
  3079. return sa;
  3080. }
  3081. static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
  3082. struct hpsa_scsi_dev_t *dev)
  3083. {
  3084. int rc;
  3085. u64 sa = 0;
  3086. if (is_hba_lunid(scsi3addr)) {
  3087. struct bmic_sense_subsystem_info *ssi;
  3088. ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
  3089. if (ssi == NULL) {
  3090. dev_warn(&h->pdev->dev,
  3091. "%s: out of memory\n", __func__);
  3092. return;
  3093. }
  3094. rc = hpsa_bmic_sense_subsystem_information(h,
  3095. scsi3addr, 0, ssi, sizeof(*ssi));
  3096. if (rc == 0) {
  3097. sa = get_unaligned_be64(ssi->primary_world_wide_id);
  3098. h->sas_address = sa;
  3099. }
  3100. kfree(ssi);
  3101. } else
  3102. sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
  3103. dev->sas_address = sa;
  3104. }
  3105. /* Get a device id from inquiry page 0x83 */
  3106. static bool hpsa_vpd_page_supported(struct ctlr_info *h,
  3107. unsigned char scsi3addr[], u8 page)
  3108. {
  3109. int rc;
  3110. int i;
  3111. int pages;
  3112. unsigned char *buf, bufsize;
  3113. buf = kzalloc(256, GFP_KERNEL);
  3114. if (!buf)
  3115. return false;
  3116. /* Get the size of the page list first */
  3117. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  3118. VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
  3119. buf, HPSA_VPD_HEADER_SZ);
  3120. if (rc != 0)
  3121. goto exit_unsupported;
  3122. pages = buf[3];
  3123. if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
  3124. bufsize = pages + HPSA_VPD_HEADER_SZ;
  3125. else
  3126. bufsize = 255;
  3127. /* Get the whole VPD page list */
  3128. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  3129. VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
  3130. buf, bufsize);
  3131. if (rc != 0)
  3132. goto exit_unsupported;
  3133. pages = buf[3];
  3134. for (i = 1; i <= pages; i++)
  3135. if (buf[3 + i] == page)
  3136. goto exit_supported;
  3137. exit_unsupported:
  3138. kfree(buf);
  3139. return false;
  3140. exit_supported:
  3141. kfree(buf);
  3142. return true;
  3143. }
  3144. static void hpsa_get_ioaccel_status(struct ctlr_info *h,
  3145. unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
  3146. {
  3147. int rc;
  3148. unsigned char *buf;
  3149. u8 ioaccel_status;
  3150. this_device->offload_config = 0;
  3151. this_device->offload_enabled = 0;
  3152. this_device->offload_to_be_enabled = 0;
  3153. buf = kzalloc(64, GFP_KERNEL);
  3154. if (!buf)
  3155. return;
  3156. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
  3157. goto out;
  3158. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  3159. VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
  3160. if (rc != 0)
  3161. goto out;
  3162. #define IOACCEL_STATUS_BYTE 4
  3163. #define OFFLOAD_CONFIGURED_BIT 0x01
  3164. #define OFFLOAD_ENABLED_BIT 0x02
  3165. ioaccel_status = buf[IOACCEL_STATUS_BYTE];
  3166. this_device->offload_config =
  3167. !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
  3168. if (this_device->offload_config) {
  3169. this_device->offload_enabled =
  3170. !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
  3171. if (hpsa_get_raid_map(h, scsi3addr, this_device))
  3172. this_device->offload_enabled = 0;
  3173. }
  3174. this_device->offload_to_be_enabled = this_device->offload_enabled;
  3175. out:
  3176. kfree(buf);
  3177. return;
  3178. }
  3179. /* Get the device id from inquiry page 0x83 */
  3180. static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
  3181. unsigned char *device_id, int index, int buflen)
  3182. {
  3183. int rc;
  3184. unsigned char *buf;
  3185. /* Does controller have VPD for device id? */
  3186. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_DEVICE_ID))
  3187. return 1; /* not supported */
  3188. buf = kzalloc(64, GFP_KERNEL);
  3189. if (!buf)
  3190. return -ENOMEM;
  3191. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
  3192. HPSA_VPD_LV_DEVICE_ID, buf, 64);
  3193. if (rc == 0) {
  3194. if (buflen > 16)
  3195. buflen = 16;
  3196. memcpy(device_id, &buf[8], buflen);
  3197. }
  3198. kfree(buf);
  3199. return rc; /*0 - got id, otherwise, didn't */
  3200. }
  3201. static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
  3202. void *buf, int bufsize,
  3203. int extended_response)
  3204. {
  3205. int rc = IO_OK;
  3206. struct CommandList *c;
  3207. unsigned char scsi3addr[8];
  3208. struct ErrorInfo *ei;
  3209. c = cmd_alloc(h);
  3210. /* address the controller */
  3211. memset(scsi3addr, 0, sizeof(scsi3addr));
  3212. if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
  3213. buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
  3214. rc = -1;
  3215. goto out;
  3216. }
  3217. if (extended_response)
  3218. c->Request.CDB[1] = extended_response;
  3219. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  3220. PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
  3221. if (rc)
  3222. goto out;
  3223. ei = c->err_info;
  3224. if (ei->CommandStatus != 0 &&
  3225. ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3226. hpsa_scsi_interpret_error(h, c);
  3227. rc = -1;
  3228. } else {
  3229. struct ReportLUNdata *rld = buf;
  3230. if (rld->extended_response_flag != extended_response) {
  3231. dev_err(&h->pdev->dev,
  3232. "report luns requested format %u, got %u\n",
  3233. extended_response,
  3234. rld->extended_response_flag);
  3235. rc = -1;
  3236. }
  3237. }
  3238. out:
  3239. cmd_free(h, c);
  3240. return rc;
  3241. }
  3242. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  3243. struct ReportExtendedLUNdata *buf, int bufsize)
  3244. {
  3245. return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
  3246. HPSA_REPORT_PHYS_EXTENDED);
  3247. }
  3248. static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
  3249. struct ReportLUNdata *buf, int bufsize)
  3250. {
  3251. return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
  3252. }
  3253. static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
  3254. int bus, int target, int lun)
  3255. {
  3256. device->bus = bus;
  3257. device->target = target;
  3258. device->lun = lun;
  3259. }
  3260. /* Use VPD inquiry to get details of volume status */
  3261. static int hpsa_get_volume_status(struct ctlr_info *h,
  3262. unsigned char scsi3addr[])
  3263. {
  3264. int rc;
  3265. int status;
  3266. int size;
  3267. unsigned char *buf;
  3268. buf = kzalloc(64, GFP_KERNEL);
  3269. if (!buf)
  3270. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3271. /* Does controller have VPD for logical volume status? */
  3272. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
  3273. goto exit_failed;
  3274. /* Get the size of the VPD return buffer */
  3275. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
  3276. buf, HPSA_VPD_HEADER_SZ);
  3277. if (rc != 0)
  3278. goto exit_failed;
  3279. size = buf[3];
  3280. /* Now get the whole VPD buffer */
  3281. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
  3282. buf, size + HPSA_VPD_HEADER_SZ);
  3283. if (rc != 0)
  3284. goto exit_failed;
  3285. status = buf[4]; /* status byte */
  3286. kfree(buf);
  3287. return status;
  3288. exit_failed:
  3289. kfree(buf);
  3290. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3291. }
  3292. /* Determine offline status of a volume.
  3293. * Return either:
  3294. * 0 (not offline)
  3295. * 0xff (offline for unknown reasons)
  3296. * # (integer code indicating one of several NOT READY states
  3297. * describing why a volume is to be kept offline)
  3298. */
  3299. static int hpsa_volume_offline(struct ctlr_info *h,
  3300. unsigned char scsi3addr[])
  3301. {
  3302. struct CommandList *c;
  3303. unsigned char *sense;
  3304. u8 sense_key, asc, ascq;
  3305. int sense_len;
  3306. int rc, ldstat = 0;
  3307. u16 cmd_status;
  3308. u8 scsi_status;
  3309. #define ASC_LUN_NOT_READY 0x04
  3310. #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
  3311. #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
  3312. c = cmd_alloc(h);
  3313. (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
  3314. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  3315. DEFAULT_TIMEOUT);
  3316. if (rc) {
  3317. cmd_free(h, c);
  3318. return 0;
  3319. }
  3320. sense = c->err_info->SenseInfo;
  3321. if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
  3322. sense_len = sizeof(c->err_info->SenseInfo);
  3323. else
  3324. sense_len = c->err_info->SenseLen;
  3325. decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
  3326. cmd_status = c->err_info->CommandStatus;
  3327. scsi_status = c->err_info->ScsiStatus;
  3328. cmd_free(h, c);
  3329. /* Is the volume 'not ready'? */
  3330. if (cmd_status != CMD_TARGET_STATUS ||
  3331. scsi_status != SAM_STAT_CHECK_CONDITION ||
  3332. sense_key != NOT_READY ||
  3333. asc != ASC_LUN_NOT_READY) {
  3334. return 0;
  3335. }
  3336. /* Determine the reason for not ready state */
  3337. ldstat = hpsa_get_volume_status(h, scsi3addr);
  3338. /* Keep volume offline in certain cases: */
  3339. switch (ldstat) {
  3340. case HPSA_LV_UNDERGOING_ERASE:
  3341. case HPSA_LV_NOT_AVAILABLE:
  3342. case HPSA_LV_UNDERGOING_RPI:
  3343. case HPSA_LV_PENDING_RPI:
  3344. case HPSA_LV_ENCRYPTED_NO_KEY:
  3345. case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
  3346. case HPSA_LV_UNDERGOING_ENCRYPTION:
  3347. case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
  3348. case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  3349. return ldstat;
  3350. case HPSA_VPD_LV_STATUS_UNSUPPORTED:
  3351. /* If VPD status page isn't available,
  3352. * use ASC/ASCQ to determine state
  3353. */
  3354. if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
  3355. (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
  3356. return ldstat;
  3357. break;
  3358. default:
  3359. break;
  3360. }
  3361. return 0;
  3362. }
  3363. /*
  3364. * Find out if a logical device supports aborts by simply trying one.
  3365. * Smart Array may claim not to support aborts on logical drives, but
  3366. * if a MSA2000 * is connected, the drives on that will be presented
  3367. * by the Smart Array as logical drives, and aborts may be sent to
  3368. * those devices successfully. So the simplest way to find out is
  3369. * to simply try an abort and see how the device responds.
  3370. */
  3371. static int hpsa_device_supports_aborts(struct ctlr_info *h,
  3372. unsigned char *scsi3addr)
  3373. {
  3374. struct CommandList *c;
  3375. struct ErrorInfo *ei;
  3376. int rc = 0;
  3377. u64 tag = (u64) -1; /* bogus tag */
  3378. /* Assume that physical devices support aborts */
  3379. if (!is_logical_dev_addr_mode(scsi3addr))
  3380. return 1;
  3381. c = cmd_alloc(h);
  3382. (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
  3383. (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  3384. DEFAULT_TIMEOUT);
  3385. /* no unmap needed here because no data xfer. */
  3386. ei = c->err_info;
  3387. switch (ei->CommandStatus) {
  3388. case CMD_INVALID:
  3389. rc = 0;
  3390. break;
  3391. case CMD_UNABORTABLE:
  3392. case CMD_ABORT_FAILED:
  3393. rc = 1;
  3394. break;
  3395. case CMD_TMF_STATUS:
  3396. rc = hpsa_evaluate_tmf_status(h, c);
  3397. break;
  3398. default:
  3399. rc = 0;
  3400. break;
  3401. }
  3402. cmd_free(h, c);
  3403. return rc;
  3404. }
  3405. static int hpsa_update_device_info(struct ctlr_info *h,
  3406. unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
  3407. unsigned char *is_OBDR_device)
  3408. {
  3409. #define OBDR_SIG_OFFSET 43
  3410. #define OBDR_TAPE_SIG "$DR-10"
  3411. #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
  3412. #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
  3413. unsigned char *inq_buff;
  3414. unsigned char *obdr_sig;
  3415. int rc = 0;
  3416. inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
  3417. if (!inq_buff) {
  3418. rc = -ENOMEM;
  3419. goto bail_out;
  3420. }
  3421. /* Do an inquiry to the device to see what it is. */
  3422. if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
  3423. (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
  3424. /* Inquiry failed (msg printed already) */
  3425. dev_err(&h->pdev->dev,
  3426. "hpsa_update_device_info: inquiry failed\n");
  3427. rc = -EIO;
  3428. goto bail_out;
  3429. }
  3430. scsi_sanitize_inquiry_string(&inq_buff[8], 8);
  3431. scsi_sanitize_inquiry_string(&inq_buff[16], 16);
  3432. this_device->devtype = (inq_buff[0] & 0x1f);
  3433. memcpy(this_device->scsi3addr, scsi3addr, 8);
  3434. memcpy(this_device->vendor, &inq_buff[8],
  3435. sizeof(this_device->vendor));
  3436. memcpy(this_device->model, &inq_buff[16],
  3437. sizeof(this_device->model));
  3438. this_device->rev = inq_buff[2];
  3439. memset(this_device->device_id, 0,
  3440. sizeof(this_device->device_id));
  3441. if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
  3442. sizeof(this_device->device_id)))
  3443. dev_err(&h->pdev->dev,
  3444. "hpsa%d: %s: can't get device id for host %d:C0:T%d:L%d\t%s\t%.16s\n",
  3445. h->ctlr, __func__,
  3446. h->scsi_host->host_no,
  3447. this_device->target, this_device->lun,
  3448. scsi_device_type(this_device->devtype),
  3449. this_device->model);
  3450. if ((this_device->devtype == TYPE_DISK ||
  3451. this_device->devtype == TYPE_ZBC) &&
  3452. is_logical_dev_addr_mode(scsi3addr)) {
  3453. int volume_offline;
  3454. hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
  3455. if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
  3456. hpsa_get_ioaccel_status(h, scsi3addr, this_device);
  3457. volume_offline = hpsa_volume_offline(h, scsi3addr);
  3458. if (volume_offline < 0 || volume_offline > 0xff)
  3459. volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3460. this_device->volume_offline = volume_offline & 0xff;
  3461. } else {
  3462. this_device->raid_level = RAID_UNKNOWN;
  3463. this_device->offload_config = 0;
  3464. this_device->offload_enabled = 0;
  3465. this_device->offload_to_be_enabled = 0;
  3466. this_device->hba_ioaccel_enabled = 0;
  3467. this_device->volume_offline = 0;
  3468. this_device->queue_depth = h->nr_cmds;
  3469. }
  3470. if (is_OBDR_device) {
  3471. /* See if this is a One-Button-Disaster-Recovery device
  3472. * by looking for "$DR-10" at offset 43 in inquiry data.
  3473. */
  3474. obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
  3475. *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
  3476. strncmp(obdr_sig, OBDR_TAPE_SIG,
  3477. OBDR_SIG_LEN) == 0);
  3478. }
  3479. kfree(inq_buff);
  3480. return 0;
  3481. bail_out:
  3482. kfree(inq_buff);
  3483. return rc;
  3484. }
  3485. static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
  3486. struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
  3487. {
  3488. unsigned long flags;
  3489. int rc, entry;
  3490. /*
  3491. * See if this device supports aborts. If we already know
  3492. * the device, we already know if it supports aborts, otherwise
  3493. * we have to find out if it supports aborts by trying one.
  3494. */
  3495. spin_lock_irqsave(&h->devlock, flags);
  3496. rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
  3497. if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
  3498. entry >= 0 && entry < h->ndevices) {
  3499. dev->supports_aborts = h->dev[entry]->supports_aborts;
  3500. spin_unlock_irqrestore(&h->devlock, flags);
  3501. } else {
  3502. spin_unlock_irqrestore(&h->devlock, flags);
  3503. dev->supports_aborts =
  3504. hpsa_device_supports_aborts(h, scsi3addr);
  3505. if (dev->supports_aborts < 0)
  3506. dev->supports_aborts = 0;
  3507. }
  3508. }
  3509. /*
  3510. * Helper function to assign bus, target, lun mapping of devices.
  3511. * Logical drive target and lun are assigned at this time, but
  3512. * physical device lun and target assignment are deferred (assigned
  3513. * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
  3514. */
  3515. static void figure_bus_target_lun(struct ctlr_info *h,
  3516. u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
  3517. {
  3518. u32 lunid = get_unaligned_le32(lunaddrbytes);
  3519. if (!is_logical_dev_addr_mode(lunaddrbytes)) {
  3520. /* physical device, target and lun filled in later */
  3521. if (is_hba_lunid(lunaddrbytes)) {
  3522. int bus = HPSA_HBA_BUS;
  3523. if (!device->rev)
  3524. bus = HPSA_LEGACY_HBA_BUS;
  3525. hpsa_set_bus_target_lun(device,
  3526. bus, 0, lunid & 0x3fff);
  3527. } else
  3528. /* defer target, lun assignment for physical devices */
  3529. hpsa_set_bus_target_lun(device,
  3530. HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
  3531. return;
  3532. }
  3533. /* It's a logical device */
  3534. if (device->external) {
  3535. hpsa_set_bus_target_lun(device,
  3536. HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
  3537. lunid & 0x00ff);
  3538. return;
  3539. }
  3540. hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
  3541. 0, lunid & 0x3fff);
  3542. }
  3543. /*
  3544. * Get address of physical disk used for an ioaccel2 mode command:
  3545. * 1. Extract ioaccel2 handle from the command.
  3546. * 2. Find a matching ioaccel2 handle from list of physical disks.
  3547. * 3. Return:
  3548. * 1 and set scsi3addr to address of matching physical
  3549. * 0 if no matching physical disk was found.
  3550. */
  3551. static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
  3552. struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
  3553. {
  3554. struct io_accel2_cmd *c2 =
  3555. &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
  3556. unsigned long flags;
  3557. int i;
  3558. spin_lock_irqsave(&h->devlock, flags);
  3559. for (i = 0; i < h->ndevices; i++)
  3560. if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
  3561. memcpy(scsi3addr, h->dev[i]->scsi3addr,
  3562. sizeof(h->dev[i]->scsi3addr));
  3563. spin_unlock_irqrestore(&h->devlock, flags);
  3564. return 1;
  3565. }
  3566. spin_unlock_irqrestore(&h->devlock, flags);
  3567. return 0;
  3568. }
  3569. static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
  3570. int i, int nphysicals, int nlocal_logicals)
  3571. {
  3572. /* In report logicals, local logicals are listed first,
  3573. * then any externals.
  3574. */
  3575. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  3576. if (i == raid_ctlr_position)
  3577. return 0;
  3578. if (i < logicals_start)
  3579. return 0;
  3580. /* i is in logicals range, but still within local logicals */
  3581. if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
  3582. return 0;
  3583. return 1; /* it's an external lun */
  3584. }
  3585. /*
  3586. * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
  3587. * logdev. The number of luns in physdev and logdev are returned in
  3588. * *nphysicals and *nlogicals, respectively.
  3589. * Returns 0 on success, -1 otherwise.
  3590. */
  3591. static int hpsa_gather_lun_info(struct ctlr_info *h,
  3592. struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
  3593. struct ReportLUNdata *logdev, u32 *nlogicals)
  3594. {
  3595. if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
  3596. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  3597. return -1;
  3598. }
  3599. *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
  3600. if (*nphysicals > HPSA_MAX_PHYS_LUN) {
  3601. dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
  3602. HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
  3603. *nphysicals = HPSA_MAX_PHYS_LUN;
  3604. }
  3605. if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
  3606. dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
  3607. return -1;
  3608. }
  3609. *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
  3610. /* Reject Logicals in excess of our max capability. */
  3611. if (*nlogicals > HPSA_MAX_LUN) {
  3612. dev_warn(&h->pdev->dev,
  3613. "maximum logical LUNs (%d) exceeded. "
  3614. "%d LUNs ignored.\n", HPSA_MAX_LUN,
  3615. *nlogicals - HPSA_MAX_LUN);
  3616. *nlogicals = HPSA_MAX_LUN;
  3617. }
  3618. if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
  3619. dev_warn(&h->pdev->dev,
  3620. "maximum logical + physical LUNs (%d) exceeded. "
  3621. "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  3622. *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
  3623. *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
  3624. }
  3625. return 0;
  3626. }
  3627. static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
  3628. int i, int nphysicals, int nlogicals,
  3629. struct ReportExtendedLUNdata *physdev_list,
  3630. struct ReportLUNdata *logdev_list)
  3631. {
  3632. /* Helper function, figure out where the LUN ID info is coming from
  3633. * given index i, lists of physical and logical devices, where in
  3634. * the list the raid controller is supposed to appear (first or last)
  3635. */
  3636. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  3637. int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
  3638. if (i == raid_ctlr_position)
  3639. return RAID_CTLR_LUNID;
  3640. if (i < logicals_start)
  3641. return &physdev_list->LUN[i -
  3642. (raid_ctlr_position == 0)].lunid[0];
  3643. if (i < last_device)
  3644. return &logdev_list->LUN[i - nphysicals -
  3645. (raid_ctlr_position == 0)][0];
  3646. BUG();
  3647. return NULL;
  3648. }
  3649. /* get physical drive ioaccel handle and queue depth */
  3650. static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
  3651. struct hpsa_scsi_dev_t *dev,
  3652. struct ReportExtendedLUNdata *rlep, int rle_index,
  3653. struct bmic_identify_physical_device *id_phys)
  3654. {
  3655. int rc;
  3656. struct ext_report_lun_entry *rle;
  3657. /*
  3658. * external targets don't support BMIC
  3659. */
  3660. if (dev->external) {
  3661. dev->queue_depth = 7;
  3662. return;
  3663. }
  3664. rle = &rlep->LUN[rle_index];
  3665. dev->ioaccel_handle = rle->ioaccel_handle;
  3666. if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
  3667. dev->hba_ioaccel_enabled = 1;
  3668. memset(id_phys, 0, sizeof(*id_phys));
  3669. rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
  3670. GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
  3671. sizeof(*id_phys));
  3672. if (!rc)
  3673. /* Reserve space for FW operations */
  3674. #define DRIVE_CMDS_RESERVED_FOR_FW 2
  3675. #define DRIVE_QUEUE_DEPTH 7
  3676. dev->queue_depth =
  3677. le16_to_cpu(id_phys->current_queue_depth_limit) -
  3678. DRIVE_CMDS_RESERVED_FOR_FW;
  3679. else
  3680. dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
  3681. }
  3682. static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
  3683. struct ReportExtendedLUNdata *rlep, int rle_index,
  3684. struct bmic_identify_physical_device *id_phys)
  3685. {
  3686. struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
  3687. if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
  3688. this_device->hba_ioaccel_enabled = 1;
  3689. memcpy(&this_device->active_path_index,
  3690. &id_phys->active_path_number,
  3691. sizeof(this_device->active_path_index));
  3692. memcpy(&this_device->path_map,
  3693. &id_phys->redundant_path_present_map,
  3694. sizeof(this_device->path_map));
  3695. memcpy(&this_device->box,
  3696. &id_phys->alternate_paths_phys_box_on_port,
  3697. sizeof(this_device->box));
  3698. memcpy(&this_device->phys_connector,
  3699. &id_phys->alternate_paths_phys_connector,
  3700. sizeof(this_device->phys_connector));
  3701. memcpy(&this_device->bay,
  3702. &id_phys->phys_bay_in_box,
  3703. sizeof(this_device->bay));
  3704. }
  3705. /* get number of local logical disks. */
  3706. static int hpsa_set_local_logical_count(struct ctlr_info *h,
  3707. struct bmic_identify_controller *id_ctlr,
  3708. u32 *nlocals)
  3709. {
  3710. int rc;
  3711. if (!id_ctlr) {
  3712. dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
  3713. __func__);
  3714. return -ENOMEM;
  3715. }
  3716. memset(id_ctlr, 0, sizeof(*id_ctlr));
  3717. rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
  3718. if (!rc)
  3719. if (id_ctlr->configured_logical_drive_count < 256)
  3720. *nlocals = id_ctlr->configured_logical_drive_count;
  3721. else
  3722. *nlocals = le16_to_cpu(
  3723. id_ctlr->extended_logical_unit_count);
  3724. else
  3725. *nlocals = -1;
  3726. return rc;
  3727. }
  3728. static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes)
  3729. {
  3730. struct bmic_identify_physical_device *id_phys;
  3731. bool is_spare = false;
  3732. int rc;
  3733. id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
  3734. if (!id_phys)
  3735. return false;
  3736. rc = hpsa_bmic_id_physical_device(h,
  3737. lunaddrbytes,
  3738. GET_BMIC_DRIVE_NUMBER(lunaddrbytes),
  3739. id_phys, sizeof(*id_phys));
  3740. if (rc == 0)
  3741. is_spare = (id_phys->more_flags >> 6) & 0x01;
  3742. kfree(id_phys);
  3743. return is_spare;
  3744. }
  3745. #define RPL_DEV_FLAG_NON_DISK 0x1
  3746. #define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2
  3747. #define RPL_DEV_FLAG_UNCONFIG_DISK 0x4
  3748. #define BMIC_DEVICE_TYPE_ENCLOSURE 6
  3749. static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes,
  3750. struct ext_report_lun_entry *rle)
  3751. {
  3752. u8 device_flags;
  3753. u8 device_type;
  3754. if (!MASKED_DEVICE(lunaddrbytes))
  3755. return false;
  3756. device_flags = rle->device_flags;
  3757. device_type = rle->device_type;
  3758. if (device_flags & RPL_DEV_FLAG_NON_DISK) {
  3759. if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE)
  3760. return false;
  3761. return true;
  3762. }
  3763. if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED))
  3764. return false;
  3765. if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK)
  3766. return false;
  3767. /*
  3768. * Spares may be spun down, we do not want to
  3769. * do an Inquiry to a RAID set spare drive as
  3770. * that would have them spun up, that is a
  3771. * performance hit because I/O to the RAID device
  3772. * stops while the spin up occurs which can take
  3773. * over 50 seconds.
  3774. */
  3775. if (hpsa_is_disk_spare(h, lunaddrbytes))
  3776. return true;
  3777. return false;
  3778. }
  3779. static void hpsa_update_scsi_devices(struct ctlr_info *h)
  3780. {
  3781. /* the idea here is we could get notified
  3782. * that some devices have changed, so we do a report
  3783. * physical luns and report logical luns cmd, and adjust
  3784. * our list of devices accordingly.
  3785. *
  3786. * The scsi3addr's of devices won't change so long as the
  3787. * adapter is not reset. That means we can rescan and
  3788. * tell which devices we already know about, vs. new
  3789. * devices, vs. disappearing devices.
  3790. */
  3791. struct ReportExtendedLUNdata *physdev_list = NULL;
  3792. struct ReportLUNdata *logdev_list = NULL;
  3793. struct bmic_identify_physical_device *id_phys = NULL;
  3794. struct bmic_identify_controller *id_ctlr = NULL;
  3795. u32 nphysicals = 0;
  3796. u32 nlogicals = 0;
  3797. u32 nlocal_logicals = 0;
  3798. u32 ndev_allocated = 0;
  3799. struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
  3800. int ncurrent = 0;
  3801. int i, n_ext_target_devs, ndevs_to_allocate;
  3802. int raid_ctlr_position;
  3803. bool physical_device;
  3804. DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
  3805. currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
  3806. physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
  3807. logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
  3808. tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
  3809. id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
  3810. id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
  3811. if (!currentsd || !physdev_list || !logdev_list ||
  3812. !tmpdevice || !id_phys || !id_ctlr) {
  3813. dev_err(&h->pdev->dev, "out of memory\n");
  3814. goto out;
  3815. }
  3816. memset(lunzerobits, 0, sizeof(lunzerobits));
  3817. h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
  3818. if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
  3819. logdev_list, &nlogicals)) {
  3820. h->drv_req_rescan = 1;
  3821. goto out;
  3822. }
  3823. /* Set number of local logicals (non PTRAID) */
  3824. if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
  3825. dev_warn(&h->pdev->dev,
  3826. "%s: Can't determine number of local logical devices.\n",
  3827. __func__);
  3828. }
  3829. /* We might see up to the maximum number of logical and physical disks
  3830. * plus external target devices, and a device for the local RAID
  3831. * controller.
  3832. */
  3833. ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
  3834. /* Allocate the per device structures */
  3835. for (i = 0; i < ndevs_to_allocate; i++) {
  3836. if (i >= HPSA_MAX_DEVICES) {
  3837. dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
  3838. " %d devices ignored.\n", HPSA_MAX_DEVICES,
  3839. ndevs_to_allocate - HPSA_MAX_DEVICES);
  3840. break;
  3841. }
  3842. currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
  3843. if (!currentsd[i]) {
  3844. dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
  3845. __FILE__, __LINE__);
  3846. h->drv_req_rescan = 1;
  3847. goto out;
  3848. }
  3849. ndev_allocated++;
  3850. }
  3851. if (is_scsi_rev_5(h))
  3852. raid_ctlr_position = 0;
  3853. else
  3854. raid_ctlr_position = nphysicals + nlogicals;
  3855. /* adjust our table of devices */
  3856. n_ext_target_devs = 0;
  3857. for (i = 0; i < nphysicals + nlogicals + 1; i++) {
  3858. u8 *lunaddrbytes, is_OBDR = 0;
  3859. int rc = 0;
  3860. int phys_dev_index = i - (raid_ctlr_position == 0);
  3861. bool skip_device = false;
  3862. physical_device = i < nphysicals + (raid_ctlr_position == 0);
  3863. /* Figure out where the LUN ID info is coming from */
  3864. lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
  3865. i, nphysicals, nlogicals, physdev_list, logdev_list);
  3866. /* Determine if this is a lun from an external target array */
  3867. tmpdevice->external =
  3868. figure_external_status(h, raid_ctlr_position, i,
  3869. nphysicals, nlocal_logicals);
  3870. /*
  3871. * Skip over some devices such as a spare.
  3872. */
  3873. if (!tmpdevice->external && physical_device) {
  3874. skip_device = hpsa_skip_device(h, lunaddrbytes,
  3875. &physdev_list->LUN[phys_dev_index]);
  3876. if (skip_device)
  3877. continue;
  3878. }
  3879. /* Get device type, vendor, model, device id */
  3880. rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
  3881. &is_OBDR);
  3882. if (rc == -ENOMEM) {
  3883. dev_warn(&h->pdev->dev,
  3884. "Out of memory, rescan deferred.\n");
  3885. h->drv_req_rescan = 1;
  3886. goto out;
  3887. }
  3888. if (rc) {
  3889. dev_warn(&h->pdev->dev,
  3890. "Inquiry failed, skipping device.\n");
  3891. continue;
  3892. }
  3893. figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
  3894. hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
  3895. this_device = currentsd[ncurrent];
  3896. /* Turn on discovery_polling if there are ext target devices.
  3897. * Event-based change notification is unreliable for those.
  3898. */
  3899. if (!h->discovery_polling) {
  3900. if (tmpdevice->external) {
  3901. h->discovery_polling = 1;
  3902. dev_info(&h->pdev->dev,
  3903. "External target, activate discovery polling.\n");
  3904. }
  3905. }
  3906. *this_device = *tmpdevice;
  3907. this_device->physical_device = physical_device;
  3908. /*
  3909. * Expose all devices except for physical devices that
  3910. * are masked.
  3911. */
  3912. if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
  3913. this_device->expose_device = 0;
  3914. else
  3915. this_device->expose_device = 1;
  3916. /*
  3917. * Get the SAS address for physical devices that are exposed.
  3918. */
  3919. if (this_device->physical_device && this_device->expose_device)
  3920. hpsa_get_sas_address(h, lunaddrbytes, this_device);
  3921. switch (this_device->devtype) {
  3922. case TYPE_ROM:
  3923. /* We don't *really* support actual CD-ROM devices,
  3924. * just "One Button Disaster Recovery" tape drive
  3925. * which temporarily pretends to be a CD-ROM drive.
  3926. * So we check that the device is really an OBDR tape
  3927. * device by checking for "$DR-10" in bytes 43-48 of
  3928. * the inquiry data.
  3929. */
  3930. if (is_OBDR)
  3931. ncurrent++;
  3932. break;
  3933. case TYPE_DISK:
  3934. case TYPE_ZBC:
  3935. if (this_device->physical_device) {
  3936. /* The disk is in HBA mode. */
  3937. /* Never use RAID mapper in HBA mode. */
  3938. this_device->offload_enabled = 0;
  3939. hpsa_get_ioaccel_drive_info(h, this_device,
  3940. physdev_list, phys_dev_index, id_phys);
  3941. hpsa_get_path_info(this_device,
  3942. physdev_list, phys_dev_index, id_phys);
  3943. }
  3944. ncurrent++;
  3945. break;
  3946. case TYPE_TAPE:
  3947. case TYPE_MEDIUM_CHANGER:
  3948. ncurrent++;
  3949. break;
  3950. case TYPE_ENCLOSURE:
  3951. if (!this_device->external)
  3952. hpsa_get_enclosure_info(h, lunaddrbytes,
  3953. physdev_list, phys_dev_index,
  3954. this_device);
  3955. ncurrent++;
  3956. break;
  3957. case TYPE_RAID:
  3958. /* Only present the Smartarray HBA as a RAID controller.
  3959. * If it's a RAID controller other than the HBA itself
  3960. * (an external RAID controller, MSA500 or similar)
  3961. * don't present it.
  3962. */
  3963. if (!is_hba_lunid(lunaddrbytes))
  3964. break;
  3965. ncurrent++;
  3966. break;
  3967. default:
  3968. break;
  3969. }
  3970. if (ncurrent >= HPSA_MAX_DEVICES)
  3971. break;
  3972. }
  3973. if (h->sas_host == NULL) {
  3974. int rc = 0;
  3975. rc = hpsa_add_sas_host(h);
  3976. if (rc) {
  3977. dev_warn(&h->pdev->dev,
  3978. "Could not add sas host %d\n", rc);
  3979. goto out;
  3980. }
  3981. }
  3982. adjust_hpsa_scsi_table(h, currentsd, ncurrent);
  3983. out:
  3984. kfree(tmpdevice);
  3985. for (i = 0; i < ndev_allocated; i++)
  3986. kfree(currentsd[i]);
  3987. kfree(currentsd);
  3988. kfree(physdev_list);
  3989. kfree(logdev_list);
  3990. kfree(id_ctlr);
  3991. kfree(id_phys);
  3992. }
  3993. static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
  3994. struct scatterlist *sg)
  3995. {
  3996. u64 addr64 = (u64) sg_dma_address(sg);
  3997. unsigned int len = sg_dma_len(sg);
  3998. desc->Addr = cpu_to_le64(addr64);
  3999. desc->Len = cpu_to_le32(len);
  4000. desc->Ext = 0;
  4001. }
  4002. /*
  4003. * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
  4004. * dma mapping and fills in the scatter gather entries of the
  4005. * hpsa command, cp.
  4006. */
  4007. static int hpsa_scatter_gather(struct ctlr_info *h,
  4008. struct CommandList *cp,
  4009. struct scsi_cmnd *cmd)
  4010. {
  4011. struct scatterlist *sg;
  4012. int use_sg, i, sg_limit, chained, last_sg;
  4013. struct SGDescriptor *curr_sg;
  4014. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  4015. use_sg = scsi_dma_map(cmd);
  4016. if (use_sg < 0)
  4017. return use_sg;
  4018. if (!use_sg)
  4019. goto sglist_finished;
  4020. /*
  4021. * If the number of entries is greater than the max for a single list,
  4022. * then we have a chained list; we will set up all but one entry in the
  4023. * first list (the last entry is saved for link information);
  4024. * otherwise, we don't have a chained list and we'll set up at each of
  4025. * the entries in the one list.
  4026. */
  4027. curr_sg = cp->SG;
  4028. chained = use_sg > h->max_cmd_sg_entries;
  4029. sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
  4030. last_sg = scsi_sg_count(cmd) - 1;
  4031. scsi_for_each_sg(cmd, sg, sg_limit, i) {
  4032. hpsa_set_sg_descriptor(curr_sg, sg);
  4033. curr_sg++;
  4034. }
  4035. if (chained) {
  4036. /*
  4037. * Continue with the chained list. Set curr_sg to the chained
  4038. * list. Modify the limit to the total count less the entries
  4039. * we've already set up. Resume the scan at the list entry
  4040. * where the previous loop left off.
  4041. */
  4042. curr_sg = h->cmd_sg_list[cp->cmdindex];
  4043. sg_limit = use_sg - sg_limit;
  4044. for_each_sg(sg, sg, sg_limit, i) {
  4045. hpsa_set_sg_descriptor(curr_sg, sg);
  4046. curr_sg++;
  4047. }
  4048. }
  4049. /* Back the pointer up to the last entry and mark it as "last". */
  4050. (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
  4051. if (use_sg + chained > h->maxSG)
  4052. h->maxSG = use_sg + chained;
  4053. if (chained) {
  4054. cp->Header.SGList = h->max_cmd_sg_entries;
  4055. cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
  4056. if (hpsa_map_sg_chain_block(h, cp)) {
  4057. scsi_dma_unmap(cmd);
  4058. return -1;
  4059. }
  4060. return 0;
  4061. }
  4062. sglist_finished:
  4063. cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
  4064. cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
  4065. return 0;
  4066. }
  4067. #define IO_ACCEL_INELIGIBLE (1)
  4068. static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
  4069. {
  4070. int is_write = 0;
  4071. u32 block;
  4072. u32 block_cnt;
  4073. /* Perform some CDB fixups if needed using 10 byte reads/writes only */
  4074. switch (cdb[0]) {
  4075. case WRITE_6:
  4076. case WRITE_12:
  4077. is_write = 1;
  4078. case READ_6:
  4079. case READ_12:
  4080. if (*cdb_len == 6) {
  4081. block = (((cdb[1] & 0x1F) << 16) |
  4082. (cdb[2] << 8) |
  4083. cdb[3]);
  4084. block_cnt = cdb[4];
  4085. if (block_cnt == 0)
  4086. block_cnt = 256;
  4087. } else {
  4088. BUG_ON(*cdb_len != 12);
  4089. block = get_unaligned_be32(&cdb[2]);
  4090. block_cnt = get_unaligned_be32(&cdb[6]);
  4091. }
  4092. if (block_cnt > 0xffff)
  4093. return IO_ACCEL_INELIGIBLE;
  4094. cdb[0] = is_write ? WRITE_10 : READ_10;
  4095. cdb[1] = 0;
  4096. cdb[2] = (u8) (block >> 24);
  4097. cdb[3] = (u8) (block >> 16);
  4098. cdb[4] = (u8) (block >> 8);
  4099. cdb[5] = (u8) (block);
  4100. cdb[6] = 0;
  4101. cdb[7] = (u8) (block_cnt >> 8);
  4102. cdb[8] = (u8) (block_cnt);
  4103. cdb[9] = 0;
  4104. *cdb_len = 10;
  4105. break;
  4106. }
  4107. return 0;
  4108. }
  4109. static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
  4110. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4111. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4112. {
  4113. struct scsi_cmnd *cmd = c->scsi_cmd;
  4114. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
  4115. unsigned int len;
  4116. unsigned int total_len = 0;
  4117. struct scatterlist *sg;
  4118. u64 addr64;
  4119. int use_sg, i;
  4120. struct SGDescriptor *curr_sg;
  4121. u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
  4122. /* TODO: implement chaining support */
  4123. if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
  4124. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4125. return IO_ACCEL_INELIGIBLE;
  4126. }
  4127. BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
  4128. if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
  4129. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4130. return IO_ACCEL_INELIGIBLE;
  4131. }
  4132. c->cmd_type = CMD_IOACCEL1;
  4133. /* Adjust the DMA address to point to the accelerated command buffer */
  4134. c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
  4135. (c->cmdindex * sizeof(*cp));
  4136. BUG_ON(c->busaddr & 0x0000007F);
  4137. use_sg = scsi_dma_map(cmd);
  4138. if (use_sg < 0) {
  4139. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4140. return use_sg;
  4141. }
  4142. if (use_sg) {
  4143. curr_sg = cp->SG;
  4144. scsi_for_each_sg(cmd, sg, use_sg, i) {
  4145. addr64 = (u64) sg_dma_address(sg);
  4146. len = sg_dma_len(sg);
  4147. total_len += len;
  4148. curr_sg->Addr = cpu_to_le64(addr64);
  4149. curr_sg->Len = cpu_to_le32(len);
  4150. curr_sg->Ext = cpu_to_le32(0);
  4151. curr_sg++;
  4152. }
  4153. (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
  4154. switch (cmd->sc_data_direction) {
  4155. case DMA_TO_DEVICE:
  4156. control |= IOACCEL1_CONTROL_DATA_OUT;
  4157. break;
  4158. case DMA_FROM_DEVICE:
  4159. control |= IOACCEL1_CONTROL_DATA_IN;
  4160. break;
  4161. case DMA_NONE:
  4162. control |= IOACCEL1_CONTROL_NODATAXFER;
  4163. break;
  4164. default:
  4165. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4166. cmd->sc_data_direction);
  4167. BUG();
  4168. break;
  4169. }
  4170. } else {
  4171. control |= IOACCEL1_CONTROL_NODATAXFER;
  4172. }
  4173. c->Header.SGList = use_sg;
  4174. /* Fill out the command structure to submit */
  4175. cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
  4176. cp->transfer_len = cpu_to_le32(total_len);
  4177. cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
  4178. (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
  4179. cp->control = cpu_to_le32(control);
  4180. memcpy(cp->CDB, cdb, cdb_len);
  4181. memcpy(cp->CISS_LUN, scsi3addr, 8);
  4182. /* Tag was already set at init time. */
  4183. enqueue_cmd_and_start_io(h, c);
  4184. return 0;
  4185. }
  4186. /*
  4187. * Queue a command directly to a device behind the controller using the
  4188. * I/O accelerator path.
  4189. */
  4190. static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
  4191. struct CommandList *c)
  4192. {
  4193. struct scsi_cmnd *cmd = c->scsi_cmd;
  4194. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4195. if (!dev)
  4196. return -1;
  4197. c->phys_disk = dev;
  4198. return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
  4199. cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
  4200. }
  4201. /*
  4202. * Set encryption parameters for the ioaccel2 request
  4203. */
  4204. static void set_encrypt_ioaccel2(struct ctlr_info *h,
  4205. struct CommandList *c, struct io_accel2_cmd *cp)
  4206. {
  4207. struct scsi_cmnd *cmd = c->scsi_cmd;
  4208. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4209. struct raid_map_data *map = &dev->raid_map;
  4210. u64 first_block;
  4211. /* Are we doing encryption on this device */
  4212. if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
  4213. return;
  4214. /* Set the data encryption key index. */
  4215. cp->dekindex = map->dekindex;
  4216. /* Set the encryption enable flag, encoded into direction field. */
  4217. cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
  4218. /* Set encryption tweak values based on logical block address
  4219. * If block size is 512, tweak value is LBA.
  4220. * For other block sizes, tweak is (LBA * block size)/ 512)
  4221. */
  4222. switch (cmd->cmnd[0]) {
  4223. /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
  4224. case READ_6:
  4225. case WRITE_6:
  4226. first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
  4227. (cmd->cmnd[2] << 8) |
  4228. cmd->cmnd[3]);
  4229. break;
  4230. case WRITE_10:
  4231. case READ_10:
  4232. /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
  4233. case WRITE_12:
  4234. case READ_12:
  4235. first_block = get_unaligned_be32(&cmd->cmnd[2]);
  4236. break;
  4237. case WRITE_16:
  4238. case READ_16:
  4239. first_block = get_unaligned_be64(&cmd->cmnd[2]);
  4240. break;
  4241. default:
  4242. dev_err(&h->pdev->dev,
  4243. "ERROR: %s: size (0x%x) not supported for encryption\n",
  4244. __func__, cmd->cmnd[0]);
  4245. BUG();
  4246. break;
  4247. }
  4248. if (le32_to_cpu(map->volume_blk_size) != 512)
  4249. first_block = first_block *
  4250. le32_to_cpu(map->volume_blk_size)/512;
  4251. cp->tweak_lower = cpu_to_le32(first_block);
  4252. cp->tweak_upper = cpu_to_le32(first_block >> 32);
  4253. }
  4254. static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
  4255. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4256. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4257. {
  4258. struct scsi_cmnd *cmd = c->scsi_cmd;
  4259. struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
  4260. struct ioaccel2_sg_element *curr_sg;
  4261. int use_sg, i;
  4262. struct scatterlist *sg;
  4263. u64 addr64;
  4264. u32 len;
  4265. u32 total_len = 0;
  4266. if (!cmd->device)
  4267. return -1;
  4268. if (!cmd->device->hostdata)
  4269. return -1;
  4270. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  4271. if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
  4272. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4273. return IO_ACCEL_INELIGIBLE;
  4274. }
  4275. c->cmd_type = CMD_IOACCEL2;
  4276. /* Adjust the DMA address to point to the accelerated command buffer */
  4277. c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
  4278. (c->cmdindex * sizeof(*cp));
  4279. BUG_ON(c->busaddr & 0x0000007F);
  4280. memset(cp, 0, sizeof(*cp));
  4281. cp->IU_type = IOACCEL2_IU_TYPE;
  4282. use_sg = scsi_dma_map(cmd);
  4283. if (use_sg < 0) {
  4284. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4285. return use_sg;
  4286. }
  4287. if (use_sg) {
  4288. curr_sg = cp->sg;
  4289. if (use_sg > h->ioaccel_maxsg) {
  4290. addr64 = le64_to_cpu(
  4291. h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
  4292. curr_sg->address = cpu_to_le64(addr64);
  4293. curr_sg->length = 0;
  4294. curr_sg->reserved[0] = 0;
  4295. curr_sg->reserved[1] = 0;
  4296. curr_sg->reserved[2] = 0;
  4297. curr_sg->chain_indicator = 0x80;
  4298. curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
  4299. }
  4300. scsi_for_each_sg(cmd, sg, use_sg, i) {
  4301. addr64 = (u64) sg_dma_address(sg);
  4302. len = sg_dma_len(sg);
  4303. total_len += len;
  4304. curr_sg->address = cpu_to_le64(addr64);
  4305. curr_sg->length = cpu_to_le32(len);
  4306. curr_sg->reserved[0] = 0;
  4307. curr_sg->reserved[1] = 0;
  4308. curr_sg->reserved[2] = 0;
  4309. curr_sg->chain_indicator = 0;
  4310. curr_sg++;
  4311. }
  4312. switch (cmd->sc_data_direction) {
  4313. case DMA_TO_DEVICE:
  4314. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4315. cp->direction |= IOACCEL2_DIR_DATA_OUT;
  4316. break;
  4317. case DMA_FROM_DEVICE:
  4318. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4319. cp->direction |= IOACCEL2_DIR_DATA_IN;
  4320. break;
  4321. case DMA_NONE:
  4322. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4323. cp->direction |= IOACCEL2_DIR_NO_DATA;
  4324. break;
  4325. default:
  4326. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4327. cmd->sc_data_direction);
  4328. BUG();
  4329. break;
  4330. }
  4331. } else {
  4332. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4333. cp->direction |= IOACCEL2_DIR_NO_DATA;
  4334. }
  4335. /* Set encryption parameters, if necessary */
  4336. set_encrypt_ioaccel2(h, c, cp);
  4337. cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
  4338. cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
  4339. memcpy(cp->cdb, cdb, sizeof(cp->cdb));
  4340. cp->data_len = cpu_to_le32(total_len);
  4341. cp->err_ptr = cpu_to_le64(c->busaddr +
  4342. offsetof(struct io_accel2_cmd, error_data));
  4343. cp->err_len = cpu_to_le32(sizeof(cp->error_data));
  4344. /* fill in sg elements */
  4345. if (use_sg > h->ioaccel_maxsg) {
  4346. cp->sg_count = 1;
  4347. cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
  4348. if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
  4349. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4350. scsi_dma_unmap(cmd);
  4351. return -1;
  4352. }
  4353. } else
  4354. cp->sg_count = (u8) use_sg;
  4355. enqueue_cmd_and_start_io(h, c);
  4356. return 0;
  4357. }
  4358. /*
  4359. * Queue a command to the correct I/O accelerator path.
  4360. */
  4361. static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
  4362. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4363. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4364. {
  4365. if (!c->scsi_cmd->device)
  4366. return -1;
  4367. if (!c->scsi_cmd->device->hostdata)
  4368. return -1;
  4369. /* Try to honor the device's queue depth */
  4370. if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
  4371. phys_disk->queue_depth) {
  4372. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4373. return IO_ACCEL_INELIGIBLE;
  4374. }
  4375. if (h->transMethod & CFGTBL_Trans_io_accel1)
  4376. return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
  4377. cdb, cdb_len, scsi3addr,
  4378. phys_disk);
  4379. else
  4380. return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
  4381. cdb, cdb_len, scsi3addr,
  4382. phys_disk);
  4383. }
  4384. static void raid_map_helper(struct raid_map_data *map,
  4385. int offload_to_mirror, u32 *map_index, u32 *current_group)
  4386. {
  4387. if (offload_to_mirror == 0) {
  4388. /* use physical disk in the first mirrored group. */
  4389. *map_index %= le16_to_cpu(map->data_disks_per_row);
  4390. return;
  4391. }
  4392. do {
  4393. /* determine mirror group that *map_index indicates */
  4394. *current_group = *map_index /
  4395. le16_to_cpu(map->data_disks_per_row);
  4396. if (offload_to_mirror == *current_group)
  4397. continue;
  4398. if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
  4399. /* select map index from next group */
  4400. *map_index += le16_to_cpu(map->data_disks_per_row);
  4401. (*current_group)++;
  4402. } else {
  4403. /* select map index from first group */
  4404. *map_index %= le16_to_cpu(map->data_disks_per_row);
  4405. *current_group = 0;
  4406. }
  4407. } while (offload_to_mirror != *current_group);
  4408. }
  4409. /*
  4410. * Attempt to perform offload RAID mapping for a logical volume I/O.
  4411. */
  4412. static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
  4413. struct CommandList *c)
  4414. {
  4415. struct scsi_cmnd *cmd = c->scsi_cmd;
  4416. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4417. struct raid_map_data *map = &dev->raid_map;
  4418. struct raid_map_disk_data *dd = &map->data[0];
  4419. int is_write = 0;
  4420. u32 map_index;
  4421. u64 first_block, last_block;
  4422. u32 block_cnt;
  4423. u32 blocks_per_row;
  4424. u64 first_row, last_row;
  4425. u32 first_row_offset, last_row_offset;
  4426. u32 first_column, last_column;
  4427. u64 r0_first_row, r0_last_row;
  4428. u32 r5or6_blocks_per_row;
  4429. u64 r5or6_first_row, r5or6_last_row;
  4430. u32 r5or6_first_row_offset, r5or6_last_row_offset;
  4431. u32 r5or6_first_column, r5or6_last_column;
  4432. u32 total_disks_per_row;
  4433. u32 stripesize;
  4434. u32 first_group, last_group, current_group;
  4435. u32 map_row;
  4436. u32 disk_handle;
  4437. u64 disk_block;
  4438. u32 disk_block_cnt;
  4439. u8 cdb[16];
  4440. u8 cdb_len;
  4441. u16 strip_size;
  4442. #if BITS_PER_LONG == 32
  4443. u64 tmpdiv;
  4444. #endif
  4445. int offload_to_mirror;
  4446. if (!dev)
  4447. return -1;
  4448. /* check for valid opcode, get LBA and block count */
  4449. switch (cmd->cmnd[0]) {
  4450. case WRITE_6:
  4451. is_write = 1;
  4452. case READ_6:
  4453. first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
  4454. (cmd->cmnd[2] << 8) |
  4455. cmd->cmnd[3]);
  4456. block_cnt = cmd->cmnd[4];
  4457. if (block_cnt == 0)
  4458. block_cnt = 256;
  4459. break;
  4460. case WRITE_10:
  4461. is_write = 1;
  4462. case READ_10:
  4463. first_block =
  4464. (((u64) cmd->cmnd[2]) << 24) |
  4465. (((u64) cmd->cmnd[3]) << 16) |
  4466. (((u64) cmd->cmnd[4]) << 8) |
  4467. cmd->cmnd[5];
  4468. block_cnt =
  4469. (((u32) cmd->cmnd[7]) << 8) |
  4470. cmd->cmnd[8];
  4471. break;
  4472. case WRITE_12:
  4473. is_write = 1;
  4474. case READ_12:
  4475. first_block =
  4476. (((u64) cmd->cmnd[2]) << 24) |
  4477. (((u64) cmd->cmnd[3]) << 16) |
  4478. (((u64) cmd->cmnd[4]) << 8) |
  4479. cmd->cmnd[5];
  4480. block_cnt =
  4481. (((u32) cmd->cmnd[6]) << 24) |
  4482. (((u32) cmd->cmnd[7]) << 16) |
  4483. (((u32) cmd->cmnd[8]) << 8) |
  4484. cmd->cmnd[9];
  4485. break;
  4486. case WRITE_16:
  4487. is_write = 1;
  4488. case READ_16:
  4489. first_block =
  4490. (((u64) cmd->cmnd[2]) << 56) |
  4491. (((u64) cmd->cmnd[3]) << 48) |
  4492. (((u64) cmd->cmnd[4]) << 40) |
  4493. (((u64) cmd->cmnd[5]) << 32) |
  4494. (((u64) cmd->cmnd[6]) << 24) |
  4495. (((u64) cmd->cmnd[7]) << 16) |
  4496. (((u64) cmd->cmnd[8]) << 8) |
  4497. cmd->cmnd[9];
  4498. block_cnt =
  4499. (((u32) cmd->cmnd[10]) << 24) |
  4500. (((u32) cmd->cmnd[11]) << 16) |
  4501. (((u32) cmd->cmnd[12]) << 8) |
  4502. cmd->cmnd[13];
  4503. break;
  4504. default:
  4505. return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
  4506. }
  4507. last_block = first_block + block_cnt - 1;
  4508. /* check for write to non-RAID-0 */
  4509. if (is_write && dev->raid_level != 0)
  4510. return IO_ACCEL_INELIGIBLE;
  4511. /* check for invalid block or wraparound */
  4512. if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
  4513. last_block < first_block)
  4514. return IO_ACCEL_INELIGIBLE;
  4515. /* calculate stripe information for the request */
  4516. blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
  4517. le16_to_cpu(map->strip_size);
  4518. strip_size = le16_to_cpu(map->strip_size);
  4519. #if BITS_PER_LONG == 32
  4520. tmpdiv = first_block;
  4521. (void) do_div(tmpdiv, blocks_per_row);
  4522. first_row = tmpdiv;
  4523. tmpdiv = last_block;
  4524. (void) do_div(tmpdiv, blocks_per_row);
  4525. last_row = tmpdiv;
  4526. first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
  4527. last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
  4528. tmpdiv = first_row_offset;
  4529. (void) do_div(tmpdiv, strip_size);
  4530. first_column = tmpdiv;
  4531. tmpdiv = last_row_offset;
  4532. (void) do_div(tmpdiv, strip_size);
  4533. last_column = tmpdiv;
  4534. #else
  4535. first_row = first_block / blocks_per_row;
  4536. last_row = last_block / blocks_per_row;
  4537. first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
  4538. last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
  4539. first_column = first_row_offset / strip_size;
  4540. last_column = last_row_offset / strip_size;
  4541. #endif
  4542. /* if this isn't a single row/column then give to the controller */
  4543. if ((first_row != last_row) || (first_column != last_column))
  4544. return IO_ACCEL_INELIGIBLE;
  4545. /* proceeding with driver mapping */
  4546. total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
  4547. le16_to_cpu(map->metadata_disks_per_row);
  4548. map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
  4549. le16_to_cpu(map->row_cnt);
  4550. map_index = (map_row * total_disks_per_row) + first_column;
  4551. switch (dev->raid_level) {
  4552. case HPSA_RAID_0:
  4553. break; /* nothing special to do */
  4554. case HPSA_RAID_1:
  4555. /* Handles load balance across RAID 1 members.
  4556. * (2-drive R1 and R10 with even # of drives.)
  4557. * Appropriate for SSDs, not optimal for HDDs
  4558. */
  4559. BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
  4560. if (dev->offload_to_mirror)
  4561. map_index += le16_to_cpu(map->data_disks_per_row);
  4562. dev->offload_to_mirror = !dev->offload_to_mirror;
  4563. break;
  4564. case HPSA_RAID_ADM:
  4565. /* Handles N-way mirrors (R1-ADM)
  4566. * and R10 with # of drives divisible by 3.)
  4567. */
  4568. BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
  4569. offload_to_mirror = dev->offload_to_mirror;
  4570. raid_map_helper(map, offload_to_mirror,
  4571. &map_index, &current_group);
  4572. /* set mirror group to use next time */
  4573. offload_to_mirror =
  4574. (offload_to_mirror >=
  4575. le16_to_cpu(map->layout_map_count) - 1)
  4576. ? 0 : offload_to_mirror + 1;
  4577. dev->offload_to_mirror = offload_to_mirror;
  4578. /* Avoid direct use of dev->offload_to_mirror within this
  4579. * function since multiple threads might simultaneously
  4580. * increment it beyond the range of dev->layout_map_count -1.
  4581. */
  4582. break;
  4583. case HPSA_RAID_5:
  4584. case HPSA_RAID_6:
  4585. if (le16_to_cpu(map->layout_map_count) <= 1)
  4586. break;
  4587. /* Verify first and last block are in same RAID group */
  4588. r5or6_blocks_per_row =
  4589. le16_to_cpu(map->strip_size) *
  4590. le16_to_cpu(map->data_disks_per_row);
  4591. BUG_ON(r5or6_blocks_per_row == 0);
  4592. stripesize = r5or6_blocks_per_row *
  4593. le16_to_cpu(map->layout_map_count);
  4594. #if BITS_PER_LONG == 32
  4595. tmpdiv = first_block;
  4596. first_group = do_div(tmpdiv, stripesize);
  4597. tmpdiv = first_group;
  4598. (void) do_div(tmpdiv, r5or6_blocks_per_row);
  4599. first_group = tmpdiv;
  4600. tmpdiv = last_block;
  4601. last_group = do_div(tmpdiv, stripesize);
  4602. tmpdiv = last_group;
  4603. (void) do_div(tmpdiv, r5or6_blocks_per_row);
  4604. last_group = tmpdiv;
  4605. #else
  4606. first_group = (first_block % stripesize) / r5or6_blocks_per_row;
  4607. last_group = (last_block % stripesize) / r5or6_blocks_per_row;
  4608. #endif
  4609. if (first_group != last_group)
  4610. return IO_ACCEL_INELIGIBLE;
  4611. /* Verify request is in a single row of RAID 5/6 */
  4612. #if BITS_PER_LONG == 32
  4613. tmpdiv = first_block;
  4614. (void) do_div(tmpdiv, stripesize);
  4615. first_row = r5or6_first_row = r0_first_row = tmpdiv;
  4616. tmpdiv = last_block;
  4617. (void) do_div(tmpdiv, stripesize);
  4618. r5or6_last_row = r0_last_row = tmpdiv;
  4619. #else
  4620. first_row = r5or6_first_row = r0_first_row =
  4621. first_block / stripesize;
  4622. r5or6_last_row = r0_last_row = last_block / stripesize;
  4623. #endif
  4624. if (r5or6_first_row != r5or6_last_row)
  4625. return IO_ACCEL_INELIGIBLE;
  4626. /* Verify request is in a single column */
  4627. #if BITS_PER_LONG == 32
  4628. tmpdiv = first_block;
  4629. first_row_offset = do_div(tmpdiv, stripesize);
  4630. tmpdiv = first_row_offset;
  4631. first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
  4632. r5or6_first_row_offset = first_row_offset;
  4633. tmpdiv = last_block;
  4634. r5or6_last_row_offset = do_div(tmpdiv, stripesize);
  4635. tmpdiv = r5or6_last_row_offset;
  4636. r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
  4637. tmpdiv = r5or6_first_row_offset;
  4638. (void) do_div(tmpdiv, map->strip_size);
  4639. first_column = r5or6_first_column = tmpdiv;
  4640. tmpdiv = r5or6_last_row_offset;
  4641. (void) do_div(tmpdiv, map->strip_size);
  4642. r5or6_last_column = tmpdiv;
  4643. #else
  4644. first_row_offset = r5or6_first_row_offset =
  4645. (u32)((first_block % stripesize) %
  4646. r5or6_blocks_per_row);
  4647. r5or6_last_row_offset =
  4648. (u32)((last_block % stripesize) %
  4649. r5or6_blocks_per_row);
  4650. first_column = r5or6_first_column =
  4651. r5or6_first_row_offset / le16_to_cpu(map->strip_size);
  4652. r5or6_last_column =
  4653. r5or6_last_row_offset / le16_to_cpu(map->strip_size);
  4654. #endif
  4655. if (r5or6_first_column != r5or6_last_column)
  4656. return IO_ACCEL_INELIGIBLE;
  4657. /* Request is eligible */
  4658. map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
  4659. le16_to_cpu(map->row_cnt);
  4660. map_index = (first_group *
  4661. (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
  4662. (map_row * total_disks_per_row) + first_column;
  4663. break;
  4664. default:
  4665. return IO_ACCEL_INELIGIBLE;
  4666. }
  4667. if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
  4668. return IO_ACCEL_INELIGIBLE;
  4669. c->phys_disk = dev->phys_disk[map_index];
  4670. if (!c->phys_disk)
  4671. return IO_ACCEL_INELIGIBLE;
  4672. disk_handle = dd[map_index].ioaccel_handle;
  4673. disk_block = le64_to_cpu(map->disk_starting_blk) +
  4674. first_row * le16_to_cpu(map->strip_size) +
  4675. (first_row_offset - first_column *
  4676. le16_to_cpu(map->strip_size));
  4677. disk_block_cnt = block_cnt;
  4678. /* handle differing logical/physical block sizes */
  4679. if (map->phys_blk_shift) {
  4680. disk_block <<= map->phys_blk_shift;
  4681. disk_block_cnt <<= map->phys_blk_shift;
  4682. }
  4683. BUG_ON(disk_block_cnt > 0xffff);
  4684. /* build the new CDB for the physical disk I/O */
  4685. if (disk_block > 0xffffffff) {
  4686. cdb[0] = is_write ? WRITE_16 : READ_16;
  4687. cdb[1] = 0;
  4688. cdb[2] = (u8) (disk_block >> 56);
  4689. cdb[3] = (u8) (disk_block >> 48);
  4690. cdb[4] = (u8) (disk_block >> 40);
  4691. cdb[5] = (u8) (disk_block >> 32);
  4692. cdb[6] = (u8) (disk_block >> 24);
  4693. cdb[7] = (u8) (disk_block >> 16);
  4694. cdb[8] = (u8) (disk_block >> 8);
  4695. cdb[9] = (u8) (disk_block);
  4696. cdb[10] = (u8) (disk_block_cnt >> 24);
  4697. cdb[11] = (u8) (disk_block_cnt >> 16);
  4698. cdb[12] = (u8) (disk_block_cnt >> 8);
  4699. cdb[13] = (u8) (disk_block_cnt);
  4700. cdb[14] = 0;
  4701. cdb[15] = 0;
  4702. cdb_len = 16;
  4703. } else {
  4704. cdb[0] = is_write ? WRITE_10 : READ_10;
  4705. cdb[1] = 0;
  4706. cdb[2] = (u8) (disk_block >> 24);
  4707. cdb[3] = (u8) (disk_block >> 16);
  4708. cdb[4] = (u8) (disk_block >> 8);
  4709. cdb[5] = (u8) (disk_block);
  4710. cdb[6] = 0;
  4711. cdb[7] = (u8) (disk_block_cnt >> 8);
  4712. cdb[8] = (u8) (disk_block_cnt);
  4713. cdb[9] = 0;
  4714. cdb_len = 10;
  4715. }
  4716. return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
  4717. dev->scsi3addr,
  4718. dev->phys_disk[map_index]);
  4719. }
  4720. /*
  4721. * Submit commands down the "normal" RAID stack path
  4722. * All callers to hpsa_ciss_submit must check lockup_detected
  4723. * beforehand, before (opt.) and after calling cmd_alloc
  4724. */
  4725. static int hpsa_ciss_submit(struct ctlr_info *h,
  4726. struct CommandList *c, struct scsi_cmnd *cmd,
  4727. unsigned char scsi3addr[])
  4728. {
  4729. cmd->host_scribble = (unsigned char *) c;
  4730. c->cmd_type = CMD_SCSI;
  4731. c->scsi_cmd = cmd;
  4732. c->Header.ReplyQueue = 0; /* unused in simple mode */
  4733. memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
  4734. c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
  4735. /* Fill in the request block... */
  4736. c->Request.Timeout = 0;
  4737. BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
  4738. c->Request.CDBLen = cmd->cmd_len;
  4739. memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
  4740. switch (cmd->sc_data_direction) {
  4741. case DMA_TO_DEVICE:
  4742. c->Request.type_attr_dir =
  4743. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
  4744. break;
  4745. case DMA_FROM_DEVICE:
  4746. c->Request.type_attr_dir =
  4747. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
  4748. break;
  4749. case DMA_NONE:
  4750. c->Request.type_attr_dir =
  4751. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
  4752. break;
  4753. case DMA_BIDIRECTIONAL:
  4754. /* This can happen if a buggy application does a scsi passthru
  4755. * and sets both inlen and outlen to non-zero. ( see
  4756. * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
  4757. */
  4758. c->Request.type_attr_dir =
  4759. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
  4760. /* This is technically wrong, and hpsa controllers should
  4761. * reject it with CMD_INVALID, which is the most correct
  4762. * response, but non-fibre backends appear to let it
  4763. * slide by, and give the same results as if this field
  4764. * were set correctly. Either way is acceptable for
  4765. * our purposes here.
  4766. */
  4767. break;
  4768. default:
  4769. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4770. cmd->sc_data_direction);
  4771. BUG();
  4772. break;
  4773. }
  4774. if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
  4775. hpsa_cmd_resolve_and_free(h, c);
  4776. return SCSI_MLQUEUE_HOST_BUSY;
  4777. }
  4778. enqueue_cmd_and_start_io(h, c);
  4779. /* the cmd'll come back via intr handler in complete_scsi_command() */
  4780. return 0;
  4781. }
  4782. static void hpsa_cmd_init(struct ctlr_info *h, int index,
  4783. struct CommandList *c)
  4784. {
  4785. dma_addr_t cmd_dma_handle, err_dma_handle;
  4786. /* Zero out all of commandlist except the last field, refcount */
  4787. memset(c, 0, offsetof(struct CommandList, refcount));
  4788. c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
  4789. cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
  4790. c->err_info = h->errinfo_pool + index;
  4791. memset(c->err_info, 0, sizeof(*c->err_info));
  4792. err_dma_handle = h->errinfo_pool_dhandle
  4793. + index * sizeof(*c->err_info);
  4794. c->cmdindex = index;
  4795. c->busaddr = (u32) cmd_dma_handle;
  4796. c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
  4797. c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
  4798. c->h = h;
  4799. c->scsi_cmd = SCSI_CMD_IDLE;
  4800. }
  4801. static void hpsa_preinitialize_commands(struct ctlr_info *h)
  4802. {
  4803. int i;
  4804. for (i = 0; i < h->nr_cmds; i++) {
  4805. struct CommandList *c = h->cmd_pool + i;
  4806. hpsa_cmd_init(h, i, c);
  4807. atomic_set(&c->refcount, 0);
  4808. }
  4809. }
  4810. static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
  4811. struct CommandList *c)
  4812. {
  4813. dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
  4814. BUG_ON(c->cmdindex != index);
  4815. memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
  4816. memset(c->err_info, 0, sizeof(*c->err_info));
  4817. c->busaddr = (u32) cmd_dma_handle;
  4818. }
  4819. static int hpsa_ioaccel_submit(struct ctlr_info *h,
  4820. struct CommandList *c, struct scsi_cmnd *cmd,
  4821. unsigned char *scsi3addr)
  4822. {
  4823. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4824. int rc = IO_ACCEL_INELIGIBLE;
  4825. if (!dev)
  4826. return SCSI_MLQUEUE_HOST_BUSY;
  4827. cmd->host_scribble = (unsigned char *) c;
  4828. if (dev->offload_enabled) {
  4829. hpsa_cmd_init(h, c->cmdindex, c);
  4830. c->cmd_type = CMD_SCSI;
  4831. c->scsi_cmd = cmd;
  4832. rc = hpsa_scsi_ioaccel_raid_map(h, c);
  4833. if (rc < 0) /* scsi_dma_map failed. */
  4834. rc = SCSI_MLQUEUE_HOST_BUSY;
  4835. } else if (dev->hba_ioaccel_enabled) {
  4836. hpsa_cmd_init(h, c->cmdindex, c);
  4837. c->cmd_type = CMD_SCSI;
  4838. c->scsi_cmd = cmd;
  4839. rc = hpsa_scsi_ioaccel_direct_map(h, c);
  4840. if (rc < 0) /* scsi_dma_map failed. */
  4841. rc = SCSI_MLQUEUE_HOST_BUSY;
  4842. }
  4843. return rc;
  4844. }
  4845. static void hpsa_command_resubmit_worker(struct work_struct *work)
  4846. {
  4847. struct scsi_cmnd *cmd;
  4848. struct hpsa_scsi_dev_t *dev;
  4849. struct CommandList *c = container_of(work, struct CommandList, work);
  4850. cmd = c->scsi_cmd;
  4851. dev = cmd->device->hostdata;
  4852. if (!dev) {
  4853. cmd->result = DID_NO_CONNECT << 16;
  4854. return hpsa_cmd_free_and_done(c->h, c, cmd);
  4855. }
  4856. if (c->reset_pending)
  4857. return hpsa_cmd_resolve_and_free(c->h, c);
  4858. if (c->abort_pending)
  4859. return hpsa_cmd_abort_and_free(c->h, c, cmd);
  4860. if (c->cmd_type == CMD_IOACCEL2) {
  4861. struct ctlr_info *h = c->h;
  4862. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  4863. int rc;
  4864. if (c2->error_data.serv_response ==
  4865. IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
  4866. rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
  4867. if (rc == 0)
  4868. return;
  4869. if (rc == SCSI_MLQUEUE_HOST_BUSY) {
  4870. /*
  4871. * If we get here, it means dma mapping failed.
  4872. * Try again via scsi mid layer, which will
  4873. * then get SCSI_MLQUEUE_HOST_BUSY.
  4874. */
  4875. cmd->result = DID_IMM_RETRY << 16;
  4876. return hpsa_cmd_free_and_done(h, c, cmd);
  4877. }
  4878. /* else, fall thru and resubmit down CISS path */
  4879. }
  4880. }
  4881. hpsa_cmd_partial_init(c->h, c->cmdindex, c);
  4882. if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
  4883. /*
  4884. * If we get here, it means dma mapping failed. Try
  4885. * again via scsi mid layer, which will then get
  4886. * SCSI_MLQUEUE_HOST_BUSY.
  4887. *
  4888. * hpsa_ciss_submit will have already freed c
  4889. * if it encountered a dma mapping failure.
  4890. */
  4891. cmd->result = DID_IMM_RETRY << 16;
  4892. cmd->scsi_done(cmd);
  4893. }
  4894. }
  4895. /* Running in struct Scsi_Host->host_lock less mode */
  4896. static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
  4897. {
  4898. struct ctlr_info *h;
  4899. struct hpsa_scsi_dev_t *dev;
  4900. unsigned char scsi3addr[8];
  4901. struct CommandList *c;
  4902. int rc = 0;
  4903. /* Get the ptr to our adapter structure out of cmd->host. */
  4904. h = sdev_to_hba(cmd->device);
  4905. BUG_ON(cmd->request->tag < 0);
  4906. dev = cmd->device->hostdata;
  4907. if (!dev) {
  4908. cmd->result = NOT_READY << 16; /* host byte */
  4909. cmd->scsi_done(cmd);
  4910. return 0;
  4911. }
  4912. if (dev->removed) {
  4913. cmd->result = DID_NO_CONNECT << 16;
  4914. cmd->scsi_done(cmd);
  4915. return 0;
  4916. }
  4917. memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
  4918. if (unlikely(lockup_detected(h))) {
  4919. cmd->result = DID_NO_CONNECT << 16;
  4920. cmd->scsi_done(cmd);
  4921. return 0;
  4922. }
  4923. c = cmd_tagged_alloc(h, cmd);
  4924. /*
  4925. * Call alternate submit routine for I/O accelerated commands.
  4926. * Retries always go down the normal I/O path.
  4927. */
  4928. if (likely(cmd->retries == 0 &&
  4929. cmd->request->cmd_type == REQ_TYPE_FS &&
  4930. h->acciopath_status)) {
  4931. rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
  4932. if (rc == 0)
  4933. return 0;
  4934. if (rc == SCSI_MLQUEUE_HOST_BUSY) {
  4935. hpsa_cmd_resolve_and_free(h, c);
  4936. return SCSI_MLQUEUE_HOST_BUSY;
  4937. }
  4938. }
  4939. return hpsa_ciss_submit(h, c, cmd, scsi3addr);
  4940. }
  4941. static void hpsa_scan_complete(struct ctlr_info *h)
  4942. {
  4943. unsigned long flags;
  4944. spin_lock_irqsave(&h->scan_lock, flags);
  4945. h->scan_finished = 1;
  4946. wake_up_all(&h->scan_wait_queue);
  4947. spin_unlock_irqrestore(&h->scan_lock, flags);
  4948. }
  4949. static void hpsa_scan_start(struct Scsi_Host *sh)
  4950. {
  4951. struct ctlr_info *h = shost_to_hba(sh);
  4952. unsigned long flags;
  4953. /*
  4954. * Don't let rescans be initiated on a controller known to be locked
  4955. * up. If the controller locks up *during* a rescan, that thread is
  4956. * probably hosed, but at least we can prevent new rescan threads from
  4957. * piling up on a locked up controller.
  4958. */
  4959. if (unlikely(lockup_detected(h)))
  4960. return hpsa_scan_complete(h);
  4961. /* wait until any scan already in progress is finished. */
  4962. while (1) {
  4963. spin_lock_irqsave(&h->scan_lock, flags);
  4964. if (h->scan_finished)
  4965. break;
  4966. spin_unlock_irqrestore(&h->scan_lock, flags);
  4967. wait_event(h->scan_wait_queue, h->scan_finished);
  4968. /* Note: We don't need to worry about a race between this
  4969. * thread and driver unload because the midlayer will
  4970. * have incremented the reference count, so unload won't
  4971. * happen if we're in here.
  4972. */
  4973. }
  4974. h->scan_finished = 0; /* mark scan as in progress */
  4975. spin_unlock_irqrestore(&h->scan_lock, flags);
  4976. if (unlikely(lockup_detected(h)))
  4977. return hpsa_scan_complete(h);
  4978. hpsa_update_scsi_devices(h);
  4979. hpsa_scan_complete(h);
  4980. }
  4981. static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
  4982. {
  4983. struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
  4984. if (!logical_drive)
  4985. return -ENODEV;
  4986. if (qdepth < 1)
  4987. qdepth = 1;
  4988. else if (qdepth > logical_drive->queue_depth)
  4989. qdepth = logical_drive->queue_depth;
  4990. return scsi_change_queue_depth(sdev, qdepth);
  4991. }
  4992. static int hpsa_scan_finished(struct Scsi_Host *sh,
  4993. unsigned long elapsed_time)
  4994. {
  4995. struct ctlr_info *h = shost_to_hba(sh);
  4996. unsigned long flags;
  4997. int finished;
  4998. spin_lock_irqsave(&h->scan_lock, flags);
  4999. finished = h->scan_finished;
  5000. spin_unlock_irqrestore(&h->scan_lock, flags);
  5001. return finished;
  5002. }
  5003. static int hpsa_scsi_host_alloc(struct ctlr_info *h)
  5004. {
  5005. struct Scsi_Host *sh;
  5006. sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
  5007. if (sh == NULL) {
  5008. dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
  5009. return -ENOMEM;
  5010. }
  5011. sh->io_port = 0;
  5012. sh->n_io_port = 0;
  5013. sh->this_id = -1;
  5014. sh->max_channel = 3;
  5015. sh->max_cmd_len = MAX_COMMAND_SIZE;
  5016. sh->max_lun = HPSA_MAX_LUN;
  5017. sh->max_id = HPSA_MAX_LUN;
  5018. sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
  5019. sh->cmd_per_lun = sh->can_queue;
  5020. sh->sg_tablesize = h->maxsgentries;
  5021. sh->transportt = hpsa_sas_transport_template;
  5022. sh->hostdata[0] = (unsigned long) h;
  5023. sh->irq = h->intr[h->intr_mode];
  5024. sh->unique_id = sh->irq;
  5025. h->scsi_host = sh;
  5026. return 0;
  5027. }
  5028. static int hpsa_scsi_add_host(struct ctlr_info *h)
  5029. {
  5030. int rv;
  5031. rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
  5032. if (rv) {
  5033. dev_err(&h->pdev->dev, "scsi_add_host failed\n");
  5034. return rv;
  5035. }
  5036. scsi_scan_host(h->scsi_host);
  5037. return 0;
  5038. }
  5039. /*
  5040. * The block layer has already gone to the trouble of picking out a unique,
  5041. * small-integer tag for this request. We use an offset from that value as
  5042. * an index to select our command block. (The offset allows us to reserve the
  5043. * low-numbered entries for our own uses.)
  5044. */
  5045. static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
  5046. {
  5047. int idx = scmd->request->tag;
  5048. if (idx < 0)
  5049. return idx;
  5050. /* Offset to leave space for internal cmds. */
  5051. return idx += HPSA_NRESERVED_CMDS;
  5052. }
  5053. /*
  5054. * Send a TEST_UNIT_READY command to the specified LUN using the specified
  5055. * reply queue; returns zero if the unit is ready, and non-zero otherwise.
  5056. */
  5057. static int hpsa_send_test_unit_ready(struct ctlr_info *h,
  5058. struct CommandList *c, unsigned char lunaddr[],
  5059. int reply_queue)
  5060. {
  5061. int rc;
  5062. /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
  5063. (void) fill_cmd(c, TEST_UNIT_READY, h,
  5064. NULL, 0, 0, lunaddr, TYPE_CMD);
  5065. rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
  5066. if (rc)
  5067. return rc;
  5068. /* no unmap needed here because no data xfer. */
  5069. /* Check if the unit is already ready. */
  5070. if (c->err_info->CommandStatus == CMD_SUCCESS)
  5071. return 0;
  5072. /*
  5073. * The first command sent after reset will receive "unit attention" to
  5074. * indicate that the LUN has been reset...this is actually what we're
  5075. * looking for (but, success is good too).
  5076. */
  5077. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  5078. c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
  5079. (c->err_info->SenseInfo[2] == NO_SENSE ||
  5080. c->err_info->SenseInfo[2] == UNIT_ATTENTION))
  5081. return 0;
  5082. return 1;
  5083. }
  5084. /*
  5085. * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
  5086. * returns zero when the unit is ready, and non-zero when giving up.
  5087. */
  5088. static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
  5089. struct CommandList *c,
  5090. unsigned char lunaddr[], int reply_queue)
  5091. {
  5092. int rc;
  5093. int count = 0;
  5094. int waittime = 1; /* seconds */
  5095. /* Send test unit ready until device ready, or give up. */
  5096. for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
  5097. /*
  5098. * Wait for a bit. do this first, because if we send
  5099. * the TUR right away, the reset will just abort it.
  5100. */
  5101. msleep(1000 * waittime);
  5102. rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
  5103. if (!rc)
  5104. break;
  5105. /* Increase wait time with each try, up to a point. */
  5106. if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
  5107. waittime *= 2;
  5108. dev_warn(&h->pdev->dev,
  5109. "waiting %d secs for device to become ready.\n",
  5110. waittime);
  5111. }
  5112. return rc;
  5113. }
  5114. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  5115. unsigned char lunaddr[],
  5116. int reply_queue)
  5117. {
  5118. int first_queue;
  5119. int last_queue;
  5120. int rq;
  5121. int rc = 0;
  5122. struct CommandList *c;
  5123. c = cmd_alloc(h);
  5124. /*
  5125. * If no specific reply queue was requested, then send the TUR
  5126. * repeatedly, requesting a reply on each reply queue; otherwise execute
  5127. * the loop exactly once using only the specified queue.
  5128. */
  5129. if (reply_queue == DEFAULT_REPLY_QUEUE) {
  5130. first_queue = 0;
  5131. last_queue = h->nreply_queues - 1;
  5132. } else {
  5133. first_queue = reply_queue;
  5134. last_queue = reply_queue;
  5135. }
  5136. for (rq = first_queue; rq <= last_queue; rq++) {
  5137. rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
  5138. if (rc)
  5139. break;
  5140. }
  5141. if (rc)
  5142. dev_warn(&h->pdev->dev, "giving up on device.\n");
  5143. else
  5144. dev_warn(&h->pdev->dev, "device is ready.\n");
  5145. cmd_free(h, c);
  5146. return rc;
  5147. }
  5148. /* Need at least one of these error handlers to keep ../scsi/hosts.c from
  5149. * complaining. Doing a host- or bus-reset can't do anything good here.
  5150. */
  5151. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
  5152. {
  5153. int rc;
  5154. struct ctlr_info *h;
  5155. struct hpsa_scsi_dev_t *dev;
  5156. u8 reset_type;
  5157. char msg[48];
  5158. /* find the controller to which the command to be aborted was sent */
  5159. h = sdev_to_hba(scsicmd->device);
  5160. if (h == NULL) /* paranoia */
  5161. return FAILED;
  5162. if (lockup_detected(h))
  5163. return FAILED;
  5164. dev = scsicmd->device->hostdata;
  5165. if (!dev) {
  5166. dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
  5167. return FAILED;
  5168. }
  5169. /* if controller locked up, we can guarantee command won't complete */
  5170. if (lockup_detected(h)) {
  5171. snprintf(msg, sizeof(msg),
  5172. "cmd %d RESET FAILED, lockup detected",
  5173. hpsa_get_cmd_index(scsicmd));
  5174. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5175. return FAILED;
  5176. }
  5177. /* this reset request might be the result of a lockup; check */
  5178. if (detect_controller_lockup(h)) {
  5179. snprintf(msg, sizeof(msg),
  5180. "cmd %d RESET FAILED, new lockup detected",
  5181. hpsa_get_cmd_index(scsicmd));
  5182. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5183. return FAILED;
  5184. }
  5185. /* Do not attempt on controller */
  5186. if (is_hba_lunid(dev->scsi3addr))
  5187. return SUCCESS;
  5188. if (is_logical_dev_addr_mode(dev->scsi3addr))
  5189. reset_type = HPSA_DEVICE_RESET_MSG;
  5190. else
  5191. reset_type = HPSA_PHYS_TARGET_RESET;
  5192. sprintf(msg, "resetting %s",
  5193. reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
  5194. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5195. h->reset_in_progress = 1;
  5196. /* send a reset to the SCSI LUN which the command was sent to */
  5197. rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
  5198. DEFAULT_REPLY_QUEUE);
  5199. sprintf(msg, "reset %s %s",
  5200. reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
  5201. rc == 0 ? "completed successfully" : "failed");
  5202. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5203. h->reset_in_progress = 0;
  5204. return rc == 0 ? SUCCESS : FAILED;
  5205. }
  5206. static void swizzle_abort_tag(u8 *tag)
  5207. {
  5208. u8 original_tag[8];
  5209. memcpy(original_tag, tag, 8);
  5210. tag[0] = original_tag[3];
  5211. tag[1] = original_tag[2];
  5212. tag[2] = original_tag[1];
  5213. tag[3] = original_tag[0];
  5214. tag[4] = original_tag[7];
  5215. tag[5] = original_tag[6];
  5216. tag[6] = original_tag[5];
  5217. tag[7] = original_tag[4];
  5218. }
  5219. static void hpsa_get_tag(struct ctlr_info *h,
  5220. struct CommandList *c, __le32 *taglower, __le32 *tagupper)
  5221. {
  5222. u64 tag;
  5223. if (c->cmd_type == CMD_IOACCEL1) {
  5224. struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
  5225. &h->ioaccel_cmd_pool[c->cmdindex];
  5226. tag = le64_to_cpu(cm1->tag);
  5227. *tagupper = cpu_to_le32(tag >> 32);
  5228. *taglower = cpu_to_le32(tag);
  5229. return;
  5230. }
  5231. if (c->cmd_type == CMD_IOACCEL2) {
  5232. struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
  5233. &h->ioaccel2_cmd_pool[c->cmdindex];
  5234. /* upper tag not used in ioaccel2 mode */
  5235. memset(tagupper, 0, sizeof(*tagupper));
  5236. *taglower = cm2->Tag;
  5237. return;
  5238. }
  5239. tag = le64_to_cpu(c->Header.tag);
  5240. *tagupper = cpu_to_le32(tag >> 32);
  5241. *taglower = cpu_to_le32(tag);
  5242. }
  5243. static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
  5244. struct CommandList *abort, int reply_queue)
  5245. {
  5246. int rc = IO_OK;
  5247. struct CommandList *c;
  5248. struct ErrorInfo *ei;
  5249. __le32 tagupper, taglower;
  5250. c = cmd_alloc(h);
  5251. /* fill_cmd can't fail here, no buffer to map */
  5252. (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
  5253. 0, 0, scsi3addr, TYPE_MSG);
  5254. if (h->needs_abort_tags_swizzled)
  5255. swizzle_abort_tag(&c->Request.CDB[4]);
  5256. (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
  5257. hpsa_get_tag(h, abort, &taglower, &tagupper);
  5258. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
  5259. __func__, tagupper, taglower);
  5260. /* no unmap needed here because no data xfer. */
  5261. ei = c->err_info;
  5262. switch (ei->CommandStatus) {
  5263. case CMD_SUCCESS:
  5264. break;
  5265. case CMD_TMF_STATUS:
  5266. rc = hpsa_evaluate_tmf_status(h, c);
  5267. break;
  5268. case CMD_UNABORTABLE: /* Very common, don't make noise. */
  5269. rc = -1;
  5270. break;
  5271. default:
  5272. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
  5273. __func__, tagupper, taglower);
  5274. hpsa_scsi_interpret_error(h, c);
  5275. rc = -1;
  5276. break;
  5277. }
  5278. cmd_free(h, c);
  5279. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
  5280. __func__, tagupper, taglower);
  5281. return rc;
  5282. }
  5283. static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
  5284. struct CommandList *command_to_abort, int reply_queue)
  5285. {
  5286. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  5287. struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
  5288. struct io_accel2_cmd *c2a =
  5289. &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
  5290. struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
  5291. struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
  5292. if (!dev)
  5293. return;
  5294. /*
  5295. * We're overlaying struct hpsa_tmf_struct on top of something which
  5296. * was allocated as a struct io_accel2_cmd, so we better be sure it
  5297. * actually fits, and doesn't overrun the error info space.
  5298. */
  5299. BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
  5300. sizeof(struct io_accel2_cmd));
  5301. BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
  5302. offsetof(struct hpsa_tmf_struct, error_len) +
  5303. sizeof(ac->error_len));
  5304. c->cmd_type = IOACCEL2_TMF;
  5305. c->scsi_cmd = SCSI_CMD_BUSY;
  5306. /* Adjust the DMA address to point to the accelerated command buffer */
  5307. c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
  5308. (c->cmdindex * sizeof(struct io_accel2_cmd));
  5309. BUG_ON(c->busaddr & 0x0000007F);
  5310. memset(ac, 0, sizeof(*c2)); /* yes this is correct */
  5311. ac->iu_type = IOACCEL2_IU_TMF_TYPE;
  5312. ac->reply_queue = reply_queue;
  5313. ac->tmf = IOACCEL2_TMF_ABORT;
  5314. ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
  5315. memset(ac->lun_id, 0, sizeof(ac->lun_id));
  5316. ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
  5317. ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
  5318. ac->error_ptr = cpu_to_le64(c->busaddr +
  5319. offsetof(struct io_accel2_cmd, error_data));
  5320. ac->error_len = cpu_to_le32(sizeof(c2->error_data));
  5321. }
  5322. /* ioaccel2 path firmware cannot handle abort task requests.
  5323. * Change abort requests to physical target reset, and send to the
  5324. * address of the physical disk used for the ioaccel 2 command.
  5325. * Return 0 on success (IO_OK)
  5326. * -1 on failure
  5327. */
  5328. static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
  5329. unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
  5330. {
  5331. int rc = IO_OK;
  5332. struct scsi_cmnd *scmd; /* scsi command within request being aborted */
  5333. struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
  5334. unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
  5335. unsigned char *psa = &phys_scsi3addr[0];
  5336. /* Get a pointer to the hpsa logical device. */
  5337. scmd = abort->scsi_cmd;
  5338. dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
  5339. if (dev == NULL) {
  5340. dev_warn(&h->pdev->dev,
  5341. "Cannot abort: no device pointer for command.\n");
  5342. return -1; /* not abortable */
  5343. }
  5344. if (h->raid_offload_debug > 0)
  5345. dev_info(&h->pdev->dev,
  5346. "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5347. h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
  5348. "Reset as abort",
  5349. scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
  5350. scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
  5351. if (!dev->offload_enabled) {
  5352. dev_warn(&h->pdev->dev,
  5353. "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
  5354. return -1; /* not abortable */
  5355. }
  5356. /* Incoming scsi3addr is logical addr. We need physical disk addr. */
  5357. if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
  5358. dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
  5359. return -1; /* not abortable */
  5360. }
  5361. /* send the reset */
  5362. if (h->raid_offload_debug > 0)
  5363. dev_info(&h->pdev->dev,
  5364. "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5365. psa[0], psa[1], psa[2], psa[3],
  5366. psa[4], psa[5], psa[6], psa[7]);
  5367. rc = hpsa_do_reset(h, dev, psa, HPSA_PHYS_TARGET_RESET, reply_queue);
  5368. if (rc != 0) {
  5369. dev_warn(&h->pdev->dev,
  5370. "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5371. psa[0], psa[1], psa[2], psa[3],
  5372. psa[4], psa[5], psa[6], psa[7]);
  5373. return rc; /* failed to reset */
  5374. }
  5375. /* wait for device to recover */
  5376. if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
  5377. dev_warn(&h->pdev->dev,
  5378. "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5379. psa[0], psa[1], psa[2], psa[3],
  5380. psa[4], psa[5], psa[6], psa[7]);
  5381. return -1; /* failed to recover */
  5382. }
  5383. /* device recovered */
  5384. dev_info(&h->pdev->dev,
  5385. "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5386. psa[0], psa[1], psa[2], psa[3],
  5387. psa[4], psa[5], psa[6], psa[7]);
  5388. return rc; /* success */
  5389. }
  5390. static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
  5391. struct CommandList *abort, int reply_queue)
  5392. {
  5393. int rc = IO_OK;
  5394. struct CommandList *c;
  5395. __le32 taglower, tagupper;
  5396. struct hpsa_scsi_dev_t *dev;
  5397. struct io_accel2_cmd *c2;
  5398. dev = abort->scsi_cmd->device->hostdata;
  5399. if (!dev)
  5400. return -1;
  5401. if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
  5402. return -1;
  5403. c = cmd_alloc(h);
  5404. setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
  5405. c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  5406. (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
  5407. hpsa_get_tag(h, abort, &taglower, &tagupper);
  5408. dev_dbg(&h->pdev->dev,
  5409. "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
  5410. __func__, tagupper, taglower);
  5411. /* no unmap needed here because no data xfer. */
  5412. dev_dbg(&h->pdev->dev,
  5413. "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
  5414. __func__, tagupper, taglower, c2->error_data.serv_response);
  5415. switch (c2->error_data.serv_response) {
  5416. case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
  5417. case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
  5418. rc = 0;
  5419. break;
  5420. case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
  5421. case IOACCEL2_SERV_RESPONSE_FAILURE:
  5422. case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
  5423. rc = -1;
  5424. break;
  5425. default:
  5426. dev_warn(&h->pdev->dev,
  5427. "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
  5428. __func__, tagupper, taglower,
  5429. c2->error_data.serv_response);
  5430. rc = -1;
  5431. }
  5432. cmd_free(h, c);
  5433. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
  5434. tagupper, taglower);
  5435. return rc;
  5436. }
  5437. static int hpsa_send_abort_both_ways(struct ctlr_info *h,
  5438. struct hpsa_scsi_dev_t *dev, struct CommandList *abort, int reply_queue)
  5439. {
  5440. /*
  5441. * ioccelerator mode 2 commands should be aborted via the
  5442. * accelerated path, since RAID path is unaware of these commands,
  5443. * but not all underlying firmware can handle abort TMF.
  5444. * Change abort to physical device reset when abort TMF is unsupported.
  5445. */
  5446. if (abort->cmd_type == CMD_IOACCEL2) {
  5447. if ((HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags) ||
  5448. dev->physical_device)
  5449. return hpsa_send_abort_ioaccel2(h, abort,
  5450. reply_queue);
  5451. else
  5452. return hpsa_send_reset_as_abort_ioaccel2(h,
  5453. dev->scsi3addr,
  5454. abort, reply_queue);
  5455. }
  5456. return hpsa_send_abort(h, dev->scsi3addr, abort, reply_queue);
  5457. }
  5458. /* Find out which reply queue a command was meant to return on */
  5459. static int hpsa_extract_reply_queue(struct ctlr_info *h,
  5460. struct CommandList *c)
  5461. {
  5462. if (c->cmd_type == CMD_IOACCEL2)
  5463. return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
  5464. return c->Header.ReplyQueue;
  5465. }
  5466. /*
  5467. * Limit concurrency of abort commands to prevent
  5468. * over-subscription of commands
  5469. */
  5470. static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
  5471. {
  5472. #define ABORT_CMD_WAIT_MSECS 5000
  5473. return !wait_event_timeout(h->abort_cmd_wait_queue,
  5474. atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
  5475. msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
  5476. }
  5477. /* Send an abort for the specified command.
  5478. * If the device and controller support it,
  5479. * send a task abort request.
  5480. */
  5481. static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
  5482. {
  5483. int rc;
  5484. struct ctlr_info *h;
  5485. struct hpsa_scsi_dev_t *dev;
  5486. struct CommandList *abort; /* pointer to command to be aborted */
  5487. struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
  5488. char msg[256]; /* For debug messaging. */
  5489. int ml = 0;
  5490. __le32 tagupper, taglower;
  5491. int refcount, reply_queue;
  5492. if (sc == NULL)
  5493. return FAILED;
  5494. if (sc->device == NULL)
  5495. return FAILED;
  5496. /* Find the controller of the command to be aborted */
  5497. h = sdev_to_hba(sc->device);
  5498. if (h == NULL)
  5499. return FAILED;
  5500. /* Find the device of the command to be aborted */
  5501. dev = sc->device->hostdata;
  5502. if (!dev) {
  5503. dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
  5504. msg);
  5505. return FAILED;
  5506. }
  5507. /* If controller locked up, we can guarantee command won't complete */
  5508. if (lockup_detected(h)) {
  5509. hpsa_show_dev_msg(KERN_WARNING, h, dev,
  5510. "ABORT FAILED, lockup detected");
  5511. return FAILED;
  5512. }
  5513. /* This is a good time to check if controller lockup has occurred */
  5514. if (detect_controller_lockup(h)) {
  5515. hpsa_show_dev_msg(KERN_WARNING, h, dev,
  5516. "ABORT FAILED, new lockup detected");
  5517. return FAILED;
  5518. }
  5519. /* Check that controller supports some kind of task abort */
  5520. if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
  5521. !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
  5522. return FAILED;
  5523. memset(msg, 0, sizeof(msg));
  5524. ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
  5525. h->scsi_host->host_no, sc->device->channel,
  5526. sc->device->id, sc->device->lun,
  5527. "Aborting command", sc);
  5528. /* Get SCSI command to be aborted */
  5529. abort = (struct CommandList *) sc->host_scribble;
  5530. if (abort == NULL) {
  5531. /* This can happen if the command already completed. */
  5532. return SUCCESS;
  5533. }
  5534. refcount = atomic_inc_return(&abort->refcount);
  5535. if (refcount == 1) { /* Command is done already. */
  5536. cmd_free(h, abort);
  5537. return SUCCESS;
  5538. }
  5539. /* Don't bother trying the abort if we know it won't work. */
  5540. if (abort->cmd_type != CMD_IOACCEL2 &&
  5541. abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
  5542. cmd_free(h, abort);
  5543. return FAILED;
  5544. }
  5545. /*
  5546. * Check that we're aborting the right command.
  5547. * It's possible the CommandList already completed and got re-used.
  5548. */
  5549. if (abort->scsi_cmd != sc) {
  5550. cmd_free(h, abort);
  5551. return SUCCESS;
  5552. }
  5553. abort->abort_pending = true;
  5554. hpsa_get_tag(h, abort, &taglower, &tagupper);
  5555. reply_queue = hpsa_extract_reply_queue(h, abort);
  5556. ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
  5557. as = abort->scsi_cmd;
  5558. if (as != NULL)
  5559. ml += sprintf(msg+ml,
  5560. "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
  5561. as->cmd_len, as->cmnd[0], as->cmnd[1],
  5562. as->serial_number);
  5563. dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
  5564. hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
  5565. /*
  5566. * Command is in flight, or possibly already completed
  5567. * by the firmware (but not to the scsi mid layer) but we can't
  5568. * distinguish which. Send the abort down.
  5569. */
  5570. if (wait_for_available_abort_cmd(h)) {
  5571. dev_warn(&h->pdev->dev,
  5572. "%s FAILED, timeout waiting for an abort command to become available.\n",
  5573. msg);
  5574. cmd_free(h, abort);
  5575. return FAILED;
  5576. }
  5577. rc = hpsa_send_abort_both_ways(h, dev, abort, reply_queue);
  5578. atomic_inc(&h->abort_cmds_available);
  5579. wake_up_all(&h->abort_cmd_wait_queue);
  5580. if (rc != 0) {
  5581. dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
  5582. hpsa_show_dev_msg(KERN_WARNING, h, dev,
  5583. "FAILED to abort command");
  5584. cmd_free(h, abort);
  5585. return FAILED;
  5586. }
  5587. dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
  5588. wait_event(h->event_sync_wait_queue,
  5589. abort->scsi_cmd != sc || lockup_detected(h));
  5590. cmd_free(h, abort);
  5591. return !lockup_detected(h) ? SUCCESS : FAILED;
  5592. }
  5593. /*
  5594. * For operations with an associated SCSI command, a command block is allocated
  5595. * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
  5596. * block request tag as an index into a table of entries. cmd_tagged_free() is
  5597. * the complement, although cmd_free() may be called instead.
  5598. */
  5599. static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
  5600. struct scsi_cmnd *scmd)
  5601. {
  5602. int idx = hpsa_get_cmd_index(scmd);
  5603. struct CommandList *c = h->cmd_pool + idx;
  5604. if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
  5605. dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
  5606. idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
  5607. /* The index value comes from the block layer, so if it's out of
  5608. * bounds, it's probably not our bug.
  5609. */
  5610. BUG();
  5611. }
  5612. atomic_inc(&c->refcount);
  5613. if (unlikely(!hpsa_is_cmd_idle(c))) {
  5614. /*
  5615. * We expect that the SCSI layer will hand us a unique tag
  5616. * value. Thus, there should never be a collision here between
  5617. * two requests...because if the selected command isn't idle
  5618. * then someone is going to be very disappointed.
  5619. */
  5620. dev_err(&h->pdev->dev,
  5621. "tag collision (tag=%d) in cmd_tagged_alloc().\n",
  5622. idx);
  5623. if (c->scsi_cmd != NULL)
  5624. scsi_print_command(c->scsi_cmd);
  5625. scsi_print_command(scmd);
  5626. }
  5627. hpsa_cmd_partial_init(h, idx, c);
  5628. return c;
  5629. }
  5630. static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
  5631. {
  5632. /*
  5633. * Release our reference to the block. We don't need to do anything
  5634. * else to free it, because it is accessed by index. (There's no point
  5635. * in checking the result of the decrement, since we cannot guarantee
  5636. * that there isn't a concurrent abort which is also accessing it.)
  5637. */
  5638. (void)atomic_dec(&c->refcount);
  5639. }
  5640. /*
  5641. * For operations that cannot sleep, a command block is allocated at init,
  5642. * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
  5643. * which ones are free or in use. Lock must be held when calling this.
  5644. * cmd_free() is the complement.
  5645. * This function never gives up and returns NULL. If it hangs,
  5646. * another thread must call cmd_free() to free some tags.
  5647. */
  5648. static struct CommandList *cmd_alloc(struct ctlr_info *h)
  5649. {
  5650. struct CommandList *c;
  5651. int refcount, i;
  5652. int offset = 0;
  5653. /*
  5654. * There is some *extremely* small but non-zero chance that that
  5655. * multiple threads could get in here, and one thread could
  5656. * be scanning through the list of bits looking for a free
  5657. * one, but the free ones are always behind him, and other
  5658. * threads sneak in behind him and eat them before he can
  5659. * get to them, so that while there is always a free one, a
  5660. * very unlucky thread might be starved anyway, never able to
  5661. * beat the other threads. In reality, this happens so
  5662. * infrequently as to be indistinguishable from never.
  5663. *
  5664. * Note that we start allocating commands before the SCSI host structure
  5665. * is initialized. Since the search starts at bit zero, this
  5666. * all works, since we have at least one command structure available;
  5667. * however, it means that the structures with the low indexes have to be
  5668. * reserved for driver-initiated requests, while requests from the block
  5669. * layer will use the higher indexes.
  5670. */
  5671. for (;;) {
  5672. i = find_next_zero_bit(h->cmd_pool_bits,
  5673. HPSA_NRESERVED_CMDS,
  5674. offset);
  5675. if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
  5676. offset = 0;
  5677. continue;
  5678. }
  5679. c = h->cmd_pool + i;
  5680. refcount = atomic_inc_return(&c->refcount);
  5681. if (unlikely(refcount > 1)) {
  5682. cmd_free(h, c); /* already in use */
  5683. offset = (i + 1) % HPSA_NRESERVED_CMDS;
  5684. continue;
  5685. }
  5686. set_bit(i & (BITS_PER_LONG - 1),
  5687. h->cmd_pool_bits + (i / BITS_PER_LONG));
  5688. break; /* it's ours now. */
  5689. }
  5690. hpsa_cmd_partial_init(h, i, c);
  5691. return c;
  5692. }
  5693. /*
  5694. * This is the complementary operation to cmd_alloc(). Note, however, in some
  5695. * corner cases it may also be used to free blocks allocated by
  5696. * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
  5697. * the clear-bit is harmless.
  5698. */
  5699. static void cmd_free(struct ctlr_info *h, struct CommandList *c)
  5700. {
  5701. if (atomic_dec_and_test(&c->refcount)) {
  5702. int i;
  5703. i = c - h->cmd_pool;
  5704. clear_bit(i & (BITS_PER_LONG - 1),
  5705. h->cmd_pool_bits + (i / BITS_PER_LONG));
  5706. }
  5707. }
  5708. #ifdef CONFIG_COMPAT
  5709. static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
  5710. void __user *arg)
  5711. {
  5712. IOCTL32_Command_struct __user *arg32 =
  5713. (IOCTL32_Command_struct __user *) arg;
  5714. IOCTL_Command_struct arg64;
  5715. IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
  5716. int err;
  5717. u32 cp;
  5718. memset(&arg64, 0, sizeof(arg64));
  5719. err = 0;
  5720. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  5721. sizeof(arg64.LUN_info));
  5722. err |= copy_from_user(&arg64.Request, &arg32->Request,
  5723. sizeof(arg64.Request));
  5724. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  5725. sizeof(arg64.error_info));
  5726. err |= get_user(arg64.buf_size, &arg32->buf_size);
  5727. err |= get_user(cp, &arg32->buf);
  5728. arg64.buf = compat_ptr(cp);
  5729. err |= copy_to_user(p, &arg64, sizeof(arg64));
  5730. if (err)
  5731. return -EFAULT;
  5732. err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
  5733. if (err)
  5734. return err;
  5735. err |= copy_in_user(&arg32->error_info, &p->error_info,
  5736. sizeof(arg32->error_info));
  5737. if (err)
  5738. return -EFAULT;
  5739. return err;
  5740. }
  5741. static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
  5742. int cmd, void __user *arg)
  5743. {
  5744. BIG_IOCTL32_Command_struct __user *arg32 =
  5745. (BIG_IOCTL32_Command_struct __user *) arg;
  5746. BIG_IOCTL_Command_struct arg64;
  5747. BIG_IOCTL_Command_struct __user *p =
  5748. compat_alloc_user_space(sizeof(arg64));
  5749. int err;
  5750. u32 cp;
  5751. memset(&arg64, 0, sizeof(arg64));
  5752. err = 0;
  5753. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  5754. sizeof(arg64.LUN_info));
  5755. err |= copy_from_user(&arg64.Request, &arg32->Request,
  5756. sizeof(arg64.Request));
  5757. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  5758. sizeof(arg64.error_info));
  5759. err |= get_user(arg64.buf_size, &arg32->buf_size);
  5760. err |= get_user(arg64.malloc_size, &arg32->malloc_size);
  5761. err |= get_user(cp, &arg32->buf);
  5762. arg64.buf = compat_ptr(cp);
  5763. err |= copy_to_user(p, &arg64, sizeof(arg64));
  5764. if (err)
  5765. return -EFAULT;
  5766. err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
  5767. if (err)
  5768. return err;
  5769. err |= copy_in_user(&arg32->error_info, &p->error_info,
  5770. sizeof(arg32->error_info));
  5771. if (err)
  5772. return -EFAULT;
  5773. return err;
  5774. }
  5775. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
  5776. {
  5777. switch (cmd) {
  5778. case CCISS_GETPCIINFO:
  5779. case CCISS_GETINTINFO:
  5780. case CCISS_SETINTINFO:
  5781. case CCISS_GETNODENAME:
  5782. case CCISS_SETNODENAME:
  5783. case CCISS_GETHEARTBEAT:
  5784. case CCISS_GETBUSTYPES:
  5785. case CCISS_GETFIRMVER:
  5786. case CCISS_GETDRIVVER:
  5787. case CCISS_REVALIDVOLS:
  5788. case CCISS_DEREGDISK:
  5789. case CCISS_REGNEWDISK:
  5790. case CCISS_REGNEWD:
  5791. case CCISS_RESCANDISK:
  5792. case CCISS_GETLUNINFO:
  5793. return hpsa_ioctl(dev, cmd, arg);
  5794. case CCISS_PASSTHRU32:
  5795. return hpsa_ioctl32_passthru(dev, cmd, arg);
  5796. case CCISS_BIG_PASSTHRU32:
  5797. return hpsa_ioctl32_big_passthru(dev, cmd, arg);
  5798. default:
  5799. return -ENOIOCTLCMD;
  5800. }
  5801. }
  5802. #endif
  5803. static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
  5804. {
  5805. struct hpsa_pci_info pciinfo;
  5806. if (!argp)
  5807. return -EINVAL;
  5808. pciinfo.domain = pci_domain_nr(h->pdev->bus);
  5809. pciinfo.bus = h->pdev->bus->number;
  5810. pciinfo.dev_fn = h->pdev->devfn;
  5811. pciinfo.board_id = h->board_id;
  5812. if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
  5813. return -EFAULT;
  5814. return 0;
  5815. }
  5816. static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
  5817. {
  5818. DriverVer_type DriverVer;
  5819. unsigned char vmaj, vmin, vsubmin;
  5820. int rc;
  5821. rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
  5822. &vmaj, &vmin, &vsubmin);
  5823. if (rc != 3) {
  5824. dev_info(&h->pdev->dev, "driver version string '%s' "
  5825. "unrecognized.", HPSA_DRIVER_VERSION);
  5826. vmaj = 0;
  5827. vmin = 0;
  5828. vsubmin = 0;
  5829. }
  5830. DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
  5831. if (!argp)
  5832. return -EINVAL;
  5833. if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
  5834. return -EFAULT;
  5835. return 0;
  5836. }
  5837. static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  5838. {
  5839. IOCTL_Command_struct iocommand;
  5840. struct CommandList *c;
  5841. char *buff = NULL;
  5842. u64 temp64;
  5843. int rc = 0;
  5844. if (!argp)
  5845. return -EINVAL;
  5846. if (!capable(CAP_SYS_RAWIO))
  5847. return -EPERM;
  5848. if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
  5849. return -EFAULT;
  5850. if ((iocommand.buf_size < 1) &&
  5851. (iocommand.Request.Type.Direction != XFER_NONE)) {
  5852. return -EINVAL;
  5853. }
  5854. if (iocommand.buf_size > 0) {
  5855. buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
  5856. if (buff == NULL)
  5857. return -ENOMEM;
  5858. if (iocommand.Request.Type.Direction & XFER_WRITE) {
  5859. /* Copy the data into the buffer we created */
  5860. if (copy_from_user(buff, iocommand.buf,
  5861. iocommand.buf_size)) {
  5862. rc = -EFAULT;
  5863. goto out_kfree;
  5864. }
  5865. } else {
  5866. memset(buff, 0, iocommand.buf_size);
  5867. }
  5868. }
  5869. c = cmd_alloc(h);
  5870. /* Fill in the command type */
  5871. c->cmd_type = CMD_IOCTL_PEND;
  5872. c->scsi_cmd = SCSI_CMD_BUSY;
  5873. /* Fill in Command Header */
  5874. c->Header.ReplyQueue = 0; /* unused in simple mode */
  5875. if (iocommand.buf_size > 0) { /* buffer to fill */
  5876. c->Header.SGList = 1;
  5877. c->Header.SGTotal = cpu_to_le16(1);
  5878. } else { /* no buffers to fill */
  5879. c->Header.SGList = 0;
  5880. c->Header.SGTotal = cpu_to_le16(0);
  5881. }
  5882. memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
  5883. /* Fill in Request block */
  5884. memcpy(&c->Request, &iocommand.Request,
  5885. sizeof(c->Request));
  5886. /* Fill in the scatter gather information */
  5887. if (iocommand.buf_size > 0) {
  5888. temp64 = pci_map_single(h->pdev, buff,
  5889. iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
  5890. if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
  5891. c->SG[0].Addr = cpu_to_le64(0);
  5892. c->SG[0].Len = cpu_to_le32(0);
  5893. rc = -ENOMEM;
  5894. goto out;
  5895. }
  5896. c->SG[0].Addr = cpu_to_le64(temp64);
  5897. c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
  5898. c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
  5899. }
  5900. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  5901. NO_TIMEOUT);
  5902. if (iocommand.buf_size > 0)
  5903. hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
  5904. check_ioctl_unit_attention(h, c);
  5905. if (rc) {
  5906. rc = -EIO;
  5907. goto out;
  5908. }
  5909. /* Copy the error information out */
  5910. memcpy(&iocommand.error_info, c->err_info,
  5911. sizeof(iocommand.error_info));
  5912. if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
  5913. rc = -EFAULT;
  5914. goto out;
  5915. }
  5916. if ((iocommand.Request.Type.Direction & XFER_READ) &&
  5917. iocommand.buf_size > 0) {
  5918. /* Copy the data out of the buffer we created */
  5919. if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
  5920. rc = -EFAULT;
  5921. goto out;
  5922. }
  5923. }
  5924. out:
  5925. cmd_free(h, c);
  5926. out_kfree:
  5927. kfree(buff);
  5928. return rc;
  5929. }
  5930. static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  5931. {
  5932. BIG_IOCTL_Command_struct *ioc;
  5933. struct CommandList *c;
  5934. unsigned char **buff = NULL;
  5935. int *buff_size = NULL;
  5936. u64 temp64;
  5937. BYTE sg_used = 0;
  5938. int status = 0;
  5939. u32 left;
  5940. u32 sz;
  5941. BYTE __user *data_ptr;
  5942. if (!argp)
  5943. return -EINVAL;
  5944. if (!capable(CAP_SYS_RAWIO))
  5945. return -EPERM;
  5946. ioc = (BIG_IOCTL_Command_struct *)
  5947. kmalloc(sizeof(*ioc), GFP_KERNEL);
  5948. if (!ioc) {
  5949. status = -ENOMEM;
  5950. goto cleanup1;
  5951. }
  5952. if (copy_from_user(ioc, argp, sizeof(*ioc))) {
  5953. status = -EFAULT;
  5954. goto cleanup1;
  5955. }
  5956. if ((ioc->buf_size < 1) &&
  5957. (ioc->Request.Type.Direction != XFER_NONE)) {
  5958. status = -EINVAL;
  5959. goto cleanup1;
  5960. }
  5961. /* Check kmalloc limits using all SGs */
  5962. if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
  5963. status = -EINVAL;
  5964. goto cleanup1;
  5965. }
  5966. if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
  5967. status = -EINVAL;
  5968. goto cleanup1;
  5969. }
  5970. buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
  5971. if (!buff) {
  5972. status = -ENOMEM;
  5973. goto cleanup1;
  5974. }
  5975. buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
  5976. if (!buff_size) {
  5977. status = -ENOMEM;
  5978. goto cleanup1;
  5979. }
  5980. left = ioc->buf_size;
  5981. data_ptr = ioc->buf;
  5982. while (left) {
  5983. sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
  5984. buff_size[sg_used] = sz;
  5985. buff[sg_used] = kmalloc(sz, GFP_KERNEL);
  5986. if (buff[sg_used] == NULL) {
  5987. status = -ENOMEM;
  5988. goto cleanup1;
  5989. }
  5990. if (ioc->Request.Type.Direction & XFER_WRITE) {
  5991. if (copy_from_user(buff[sg_used], data_ptr, sz)) {
  5992. status = -EFAULT;
  5993. goto cleanup1;
  5994. }
  5995. } else
  5996. memset(buff[sg_used], 0, sz);
  5997. left -= sz;
  5998. data_ptr += sz;
  5999. sg_used++;
  6000. }
  6001. c = cmd_alloc(h);
  6002. c->cmd_type = CMD_IOCTL_PEND;
  6003. c->scsi_cmd = SCSI_CMD_BUSY;
  6004. c->Header.ReplyQueue = 0;
  6005. c->Header.SGList = (u8) sg_used;
  6006. c->Header.SGTotal = cpu_to_le16(sg_used);
  6007. memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
  6008. memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
  6009. if (ioc->buf_size > 0) {
  6010. int i;
  6011. for (i = 0; i < sg_used; i++) {
  6012. temp64 = pci_map_single(h->pdev, buff[i],
  6013. buff_size[i], PCI_DMA_BIDIRECTIONAL);
  6014. if (dma_mapping_error(&h->pdev->dev,
  6015. (dma_addr_t) temp64)) {
  6016. c->SG[i].Addr = cpu_to_le64(0);
  6017. c->SG[i].Len = cpu_to_le32(0);
  6018. hpsa_pci_unmap(h->pdev, c, i,
  6019. PCI_DMA_BIDIRECTIONAL);
  6020. status = -ENOMEM;
  6021. goto cleanup0;
  6022. }
  6023. c->SG[i].Addr = cpu_to_le64(temp64);
  6024. c->SG[i].Len = cpu_to_le32(buff_size[i]);
  6025. c->SG[i].Ext = cpu_to_le32(0);
  6026. }
  6027. c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
  6028. }
  6029. status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  6030. NO_TIMEOUT);
  6031. if (sg_used)
  6032. hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
  6033. check_ioctl_unit_attention(h, c);
  6034. if (status) {
  6035. status = -EIO;
  6036. goto cleanup0;
  6037. }
  6038. /* Copy the error information out */
  6039. memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
  6040. if (copy_to_user(argp, ioc, sizeof(*ioc))) {
  6041. status = -EFAULT;
  6042. goto cleanup0;
  6043. }
  6044. if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
  6045. int i;
  6046. /* Copy the data out of the buffer we created */
  6047. BYTE __user *ptr = ioc->buf;
  6048. for (i = 0; i < sg_used; i++) {
  6049. if (copy_to_user(ptr, buff[i], buff_size[i])) {
  6050. status = -EFAULT;
  6051. goto cleanup0;
  6052. }
  6053. ptr += buff_size[i];
  6054. }
  6055. }
  6056. status = 0;
  6057. cleanup0:
  6058. cmd_free(h, c);
  6059. cleanup1:
  6060. if (buff) {
  6061. int i;
  6062. for (i = 0; i < sg_used; i++)
  6063. kfree(buff[i]);
  6064. kfree(buff);
  6065. }
  6066. kfree(buff_size);
  6067. kfree(ioc);
  6068. return status;
  6069. }
  6070. static void check_ioctl_unit_attention(struct ctlr_info *h,
  6071. struct CommandList *c)
  6072. {
  6073. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  6074. c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
  6075. (void) check_for_unit_attention(h, c);
  6076. }
  6077. /*
  6078. * ioctl
  6079. */
  6080. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
  6081. {
  6082. struct ctlr_info *h;
  6083. void __user *argp = (void __user *)arg;
  6084. int rc;
  6085. h = sdev_to_hba(dev);
  6086. switch (cmd) {
  6087. case CCISS_DEREGDISK:
  6088. case CCISS_REGNEWDISK:
  6089. case CCISS_REGNEWD:
  6090. hpsa_scan_start(h->scsi_host);
  6091. return 0;
  6092. case CCISS_GETPCIINFO:
  6093. return hpsa_getpciinfo_ioctl(h, argp);
  6094. case CCISS_GETDRIVVER:
  6095. return hpsa_getdrivver_ioctl(h, argp);
  6096. case CCISS_PASSTHRU:
  6097. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  6098. return -EAGAIN;
  6099. rc = hpsa_passthru_ioctl(h, argp);
  6100. atomic_inc(&h->passthru_cmds_avail);
  6101. return rc;
  6102. case CCISS_BIG_PASSTHRU:
  6103. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  6104. return -EAGAIN;
  6105. rc = hpsa_big_passthru_ioctl(h, argp);
  6106. atomic_inc(&h->passthru_cmds_avail);
  6107. return rc;
  6108. default:
  6109. return -ENOTTY;
  6110. }
  6111. }
  6112. static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
  6113. u8 reset_type)
  6114. {
  6115. struct CommandList *c;
  6116. c = cmd_alloc(h);
  6117. /* fill_cmd can't fail here, no data buffer to map */
  6118. (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
  6119. RAID_CTLR_LUNID, TYPE_MSG);
  6120. c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
  6121. c->waiting = NULL;
  6122. enqueue_cmd_and_start_io(h, c);
  6123. /* Don't wait for completion, the reset won't complete. Don't free
  6124. * the command either. This is the last command we will send before
  6125. * re-initializing everything, so it doesn't matter and won't leak.
  6126. */
  6127. return;
  6128. }
  6129. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  6130. void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
  6131. int cmd_type)
  6132. {
  6133. int pci_dir = XFER_NONE;
  6134. u64 tag; /* for commands to be aborted */
  6135. c->cmd_type = CMD_IOCTL_PEND;
  6136. c->scsi_cmd = SCSI_CMD_BUSY;
  6137. c->Header.ReplyQueue = 0;
  6138. if (buff != NULL && size > 0) {
  6139. c->Header.SGList = 1;
  6140. c->Header.SGTotal = cpu_to_le16(1);
  6141. } else {
  6142. c->Header.SGList = 0;
  6143. c->Header.SGTotal = cpu_to_le16(0);
  6144. }
  6145. memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
  6146. if (cmd_type == TYPE_CMD) {
  6147. switch (cmd) {
  6148. case HPSA_INQUIRY:
  6149. /* are we trying to read a vital product page */
  6150. if (page_code & VPD_PAGE) {
  6151. c->Request.CDB[1] = 0x01;
  6152. c->Request.CDB[2] = (page_code & 0xff);
  6153. }
  6154. c->Request.CDBLen = 6;
  6155. c->Request.type_attr_dir =
  6156. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6157. c->Request.Timeout = 0;
  6158. c->Request.CDB[0] = HPSA_INQUIRY;
  6159. c->Request.CDB[4] = size & 0xFF;
  6160. break;
  6161. case HPSA_REPORT_LOG:
  6162. case HPSA_REPORT_PHYS:
  6163. /* Talking to controller so It's a physical command
  6164. mode = 00 target = 0. Nothing to write.
  6165. */
  6166. c->Request.CDBLen = 12;
  6167. c->Request.type_attr_dir =
  6168. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6169. c->Request.Timeout = 0;
  6170. c->Request.CDB[0] = cmd;
  6171. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  6172. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6173. c->Request.CDB[8] = (size >> 8) & 0xFF;
  6174. c->Request.CDB[9] = size & 0xFF;
  6175. break;
  6176. case BMIC_SENSE_DIAG_OPTIONS:
  6177. c->Request.CDBLen = 16;
  6178. c->Request.type_attr_dir =
  6179. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6180. c->Request.Timeout = 0;
  6181. /* Spec says this should be BMIC_WRITE */
  6182. c->Request.CDB[0] = BMIC_READ;
  6183. c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
  6184. break;
  6185. case BMIC_SET_DIAG_OPTIONS:
  6186. c->Request.CDBLen = 16;
  6187. c->Request.type_attr_dir =
  6188. TYPE_ATTR_DIR(cmd_type,
  6189. ATTR_SIMPLE, XFER_WRITE);
  6190. c->Request.Timeout = 0;
  6191. c->Request.CDB[0] = BMIC_WRITE;
  6192. c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
  6193. break;
  6194. case HPSA_CACHE_FLUSH:
  6195. c->Request.CDBLen = 12;
  6196. c->Request.type_attr_dir =
  6197. TYPE_ATTR_DIR(cmd_type,
  6198. ATTR_SIMPLE, XFER_WRITE);
  6199. c->Request.Timeout = 0;
  6200. c->Request.CDB[0] = BMIC_WRITE;
  6201. c->Request.CDB[6] = BMIC_CACHE_FLUSH;
  6202. c->Request.CDB[7] = (size >> 8) & 0xFF;
  6203. c->Request.CDB[8] = size & 0xFF;
  6204. break;
  6205. case TEST_UNIT_READY:
  6206. c->Request.CDBLen = 6;
  6207. c->Request.type_attr_dir =
  6208. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6209. c->Request.Timeout = 0;
  6210. break;
  6211. case HPSA_GET_RAID_MAP:
  6212. c->Request.CDBLen = 12;
  6213. c->Request.type_attr_dir =
  6214. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6215. c->Request.Timeout = 0;
  6216. c->Request.CDB[0] = HPSA_CISS_READ;
  6217. c->Request.CDB[1] = cmd;
  6218. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  6219. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6220. c->Request.CDB[8] = (size >> 8) & 0xFF;
  6221. c->Request.CDB[9] = size & 0xFF;
  6222. break;
  6223. case BMIC_SENSE_CONTROLLER_PARAMETERS:
  6224. c->Request.CDBLen = 10;
  6225. c->Request.type_attr_dir =
  6226. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6227. c->Request.Timeout = 0;
  6228. c->Request.CDB[0] = BMIC_READ;
  6229. c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
  6230. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6231. c->Request.CDB[8] = (size >> 8) & 0xFF;
  6232. break;
  6233. case BMIC_IDENTIFY_PHYSICAL_DEVICE:
  6234. c->Request.CDBLen = 10;
  6235. c->Request.type_attr_dir =
  6236. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6237. c->Request.Timeout = 0;
  6238. c->Request.CDB[0] = BMIC_READ;
  6239. c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
  6240. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6241. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6242. break;
  6243. case BMIC_SENSE_SUBSYSTEM_INFORMATION:
  6244. c->Request.CDBLen = 10;
  6245. c->Request.type_attr_dir =
  6246. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6247. c->Request.Timeout = 0;
  6248. c->Request.CDB[0] = BMIC_READ;
  6249. c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
  6250. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6251. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6252. break;
  6253. case BMIC_SENSE_STORAGE_BOX_PARAMS:
  6254. c->Request.CDBLen = 10;
  6255. c->Request.type_attr_dir =
  6256. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6257. c->Request.Timeout = 0;
  6258. c->Request.CDB[0] = BMIC_READ;
  6259. c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS;
  6260. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6261. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6262. break;
  6263. case BMIC_IDENTIFY_CONTROLLER:
  6264. c->Request.CDBLen = 10;
  6265. c->Request.type_attr_dir =
  6266. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6267. c->Request.Timeout = 0;
  6268. c->Request.CDB[0] = BMIC_READ;
  6269. c->Request.CDB[1] = 0;
  6270. c->Request.CDB[2] = 0;
  6271. c->Request.CDB[3] = 0;
  6272. c->Request.CDB[4] = 0;
  6273. c->Request.CDB[5] = 0;
  6274. c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
  6275. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6276. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6277. c->Request.CDB[9] = 0;
  6278. break;
  6279. default:
  6280. dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
  6281. BUG();
  6282. return -1;
  6283. }
  6284. } else if (cmd_type == TYPE_MSG) {
  6285. switch (cmd) {
  6286. case HPSA_PHYS_TARGET_RESET:
  6287. c->Request.CDBLen = 16;
  6288. c->Request.type_attr_dir =
  6289. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6290. c->Request.Timeout = 0; /* Don't time out */
  6291. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  6292. c->Request.CDB[0] = HPSA_RESET;
  6293. c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
  6294. /* Physical target reset needs no control bytes 4-7*/
  6295. c->Request.CDB[4] = 0x00;
  6296. c->Request.CDB[5] = 0x00;
  6297. c->Request.CDB[6] = 0x00;
  6298. c->Request.CDB[7] = 0x00;
  6299. break;
  6300. case HPSA_DEVICE_RESET_MSG:
  6301. c->Request.CDBLen = 16;
  6302. c->Request.type_attr_dir =
  6303. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6304. c->Request.Timeout = 0; /* Don't time out */
  6305. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  6306. c->Request.CDB[0] = cmd;
  6307. c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
  6308. /* If bytes 4-7 are zero, it means reset the */
  6309. /* LunID device */
  6310. c->Request.CDB[4] = 0x00;
  6311. c->Request.CDB[5] = 0x00;
  6312. c->Request.CDB[6] = 0x00;
  6313. c->Request.CDB[7] = 0x00;
  6314. break;
  6315. case HPSA_ABORT_MSG:
  6316. memcpy(&tag, buff, sizeof(tag));
  6317. dev_dbg(&h->pdev->dev,
  6318. "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
  6319. tag, c->Header.tag);
  6320. c->Request.CDBLen = 16;
  6321. c->Request.type_attr_dir =
  6322. TYPE_ATTR_DIR(cmd_type,
  6323. ATTR_SIMPLE, XFER_WRITE);
  6324. c->Request.Timeout = 0; /* Don't time out */
  6325. c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
  6326. c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
  6327. c->Request.CDB[2] = 0x00; /* reserved */
  6328. c->Request.CDB[3] = 0x00; /* reserved */
  6329. /* Tag to abort goes in CDB[4]-CDB[11] */
  6330. memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
  6331. c->Request.CDB[12] = 0x00; /* reserved */
  6332. c->Request.CDB[13] = 0x00; /* reserved */
  6333. c->Request.CDB[14] = 0x00; /* reserved */
  6334. c->Request.CDB[15] = 0x00; /* reserved */
  6335. break;
  6336. default:
  6337. dev_warn(&h->pdev->dev, "unknown message type %d\n",
  6338. cmd);
  6339. BUG();
  6340. }
  6341. } else {
  6342. dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
  6343. BUG();
  6344. }
  6345. switch (GET_DIR(c->Request.type_attr_dir)) {
  6346. case XFER_READ:
  6347. pci_dir = PCI_DMA_FROMDEVICE;
  6348. break;
  6349. case XFER_WRITE:
  6350. pci_dir = PCI_DMA_TODEVICE;
  6351. break;
  6352. case XFER_NONE:
  6353. pci_dir = PCI_DMA_NONE;
  6354. break;
  6355. default:
  6356. pci_dir = PCI_DMA_BIDIRECTIONAL;
  6357. }
  6358. if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
  6359. return -1;
  6360. return 0;
  6361. }
  6362. /*
  6363. * Map (physical) PCI mem into (virtual) kernel space
  6364. */
  6365. static void __iomem *remap_pci_mem(ulong base, ulong size)
  6366. {
  6367. ulong page_base = ((ulong) base) & PAGE_MASK;
  6368. ulong page_offs = ((ulong) base) - page_base;
  6369. void __iomem *page_remapped = ioremap_nocache(page_base,
  6370. page_offs + size);
  6371. return page_remapped ? (page_remapped + page_offs) : NULL;
  6372. }
  6373. static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
  6374. {
  6375. return h->access.command_completed(h, q);
  6376. }
  6377. static inline bool interrupt_pending(struct ctlr_info *h)
  6378. {
  6379. return h->access.intr_pending(h);
  6380. }
  6381. static inline long interrupt_not_for_us(struct ctlr_info *h)
  6382. {
  6383. return (h->access.intr_pending(h) == 0) ||
  6384. (h->interrupts_enabled == 0);
  6385. }
  6386. static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
  6387. u32 raw_tag)
  6388. {
  6389. if (unlikely(tag_index >= h->nr_cmds)) {
  6390. dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
  6391. return 1;
  6392. }
  6393. return 0;
  6394. }
  6395. static inline void finish_cmd(struct CommandList *c)
  6396. {
  6397. dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
  6398. if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
  6399. || c->cmd_type == CMD_IOACCEL2))
  6400. complete_scsi_command(c);
  6401. else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
  6402. complete(c->waiting);
  6403. }
  6404. /* process completion of an indexed ("direct lookup") command */
  6405. static inline void process_indexed_cmd(struct ctlr_info *h,
  6406. u32 raw_tag)
  6407. {
  6408. u32 tag_index;
  6409. struct CommandList *c;
  6410. tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
  6411. if (!bad_tag(h, tag_index, raw_tag)) {
  6412. c = h->cmd_pool + tag_index;
  6413. finish_cmd(c);
  6414. }
  6415. }
  6416. /* Some controllers, like p400, will give us one interrupt
  6417. * after a soft reset, even if we turned interrupts off.
  6418. * Only need to check for this in the hpsa_xxx_discard_completions
  6419. * functions.
  6420. */
  6421. static int ignore_bogus_interrupt(struct ctlr_info *h)
  6422. {
  6423. if (likely(!reset_devices))
  6424. return 0;
  6425. if (likely(h->interrupts_enabled))
  6426. return 0;
  6427. dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
  6428. "(known firmware bug.) Ignoring.\n");
  6429. return 1;
  6430. }
  6431. /*
  6432. * Convert &h->q[x] (passed to interrupt handlers) back to h.
  6433. * Relies on (h-q[x] == x) being true for x such that
  6434. * 0 <= x < MAX_REPLY_QUEUES.
  6435. */
  6436. static struct ctlr_info *queue_to_hba(u8 *queue)
  6437. {
  6438. return container_of((queue - *queue), struct ctlr_info, q[0]);
  6439. }
  6440. static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
  6441. {
  6442. struct ctlr_info *h = queue_to_hba(queue);
  6443. u8 q = *(u8 *) queue;
  6444. u32 raw_tag;
  6445. if (ignore_bogus_interrupt(h))
  6446. return IRQ_NONE;
  6447. if (interrupt_not_for_us(h))
  6448. return IRQ_NONE;
  6449. h->last_intr_timestamp = get_jiffies_64();
  6450. while (interrupt_pending(h)) {
  6451. raw_tag = get_next_completion(h, q);
  6452. while (raw_tag != FIFO_EMPTY)
  6453. raw_tag = next_command(h, q);
  6454. }
  6455. return IRQ_HANDLED;
  6456. }
  6457. static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
  6458. {
  6459. struct ctlr_info *h = queue_to_hba(queue);
  6460. u32 raw_tag;
  6461. u8 q = *(u8 *) queue;
  6462. if (ignore_bogus_interrupt(h))
  6463. return IRQ_NONE;
  6464. h->last_intr_timestamp = get_jiffies_64();
  6465. raw_tag = get_next_completion(h, q);
  6466. while (raw_tag != FIFO_EMPTY)
  6467. raw_tag = next_command(h, q);
  6468. return IRQ_HANDLED;
  6469. }
  6470. static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
  6471. {
  6472. struct ctlr_info *h = queue_to_hba((u8 *) queue);
  6473. u32 raw_tag;
  6474. u8 q = *(u8 *) queue;
  6475. if (interrupt_not_for_us(h))
  6476. return IRQ_NONE;
  6477. h->last_intr_timestamp = get_jiffies_64();
  6478. while (interrupt_pending(h)) {
  6479. raw_tag = get_next_completion(h, q);
  6480. while (raw_tag != FIFO_EMPTY) {
  6481. process_indexed_cmd(h, raw_tag);
  6482. raw_tag = next_command(h, q);
  6483. }
  6484. }
  6485. return IRQ_HANDLED;
  6486. }
  6487. static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
  6488. {
  6489. struct ctlr_info *h = queue_to_hba(queue);
  6490. u32 raw_tag;
  6491. u8 q = *(u8 *) queue;
  6492. h->last_intr_timestamp = get_jiffies_64();
  6493. raw_tag = get_next_completion(h, q);
  6494. while (raw_tag != FIFO_EMPTY) {
  6495. process_indexed_cmd(h, raw_tag);
  6496. raw_tag = next_command(h, q);
  6497. }
  6498. return IRQ_HANDLED;
  6499. }
  6500. /* Send a message CDB to the firmware. Careful, this only works
  6501. * in simple mode, not performant mode due to the tag lookup.
  6502. * We only ever use this immediately after a controller reset.
  6503. */
  6504. static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
  6505. unsigned char type)
  6506. {
  6507. struct Command {
  6508. struct CommandListHeader CommandHeader;
  6509. struct RequestBlock Request;
  6510. struct ErrDescriptor ErrorDescriptor;
  6511. };
  6512. struct Command *cmd;
  6513. static const size_t cmd_sz = sizeof(*cmd) +
  6514. sizeof(cmd->ErrorDescriptor);
  6515. dma_addr_t paddr64;
  6516. __le32 paddr32;
  6517. u32 tag;
  6518. void __iomem *vaddr;
  6519. int i, err;
  6520. vaddr = pci_ioremap_bar(pdev, 0);
  6521. if (vaddr == NULL)
  6522. return -ENOMEM;
  6523. /* The Inbound Post Queue only accepts 32-bit physical addresses for the
  6524. * CCISS commands, so they must be allocated from the lower 4GiB of
  6525. * memory.
  6526. */
  6527. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  6528. if (err) {
  6529. iounmap(vaddr);
  6530. return err;
  6531. }
  6532. cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
  6533. if (cmd == NULL) {
  6534. iounmap(vaddr);
  6535. return -ENOMEM;
  6536. }
  6537. /* This must fit, because of the 32-bit consistent DMA mask. Also,
  6538. * although there's no guarantee, we assume that the address is at
  6539. * least 4-byte aligned (most likely, it's page-aligned).
  6540. */
  6541. paddr32 = cpu_to_le32(paddr64);
  6542. cmd->CommandHeader.ReplyQueue = 0;
  6543. cmd->CommandHeader.SGList = 0;
  6544. cmd->CommandHeader.SGTotal = cpu_to_le16(0);
  6545. cmd->CommandHeader.tag = cpu_to_le64(paddr64);
  6546. memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
  6547. cmd->Request.CDBLen = 16;
  6548. cmd->Request.type_attr_dir =
  6549. TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
  6550. cmd->Request.Timeout = 0; /* Don't time out */
  6551. cmd->Request.CDB[0] = opcode;
  6552. cmd->Request.CDB[1] = type;
  6553. memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
  6554. cmd->ErrorDescriptor.Addr =
  6555. cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
  6556. cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
  6557. writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
  6558. for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
  6559. tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
  6560. if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
  6561. break;
  6562. msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
  6563. }
  6564. iounmap(vaddr);
  6565. /* we leak the DMA buffer here ... no choice since the controller could
  6566. * still complete the command.
  6567. */
  6568. if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
  6569. dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
  6570. opcode, type);
  6571. return -ETIMEDOUT;
  6572. }
  6573. pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
  6574. if (tag & HPSA_ERROR_BIT) {
  6575. dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
  6576. opcode, type);
  6577. return -EIO;
  6578. }
  6579. dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
  6580. opcode, type);
  6581. return 0;
  6582. }
  6583. #define hpsa_noop(p) hpsa_message(p, 3, 0)
  6584. static int hpsa_controller_hard_reset(struct pci_dev *pdev,
  6585. void __iomem *vaddr, u32 use_doorbell)
  6586. {
  6587. if (use_doorbell) {
  6588. /* For everything after the P600, the PCI power state method
  6589. * of resetting the controller doesn't work, so we have this
  6590. * other way using the doorbell register.
  6591. */
  6592. dev_info(&pdev->dev, "using doorbell to reset controller\n");
  6593. writel(use_doorbell, vaddr + SA5_DOORBELL);
  6594. /* PMC hardware guys tell us we need a 10 second delay after
  6595. * doorbell reset and before any attempt to talk to the board
  6596. * at all to ensure that this actually works and doesn't fall
  6597. * over in some weird corner cases.
  6598. */
  6599. msleep(10000);
  6600. } else { /* Try to do it the PCI power state way */
  6601. /* Quoting from the Open CISS Specification: "The Power
  6602. * Management Control/Status Register (CSR) controls the power
  6603. * state of the device. The normal operating state is D0,
  6604. * CSR=00h. The software off state is D3, CSR=03h. To reset
  6605. * the controller, place the interface device in D3 then to D0,
  6606. * this causes a secondary PCI reset which will reset the
  6607. * controller." */
  6608. int rc = 0;
  6609. dev_info(&pdev->dev, "using PCI PM to reset controller\n");
  6610. /* enter the D3hot power management state */
  6611. rc = pci_set_power_state(pdev, PCI_D3hot);
  6612. if (rc)
  6613. return rc;
  6614. msleep(500);
  6615. /* enter the D0 power management state */
  6616. rc = pci_set_power_state(pdev, PCI_D0);
  6617. if (rc)
  6618. return rc;
  6619. /*
  6620. * The P600 requires a small delay when changing states.
  6621. * Otherwise we may think the board did not reset and we bail.
  6622. * This for kdump only and is particular to the P600.
  6623. */
  6624. msleep(500);
  6625. }
  6626. return 0;
  6627. }
  6628. static void init_driver_version(char *driver_version, int len)
  6629. {
  6630. memset(driver_version, 0, len);
  6631. strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
  6632. }
  6633. static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
  6634. {
  6635. char *driver_version;
  6636. int i, size = sizeof(cfgtable->driver_version);
  6637. driver_version = kmalloc(size, GFP_KERNEL);
  6638. if (!driver_version)
  6639. return -ENOMEM;
  6640. init_driver_version(driver_version, size);
  6641. for (i = 0; i < size; i++)
  6642. writeb(driver_version[i], &cfgtable->driver_version[i]);
  6643. kfree(driver_version);
  6644. return 0;
  6645. }
  6646. static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
  6647. unsigned char *driver_ver)
  6648. {
  6649. int i;
  6650. for (i = 0; i < sizeof(cfgtable->driver_version); i++)
  6651. driver_ver[i] = readb(&cfgtable->driver_version[i]);
  6652. }
  6653. static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
  6654. {
  6655. char *driver_ver, *old_driver_ver;
  6656. int rc, size = sizeof(cfgtable->driver_version);
  6657. old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
  6658. if (!old_driver_ver)
  6659. return -ENOMEM;
  6660. driver_ver = old_driver_ver + size;
  6661. /* After a reset, the 32 bytes of "driver version" in the cfgtable
  6662. * should have been changed, otherwise we know the reset failed.
  6663. */
  6664. init_driver_version(old_driver_ver, size);
  6665. read_driver_ver_from_cfgtable(cfgtable, driver_ver);
  6666. rc = !memcmp(driver_ver, old_driver_ver, size);
  6667. kfree(old_driver_ver);
  6668. return rc;
  6669. }
  6670. /* This does a hard reset of the controller using PCI power management
  6671. * states or the using the doorbell register.
  6672. */
  6673. static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
  6674. {
  6675. u64 cfg_offset;
  6676. u32 cfg_base_addr;
  6677. u64 cfg_base_addr_index;
  6678. void __iomem *vaddr;
  6679. unsigned long paddr;
  6680. u32 misc_fw_support;
  6681. int rc;
  6682. struct CfgTable __iomem *cfgtable;
  6683. u32 use_doorbell;
  6684. u16 command_register;
  6685. /* For controllers as old as the P600, this is very nearly
  6686. * the same thing as
  6687. *
  6688. * pci_save_state(pci_dev);
  6689. * pci_set_power_state(pci_dev, PCI_D3hot);
  6690. * pci_set_power_state(pci_dev, PCI_D0);
  6691. * pci_restore_state(pci_dev);
  6692. *
  6693. * For controllers newer than the P600, the pci power state
  6694. * method of resetting doesn't work so we have another way
  6695. * using the doorbell register.
  6696. */
  6697. if (!ctlr_is_resettable(board_id)) {
  6698. dev_warn(&pdev->dev, "Controller not resettable\n");
  6699. return -ENODEV;
  6700. }
  6701. /* if controller is soft- but not hard resettable... */
  6702. if (!ctlr_is_hard_resettable(board_id))
  6703. return -ENOTSUPP; /* try soft reset later. */
  6704. /* Save the PCI command register */
  6705. pci_read_config_word(pdev, 4, &command_register);
  6706. pci_save_state(pdev);
  6707. /* find the first memory BAR, so we can find the cfg table */
  6708. rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
  6709. if (rc)
  6710. return rc;
  6711. vaddr = remap_pci_mem(paddr, 0x250);
  6712. if (!vaddr)
  6713. return -ENOMEM;
  6714. /* find cfgtable in order to check if reset via doorbell is supported */
  6715. rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
  6716. &cfg_base_addr_index, &cfg_offset);
  6717. if (rc)
  6718. goto unmap_vaddr;
  6719. cfgtable = remap_pci_mem(pci_resource_start(pdev,
  6720. cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
  6721. if (!cfgtable) {
  6722. rc = -ENOMEM;
  6723. goto unmap_vaddr;
  6724. }
  6725. rc = write_driver_ver_to_cfgtable(cfgtable);
  6726. if (rc)
  6727. goto unmap_cfgtable;
  6728. /* If reset via doorbell register is supported, use that.
  6729. * There are two such methods. Favor the newest method.
  6730. */
  6731. misc_fw_support = readl(&cfgtable->misc_fw_support);
  6732. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
  6733. if (use_doorbell) {
  6734. use_doorbell = DOORBELL_CTLR_RESET2;
  6735. } else {
  6736. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
  6737. if (use_doorbell) {
  6738. dev_warn(&pdev->dev,
  6739. "Soft reset not supported. Firmware update is required.\n");
  6740. rc = -ENOTSUPP; /* try soft reset */
  6741. goto unmap_cfgtable;
  6742. }
  6743. }
  6744. rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
  6745. if (rc)
  6746. goto unmap_cfgtable;
  6747. pci_restore_state(pdev);
  6748. pci_write_config_word(pdev, 4, command_register);
  6749. /* Some devices (notably the HP Smart Array 5i Controller)
  6750. need a little pause here */
  6751. msleep(HPSA_POST_RESET_PAUSE_MSECS);
  6752. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
  6753. if (rc) {
  6754. dev_warn(&pdev->dev,
  6755. "Failed waiting for board to become ready after hard reset\n");
  6756. goto unmap_cfgtable;
  6757. }
  6758. rc = controller_reset_failed(vaddr);
  6759. if (rc < 0)
  6760. goto unmap_cfgtable;
  6761. if (rc) {
  6762. dev_warn(&pdev->dev, "Unable to successfully reset "
  6763. "controller. Will try soft reset.\n");
  6764. rc = -ENOTSUPP;
  6765. } else {
  6766. dev_info(&pdev->dev, "board ready after hard reset.\n");
  6767. }
  6768. unmap_cfgtable:
  6769. iounmap(cfgtable);
  6770. unmap_vaddr:
  6771. iounmap(vaddr);
  6772. return rc;
  6773. }
  6774. /*
  6775. * We cannot read the structure directly, for portability we must use
  6776. * the io functions.
  6777. * This is for debug only.
  6778. */
  6779. static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
  6780. {
  6781. #ifdef HPSA_DEBUG
  6782. int i;
  6783. char temp_name[17];
  6784. dev_info(dev, "Controller Configuration information\n");
  6785. dev_info(dev, "------------------------------------\n");
  6786. for (i = 0; i < 4; i++)
  6787. temp_name[i] = readb(&(tb->Signature[i]));
  6788. temp_name[4] = '\0';
  6789. dev_info(dev, " Signature = %s\n", temp_name);
  6790. dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
  6791. dev_info(dev, " Transport methods supported = 0x%x\n",
  6792. readl(&(tb->TransportSupport)));
  6793. dev_info(dev, " Transport methods active = 0x%x\n",
  6794. readl(&(tb->TransportActive)));
  6795. dev_info(dev, " Requested transport Method = 0x%x\n",
  6796. readl(&(tb->HostWrite.TransportRequest)));
  6797. dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
  6798. readl(&(tb->HostWrite.CoalIntDelay)));
  6799. dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
  6800. readl(&(tb->HostWrite.CoalIntCount)));
  6801. dev_info(dev, " Max outstanding commands = %d\n",
  6802. readl(&(tb->CmdsOutMax)));
  6803. dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
  6804. for (i = 0; i < 16; i++)
  6805. temp_name[i] = readb(&(tb->ServerName[i]));
  6806. temp_name[16] = '\0';
  6807. dev_info(dev, " Server Name = %s\n", temp_name);
  6808. dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
  6809. readl(&(tb->HeartBeat)));
  6810. #endif /* HPSA_DEBUG */
  6811. }
  6812. static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
  6813. {
  6814. int i, offset, mem_type, bar_type;
  6815. if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
  6816. return 0;
  6817. offset = 0;
  6818. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  6819. bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
  6820. if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
  6821. offset += 4;
  6822. else {
  6823. mem_type = pci_resource_flags(pdev, i) &
  6824. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  6825. switch (mem_type) {
  6826. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  6827. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  6828. offset += 4; /* 32 bit */
  6829. break;
  6830. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  6831. offset += 8;
  6832. break;
  6833. default: /* reserved in PCI 2.2 */
  6834. dev_warn(&pdev->dev,
  6835. "base address is invalid\n");
  6836. return -1;
  6837. break;
  6838. }
  6839. }
  6840. if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
  6841. return i + 1;
  6842. }
  6843. return -1;
  6844. }
  6845. static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
  6846. {
  6847. if (h->msix_vector) {
  6848. if (h->pdev->msix_enabled)
  6849. pci_disable_msix(h->pdev);
  6850. h->msix_vector = 0;
  6851. } else if (h->msi_vector) {
  6852. if (h->pdev->msi_enabled)
  6853. pci_disable_msi(h->pdev);
  6854. h->msi_vector = 0;
  6855. }
  6856. }
  6857. /* If MSI/MSI-X is supported by the kernel we will try to enable it on
  6858. * controllers that are capable. If not, we use legacy INTx mode.
  6859. */
  6860. static void hpsa_interrupt_mode(struct ctlr_info *h)
  6861. {
  6862. #ifdef CONFIG_PCI_MSI
  6863. int err, i;
  6864. struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
  6865. for (i = 0; i < MAX_REPLY_QUEUES; i++) {
  6866. hpsa_msix_entries[i].vector = 0;
  6867. hpsa_msix_entries[i].entry = i;
  6868. }
  6869. /* Some boards advertise MSI but don't really support it */
  6870. if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
  6871. (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
  6872. goto default_int_mode;
  6873. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
  6874. dev_info(&h->pdev->dev, "MSI-X capable controller\n");
  6875. h->msix_vector = MAX_REPLY_QUEUES;
  6876. if (h->msix_vector > num_online_cpus())
  6877. h->msix_vector = num_online_cpus();
  6878. err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
  6879. 1, h->msix_vector);
  6880. if (err < 0) {
  6881. dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
  6882. h->msix_vector = 0;
  6883. goto single_msi_mode;
  6884. } else if (err < h->msix_vector) {
  6885. dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
  6886. "available\n", err);
  6887. }
  6888. h->msix_vector = err;
  6889. for (i = 0; i < h->msix_vector; i++)
  6890. h->intr[i] = hpsa_msix_entries[i].vector;
  6891. return;
  6892. }
  6893. single_msi_mode:
  6894. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
  6895. dev_info(&h->pdev->dev, "MSI capable controller\n");
  6896. if (!pci_enable_msi(h->pdev))
  6897. h->msi_vector = 1;
  6898. else
  6899. dev_warn(&h->pdev->dev, "MSI init failed\n");
  6900. }
  6901. default_int_mode:
  6902. #endif /* CONFIG_PCI_MSI */
  6903. /* if we get here we're going to use the default interrupt mode */
  6904. h->intr[h->intr_mode] = h->pdev->irq;
  6905. }
  6906. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
  6907. {
  6908. int i;
  6909. u32 subsystem_vendor_id, subsystem_device_id;
  6910. subsystem_vendor_id = pdev->subsystem_vendor;
  6911. subsystem_device_id = pdev->subsystem_device;
  6912. *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
  6913. subsystem_vendor_id;
  6914. for (i = 0; i < ARRAY_SIZE(products); i++)
  6915. if (*board_id == products[i].board_id)
  6916. return i;
  6917. if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
  6918. subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
  6919. !hpsa_allow_any) {
  6920. dev_warn(&pdev->dev, "unrecognized board ID: "
  6921. "0x%08x, ignoring.\n", *board_id);
  6922. return -ENODEV;
  6923. }
  6924. return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
  6925. }
  6926. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  6927. unsigned long *memory_bar)
  6928. {
  6929. int i;
  6930. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  6931. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  6932. /* addressing mode bits already removed */
  6933. *memory_bar = pci_resource_start(pdev, i);
  6934. dev_dbg(&pdev->dev, "memory BAR = %lx\n",
  6935. *memory_bar);
  6936. return 0;
  6937. }
  6938. dev_warn(&pdev->dev, "no memory BAR found\n");
  6939. return -ENODEV;
  6940. }
  6941. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  6942. int wait_for_ready)
  6943. {
  6944. int i, iterations;
  6945. u32 scratchpad;
  6946. if (wait_for_ready)
  6947. iterations = HPSA_BOARD_READY_ITERATIONS;
  6948. else
  6949. iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
  6950. for (i = 0; i < iterations; i++) {
  6951. scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
  6952. if (wait_for_ready) {
  6953. if (scratchpad == HPSA_FIRMWARE_READY)
  6954. return 0;
  6955. } else {
  6956. if (scratchpad != HPSA_FIRMWARE_READY)
  6957. return 0;
  6958. }
  6959. msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
  6960. }
  6961. dev_warn(&pdev->dev, "board not ready, timed out.\n");
  6962. return -ENODEV;
  6963. }
  6964. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  6965. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  6966. u64 *cfg_offset)
  6967. {
  6968. *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
  6969. *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
  6970. *cfg_base_addr &= (u32) 0x0000ffff;
  6971. *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
  6972. if (*cfg_base_addr_index == -1) {
  6973. dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
  6974. return -ENODEV;
  6975. }
  6976. return 0;
  6977. }
  6978. static void hpsa_free_cfgtables(struct ctlr_info *h)
  6979. {
  6980. if (h->transtable) {
  6981. iounmap(h->transtable);
  6982. h->transtable = NULL;
  6983. }
  6984. if (h->cfgtable) {
  6985. iounmap(h->cfgtable);
  6986. h->cfgtable = NULL;
  6987. }
  6988. }
  6989. /* Find and map CISS config table and transfer table
  6990. + * several items must be unmapped (freed) later
  6991. + * */
  6992. static int hpsa_find_cfgtables(struct ctlr_info *h)
  6993. {
  6994. u64 cfg_offset;
  6995. u32 cfg_base_addr;
  6996. u64 cfg_base_addr_index;
  6997. u32 trans_offset;
  6998. int rc;
  6999. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  7000. &cfg_base_addr_index, &cfg_offset);
  7001. if (rc)
  7002. return rc;
  7003. h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
  7004. cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
  7005. if (!h->cfgtable) {
  7006. dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
  7007. return -ENOMEM;
  7008. }
  7009. rc = write_driver_ver_to_cfgtable(h->cfgtable);
  7010. if (rc)
  7011. return rc;
  7012. /* Find performant mode table. */
  7013. trans_offset = readl(&h->cfgtable->TransMethodOffset);
  7014. h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
  7015. cfg_base_addr_index)+cfg_offset+trans_offset,
  7016. sizeof(*h->transtable));
  7017. if (!h->transtable) {
  7018. dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
  7019. hpsa_free_cfgtables(h);
  7020. return -ENOMEM;
  7021. }
  7022. return 0;
  7023. }
  7024. static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
  7025. {
  7026. #define MIN_MAX_COMMANDS 16
  7027. BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
  7028. h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
  7029. /* Limit commands in memory limited kdump scenario. */
  7030. if (reset_devices && h->max_commands > 32)
  7031. h->max_commands = 32;
  7032. if (h->max_commands < MIN_MAX_COMMANDS) {
  7033. dev_warn(&h->pdev->dev,
  7034. "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
  7035. h->max_commands,
  7036. MIN_MAX_COMMANDS);
  7037. h->max_commands = MIN_MAX_COMMANDS;
  7038. }
  7039. }
  7040. /* If the controller reports that the total max sg entries is greater than 512,
  7041. * then we know that chained SG blocks work. (Original smart arrays did not
  7042. * support chained SG blocks and would return zero for max sg entries.)
  7043. */
  7044. static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
  7045. {
  7046. return h->maxsgentries > 512;
  7047. }
  7048. /* Interrogate the hardware for some limits:
  7049. * max commands, max SG elements without chaining, and with chaining,
  7050. * SG chain block size, etc.
  7051. */
  7052. static void hpsa_find_board_params(struct ctlr_info *h)
  7053. {
  7054. hpsa_get_max_perf_mode_cmds(h);
  7055. h->nr_cmds = h->max_commands;
  7056. h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
  7057. h->fw_support = readl(&(h->cfgtable->misc_fw_support));
  7058. if (hpsa_supports_chained_sg_blocks(h)) {
  7059. /* Limit in-command s/g elements to 32 save dma'able memory. */
  7060. h->max_cmd_sg_entries = 32;
  7061. h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
  7062. h->maxsgentries--; /* save one for chain pointer */
  7063. } else {
  7064. /*
  7065. * Original smart arrays supported at most 31 s/g entries
  7066. * embedded inline in the command (trying to use more
  7067. * would lock up the controller)
  7068. */
  7069. h->max_cmd_sg_entries = 31;
  7070. h->maxsgentries = 31; /* default to traditional values */
  7071. h->chainsize = 0;
  7072. }
  7073. /* Find out what task management functions are supported and cache */
  7074. h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
  7075. if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
  7076. dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
  7077. if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
  7078. dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
  7079. if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
  7080. dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
  7081. }
  7082. static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
  7083. {
  7084. if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
  7085. dev_err(&h->pdev->dev, "not a valid CISS config table\n");
  7086. return false;
  7087. }
  7088. return true;
  7089. }
  7090. static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
  7091. {
  7092. u32 driver_support;
  7093. driver_support = readl(&(h->cfgtable->driver_support));
  7094. /* Need to enable prefetch in the SCSI core for 6400 in x86 */
  7095. #ifdef CONFIG_X86
  7096. driver_support |= ENABLE_SCSI_PREFETCH;
  7097. #endif
  7098. driver_support |= ENABLE_UNIT_ATTN;
  7099. writel(driver_support, &(h->cfgtable->driver_support));
  7100. }
  7101. /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
  7102. * in a prefetch beyond physical memory.
  7103. */
  7104. static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
  7105. {
  7106. u32 dma_prefetch;
  7107. if (h->board_id != 0x3225103C)
  7108. return;
  7109. dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
  7110. dma_prefetch |= 0x8000;
  7111. writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
  7112. }
  7113. static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
  7114. {
  7115. int i;
  7116. u32 doorbell_value;
  7117. unsigned long flags;
  7118. /* wait until the clear_event_notify bit 6 is cleared by controller. */
  7119. for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
  7120. spin_lock_irqsave(&h->lock, flags);
  7121. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  7122. spin_unlock_irqrestore(&h->lock, flags);
  7123. if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
  7124. goto done;
  7125. /* delay and try again */
  7126. msleep(CLEAR_EVENT_WAIT_INTERVAL);
  7127. }
  7128. return -ENODEV;
  7129. done:
  7130. return 0;
  7131. }
  7132. static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
  7133. {
  7134. int i;
  7135. u32 doorbell_value;
  7136. unsigned long flags;
  7137. /* under certain very rare conditions, this can take awhile.
  7138. * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
  7139. * as we enter this code.)
  7140. */
  7141. for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
  7142. if (h->remove_in_progress)
  7143. goto done;
  7144. spin_lock_irqsave(&h->lock, flags);
  7145. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  7146. spin_unlock_irqrestore(&h->lock, flags);
  7147. if (!(doorbell_value & CFGTBL_ChangeReq))
  7148. goto done;
  7149. /* delay and try again */
  7150. msleep(MODE_CHANGE_WAIT_INTERVAL);
  7151. }
  7152. return -ENODEV;
  7153. done:
  7154. return 0;
  7155. }
  7156. /* return -ENODEV or other reason on error, 0 on success */
  7157. static int hpsa_enter_simple_mode(struct ctlr_info *h)
  7158. {
  7159. u32 trans_support;
  7160. trans_support = readl(&(h->cfgtable->TransportSupport));
  7161. if (!(trans_support & SIMPLE_MODE))
  7162. return -ENOTSUPP;
  7163. h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
  7164. /* Update the field, and then ring the doorbell */
  7165. writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
  7166. writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
  7167. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  7168. if (hpsa_wait_for_mode_change_ack(h))
  7169. goto error;
  7170. print_cfg_table(&h->pdev->dev, h->cfgtable);
  7171. if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
  7172. goto error;
  7173. h->transMethod = CFGTBL_Trans_Simple;
  7174. return 0;
  7175. error:
  7176. dev_err(&h->pdev->dev, "failed to enter simple mode\n");
  7177. return -ENODEV;
  7178. }
  7179. /* free items allocated or mapped by hpsa_pci_init */
  7180. static void hpsa_free_pci_init(struct ctlr_info *h)
  7181. {
  7182. hpsa_free_cfgtables(h); /* pci_init 4 */
  7183. iounmap(h->vaddr); /* pci_init 3 */
  7184. h->vaddr = NULL;
  7185. hpsa_disable_interrupt_mode(h); /* pci_init 2 */
  7186. /*
  7187. * call pci_disable_device before pci_release_regions per
  7188. * Documentation/PCI/pci.txt
  7189. */
  7190. pci_disable_device(h->pdev); /* pci_init 1 */
  7191. pci_release_regions(h->pdev); /* pci_init 2 */
  7192. }
  7193. /* several items must be freed later */
  7194. static int hpsa_pci_init(struct ctlr_info *h)
  7195. {
  7196. int prod_index, err;
  7197. prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
  7198. if (prod_index < 0)
  7199. return prod_index;
  7200. h->product_name = products[prod_index].product_name;
  7201. h->access = *(products[prod_index].access);
  7202. h->needs_abort_tags_swizzled =
  7203. ctlr_needs_abort_tags_swizzled(h->board_id);
  7204. pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
  7205. PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
  7206. err = pci_enable_device(h->pdev);
  7207. if (err) {
  7208. dev_err(&h->pdev->dev, "failed to enable PCI device\n");
  7209. pci_disable_device(h->pdev);
  7210. return err;
  7211. }
  7212. err = pci_request_regions(h->pdev, HPSA);
  7213. if (err) {
  7214. dev_err(&h->pdev->dev,
  7215. "failed to obtain PCI resources\n");
  7216. pci_disable_device(h->pdev);
  7217. return err;
  7218. }
  7219. pci_set_master(h->pdev);
  7220. hpsa_interrupt_mode(h);
  7221. err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
  7222. if (err)
  7223. goto clean2; /* intmode+region, pci */
  7224. h->vaddr = remap_pci_mem(h->paddr, 0x250);
  7225. if (!h->vaddr) {
  7226. dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
  7227. err = -ENOMEM;
  7228. goto clean2; /* intmode+region, pci */
  7229. }
  7230. err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  7231. if (err)
  7232. goto clean3; /* vaddr, intmode+region, pci */
  7233. err = hpsa_find_cfgtables(h);
  7234. if (err)
  7235. goto clean3; /* vaddr, intmode+region, pci */
  7236. hpsa_find_board_params(h);
  7237. if (!hpsa_CISS_signature_present(h)) {
  7238. err = -ENODEV;
  7239. goto clean4; /* cfgtables, vaddr, intmode+region, pci */
  7240. }
  7241. hpsa_set_driver_support_bits(h);
  7242. hpsa_p600_dma_prefetch_quirk(h);
  7243. err = hpsa_enter_simple_mode(h);
  7244. if (err)
  7245. goto clean4; /* cfgtables, vaddr, intmode+region, pci */
  7246. return 0;
  7247. clean4: /* cfgtables, vaddr, intmode+region, pci */
  7248. hpsa_free_cfgtables(h);
  7249. clean3: /* vaddr, intmode+region, pci */
  7250. iounmap(h->vaddr);
  7251. h->vaddr = NULL;
  7252. clean2: /* intmode+region, pci */
  7253. hpsa_disable_interrupt_mode(h);
  7254. /*
  7255. * call pci_disable_device before pci_release_regions per
  7256. * Documentation/PCI/pci.txt
  7257. */
  7258. pci_disable_device(h->pdev);
  7259. pci_release_regions(h->pdev);
  7260. return err;
  7261. }
  7262. static void hpsa_hba_inquiry(struct ctlr_info *h)
  7263. {
  7264. int rc;
  7265. #define HBA_INQUIRY_BYTE_COUNT 64
  7266. h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
  7267. if (!h->hba_inquiry_data)
  7268. return;
  7269. rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
  7270. h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
  7271. if (rc != 0) {
  7272. kfree(h->hba_inquiry_data);
  7273. h->hba_inquiry_data = NULL;
  7274. }
  7275. }
  7276. static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
  7277. {
  7278. int rc, i;
  7279. void __iomem *vaddr;
  7280. if (!reset_devices)
  7281. return 0;
  7282. /* kdump kernel is loading, we don't know in which state is
  7283. * the pci interface. The dev->enable_cnt is equal zero
  7284. * so we call enable+disable, wait a while and switch it on.
  7285. */
  7286. rc = pci_enable_device(pdev);
  7287. if (rc) {
  7288. dev_warn(&pdev->dev, "Failed to enable PCI device\n");
  7289. return -ENODEV;
  7290. }
  7291. pci_disable_device(pdev);
  7292. msleep(260); /* a randomly chosen number */
  7293. rc = pci_enable_device(pdev);
  7294. if (rc) {
  7295. dev_warn(&pdev->dev, "failed to enable device.\n");
  7296. return -ENODEV;
  7297. }
  7298. pci_set_master(pdev);
  7299. vaddr = pci_ioremap_bar(pdev, 0);
  7300. if (vaddr == NULL) {
  7301. rc = -ENOMEM;
  7302. goto out_disable;
  7303. }
  7304. writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  7305. iounmap(vaddr);
  7306. /* Reset the controller with a PCI power-cycle or via doorbell */
  7307. rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
  7308. /* -ENOTSUPP here means we cannot reset the controller
  7309. * but it's already (and still) up and running in
  7310. * "performant mode". Or, it might be 640x, which can't reset
  7311. * due to concerns about shared bbwc between 6402/6404 pair.
  7312. */
  7313. if (rc)
  7314. goto out_disable;
  7315. /* Now try to get the controller to respond to a no-op */
  7316. dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
  7317. for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
  7318. if (hpsa_noop(pdev) == 0)
  7319. break;
  7320. else
  7321. dev_warn(&pdev->dev, "no-op failed%s\n",
  7322. (i < 11 ? "; re-trying" : ""));
  7323. }
  7324. out_disable:
  7325. pci_disable_device(pdev);
  7326. return rc;
  7327. }
  7328. static void hpsa_free_cmd_pool(struct ctlr_info *h)
  7329. {
  7330. kfree(h->cmd_pool_bits);
  7331. h->cmd_pool_bits = NULL;
  7332. if (h->cmd_pool) {
  7333. pci_free_consistent(h->pdev,
  7334. h->nr_cmds * sizeof(struct CommandList),
  7335. h->cmd_pool,
  7336. h->cmd_pool_dhandle);
  7337. h->cmd_pool = NULL;
  7338. h->cmd_pool_dhandle = 0;
  7339. }
  7340. if (h->errinfo_pool) {
  7341. pci_free_consistent(h->pdev,
  7342. h->nr_cmds * sizeof(struct ErrorInfo),
  7343. h->errinfo_pool,
  7344. h->errinfo_pool_dhandle);
  7345. h->errinfo_pool = NULL;
  7346. h->errinfo_pool_dhandle = 0;
  7347. }
  7348. }
  7349. static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
  7350. {
  7351. h->cmd_pool_bits = kzalloc(
  7352. DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
  7353. sizeof(unsigned long), GFP_KERNEL);
  7354. h->cmd_pool = pci_alloc_consistent(h->pdev,
  7355. h->nr_cmds * sizeof(*h->cmd_pool),
  7356. &(h->cmd_pool_dhandle));
  7357. h->errinfo_pool = pci_alloc_consistent(h->pdev,
  7358. h->nr_cmds * sizeof(*h->errinfo_pool),
  7359. &(h->errinfo_pool_dhandle));
  7360. if ((h->cmd_pool_bits == NULL)
  7361. || (h->cmd_pool == NULL)
  7362. || (h->errinfo_pool == NULL)) {
  7363. dev_err(&h->pdev->dev, "out of memory in %s", __func__);
  7364. goto clean_up;
  7365. }
  7366. hpsa_preinitialize_commands(h);
  7367. return 0;
  7368. clean_up:
  7369. hpsa_free_cmd_pool(h);
  7370. return -ENOMEM;
  7371. }
  7372. static void hpsa_irq_affinity_hints(struct ctlr_info *h)
  7373. {
  7374. int i, cpu;
  7375. cpu = cpumask_first(cpu_online_mask);
  7376. for (i = 0; i < h->msix_vector; i++) {
  7377. irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
  7378. cpu = cpumask_next(cpu, cpu_online_mask);
  7379. }
  7380. }
  7381. /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
  7382. static void hpsa_free_irqs(struct ctlr_info *h)
  7383. {
  7384. int i;
  7385. if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
  7386. /* Single reply queue, only one irq to free */
  7387. i = h->intr_mode;
  7388. irq_set_affinity_hint(h->intr[i], NULL);
  7389. free_irq(h->intr[i], &h->q[i]);
  7390. h->q[i] = 0;
  7391. return;
  7392. }
  7393. for (i = 0; i < h->msix_vector; i++) {
  7394. irq_set_affinity_hint(h->intr[i], NULL);
  7395. free_irq(h->intr[i], &h->q[i]);
  7396. h->q[i] = 0;
  7397. }
  7398. for (; i < MAX_REPLY_QUEUES; i++)
  7399. h->q[i] = 0;
  7400. }
  7401. /* returns 0 on success; cleans up and returns -Enn on error */
  7402. static int hpsa_request_irqs(struct ctlr_info *h,
  7403. irqreturn_t (*msixhandler)(int, void *),
  7404. irqreturn_t (*intxhandler)(int, void *))
  7405. {
  7406. int rc, i;
  7407. /*
  7408. * initialize h->q[x] = x so that interrupt handlers know which
  7409. * queue to process.
  7410. */
  7411. for (i = 0; i < MAX_REPLY_QUEUES; i++)
  7412. h->q[i] = (u8) i;
  7413. if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
  7414. /* If performant mode and MSI-X, use multiple reply queues */
  7415. for (i = 0; i < h->msix_vector; i++) {
  7416. sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
  7417. rc = request_irq(h->intr[i], msixhandler,
  7418. 0, h->intrname[i],
  7419. &h->q[i]);
  7420. if (rc) {
  7421. int j;
  7422. dev_err(&h->pdev->dev,
  7423. "failed to get irq %d for %s\n",
  7424. h->intr[i], h->devname);
  7425. for (j = 0; j < i; j++) {
  7426. free_irq(h->intr[j], &h->q[j]);
  7427. h->q[j] = 0;
  7428. }
  7429. for (; j < MAX_REPLY_QUEUES; j++)
  7430. h->q[j] = 0;
  7431. return rc;
  7432. }
  7433. }
  7434. hpsa_irq_affinity_hints(h);
  7435. } else {
  7436. /* Use single reply pool */
  7437. if (h->msix_vector > 0 || h->msi_vector) {
  7438. if (h->msix_vector)
  7439. sprintf(h->intrname[h->intr_mode],
  7440. "%s-msix", h->devname);
  7441. else
  7442. sprintf(h->intrname[h->intr_mode],
  7443. "%s-msi", h->devname);
  7444. rc = request_irq(h->intr[h->intr_mode],
  7445. msixhandler, 0,
  7446. h->intrname[h->intr_mode],
  7447. &h->q[h->intr_mode]);
  7448. } else {
  7449. sprintf(h->intrname[h->intr_mode],
  7450. "%s-intx", h->devname);
  7451. rc = request_irq(h->intr[h->intr_mode],
  7452. intxhandler, IRQF_SHARED,
  7453. h->intrname[h->intr_mode],
  7454. &h->q[h->intr_mode]);
  7455. }
  7456. irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
  7457. }
  7458. if (rc) {
  7459. dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
  7460. h->intr[h->intr_mode], h->devname);
  7461. hpsa_free_irqs(h);
  7462. return -ENODEV;
  7463. }
  7464. return 0;
  7465. }
  7466. static int hpsa_kdump_soft_reset(struct ctlr_info *h)
  7467. {
  7468. int rc;
  7469. hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
  7470. dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
  7471. rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
  7472. if (rc) {
  7473. dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
  7474. return rc;
  7475. }
  7476. dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
  7477. rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  7478. if (rc) {
  7479. dev_warn(&h->pdev->dev, "Board failed to become ready "
  7480. "after soft reset.\n");
  7481. return rc;
  7482. }
  7483. return 0;
  7484. }
  7485. static void hpsa_free_reply_queues(struct ctlr_info *h)
  7486. {
  7487. int i;
  7488. for (i = 0; i < h->nreply_queues; i++) {
  7489. if (!h->reply_queue[i].head)
  7490. continue;
  7491. pci_free_consistent(h->pdev,
  7492. h->reply_queue_size,
  7493. h->reply_queue[i].head,
  7494. h->reply_queue[i].busaddr);
  7495. h->reply_queue[i].head = NULL;
  7496. h->reply_queue[i].busaddr = 0;
  7497. }
  7498. h->reply_queue_size = 0;
  7499. }
  7500. static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
  7501. {
  7502. hpsa_free_performant_mode(h); /* init_one 7 */
  7503. hpsa_free_sg_chain_blocks(h); /* init_one 6 */
  7504. hpsa_free_cmd_pool(h); /* init_one 5 */
  7505. hpsa_free_irqs(h); /* init_one 4 */
  7506. scsi_host_put(h->scsi_host); /* init_one 3 */
  7507. h->scsi_host = NULL; /* init_one 3 */
  7508. hpsa_free_pci_init(h); /* init_one 2_5 */
  7509. free_percpu(h->lockup_detected); /* init_one 2 */
  7510. h->lockup_detected = NULL; /* init_one 2 */
  7511. if (h->resubmit_wq) {
  7512. destroy_workqueue(h->resubmit_wq); /* init_one 1 */
  7513. h->resubmit_wq = NULL;
  7514. }
  7515. if (h->rescan_ctlr_wq) {
  7516. destroy_workqueue(h->rescan_ctlr_wq);
  7517. h->rescan_ctlr_wq = NULL;
  7518. }
  7519. kfree(h); /* init_one 1 */
  7520. }
  7521. /* Called when controller lockup detected. */
  7522. static void fail_all_outstanding_cmds(struct ctlr_info *h)
  7523. {
  7524. int i, refcount;
  7525. struct CommandList *c;
  7526. int failcount = 0;
  7527. flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
  7528. for (i = 0; i < h->nr_cmds; i++) {
  7529. c = h->cmd_pool + i;
  7530. refcount = atomic_inc_return(&c->refcount);
  7531. if (refcount > 1) {
  7532. c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
  7533. finish_cmd(c);
  7534. atomic_dec(&h->commands_outstanding);
  7535. failcount++;
  7536. }
  7537. cmd_free(h, c);
  7538. }
  7539. dev_warn(&h->pdev->dev,
  7540. "failed %d commands in fail_all\n", failcount);
  7541. }
  7542. static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
  7543. {
  7544. int cpu;
  7545. for_each_online_cpu(cpu) {
  7546. u32 *lockup_detected;
  7547. lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
  7548. *lockup_detected = value;
  7549. }
  7550. wmb(); /* be sure the per-cpu variables are out to memory */
  7551. }
  7552. static void controller_lockup_detected(struct ctlr_info *h)
  7553. {
  7554. unsigned long flags;
  7555. u32 lockup_detected;
  7556. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7557. spin_lock_irqsave(&h->lock, flags);
  7558. lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
  7559. if (!lockup_detected) {
  7560. /* no heartbeat, but controller gave us a zero. */
  7561. dev_warn(&h->pdev->dev,
  7562. "lockup detected after %d but scratchpad register is zero\n",
  7563. h->heartbeat_sample_interval / HZ);
  7564. lockup_detected = 0xffffffff;
  7565. }
  7566. set_lockup_detected_for_all_cpus(h, lockup_detected);
  7567. spin_unlock_irqrestore(&h->lock, flags);
  7568. dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
  7569. lockup_detected, h->heartbeat_sample_interval / HZ);
  7570. pci_disable_device(h->pdev);
  7571. fail_all_outstanding_cmds(h);
  7572. }
  7573. static int detect_controller_lockup(struct ctlr_info *h)
  7574. {
  7575. u64 now;
  7576. u32 heartbeat;
  7577. unsigned long flags;
  7578. now = get_jiffies_64();
  7579. /* If we've received an interrupt recently, we're ok. */
  7580. if (time_after64(h->last_intr_timestamp +
  7581. (h->heartbeat_sample_interval), now))
  7582. return false;
  7583. /*
  7584. * If we've already checked the heartbeat recently, we're ok.
  7585. * This could happen if someone sends us a signal. We
  7586. * otherwise don't care about signals in this thread.
  7587. */
  7588. if (time_after64(h->last_heartbeat_timestamp +
  7589. (h->heartbeat_sample_interval), now))
  7590. return false;
  7591. /* If heartbeat has not changed since we last looked, we're not ok. */
  7592. spin_lock_irqsave(&h->lock, flags);
  7593. heartbeat = readl(&h->cfgtable->HeartBeat);
  7594. spin_unlock_irqrestore(&h->lock, flags);
  7595. if (h->last_heartbeat == heartbeat) {
  7596. controller_lockup_detected(h);
  7597. return true;
  7598. }
  7599. /* We're ok. */
  7600. h->last_heartbeat = heartbeat;
  7601. h->last_heartbeat_timestamp = now;
  7602. return false;
  7603. }
  7604. static void hpsa_ack_ctlr_events(struct ctlr_info *h)
  7605. {
  7606. int i;
  7607. char *event_type;
  7608. if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
  7609. return;
  7610. /* Ask the controller to clear the events we're handling. */
  7611. if ((h->transMethod & (CFGTBL_Trans_io_accel1
  7612. | CFGTBL_Trans_io_accel2)) &&
  7613. (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
  7614. h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
  7615. if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
  7616. event_type = "state change";
  7617. if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
  7618. event_type = "configuration change";
  7619. /* Stop sending new RAID offload reqs via the IO accelerator */
  7620. scsi_block_requests(h->scsi_host);
  7621. for (i = 0; i < h->ndevices; i++) {
  7622. h->dev[i]->offload_enabled = 0;
  7623. h->dev[i]->offload_to_be_enabled = 0;
  7624. }
  7625. hpsa_drain_accel_commands(h);
  7626. /* Set 'accelerator path config change' bit */
  7627. dev_warn(&h->pdev->dev,
  7628. "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
  7629. h->events, event_type);
  7630. writel(h->events, &(h->cfgtable->clear_event_notify));
  7631. /* Set the "clear event notify field update" bit 6 */
  7632. writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
  7633. /* Wait until ctlr clears 'clear event notify field', bit 6 */
  7634. hpsa_wait_for_clear_event_notify_ack(h);
  7635. scsi_unblock_requests(h->scsi_host);
  7636. } else {
  7637. /* Acknowledge controller notification events. */
  7638. writel(h->events, &(h->cfgtable->clear_event_notify));
  7639. writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
  7640. hpsa_wait_for_clear_event_notify_ack(h);
  7641. #if 0
  7642. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  7643. hpsa_wait_for_mode_change_ack(h);
  7644. #endif
  7645. }
  7646. return;
  7647. }
  7648. /* Check a register on the controller to see if there are configuration
  7649. * changes (added/changed/removed logical drives, etc.) which mean that
  7650. * we should rescan the controller for devices.
  7651. * Also check flag for driver-initiated rescan.
  7652. */
  7653. static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
  7654. {
  7655. if (h->drv_req_rescan) {
  7656. h->drv_req_rescan = 0;
  7657. return 1;
  7658. }
  7659. if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
  7660. return 0;
  7661. h->events = readl(&(h->cfgtable->event_notify));
  7662. return h->events & RESCAN_REQUIRED_EVENT_BITS;
  7663. }
  7664. /*
  7665. * Check if any of the offline devices have become ready
  7666. */
  7667. static int hpsa_offline_devices_ready(struct ctlr_info *h)
  7668. {
  7669. unsigned long flags;
  7670. struct offline_device_entry *d;
  7671. struct list_head *this, *tmp;
  7672. spin_lock_irqsave(&h->offline_device_lock, flags);
  7673. list_for_each_safe(this, tmp, &h->offline_device_list) {
  7674. d = list_entry(this, struct offline_device_entry,
  7675. offline_list);
  7676. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7677. if (!hpsa_volume_offline(h, d->scsi3addr)) {
  7678. spin_lock_irqsave(&h->offline_device_lock, flags);
  7679. list_del(&d->offline_list);
  7680. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7681. return 1;
  7682. }
  7683. spin_lock_irqsave(&h->offline_device_lock, flags);
  7684. }
  7685. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7686. return 0;
  7687. }
  7688. static int hpsa_luns_changed(struct ctlr_info *h)
  7689. {
  7690. int rc = 1; /* assume there are changes */
  7691. struct ReportLUNdata *logdev = NULL;
  7692. /* if we can't find out if lun data has changed,
  7693. * assume that it has.
  7694. */
  7695. if (!h->lastlogicals)
  7696. goto out;
  7697. logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
  7698. if (!logdev) {
  7699. dev_warn(&h->pdev->dev,
  7700. "Out of memory, can't track lun changes.\n");
  7701. goto out;
  7702. }
  7703. if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
  7704. dev_warn(&h->pdev->dev,
  7705. "report luns failed, can't track lun changes.\n");
  7706. goto out;
  7707. }
  7708. if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
  7709. dev_info(&h->pdev->dev,
  7710. "Lun changes detected.\n");
  7711. memcpy(h->lastlogicals, logdev, sizeof(*logdev));
  7712. goto out;
  7713. } else
  7714. rc = 0; /* no changes detected. */
  7715. out:
  7716. kfree(logdev);
  7717. return rc;
  7718. }
  7719. static void hpsa_rescan_ctlr_worker(struct work_struct *work)
  7720. {
  7721. unsigned long flags;
  7722. struct ctlr_info *h = container_of(to_delayed_work(work),
  7723. struct ctlr_info, rescan_ctlr_work);
  7724. if (h->remove_in_progress)
  7725. return;
  7726. if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
  7727. scsi_host_get(h->scsi_host);
  7728. hpsa_ack_ctlr_events(h);
  7729. hpsa_scan_start(h->scsi_host);
  7730. scsi_host_put(h->scsi_host);
  7731. } else if (h->discovery_polling) {
  7732. hpsa_disable_rld_caching(h);
  7733. if (hpsa_luns_changed(h)) {
  7734. struct Scsi_Host *sh = NULL;
  7735. dev_info(&h->pdev->dev,
  7736. "driver discovery polling rescan.\n");
  7737. sh = scsi_host_get(h->scsi_host);
  7738. if (sh != NULL) {
  7739. hpsa_scan_start(sh);
  7740. scsi_host_put(sh);
  7741. }
  7742. }
  7743. }
  7744. spin_lock_irqsave(&h->lock, flags);
  7745. if (!h->remove_in_progress)
  7746. queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
  7747. h->heartbeat_sample_interval);
  7748. spin_unlock_irqrestore(&h->lock, flags);
  7749. }
  7750. static void hpsa_monitor_ctlr_worker(struct work_struct *work)
  7751. {
  7752. unsigned long flags;
  7753. struct ctlr_info *h = container_of(to_delayed_work(work),
  7754. struct ctlr_info, monitor_ctlr_work);
  7755. detect_controller_lockup(h);
  7756. if (lockup_detected(h))
  7757. return;
  7758. spin_lock_irqsave(&h->lock, flags);
  7759. if (!h->remove_in_progress)
  7760. schedule_delayed_work(&h->monitor_ctlr_work,
  7761. h->heartbeat_sample_interval);
  7762. spin_unlock_irqrestore(&h->lock, flags);
  7763. }
  7764. static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
  7765. char *name)
  7766. {
  7767. struct workqueue_struct *wq = NULL;
  7768. wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
  7769. if (!wq)
  7770. dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
  7771. return wq;
  7772. }
  7773. static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  7774. {
  7775. int dac, rc;
  7776. struct ctlr_info *h;
  7777. int try_soft_reset = 0;
  7778. unsigned long flags;
  7779. u32 board_id;
  7780. if (number_of_controllers == 0)
  7781. printk(KERN_INFO DRIVER_NAME "\n");
  7782. rc = hpsa_lookup_board_id(pdev, &board_id);
  7783. if (rc < 0) {
  7784. dev_warn(&pdev->dev, "Board ID not found\n");
  7785. return rc;
  7786. }
  7787. rc = hpsa_init_reset_devices(pdev, board_id);
  7788. if (rc) {
  7789. if (rc != -ENOTSUPP)
  7790. return rc;
  7791. /* If the reset fails in a particular way (it has no way to do
  7792. * a proper hard reset, so returns -ENOTSUPP) we can try to do
  7793. * a soft reset once we get the controller configured up to the
  7794. * point that it can accept a command.
  7795. */
  7796. try_soft_reset = 1;
  7797. rc = 0;
  7798. }
  7799. reinit_after_soft_reset:
  7800. /* Command structures must be aligned on a 32-byte boundary because
  7801. * the 5 lower bits of the address are used by the hardware. and by
  7802. * the driver. See comments in hpsa.h for more info.
  7803. */
  7804. BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
  7805. h = kzalloc(sizeof(*h), GFP_KERNEL);
  7806. if (!h) {
  7807. dev_err(&pdev->dev, "Failed to allocate controller head\n");
  7808. return -ENOMEM;
  7809. }
  7810. h->pdev = pdev;
  7811. h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
  7812. INIT_LIST_HEAD(&h->offline_device_list);
  7813. spin_lock_init(&h->lock);
  7814. spin_lock_init(&h->offline_device_lock);
  7815. spin_lock_init(&h->scan_lock);
  7816. atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
  7817. atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
  7818. /* Allocate and clear per-cpu variable lockup_detected */
  7819. h->lockup_detected = alloc_percpu(u32);
  7820. if (!h->lockup_detected) {
  7821. dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
  7822. rc = -ENOMEM;
  7823. goto clean1; /* aer/h */
  7824. }
  7825. set_lockup_detected_for_all_cpus(h, 0);
  7826. rc = hpsa_pci_init(h);
  7827. if (rc)
  7828. goto clean2; /* lu, aer/h */
  7829. /* relies on h-> settings made by hpsa_pci_init, including
  7830. * interrupt_mode h->intr */
  7831. rc = hpsa_scsi_host_alloc(h);
  7832. if (rc)
  7833. goto clean2_5; /* pci, lu, aer/h */
  7834. sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
  7835. h->ctlr = number_of_controllers;
  7836. number_of_controllers++;
  7837. /* configure PCI DMA stuff */
  7838. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  7839. if (rc == 0) {
  7840. dac = 1;
  7841. } else {
  7842. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  7843. if (rc == 0) {
  7844. dac = 0;
  7845. } else {
  7846. dev_err(&pdev->dev, "no suitable DMA available\n");
  7847. goto clean3; /* shost, pci, lu, aer/h */
  7848. }
  7849. }
  7850. /* make sure the board interrupts are off */
  7851. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7852. rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
  7853. if (rc)
  7854. goto clean3; /* shost, pci, lu, aer/h */
  7855. rc = hpsa_alloc_cmd_pool(h);
  7856. if (rc)
  7857. goto clean4; /* irq, shost, pci, lu, aer/h */
  7858. rc = hpsa_alloc_sg_chain_blocks(h);
  7859. if (rc)
  7860. goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
  7861. init_waitqueue_head(&h->scan_wait_queue);
  7862. init_waitqueue_head(&h->abort_cmd_wait_queue);
  7863. init_waitqueue_head(&h->event_sync_wait_queue);
  7864. mutex_init(&h->reset_mutex);
  7865. h->scan_finished = 1; /* no scan currently in progress */
  7866. pci_set_drvdata(pdev, h);
  7867. h->ndevices = 0;
  7868. spin_lock_init(&h->devlock);
  7869. rc = hpsa_put_ctlr_into_performant_mode(h);
  7870. if (rc)
  7871. goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
  7872. /* create the resubmit workqueue */
  7873. h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
  7874. if (!h->rescan_ctlr_wq) {
  7875. rc = -ENOMEM;
  7876. goto clean7;
  7877. }
  7878. h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
  7879. if (!h->resubmit_wq) {
  7880. rc = -ENOMEM;
  7881. goto clean7; /* aer/h */
  7882. }
  7883. /*
  7884. * At this point, the controller is ready to take commands.
  7885. * Now, if reset_devices and the hard reset didn't work, try
  7886. * the soft reset and see if that works.
  7887. */
  7888. if (try_soft_reset) {
  7889. /* This is kind of gross. We may or may not get a completion
  7890. * from the soft reset command, and if we do, then the value
  7891. * from the fifo may or may not be valid. So, we wait 10 secs
  7892. * after the reset throwing away any completions we get during
  7893. * that time. Unregister the interrupt handler and register
  7894. * fake ones to scoop up any residual completions.
  7895. */
  7896. spin_lock_irqsave(&h->lock, flags);
  7897. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7898. spin_unlock_irqrestore(&h->lock, flags);
  7899. hpsa_free_irqs(h);
  7900. rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
  7901. hpsa_intx_discard_completions);
  7902. if (rc) {
  7903. dev_warn(&h->pdev->dev,
  7904. "Failed to request_irq after soft reset.\n");
  7905. /*
  7906. * cannot goto clean7 or free_irqs will be called
  7907. * again. Instead, do its work
  7908. */
  7909. hpsa_free_performant_mode(h); /* clean7 */
  7910. hpsa_free_sg_chain_blocks(h); /* clean6 */
  7911. hpsa_free_cmd_pool(h); /* clean5 */
  7912. /*
  7913. * skip hpsa_free_irqs(h) clean4 since that
  7914. * was just called before request_irqs failed
  7915. */
  7916. goto clean3;
  7917. }
  7918. rc = hpsa_kdump_soft_reset(h);
  7919. if (rc)
  7920. /* Neither hard nor soft reset worked, we're hosed. */
  7921. goto clean7;
  7922. dev_info(&h->pdev->dev, "Board READY.\n");
  7923. dev_info(&h->pdev->dev,
  7924. "Waiting for stale completions to drain.\n");
  7925. h->access.set_intr_mask(h, HPSA_INTR_ON);
  7926. msleep(10000);
  7927. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7928. rc = controller_reset_failed(h->cfgtable);
  7929. if (rc)
  7930. dev_info(&h->pdev->dev,
  7931. "Soft reset appears to have failed.\n");
  7932. /* since the controller's reset, we have to go back and re-init
  7933. * everything. Easiest to just forget what we've done and do it
  7934. * all over again.
  7935. */
  7936. hpsa_undo_allocations_after_kdump_soft_reset(h);
  7937. try_soft_reset = 0;
  7938. if (rc)
  7939. /* don't goto clean, we already unallocated */
  7940. return -ENODEV;
  7941. goto reinit_after_soft_reset;
  7942. }
  7943. /* Enable Accelerated IO path at driver layer */
  7944. h->acciopath_status = 1;
  7945. /* Disable discovery polling.*/
  7946. h->discovery_polling = 0;
  7947. /* Turn the interrupts on so we can service requests */
  7948. h->access.set_intr_mask(h, HPSA_INTR_ON);
  7949. hpsa_hba_inquiry(h);
  7950. h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
  7951. if (!h->lastlogicals)
  7952. dev_info(&h->pdev->dev,
  7953. "Can't track change to report lun data\n");
  7954. /* hook into SCSI subsystem */
  7955. rc = hpsa_scsi_add_host(h);
  7956. if (rc)
  7957. goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7958. /* Monitor the controller for firmware lockups */
  7959. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  7960. INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
  7961. schedule_delayed_work(&h->monitor_ctlr_work,
  7962. h->heartbeat_sample_interval);
  7963. INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
  7964. queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
  7965. h->heartbeat_sample_interval);
  7966. return 0;
  7967. clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7968. hpsa_free_performant_mode(h);
  7969. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7970. clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
  7971. hpsa_free_sg_chain_blocks(h);
  7972. clean5: /* cmd, irq, shost, pci, lu, aer/h */
  7973. hpsa_free_cmd_pool(h);
  7974. clean4: /* irq, shost, pci, lu, aer/h */
  7975. hpsa_free_irqs(h);
  7976. clean3: /* shost, pci, lu, aer/h */
  7977. scsi_host_put(h->scsi_host);
  7978. h->scsi_host = NULL;
  7979. clean2_5: /* pci, lu, aer/h */
  7980. hpsa_free_pci_init(h);
  7981. clean2: /* lu, aer/h */
  7982. if (h->lockup_detected) {
  7983. free_percpu(h->lockup_detected);
  7984. h->lockup_detected = NULL;
  7985. }
  7986. clean1: /* wq/aer/h */
  7987. if (h->resubmit_wq) {
  7988. destroy_workqueue(h->resubmit_wq);
  7989. h->resubmit_wq = NULL;
  7990. }
  7991. if (h->rescan_ctlr_wq) {
  7992. destroy_workqueue(h->rescan_ctlr_wq);
  7993. h->rescan_ctlr_wq = NULL;
  7994. }
  7995. kfree(h);
  7996. return rc;
  7997. }
  7998. static void hpsa_flush_cache(struct ctlr_info *h)
  7999. {
  8000. char *flush_buf;
  8001. struct CommandList *c;
  8002. int rc;
  8003. if (unlikely(lockup_detected(h)))
  8004. return;
  8005. flush_buf = kzalloc(4, GFP_KERNEL);
  8006. if (!flush_buf)
  8007. return;
  8008. c = cmd_alloc(h);
  8009. if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
  8010. RAID_CTLR_LUNID, TYPE_CMD)) {
  8011. goto out;
  8012. }
  8013. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  8014. PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
  8015. if (rc)
  8016. goto out;
  8017. if (c->err_info->CommandStatus != 0)
  8018. out:
  8019. dev_warn(&h->pdev->dev,
  8020. "error flushing cache on controller\n");
  8021. cmd_free(h, c);
  8022. kfree(flush_buf);
  8023. }
  8024. /* Make controller gather fresh report lun data each time we
  8025. * send down a report luns request
  8026. */
  8027. static void hpsa_disable_rld_caching(struct ctlr_info *h)
  8028. {
  8029. u32 *options;
  8030. struct CommandList *c;
  8031. int rc;
  8032. /* Don't bother trying to set diag options if locked up */
  8033. if (unlikely(h->lockup_detected))
  8034. return;
  8035. options = kzalloc(sizeof(*options), GFP_KERNEL);
  8036. if (!options) {
  8037. dev_err(&h->pdev->dev,
  8038. "Error: failed to disable rld caching, during alloc.\n");
  8039. return;
  8040. }
  8041. c = cmd_alloc(h);
  8042. /* first, get the current diag options settings */
  8043. if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
  8044. RAID_CTLR_LUNID, TYPE_CMD))
  8045. goto errout;
  8046. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  8047. PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
  8048. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  8049. goto errout;
  8050. /* Now, set the bit for disabling the RLD caching */
  8051. *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
  8052. if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
  8053. RAID_CTLR_LUNID, TYPE_CMD))
  8054. goto errout;
  8055. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  8056. PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
  8057. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  8058. goto errout;
  8059. /* Now verify that it got set: */
  8060. if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
  8061. RAID_CTLR_LUNID, TYPE_CMD))
  8062. goto errout;
  8063. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  8064. PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
  8065. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  8066. goto errout;
  8067. if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
  8068. goto out;
  8069. errout:
  8070. dev_err(&h->pdev->dev,
  8071. "Error: failed to disable report lun data caching.\n");
  8072. out:
  8073. cmd_free(h, c);
  8074. kfree(options);
  8075. }
  8076. static void hpsa_shutdown(struct pci_dev *pdev)
  8077. {
  8078. struct ctlr_info *h;
  8079. h = pci_get_drvdata(pdev);
  8080. /* Turn board interrupts off and send the flush cache command
  8081. * sendcmd will turn off interrupt, and send the flush...
  8082. * To write all data in the battery backed cache to disks
  8083. */
  8084. hpsa_flush_cache(h);
  8085. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  8086. hpsa_free_irqs(h); /* init_one 4 */
  8087. hpsa_disable_interrupt_mode(h); /* pci_init 2 */
  8088. }
  8089. static void hpsa_free_device_info(struct ctlr_info *h)
  8090. {
  8091. int i;
  8092. for (i = 0; i < h->ndevices; i++) {
  8093. kfree(h->dev[i]);
  8094. h->dev[i] = NULL;
  8095. }
  8096. }
  8097. static void hpsa_remove_one(struct pci_dev *pdev)
  8098. {
  8099. struct ctlr_info *h;
  8100. unsigned long flags;
  8101. if (pci_get_drvdata(pdev) == NULL) {
  8102. dev_err(&pdev->dev, "unable to remove device\n");
  8103. return;
  8104. }
  8105. h = pci_get_drvdata(pdev);
  8106. /* Get rid of any controller monitoring work items */
  8107. spin_lock_irqsave(&h->lock, flags);
  8108. h->remove_in_progress = 1;
  8109. spin_unlock_irqrestore(&h->lock, flags);
  8110. cancel_delayed_work_sync(&h->monitor_ctlr_work);
  8111. cancel_delayed_work_sync(&h->rescan_ctlr_work);
  8112. destroy_workqueue(h->rescan_ctlr_wq);
  8113. destroy_workqueue(h->resubmit_wq);
  8114. /*
  8115. * Call before disabling interrupts.
  8116. * scsi_remove_host can trigger I/O operations especially
  8117. * when multipath is enabled. There can be SYNCHRONIZE CACHE
  8118. * operations which cannot complete and will hang the system.
  8119. */
  8120. if (h->scsi_host)
  8121. scsi_remove_host(h->scsi_host); /* init_one 8 */
  8122. /* includes hpsa_free_irqs - init_one 4 */
  8123. /* includes hpsa_disable_interrupt_mode - pci_init 2 */
  8124. hpsa_shutdown(pdev);
  8125. hpsa_free_device_info(h); /* scan */
  8126. kfree(h->hba_inquiry_data); /* init_one 10 */
  8127. h->hba_inquiry_data = NULL; /* init_one 10 */
  8128. hpsa_free_ioaccel2_sg_chain_blocks(h);
  8129. hpsa_free_performant_mode(h); /* init_one 7 */
  8130. hpsa_free_sg_chain_blocks(h); /* init_one 6 */
  8131. hpsa_free_cmd_pool(h); /* init_one 5 */
  8132. kfree(h->lastlogicals);
  8133. /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
  8134. scsi_host_put(h->scsi_host); /* init_one 3 */
  8135. h->scsi_host = NULL; /* init_one 3 */
  8136. /* includes hpsa_disable_interrupt_mode - pci_init 2 */
  8137. hpsa_free_pci_init(h); /* init_one 2.5 */
  8138. free_percpu(h->lockup_detected); /* init_one 2 */
  8139. h->lockup_detected = NULL; /* init_one 2 */
  8140. /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
  8141. hpsa_delete_sas_host(h);
  8142. kfree(h); /* init_one 1 */
  8143. }
  8144. static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
  8145. __attribute__((unused)) pm_message_t state)
  8146. {
  8147. return -ENOSYS;
  8148. }
  8149. static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
  8150. {
  8151. return -ENOSYS;
  8152. }
  8153. static struct pci_driver hpsa_pci_driver = {
  8154. .name = HPSA,
  8155. .probe = hpsa_init_one,
  8156. .remove = hpsa_remove_one,
  8157. .id_table = hpsa_pci_device_id, /* id_table */
  8158. .shutdown = hpsa_shutdown,
  8159. .suspend = hpsa_suspend,
  8160. .resume = hpsa_resume,
  8161. };
  8162. /* Fill in bucket_map[], given nsgs (the max number of
  8163. * scatter gather elements supported) and bucket[],
  8164. * which is an array of 8 integers. The bucket[] array
  8165. * contains 8 different DMA transfer sizes (in 16
  8166. * byte increments) which the controller uses to fetch
  8167. * commands. This function fills in bucket_map[], which
  8168. * maps a given number of scatter gather elements to one of
  8169. * the 8 DMA transfer sizes. The point of it is to allow the
  8170. * controller to only do as much DMA as needed to fetch the
  8171. * command, with the DMA transfer size encoded in the lower
  8172. * bits of the command address.
  8173. */
  8174. static void calc_bucket_map(int bucket[], int num_buckets,
  8175. int nsgs, int min_blocks, u32 *bucket_map)
  8176. {
  8177. int i, j, b, size;
  8178. /* Note, bucket_map must have nsgs+1 entries. */
  8179. for (i = 0; i <= nsgs; i++) {
  8180. /* Compute size of a command with i SG entries */
  8181. size = i + min_blocks;
  8182. b = num_buckets; /* Assume the biggest bucket */
  8183. /* Find the bucket that is just big enough */
  8184. for (j = 0; j < num_buckets; j++) {
  8185. if (bucket[j] >= size) {
  8186. b = j;
  8187. break;
  8188. }
  8189. }
  8190. /* for a command with i SG entries, use bucket b. */
  8191. bucket_map[i] = b;
  8192. }
  8193. }
  8194. /*
  8195. * return -ENODEV on err, 0 on success (or no action)
  8196. * allocates numerous items that must be freed later
  8197. */
  8198. static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
  8199. {
  8200. int i;
  8201. unsigned long register_value;
  8202. unsigned long transMethod = CFGTBL_Trans_Performant |
  8203. (trans_support & CFGTBL_Trans_use_short_tags) |
  8204. CFGTBL_Trans_enable_directed_msix |
  8205. (trans_support & (CFGTBL_Trans_io_accel1 |
  8206. CFGTBL_Trans_io_accel2));
  8207. struct access_method access = SA5_performant_access;
  8208. /* This is a bit complicated. There are 8 registers on
  8209. * the controller which we write to to tell it 8 different
  8210. * sizes of commands which there may be. It's a way of
  8211. * reducing the DMA done to fetch each command. Encoded into
  8212. * each command's tag are 3 bits which communicate to the controller
  8213. * which of the eight sizes that command fits within. The size of
  8214. * each command depends on how many scatter gather entries there are.
  8215. * Each SG entry requires 16 bytes. The eight registers are programmed
  8216. * with the number of 16-byte blocks a command of that size requires.
  8217. * The smallest command possible requires 5 such 16 byte blocks.
  8218. * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
  8219. * blocks. Note, this only extends to the SG entries contained
  8220. * within the command block, and does not extend to chained blocks
  8221. * of SG elements. bft[] contains the eight values we write to
  8222. * the registers. They are not evenly distributed, but have more
  8223. * sizes for small commands, and fewer sizes for larger commands.
  8224. */
  8225. int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
  8226. #define MIN_IOACCEL2_BFT_ENTRY 5
  8227. #define HPSA_IOACCEL2_HEADER_SZ 4
  8228. int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
  8229. 13, 14, 15, 16, 17, 18, 19,
  8230. HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
  8231. BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
  8232. BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
  8233. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
  8234. 16 * MIN_IOACCEL2_BFT_ENTRY);
  8235. BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
  8236. BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
  8237. /* 5 = 1 s/g entry or 4k
  8238. * 6 = 2 s/g entry or 8k
  8239. * 8 = 4 s/g entry or 16k
  8240. * 10 = 6 s/g entry or 24k
  8241. */
  8242. /* If the controller supports either ioaccel method then
  8243. * we can also use the RAID stack submit path that does not
  8244. * perform the superfluous readl() after each command submission.
  8245. */
  8246. if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
  8247. access = SA5_performant_access_no_read;
  8248. /* Controller spec: zero out this buffer. */
  8249. for (i = 0; i < h->nreply_queues; i++)
  8250. memset(h->reply_queue[i].head, 0, h->reply_queue_size);
  8251. bft[7] = SG_ENTRIES_IN_CMD + 4;
  8252. calc_bucket_map(bft, ARRAY_SIZE(bft),
  8253. SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
  8254. for (i = 0; i < 8; i++)
  8255. writel(bft[i], &h->transtable->BlockFetch[i]);
  8256. /* size of controller ring buffer */
  8257. writel(h->max_commands, &h->transtable->RepQSize);
  8258. writel(h->nreply_queues, &h->transtable->RepQCount);
  8259. writel(0, &h->transtable->RepQCtrAddrLow32);
  8260. writel(0, &h->transtable->RepQCtrAddrHigh32);
  8261. for (i = 0; i < h->nreply_queues; i++) {
  8262. writel(0, &h->transtable->RepQAddr[i].upper);
  8263. writel(h->reply_queue[i].busaddr,
  8264. &h->transtable->RepQAddr[i].lower);
  8265. }
  8266. writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
  8267. writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
  8268. /*
  8269. * enable outbound interrupt coalescing in accelerator mode;
  8270. */
  8271. if (trans_support & CFGTBL_Trans_io_accel1) {
  8272. access = SA5_ioaccel_mode1_access;
  8273. writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
  8274. writel(4, &h->cfgtable->HostWrite.CoalIntCount);
  8275. } else {
  8276. if (trans_support & CFGTBL_Trans_io_accel2) {
  8277. access = SA5_ioaccel_mode2_access;
  8278. writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
  8279. writel(4, &h->cfgtable->HostWrite.CoalIntCount);
  8280. }
  8281. }
  8282. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  8283. if (hpsa_wait_for_mode_change_ack(h)) {
  8284. dev_err(&h->pdev->dev,
  8285. "performant mode problem - doorbell timeout\n");
  8286. return -ENODEV;
  8287. }
  8288. register_value = readl(&(h->cfgtable->TransportActive));
  8289. if (!(register_value & CFGTBL_Trans_Performant)) {
  8290. dev_err(&h->pdev->dev,
  8291. "performant mode problem - transport not active\n");
  8292. return -ENODEV;
  8293. }
  8294. /* Change the access methods to the performant access methods */
  8295. h->access = access;
  8296. h->transMethod = transMethod;
  8297. if (!((trans_support & CFGTBL_Trans_io_accel1) ||
  8298. (trans_support & CFGTBL_Trans_io_accel2)))
  8299. return 0;
  8300. if (trans_support & CFGTBL_Trans_io_accel1) {
  8301. /* Set up I/O accelerator mode */
  8302. for (i = 0; i < h->nreply_queues; i++) {
  8303. writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
  8304. h->reply_queue[i].current_entry =
  8305. readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
  8306. }
  8307. bft[7] = h->ioaccel_maxsg + 8;
  8308. calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
  8309. h->ioaccel1_blockFetchTable);
  8310. /* initialize all reply queue entries to unused */
  8311. for (i = 0; i < h->nreply_queues; i++)
  8312. memset(h->reply_queue[i].head,
  8313. (u8) IOACCEL_MODE1_REPLY_UNUSED,
  8314. h->reply_queue_size);
  8315. /* set all the constant fields in the accelerator command
  8316. * frames once at init time to save CPU cycles later.
  8317. */
  8318. for (i = 0; i < h->nr_cmds; i++) {
  8319. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
  8320. cp->function = IOACCEL1_FUNCTION_SCSIIO;
  8321. cp->err_info = (u32) (h->errinfo_pool_dhandle +
  8322. (i * sizeof(struct ErrorInfo)));
  8323. cp->err_info_len = sizeof(struct ErrorInfo);
  8324. cp->sgl_offset = IOACCEL1_SGLOFFSET;
  8325. cp->host_context_flags =
  8326. cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
  8327. cp->timeout_sec = 0;
  8328. cp->ReplyQueue = 0;
  8329. cp->tag =
  8330. cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
  8331. cp->host_addr =
  8332. cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
  8333. (i * sizeof(struct io_accel1_cmd)));
  8334. }
  8335. } else if (trans_support & CFGTBL_Trans_io_accel2) {
  8336. u64 cfg_offset, cfg_base_addr_index;
  8337. u32 bft2_offset, cfg_base_addr;
  8338. int rc;
  8339. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  8340. &cfg_base_addr_index, &cfg_offset);
  8341. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
  8342. bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
  8343. calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
  8344. 4, h->ioaccel2_blockFetchTable);
  8345. bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
  8346. BUILD_BUG_ON(offsetof(struct CfgTable,
  8347. io_accel_request_size_offset) != 0xb8);
  8348. h->ioaccel2_bft2_regs =
  8349. remap_pci_mem(pci_resource_start(h->pdev,
  8350. cfg_base_addr_index) +
  8351. cfg_offset + bft2_offset,
  8352. ARRAY_SIZE(bft2) *
  8353. sizeof(*h->ioaccel2_bft2_regs));
  8354. for (i = 0; i < ARRAY_SIZE(bft2); i++)
  8355. writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
  8356. }
  8357. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  8358. if (hpsa_wait_for_mode_change_ack(h)) {
  8359. dev_err(&h->pdev->dev,
  8360. "performant mode problem - enabling ioaccel mode\n");
  8361. return -ENODEV;
  8362. }
  8363. return 0;
  8364. }
  8365. /* Free ioaccel1 mode command blocks and block fetch table */
  8366. static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
  8367. {
  8368. if (h->ioaccel_cmd_pool) {
  8369. pci_free_consistent(h->pdev,
  8370. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
  8371. h->ioaccel_cmd_pool,
  8372. h->ioaccel_cmd_pool_dhandle);
  8373. h->ioaccel_cmd_pool = NULL;
  8374. h->ioaccel_cmd_pool_dhandle = 0;
  8375. }
  8376. kfree(h->ioaccel1_blockFetchTable);
  8377. h->ioaccel1_blockFetchTable = NULL;
  8378. }
  8379. /* Allocate ioaccel1 mode command blocks and block fetch table */
  8380. static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
  8381. {
  8382. h->ioaccel_maxsg =
  8383. readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
  8384. if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
  8385. h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
  8386. /* Command structures must be aligned on a 128-byte boundary
  8387. * because the 7 lower bits of the address are used by the
  8388. * hardware.
  8389. */
  8390. BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
  8391. IOACCEL1_COMMANDLIST_ALIGNMENT);
  8392. h->ioaccel_cmd_pool =
  8393. pci_alloc_consistent(h->pdev,
  8394. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
  8395. &(h->ioaccel_cmd_pool_dhandle));
  8396. h->ioaccel1_blockFetchTable =
  8397. kmalloc(((h->ioaccel_maxsg + 1) *
  8398. sizeof(u32)), GFP_KERNEL);
  8399. if ((h->ioaccel_cmd_pool == NULL) ||
  8400. (h->ioaccel1_blockFetchTable == NULL))
  8401. goto clean_up;
  8402. memset(h->ioaccel_cmd_pool, 0,
  8403. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
  8404. return 0;
  8405. clean_up:
  8406. hpsa_free_ioaccel1_cmd_and_bft(h);
  8407. return -ENOMEM;
  8408. }
  8409. /* Free ioaccel2 mode command blocks and block fetch table */
  8410. static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
  8411. {
  8412. hpsa_free_ioaccel2_sg_chain_blocks(h);
  8413. if (h->ioaccel2_cmd_pool) {
  8414. pci_free_consistent(h->pdev,
  8415. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
  8416. h->ioaccel2_cmd_pool,
  8417. h->ioaccel2_cmd_pool_dhandle);
  8418. h->ioaccel2_cmd_pool = NULL;
  8419. h->ioaccel2_cmd_pool_dhandle = 0;
  8420. }
  8421. kfree(h->ioaccel2_blockFetchTable);
  8422. h->ioaccel2_blockFetchTable = NULL;
  8423. }
  8424. /* Allocate ioaccel2 mode command blocks and block fetch table */
  8425. static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
  8426. {
  8427. int rc;
  8428. /* Allocate ioaccel2 mode command blocks and block fetch table */
  8429. h->ioaccel_maxsg =
  8430. readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
  8431. if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
  8432. h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
  8433. BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
  8434. IOACCEL2_COMMANDLIST_ALIGNMENT);
  8435. h->ioaccel2_cmd_pool =
  8436. pci_alloc_consistent(h->pdev,
  8437. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
  8438. &(h->ioaccel2_cmd_pool_dhandle));
  8439. h->ioaccel2_blockFetchTable =
  8440. kmalloc(((h->ioaccel_maxsg + 1) *
  8441. sizeof(u32)), GFP_KERNEL);
  8442. if ((h->ioaccel2_cmd_pool == NULL) ||
  8443. (h->ioaccel2_blockFetchTable == NULL)) {
  8444. rc = -ENOMEM;
  8445. goto clean_up;
  8446. }
  8447. rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
  8448. if (rc)
  8449. goto clean_up;
  8450. memset(h->ioaccel2_cmd_pool, 0,
  8451. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
  8452. return 0;
  8453. clean_up:
  8454. hpsa_free_ioaccel2_cmd_and_bft(h);
  8455. return rc;
  8456. }
  8457. /* Free items allocated by hpsa_put_ctlr_into_performant_mode */
  8458. static void hpsa_free_performant_mode(struct ctlr_info *h)
  8459. {
  8460. kfree(h->blockFetchTable);
  8461. h->blockFetchTable = NULL;
  8462. hpsa_free_reply_queues(h);
  8463. hpsa_free_ioaccel1_cmd_and_bft(h);
  8464. hpsa_free_ioaccel2_cmd_and_bft(h);
  8465. }
  8466. /* return -ENODEV on error, 0 on success (or no action)
  8467. * allocates numerous items that must be freed later
  8468. */
  8469. static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
  8470. {
  8471. u32 trans_support;
  8472. unsigned long transMethod = CFGTBL_Trans_Performant |
  8473. CFGTBL_Trans_use_short_tags;
  8474. int i, rc;
  8475. if (hpsa_simple_mode)
  8476. return 0;
  8477. trans_support = readl(&(h->cfgtable->TransportSupport));
  8478. if (!(trans_support & PERFORMANT_MODE))
  8479. return 0;
  8480. /* Check for I/O accelerator mode support */
  8481. if (trans_support & CFGTBL_Trans_io_accel1) {
  8482. transMethod |= CFGTBL_Trans_io_accel1 |
  8483. CFGTBL_Trans_enable_directed_msix;
  8484. rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
  8485. if (rc)
  8486. return rc;
  8487. } else if (trans_support & CFGTBL_Trans_io_accel2) {
  8488. transMethod |= CFGTBL_Trans_io_accel2 |
  8489. CFGTBL_Trans_enable_directed_msix;
  8490. rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
  8491. if (rc)
  8492. return rc;
  8493. }
  8494. h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
  8495. hpsa_get_max_perf_mode_cmds(h);
  8496. /* Performant mode ring buffer and supporting data structures */
  8497. h->reply_queue_size = h->max_commands * sizeof(u64);
  8498. for (i = 0; i < h->nreply_queues; i++) {
  8499. h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
  8500. h->reply_queue_size,
  8501. &(h->reply_queue[i].busaddr));
  8502. if (!h->reply_queue[i].head) {
  8503. rc = -ENOMEM;
  8504. goto clean1; /* rq, ioaccel */
  8505. }
  8506. h->reply_queue[i].size = h->max_commands;
  8507. h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
  8508. h->reply_queue[i].current_entry = 0;
  8509. }
  8510. /* Need a block fetch table for performant mode */
  8511. h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
  8512. sizeof(u32)), GFP_KERNEL);
  8513. if (!h->blockFetchTable) {
  8514. rc = -ENOMEM;
  8515. goto clean1; /* rq, ioaccel */
  8516. }
  8517. rc = hpsa_enter_performant_mode(h, trans_support);
  8518. if (rc)
  8519. goto clean2; /* bft, rq, ioaccel */
  8520. return 0;
  8521. clean2: /* bft, rq, ioaccel */
  8522. kfree(h->blockFetchTable);
  8523. h->blockFetchTable = NULL;
  8524. clean1: /* rq, ioaccel */
  8525. hpsa_free_reply_queues(h);
  8526. hpsa_free_ioaccel1_cmd_and_bft(h);
  8527. hpsa_free_ioaccel2_cmd_and_bft(h);
  8528. return rc;
  8529. }
  8530. static int is_accelerated_cmd(struct CommandList *c)
  8531. {
  8532. return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
  8533. }
  8534. static void hpsa_drain_accel_commands(struct ctlr_info *h)
  8535. {
  8536. struct CommandList *c = NULL;
  8537. int i, accel_cmds_out;
  8538. int refcount;
  8539. do { /* wait for all outstanding ioaccel commands to drain out */
  8540. accel_cmds_out = 0;
  8541. for (i = 0; i < h->nr_cmds; i++) {
  8542. c = h->cmd_pool + i;
  8543. refcount = atomic_inc_return(&c->refcount);
  8544. if (refcount > 1) /* Command is allocated */
  8545. accel_cmds_out += is_accelerated_cmd(c);
  8546. cmd_free(h, c);
  8547. }
  8548. if (accel_cmds_out <= 0)
  8549. break;
  8550. msleep(100);
  8551. } while (1);
  8552. }
  8553. static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
  8554. struct hpsa_sas_port *hpsa_sas_port)
  8555. {
  8556. struct hpsa_sas_phy *hpsa_sas_phy;
  8557. struct sas_phy *phy;
  8558. hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL);
  8559. if (!hpsa_sas_phy)
  8560. return NULL;
  8561. phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
  8562. hpsa_sas_port->next_phy_index);
  8563. if (!phy) {
  8564. kfree(hpsa_sas_phy);
  8565. return NULL;
  8566. }
  8567. hpsa_sas_port->next_phy_index++;
  8568. hpsa_sas_phy->phy = phy;
  8569. hpsa_sas_phy->parent_port = hpsa_sas_port;
  8570. return hpsa_sas_phy;
  8571. }
  8572. static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
  8573. {
  8574. struct sas_phy *phy = hpsa_sas_phy->phy;
  8575. sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
  8576. sas_phy_free(phy);
  8577. if (hpsa_sas_phy->added_to_port)
  8578. list_del(&hpsa_sas_phy->phy_list_entry);
  8579. kfree(hpsa_sas_phy);
  8580. }
  8581. static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
  8582. {
  8583. int rc;
  8584. struct hpsa_sas_port *hpsa_sas_port;
  8585. struct sas_phy *phy;
  8586. struct sas_identify *identify;
  8587. hpsa_sas_port = hpsa_sas_phy->parent_port;
  8588. phy = hpsa_sas_phy->phy;
  8589. identify = &phy->identify;
  8590. memset(identify, 0, sizeof(*identify));
  8591. identify->sas_address = hpsa_sas_port->sas_address;
  8592. identify->device_type = SAS_END_DEVICE;
  8593. identify->initiator_port_protocols = SAS_PROTOCOL_STP;
  8594. identify->target_port_protocols = SAS_PROTOCOL_STP;
  8595. phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
  8596. phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
  8597. phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
  8598. phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
  8599. phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
  8600. rc = sas_phy_add(hpsa_sas_phy->phy);
  8601. if (rc)
  8602. return rc;
  8603. sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
  8604. list_add_tail(&hpsa_sas_phy->phy_list_entry,
  8605. &hpsa_sas_port->phy_list_head);
  8606. hpsa_sas_phy->added_to_port = true;
  8607. return 0;
  8608. }
  8609. static int
  8610. hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
  8611. struct sas_rphy *rphy)
  8612. {
  8613. struct sas_identify *identify;
  8614. identify = &rphy->identify;
  8615. identify->sas_address = hpsa_sas_port->sas_address;
  8616. identify->initiator_port_protocols = SAS_PROTOCOL_STP;
  8617. identify->target_port_protocols = SAS_PROTOCOL_STP;
  8618. return sas_rphy_add(rphy);
  8619. }
  8620. static struct hpsa_sas_port
  8621. *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
  8622. u64 sas_address)
  8623. {
  8624. int rc;
  8625. struct hpsa_sas_port *hpsa_sas_port;
  8626. struct sas_port *port;
  8627. hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL);
  8628. if (!hpsa_sas_port)
  8629. return NULL;
  8630. INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
  8631. hpsa_sas_port->parent_node = hpsa_sas_node;
  8632. port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
  8633. if (!port)
  8634. goto free_hpsa_port;
  8635. rc = sas_port_add(port);
  8636. if (rc)
  8637. goto free_sas_port;
  8638. hpsa_sas_port->port = port;
  8639. hpsa_sas_port->sas_address = sas_address;
  8640. list_add_tail(&hpsa_sas_port->port_list_entry,
  8641. &hpsa_sas_node->port_list_head);
  8642. return hpsa_sas_port;
  8643. free_sas_port:
  8644. sas_port_free(port);
  8645. free_hpsa_port:
  8646. kfree(hpsa_sas_port);
  8647. return NULL;
  8648. }
  8649. static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
  8650. {
  8651. struct hpsa_sas_phy *hpsa_sas_phy;
  8652. struct hpsa_sas_phy *next;
  8653. list_for_each_entry_safe(hpsa_sas_phy, next,
  8654. &hpsa_sas_port->phy_list_head, phy_list_entry)
  8655. hpsa_free_sas_phy(hpsa_sas_phy);
  8656. sas_port_delete(hpsa_sas_port->port);
  8657. list_del(&hpsa_sas_port->port_list_entry);
  8658. kfree(hpsa_sas_port);
  8659. }
  8660. static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
  8661. {
  8662. struct hpsa_sas_node *hpsa_sas_node;
  8663. hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL);
  8664. if (hpsa_sas_node) {
  8665. hpsa_sas_node->parent_dev = parent_dev;
  8666. INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
  8667. }
  8668. return hpsa_sas_node;
  8669. }
  8670. static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
  8671. {
  8672. struct hpsa_sas_port *hpsa_sas_port;
  8673. struct hpsa_sas_port *next;
  8674. if (!hpsa_sas_node)
  8675. return;
  8676. list_for_each_entry_safe(hpsa_sas_port, next,
  8677. &hpsa_sas_node->port_list_head, port_list_entry)
  8678. hpsa_free_sas_port(hpsa_sas_port);
  8679. kfree(hpsa_sas_node);
  8680. }
  8681. static struct hpsa_scsi_dev_t
  8682. *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
  8683. struct sas_rphy *rphy)
  8684. {
  8685. int i;
  8686. struct hpsa_scsi_dev_t *device;
  8687. for (i = 0; i < h->ndevices; i++) {
  8688. device = h->dev[i];
  8689. if (!device->sas_port)
  8690. continue;
  8691. if (device->sas_port->rphy == rphy)
  8692. return device;
  8693. }
  8694. return NULL;
  8695. }
  8696. static int hpsa_add_sas_host(struct ctlr_info *h)
  8697. {
  8698. int rc;
  8699. struct device *parent_dev;
  8700. struct hpsa_sas_node *hpsa_sas_node;
  8701. struct hpsa_sas_port *hpsa_sas_port;
  8702. struct hpsa_sas_phy *hpsa_sas_phy;
  8703. parent_dev = &h->scsi_host->shost_gendev;
  8704. hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
  8705. if (!hpsa_sas_node)
  8706. return -ENOMEM;
  8707. hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
  8708. if (!hpsa_sas_port) {
  8709. rc = -ENODEV;
  8710. goto free_sas_node;
  8711. }
  8712. hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
  8713. if (!hpsa_sas_phy) {
  8714. rc = -ENODEV;
  8715. goto free_sas_port;
  8716. }
  8717. rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
  8718. if (rc)
  8719. goto free_sas_phy;
  8720. h->sas_host = hpsa_sas_node;
  8721. return 0;
  8722. free_sas_phy:
  8723. hpsa_free_sas_phy(hpsa_sas_phy);
  8724. free_sas_port:
  8725. hpsa_free_sas_port(hpsa_sas_port);
  8726. free_sas_node:
  8727. hpsa_free_sas_node(hpsa_sas_node);
  8728. return rc;
  8729. }
  8730. static void hpsa_delete_sas_host(struct ctlr_info *h)
  8731. {
  8732. hpsa_free_sas_node(h->sas_host);
  8733. }
  8734. static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
  8735. struct hpsa_scsi_dev_t *device)
  8736. {
  8737. int rc;
  8738. struct hpsa_sas_port *hpsa_sas_port;
  8739. struct sas_rphy *rphy;
  8740. hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
  8741. if (!hpsa_sas_port)
  8742. return -ENOMEM;
  8743. rphy = sas_end_device_alloc(hpsa_sas_port->port);
  8744. if (!rphy) {
  8745. rc = -ENODEV;
  8746. goto free_sas_port;
  8747. }
  8748. hpsa_sas_port->rphy = rphy;
  8749. device->sas_port = hpsa_sas_port;
  8750. rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
  8751. if (rc)
  8752. goto free_sas_port;
  8753. return 0;
  8754. free_sas_port:
  8755. hpsa_free_sas_port(hpsa_sas_port);
  8756. device->sas_port = NULL;
  8757. return rc;
  8758. }
  8759. static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
  8760. {
  8761. if (device->sas_port) {
  8762. hpsa_free_sas_port(device->sas_port);
  8763. device->sas_port = NULL;
  8764. }
  8765. }
  8766. static int
  8767. hpsa_sas_get_linkerrors(struct sas_phy *phy)
  8768. {
  8769. return 0;
  8770. }
  8771. static int
  8772. hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
  8773. {
  8774. *identifier = 0;
  8775. return 0;
  8776. }
  8777. static int
  8778. hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
  8779. {
  8780. return -ENXIO;
  8781. }
  8782. static int
  8783. hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
  8784. {
  8785. return 0;
  8786. }
  8787. static int
  8788. hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
  8789. {
  8790. return 0;
  8791. }
  8792. static int
  8793. hpsa_sas_phy_setup(struct sas_phy *phy)
  8794. {
  8795. return 0;
  8796. }
  8797. static void
  8798. hpsa_sas_phy_release(struct sas_phy *phy)
  8799. {
  8800. }
  8801. static int
  8802. hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
  8803. {
  8804. return -EINVAL;
  8805. }
  8806. /* SMP = Serial Management Protocol */
  8807. static int
  8808. hpsa_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
  8809. struct request *req)
  8810. {
  8811. return -EINVAL;
  8812. }
  8813. static struct sas_function_template hpsa_sas_transport_functions = {
  8814. .get_linkerrors = hpsa_sas_get_linkerrors,
  8815. .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
  8816. .get_bay_identifier = hpsa_sas_get_bay_identifier,
  8817. .phy_reset = hpsa_sas_phy_reset,
  8818. .phy_enable = hpsa_sas_phy_enable,
  8819. .phy_setup = hpsa_sas_phy_setup,
  8820. .phy_release = hpsa_sas_phy_release,
  8821. .set_phy_speed = hpsa_sas_phy_speed,
  8822. .smp_handler = hpsa_sas_smp_handler,
  8823. };
  8824. /*
  8825. * This is it. Register the PCI driver information for the cards we control
  8826. * the OS will call our registered routines when it finds one of our cards.
  8827. */
  8828. static int __init hpsa_init(void)
  8829. {
  8830. int rc;
  8831. hpsa_sas_transport_template =
  8832. sas_attach_transport(&hpsa_sas_transport_functions);
  8833. if (!hpsa_sas_transport_template)
  8834. return -ENODEV;
  8835. rc = pci_register_driver(&hpsa_pci_driver);
  8836. if (rc)
  8837. sas_release_transport(hpsa_sas_transport_template);
  8838. return rc;
  8839. }
  8840. static void __exit hpsa_cleanup(void)
  8841. {
  8842. pci_unregister_driver(&hpsa_pci_driver);
  8843. sas_release_transport(hpsa_sas_transport_template);
  8844. }
  8845. static void __attribute__((unused)) verify_offsets(void)
  8846. {
  8847. #define VERIFY_OFFSET(member, offset) \
  8848. BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
  8849. VERIFY_OFFSET(structure_size, 0);
  8850. VERIFY_OFFSET(volume_blk_size, 4);
  8851. VERIFY_OFFSET(volume_blk_cnt, 8);
  8852. VERIFY_OFFSET(phys_blk_shift, 16);
  8853. VERIFY_OFFSET(parity_rotation_shift, 17);
  8854. VERIFY_OFFSET(strip_size, 18);
  8855. VERIFY_OFFSET(disk_starting_blk, 20);
  8856. VERIFY_OFFSET(disk_blk_cnt, 28);
  8857. VERIFY_OFFSET(data_disks_per_row, 36);
  8858. VERIFY_OFFSET(metadata_disks_per_row, 38);
  8859. VERIFY_OFFSET(row_cnt, 40);
  8860. VERIFY_OFFSET(layout_map_count, 42);
  8861. VERIFY_OFFSET(flags, 44);
  8862. VERIFY_OFFSET(dekindex, 46);
  8863. /* VERIFY_OFFSET(reserved, 48 */
  8864. VERIFY_OFFSET(data, 64);
  8865. #undef VERIFY_OFFSET
  8866. #define VERIFY_OFFSET(member, offset) \
  8867. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
  8868. VERIFY_OFFSET(IU_type, 0);
  8869. VERIFY_OFFSET(direction, 1);
  8870. VERIFY_OFFSET(reply_queue, 2);
  8871. /* VERIFY_OFFSET(reserved1, 3); */
  8872. VERIFY_OFFSET(scsi_nexus, 4);
  8873. VERIFY_OFFSET(Tag, 8);
  8874. VERIFY_OFFSET(cdb, 16);
  8875. VERIFY_OFFSET(cciss_lun, 32);
  8876. VERIFY_OFFSET(data_len, 40);
  8877. VERIFY_OFFSET(cmd_priority_task_attr, 44);
  8878. VERIFY_OFFSET(sg_count, 45);
  8879. /* VERIFY_OFFSET(reserved3 */
  8880. VERIFY_OFFSET(err_ptr, 48);
  8881. VERIFY_OFFSET(err_len, 56);
  8882. /* VERIFY_OFFSET(reserved4 */
  8883. VERIFY_OFFSET(sg, 64);
  8884. #undef VERIFY_OFFSET
  8885. #define VERIFY_OFFSET(member, offset) \
  8886. BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
  8887. VERIFY_OFFSET(dev_handle, 0x00);
  8888. VERIFY_OFFSET(reserved1, 0x02);
  8889. VERIFY_OFFSET(function, 0x03);
  8890. VERIFY_OFFSET(reserved2, 0x04);
  8891. VERIFY_OFFSET(err_info, 0x0C);
  8892. VERIFY_OFFSET(reserved3, 0x10);
  8893. VERIFY_OFFSET(err_info_len, 0x12);
  8894. VERIFY_OFFSET(reserved4, 0x13);
  8895. VERIFY_OFFSET(sgl_offset, 0x14);
  8896. VERIFY_OFFSET(reserved5, 0x15);
  8897. VERIFY_OFFSET(transfer_len, 0x1C);
  8898. VERIFY_OFFSET(reserved6, 0x20);
  8899. VERIFY_OFFSET(io_flags, 0x24);
  8900. VERIFY_OFFSET(reserved7, 0x26);
  8901. VERIFY_OFFSET(LUN, 0x34);
  8902. VERIFY_OFFSET(control, 0x3C);
  8903. VERIFY_OFFSET(CDB, 0x40);
  8904. VERIFY_OFFSET(reserved8, 0x50);
  8905. VERIFY_OFFSET(host_context_flags, 0x60);
  8906. VERIFY_OFFSET(timeout_sec, 0x62);
  8907. VERIFY_OFFSET(ReplyQueue, 0x64);
  8908. VERIFY_OFFSET(reserved9, 0x65);
  8909. VERIFY_OFFSET(tag, 0x68);
  8910. VERIFY_OFFSET(host_addr, 0x70);
  8911. VERIFY_OFFSET(CISS_LUN, 0x78);
  8912. VERIFY_OFFSET(SG, 0x78 + 8);
  8913. #undef VERIFY_OFFSET
  8914. }
  8915. module_init(hpsa_init);
  8916. module_exit(hpsa_cleanup);