pcie-artpec6.c 7.8 KB

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  1. /*
  2. * PCIe host controller driver for Axis ARTPEC-6 SoC
  3. *
  4. * Author: Niklas Cassel <niklas.cassel@axis.com>
  5. *
  6. * Based on work done by Phil Edworthy <phil@edworthys.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/resource.h>
  18. #include <linux/signal.h>
  19. #include <linux/types.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/mfd/syscon.h>
  22. #include <linux/regmap.h>
  23. #include "pcie-designware.h"
  24. #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
  25. struct artpec6_pcie {
  26. struct dw_pcie *pci;
  27. struct regmap *regmap; /* DT axis,syscon-pcie */
  28. void __iomem *phy_base; /* DT phy */
  29. };
  30. /* PCIe Port Logic registers (memory-mapped) */
  31. #define PL_OFFSET 0x700
  32. #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  33. #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  34. #define MISC_CONTROL_1_OFF (PL_OFFSET + 0x1bc)
  35. #define DBI_RO_WR_EN 1
  36. /* ARTPEC-6 specific registers */
  37. #define PCIECFG 0x18
  38. #define PCIECFG_DBG_OEN (1 << 24)
  39. #define PCIECFG_CORE_RESET_REQ (1 << 21)
  40. #define PCIECFG_LTSSM_ENABLE (1 << 20)
  41. #define PCIECFG_CLKREQ_B (1 << 11)
  42. #define PCIECFG_REFCLK_ENABLE (1 << 10)
  43. #define PCIECFG_PLL_ENABLE (1 << 9)
  44. #define PCIECFG_PCLK_ENABLE (1 << 8)
  45. #define PCIECFG_RISRCREN (1 << 4)
  46. #define PCIECFG_MODE_TX_DRV_EN (1 << 3)
  47. #define PCIECFG_CISRREN (1 << 2)
  48. #define PCIECFG_MACRO_ENABLE (1 << 0)
  49. #define NOCCFG 0x40
  50. #define NOCCFG_ENABLE_CLK_PCIE (1 << 4)
  51. #define NOCCFG_POWER_PCIE_IDLEACK (1 << 3)
  52. #define NOCCFG_POWER_PCIE_IDLE (1 << 2)
  53. #define NOCCFG_POWER_PCIE_IDLEREQ (1 << 1)
  54. #define PHY_STATUS 0x118
  55. #define PHY_COSPLLLOCK (1 << 0)
  56. #define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff
  57. static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
  58. {
  59. u32 val;
  60. regmap_read(artpec6_pcie->regmap, offset, &val);
  61. return val;
  62. }
  63. static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
  64. {
  65. regmap_write(artpec6_pcie->regmap, offset, val);
  66. }
  67. static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
  68. {
  69. struct dw_pcie *pci = artpec6_pcie->pci;
  70. struct pcie_port *pp = &pci->pp;
  71. u32 val;
  72. unsigned int retries;
  73. /* Hold DW core in reset */
  74. val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  75. val |= PCIECFG_CORE_RESET_REQ;
  76. artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
  77. val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  78. val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
  79. PCIECFG_MODE_TX_DRV_EN |
  80. PCIECFG_CISRREN | /* Reference clock term. 100 Ohm */
  81. PCIECFG_MACRO_ENABLE;
  82. val |= PCIECFG_REFCLK_ENABLE;
  83. val &= ~PCIECFG_DBG_OEN;
  84. val &= ~PCIECFG_CLKREQ_B;
  85. artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
  86. usleep_range(5000, 6000);
  87. val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
  88. val |= NOCCFG_ENABLE_CLK_PCIE;
  89. artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
  90. usleep_range(20, 30);
  91. val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  92. val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
  93. artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
  94. usleep_range(6000, 7000);
  95. val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
  96. val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
  97. artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
  98. retries = 50;
  99. do {
  100. usleep_range(1000, 2000);
  101. val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
  102. retries--;
  103. } while (retries &&
  104. (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
  105. retries = 50;
  106. do {
  107. usleep_range(1000, 2000);
  108. val = readl(artpec6_pcie->phy_base + PHY_STATUS);
  109. retries--;
  110. } while (retries && !(val & PHY_COSPLLLOCK));
  111. /* Take DW core out of reset */
  112. val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  113. val &= ~PCIECFG_CORE_RESET_REQ;
  114. artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
  115. usleep_range(100, 200);
  116. /*
  117. * Enable writing to config regs. This is required as the Synopsys
  118. * driver changes the class code. That register needs DBI write enable.
  119. */
  120. dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
  121. pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
  122. pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
  123. pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR;
  124. pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR;
  125. /* setup root complex */
  126. dw_pcie_setup_rc(pp);
  127. /* assert LTSSM enable */
  128. val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  129. val |= PCIECFG_LTSSM_ENABLE;
  130. artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
  131. /* check if the link is up or not */
  132. if (!dw_pcie_wait_for_link(pci))
  133. return 0;
  134. dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
  135. dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
  136. dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
  137. return -ETIMEDOUT;
  138. }
  139. static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
  140. {
  141. struct dw_pcie *pci = artpec6_pcie->pci;
  142. struct pcie_port *pp = &pci->pp;
  143. if (IS_ENABLED(CONFIG_PCI_MSI))
  144. dw_pcie_msi_init(pp);
  145. }
  146. static void artpec6_pcie_host_init(struct pcie_port *pp)
  147. {
  148. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  149. struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
  150. artpec6_pcie_establish_link(artpec6_pcie);
  151. artpec6_pcie_enable_interrupts(artpec6_pcie);
  152. }
  153. static struct dw_pcie_host_ops artpec6_pcie_host_ops = {
  154. .host_init = artpec6_pcie_host_init,
  155. };
  156. static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
  157. {
  158. struct artpec6_pcie *artpec6_pcie = arg;
  159. struct dw_pcie *pci = artpec6_pcie->pci;
  160. struct pcie_port *pp = &pci->pp;
  161. return dw_handle_msi_irq(pp);
  162. }
  163. static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
  164. struct platform_device *pdev)
  165. {
  166. struct dw_pcie *pci = artpec6_pcie->pci;
  167. struct pcie_port *pp = &pci->pp;
  168. struct device *dev = pci->dev;
  169. int ret;
  170. if (IS_ENABLED(CONFIG_PCI_MSI)) {
  171. pp->msi_irq = platform_get_irq_byname(pdev, "msi");
  172. if (pp->msi_irq <= 0) {
  173. dev_err(dev, "failed to get MSI irq\n");
  174. return -ENODEV;
  175. }
  176. ret = devm_request_irq(dev, pp->msi_irq,
  177. artpec6_pcie_msi_handler,
  178. IRQF_SHARED | IRQF_NO_THREAD,
  179. "artpec6-pcie-msi", artpec6_pcie);
  180. if (ret) {
  181. dev_err(dev, "failed to request MSI irq\n");
  182. return ret;
  183. }
  184. }
  185. pp->root_bus_nr = -1;
  186. pp->ops = &artpec6_pcie_host_ops;
  187. ret = dw_pcie_host_init(pp);
  188. if (ret) {
  189. dev_err(dev, "failed to initialize host\n");
  190. return ret;
  191. }
  192. return 0;
  193. }
  194. static int artpec6_pcie_probe(struct platform_device *pdev)
  195. {
  196. struct device *dev = &pdev->dev;
  197. struct dw_pcie *pci;
  198. struct artpec6_pcie *artpec6_pcie;
  199. struct resource *dbi_base;
  200. struct resource *phy_base;
  201. int ret;
  202. artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
  203. if (!artpec6_pcie)
  204. return -ENOMEM;
  205. pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
  206. if (!pci)
  207. return -ENOMEM;
  208. pci->dev = dev;
  209. artpec6_pcie->pci = pci;
  210. dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
  211. pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
  212. if (IS_ERR(pci->dbi_base))
  213. return PTR_ERR(pci->dbi_base);
  214. phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
  215. artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
  216. if (IS_ERR(artpec6_pcie->phy_base))
  217. return PTR_ERR(artpec6_pcie->phy_base);
  218. artpec6_pcie->regmap =
  219. syscon_regmap_lookup_by_phandle(dev->of_node,
  220. "axis,syscon-pcie");
  221. if (IS_ERR(artpec6_pcie->regmap))
  222. return PTR_ERR(artpec6_pcie->regmap);
  223. platform_set_drvdata(pdev, artpec6_pcie);
  224. ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
  225. if (ret < 0)
  226. return ret;
  227. return 0;
  228. }
  229. static const struct of_device_id artpec6_pcie_of_match[] = {
  230. { .compatible = "axis,artpec6-pcie", },
  231. {},
  232. };
  233. static struct platform_driver artpec6_pcie_driver = {
  234. .probe = artpec6_pcie_probe,
  235. .driver = {
  236. .name = "artpec6-pcie",
  237. .of_match_table = artpec6_pcie_of_match,
  238. },
  239. };
  240. builtin_platform_driver(artpec6_pcie_driver);