pci-keystone.h 3.0 KB

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  1. /*
  2. * Keystone PCI Controller's common includes
  3. *
  4. * Copyright (C) 2013-2014 Texas Instruments., Ltd.
  5. * http://www.ti.com
  6. *
  7. * Author: Murali Karicheri <m-karicheri2@ti.com>
  8. *
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #define MAX_LEGACY_IRQS 4
  15. #define MAX_MSI_HOST_IRQS 8
  16. #define MAX_LEGACY_HOST_IRQS 4
  17. #define OUTBOUND_WINDOWS 32
  18. struct keystone_outbound_win {
  19. u64 cpu_addr;
  20. u8 no_of_regions;
  21. };
  22. struct keystone_pcie {
  23. struct dw_pcie *pci;
  24. struct clk *clk;
  25. /* PCI Device ID */
  26. u32 device_id;
  27. int num_legacy_host_irqs;
  28. int legacy_host_irqs[MAX_LEGACY_HOST_IRQS];
  29. struct device_node *legacy_intc_np;
  30. int num_msi_host_irqs;
  31. int msi_host_irqs[MAX_MSI_HOST_IRQS];
  32. struct device_node *msi_intc_np;
  33. struct irq_domain *legacy_irq_domain;
  34. struct device_node *np;
  35. int error_irq;
  36. /* Application register space */
  37. void __iomem *va_app_base; /* DT 1st resource */
  38. struct resource app;
  39. unsigned long ob_window_map;
  40. struct keystone_outbound_win ob_win[OUTBOUND_WINDOWS];
  41. };
  42. u32 ks_dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base,
  43. u32 reg, size_t size);
  44. void ks_dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base,
  45. u32 reg, size_t size, u32 val);
  46. int ks_dw_pcie_inbound_atu(struct dw_pcie *pci, u32 index,
  47. enum pci_barno bar, dma_addr_t cpu_addr);
  48. int ks_dw_pcie_outbound_atu(struct dw_pcie *pci, u64 cpu_addr, u64 pci_addr,
  49. size_t size);
  50. void ks_dw_pcie_disable_atu(struct dw_pcie *pci, phys_addr_t addr, int index,
  51. enum dw_pcie_region_type type);
  52. void ks_dw_pcie_ep_init(struct dw_pcie_ep *ep);
  53. void ks_dw_pcie_raise_legacy_irq(struct keystone_pcie *ks_pcie);
  54. /* Keystone DW specific MSI controller APIs/definitions */
  55. void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
  56. phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
  57. /* Keystone specific PCI controller APIs */
  58. void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
  59. void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
  60. void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie);
  61. irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie);
  62. int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
  63. struct device_node *msi_intc_np);
  64. int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
  65. unsigned int devfn, int where, int size, u32 val);
  66. int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
  67. unsigned int devfn, int where, int size, u32 *val);
  68. void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
  69. void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
  70. void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
  71. void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
  72. void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
  73. int ks_dw_pcie_msi_host_init(struct pcie_port *pp,
  74. struct msi_controller *chip);
  75. int ks_dw_pcie_link_up(struct dw_pcie *pci);