Kconfig 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179
  1. menu "DesignWare PCI Core Support"
  2. config PCIE_DW
  3. bool
  4. config PCIE_DW_HOST
  5. bool
  6. depends on PCI
  7. depends on PCI_MSI_IRQ_DOMAIN
  8. select PCIE_DW
  9. config PCIE_DW_EP
  10. bool
  11. depends on PCI_ENDPOINT
  12. select PCIE_DW
  13. config PCI_DRA7XX
  14. bool "TI DRA7xx PCIe controller"
  15. depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT
  16. depends on OF && HAS_IOMEM && TI_PIPE3
  17. help
  18. Enables support for the PCIe controller in the DRA7xx SoC. There
  19. are two instances of PCIe controller in DRA7xx. This controller can
  20. work either as EP or RC. In order to enable host specific features
  21. PCI_DRA7XX_HOST must be selected and in order to enable device
  22. specific features PCI_DRA7XX_EP must be selected. This uses
  23. the Designware core.
  24. if PCI_DRA7XX
  25. config PCI_DRA7XX_HOST
  26. bool "PCI DRA7xx Host Mode"
  27. depends on PCI
  28. depends on PCI_MSI_IRQ_DOMAIN
  29. select PCIE_DW_HOST
  30. default y
  31. help
  32. Enables support for the PCIe controller in the DRA7xx SoC to work in
  33. host mode.
  34. config PCI_DRA7XX_EP
  35. bool "PCI DRA7xx Endpoint Mode"
  36. depends on PCI_ENDPOINT
  37. select PCIE_DW_EP
  38. help
  39. Enables support for the PCIe controller in the DRA7xx SoC to work in
  40. endpoint mode.
  41. endif
  42. config PCIE_DW_PLAT
  43. bool "Platform bus based DesignWare PCIe Controller"
  44. depends on PCI
  45. depends on PCI_MSI_IRQ_DOMAIN
  46. select PCIE_DW_HOST
  47. ---help---
  48. This selects the DesignWare PCIe controller support. Select this if
  49. you have a PCIe controller on Platform bus.
  50. If you have a controller with this interface, say Y or M here.
  51. If unsure, say N.
  52. config PCI_EXYNOS
  53. bool "Samsung Exynos PCIe controller"
  54. depends on PCI
  55. depends on SOC_EXYNOS5440 || COMPILE_TEST
  56. depends on PCI_MSI_IRQ_DOMAIN
  57. select PCIEPORTBUS
  58. select PCIE_DW_HOST
  59. config PCI_IMX6
  60. bool "Freescale i.MX6 PCIe controller"
  61. depends on PCI
  62. depends on SOC_IMX6Q || COMPILE_TEST
  63. depends on PCI_MSI_IRQ_DOMAIN
  64. select PCIEPORTBUS
  65. select PCIE_DW_HOST
  66. config PCIE_SPEAR13XX
  67. bool "STMicroelectronics SPEAr PCIe controller"
  68. depends on PCI
  69. depends on ARCH_SPEAR13XX || COMPILE_TEST
  70. depends on PCI_MSI_IRQ_DOMAIN
  71. select PCIEPORTBUS
  72. select PCIE_DW_HOST
  73. help
  74. Say Y here if you want PCIe support on SPEAr13XX SoCs.
  75. config PCI_KEYSTONE
  76. bool "TI Keystone PCIe controller"
  77. depends on ARCH_KEYSTONE || COMPILE_TEST
  78. help
  79. Say Y here if you want to enable PCI controller support on Keystone
  80. SoCs. The PCI controller on Keystone is based on Designware hardware
  81. and therefore the driver re-uses the Designware core functions to
  82. implement the driver.
  83. if PCI_KEYSTONE
  84. config PCI_KEYSTONE_HOST
  85. bool "PCI Keystone Host Mode"
  86. depends on PCI
  87. depends on PCI_MSI_IRQ_DOMAIN
  88. select PCIEPORTBUS
  89. select PCIE_DW_HOST
  90. default y
  91. help
  92. Enables support for the PCIe controller in the Keystone SoC to work in
  93. host mode.
  94. config PCI_KEYSTONE_EP
  95. bool "PCI Keystone Endpoint Mode"
  96. depends on PCI_ENDPOINT
  97. select PCIE_DW_EP
  98. help
  99. Enables support for the PCIe controller in the Keystone SoC to work in
  100. endpoint mode.
  101. endif
  102. config PCI_LAYERSCAPE
  103. bool "Freescale Layerscape PCIe controller"
  104. depends on PCI
  105. depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
  106. depends on PCI_MSI_IRQ_DOMAIN
  107. select MFD_SYSCON
  108. select PCIE_DW_HOST
  109. help
  110. Say Y here if you want PCIe controller support on Layerscape SoCs.
  111. config PCI_HISI
  112. depends on OF && (ARM64 || COMPILE_TEST)
  113. bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
  114. depends on PCI
  115. depends on PCI_MSI_IRQ_DOMAIN
  116. select PCIEPORTBUS
  117. select PCIE_DW_HOST
  118. help
  119. Say Y here if you want PCIe controller support on HiSilicon
  120. Hip05 and Hip06 SoCs
  121. config PCIE_QCOM
  122. bool "Qualcomm PCIe controller"
  123. depends on PCI
  124. depends on (ARCH_QCOM || COMPILE_TEST) && OF
  125. depends on PCI_MSI_IRQ_DOMAIN
  126. select PCIEPORTBUS
  127. select PCIE_DW_HOST
  128. help
  129. Say Y here to enable PCIe controller support on Qualcomm SoCs. The
  130. PCIe controller uses the Designware core plus Qualcomm-specific
  131. hardware wrappers.
  132. config PCIE_ARMADA_8K
  133. bool "Marvell Armada-8K PCIe controller"
  134. depends on PCI
  135. depends on ARCH_MVEBU || COMPILE_TEST
  136. depends on PCI_MSI_IRQ_DOMAIN
  137. select PCIEPORTBUS
  138. select PCIE_DW_HOST
  139. help
  140. Say Y here if you want to enable PCIe controller support on
  141. Armada-8K SoCs. The PCIe controller on Armada-8K is based on
  142. Designware hardware and therefore the driver re-uses the
  143. Designware core functions to implement the driver.
  144. config PCIE_ARTPEC6
  145. bool "Axis ARTPEC-6 PCIe controller"
  146. depends on PCI
  147. depends on MACH_ARTPEC6 || COMPILE_TEST
  148. depends on PCI_MSI_IRQ_DOMAIN
  149. select PCIEPORTBUS
  150. select PCIE_DW_HOST
  151. help
  152. Say Y here to enable PCIe controller support on Axis ARTPEC-6
  153. SoCs. This PCIe controller uses the DesignWare core.
  154. endmenu