smsc75xx.c 56 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2010 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. *****************************************************************************/
  19. #include <linux/module.h>
  20. #include <linux/kmod.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/etherdevice.h>
  23. #include <linux/ethtool.h>
  24. #include <linux/mii.h>
  25. #include <linux/usb.h>
  26. #include <linux/bitrev.h>
  27. #include <linux/crc16.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include <linux/of_net.h>
  32. #include "smsc75xx.h"
  33. #define SMSC_CHIPNAME "smsc75xx"
  34. #define SMSC_DRIVER_VERSION "1.0.0"
  35. #define HS_USB_PKT_SIZE (512)
  36. #define FS_USB_PKT_SIZE (64)
  37. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  38. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  39. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  40. #define MAX_SINGLE_PACKET_SIZE (9000)
  41. #define LAN75XX_EEPROM_MAGIC (0x7500)
  42. #define EEPROM_MAC_OFFSET (0x01)
  43. #define DEFAULT_TX_CSUM_ENABLE (true)
  44. #define DEFAULT_RX_CSUM_ENABLE (true)
  45. #define SMSC75XX_INTERNAL_PHY_ID (1)
  46. #define SMSC75XX_TX_OVERHEAD (8)
  47. #define MAX_RX_FIFO_SIZE (20 * 1024)
  48. #define MAX_TX_FIFO_SIZE (12 * 1024)
  49. #define USB_VENDOR_ID_SMSC (0x0424)
  50. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  51. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  52. #define RXW_PADDING 2
  53. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  54. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  55. #define SUSPEND_SUSPEND0 (0x01)
  56. #define SUSPEND_SUSPEND1 (0x02)
  57. #define SUSPEND_SUSPEND2 (0x04)
  58. #define SUSPEND_SUSPEND3 (0x08)
  59. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  60. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  61. struct smsc75xx_priv {
  62. struct usbnet *dev;
  63. u32 rfe_ctl;
  64. u32 wolopts;
  65. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  66. struct mutex dataport_mutex;
  67. spinlock_t rfe_ctl_lock;
  68. struct work_struct set_multicast;
  69. u8 suspend_flags;
  70. };
  71. struct usb_context {
  72. struct usb_ctrlrequest req;
  73. struct usbnet *dev;
  74. };
  75. static bool turbo_mode = true;
  76. module_param(turbo_mode, bool, 0644);
  77. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  78. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  79. u32 *data, int in_pm)
  80. {
  81. u32 buf;
  82. int ret;
  83. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  84. BUG_ON(!dev);
  85. if (!in_pm)
  86. fn = usbnet_read_cmd;
  87. else
  88. fn = usbnet_read_cmd_nopm;
  89. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  90. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  91. 0, index, &buf, 4);
  92. if (unlikely(ret < 0)) {
  93. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  94. index, ret);
  95. return ret;
  96. }
  97. le32_to_cpus(&buf);
  98. *data = buf;
  99. return ret;
  100. }
  101. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  102. u32 data, int in_pm)
  103. {
  104. u32 buf;
  105. int ret;
  106. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  107. BUG_ON(!dev);
  108. if (!in_pm)
  109. fn = usbnet_write_cmd;
  110. else
  111. fn = usbnet_write_cmd_nopm;
  112. buf = data;
  113. cpu_to_le32s(&buf);
  114. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  115. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  116. 0, index, &buf, 4);
  117. if (unlikely(ret < 0))
  118. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  119. index, ret);
  120. return ret;
  121. }
  122. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  123. u32 *data)
  124. {
  125. return __smsc75xx_read_reg(dev, index, data, 1);
  126. }
  127. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  128. u32 data)
  129. {
  130. return __smsc75xx_write_reg(dev, index, data, 1);
  131. }
  132. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  133. u32 *data)
  134. {
  135. return __smsc75xx_read_reg(dev, index, data, 0);
  136. }
  137. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  138. u32 data)
  139. {
  140. return __smsc75xx_write_reg(dev, index, data, 0);
  141. }
  142. /* Loop until the read is completed with timeout
  143. * called with phy_mutex held */
  144. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  145. int in_pm)
  146. {
  147. unsigned long start_time = jiffies;
  148. u32 val;
  149. int ret;
  150. do {
  151. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  152. if (ret < 0) {
  153. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  154. return ret;
  155. }
  156. if (!(val & MII_ACCESS_BUSY))
  157. return 0;
  158. } while (!time_after(jiffies, start_time + HZ));
  159. return -EIO;
  160. }
  161. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  162. int in_pm)
  163. {
  164. struct usbnet *dev = netdev_priv(netdev);
  165. u32 val, addr;
  166. int ret;
  167. mutex_lock(&dev->phy_mutex);
  168. /* confirm MII not busy */
  169. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  170. if (ret < 0) {
  171. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  172. goto done;
  173. }
  174. /* set the address, index & direction (read from PHY) */
  175. phy_id &= dev->mii.phy_id_mask;
  176. idx &= dev->mii.reg_num_mask;
  177. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  178. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  179. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  180. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  181. if (ret < 0) {
  182. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  183. goto done;
  184. }
  185. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  186. if (ret < 0) {
  187. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  188. goto done;
  189. }
  190. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  191. if (ret < 0) {
  192. netdev_warn(dev->net, "Error reading MII_DATA\n");
  193. goto done;
  194. }
  195. ret = (u16)(val & 0xFFFF);
  196. done:
  197. mutex_unlock(&dev->phy_mutex);
  198. return ret;
  199. }
  200. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  201. int idx, int regval, int in_pm)
  202. {
  203. struct usbnet *dev = netdev_priv(netdev);
  204. u32 val, addr;
  205. int ret;
  206. mutex_lock(&dev->phy_mutex);
  207. /* confirm MII not busy */
  208. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  209. if (ret < 0) {
  210. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  211. goto done;
  212. }
  213. val = regval;
  214. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  215. if (ret < 0) {
  216. netdev_warn(dev->net, "Error writing MII_DATA\n");
  217. goto done;
  218. }
  219. /* set the address, index & direction (write to PHY) */
  220. phy_id &= dev->mii.phy_id_mask;
  221. idx &= dev->mii.reg_num_mask;
  222. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  223. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  224. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  225. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  226. if (ret < 0) {
  227. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  228. goto done;
  229. }
  230. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  231. if (ret < 0) {
  232. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  233. goto done;
  234. }
  235. done:
  236. mutex_unlock(&dev->phy_mutex);
  237. }
  238. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  239. int idx)
  240. {
  241. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  242. }
  243. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  244. int idx, int regval)
  245. {
  246. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  247. }
  248. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  249. {
  250. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  251. }
  252. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  253. int regval)
  254. {
  255. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  256. }
  257. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  258. {
  259. unsigned long start_time = jiffies;
  260. u32 val;
  261. int ret;
  262. do {
  263. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  264. if (ret < 0) {
  265. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  266. return ret;
  267. }
  268. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  269. break;
  270. udelay(40);
  271. } while (!time_after(jiffies, start_time + HZ));
  272. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  273. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  274. return -EIO;
  275. }
  276. return 0;
  277. }
  278. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  279. {
  280. unsigned long start_time = jiffies;
  281. u32 val;
  282. int ret;
  283. do {
  284. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  285. if (ret < 0) {
  286. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  287. return ret;
  288. }
  289. if (!(val & E2P_CMD_BUSY))
  290. return 0;
  291. udelay(40);
  292. } while (!time_after(jiffies, start_time + HZ));
  293. netdev_warn(dev->net, "EEPROM is busy\n");
  294. return -EIO;
  295. }
  296. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  297. u8 *data)
  298. {
  299. u32 val;
  300. int i, ret;
  301. BUG_ON(!dev);
  302. BUG_ON(!data);
  303. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  304. if (ret)
  305. return ret;
  306. for (i = 0; i < length; i++) {
  307. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  308. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  309. if (ret < 0) {
  310. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  311. return ret;
  312. }
  313. ret = smsc75xx_wait_eeprom(dev);
  314. if (ret < 0)
  315. return ret;
  316. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  317. if (ret < 0) {
  318. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  319. return ret;
  320. }
  321. data[i] = val & 0xFF;
  322. offset++;
  323. }
  324. return 0;
  325. }
  326. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  327. u8 *data)
  328. {
  329. u32 val;
  330. int i, ret;
  331. BUG_ON(!dev);
  332. BUG_ON(!data);
  333. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  334. if (ret)
  335. return ret;
  336. /* Issue write/erase enable command */
  337. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  338. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  339. if (ret < 0) {
  340. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  341. return ret;
  342. }
  343. ret = smsc75xx_wait_eeprom(dev);
  344. if (ret < 0)
  345. return ret;
  346. for (i = 0; i < length; i++) {
  347. /* Fill data register */
  348. val = data[i];
  349. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  350. if (ret < 0) {
  351. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  352. return ret;
  353. }
  354. /* Send "write" command */
  355. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  356. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  357. if (ret < 0) {
  358. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  359. return ret;
  360. }
  361. ret = smsc75xx_wait_eeprom(dev);
  362. if (ret < 0)
  363. return ret;
  364. offset++;
  365. }
  366. return 0;
  367. }
  368. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  369. {
  370. int i, ret;
  371. for (i = 0; i < 100; i++) {
  372. u32 dp_sel;
  373. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  374. if (ret < 0) {
  375. netdev_warn(dev->net, "Error reading DP_SEL\n");
  376. return ret;
  377. }
  378. if (dp_sel & DP_SEL_DPRDY)
  379. return 0;
  380. udelay(40);
  381. }
  382. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  383. return -EIO;
  384. }
  385. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  386. u32 length, u32 *buf)
  387. {
  388. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  389. u32 dp_sel;
  390. int i, ret;
  391. mutex_lock(&pdata->dataport_mutex);
  392. ret = smsc75xx_dataport_wait_not_busy(dev);
  393. if (ret < 0) {
  394. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  395. goto done;
  396. }
  397. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  398. if (ret < 0) {
  399. netdev_warn(dev->net, "Error reading DP_SEL\n");
  400. goto done;
  401. }
  402. dp_sel &= ~DP_SEL_RSEL;
  403. dp_sel |= ram_select;
  404. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  405. if (ret < 0) {
  406. netdev_warn(dev->net, "Error writing DP_SEL\n");
  407. goto done;
  408. }
  409. for (i = 0; i < length; i++) {
  410. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  411. if (ret < 0) {
  412. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  413. goto done;
  414. }
  415. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  416. if (ret < 0) {
  417. netdev_warn(dev->net, "Error writing DP_DATA\n");
  418. goto done;
  419. }
  420. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  421. if (ret < 0) {
  422. netdev_warn(dev->net, "Error writing DP_CMD\n");
  423. goto done;
  424. }
  425. ret = smsc75xx_dataport_wait_not_busy(dev);
  426. if (ret < 0) {
  427. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  428. goto done;
  429. }
  430. }
  431. done:
  432. mutex_unlock(&pdata->dataport_mutex);
  433. return ret;
  434. }
  435. /* returns hash bit number for given MAC address */
  436. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  437. {
  438. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  439. }
  440. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  441. {
  442. struct smsc75xx_priv *pdata =
  443. container_of(param, struct smsc75xx_priv, set_multicast);
  444. struct usbnet *dev = pdata->dev;
  445. int ret;
  446. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  447. pdata->rfe_ctl);
  448. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  449. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  450. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  451. if (ret < 0)
  452. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  453. }
  454. static void smsc75xx_set_multicast(struct net_device *netdev)
  455. {
  456. struct usbnet *dev = netdev_priv(netdev);
  457. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  458. unsigned long flags;
  459. int i;
  460. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  461. pdata->rfe_ctl &=
  462. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  463. pdata->rfe_ctl |= RFE_CTL_AB;
  464. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  465. pdata->multicast_hash_table[i] = 0;
  466. if (dev->net->flags & IFF_PROMISC) {
  467. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  468. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  469. } else if (dev->net->flags & IFF_ALLMULTI) {
  470. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  471. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  472. } else if (!netdev_mc_empty(dev->net)) {
  473. struct netdev_hw_addr *ha;
  474. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  475. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  476. netdev_for_each_mc_addr(ha, netdev) {
  477. u32 bitnum = smsc75xx_hash(ha->addr);
  478. pdata->multicast_hash_table[bitnum / 32] |=
  479. (1 << (bitnum % 32));
  480. }
  481. } else {
  482. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  483. pdata->rfe_ctl |= RFE_CTL_DPF;
  484. }
  485. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  486. /* defer register writes to a sleepable context */
  487. schedule_work(&pdata->set_multicast);
  488. }
  489. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  490. u16 lcladv, u16 rmtadv)
  491. {
  492. u32 flow = 0, fct_flow = 0;
  493. int ret;
  494. if (duplex == DUPLEX_FULL) {
  495. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  496. if (cap & FLOW_CTRL_TX) {
  497. flow = (FLOW_TX_FCEN | 0xFFFF);
  498. /* set fct_flow thresholds to 20% and 80% */
  499. fct_flow = (8 << 8) | 32;
  500. }
  501. if (cap & FLOW_CTRL_RX)
  502. flow |= FLOW_RX_FCEN;
  503. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  504. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  505. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  506. } else {
  507. netif_dbg(dev, link, dev->net, "half duplex\n");
  508. }
  509. ret = smsc75xx_write_reg(dev, FLOW, flow);
  510. if (ret < 0) {
  511. netdev_warn(dev->net, "Error writing FLOW\n");
  512. return ret;
  513. }
  514. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  515. if (ret < 0) {
  516. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  517. return ret;
  518. }
  519. return 0;
  520. }
  521. static int smsc75xx_link_reset(struct usbnet *dev)
  522. {
  523. struct mii_if_info *mii = &dev->mii;
  524. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  525. u16 lcladv, rmtadv;
  526. int ret;
  527. /* write to clear phy interrupt status */
  528. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  529. PHY_INT_SRC_CLEAR_ALL);
  530. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  531. if (ret < 0) {
  532. netdev_warn(dev->net, "Error writing INT_STS\n");
  533. return ret;
  534. }
  535. mii_check_media(mii, 1, 1);
  536. mii_ethtool_gset(&dev->mii, &ecmd);
  537. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  538. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  539. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  540. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  541. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  542. }
  543. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  544. {
  545. u32 intdata;
  546. if (urb->actual_length != 4) {
  547. netdev_warn(dev->net, "unexpected urb length %d\n",
  548. urb->actual_length);
  549. return;
  550. }
  551. memcpy(&intdata, urb->transfer_buffer, 4);
  552. le32_to_cpus(&intdata);
  553. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  554. if (intdata & INT_ENP_PHY_INT)
  555. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  556. else
  557. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  558. intdata);
  559. }
  560. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  561. {
  562. return MAX_EEPROM_SIZE;
  563. }
  564. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  565. struct ethtool_eeprom *ee, u8 *data)
  566. {
  567. struct usbnet *dev = netdev_priv(netdev);
  568. ee->magic = LAN75XX_EEPROM_MAGIC;
  569. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  570. }
  571. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  572. struct ethtool_eeprom *ee, u8 *data)
  573. {
  574. struct usbnet *dev = netdev_priv(netdev);
  575. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  576. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  577. ee->magic);
  578. return -EINVAL;
  579. }
  580. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  581. }
  582. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  583. struct ethtool_wolinfo *wolinfo)
  584. {
  585. struct usbnet *dev = netdev_priv(net);
  586. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  587. wolinfo->supported = SUPPORTED_WAKE;
  588. wolinfo->wolopts = pdata->wolopts;
  589. }
  590. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  591. struct ethtool_wolinfo *wolinfo)
  592. {
  593. struct usbnet *dev = netdev_priv(net);
  594. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  595. int ret;
  596. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  597. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  598. if (ret < 0)
  599. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  600. return ret;
  601. }
  602. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  603. .get_link = usbnet_get_link,
  604. .nway_reset = usbnet_nway_reset,
  605. .get_drvinfo = usbnet_get_drvinfo,
  606. .get_msglevel = usbnet_get_msglevel,
  607. .set_msglevel = usbnet_set_msglevel,
  608. .get_settings = usbnet_get_settings,
  609. .set_settings = usbnet_set_settings,
  610. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  611. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  612. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  613. .get_wol = smsc75xx_ethtool_get_wol,
  614. .set_wol = smsc75xx_ethtool_set_wol,
  615. };
  616. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  617. {
  618. struct usbnet *dev = netdev_priv(netdev);
  619. if (!netif_running(netdev))
  620. return -EINVAL;
  621. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  622. }
  623. static void smsc75xx_init_mac_address(struct usbnet *dev)
  624. {
  625. const u8 *mac_addr;
  626. /* maybe the boot loader passed the MAC address in devicetree */
  627. mac_addr = of_get_mac_address(dev->udev->dev.of_node);
  628. if (mac_addr) {
  629. memcpy(dev->net->dev_addr, mac_addr, ETH_ALEN);
  630. return;
  631. }
  632. /* try reading mac address from EEPROM */
  633. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  634. dev->net->dev_addr) == 0) {
  635. if (is_valid_ether_addr(dev->net->dev_addr)) {
  636. /* eeprom values are valid so use them */
  637. netif_dbg(dev, ifup, dev->net,
  638. "MAC address read from EEPROM\n");
  639. return;
  640. }
  641. }
  642. /* no useful static MAC address found. generate a random one */
  643. eth_hw_addr_random(dev->net);
  644. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  645. }
  646. static int smsc75xx_set_mac_address(struct usbnet *dev)
  647. {
  648. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  649. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  650. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  651. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  652. if (ret < 0) {
  653. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  654. return ret;
  655. }
  656. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  657. if (ret < 0) {
  658. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  659. return ret;
  660. }
  661. addr_hi |= ADDR_FILTX_FB_VALID;
  662. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  663. if (ret < 0) {
  664. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  665. return ret;
  666. }
  667. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  668. if (ret < 0)
  669. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  670. return ret;
  671. }
  672. static int smsc75xx_phy_initialize(struct usbnet *dev)
  673. {
  674. int bmcr, ret, timeout = 0;
  675. /* Initialize MII structure */
  676. dev->mii.dev = dev->net;
  677. dev->mii.mdio_read = smsc75xx_mdio_read;
  678. dev->mii.mdio_write = smsc75xx_mdio_write;
  679. dev->mii.phy_id_mask = 0x1f;
  680. dev->mii.reg_num_mask = 0x1f;
  681. dev->mii.supports_gmii = 1;
  682. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  683. /* reset phy and wait for reset to complete */
  684. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  685. do {
  686. msleep(10);
  687. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  688. if (bmcr < 0) {
  689. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  690. return bmcr;
  691. }
  692. timeout++;
  693. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  694. if (timeout >= 100) {
  695. netdev_warn(dev->net, "timeout on PHY Reset\n");
  696. return -EIO;
  697. }
  698. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  699. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  700. ADVERTISE_PAUSE_ASYM);
  701. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  702. ADVERTISE_1000FULL);
  703. /* read and write to clear phy interrupt status */
  704. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  705. if (ret < 0) {
  706. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  707. return ret;
  708. }
  709. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  710. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  711. PHY_INT_MASK_DEFAULT);
  712. mii_nway_restart(&dev->mii);
  713. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  714. return 0;
  715. }
  716. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  717. {
  718. int ret = 0;
  719. u32 buf;
  720. bool rxenabled;
  721. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  722. if (ret < 0) {
  723. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  724. return ret;
  725. }
  726. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  727. if (rxenabled) {
  728. buf &= ~MAC_RX_RXEN;
  729. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  730. if (ret < 0) {
  731. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  732. return ret;
  733. }
  734. }
  735. /* add 4 to size for FCS */
  736. buf &= ~MAC_RX_MAX_SIZE;
  737. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  738. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  739. if (ret < 0) {
  740. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  741. return ret;
  742. }
  743. if (rxenabled) {
  744. buf |= MAC_RX_RXEN;
  745. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  746. if (ret < 0) {
  747. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  748. return ret;
  749. }
  750. }
  751. return 0;
  752. }
  753. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  754. {
  755. struct usbnet *dev = netdev_priv(netdev);
  756. int ret;
  757. if (new_mtu > MAX_SINGLE_PACKET_SIZE)
  758. return -EINVAL;
  759. ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
  760. if (ret < 0) {
  761. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  762. return ret;
  763. }
  764. return usbnet_change_mtu(netdev, new_mtu);
  765. }
  766. /* Enable or disable Rx checksum offload engine */
  767. static int smsc75xx_set_features(struct net_device *netdev,
  768. netdev_features_t features)
  769. {
  770. struct usbnet *dev = netdev_priv(netdev);
  771. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  772. unsigned long flags;
  773. int ret;
  774. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  775. if (features & NETIF_F_RXCSUM)
  776. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  777. else
  778. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  779. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  780. /* it's racing here! */
  781. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  782. if (ret < 0)
  783. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  784. return ret;
  785. }
  786. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  787. {
  788. int timeout = 0;
  789. do {
  790. u32 buf;
  791. int ret;
  792. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  793. if (ret < 0) {
  794. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  795. return ret;
  796. }
  797. if (buf & PMT_CTL_DEV_RDY)
  798. return 0;
  799. msleep(10);
  800. timeout++;
  801. } while (timeout < 100);
  802. netdev_warn(dev->net, "timeout waiting for device ready\n");
  803. return -EIO;
  804. }
  805. static int smsc75xx_reset(struct usbnet *dev)
  806. {
  807. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  808. u32 buf;
  809. int ret = 0, timeout;
  810. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  811. ret = smsc75xx_wait_ready(dev, 0);
  812. if (ret < 0) {
  813. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  814. return ret;
  815. }
  816. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  817. if (ret < 0) {
  818. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  819. return ret;
  820. }
  821. buf |= HW_CFG_LRST;
  822. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  823. if (ret < 0) {
  824. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  825. return ret;
  826. }
  827. timeout = 0;
  828. do {
  829. msleep(10);
  830. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  831. if (ret < 0) {
  832. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  833. return ret;
  834. }
  835. timeout++;
  836. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  837. if (timeout >= 100) {
  838. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  839. return -EIO;
  840. }
  841. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  842. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  843. if (ret < 0) {
  844. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  845. return ret;
  846. }
  847. buf |= PMT_CTL_PHY_RST;
  848. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  849. if (ret < 0) {
  850. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  851. return ret;
  852. }
  853. timeout = 0;
  854. do {
  855. msleep(10);
  856. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  857. if (ret < 0) {
  858. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  859. return ret;
  860. }
  861. timeout++;
  862. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  863. if (timeout >= 100) {
  864. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  865. return -EIO;
  866. }
  867. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  868. ret = smsc75xx_set_mac_address(dev);
  869. if (ret < 0) {
  870. netdev_warn(dev->net, "Failed to set mac address\n");
  871. return ret;
  872. }
  873. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  874. dev->net->dev_addr);
  875. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  876. if (ret < 0) {
  877. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  878. return ret;
  879. }
  880. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  881. buf);
  882. buf |= HW_CFG_BIR;
  883. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  884. if (ret < 0) {
  885. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  886. return ret;
  887. }
  888. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  889. if (ret < 0) {
  890. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  891. return ret;
  892. }
  893. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  894. buf);
  895. if (!turbo_mode) {
  896. buf = 0;
  897. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  898. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  899. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  900. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  901. } else {
  902. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  903. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  904. }
  905. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  906. (ulong)dev->rx_urb_size);
  907. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  908. if (ret < 0) {
  909. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  910. return ret;
  911. }
  912. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  913. if (ret < 0) {
  914. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  915. return ret;
  916. }
  917. netif_dbg(dev, ifup, dev->net,
  918. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  919. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  920. if (ret < 0) {
  921. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  922. return ret;
  923. }
  924. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  925. if (ret < 0) {
  926. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  927. return ret;
  928. }
  929. netif_dbg(dev, ifup, dev->net,
  930. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  931. if (turbo_mode) {
  932. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  933. if (ret < 0) {
  934. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  935. return ret;
  936. }
  937. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  938. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  939. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  940. if (ret < 0) {
  941. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  942. return ret;
  943. }
  944. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  945. if (ret < 0) {
  946. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  947. return ret;
  948. }
  949. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  950. }
  951. /* set FIFO sizes */
  952. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  953. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  954. if (ret < 0) {
  955. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  956. return ret;
  957. }
  958. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  959. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  960. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  961. if (ret < 0) {
  962. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  963. return ret;
  964. }
  965. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  966. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  967. if (ret < 0) {
  968. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  969. return ret;
  970. }
  971. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  972. if (ret < 0) {
  973. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  974. return ret;
  975. }
  976. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  977. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  978. if (ret < 0) {
  979. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  980. return ret;
  981. }
  982. /* only set default GPIO/LED settings if no EEPROM is detected */
  983. if (!(buf & E2P_CMD_LOADED)) {
  984. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  985. if (ret < 0) {
  986. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  987. return ret;
  988. }
  989. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  990. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  991. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  992. if (ret < 0) {
  993. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  994. return ret;
  995. }
  996. }
  997. ret = smsc75xx_write_reg(dev, FLOW, 0);
  998. if (ret < 0) {
  999. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  1000. return ret;
  1001. }
  1002. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  1003. if (ret < 0) {
  1004. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  1005. return ret;
  1006. }
  1007. /* Don't need rfe_ctl_lock during initialisation */
  1008. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1009. if (ret < 0) {
  1010. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1011. return ret;
  1012. }
  1013. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1014. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1015. if (ret < 0) {
  1016. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1017. return ret;
  1018. }
  1019. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1020. if (ret < 0) {
  1021. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1022. return ret;
  1023. }
  1024. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1025. pdata->rfe_ctl);
  1026. /* Enable or disable checksum offload engines */
  1027. smsc75xx_set_features(dev->net, dev->net->features);
  1028. smsc75xx_set_multicast(dev->net);
  1029. ret = smsc75xx_phy_initialize(dev);
  1030. if (ret < 0) {
  1031. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1032. return ret;
  1033. }
  1034. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1035. if (ret < 0) {
  1036. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1037. return ret;
  1038. }
  1039. /* enable PHY interrupts */
  1040. buf |= INT_ENP_PHY_INT;
  1041. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1042. if (ret < 0) {
  1043. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1044. return ret;
  1045. }
  1046. /* allow mac to detect speed and duplex from phy */
  1047. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1048. if (ret < 0) {
  1049. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1050. return ret;
  1051. }
  1052. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1053. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1054. if (ret < 0) {
  1055. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1056. return ret;
  1057. }
  1058. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1059. if (ret < 0) {
  1060. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1061. return ret;
  1062. }
  1063. buf |= MAC_TX_TXEN;
  1064. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1065. if (ret < 0) {
  1066. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1067. return ret;
  1068. }
  1069. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1070. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1071. if (ret < 0) {
  1072. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1073. return ret;
  1074. }
  1075. buf |= FCT_TX_CTL_EN;
  1076. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1077. if (ret < 0) {
  1078. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1079. return ret;
  1080. }
  1081. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1082. ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
  1083. if (ret < 0) {
  1084. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1085. return ret;
  1086. }
  1087. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1088. if (ret < 0) {
  1089. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1090. return ret;
  1091. }
  1092. buf |= MAC_RX_RXEN;
  1093. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1094. if (ret < 0) {
  1095. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1096. return ret;
  1097. }
  1098. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1099. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1100. if (ret < 0) {
  1101. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1102. return ret;
  1103. }
  1104. buf |= FCT_RX_CTL_EN;
  1105. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1106. if (ret < 0) {
  1107. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1108. return ret;
  1109. }
  1110. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1111. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1112. return 0;
  1113. }
  1114. static const struct net_device_ops smsc75xx_netdev_ops = {
  1115. .ndo_open = usbnet_open,
  1116. .ndo_stop = usbnet_stop,
  1117. .ndo_start_xmit = usbnet_start_xmit,
  1118. .ndo_tx_timeout = usbnet_tx_timeout,
  1119. .ndo_change_mtu = smsc75xx_change_mtu,
  1120. .ndo_set_mac_address = eth_mac_addr,
  1121. .ndo_validate_addr = eth_validate_addr,
  1122. .ndo_do_ioctl = smsc75xx_ioctl,
  1123. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1124. .ndo_set_features = smsc75xx_set_features,
  1125. };
  1126. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1127. {
  1128. struct smsc75xx_priv *pdata = NULL;
  1129. int ret;
  1130. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1131. ret = usbnet_get_endpoints(dev, intf);
  1132. if (ret < 0) {
  1133. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1134. return ret;
  1135. }
  1136. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  1137. GFP_KERNEL);
  1138. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1139. if (!pdata)
  1140. return -ENOMEM;
  1141. pdata->dev = dev;
  1142. spin_lock_init(&pdata->rfe_ctl_lock);
  1143. mutex_init(&pdata->dataport_mutex);
  1144. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1145. if (DEFAULT_TX_CSUM_ENABLE)
  1146. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1147. if (DEFAULT_RX_CSUM_ENABLE)
  1148. dev->net->features |= NETIF_F_RXCSUM;
  1149. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1150. NETIF_F_RXCSUM;
  1151. ret = smsc75xx_wait_ready(dev, 0);
  1152. if (ret < 0) {
  1153. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1154. return ret;
  1155. }
  1156. smsc75xx_init_mac_address(dev);
  1157. /* Init all registers */
  1158. ret = smsc75xx_reset(dev);
  1159. if (ret < 0) {
  1160. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1161. return ret;
  1162. }
  1163. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1164. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1165. dev->net->flags |= IFF_MULTICAST;
  1166. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1167. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1168. return 0;
  1169. }
  1170. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1171. {
  1172. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1173. if (pdata) {
  1174. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1175. kfree(pdata);
  1176. pdata = NULL;
  1177. dev->data[0] = 0;
  1178. }
  1179. }
  1180. static u16 smsc_crc(const u8 *buffer, size_t len)
  1181. {
  1182. return bitrev16(crc16(0xFFFF, buffer, len));
  1183. }
  1184. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1185. u32 wuf_mask1)
  1186. {
  1187. int cfg_base = WUF_CFGX + filter * 4;
  1188. int mask_base = WUF_MASKX + filter * 16;
  1189. int ret;
  1190. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1191. if (ret < 0) {
  1192. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1193. return ret;
  1194. }
  1195. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1196. if (ret < 0) {
  1197. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1198. return ret;
  1199. }
  1200. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1201. if (ret < 0) {
  1202. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1203. return ret;
  1204. }
  1205. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1206. if (ret < 0) {
  1207. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1208. return ret;
  1209. }
  1210. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1211. if (ret < 0) {
  1212. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1213. return ret;
  1214. }
  1215. return 0;
  1216. }
  1217. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1218. {
  1219. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1220. u32 val;
  1221. int ret;
  1222. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1223. if (ret < 0) {
  1224. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1225. return ret;
  1226. }
  1227. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1228. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1229. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1230. if (ret < 0) {
  1231. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1232. return ret;
  1233. }
  1234. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1235. return 0;
  1236. }
  1237. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1238. {
  1239. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1240. u32 val;
  1241. int ret;
  1242. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1243. if (ret < 0) {
  1244. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1245. return ret;
  1246. }
  1247. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1248. val |= PMT_CTL_SUS_MODE_1;
  1249. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1250. if (ret < 0) {
  1251. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1252. return ret;
  1253. }
  1254. /* clear wol status, enable energy detection */
  1255. val &= ~PMT_CTL_WUPS;
  1256. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1257. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1258. if (ret < 0) {
  1259. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1260. return ret;
  1261. }
  1262. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1263. return 0;
  1264. }
  1265. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1266. {
  1267. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1268. u32 val;
  1269. int ret;
  1270. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1271. if (ret < 0) {
  1272. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1273. return ret;
  1274. }
  1275. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1276. val |= PMT_CTL_SUS_MODE_2;
  1277. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1278. if (ret < 0) {
  1279. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1280. return ret;
  1281. }
  1282. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1283. return 0;
  1284. }
  1285. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1286. {
  1287. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1288. u32 val;
  1289. int ret;
  1290. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1291. if (ret < 0) {
  1292. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1293. return ret;
  1294. }
  1295. if (val & FCT_RX_CTL_RXUSED) {
  1296. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1297. return -EBUSY;
  1298. }
  1299. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1300. if (ret < 0) {
  1301. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1302. return ret;
  1303. }
  1304. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1305. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1306. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1307. if (ret < 0) {
  1308. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1309. return ret;
  1310. }
  1311. /* clear wol status */
  1312. val &= ~PMT_CTL_WUPS;
  1313. val |= PMT_CTL_WUPS_WOL;
  1314. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1315. if (ret < 0) {
  1316. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1317. return ret;
  1318. }
  1319. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1320. return 0;
  1321. }
  1322. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1323. {
  1324. struct mii_if_info *mii = &dev->mii;
  1325. int ret;
  1326. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1327. /* read to clear */
  1328. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1329. if (ret < 0) {
  1330. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1331. return ret;
  1332. }
  1333. /* enable interrupt source */
  1334. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1335. if (ret < 0) {
  1336. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1337. return ret;
  1338. }
  1339. ret |= mask;
  1340. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1341. return 0;
  1342. }
  1343. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1344. {
  1345. struct mii_if_info *mii = &dev->mii;
  1346. int ret;
  1347. /* first, a dummy read, needed to latch some MII phys */
  1348. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1349. if (ret < 0) {
  1350. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1351. return ret;
  1352. }
  1353. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1354. if (ret < 0) {
  1355. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1356. return ret;
  1357. }
  1358. return !!(ret & BMSR_LSTATUS);
  1359. }
  1360. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1361. {
  1362. int ret;
  1363. if (!netif_running(dev->net)) {
  1364. /* interface is ifconfig down so fully power down hw */
  1365. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1366. return smsc75xx_enter_suspend2(dev);
  1367. }
  1368. if (!link_up) {
  1369. /* link is down so enter EDPD mode */
  1370. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1371. /* enable PHY wakeup events for if cable is attached */
  1372. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1373. PHY_INT_MASK_ANEG_COMP);
  1374. if (ret < 0) {
  1375. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1376. return ret;
  1377. }
  1378. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1379. return smsc75xx_enter_suspend1(dev);
  1380. }
  1381. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1382. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1383. PHY_INT_MASK_LINK_DOWN);
  1384. if (ret < 0) {
  1385. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1386. return ret;
  1387. }
  1388. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1389. return smsc75xx_enter_suspend3(dev);
  1390. }
  1391. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1392. {
  1393. struct usbnet *dev = usb_get_intfdata(intf);
  1394. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1395. u32 val, link_up;
  1396. int ret;
  1397. ret = usbnet_suspend(intf, message);
  1398. if (ret < 0) {
  1399. netdev_warn(dev->net, "usbnet_suspend error\n");
  1400. return ret;
  1401. }
  1402. if (pdata->suspend_flags) {
  1403. netdev_warn(dev->net, "error during last resume\n");
  1404. pdata->suspend_flags = 0;
  1405. }
  1406. /* determine if link is up using only _nopm functions */
  1407. link_up = smsc75xx_link_ok_nopm(dev);
  1408. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1409. ret = smsc75xx_autosuspend(dev, link_up);
  1410. goto done;
  1411. }
  1412. /* if we get this far we're not autosuspending */
  1413. /* if no wol options set, or if link is down and we're not waking on
  1414. * PHY activity, enter lowest power SUSPEND2 mode
  1415. */
  1416. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1417. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1418. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1419. /* disable energy detect (link up) & wake up events */
  1420. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1421. if (ret < 0) {
  1422. netdev_warn(dev->net, "Error reading WUCSR\n");
  1423. goto done;
  1424. }
  1425. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1426. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1427. if (ret < 0) {
  1428. netdev_warn(dev->net, "Error writing WUCSR\n");
  1429. goto done;
  1430. }
  1431. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1432. if (ret < 0) {
  1433. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1434. goto done;
  1435. }
  1436. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1437. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1438. if (ret < 0) {
  1439. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1440. goto done;
  1441. }
  1442. ret = smsc75xx_enter_suspend2(dev);
  1443. goto done;
  1444. }
  1445. if (pdata->wolopts & WAKE_PHY) {
  1446. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1447. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1448. if (ret < 0) {
  1449. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1450. goto done;
  1451. }
  1452. /* if link is down then configure EDPD and enter SUSPEND1,
  1453. * otherwise enter SUSPEND0 below
  1454. */
  1455. if (!link_up) {
  1456. struct mii_if_info *mii = &dev->mii;
  1457. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1458. /* enable energy detect power-down mode */
  1459. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1460. PHY_MODE_CTRL_STS);
  1461. if (ret < 0) {
  1462. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1463. goto done;
  1464. }
  1465. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1466. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1467. PHY_MODE_CTRL_STS, ret);
  1468. /* enter SUSPEND1 mode */
  1469. ret = smsc75xx_enter_suspend1(dev);
  1470. goto done;
  1471. }
  1472. }
  1473. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1474. int i, filter = 0;
  1475. /* disable all filters */
  1476. for (i = 0; i < WUF_NUM; i++) {
  1477. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1478. if (ret < 0) {
  1479. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1480. goto done;
  1481. }
  1482. }
  1483. if (pdata->wolopts & WAKE_MCAST) {
  1484. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1485. netdev_info(dev->net, "enabling multicast detection\n");
  1486. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1487. | smsc_crc(mcast, 3);
  1488. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1489. if (ret < 0) {
  1490. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1491. goto done;
  1492. }
  1493. }
  1494. if (pdata->wolopts & WAKE_ARP) {
  1495. const u8 arp[] = {0x08, 0x06};
  1496. netdev_info(dev->net, "enabling ARP detection\n");
  1497. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1498. | smsc_crc(arp, 2);
  1499. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1500. if (ret < 0) {
  1501. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1502. goto done;
  1503. }
  1504. }
  1505. /* clear any pending pattern match packet status */
  1506. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1507. if (ret < 0) {
  1508. netdev_warn(dev->net, "Error reading WUCSR\n");
  1509. goto done;
  1510. }
  1511. val |= WUCSR_WUFR;
  1512. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1513. if (ret < 0) {
  1514. netdev_warn(dev->net, "Error writing WUCSR\n");
  1515. goto done;
  1516. }
  1517. netdev_info(dev->net, "enabling packet match detection\n");
  1518. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1519. if (ret < 0) {
  1520. netdev_warn(dev->net, "Error reading WUCSR\n");
  1521. goto done;
  1522. }
  1523. val |= WUCSR_WUEN;
  1524. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1525. if (ret < 0) {
  1526. netdev_warn(dev->net, "Error writing WUCSR\n");
  1527. goto done;
  1528. }
  1529. } else {
  1530. netdev_info(dev->net, "disabling packet match detection\n");
  1531. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1532. if (ret < 0) {
  1533. netdev_warn(dev->net, "Error reading WUCSR\n");
  1534. goto done;
  1535. }
  1536. val &= ~WUCSR_WUEN;
  1537. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1538. if (ret < 0) {
  1539. netdev_warn(dev->net, "Error writing WUCSR\n");
  1540. goto done;
  1541. }
  1542. }
  1543. /* disable magic, bcast & unicast wakeup sources */
  1544. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1545. if (ret < 0) {
  1546. netdev_warn(dev->net, "Error reading WUCSR\n");
  1547. goto done;
  1548. }
  1549. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1550. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1551. if (ret < 0) {
  1552. netdev_warn(dev->net, "Error writing WUCSR\n");
  1553. goto done;
  1554. }
  1555. if (pdata->wolopts & WAKE_PHY) {
  1556. netdev_info(dev->net, "enabling PHY wakeup\n");
  1557. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1558. if (ret < 0) {
  1559. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1560. goto done;
  1561. }
  1562. /* clear wol status, enable energy detection */
  1563. val &= ~PMT_CTL_WUPS;
  1564. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1565. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1566. if (ret < 0) {
  1567. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1568. goto done;
  1569. }
  1570. }
  1571. if (pdata->wolopts & WAKE_MAGIC) {
  1572. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1573. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1574. if (ret < 0) {
  1575. netdev_warn(dev->net, "Error reading WUCSR\n");
  1576. goto done;
  1577. }
  1578. /* clear any pending magic packet status */
  1579. val |= WUCSR_MPR | WUCSR_MPEN;
  1580. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1581. if (ret < 0) {
  1582. netdev_warn(dev->net, "Error writing WUCSR\n");
  1583. goto done;
  1584. }
  1585. }
  1586. if (pdata->wolopts & WAKE_BCAST) {
  1587. netdev_info(dev->net, "enabling broadcast detection\n");
  1588. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1589. if (ret < 0) {
  1590. netdev_warn(dev->net, "Error reading WUCSR\n");
  1591. goto done;
  1592. }
  1593. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1594. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1595. if (ret < 0) {
  1596. netdev_warn(dev->net, "Error writing WUCSR\n");
  1597. goto done;
  1598. }
  1599. }
  1600. if (pdata->wolopts & WAKE_UCAST) {
  1601. netdev_info(dev->net, "enabling unicast detection\n");
  1602. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1603. if (ret < 0) {
  1604. netdev_warn(dev->net, "Error reading WUCSR\n");
  1605. goto done;
  1606. }
  1607. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1608. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1609. if (ret < 0) {
  1610. netdev_warn(dev->net, "Error writing WUCSR\n");
  1611. goto done;
  1612. }
  1613. }
  1614. /* enable receiver to enable frame reception */
  1615. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1616. if (ret < 0) {
  1617. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1618. goto done;
  1619. }
  1620. val |= MAC_RX_RXEN;
  1621. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1622. if (ret < 0) {
  1623. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1624. goto done;
  1625. }
  1626. /* some wol options are enabled, so enter SUSPEND0 */
  1627. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1628. ret = smsc75xx_enter_suspend0(dev);
  1629. done:
  1630. /*
  1631. * TODO: resume() might need to handle the suspend failure
  1632. * in system sleep
  1633. */
  1634. if (ret && PMSG_IS_AUTO(message))
  1635. usbnet_resume(intf);
  1636. return ret;
  1637. }
  1638. static int smsc75xx_resume(struct usb_interface *intf)
  1639. {
  1640. struct usbnet *dev = usb_get_intfdata(intf);
  1641. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1642. u8 suspend_flags = pdata->suspend_flags;
  1643. int ret;
  1644. u32 val;
  1645. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1646. /* do this first to ensure it's cleared even in error case */
  1647. pdata->suspend_flags = 0;
  1648. if (suspend_flags & SUSPEND_ALLMODES) {
  1649. /* Disable wakeup sources */
  1650. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1651. if (ret < 0) {
  1652. netdev_warn(dev->net, "Error reading WUCSR\n");
  1653. return ret;
  1654. }
  1655. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1656. | WUCSR_BCST_EN);
  1657. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1658. if (ret < 0) {
  1659. netdev_warn(dev->net, "Error writing WUCSR\n");
  1660. return ret;
  1661. }
  1662. /* clear wake-up status */
  1663. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1664. if (ret < 0) {
  1665. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1666. return ret;
  1667. }
  1668. val &= ~PMT_CTL_WOL_EN;
  1669. val |= PMT_CTL_WUPS;
  1670. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1671. if (ret < 0) {
  1672. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1673. return ret;
  1674. }
  1675. }
  1676. if (suspend_flags & SUSPEND_SUSPEND2) {
  1677. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1678. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1679. if (ret < 0) {
  1680. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1681. return ret;
  1682. }
  1683. val |= PMT_CTL_PHY_PWRUP;
  1684. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1685. if (ret < 0) {
  1686. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1687. return ret;
  1688. }
  1689. }
  1690. ret = smsc75xx_wait_ready(dev, 1);
  1691. if (ret < 0) {
  1692. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1693. return ret;
  1694. }
  1695. return usbnet_resume(intf);
  1696. }
  1697. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1698. u32 rx_cmd_a, u32 rx_cmd_b)
  1699. {
  1700. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1701. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1702. skb->ip_summed = CHECKSUM_NONE;
  1703. } else {
  1704. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1705. skb->ip_summed = CHECKSUM_COMPLETE;
  1706. }
  1707. }
  1708. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1709. {
  1710. /* This check is no longer done by usbnet */
  1711. if (skb->len < dev->net->hard_header_len)
  1712. return 0;
  1713. while (skb->len > 0) {
  1714. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1715. struct sk_buff *ax_skb;
  1716. unsigned char *packet;
  1717. memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
  1718. le32_to_cpus(&rx_cmd_a);
  1719. skb_pull(skb, 4);
  1720. memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
  1721. le32_to_cpus(&rx_cmd_b);
  1722. skb_pull(skb, 4 + RXW_PADDING);
  1723. packet = skb->data;
  1724. /* get the packet length */
  1725. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1726. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1727. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1728. netif_dbg(dev, rx_err, dev->net,
  1729. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1730. dev->net->stats.rx_errors++;
  1731. dev->net->stats.rx_dropped++;
  1732. if (rx_cmd_a & RX_CMD_A_FCS)
  1733. dev->net->stats.rx_crc_errors++;
  1734. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1735. dev->net->stats.rx_frame_errors++;
  1736. } else {
  1737. /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
  1738. if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
  1739. netif_dbg(dev, rx_err, dev->net,
  1740. "size err rx_cmd_a=0x%08x\n",
  1741. rx_cmd_a);
  1742. return 0;
  1743. }
  1744. /* last frame in this batch */
  1745. if (skb->len == size) {
  1746. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1747. rx_cmd_b);
  1748. skb_trim(skb, skb->len - 4); /* remove fcs */
  1749. skb->truesize = size + sizeof(struct sk_buff);
  1750. return 1;
  1751. }
  1752. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1753. if (unlikely(!ax_skb)) {
  1754. netdev_warn(dev->net, "Error allocating skb\n");
  1755. return 0;
  1756. }
  1757. ax_skb->len = size;
  1758. ax_skb->data = packet;
  1759. skb_set_tail_pointer(ax_skb, size);
  1760. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1761. rx_cmd_b);
  1762. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1763. ax_skb->truesize = size + sizeof(struct sk_buff);
  1764. usbnet_skb_return(dev, ax_skb);
  1765. }
  1766. skb_pull(skb, size);
  1767. /* padding bytes before the next frame starts */
  1768. if (skb->len)
  1769. skb_pull(skb, align_count);
  1770. }
  1771. return 1;
  1772. }
  1773. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1774. struct sk_buff *skb, gfp_t flags)
  1775. {
  1776. u32 tx_cmd_a, tx_cmd_b;
  1777. if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
  1778. struct sk_buff *skb2 =
  1779. skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
  1780. dev_kfree_skb_any(skb);
  1781. skb = skb2;
  1782. if (!skb)
  1783. return NULL;
  1784. }
  1785. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1786. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1787. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1788. if (skb_is_gso(skb)) {
  1789. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1790. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1791. tx_cmd_a |= TX_CMD_A_LSO;
  1792. } else {
  1793. tx_cmd_b = 0;
  1794. }
  1795. skb_push(skb, 4);
  1796. cpu_to_le32s(&tx_cmd_b);
  1797. memcpy(skb->data, &tx_cmd_b, 4);
  1798. skb_push(skb, 4);
  1799. cpu_to_le32s(&tx_cmd_a);
  1800. memcpy(skb->data, &tx_cmd_a, 4);
  1801. return skb;
  1802. }
  1803. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1804. {
  1805. dev->intf->needs_remote_wakeup = on;
  1806. return 0;
  1807. }
  1808. static const struct driver_info smsc75xx_info = {
  1809. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1810. .bind = smsc75xx_bind,
  1811. .unbind = smsc75xx_unbind,
  1812. .link_reset = smsc75xx_link_reset,
  1813. .reset = smsc75xx_reset,
  1814. .rx_fixup = smsc75xx_rx_fixup,
  1815. .tx_fixup = smsc75xx_tx_fixup,
  1816. .status = smsc75xx_status,
  1817. .manage_power = smsc75xx_manage_power,
  1818. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1819. };
  1820. static const struct usb_device_id products[] = {
  1821. {
  1822. /* SMSC7500 USB Gigabit Ethernet Device */
  1823. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1824. .driver_info = (unsigned long) &smsc75xx_info,
  1825. },
  1826. {
  1827. /* SMSC7500 USB Gigabit Ethernet Device */
  1828. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1829. .driver_info = (unsigned long) &smsc75xx_info,
  1830. },
  1831. { }, /* END */
  1832. };
  1833. MODULE_DEVICE_TABLE(usb, products);
  1834. static struct usb_driver smsc75xx_driver = {
  1835. .name = SMSC_CHIPNAME,
  1836. .id_table = products,
  1837. .probe = usbnet_probe,
  1838. .suspend = smsc75xx_suspend,
  1839. .resume = smsc75xx_resume,
  1840. .reset_resume = smsc75xx_resume,
  1841. .disconnect = usbnet_disconnect,
  1842. .disable_hub_initiated_lpm = 1,
  1843. .supports_autosuspend = 1,
  1844. };
  1845. module_usb_driver(smsc75xx_driver);
  1846. MODULE_AUTHOR("Nancy Lin");
  1847. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1848. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1849. MODULE_LICENSE("GPL");