r8152.c 103 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. #include <linux/suspend.h>
  28. #include <linux/acpi.h>
  29. /* Information for net-next */
  30. #define NETNEXT_VERSION "08"
  31. /* Information for net */
  32. #define NET_VERSION "8"
  33. #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
  34. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  35. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  36. #define MODULENAME "r8152"
  37. #define R8152_PHY_ID 32
  38. #define PLA_IDR 0xc000
  39. #define PLA_RCR 0xc010
  40. #define PLA_RMS 0xc016
  41. #define PLA_RXFIFO_CTRL0 0xc0a0
  42. #define PLA_RXFIFO_CTRL1 0xc0a4
  43. #define PLA_RXFIFO_CTRL2 0xc0a8
  44. #define PLA_DMY_REG0 0xc0b0
  45. #define PLA_FMC 0xc0b4
  46. #define PLA_CFG_WOL 0xc0b6
  47. #define PLA_TEREDO_CFG 0xc0bc
  48. #define PLA_MAR 0xcd00
  49. #define PLA_BACKUP 0xd000
  50. #define PAL_BDC_CR 0xd1a0
  51. #define PLA_TEREDO_TIMER 0xd2cc
  52. #define PLA_REALWOW_TIMER 0xd2e8
  53. #define PLA_LEDSEL 0xdd90
  54. #define PLA_LED_FEATURE 0xdd92
  55. #define PLA_PHYAR 0xde00
  56. #define PLA_BOOT_CTRL 0xe004
  57. #define PLA_GPHY_INTR_IMR 0xe022
  58. #define PLA_EEE_CR 0xe040
  59. #define PLA_EEEP_CR 0xe080
  60. #define PLA_MAC_PWR_CTRL 0xe0c0
  61. #define PLA_MAC_PWR_CTRL2 0xe0ca
  62. #define PLA_MAC_PWR_CTRL3 0xe0cc
  63. #define PLA_MAC_PWR_CTRL4 0xe0ce
  64. #define PLA_WDT6_CTRL 0xe428
  65. #define PLA_TCR0 0xe610
  66. #define PLA_TCR1 0xe612
  67. #define PLA_MTPS 0xe615
  68. #define PLA_TXFIFO_CTRL 0xe618
  69. #define PLA_RSTTALLY 0xe800
  70. #define PLA_CR 0xe813
  71. #define PLA_CRWECR 0xe81c
  72. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  73. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  74. #define PLA_CONFIG5 0xe822
  75. #define PLA_PHY_PWR 0xe84c
  76. #define PLA_OOB_CTRL 0xe84f
  77. #define PLA_CPCR 0xe854
  78. #define PLA_MISC_0 0xe858
  79. #define PLA_MISC_1 0xe85a
  80. #define PLA_OCP_GPHY_BASE 0xe86c
  81. #define PLA_TALLYCNT 0xe890
  82. #define PLA_SFF_STS_7 0xe8de
  83. #define PLA_PHYSTATUS 0xe908
  84. #define PLA_BP_BA 0xfc26
  85. #define PLA_BP_0 0xfc28
  86. #define PLA_BP_1 0xfc2a
  87. #define PLA_BP_2 0xfc2c
  88. #define PLA_BP_3 0xfc2e
  89. #define PLA_BP_4 0xfc30
  90. #define PLA_BP_5 0xfc32
  91. #define PLA_BP_6 0xfc34
  92. #define PLA_BP_7 0xfc36
  93. #define PLA_BP_EN 0xfc38
  94. #define USB_USB2PHY 0xb41e
  95. #define USB_SSPHYLINK2 0xb428
  96. #define USB_U2P3_CTRL 0xb460
  97. #define USB_CSR_DUMMY1 0xb464
  98. #define USB_CSR_DUMMY2 0xb466
  99. #define USB_DEV_STAT 0xb808
  100. #define USB_CONNECT_TIMER 0xcbf8
  101. #define USB_BURST_SIZE 0xcfc0
  102. #define USB_USB_CTRL 0xd406
  103. #define USB_PHY_CTRL 0xd408
  104. #define USB_TX_AGG 0xd40a
  105. #define USB_RX_BUF_TH 0xd40c
  106. #define USB_USB_TIMER 0xd428
  107. #define USB_RX_EARLY_TIMEOUT 0xd42c
  108. #define USB_RX_EARLY_SIZE 0xd42e
  109. #define USB_PM_CTRL_STATUS 0xd432
  110. #define USB_TX_DMA 0xd434
  111. #define USB_TOLERANCE 0xd490
  112. #define USB_LPM_CTRL 0xd41a
  113. #define USB_BMU_RESET 0xd4b0
  114. #define USB_UPS_CTRL 0xd800
  115. #define USB_MISC_0 0xd81a
  116. #define USB_POWER_CUT 0xd80a
  117. #define USB_AFE_CTRL2 0xd824
  118. #define USB_WDT11_CTRL 0xe43c
  119. #define USB_BP_BA 0xfc26
  120. #define USB_BP_0 0xfc28
  121. #define USB_BP_1 0xfc2a
  122. #define USB_BP_2 0xfc2c
  123. #define USB_BP_3 0xfc2e
  124. #define USB_BP_4 0xfc30
  125. #define USB_BP_5 0xfc32
  126. #define USB_BP_6 0xfc34
  127. #define USB_BP_7 0xfc36
  128. #define USB_BP_EN 0xfc38
  129. /* OCP Registers */
  130. #define OCP_ALDPS_CONFIG 0x2010
  131. #define OCP_EEE_CONFIG1 0x2080
  132. #define OCP_EEE_CONFIG2 0x2092
  133. #define OCP_EEE_CONFIG3 0x2094
  134. #define OCP_BASE_MII 0xa400
  135. #define OCP_EEE_AR 0xa41a
  136. #define OCP_EEE_DATA 0xa41c
  137. #define OCP_PHY_STATUS 0xa420
  138. #define OCP_POWER_CFG 0xa430
  139. #define OCP_EEE_CFG 0xa432
  140. #define OCP_SRAM_ADDR 0xa436
  141. #define OCP_SRAM_DATA 0xa438
  142. #define OCP_DOWN_SPEED 0xa442
  143. #define OCP_EEE_ABLE 0xa5c4
  144. #define OCP_EEE_ADV 0xa5d0
  145. #define OCP_EEE_LPABLE 0xa5d2
  146. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  147. #define OCP_ADC_CFG 0xbc06
  148. /* SRAM Register */
  149. #define SRAM_LPF_CFG 0x8012
  150. #define SRAM_10M_AMP1 0x8080
  151. #define SRAM_10M_AMP2 0x8082
  152. #define SRAM_IMPEDANCE 0x8084
  153. /* PLA_RCR */
  154. #define RCR_AAP 0x00000001
  155. #define RCR_APM 0x00000002
  156. #define RCR_AM 0x00000004
  157. #define RCR_AB 0x00000008
  158. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  159. /* PLA_RXFIFO_CTRL0 */
  160. #define RXFIFO_THR1_NORMAL 0x00080002
  161. #define RXFIFO_THR1_OOB 0x01800003
  162. /* PLA_RXFIFO_CTRL1 */
  163. #define RXFIFO_THR2_FULL 0x00000060
  164. #define RXFIFO_THR2_HIGH 0x00000038
  165. #define RXFIFO_THR2_OOB 0x0000004a
  166. #define RXFIFO_THR2_NORMAL 0x00a0
  167. /* PLA_RXFIFO_CTRL2 */
  168. #define RXFIFO_THR3_FULL 0x00000078
  169. #define RXFIFO_THR3_HIGH 0x00000048
  170. #define RXFIFO_THR3_OOB 0x0000005a
  171. #define RXFIFO_THR3_NORMAL 0x0110
  172. /* PLA_TXFIFO_CTRL */
  173. #define TXFIFO_THR_NORMAL 0x00400008
  174. #define TXFIFO_THR_NORMAL2 0x01000008
  175. /* PLA_DMY_REG0 */
  176. #define ECM_ALDPS 0x0002
  177. /* PLA_FMC */
  178. #define FMC_FCR_MCU_EN 0x0001
  179. /* PLA_EEEP_CR */
  180. #define EEEP_CR_EEEP_TX 0x0002
  181. /* PLA_WDT6_CTRL */
  182. #define WDT6_SET_MODE 0x0010
  183. /* PLA_TCR0 */
  184. #define TCR0_TX_EMPTY 0x0800
  185. #define TCR0_AUTO_FIFO 0x0080
  186. /* PLA_TCR1 */
  187. #define VERSION_MASK 0x7cf0
  188. /* PLA_MTPS */
  189. #define MTPS_JUMBO (12 * 1024 / 64)
  190. #define MTPS_DEFAULT (6 * 1024 / 64)
  191. /* PLA_RSTTALLY */
  192. #define TALLY_RESET 0x0001
  193. /* PLA_CR */
  194. #define CR_RST 0x10
  195. #define CR_RE 0x08
  196. #define CR_TE 0x04
  197. /* PLA_CRWECR */
  198. #define CRWECR_NORAML 0x00
  199. #define CRWECR_CONFIG 0xc0
  200. /* PLA_OOB_CTRL */
  201. #define NOW_IS_OOB 0x80
  202. #define TXFIFO_EMPTY 0x20
  203. #define RXFIFO_EMPTY 0x10
  204. #define LINK_LIST_READY 0x02
  205. #define DIS_MCU_CLROOB 0x01
  206. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  207. /* PLA_MISC_1 */
  208. #define RXDY_GATED_EN 0x0008
  209. /* PLA_SFF_STS_7 */
  210. #define RE_INIT_LL 0x8000
  211. #define MCU_BORW_EN 0x4000
  212. /* PLA_CPCR */
  213. #define CPCR_RX_VLAN 0x0040
  214. /* PLA_CFG_WOL */
  215. #define MAGIC_EN 0x0001
  216. /* PLA_TEREDO_CFG */
  217. #define TEREDO_SEL 0x8000
  218. #define TEREDO_WAKE_MASK 0x7f00
  219. #define TEREDO_RS_EVENT_MASK 0x00fe
  220. #define OOB_TEREDO_EN 0x0001
  221. /* PAL_BDC_CR */
  222. #define ALDPS_PROXY_MODE 0x0001
  223. /* PLA_CONFIG34 */
  224. #define LINK_ON_WAKE_EN 0x0010
  225. #define LINK_OFF_WAKE_EN 0x0008
  226. /* PLA_CONFIG5 */
  227. #define BWF_EN 0x0040
  228. #define MWF_EN 0x0020
  229. #define UWF_EN 0x0010
  230. #define LAN_WAKE_EN 0x0002
  231. /* PLA_LED_FEATURE */
  232. #define LED_MODE_MASK 0x0700
  233. /* PLA_PHY_PWR */
  234. #define TX_10M_IDLE_EN 0x0080
  235. #define PFM_PWM_SWITCH 0x0040
  236. /* PLA_MAC_PWR_CTRL */
  237. #define D3_CLK_GATED_EN 0x00004000
  238. #define MCU_CLK_RATIO 0x07010f07
  239. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  240. #define ALDPS_SPDWN_RATIO 0x0f87
  241. /* PLA_MAC_PWR_CTRL2 */
  242. #define EEE_SPDWN_RATIO 0x8007
  243. /* PLA_MAC_PWR_CTRL3 */
  244. #define PKT_AVAIL_SPDWN_EN 0x0100
  245. #define SUSPEND_SPDWN_EN 0x0004
  246. #define U1U2_SPDWN_EN 0x0002
  247. #define L1_SPDWN_EN 0x0001
  248. /* PLA_MAC_PWR_CTRL4 */
  249. #define PWRSAVE_SPDWN_EN 0x1000
  250. #define RXDV_SPDWN_EN 0x0800
  251. #define TX10MIDLE_EN 0x0100
  252. #define TP100_SPDWN_EN 0x0020
  253. #define TP500_SPDWN_EN 0x0010
  254. #define TP1000_SPDWN_EN 0x0008
  255. #define EEE_SPDWN_EN 0x0001
  256. /* PLA_GPHY_INTR_IMR */
  257. #define GPHY_STS_MSK 0x0001
  258. #define SPEED_DOWN_MSK 0x0002
  259. #define SPDWN_RXDV_MSK 0x0004
  260. #define SPDWN_LINKCHG_MSK 0x0008
  261. /* PLA_PHYAR */
  262. #define PHYAR_FLAG 0x80000000
  263. /* PLA_EEE_CR */
  264. #define EEE_RX_EN 0x0001
  265. #define EEE_TX_EN 0x0002
  266. /* PLA_BOOT_CTRL */
  267. #define AUTOLOAD_DONE 0x0002
  268. /* USB_USB2PHY */
  269. #define USB2PHY_SUSPEND 0x0001
  270. #define USB2PHY_L1 0x0002
  271. /* USB_SSPHYLINK2 */
  272. #define pwd_dn_scale_mask 0x3ffe
  273. #define pwd_dn_scale(x) ((x) << 1)
  274. /* USB_CSR_DUMMY1 */
  275. #define DYNAMIC_BURST 0x0001
  276. /* USB_CSR_DUMMY2 */
  277. #define EP4_FULL_FC 0x0001
  278. /* USB_DEV_STAT */
  279. #define STAT_SPEED_MASK 0x0006
  280. #define STAT_SPEED_HIGH 0x0000
  281. #define STAT_SPEED_FULL 0x0002
  282. /* USB_TX_AGG */
  283. #define TX_AGG_MAX_THRESHOLD 0x03
  284. /* USB_RX_BUF_TH */
  285. #define RX_THR_SUPPER 0x0c350180
  286. #define RX_THR_HIGH 0x7a120180
  287. #define RX_THR_SLOW 0xffff0180
  288. /* USB_TX_DMA */
  289. #define TEST_MODE_DISABLE 0x00000001
  290. #define TX_SIZE_ADJUST1 0x00000100
  291. /* USB_BMU_RESET */
  292. #define BMU_RESET_EP_IN 0x01
  293. #define BMU_RESET_EP_OUT 0x02
  294. /* USB_UPS_CTRL */
  295. #define POWER_CUT 0x0100
  296. /* USB_PM_CTRL_STATUS */
  297. #define RESUME_INDICATE 0x0001
  298. /* USB_USB_CTRL */
  299. #define RX_AGG_DISABLE 0x0010
  300. #define RX_ZERO_EN 0x0080
  301. /* USB_U2P3_CTRL */
  302. #define U2P3_ENABLE 0x0001
  303. /* USB_POWER_CUT */
  304. #define PWR_EN 0x0001
  305. #define PHASE2_EN 0x0008
  306. /* USB_MISC_0 */
  307. #define PCUT_STATUS 0x0001
  308. /* USB_RX_EARLY_TIMEOUT */
  309. #define COALESCE_SUPER 85000U
  310. #define COALESCE_HIGH 250000U
  311. #define COALESCE_SLOW 524280U
  312. /* USB_WDT11_CTRL */
  313. #define TIMER11_EN 0x0001
  314. /* USB_LPM_CTRL */
  315. /* bit 4 ~ 5: fifo empty boundary */
  316. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  317. /* bit 2 ~ 3: LMP timer */
  318. #define LPM_TIMER_MASK 0x0c
  319. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  320. #define LPM_TIMER_500US 0x0c /* 500 us */
  321. #define ROK_EXIT_LPM 0x02
  322. /* USB_AFE_CTRL2 */
  323. #define SEN_VAL_MASK 0xf800
  324. #define SEN_VAL_NORMAL 0xa000
  325. #define SEL_RXIDLE 0x0100
  326. /* OCP_ALDPS_CONFIG */
  327. #define ENPWRSAVE 0x8000
  328. #define ENPDNPS 0x0200
  329. #define LINKENA 0x0100
  330. #define DIS_SDSAVE 0x0010
  331. /* OCP_PHY_STATUS */
  332. #define PHY_STAT_MASK 0x0007
  333. #define PHY_STAT_LAN_ON 3
  334. #define PHY_STAT_PWRDN 5
  335. /* OCP_POWER_CFG */
  336. #define EEE_CLKDIV_EN 0x8000
  337. #define EN_ALDPS 0x0004
  338. #define EN_10M_PLLOFF 0x0001
  339. /* OCP_EEE_CONFIG1 */
  340. #define RG_TXLPI_MSK_HFDUP 0x8000
  341. #define RG_MATCLR_EN 0x4000
  342. #define EEE_10_CAP 0x2000
  343. #define EEE_NWAY_EN 0x1000
  344. #define TX_QUIET_EN 0x0200
  345. #define RX_QUIET_EN 0x0100
  346. #define sd_rise_time_mask 0x0070
  347. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  348. #define RG_RXLPI_MSK_HFDUP 0x0008
  349. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  350. /* OCP_EEE_CONFIG2 */
  351. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  352. #define RG_DACQUIET_EN 0x0400
  353. #define RG_LDVQUIET_EN 0x0200
  354. #define RG_CKRSEL 0x0020
  355. #define RG_EEEPRG_EN 0x0010
  356. /* OCP_EEE_CONFIG3 */
  357. #define fast_snr_mask 0xff80
  358. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  359. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  360. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  361. /* OCP_EEE_AR */
  362. /* bit[15:14] function */
  363. #define FUN_ADDR 0x0000
  364. #define FUN_DATA 0x4000
  365. /* bit[4:0] device addr */
  366. /* OCP_EEE_CFG */
  367. #define CTAP_SHORT_EN 0x0040
  368. #define EEE10_EN 0x0010
  369. /* OCP_DOWN_SPEED */
  370. #define EN_10M_BGOFF 0x0080
  371. /* OCP_PHY_STATE */
  372. #define TXDIS_STATE 0x01
  373. #define ABD_STATE 0x02
  374. /* OCP_ADC_CFG */
  375. #define CKADSEL_L 0x0100
  376. #define ADC_EN 0x0080
  377. #define EN_EMI_L 0x0040
  378. /* SRAM_LPF_CFG */
  379. #define LPF_AUTO_TUNE 0x8000
  380. /* SRAM_10M_AMP1 */
  381. #define GDAC_IB_UPALL 0x0008
  382. /* SRAM_10M_AMP2 */
  383. #define AMP_DN 0x0200
  384. /* SRAM_IMPEDANCE */
  385. #define RX_DRIVING_MASK 0x6000
  386. /* MAC PASSTHRU */
  387. #define AD_MASK 0xfee0
  388. #define EFUSE 0xcfdb
  389. #define PASS_THRU_MASK 0x1
  390. enum rtl_register_content {
  391. _1000bps = 0x10,
  392. _100bps = 0x08,
  393. _10bps = 0x04,
  394. LINK_STATUS = 0x02,
  395. FULL_DUP = 0x01,
  396. };
  397. #define RTL8152_MAX_TX 4
  398. #define RTL8152_MAX_RX 10
  399. #define INTBUFSIZE 2
  400. #define CRC_SIZE 4
  401. #define TX_ALIGN 4
  402. #define RX_ALIGN 8
  403. #define INTR_LINK 0x0004
  404. #define RTL8152_REQT_READ 0xc0
  405. #define RTL8152_REQT_WRITE 0x40
  406. #define RTL8152_REQ_GET_REGS 0x05
  407. #define RTL8152_REQ_SET_REGS 0x05
  408. #define BYTE_EN_DWORD 0xff
  409. #define BYTE_EN_WORD 0x33
  410. #define BYTE_EN_BYTE 0x11
  411. #define BYTE_EN_SIX_BYTES 0x3f
  412. #define BYTE_EN_START_MASK 0x0f
  413. #define BYTE_EN_END_MASK 0xf0
  414. #define RTL8153_MAX_PACKET 9216 /* 9K */
  415. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  416. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  417. #define RTL8153_RMS RTL8153_MAX_PACKET
  418. #define RTL8152_TX_TIMEOUT (5 * HZ)
  419. #define RTL8152_NAPI_WEIGHT 64
  420. /* rtl8152 flags */
  421. enum rtl8152_flags {
  422. RTL8152_UNPLUG = 0,
  423. RTL8152_SET_RX_MODE,
  424. WORK_ENABLE,
  425. RTL8152_LINK_CHG,
  426. SELECTIVE_SUSPEND,
  427. PHY_RESET,
  428. SCHEDULE_NAPI,
  429. };
  430. /* Define these values to match your device */
  431. #define VENDOR_ID_REALTEK 0x0bda
  432. #define VENDOR_ID_SAMSUNG 0x04e8
  433. #define VENDOR_ID_LENOVO 0x17ef
  434. #define VENDOR_ID_NVIDIA 0x0955
  435. #define MCU_TYPE_PLA 0x0100
  436. #define MCU_TYPE_USB 0x0000
  437. struct tally_counter {
  438. __le64 tx_packets;
  439. __le64 rx_packets;
  440. __le64 tx_errors;
  441. __le32 rx_errors;
  442. __le16 rx_missed;
  443. __le16 align_errors;
  444. __le32 tx_one_collision;
  445. __le32 tx_multi_collision;
  446. __le64 rx_unicast;
  447. __le64 rx_broadcast;
  448. __le32 rx_multicast;
  449. __le16 tx_aborted;
  450. __le16 tx_underrun;
  451. };
  452. struct rx_desc {
  453. __le32 opts1;
  454. #define RX_LEN_MASK 0x7fff
  455. __le32 opts2;
  456. #define RD_UDP_CS BIT(23)
  457. #define RD_TCP_CS BIT(22)
  458. #define RD_IPV6_CS BIT(20)
  459. #define RD_IPV4_CS BIT(19)
  460. __le32 opts3;
  461. #define IPF BIT(23) /* IP checksum fail */
  462. #define UDPF BIT(22) /* UDP checksum fail */
  463. #define TCPF BIT(21) /* TCP checksum fail */
  464. #define RX_VLAN_TAG BIT(16)
  465. __le32 opts4;
  466. __le32 opts5;
  467. __le32 opts6;
  468. };
  469. struct tx_desc {
  470. __le32 opts1;
  471. #define TX_FS BIT(31) /* First segment of a packet */
  472. #define TX_LS BIT(30) /* Final segment of a packet */
  473. #define GTSENDV4 BIT(28)
  474. #define GTSENDV6 BIT(27)
  475. #define GTTCPHO_SHIFT 18
  476. #define GTTCPHO_MAX 0x7fU
  477. #define TX_LEN_MAX 0x3ffffU
  478. __le32 opts2;
  479. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  480. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  481. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  482. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  483. #define MSS_SHIFT 17
  484. #define MSS_MAX 0x7ffU
  485. #define TCPHO_SHIFT 17
  486. #define TCPHO_MAX 0x7ffU
  487. #define TX_VLAN_TAG BIT(16)
  488. };
  489. struct r8152;
  490. struct rx_agg {
  491. struct list_head list;
  492. struct urb *urb;
  493. struct r8152 *context;
  494. void *buffer;
  495. void *head;
  496. };
  497. struct tx_agg {
  498. struct list_head list;
  499. struct urb *urb;
  500. struct r8152 *context;
  501. void *buffer;
  502. void *head;
  503. u32 skb_num;
  504. u32 skb_len;
  505. };
  506. struct r8152 {
  507. unsigned long flags;
  508. struct usb_device *udev;
  509. struct napi_struct napi;
  510. struct usb_interface *intf;
  511. struct net_device *netdev;
  512. struct urb *intr_urb;
  513. struct tx_agg tx_info[RTL8152_MAX_TX];
  514. struct rx_agg rx_info[RTL8152_MAX_RX];
  515. struct list_head rx_done, tx_free;
  516. struct sk_buff_head tx_queue, rx_queue;
  517. spinlock_t rx_lock, tx_lock;
  518. struct delayed_work schedule, hw_phy_work;
  519. struct mii_if_info mii;
  520. struct mutex control; /* use for hw setting */
  521. #ifdef CONFIG_PM_SLEEP
  522. struct notifier_block pm_notifier;
  523. #endif
  524. struct rtl_ops {
  525. void (*init)(struct r8152 *);
  526. int (*enable)(struct r8152 *);
  527. void (*disable)(struct r8152 *);
  528. void (*up)(struct r8152 *);
  529. void (*down)(struct r8152 *);
  530. void (*unload)(struct r8152 *);
  531. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  532. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  533. bool (*in_nway)(struct r8152 *);
  534. void (*hw_phy_cfg)(struct r8152 *);
  535. void (*autosuspend_en)(struct r8152 *tp, bool enable);
  536. } rtl_ops;
  537. int intr_interval;
  538. u32 saved_wolopts;
  539. u32 msg_enable;
  540. u32 tx_qlen;
  541. u32 coalesce;
  542. u16 ocp_base;
  543. u16 speed;
  544. u8 *intr_buff;
  545. u8 version;
  546. u8 duplex;
  547. u8 autoneg;
  548. };
  549. enum rtl_version {
  550. RTL_VER_UNKNOWN = 0,
  551. RTL_VER_01,
  552. RTL_VER_02,
  553. RTL_VER_03,
  554. RTL_VER_04,
  555. RTL_VER_05,
  556. RTL_VER_06,
  557. RTL_VER_MAX
  558. };
  559. enum tx_csum_stat {
  560. TX_CSUM_SUCCESS = 0,
  561. TX_CSUM_TSO,
  562. TX_CSUM_NONE
  563. };
  564. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  565. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  566. */
  567. static const int multicast_filter_limit = 32;
  568. static unsigned int agg_buf_sz = 16384;
  569. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  570. VLAN_ETH_HLEN - VLAN_HLEN)
  571. static
  572. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  573. {
  574. int ret;
  575. void *tmp;
  576. tmp = kmalloc(size, GFP_KERNEL);
  577. if (!tmp)
  578. return -ENOMEM;
  579. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  580. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  581. value, index, tmp, size, 500);
  582. memcpy(data, tmp, size);
  583. kfree(tmp);
  584. return ret;
  585. }
  586. static
  587. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  588. {
  589. int ret;
  590. void *tmp;
  591. tmp = kmemdup(data, size, GFP_KERNEL);
  592. if (!tmp)
  593. return -ENOMEM;
  594. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  595. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  596. value, index, tmp, size, 500);
  597. kfree(tmp);
  598. return ret;
  599. }
  600. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  601. void *data, u16 type)
  602. {
  603. u16 limit = 64;
  604. int ret = 0;
  605. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  606. return -ENODEV;
  607. /* both size and indix must be 4 bytes align */
  608. if ((size & 3) || !size || (index & 3) || !data)
  609. return -EPERM;
  610. if ((u32)index + (u32)size > 0xffff)
  611. return -EPERM;
  612. while (size) {
  613. if (size > limit) {
  614. ret = get_registers(tp, index, type, limit, data);
  615. if (ret < 0)
  616. break;
  617. index += limit;
  618. data += limit;
  619. size -= limit;
  620. } else {
  621. ret = get_registers(tp, index, type, size, data);
  622. if (ret < 0)
  623. break;
  624. index += size;
  625. data += size;
  626. size = 0;
  627. break;
  628. }
  629. }
  630. if (ret == -ENODEV)
  631. set_bit(RTL8152_UNPLUG, &tp->flags);
  632. return ret;
  633. }
  634. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  635. u16 size, void *data, u16 type)
  636. {
  637. int ret;
  638. u16 byteen_start, byteen_end, byen;
  639. u16 limit = 512;
  640. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  641. return -ENODEV;
  642. /* both size and indix must be 4 bytes align */
  643. if ((size & 3) || !size || (index & 3) || !data)
  644. return -EPERM;
  645. if ((u32)index + (u32)size > 0xffff)
  646. return -EPERM;
  647. byteen_start = byteen & BYTE_EN_START_MASK;
  648. byteen_end = byteen & BYTE_EN_END_MASK;
  649. byen = byteen_start | (byteen_start << 4);
  650. ret = set_registers(tp, index, type | byen, 4, data);
  651. if (ret < 0)
  652. goto error1;
  653. index += 4;
  654. data += 4;
  655. size -= 4;
  656. if (size) {
  657. size -= 4;
  658. while (size) {
  659. if (size > limit) {
  660. ret = set_registers(tp, index,
  661. type | BYTE_EN_DWORD,
  662. limit, data);
  663. if (ret < 0)
  664. goto error1;
  665. index += limit;
  666. data += limit;
  667. size -= limit;
  668. } else {
  669. ret = set_registers(tp, index,
  670. type | BYTE_EN_DWORD,
  671. size, data);
  672. if (ret < 0)
  673. goto error1;
  674. index += size;
  675. data += size;
  676. size = 0;
  677. break;
  678. }
  679. }
  680. byen = byteen_end | (byteen_end >> 4);
  681. ret = set_registers(tp, index, type | byen, 4, data);
  682. if (ret < 0)
  683. goto error1;
  684. }
  685. error1:
  686. if (ret == -ENODEV)
  687. set_bit(RTL8152_UNPLUG, &tp->flags);
  688. return ret;
  689. }
  690. static inline
  691. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  692. {
  693. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  694. }
  695. static inline
  696. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  697. {
  698. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  699. }
  700. static inline
  701. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  702. {
  703. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  704. }
  705. static inline
  706. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  707. {
  708. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  709. }
  710. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  711. {
  712. __le32 data;
  713. generic_ocp_read(tp, index, sizeof(data), &data, type);
  714. return __le32_to_cpu(data);
  715. }
  716. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  717. {
  718. __le32 tmp = __cpu_to_le32(data);
  719. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  720. }
  721. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  722. {
  723. u32 data;
  724. __le32 tmp;
  725. u8 shift = index & 2;
  726. index &= ~3;
  727. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  728. data = __le32_to_cpu(tmp);
  729. data >>= (shift * 8);
  730. data &= 0xffff;
  731. return (u16)data;
  732. }
  733. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  734. {
  735. u32 mask = 0xffff;
  736. __le32 tmp;
  737. u16 byen = BYTE_EN_WORD;
  738. u8 shift = index & 2;
  739. data &= mask;
  740. if (index & 2) {
  741. byen <<= shift;
  742. mask <<= (shift * 8);
  743. data <<= (shift * 8);
  744. index &= ~3;
  745. }
  746. tmp = __cpu_to_le32(data);
  747. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  748. }
  749. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  750. {
  751. u32 data;
  752. __le32 tmp;
  753. u8 shift = index & 3;
  754. index &= ~3;
  755. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  756. data = __le32_to_cpu(tmp);
  757. data >>= (shift * 8);
  758. data &= 0xff;
  759. return (u8)data;
  760. }
  761. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  762. {
  763. u32 mask = 0xff;
  764. __le32 tmp;
  765. u16 byen = BYTE_EN_BYTE;
  766. u8 shift = index & 3;
  767. data &= mask;
  768. if (index & 3) {
  769. byen <<= shift;
  770. mask <<= (shift * 8);
  771. data <<= (shift * 8);
  772. index &= ~3;
  773. }
  774. tmp = __cpu_to_le32(data);
  775. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  776. }
  777. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  778. {
  779. u16 ocp_base, ocp_index;
  780. ocp_base = addr & 0xf000;
  781. if (ocp_base != tp->ocp_base) {
  782. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  783. tp->ocp_base = ocp_base;
  784. }
  785. ocp_index = (addr & 0x0fff) | 0xb000;
  786. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  787. }
  788. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  789. {
  790. u16 ocp_base, ocp_index;
  791. ocp_base = addr & 0xf000;
  792. if (ocp_base != tp->ocp_base) {
  793. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  794. tp->ocp_base = ocp_base;
  795. }
  796. ocp_index = (addr & 0x0fff) | 0xb000;
  797. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  798. }
  799. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  800. {
  801. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  802. }
  803. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  804. {
  805. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  806. }
  807. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  808. {
  809. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  810. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  811. }
  812. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  813. {
  814. struct r8152 *tp = netdev_priv(netdev);
  815. int ret;
  816. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  817. return -ENODEV;
  818. if (phy_id != R8152_PHY_ID)
  819. return -EINVAL;
  820. ret = r8152_mdio_read(tp, reg);
  821. return ret;
  822. }
  823. static
  824. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  825. {
  826. struct r8152 *tp = netdev_priv(netdev);
  827. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  828. return;
  829. if (phy_id != R8152_PHY_ID)
  830. return;
  831. r8152_mdio_write(tp, reg, val);
  832. }
  833. static int
  834. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  835. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  836. {
  837. struct r8152 *tp = netdev_priv(netdev);
  838. struct sockaddr *addr = p;
  839. int ret = -EADDRNOTAVAIL;
  840. if (!is_valid_ether_addr(addr->sa_data))
  841. goto out1;
  842. ret = usb_autopm_get_interface(tp->intf);
  843. if (ret < 0)
  844. goto out1;
  845. mutex_lock(&tp->control);
  846. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  847. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  848. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  849. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  850. mutex_unlock(&tp->control);
  851. usb_autopm_put_interface(tp->intf);
  852. out1:
  853. return ret;
  854. }
  855. /* Devices containing RTL8153-AD can support a persistent
  856. * host system provided MAC address.
  857. * Examples of this are Dell TB15 and Dell WD15 docks
  858. */
  859. static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
  860. {
  861. acpi_status status;
  862. struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
  863. union acpi_object *obj;
  864. int ret = -EINVAL;
  865. u32 ocp_data;
  866. unsigned char buf[6];
  867. /* test for -AD variant of RTL8153 */
  868. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  869. if ((ocp_data & AD_MASK) != 0x1000)
  870. return -ENODEV;
  871. /* test for MAC address pass-through bit */
  872. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
  873. if ((ocp_data & PASS_THRU_MASK) != 1)
  874. return -ENODEV;
  875. /* returns _AUXMAC_#AABBCCDDEEFF# */
  876. status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
  877. obj = (union acpi_object *)buffer.pointer;
  878. if (!ACPI_SUCCESS(status))
  879. return -ENODEV;
  880. if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
  881. netif_warn(tp, probe, tp->netdev,
  882. "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
  883. obj->type, obj->string.length);
  884. goto amacout;
  885. }
  886. if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
  887. strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
  888. netif_warn(tp, probe, tp->netdev,
  889. "Invalid header when reading pass-thru MAC addr\n");
  890. goto amacout;
  891. }
  892. ret = hex2bin(buf, obj->string.pointer + 9, 6);
  893. if (!(ret == 0 && is_valid_ether_addr(buf))) {
  894. netif_warn(tp, probe, tp->netdev,
  895. "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
  896. ret, buf);
  897. ret = -EINVAL;
  898. goto amacout;
  899. }
  900. memcpy(sa->sa_data, buf, 6);
  901. ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
  902. netif_info(tp, probe, tp->netdev,
  903. "Using pass-thru MAC addr %pM\n", sa->sa_data);
  904. amacout:
  905. kfree(obj);
  906. return ret;
  907. }
  908. static int set_ethernet_addr(struct r8152 *tp)
  909. {
  910. struct net_device *dev = tp->netdev;
  911. struct sockaddr sa;
  912. int ret;
  913. if (tp->version == RTL_VER_01) {
  914. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  915. } else {
  916. /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
  917. * or system doesn't provide valid _SB.AMAC this will be
  918. * be expected to non-zero
  919. */
  920. ret = vendor_mac_passthru_addr_read(tp, &sa);
  921. if (ret < 0)
  922. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  923. }
  924. if (ret < 0) {
  925. netif_err(tp, probe, dev, "Get ether addr fail\n");
  926. } else if (!is_valid_ether_addr(sa.sa_data)) {
  927. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  928. sa.sa_data);
  929. eth_hw_addr_random(dev);
  930. ether_addr_copy(sa.sa_data, dev->dev_addr);
  931. ret = rtl8152_set_mac_address(dev, &sa);
  932. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  933. sa.sa_data);
  934. } else {
  935. if (tp->version == RTL_VER_01)
  936. ether_addr_copy(dev->dev_addr, sa.sa_data);
  937. else
  938. ret = rtl8152_set_mac_address(dev, &sa);
  939. }
  940. return ret;
  941. }
  942. static void read_bulk_callback(struct urb *urb)
  943. {
  944. struct net_device *netdev;
  945. int status = urb->status;
  946. struct rx_agg *agg;
  947. struct r8152 *tp;
  948. agg = urb->context;
  949. if (!agg)
  950. return;
  951. tp = agg->context;
  952. if (!tp)
  953. return;
  954. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  955. return;
  956. if (!test_bit(WORK_ENABLE, &tp->flags))
  957. return;
  958. netdev = tp->netdev;
  959. /* When link down, the driver would cancel all bulks. */
  960. /* This avoid the re-submitting bulk */
  961. if (!netif_carrier_ok(netdev))
  962. return;
  963. usb_mark_last_busy(tp->udev);
  964. switch (status) {
  965. case 0:
  966. if (urb->actual_length < ETH_ZLEN)
  967. break;
  968. spin_lock(&tp->rx_lock);
  969. list_add_tail(&agg->list, &tp->rx_done);
  970. spin_unlock(&tp->rx_lock);
  971. napi_schedule(&tp->napi);
  972. return;
  973. case -ESHUTDOWN:
  974. set_bit(RTL8152_UNPLUG, &tp->flags);
  975. netif_device_detach(tp->netdev);
  976. return;
  977. case -ENOENT:
  978. return; /* the urb is in unlink state */
  979. case -ETIME:
  980. if (net_ratelimit())
  981. netdev_warn(netdev, "maybe reset is needed?\n");
  982. break;
  983. default:
  984. if (net_ratelimit())
  985. netdev_warn(netdev, "Rx status %d\n", status);
  986. break;
  987. }
  988. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  989. }
  990. static void write_bulk_callback(struct urb *urb)
  991. {
  992. struct net_device_stats *stats;
  993. struct net_device *netdev;
  994. struct tx_agg *agg;
  995. struct r8152 *tp;
  996. int status = urb->status;
  997. agg = urb->context;
  998. if (!agg)
  999. return;
  1000. tp = agg->context;
  1001. if (!tp)
  1002. return;
  1003. netdev = tp->netdev;
  1004. stats = &netdev->stats;
  1005. if (status) {
  1006. if (net_ratelimit())
  1007. netdev_warn(netdev, "Tx status %d\n", status);
  1008. stats->tx_errors += agg->skb_num;
  1009. } else {
  1010. stats->tx_packets += agg->skb_num;
  1011. stats->tx_bytes += agg->skb_len;
  1012. }
  1013. spin_lock(&tp->tx_lock);
  1014. list_add_tail(&agg->list, &tp->tx_free);
  1015. spin_unlock(&tp->tx_lock);
  1016. usb_autopm_put_interface_async(tp->intf);
  1017. if (!netif_carrier_ok(netdev))
  1018. return;
  1019. if (!test_bit(WORK_ENABLE, &tp->flags))
  1020. return;
  1021. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1022. return;
  1023. if (!skb_queue_empty(&tp->tx_queue))
  1024. napi_schedule(&tp->napi);
  1025. }
  1026. static void intr_callback(struct urb *urb)
  1027. {
  1028. struct r8152 *tp;
  1029. __le16 *d;
  1030. int status = urb->status;
  1031. int res;
  1032. tp = urb->context;
  1033. if (!tp)
  1034. return;
  1035. if (!test_bit(WORK_ENABLE, &tp->flags))
  1036. return;
  1037. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1038. return;
  1039. switch (status) {
  1040. case 0: /* success */
  1041. break;
  1042. case -ECONNRESET: /* unlink */
  1043. case -ESHUTDOWN:
  1044. netif_device_detach(tp->netdev);
  1045. case -ENOENT:
  1046. case -EPROTO:
  1047. netif_info(tp, intr, tp->netdev,
  1048. "Stop submitting intr, status %d\n", status);
  1049. return;
  1050. case -EOVERFLOW:
  1051. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  1052. goto resubmit;
  1053. /* -EPIPE: should clear the halt */
  1054. default:
  1055. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  1056. goto resubmit;
  1057. }
  1058. d = urb->transfer_buffer;
  1059. if (INTR_LINK & __le16_to_cpu(d[0])) {
  1060. if (!netif_carrier_ok(tp->netdev)) {
  1061. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1062. schedule_delayed_work(&tp->schedule, 0);
  1063. }
  1064. } else {
  1065. if (netif_carrier_ok(tp->netdev)) {
  1066. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1067. schedule_delayed_work(&tp->schedule, 0);
  1068. }
  1069. }
  1070. resubmit:
  1071. res = usb_submit_urb(urb, GFP_ATOMIC);
  1072. if (res == -ENODEV) {
  1073. set_bit(RTL8152_UNPLUG, &tp->flags);
  1074. netif_device_detach(tp->netdev);
  1075. } else if (res) {
  1076. netif_err(tp, intr, tp->netdev,
  1077. "can't resubmit intr, status %d\n", res);
  1078. }
  1079. }
  1080. static inline void *rx_agg_align(void *data)
  1081. {
  1082. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  1083. }
  1084. static inline void *tx_agg_align(void *data)
  1085. {
  1086. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  1087. }
  1088. static void free_all_mem(struct r8152 *tp)
  1089. {
  1090. int i;
  1091. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1092. usb_free_urb(tp->rx_info[i].urb);
  1093. tp->rx_info[i].urb = NULL;
  1094. kfree(tp->rx_info[i].buffer);
  1095. tp->rx_info[i].buffer = NULL;
  1096. tp->rx_info[i].head = NULL;
  1097. }
  1098. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1099. usb_free_urb(tp->tx_info[i].urb);
  1100. tp->tx_info[i].urb = NULL;
  1101. kfree(tp->tx_info[i].buffer);
  1102. tp->tx_info[i].buffer = NULL;
  1103. tp->tx_info[i].head = NULL;
  1104. }
  1105. usb_free_urb(tp->intr_urb);
  1106. tp->intr_urb = NULL;
  1107. kfree(tp->intr_buff);
  1108. tp->intr_buff = NULL;
  1109. }
  1110. static int alloc_all_mem(struct r8152 *tp)
  1111. {
  1112. struct net_device *netdev = tp->netdev;
  1113. struct usb_interface *intf = tp->intf;
  1114. struct usb_host_interface *alt = intf->cur_altsetting;
  1115. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1116. struct urb *urb;
  1117. int node, i;
  1118. u8 *buf;
  1119. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1120. spin_lock_init(&tp->rx_lock);
  1121. spin_lock_init(&tp->tx_lock);
  1122. INIT_LIST_HEAD(&tp->tx_free);
  1123. skb_queue_head_init(&tp->tx_queue);
  1124. skb_queue_head_init(&tp->rx_queue);
  1125. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1126. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1127. if (!buf)
  1128. goto err1;
  1129. if (buf != rx_agg_align(buf)) {
  1130. kfree(buf);
  1131. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1132. node);
  1133. if (!buf)
  1134. goto err1;
  1135. }
  1136. urb = usb_alloc_urb(0, GFP_KERNEL);
  1137. if (!urb) {
  1138. kfree(buf);
  1139. goto err1;
  1140. }
  1141. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1142. tp->rx_info[i].context = tp;
  1143. tp->rx_info[i].urb = urb;
  1144. tp->rx_info[i].buffer = buf;
  1145. tp->rx_info[i].head = rx_agg_align(buf);
  1146. }
  1147. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1148. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1149. if (!buf)
  1150. goto err1;
  1151. if (buf != tx_agg_align(buf)) {
  1152. kfree(buf);
  1153. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1154. node);
  1155. if (!buf)
  1156. goto err1;
  1157. }
  1158. urb = usb_alloc_urb(0, GFP_KERNEL);
  1159. if (!urb) {
  1160. kfree(buf);
  1161. goto err1;
  1162. }
  1163. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1164. tp->tx_info[i].context = tp;
  1165. tp->tx_info[i].urb = urb;
  1166. tp->tx_info[i].buffer = buf;
  1167. tp->tx_info[i].head = tx_agg_align(buf);
  1168. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1169. }
  1170. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1171. if (!tp->intr_urb)
  1172. goto err1;
  1173. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1174. if (!tp->intr_buff)
  1175. goto err1;
  1176. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1177. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1178. tp->intr_buff, INTBUFSIZE, intr_callback,
  1179. tp, tp->intr_interval);
  1180. return 0;
  1181. err1:
  1182. free_all_mem(tp);
  1183. return -ENOMEM;
  1184. }
  1185. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1186. {
  1187. struct tx_agg *agg = NULL;
  1188. unsigned long flags;
  1189. if (list_empty(&tp->tx_free))
  1190. return NULL;
  1191. spin_lock_irqsave(&tp->tx_lock, flags);
  1192. if (!list_empty(&tp->tx_free)) {
  1193. struct list_head *cursor;
  1194. cursor = tp->tx_free.next;
  1195. list_del_init(cursor);
  1196. agg = list_entry(cursor, struct tx_agg, list);
  1197. }
  1198. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1199. return agg;
  1200. }
  1201. /* r8152_csum_workaround()
  1202. * The hw limites the value the transport offset. When the offset is out of the
  1203. * range, calculate the checksum by sw.
  1204. */
  1205. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1206. struct sk_buff_head *list)
  1207. {
  1208. if (skb_shinfo(skb)->gso_size) {
  1209. netdev_features_t features = tp->netdev->features;
  1210. struct sk_buff_head seg_list;
  1211. struct sk_buff *segs, *nskb;
  1212. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1213. segs = skb_gso_segment(skb, features);
  1214. if (IS_ERR(segs) || !segs)
  1215. goto drop;
  1216. __skb_queue_head_init(&seg_list);
  1217. do {
  1218. nskb = segs;
  1219. segs = segs->next;
  1220. nskb->next = NULL;
  1221. __skb_queue_tail(&seg_list, nskb);
  1222. } while (segs);
  1223. skb_queue_splice(&seg_list, list);
  1224. dev_kfree_skb(skb);
  1225. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1226. if (skb_checksum_help(skb) < 0)
  1227. goto drop;
  1228. __skb_queue_head(list, skb);
  1229. } else {
  1230. struct net_device_stats *stats;
  1231. drop:
  1232. stats = &tp->netdev->stats;
  1233. stats->tx_dropped++;
  1234. dev_kfree_skb(skb);
  1235. }
  1236. }
  1237. /* msdn_giant_send_check()
  1238. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1239. * packet length for IPv6 TCP large packets.
  1240. */
  1241. static int msdn_giant_send_check(struct sk_buff *skb)
  1242. {
  1243. const struct ipv6hdr *ipv6h;
  1244. struct tcphdr *th;
  1245. int ret;
  1246. ret = skb_cow_head(skb, 0);
  1247. if (ret)
  1248. return ret;
  1249. ipv6h = ipv6_hdr(skb);
  1250. th = tcp_hdr(skb);
  1251. th->check = 0;
  1252. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1253. return ret;
  1254. }
  1255. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1256. {
  1257. if (skb_vlan_tag_present(skb)) {
  1258. u32 opts2;
  1259. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1260. desc->opts2 |= cpu_to_le32(opts2);
  1261. }
  1262. }
  1263. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1264. {
  1265. u32 opts2 = le32_to_cpu(desc->opts2);
  1266. if (opts2 & RX_VLAN_TAG)
  1267. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1268. swab16(opts2 & 0xffff));
  1269. }
  1270. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1271. struct sk_buff *skb, u32 len, u32 transport_offset)
  1272. {
  1273. u32 mss = skb_shinfo(skb)->gso_size;
  1274. u32 opts1, opts2 = 0;
  1275. int ret = TX_CSUM_SUCCESS;
  1276. WARN_ON_ONCE(len > TX_LEN_MAX);
  1277. opts1 = len | TX_FS | TX_LS;
  1278. if (mss) {
  1279. if (transport_offset > GTTCPHO_MAX) {
  1280. netif_warn(tp, tx_err, tp->netdev,
  1281. "Invalid transport offset 0x%x for TSO\n",
  1282. transport_offset);
  1283. ret = TX_CSUM_TSO;
  1284. goto unavailable;
  1285. }
  1286. switch (vlan_get_protocol(skb)) {
  1287. case htons(ETH_P_IP):
  1288. opts1 |= GTSENDV4;
  1289. break;
  1290. case htons(ETH_P_IPV6):
  1291. if (msdn_giant_send_check(skb)) {
  1292. ret = TX_CSUM_TSO;
  1293. goto unavailable;
  1294. }
  1295. opts1 |= GTSENDV6;
  1296. break;
  1297. default:
  1298. WARN_ON_ONCE(1);
  1299. break;
  1300. }
  1301. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1302. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1303. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1304. u8 ip_protocol;
  1305. if (transport_offset > TCPHO_MAX) {
  1306. netif_warn(tp, tx_err, tp->netdev,
  1307. "Invalid transport offset 0x%x\n",
  1308. transport_offset);
  1309. ret = TX_CSUM_NONE;
  1310. goto unavailable;
  1311. }
  1312. switch (vlan_get_protocol(skb)) {
  1313. case htons(ETH_P_IP):
  1314. opts2 |= IPV4_CS;
  1315. ip_protocol = ip_hdr(skb)->protocol;
  1316. break;
  1317. case htons(ETH_P_IPV6):
  1318. opts2 |= IPV6_CS;
  1319. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1320. break;
  1321. default:
  1322. ip_protocol = IPPROTO_RAW;
  1323. break;
  1324. }
  1325. if (ip_protocol == IPPROTO_TCP)
  1326. opts2 |= TCP_CS;
  1327. else if (ip_protocol == IPPROTO_UDP)
  1328. opts2 |= UDP_CS;
  1329. else
  1330. WARN_ON_ONCE(1);
  1331. opts2 |= transport_offset << TCPHO_SHIFT;
  1332. }
  1333. desc->opts2 = cpu_to_le32(opts2);
  1334. desc->opts1 = cpu_to_le32(opts1);
  1335. unavailable:
  1336. return ret;
  1337. }
  1338. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1339. {
  1340. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1341. int remain, ret;
  1342. u8 *tx_data;
  1343. __skb_queue_head_init(&skb_head);
  1344. spin_lock(&tx_queue->lock);
  1345. skb_queue_splice_init(tx_queue, &skb_head);
  1346. spin_unlock(&tx_queue->lock);
  1347. tx_data = agg->head;
  1348. agg->skb_num = 0;
  1349. agg->skb_len = 0;
  1350. remain = agg_buf_sz;
  1351. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1352. struct tx_desc *tx_desc;
  1353. struct sk_buff *skb;
  1354. unsigned int len;
  1355. u32 offset;
  1356. skb = __skb_dequeue(&skb_head);
  1357. if (!skb)
  1358. break;
  1359. len = skb->len + sizeof(*tx_desc);
  1360. if (len > remain) {
  1361. __skb_queue_head(&skb_head, skb);
  1362. break;
  1363. }
  1364. tx_data = tx_agg_align(tx_data);
  1365. tx_desc = (struct tx_desc *)tx_data;
  1366. offset = (u32)skb_transport_offset(skb);
  1367. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1368. r8152_csum_workaround(tp, skb, &skb_head);
  1369. continue;
  1370. }
  1371. rtl_tx_vlan_tag(tx_desc, skb);
  1372. tx_data += sizeof(*tx_desc);
  1373. len = skb->len;
  1374. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1375. struct net_device_stats *stats = &tp->netdev->stats;
  1376. stats->tx_dropped++;
  1377. dev_kfree_skb_any(skb);
  1378. tx_data -= sizeof(*tx_desc);
  1379. continue;
  1380. }
  1381. tx_data += len;
  1382. agg->skb_len += len;
  1383. agg->skb_num++;
  1384. dev_kfree_skb_any(skb);
  1385. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1386. }
  1387. if (!skb_queue_empty(&skb_head)) {
  1388. spin_lock(&tx_queue->lock);
  1389. skb_queue_splice(&skb_head, tx_queue);
  1390. spin_unlock(&tx_queue->lock);
  1391. }
  1392. netif_tx_lock(tp->netdev);
  1393. if (netif_queue_stopped(tp->netdev) &&
  1394. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1395. netif_wake_queue(tp->netdev);
  1396. netif_tx_unlock(tp->netdev);
  1397. ret = usb_autopm_get_interface_async(tp->intf);
  1398. if (ret < 0)
  1399. goto out_tx_fill;
  1400. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1401. agg->head, (int)(tx_data - (u8 *)agg->head),
  1402. (usb_complete_t)write_bulk_callback, agg);
  1403. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1404. if (ret < 0)
  1405. usb_autopm_put_interface_async(tp->intf);
  1406. out_tx_fill:
  1407. return ret;
  1408. }
  1409. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1410. {
  1411. u8 checksum = CHECKSUM_NONE;
  1412. u32 opts2, opts3;
  1413. if (!(tp->netdev->features & NETIF_F_RXCSUM))
  1414. goto return_result;
  1415. opts2 = le32_to_cpu(rx_desc->opts2);
  1416. opts3 = le32_to_cpu(rx_desc->opts3);
  1417. if (opts2 & RD_IPV4_CS) {
  1418. if (opts3 & IPF)
  1419. checksum = CHECKSUM_NONE;
  1420. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1421. checksum = CHECKSUM_NONE;
  1422. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1423. checksum = CHECKSUM_NONE;
  1424. else
  1425. checksum = CHECKSUM_UNNECESSARY;
  1426. } else if (opts2 & RD_IPV6_CS) {
  1427. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1428. checksum = CHECKSUM_UNNECESSARY;
  1429. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1430. checksum = CHECKSUM_UNNECESSARY;
  1431. }
  1432. return_result:
  1433. return checksum;
  1434. }
  1435. static int rx_bottom(struct r8152 *tp, int budget)
  1436. {
  1437. unsigned long flags;
  1438. struct list_head *cursor, *next, rx_queue;
  1439. int ret = 0, work_done = 0;
  1440. if (!skb_queue_empty(&tp->rx_queue)) {
  1441. while (work_done < budget) {
  1442. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1443. struct net_device *netdev = tp->netdev;
  1444. struct net_device_stats *stats = &netdev->stats;
  1445. unsigned int pkt_len;
  1446. if (!skb)
  1447. break;
  1448. pkt_len = skb->len;
  1449. napi_gro_receive(&tp->napi, skb);
  1450. work_done++;
  1451. stats->rx_packets++;
  1452. stats->rx_bytes += pkt_len;
  1453. }
  1454. }
  1455. if (list_empty(&tp->rx_done))
  1456. goto out1;
  1457. INIT_LIST_HEAD(&rx_queue);
  1458. spin_lock_irqsave(&tp->rx_lock, flags);
  1459. list_splice_init(&tp->rx_done, &rx_queue);
  1460. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1461. list_for_each_safe(cursor, next, &rx_queue) {
  1462. struct rx_desc *rx_desc;
  1463. struct rx_agg *agg;
  1464. int len_used = 0;
  1465. struct urb *urb;
  1466. u8 *rx_data;
  1467. list_del_init(cursor);
  1468. agg = list_entry(cursor, struct rx_agg, list);
  1469. urb = agg->urb;
  1470. if (urb->actual_length < ETH_ZLEN)
  1471. goto submit;
  1472. rx_desc = agg->head;
  1473. rx_data = agg->head;
  1474. len_used += sizeof(struct rx_desc);
  1475. while (urb->actual_length > len_used) {
  1476. struct net_device *netdev = tp->netdev;
  1477. struct net_device_stats *stats = &netdev->stats;
  1478. unsigned int pkt_len;
  1479. struct sk_buff *skb;
  1480. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1481. if (pkt_len < ETH_ZLEN)
  1482. break;
  1483. len_used += pkt_len;
  1484. if (urb->actual_length < len_used)
  1485. break;
  1486. pkt_len -= CRC_SIZE;
  1487. rx_data += sizeof(struct rx_desc);
  1488. skb = napi_alloc_skb(&tp->napi, pkt_len);
  1489. if (!skb) {
  1490. stats->rx_dropped++;
  1491. goto find_next_rx;
  1492. }
  1493. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1494. memcpy(skb->data, rx_data, pkt_len);
  1495. skb_put(skb, pkt_len);
  1496. skb->protocol = eth_type_trans(skb, netdev);
  1497. rtl_rx_vlan_tag(rx_desc, skb);
  1498. if (work_done < budget) {
  1499. napi_gro_receive(&tp->napi, skb);
  1500. work_done++;
  1501. stats->rx_packets++;
  1502. stats->rx_bytes += pkt_len;
  1503. } else {
  1504. __skb_queue_tail(&tp->rx_queue, skb);
  1505. }
  1506. find_next_rx:
  1507. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1508. rx_desc = (struct rx_desc *)rx_data;
  1509. len_used = (int)(rx_data - (u8 *)agg->head);
  1510. len_used += sizeof(struct rx_desc);
  1511. }
  1512. submit:
  1513. if (!ret) {
  1514. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1515. } else {
  1516. urb->actual_length = 0;
  1517. list_add_tail(&agg->list, next);
  1518. }
  1519. }
  1520. if (!list_empty(&rx_queue)) {
  1521. spin_lock_irqsave(&tp->rx_lock, flags);
  1522. list_splice_tail(&rx_queue, &tp->rx_done);
  1523. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1524. }
  1525. out1:
  1526. return work_done;
  1527. }
  1528. static void tx_bottom(struct r8152 *tp)
  1529. {
  1530. int res;
  1531. do {
  1532. struct tx_agg *agg;
  1533. if (skb_queue_empty(&tp->tx_queue))
  1534. break;
  1535. agg = r8152_get_tx_agg(tp);
  1536. if (!agg)
  1537. break;
  1538. res = r8152_tx_agg_fill(tp, agg);
  1539. if (res) {
  1540. struct net_device *netdev = tp->netdev;
  1541. if (res == -ENODEV) {
  1542. set_bit(RTL8152_UNPLUG, &tp->flags);
  1543. netif_device_detach(netdev);
  1544. } else {
  1545. struct net_device_stats *stats = &netdev->stats;
  1546. unsigned long flags;
  1547. netif_warn(tp, tx_err, netdev,
  1548. "failed tx_urb %d\n", res);
  1549. stats->tx_dropped += agg->skb_num;
  1550. spin_lock_irqsave(&tp->tx_lock, flags);
  1551. list_add_tail(&agg->list, &tp->tx_free);
  1552. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1553. }
  1554. }
  1555. } while (res == 0);
  1556. }
  1557. static void bottom_half(struct r8152 *tp)
  1558. {
  1559. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1560. return;
  1561. if (!test_bit(WORK_ENABLE, &tp->flags))
  1562. return;
  1563. /* When link down, the driver would cancel all bulks. */
  1564. /* This avoid the re-submitting bulk */
  1565. if (!netif_carrier_ok(tp->netdev))
  1566. return;
  1567. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1568. tx_bottom(tp);
  1569. }
  1570. static int r8152_poll(struct napi_struct *napi, int budget)
  1571. {
  1572. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1573. int work_done;
  1574. work_done = rx_bottom(tp, budget);
  1575. bottom_half(tp);
  1576. if (work_done < budget) {
  1577. napi_complete(napi);
  1578. if (!list_empty(&tp->rx_done))
  1579. napi_schedule(napi);
  1580. else if (!skb_queue_empty(&tp->tx_queue) &&
  1581. !list_empty(&tp->tx_free))
  1582. napi_schedule(napi);
  1583. }
  1584. return work_done;
  1585. }
  1586. static
  1587. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1588. {
  1589. int ret;
  1590. /* The rx would be stopped, so skip submitting */
  1591. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1592. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1593. return 0;
  1594. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1595. agg->head, agg_buf_sz,
  1596. (usb_complete_t)read_bulk_callback, agg);
  1597. ret = usb_submit_urb(agg->urb, mem_flags);
  1598. if (ret == -ENODEV) {
  1599. set_bit(RTL8152_UNPLUG, &tp->flags);
  1600. netif_device_detach(tp->netdev);
  1601. } else if (ret) {
  1602. struct urb *urb = agg->urb;
  1603. unsigned long flags;
  1604. urb->actual_length = 0;
  1605. spin_lock_irqsave(&tp->rx_lock, flags);
  1606. list_add_tail(&agg->list, &tp->rx_done);
  1607. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1608. netif_err(tp, rx_err, tp->netdev,
  1609. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1610. napi_schedule(&tp->napi);
  1611. }
  1612. return ret;
  1613. }
  1614. static void rtl_drop_queued_tx(struct r8152 *tp)
  1615. {
  1616. struct net_device_stats *stats = &tp->netdev->stats;
  1617. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1618. struct sk_buff *skb;
  1619. if (skb_queue_empty(tx_queue))
  1620. return;
  1621. __skb_queue_head_init(&skb_head);
  1622. spin_lock_bh(&tx_queue->lock);
  1623. skb_queue_splice_init(tx_queue, &skb_head);
  1624. spin_unlock_bh(&tx_queue->lock);
  1625. while ((skb = __skb_dequeue(&skb_head))) {
  1626. dev_kfree_skb(skb);
  1627. stats->tx_dropped++;
  1628. }
  1629. }
  1630. static void rtl8152_tx_timeout(struct net_device *netdev)
  1631. {
  1632. struct r8152 *tp = netdev_priv(netdev);
  1633. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1634. usb_queue_reset_device(tp->intf);
  1635. }
  1636. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1637. {
  1638. struct r8152 *tp = netdev_priv(netdev);
  1639. if (netif_carrier_ok(netdev)) {
  1640. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1641. schedule_delayed_work(&tp->schedule, 0);
  1642. }
  1643. }
  1644. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1645. {
  1646. struct r8152 *tp = netdev_priv(netdev);
  1647. u32 mc_filter[2]; /* Multicast hash filter */
  1648. __le32 tmp[2];
  1649. u32 ocp_data;
  1650. netif_stop_queue(netdev);
  1651. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1652. ocp_data &= ~RCR_ACPT_ALL;
  1653. ocp_data |= RCR_AB | RCR_APM;
  1654. if (netdev->flags & IFF_PROMISC) {
  1655. /* Unconditionally log net taps. */
  1656. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1657. ocp_data |= RCR_AM | RCR_AAP;
  1658. mc_filter[1] = 0xffffffff;
  1659. mc_filter[0] = 0xffffffff;
  1660. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1661. (netdev->flags & IFF_ALLMULTI)) {
  1662. /* Too many to filter perfectly -- accept all multicasts. */
  1663. ocp_data |= RCR_AM;
  1664. mc_filter[1] = 0xffffffff;
  1665. mc_filter[0] = 0xffffffff;
  1666. } else {
  1667. struct netdev_hw_addr *ha;
  1668. mc_filter[1] = 0;
  1669. mc_filter[0] = 0;
  1670. netdev_for_each_mc_addr(ha, netdev) {
  1671. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1672. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1673. ocp_data |= RCR_AM;
  1674. }
  1675. }
  1676. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1677. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1678. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1679. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1680. netif_wake_queue(netdev);
  1681. }
  1682. static netdev_features_t
  1683. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1684. netdev_features_t features)
  1685. {
  1686. u32 mss = skb_shinfo(skb)->gso_size;
  1687. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1688. int offset = skb_transport_offset(skb);
  1689. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1690. features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
  1691. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1692. features &= ~NETIF_F_GSO_MASK;
  1693. return features;
  1694. }
  1695. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1696. struct net_device *netdev)
  1697. {
  1698. struct r8152 *tp = netdev_priv(netdev);
  1699. skb_tx_timestamp(skb);
  1700. skb_queue_tail(&tp->tx_queue, skb);
  1701. if (!list_empty(&tp->tx_free)) {
  1702. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1703. set_bit(SCHEDULE_NAPI, &tp->flags);
  1704. schedule_delayed_work(&tp->schedule, 0);
  1705. } else {
  1706. usb_mark_last_busy(tp->udev);
  1707. napi_schedule(&tp->napi);
  1708. }
  1709. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1710. netif_stop_queue(netdev);
  1711. }
  1712. return NETDEV_TX_OK;
  1713. }
  1714. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1715. {
  1716. u32 ocp_data;
  1717. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1718. ocp_data &= ~FMC_FCR_MCU_EN;
  1719. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1720. ocp_data |= FMC_FCR_MCU_EN;
  1721. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1722. }
  1723. static void rtl8152_nic_reset(struct r8152 *tp)
  1724. {
  1725. int i;
  1726. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1727. for (i = 0; i < 1000; i++) {
  1728. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1729. break;
  1730. usleep_range(100, 400);
  1731. }
  1732. }
  1733. static void set_tx_qlen(struct r8152 *tp)
  1734. {
  1735. struct net_device *netdev = tp->netdev;
  1736. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1737. sizeof(struct tx_desc));
  1738. }
  1739. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1740. {
  1741. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1742. }
  1743. static void rtl_set_eee_plus(struct r8152 *tp)
  1744. {
  1745. u32 ocp_data;
  1746. u8 speed;
  1747. speed = rtl8152_get_speed(tp);
  1748. if (speed & _10bps) {
  1749. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1750. ocp_data |= EEEP_CR_EEEP_TX;
  1751. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1752. } else {
  1753. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1754. ocp_data &= ~EEEP_CR_EEEP_TX;
  1755. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1756. }
  1757. }
  1758. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1759. {
  1760. u32 ocp_data;
  1761. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1762. if (enable)
  1763. ocp_data |= RXDY_GATED_EN;
  1764. else
  1765. ocp_data &= ~RXDY_GATED_EN;
  1766. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1767. }
  1768. static int rtl_start_rx(struct r8152 *tp)
  1769. {
  1770. int i, ret = 0;
  1771. INIT_LIST_HEAD(&tp->rx_done);
  1772. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1773. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1774. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1775. if (ret)
  1776. break;
  1777. }
  1778. if (ret && ++i < RTL8152_MAX_RX) {
  1779. struct list_head rx_queue;
  1780. unsigned long flags;
  1781. INIT_LIST_HEAD(&rx_queue);
  1782. do {
  1783. struct rx_agg *agg = &tp->rx_info[i++];
  1784. struct urb *urb = agg->urb;
  1785. urb->actual_length = 0;
  1786. list_add_tail(&agg->list, &rx_queue);
  1787. } while (i < RTL8152_MAX_RX);
  1788. spin_lock_irqsave(&tp->rx_lock, flags);
  1789. list_splice_tail(&rx_queue, &tp->rx_done);
  1790. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1791. }
  1792. return ret;
  1793. }
  1794. static int rtl_stop_rx(struct r8152 *tp)
  1795. {
  1796. int i;
  1797. for (i = 0; i < RTL8152_MAX_RX; i++)
  1798. usb_kill_urb(tp->rx_info[i].urb);
  1799. while (!skb_queue_empty(&tp->rx_queue))
  1800. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1801. return 0;
  1802. }
  1803. static int rtl_enable(struct r8152 *tp)
  1804. {
  1805. u32 ocp_data;
  1806. r8152b_reset_packet_filter(tp);
  1807. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1808. ocp_data |= CR_RE | CR_TE;
  1809. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1810. rxdy_gated_en(tp, false);
  1811. return 0;
  1812. }
  1813. static int rtl8152_enable(struct r8152 *tp)
  1814. {
  1815. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1816. return -ENODEV;
  1817. set_tx_qlen(tp);
  1818. rtl_set_eee_plus(tp);
  1819. return rtl_enable(tp);
  1820. }
  1821. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  1822. {
  1823. u32 ocp_data = tp->coalesce / 8;
  1824. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  1825. }
  1826. static void r8153_set_rx_early_size(struct r8152 *tp)
  1827. {
  1828. u32 mtu = tp->netdev->mtu;
  1829. u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 8;
  1830. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  1831. }
  1832. static int rtl8153_enable(struct r8152 *tp)
  1833. {
  1834. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1835. return -ENODEV;
  1836. usb_disable_lpm(tp->udev);
  1837. set_tx_qlen(tp);
  1838. rtl_set_eee_plus(tp);
  1839. r8153_set_rx_early_timeout(tp);
  1840. r8153_set_rx_early_size(tp);
  1841. return rtl_enable(tp);
  1842. }
  1843. static void rtl_disable(struct r8152 *tp)
  1844. {
  1845. u32 ocp_data;
  1846. int i;
  1847. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1848. rtl_drop_queued_tx(tp);
  1849. return;
  1850. }
  1851. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1852. ocp_data &= ~RCR_ACPT_ALL;
  1853. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1854. rtl_drop_queued_tx(tp);
  1855. for (i = 0; i < RTL8152_MAX_TX; i++)
  1856. usb_kill_urb(tp->tx_info[i].urb);
  1857. rxdy_gated_en(tp, true);
  1858. for (i = 0; i < 1000; i++) {
  1859. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1860. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1861. break;
  1862. usleep_range(1000, 2000);
  1863. }
  1864. for (i = 0; i < 1000; i++) {
  1865. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1866. break;
  1867. usleep_range(1000, 2000);
  1868. }
  1869. rtl_stop_rx(tp);
  1870. rtl8152_nic_reset(tp);
  1871. }
  1872. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1873. {
  1874. u32 ocp_data;
  1875. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1876. if (enable)
  1877. ocp_data |= POWER_CUT;
  1878. else
  1879. ocp_data &= ~POWER_CUT;
  1880. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1881. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1882. ocp_data &= ~RESUME_INDICATE;
  1883. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1884. }
  1885. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1886. {
  1887. u32 ocp_data;
  1888. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1889. if (enable)
  1890. ocp_data |= CPCR_RX_VLAN;
  1891. else
  1892. ocp_data &= ~CPCR_RX_VLAN;
  1893. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1894. }
  1895. static int rtl8152_set_features(struct net_device *dev,
  1896. netdev_features_t features)
  1897. {
  1898. netdev_features_t changed = features ^ dev->features;
  1899. struct r8152 *tp = netdev_priv(dev);
  1900. int ret;
  1901. ret = usb_autopm_get_interface(tp->intf);
  1902. if (ret < 0)
  1903. goto out;
  1904. mutex_lock(&tp->control);
  1905. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1906. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1907. rtl_rx_vlan_en(tp, true);
  1908. else
  1909. rtl_rx_vlan_en(tp, false);
  1910. }
  1911. mutex_unlock(&tp->control);
  1912. usb_autopm_put_interface(tp->intf);
  1913. out:
  1914. return ret;
  1915. }
  1916. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1917. static u32 __rtl_get_wol(struct r8152 *tp)
  1918. {
  1919. u32 ocp_data;
  1920. u32 wolopts = 0;
  1921. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1922. if (ocp_data & LINK_ON_WAKE_EN)
  1923. wolopts |= WAKE_PHY;
  1924. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1925. if (ocp_data & UWF_EN)
  1926. wolopts |= WAKE_UCAST;
  1927. if (ocp_data & BWF_EN)
  1928. wolopts |= WAKE_BCAST;
  1929. if (ocp_data & MWF_EN)
  1930. wolopts |= WAKE_MCAST;
  1931. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1932. if (ocp_data & MAGIC_EN)
  1933. wolopts |= WAKE_MAGIC;
  1934. return wolopts;
  1935. }
  1936. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1937. {
  1938. u32 ocp_data;
  1939. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1940. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1941. ocp_data &= ~LINK_ON_WAKE_EN;
  1942. if (wolopts & WAKE_PHY)
  1943. ocp_data |= LINK_ON_WAKE_EN;
  1944. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1945. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1946. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
  1947. if (wolopts & WAKE_UCAST)
  1948. ocp_data |= UWF_EN;
  1949. if (wolopts & WAKE_BCAST)
  1950. ocp_data |= BWF_EN;
  1951. if (wolopts & WAKE_MCAST)
  1952. ocp_data |= MWF_EN;
  1953. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1954. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1955. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1956. ocp_data &= ~MAGIC_EN;
  1957. if (wolopts & WAKE_MAGIC)
  1958. ocp_data |= MAGIC_EN;
  1959. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1960. if (wolopts & WAKE_ANY)
  1961. device_set_wakeup_enable(&tp->udev->dev, true);
  1962. else
  1963. device_set_wakeup_enable(&tp->udev->dev, false);
  1964. }
  1965. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  1966. {
  1967. u8 u1u2[8];
  1968. if (enable)
  1969. memset(u1u2, 0xff, sizeof(u1u2));
  1970. else
  1971. memset(u1u2, 0x00, sizeof(u1u2));
  1972. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  1973. }
  1974. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  1975. {
  1976. u32 ocp_data;
  1977. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  1978. if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
  1979. ocp_data |= U2P3_ENABLE;
  1980. else
  1981. ocp_data &= ~U2P3_ENABLE;
  1982. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  1983. }
  1984. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  1985. {
  1986. u32 ocp_data;
  1987. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  1988. if (enable)
  1989. ocp_data |= PWR_EN | PHASE2_EN;
  1990. else
  1991. ocp_data &= ~(PWR_EN | PHASE2_EN);
  1992. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  1993. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  1994. ocp_data &= ~PCUT_STATUS;
  1995. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  1996. }
  1997. static bool rtl_can_wakeup(struct r8152 *tp)
  1998. {
  1999. struct usb_device *udev = tp->udev;
  2000. return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
  2001. }
  2002. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  2003. {
  2004. if (enable) {
  2005. u32 ocp_data;
  2006. __rtl_set_wol(tp, WAKE_ANY);
  2007. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2008. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2009. ocp_data |= LINK_OFF_WAKE_EN;
  2010. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2011. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2012. } else {
  2013. u32 ocp_data;
  2014. __rtl_set_wol(tp, tp->saved_wolopts);
  2015. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2016. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2017. ocp_data &= ~LINK_OFF_WAKE_EN;
  2018. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2019. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2020. }
  2021. }
  2022. static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
  2023. {
  2024. rtl_runtime_suspend_enable(tp, enable);
  2025. if (enable) {
  2026. r8153_u1u2en(tp, false);
  2027. r8153_u2p3en(tp, false);
  2028. } else {
  2029. r8153_u2p3en(tp, true);
  2030. r8153_u1u2en(tp, true);
  2031. }
  2032. }
  2033. static void r8153_teredo_off(struct r8152 *tp)
  2034. {
  2035. u32 ocp_data;
  2036. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2037. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  2038. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2039. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  2040. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  2041. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  2042. }
  2043. static void rtl_reset_bmu(struct r8152 *tp)
  2044. {
  2045. u32 ocp_data;
  2046. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
  2047. ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
  2048. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2049. ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
  2050. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2051. }
  2052. static void r8152_aldps_en(struct r8152 *tp, bool enable)
  2053. {
  2054. if (enable) {
  2055. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  2056. LINKENA | DIS_SDSAVE);
  2057. } else {
  2058. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
  2059. DIS_SDSAVE);
  2060. msleep(20);
  2061. }
  2062. }
  2063. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2064. {
  2065. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2066. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2067. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2068. }
  2069. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2070. {
  2071. u16 data;
  2072. r8152_mmd_indirect(tp, dev, reg);
  2073. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2074. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2075. return data;
  2076. }
  2077. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2078. {
  2079. r8152_mmd_indirect(tp, dev, reg);
  2080. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2081. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2082. }
  2083. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2084. {
  2085. u16 config1, config2, config3;
  2086. u32 ocp_data;
  2087. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2088. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2089. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2090. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2091. if (enable) {
  2092. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2093. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2094. config1 |= sd_rise_time(1);
  2095. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2096. config3 |= fast_snr(42);
  2097. } else {
  2098. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2099. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2100. RX_QUIET_EN);
  2101. config1 |= sd_rise_time(7);
  2102. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2103. config3 |= fast_snr(511);
  2104. }
  2105. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2106. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2107. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2108. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2109. }
  2110. static void r8152b_enable_eee(struct r8152 *tp)
  2111. {
  2112. r8152_eee_en(tp, true);
  2113. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2114. }
  2115. static void r8152b_enable_fc(struct r8152 *tp)
  2116. {
  2117. u16 anar;
  2118. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2119. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2120. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2121. }
  2122. static void rtl8152_disable(struct r8152 *tp)
  2123. {
  2124. r8152_aldps_en(tp, false);
  2125. rtl_disable(tp);
  2126. r8152_aldps_en(tp, true);
  2127. }
  2128. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  2129. {
  2130. r8152b_enable_eee(tp);
  2131. r8152_aldps_en(tp, true);
  2132. r8152b_enable_fc(tp);
  2133. set_bit(PHY_RESET, &tp->flags);
  2134. }
  2135. static void r8152b_exit_oob(struct r8152 *tp)
  2136. {
  2137. u32 ocp_data;
  2138. int i;
  2139. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2140. ocp_data &= ~RCR_ACPT_ALL;
  2141. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2142. rxdy_gated_en(tp, true);
  2143. r8153_teredo_off(tp);
  2144. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2145. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  2146. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2147. ocp_data &= ~NOW_IS_OOB;
  2148. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2149. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2150. ocp_data &= ~MCU_BORW_EN;
  2151. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2152. for (i = 0; i < 1000; i++) {
  2153. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2154. if (ocp_data & LINK_LIST_READY)
  2155. break;
  2156. usleep_range(1000, 2000);
  2157. }
  2158. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2159. ocp_data |= RE_INIT_LL;
  2160. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2161. for (i = 0; i < 1000; i++) {
  2162. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2163. if (ocp_data & LINK_LIST_READY)
  2164. break;
  2165. usleep_range(1000, 2000);
  2166. }
  2167. rtl8152_nic_reset(tp);
  2168. /* rx share fifo credit full threshold */
  2169. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2170. if (tp->udev->speed == USB_SPEED_FULL ||
  2171. tp->udev->speed == USB_SPEED_LOW) {
  2172. /* rx share fifo credit near full threshold */
  2173. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2174. RXFIFO_THR2_FULL);
  2175. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2176. RXFIFO_THR3_FULL);
  2177. } else {
  2178. /* rx share fifo credit near full threshold */
  2179. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2180. RXFIFO_THR2_HIGH);
  2181. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2182. RXFIFO_THR3_HIGH);
  2183. }
  2184. /* TX share fifo free credit full threshold */
  2185. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2186. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2187. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2188. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2189. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2190. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2191. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2192. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2193. ocp_data |= TCR0_AUTO_FIFO;
  2194. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2195. }
  2196. static void r8152b_enter_oob(struct r8152 *tp)
  2197. {
  2198. u32 ocp_data;
  2199. int i;
  2200. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2201. ocp_data &= ~NOW_IS_OOB;
  2202. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2203. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2204. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2205. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2206. rtl_disable(tp);
  2207. for (i = 0; i < 1000; i++) {
  2208. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2209. if (ocp_data & LINK_LIST_READY)
  2210. break;
  2211. usleep_range(1000, 2000);
  2212. }
  2213. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2214. ocp_data |= RE_INIT_LL;
  2215. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2216. for (i = 0; i < 1000; i++) {
  2217. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2218. if (ocp_data & LINK_LIST_READY)
  2219. break;
  2220. usleep_range(1000, 2000);
  2221. }
  2222. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2223. rtl_rx_vlan_en(tp, true);
  2224. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2225. ocp_data |= ALDPS_PROXY_MODE;
  2226. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2227. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2228. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2229. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2230. rxdy_gated_en(tp, false);
  2231. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2232. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2233. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2234. }
  2235. static void r8153_aldps_en(struct r8152 *tp, bool enable)
  2236. {
  2237. u16 data;
  2238. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2239. if (enable) {
  2240. data |= EN_ALDPS;
  2241. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2242. } else {
  2243. data &= ~EN_ALDPS;
  2244. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2245. msleep(20);
  2246. }
  2247. }
  2248. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2249. {
  2250. u32 ocp_data;
  2251. u16 config;
  2252. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2253. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2254. if (enable) {
  2255. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2256. config |= EEE10_EN;
  2257. } else {
  2258. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2259. config &= ~EEE10_EN;
  2260. }
  2261. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2262. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2263. }
  2264. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2265. {
  2266. u32 ocp_data;
  2267. u16 data;
  2268. /* disable ALDPS before updating the PHY parameters */
  2269. r8153_aldps_en(tp, false);
  2270. /* disable EEE before updating the PHY parameters */
  2271. r8153_eee_en(tp, false);
  2272. ocp_reg_write(tp, OCP_EEE_ADV, 0);
  2273. if (tp->version == RTL_VER_03) {
  2274. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2275. data &= ~CTAP_SHORT_EN;
  2276. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2277. }
  2278. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2279. data |= EEE_CLKDIV_EN;
  2280. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2281. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2282. data |= EN_10M_BGOFF;
  2283. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2284. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2285. data |= EN_10M_PLLOFF;
  2286. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2287. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2288. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2289. ocp_data |= PFM_PWM_SWITCH;
  2290. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2291. /* Enable LPF corner auto tune */
  2292. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2293. /* Adjust 10M Amplitude */
  2294. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2295. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2296. r8153_eee_en(tp, true);
  2297. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2298. r8153_aldps_en(tp, true);
  2299. r8152b_enable_fc(tp);
  2300. set_bit(PHY_RESET, &tp->flags);
  2301. }
  2302. static void r8153_first_init(struct r8152 *tp)
  2303. {
  2304. u32 ocp_data;
  2305. int i;
  2306. rxdy_gated_en(tp, true);
  2307. r8153_teredo_off(tp);
  2308. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2309. ocp_data &= ~RCR_ACPT_ALL;
  2310. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2311. rtl8152_nic_reset(tp);
  2312. rtl_reset_bmu(tp);
  2313. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2314. ocp_data &= ~NOW_IS_OOB;
  2315. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2316. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2317. ocp_data &= ~MCU_BORW_EN;
  2318. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2319. for (i = 0; i < 1000; i++) {
  2320. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2321. if (ocp_data & LINK_LIST_READY)
  2322. break;
  2323. usleep_range(1000, 2000);
  2324. }
  2325. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2326. ocp_data |= RE_INIT_LL;
  2327. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2328. for (i = 0; i < 1000; i++) {
  2329. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2330. if (ocp_data & LINK_LIST_READY)
  2331. break;
  2332. usleep_range(1000, 2000);
  2333. }
  2334. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2335. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2336. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2337. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2338. ocp_data |= TCR0_AUTO_FIFO;
  2339. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2340. rtl8152_nic_reset(tp);
  2341. /* rx share fifo credit full threshold */
  2342. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2343. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2344. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2345. /* TX share fifo free credit full threshold */
  2346. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2347. /* rx aggregation */
  2348. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2349. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2350. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2351. }
  2352. static void r8153_enter_oob(struct r8152 *tp)
  2353. {
  2354. u32 ocp_data;
  2355. int i;
  2356. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2357. ocp_data &= ~NOW_IS_OOB;
  2358. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2359. rtl_disable(tp);
  2360. rtl_reset_bmu(tp);
  2361. for (i = 0; i < 1000; i++) {
  2362. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2363. if (ocp_data & LINK_LIST_READY)
  2364. break;
  2365. usleep_range(1000, 2000);
  2366. }
  2367. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2368. ocp_data |= RE_INIT_LL;
  2369. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2370. for (i = 0; i < 1000; i++) {
  2371. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2372. if (ocp_data & LINK_LIST_READY)
  2373. break;
  2374. usleep_range(1000, 2000);
  2375. }
  2376. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2377. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2378. ocp_data &= ~TEREDO_WAKE_MASK;
  2379. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2380. rtl_rx_vlan_en(tp, true);
  2381. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2382. ocp_data |= ALDPS_PROXY_MODE;
  2383. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2384. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2385. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2386. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2387. rxdy_gated_en(tp, false);
  2388. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2389. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2390. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2391. }
  2392. static void rtl8153_disable(struct r8152 *tp)
  2393. {
  2394. r8153_aldps_en(tp, false);
  2395. rtl_disable(tp);
  2396. rtl_reset_bmu(tp);
  2397. r8153_aldps_en(tp, true);
  2398. usb_enable_lpm(tp->udev);
  2399. }
  2400. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2401. {
  2402. u16 bmcr, anar, gbcr;
  2403. int ret = 0;
  2404. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2405. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2406. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2407. if (tp->mii.supports_gmii) {
  2408. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2409. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2410. } else {
  2411. gbcr = 0;
  2412. }
  2413. if (autoneg == AUTONEG_DISABLE) {
  2414. if (speed == SPEED_10) {
  2415. bmcr = 0;
  2416. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2417. } else if (speed == SPEED_100) {
  2418. bmcr = BMCR_SPEED100;
  2419. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2420. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2421. bmcr = BMCR_SPEED1000;
  2422. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2423. } else {
  2424. ret = -EINVAL;
  2425. goto out;
  2426. }
  2427. if (duplex == DUPLEX_FULL)
  2428. bmcr |= BMCR_FULLDPLX;
  2429. } else {
  2430. if (speed == SPEED_10) {
  2431. if (duplex == DUPLEX_FULL)
  2432. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2433. else
  2434. anar |= ADVERTISE_10HALF;
  2435. } else if (speed == SPEED_100) {
  2436. if (duplex == DUPLEX_FULL) {
  2437. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2438. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2439. } else {
  2440. anar |= ADVERTISE_10HALF;
  2441. anar |= ADVERTISE_100HALF;
  2442. }
  2443. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2444. if (duplex == DUPLEX_FULL) {
  2445. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2446. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2447. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2448. } else {
  2449. anar |= ADVERTISE_10HALF;
  2450. anar |= ADVERTISE_100HALF;
  2451. gbcr |= ADVERTISE_1000HALF;
  2452. }
  2453. } else {
  2454. ret = -EINVAL;
  2455. goto out;
  2456. }
  2457. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2458. }
  2459. if (test_and_clear_bit(PHY_RESET, &tp->flags))
  2460. bmcr |= BMCR_RESET;
  2461. if (tp->mii.supports_gmii)
  2462. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2463. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2464. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2465. if (bmcr & BMCR_RESET) {
  2466. int i;
  2467. for (i = 0; i < 50; i++) {
  2468. msleep(20);
  2469. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2470. break;
  2471. }
  2472. }
  2473. out:
  2474. return ret;
  2475. }
  2476. static void rtl8152_up(struct r8152 *tp)
  2477. {
  2478. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2479. return;
  2480. r8152_aldps_en(tp, false);
  2481. r8152b_exit_oob(tp);
  2482. r8152_aldps_en(tp, true);
  2483. }
  2484. static void rtl8152_down(struct r8152 *tp)
  2485. {
  2486. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2487. rtl_drop_queued_tx(tp);
  2488. return;
  2489. }
  2490. r8152_power_cut_en(tp, false);
  2491. r8152_aldps_en(tp, false);
  2492. r8152b_enter_oob(tp);
  2493. r8152_aldps_en(tp, true);
  2494. }
  2495. static void rtl8153_up(struct r8152 *tp)
  2496. {
  2497. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2498. return;
  2499. r8153_u1u2en(tp, false);
  2500. r8153_aldps_en(tp, false);
  2501. r8153_first_init(tp);
  2502. r8153_aldps_en(tp, true);
  2503. r8153_u2p3en(tp, true);
  2504. r8153_u1u2en(tp, true);
  2505. usb_enable_lpm(tp->udev);
  2506. }
  2507. static void rtl8153_down(struct r8152 *tp)
  2508. {
  2509. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2510. rtl_drop_queued_tx(tp);
  2511. return;
  2512. }
  2513. r8153_u1u2en(tp, false);
  2514. r8153_u2p3en(tp, false);
  2515. r8153_power_cut_en(tp, false);
  2516. r8153_aldps_en(tp, false);
  2517. r8153_enter_oob(tp);
  2518. r8153_aldps_en(tp, true);
  2519. }
  2520. static bool rtl8152_in_nway(struct r8152 *tp)
  2521. {
  2522. u16 nway_state;
  2523. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
  2524. tp->ocp_base = 0x2000;
  2525. ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
  2526. nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
  2527. /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
  2528. if (nway_state & 0xc000)
  2529. return false;
  2530. else
  2531. return true;
  2532. }
  2533. static bool rtl8153_in_nway(struct r8152 *tp)
  2534. {
  2535. u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
  2536. if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
  2537. return false;
  2538. else
  2539. return true;
  2540. }
  2541. static void set_carrier(struct r8152 *tp)
  2542. {
  2543. struct net_device *netdev = tp->netdev;
  2544. u8 speed;
  2545. speed = rtl8152_get_speed(tp);
  2546. if (speed & LINK_STATUS) {
  2547. if (!netif_carrier_ok(netdev)) {
  2548. tp->rtl_ops.enable(tp);
  2549. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2550. netif_stop_queue(netdev);
  2551. napi_disable(&tp->napi);
  2552. netif_carrier_on(netdev);
  2553. rtl_start_rx(tp);
  2554. napi_enable(&tp->napi);
  2555. netif_wake_queue(netdev);
  2556. netif_info(tp, link, netdev, "carrier on\n");
  2557. }
  2558. } else {
  2559. if (netif_carrier_ok(netdev)) {
  2560. netif_carrier_off(netdev);
  2561. napi_disable(&tp->napi);
  2562. tp->rtl_ops.disable(tp);
  2563. napi_enable(&tp->napi);
  2564. netif_info(tp, link, netdev, "carrier off\n");
  2565. }
  2566. }
  2567. }
  2568. static void rtl_work_func_t(struct work_struct *work)
  2569. {
  2570. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2571. /* If the device is unplugged or !netif_running(), the workqueue
  2572. * doesn't need to wake the device, and could return directly.
  2573. */
  2574. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2575. return;
  2576. if (usb_autopm_get_interface(tp->intf) < 0)
  2577. return;
  2578. if (!test_bit(WORK_ENABLE, &tp->flags))
  2579. goto out1;
  2580. if (!mutex_trylock(&tp->control)) {
  2581. schedule_delayed_work(&tp->schedule, 0);
  2582. goto out1;
  2583. }
  2584. if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
  2585. set_carrier(tp);
  2586. if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2587. _rtl8152_set_rx_mode(tp->netdev);
  2588. /* don't schedule napi before linking */
  2589. if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
  2590. netif_carrier_ok(tp->netdev))
  2591. napi_schedule(&tp->napi);
  2592. mutex_unlock(&tp->control);
  2593. out1:
  2594. usb_autopm_put_interface(tp->intf);
  2595. }
  2596. static void rtl_hw_phy_work_func_t(struct work_struct *work)
  2597. {
  2598. struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
  2599. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2600. return;
  2601. if (usb_autopm_get_interface(tp->intf) < 0)
  2602. return;
  2603. mutex_lock(&tp->control);
  2604. tp->rtl_ops.hw_phy_cfg(tp);
  2605. rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
  2606. mutex_unlock(&tp->control);
  2607. usb_autopm_put_interface(tp->intf);
  2608. }
  2609. #ifdef CONFIG_PM_SLEEP
  2610. static int rtl_notifier(struct notifier_block *nb, unsigned long action,
  2611. void *data)
  2612. {
  2613. struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
  2614. switch (action) {
  2615. case PM_HIBERNATION_PREPARE:
  2616. case PM_SUSPEND_PREPARE:
  2617. usb_autopm_get_interface(tp->intf);
  2618. break;
  2619. case PM_POST_HIBERNATION:
  2620. case PM_POST_SUSPEND:
  2621. usb_autopm_put_interface(tp->intf);
  2622. break;
  2623. case PM_POST_RESTORE:
  2624. case PM_RESTORE_PREPARE:
  2625. default:
  2626. break;
  2627. }
  2628. return NOTIFY_DONE;
  2629. }
  2630. #endif
  2631. static int rtl8152_open(struct net_device *netdev)
  2632. {
  2633. struct r8152 *tp = netdev_priv(netdev);
  2634. int res = 0;
  2635. res = alloc_all_mem(tp);
  2636. if (res)
  2637. goto out;
  2638. res = usb_autopm_get_interface(tp->intf);
  2639. if (res < 0)
  2640. goto out_free;
  2641. mutex_lock(&tp->control);
  2642. tp->rtl_ops.up(tp);
  2643. netif_carrier_off(netdev);
  2644. netif_start_queue(netdev);
  2645. set_bit(WORK_ENABLE, &tp->flags);
  2646. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2647. if (res) {
  2648. if (res == -ENODEV)
  2649. netif_device_detach(tp->netdev);
  2650. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2651. res);
  2652. goto out_unlock;
  2653. }
  2654. napi_enable(&tp->napi);
  2655. mutex_unlock(&tp->control);
  2656. usb_autopm_put_interface(tp->intf);
  2657. #ifdef CONFIG_PM_SLEEP
  2658. tp->pm_notifier.notifier_call = rtl_notifier;
  2659. register_pm_notifier(&tp->pm_notifier);
  2660. #endif
  2661. return 0;
  2662. out_unlock:
  2663. mutex_unlock(&tp->control);
  2664. usb_autopm_put_interface(tp->intf);
  2665. out_free:
  2666. free_all_mem(tp);
  2667. out:
  2668. return res;
  2669. }
  2670. static int rtl8152_close(struct net_device *netdev)
  2671. {
  2672. struct r8152 *tp = netdev_priv(netdev);
  2673. int res = 0;
  2674. #ifdef CONFIG_PM_SLEEP
  2675. unregister_pm_notifier(&tp->pm_notifier);
  2676. #endif
  2677. napi_disable(&tp->napi);
  2678. clear_bit(WORK_ENABLE, &tp->flags);
  2679. usb_kill_urb(tp->intr_urb);
  2680. cancel_delayed_work_sync(&tp->schedule);
  2681. netif_stop_queue(netdev);
  2682. res = usb_autopm_get_interface(tp->intf);
  2683. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2684. rtl_drop_queued_tx(tp);
  2685. rtl_stop_rx(tp);
  2686. } else {
  2687. mutex_lock(&tp->control);
  2688. tp->rtl_ops.down(tp);
  2689. mutex_unlock(&tp->control);
  2690. usb_autopm_put_interface(tp->intf);
  2691. }
  2692. free_all_mem(tp);
  2693. return res;
  2694. }
  2695. static void rtl_tally_reset(struct r8152 *tp)
  2696. {
  2697. u32 ocp_data;
  2698. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2699. ocp_data |= TALLY_RESET;
  2700. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2701. }
  2702. static void r8152b_init(struct r8152 *tp)
  2703. {
  2704. u32 ocp_data;
  2705. u16 data;
  2706. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2707. return;
  2708. data = r8152_mdio_read(tp, MII_BMCR);
  2709. if (data & BMCR_PDOWN) {
  2710. data &= ~BMCR_PDOWN;
  2711. r8152_mdio_write(tp, MII_BMCR, data);
  2712. }
  2713. r8152_aldps_en(tp, false);
  2714. if (tp->version == RTL_VER_01) {
  2715. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2716. ocp_data &= ~LED_MODE_MASK;
  2717. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2718. }
  2719. r8152_power_cut_en(tp, false);
  2720. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2721. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2722. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2723. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2724. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2725. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2726. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2727. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2728. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2729. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2730. rtl_tally_reset(tp);
  2731. /* enable rx aggregation */
  2732. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2733. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2734. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2735. }
  2736. static void r8153_init(struct r8152 *tp)
  2737. {
  2738. u32 ocp_data;
  2739. u16 data;
  2740. int i;
  2741. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2742. return;
  2743. r8153_u1u2en(tp, false);
  2744. for (i = 0; i < 500; i++) {
  2745. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2746. AUTOLOAD_DONE)
  2747. break;
  2748. msleep(20);
  2749. }
  2750. for (i = 0; i < 500; i++) {
  2751. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2752. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2753. break;
  2754. msleep(20);
  2755. }
  2756. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  2757. tp->version == RTL_VER_05)
  2758. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2759. data = r8152_mdio_read(tp, MII_BMCR);
  2760. if (data & BMCR_PDOWN) {
  2761. data &= ~BMCR_PDOWN;
  2762. r8152_mdio_write(tp, MII_BMCR, data);
  2763. }
  2764. for (i = 0; i < 500; i++) {
  2765. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2766. if (ocp_data == PHY_STAT_LAN_ON)
  2767. break;
  2768. msleep(20);
  2769. }
  2770. usb_disable_lpm(tp->udev);
  2771. r8153_u2p3en(tp, false);
  2772. if (tp->version == RTL_VER_04) {
  2773. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  2774. ocp_data &= ~pwd_dn_scale_mask;
  2775. ocp_data |= pwd_dn_scale(96);
  2776. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  2777. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  2778. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  2779. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  2780. } else if (tp->version == RTL_VER_05) {
  2781. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  2782. ocp_data &= ~ECM_ALDPS;
  2783. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  2784. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2785. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2786. ocp_data &= ~DYNAMIC_BURST;
  2787. else
  2788. ocp_data |= DYNAMIC_BURST;
  2789. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2790. } else if (tp->version == RTL_VER_06) {
  2791. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2792. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2793. ocp_data &= ~DYNAMIC_BURST;
  2794. else
  2795. ocp_data |= DYNAMIC_BURST;
  2796. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2797. }
  2798. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  2799. ocp_data |= EP4_FULL_FC;
  2800. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  2801. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2802. ocp_data &= ~TIMER11_EN;
  2803. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2804. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2805. ocp_data &= ~LED_MODE_MASK;
  2806. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2807. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  2808. if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
  2809. ocp_data |= LPM_TIMER_500MS;
  2810. else
  2811. ocp_data |= LPM_TIMER_500US;
  2812. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2813. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2814. ocp_data &= ~SEN_VAL_MASK;
  2815. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2816. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2817. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  2818. r8153_power_cut_en(tp, false);
  2819. r8153_u1u2en(tp, true);
  2820. /* MAC clock speed down */
  2821. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
  2822. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
  2823. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
  2824. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
  2825. rtl_tally_reset(tp);
  2826. r8153_u2p3en(tp, true);
  2827. }
  2828. static int rtl8152_pre_reset(struct usb_interface *intf)
  2829. {
  2830. struct r8152 *tp = usb_get_intfdata(intf);
  2831. struct net_device *netdev;
  2832. if (!tp)
  2833. return 0;
  2834. netdev = tp->netdev;
  2835. if (!netif_running(netdev))
  2836. return 0;
  2837. netif_stop_queue(netdev);
  2838. napi_disable(&tp->napi);
  2839. clear_bit(WORK_ENABLE, &tp->flags);
  2840. usb_kill_urb(tp->intr_urb);
  2841. cancel_delayed_work_sync(&tp->schedule);
  2842. if (netif_carrier_ok(netdev)) {
  2843. mutex_lock(&tp->control);
  2844. tp->rtl_ops.disable(tp);
  2845. mutex_unlock(&tp->control);
  2846. }
  2847. return 0;
  2848. }
  2849. static int rtl8152_post_reset(struct usb_interface *intf)
  2850. {
  2851. struct r8152 *tp = usb_get_intfdata(intf);
  2852. struct net_device *netdev;
  2853. if (!tp)
  2854. return 0;
  2855. netdev = tp->netdev;
  2856. if (!netif_running(netdev))
  2857. return 0;
  2858. set_bit(WORK_ENABLE, &tp->flags);
  2859. if (netif_carrier_ok(netdev)) {
  2860. mutex_lock(&tp->control);
  2861. tp->rtl_ops.enable(tp);
  2862. rtl_start_rx(tp);
  2863. rtl8152_set_rx_mode(netdev);
  2864. mutex_unlock(&tp->control);
  2865. }
  2866. napi_enable(&tp->napi);
  2867. netif_wake_queue(netdev);
  2868. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2869. if (!list_empty(&tp->rx_done))
  2870. napi_schedule(&tp->napi);
  2871. return 0;
  2872. }
  2873. static bool delay_autosuspend(struct r8152 *tp)
  2874. {
  2875. bool sw_linking = !!netif_carrier_ok(tp->netdev);
  2876. bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
  2877. /* This means a linking change occurs and the driver doesn't detect it,
  2878. * yet. If the driver has disabled tx/rx and hw is linking on, the
  2879. * device wouldn't wake up by receiving any packet.
  2880. */
  2881. if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
  2882. return true;
  2883. /* If the linking down is occurred by nway, the device may miss the
  2884. * linking change event. And it wouldn't wake when linking on.
  2885. */
  2886. if (!sw_linking && tp->rtl_ops.in_nway(tp))
  2887. return true;
  2888. else if (!skb_queue_empty(&tp->tx_queue))
  2889. return true;
  2890. else
  2891. return false;
  2892. }
  2893. static int rtl8152_rumtime_suspend(struct r8152 *tp)
  2894. {
  2895. struct net_device *netdev = tp->netdev;
  2896. int ret = 0;
  2897. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2898. smp_mb__after_atomic();
  2899. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2900. u32 rcr = 0;
  2901. if (delay_autosuspend(tp)) {
  2902. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2903. smp_mb__after_atomic();
  2904. ret = -EBUSY;
  2905. goto out1;
  2906. }
  2907. if (netif_carrier_ok(netdev)) {
  2908. u32 ocp_data;
  2909. rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2910. ocp_data = rcr & ~RCR_ACPT_ALL;
  2911. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2912. rxdy_gated_en(tp, true);
  2913. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
  2914. PLA_OOB_CTRL);
  2915. if (!(ocp_data & RXFIFO_EMPTY)) {
  2916. rxdy_gated_en(tp, false);
  2917. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  2918. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2919. smp_mb__after_atomic();
  2920. ret = -EBUSY;
  2921. goto out1;
  2922. }
  2923. }
  2924. clear_bit(WORK_ENABLE, &tp->flags);
  2925. usb_kill_urb(tp->intr_urb);
  2926. tp->rtl_ops.autosuspend_en(tp, true);
  2927. if (netif_carrier_ok(netdev)) {
  2928. napi_disable(&tp->napi);
  2929. rtl_stop_rx(tp);
  2930. rxdy_gated_en(tp, false);
  2931. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  2932. napi_enable(&tp->napi);
  2933. }
  2934. }
  2935. out1:
  2936. return ret;
  2937. }
  2938. static int rtl8152_system_suspend(struct r8152 *tp)
  2939. {
  2940. struct net_device *netdev = tp->netdev;
  2941. int ret = 0;
  2942. netif_device_detach(netdev);
  2943. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2944. clear_bit(WORK_ENABLE, &tp->flags);
  2945. usb_kill_urb(tp->intr_urb);
  2946. napi_disable(&tp->napi);
  2947. cancel_delayed_work_sync(&tp->schedule);
  2948. tp->rtl_ops.down(tp);
  2949. napi_enable(&tp->napi);
  2950. }
  2951. return ret;
  2952. }
  2953. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2954. {
  2955. struct r8152 *tp = usb_get_intfdata(intf);
  2956. int ret;
  2957. mutex_lock(&tp->control);
  2958. if (PMSG_IS_AUTO(message))
  2959. ret = rtl8152_rumtime_suspend(tp);
  2960. else
  2961. ret = rtl8152_system_suspend(tp);
  2962. mutex_unlock(&tp->control);
  2963. return ret;
  2964. }
  2965. static int rtl8152_resume(struct usb_interface *intf)
  2966. {
  2967. struct r8152 *tp = usb_get_intfdata(intf);
  2968. mutex_lock(&tp->control);
  2969. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2970. tp->rtl_ops.init(tp);
  2971. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  2972. netif_device_attach(tp->netdev);
  2973. }
  2974. if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
  2975. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2976. tp->rtl_ops.autosuspend_en(tp, false);
  2977. napi_disable(&tp->napi);
  2978. set_bit(WORK_ENABLE, &tp->flags);
  2979. if (netif_carrier_ok(tp->netdev))
  2980. rtl_start_rx(tp);
  2981. napi_enable(&tp->napi);
  2982. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2983. smp_mb__after_atomic();
  2984. if (!list_empty(&tp->rx_done))
  2985. napi_schedule(&tp->napi);
  2986. } else {
  2987. tp->rtl_ops.up(tp);
  2988. netif_carrier_off(tp->netdev);
  2989. set_bit(WORK_ENABLE, &tp->flags);
  2990. }
  2991. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2992. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2993. if (tp->netdev->flags & IFF_UP)
  2994. tp->rtl_ops.autosuspend_en(tp, false);
  2995. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2996. }
  2997. mutex_unlock(&tp->control);
  2998. return 0;
  2999. }
  3000. static int rtl8152_reset_resume(struct usb_interface *intf)
  3001. {
  3002. struct r8152 *tp = usb_get_intfdata(intf);
  3003. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  3004. return rtl8152_resume(intf);
  3005. }
  3006. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  3007. {
  3008. struct r8152 *tp = netdev_priv(dev);
  3009. if (usb_autopm_get_interface(tp->intf) < 0)
  3010. return;
  3011. if (!rtl_can_wakeup(tp)) {
  3012. wol->supported = 0;
  3013. wol->wolopts = 0;
  3014. } else {
  3015. mutex_lock(&tp->control);
  3016. wol->supported = WAKE_ANY;
  3017. wol->wolopts = __rtl_get_wol(tp);
  3018. mutex_unlock(&tp->control);
  3019. }
  3020. usb_autopm_put_interface(tp->intf);
  3021. }
  3022. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  3023. {
  3024. struct r8152 *tp = netdev_priv(dev);
  3025. int ret;
  3026. if (!rtl_can_wakeup(tp))
  3027. return -EOPNOTSUPP;
  3028. ret = usb_autopm_get_interface(tp->intf);
  3029. if (ret < 0)
  3030. goto out_set_wol;
  3031. mutex_lock(&tp->control);
  3032. __rtl_set_wol(tp, wol->wolopts);
  3033. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  3034. mutex_unlock(&tp->control);
  3035. usb_autopm_put_interface(tp->intf);
  3036. out_set_wol:
  3037. return ret;
  3038. }
  3039. static u32 rtl8152_get_msglevel(struct net_device *dev)
  3040. {
  3041. struct r8152 *tp = netdev_priv(dev);
  3042. return tp->msg_enable;
  3043. }
  3044. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  3045. {
  3046. struct r8152 *tp = netdev_priv(dev);
  3047. tp->msg_enable = value;
  3048. }
  3049. static void rtl8152_get_drvinfo(struct net_device *netdev,
  3050. struct ethtool_drvinfo *info)
  3051. {
  3052. struct r8152 *tp = netdev_priv(netdev);
  3053. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  3054. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  3055. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  3056. }
  3057. static
  3058. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  3059. {
  3060. struct r8152 *tp = netdev_priv(netdev);
  3061. int ret;
  3062. if (!tp->mii.mdio_read)
  3063. return -EOPNOTSUPP;
  3064. ret = usb_autopm_get_interface(tp->intf);
  3065. if (ret < 0)
  3066. goto out;
  3067. mutex_lock(&tp->control);
  3068. ret = mii_ethtool_gset(&tp->mii, cmd);
  3069. mutex_unlock(&tp->control);
  3070. usb_autopm_put_interface(tp->intf);
  3071. out:
  3072. return ret;
  3073. }
  3074. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  3075. {
  3076. struct r8152 *tp = netdev_priv(dev);
  3077. int ret;
  3078. ret = usb_autopm_get_interface(tp->intf);
  3079. if (ret < 0)
  3080. goto out;
  3081. mutex_lock(&tp->control);
  3082. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  3083. if (!ret) {
  3084. tp->autoneg = cmd->autoneg;
  3085. tp->speed = cmd->speed;
  3086. tp->duplex = cmd->duplex;
  3087. }
  3088. mutex_unlock(&tp->control);
  3089. usb_autopm_put_interface(tp->intf);
  3090. out:
  3091. return ret;
  3092. }
  3093. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  3094. "tx_packets",
  3095. "rx_packets",
  3096. "tx_errors",
  3097. "rx_errors",
  3098. "rx_missed",
  3099. "align_errors",
  3100. "tx_single_collisions",
  3101. "tx_multi_collisions",
  3102. "rx_unicast",
  3103. "rx_broadcast",
  3104. "rx_multicast",
  3105. "tx_aborted",
  3106. "tx_underrun",
  3107. };
  3108. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  3109. {
  3110. switch (sset) {
  3111. case ETH_SS_STATS:
  3112. return ARRAY_SIZE(rtl8152_gstrings);
  3113. default:
  3114. return -EOPNOTSUPP;
  3115. }
  3116. }
  3117. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  3118. struct ethtool_stats *stats, u64 *data)
  3119. {
  3120. struct r8152 *tp = netdev_priv(dev);
  3121. struct tally_counter tally;
  3122. if (usb_autopm_get_interface(tp->intf) < 0)
  3123. return;
  3124. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  3125. usb_autopm_put_interface(tp->intf);
  3126. data[0] = le64_to_cpu(tally.tx_packets);
  3127. data[1] = le64_to_cpu(tally.rx_packets);
  3128. data[2] = le64_to_cpu(tally.tx_errors);
  3129. data[3] = le32_to_cpu(tally.rx_errors);
  3130. data[4] = le16_to_cpu(tally.rx_missed);
  3131. data[5] = le16_to_cpu(tally.align_errors);
  3132. data[6] = le32_to_cpu(tally.tx_one_collision);
  3133. data[7] = le32_to_cpu(tally.tx_multi_collision);
  3134. data[8] = le64_to_cpu(tally.rx_unicast);
  3135. data[9] = le64_to_cpu(tally.rx_broadcast);
  3136. data[10] = le32_to_cpu(tally.rx_multicast);
  3137. data[11] = le16_to_cpu(tally.tx_aborted);
  3138. data[12] = le16_to_cpu(tally.tx_underrun);
  3139. }
  3140. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3141. {
  3142. switch (stringset) {
  3143. case ETH_SS_STATS:
  3144. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  3145. break;
  3146. }
  3147. }
  3148. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3149. {
  3150. u32 ocp_data, lp, adv, supported = 0;
  3151. u16 val;
  3152. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  3153. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3154. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  3155. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3156. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  3157. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3158. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3159. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3160. eee->eee_enabled = !!ocp_data;
  3161. eee->eee_active = !!(supported & adv & lp);
  3162. eee->supported = supported;
  3163. eee->advertised = adv;
  3164. eee->lp_advertised = lp;
  3165. return 0;
  3166. }
  3167. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3168. {
  3169. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3170. r8152_eee_en(tp, eee->eee_enabled);
  3171. if (!eee->eee_enabled)
  3172. val = 0;
  3173. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  3174. return 0;
  3175. }
  3176. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3177. {
  3178. u32 ocp_data, lp, adv, supported = 0;
  3179. u16 val;
  3180. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  3181. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3182. val = ocp_reg_read(tp, OCP_EEE_ADV);
  3183. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3184. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  3185. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3186. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3187. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3188. eee->eee_enabled = !!ocp_data;
  3189. eee->eee_active = !!(supported & adv & lp);
  3190. eee->supported = supported;
  3191. eee->advertised = adv;
  3192. eee->lp_advertised = lp;
  3193. return 0;
  3194. }
  3195. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3196. {
  3197. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3198. r8153_eee_en(tp, eee->eee_enabled);
  3199. if (!eee->eee_enabled)
  3200. val = 0;
  3201. ocp_reg_write(tp, OCP_EEE_ADV, val);
  3202. return 0;
  3203. }
  3204. static int
  3205. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  3206. {
  3207. struct r8152 *tp = netdev_priv(net);
  3208. int ret;
  3209. ret = usb_autopm_get_interface(tp->intf);
  3210. if (ret < 0)
  3211. goto out;
  3212. mutex_lock(&tp->control);
  3213. ret = tp->rtl_ops.eee_get(tp, edata);
  3214. mutex_unlock(&tp->control);
  3215. usb_autopm_put_interface(tp->intf);
  3216. out:
  3217. return ret;
  3218. }
  3219. static int
  3220. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  3221. {
  3222. struct r8152 *tp = netdev_priv(net);
  3223. int ret;
  3224. ret = usb_autopm_get_interface(tp->intf);
  3225. if (ret < 0)
  3226. goto out;
  3227. mutex_lock(&tp->control);
  3228. ret = tp->rtl_ops.eee_set(tp, edata);
  3229. if (!ret)
  3230. ret = mii_nway_restart(&tp->mii);
  3231. mutex_unlock(&tp->control);
  3232. usb_autopm_put_interface(tp->intf);
  3233. out:
  3234. return ret;
  3235. }
  3236. static int rtl8152_nway_reset(struct net_device *dev)
  3237. {
  3238. struct r8152 *tp = netdev_priv(dev);
  3239. int ret;
  3240. ret = usb_autopm_get_interface(tp->intf);
  3241. if (ret < 0)
  3242. goto out;
  3243. mutex_lock(&tp->control);
  3244. ret = mii_nway_restart(&tp->mii);
  3245. mutex_unlock(&tp->control);
  3246. usb_autopm_put_interface(tp->intf);
  3247. out:
  3248. return ret;
  3249. }
  3250. static int rtl8152_get_coalesce(struct net_device *netdev,
  3251. struct ethtool_coalesce *coalesce)
  3252. {
  3253. struct r8152 *tp = netdev_priv(netdev);
  3254. switch (tp->version) {
  3255. case RTL_VER_01:
  3256. case RTL_VER_02:
  3257. return -EOPNOTSUPP;
  3258. default:
  3259. break;
  3260. }
  3261. coalesce->rx_coalesce_usecs = tp->coalesce;
  3262. return 0;
  3263. }
  3264. static int rtl8152_set_coalesce(struct net_device *netdev,
  3265. struct ethtool_coalesce *coalesce)
  3266. {
  3267. struct r8152 *tp = netdev_priv(netdev);
  3268. int ret;
  3269. switch (tp->version) {
  3270. case RTL_VER_01:
  3271. case RTL_VER_02:
  3272. return -EOPNOTSUPP;
  3273. default:
  3274. break;
  3275. }
  3276. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  3277. return -EINVAL;
  3278. ret = usb_autopm_get_interface(tp->intf);
  3279. if (ret < 0)
  3280. return ret;
  3281. mutex_lock(&tp->control);
  3282. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  3283. tp->coalesce = coalesce->rx_coalesce_usecs;
  3284. if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
  3285. r8153_set_rx_early_timeout(tp);
  3286. }
  3287. mutex_unlock(&tp->control);
  3288. usb_autopm_put_interface(tp->intf);
  3289. return ret;
  3290. }
  3291. static const struct ethtool_ops ops = {
  3292. .get_drvinfo = rtl8152_get_drvinfo,
  3293. .get_settings = rtl8152_get_settings,
  3294. .set_settings = rtl8152_set_settings,
  3295. .get_link = ethtool_op_get_link,
  3296. .nway_reset = rtl8152_nway_reset,
  3297. .get_msglevel = rtl8152_get_msglevel,
  3298. .set_msglevel = rtl8152_set_msglevel,
  3299. .get_wol = rtl8152_get_wol,
  3300. .set_wol = rtl8152_set_wol,
  3301. .get_strings = rtl8152_get_strings,
  3302. .get_sset_count = rtl8152_get_sset_count,
  3303. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  3304. .get_coalesce = rtl8152_get_coalesce,
  3305. .set_coalesce = rtl8152_set_coalesce,
  3306. .get_eee = rtl_ethtool_get_eee,
  3307. .set_eee = rtl_ethtool_set_eee,
  3308. };
  3309. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  3310. {
  3311. struct r8152 *tp = netdev_priv(netdev);
  3312. struct mii_ioctl_data *data = if_mii(rq);
  3313. int res;
  3314. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3315. return -ENODEV;
  3316. res = usb_autopm_get_interface(tp->intf);
  3317. if (res < 0)
  3318. goto out;
  3319. switch (cmd) {
  3320. case SIOCGMIIPHY:
  3321. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  3322. break;
  3323. case SIOCGMIIREG:
  3324. mutex_lock(&tp->control);
  3325. data->val_out = r8152_mdio_read(tp, data->reg_num);
  3326. mutex_unlock(&tp->control);
  3327. break;
  3328. case SIOCSMIIREG:
  3329. if (!capable(CAP_NET_ADMIN)) {
  3330. res = -EPERM;
  3331. break;
  3332. }
  3333. mutex_lock(&tp->control);
  3334. r8152_mdio_write(tp, data->reg_num, data->val_in);
  3335. mutex_unlock(&tp->control);
  3336. break;
  3337. default:
  3338. res = -EOPNOTSUPP;
  3339. }
  3340. usb_autopm_put_interface(tp->intf);
  3341. out:
  3342. return res;
  3343. }
  3344. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  3345. {
  3346. struct r8152 *tp = netdev_priv(dev);
  3347. int ret;
  3348. switch (tp->version) {
  3349. case RTL_VER_01:
  3350. case RTL_VER_02:
  3351. return eth_change_mtu(dev, new_mtu);
  3352. default:
  3353. break;
  3354. }
  3355. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3356. return -EINVAL;
  3357. ret = usb_autopm_get_interface(tp->intf);
  3358. if (ret < 0)
  3359. return ret;
  3360. mutex_lock(&tp->control);
  3361. dev->mtu = new_mtu;
  3362. if (netif_running(dev) && netif_carrier_ok(dev))
  3363. r8153_set_rx_early_size(tp);
  3364. mutex_unlock(&tp->control);
  3365. usb_autopm_put_interface(tp->intf);
  3366. return ret;
  3367. }
  3368. static const struct net_device_ops rtl8152_netdev_ops = {
  3369. .ndo_open = rtl8152_open,
  3370. .ndo_stop = rtl8152_close,
  3371. .ndo_do_ioctl = rtl8152_ioctl,
  3372. .ndo_start_xmit = rtl8152_start_xmit,
  3373. .ndo_tx_timeout = rtl8152_tx_timeout,
  3374. .ndo_set_features = rtl8152_set_features,
  3375. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3376. .ndo_set_mac_address = rtl8152_set_mac_address,
  3377. .ndo_change_mtu = rtl8152_change_mtu,
  3378. .ndo_validate_addr = eth_validate_addr,
  3379. .ndo_features_check = rtl8152_features_check,
  3380. };
  3381. static void r8152b_get_version(struct r8152 *tp)
  3382. {
  3383. u32 ocp_data;
  3384. u16 version;
  3385. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3386. version = (u16)(ocp_data & VERSION_MASK);
  3387. switch (version) {
  3388. case 0x4c00:
  3389. tp->version = RTL_VER_01;
  3390. break;
  3391. case 0x4c10:
  3392. tp->version = RTL_VER_02;
  3393. break;
  3394. case 0x5c00:
  3395. tp->version = RTL_VER_03;
  3396. tp->mii.supports_gmii = 1;
  3397. break;
  3398. case 0x5c10:
  3399. tp->version = RTL_VER_04;
  3400. tp->mii.supports_gmii = 1;
  3401. break;
  3402. case 0x5c20:
  3403. tp->version = RTL_VER_05;
  3404. tp->mii.supports_gmii = 1;
  3405. break;
  3406. case 0x5c30:
  3407. tp->version = RTL_VER_06;
  3408. tp->mii.supports_gmii = 1;
  3409. break;
  3410. default:
  3411. netif_info(tp, probe, tp->netdev,
  3412. "Unknown version 0x%04x\n", version);
  3413. break;
  3414. }
  3415. }
  3416. static void rtl8152_unload(struct r8152 *tp)
  3417. {
  3418. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3419. return;
  3420. if (tp->version != RTL_VER_01)
  3421. r8152_power_cut_en(tp, true);
  3422. }
  3423. static void rtl8153_unload(struct r8152 *tp)
  3424. {
  3425. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3426. return;
  3427. r8153_power_cut_en(tp, false);
  3428. }
  3429. static int rtl_ops_init(struct r8152 *tp)
  3430. {
  3431. struct rtl_ops *ops = &tp->rtl_ops;
  3432. int ret = 0;
  3433. switch (tp->version) {
  3434. case RTL_VER_01:
  3435. case RTL_VER_02:
  3436. ops->init = r8152b_init;
  3437. ops->enable = rtl8152_enable;
  3438. ops->disable = rtl8152_disable;
  3439. ops->up = rtl8152_up;
  3440. ops->down = rtl8152_down;
  3441. ops->unload = rtl8152_unload;
  3442. ops->eee_get = r8152_get_eee;
  3443. ops->eee_set = r8152_set_eee;
  3444. ops->in_nway = rtl8152_in_nway;
  3445. ops->hw_phy_cfg = r8152b_hw_phy_cfg;
  3446. ops->autosuspend_en = rtl_runtime_suspend_enable;
  3447. break;
  3448. case RTL_VER_03:
  3449. case RTL_VER_04:
  3450. case RTL_VER_05:
  3451. case RTL_VER_06:
  3452. ops->init = r8153_init;
  3453. ops->enable = rtl8153_enable;
  3454. ops->disable = rtl8153_disable;
  3455. ops->up = rtl8153_up;
  3456. ops->down = rtl8153_down;
  3457. ops->unload = rtl8153_unload;
  3458. ops->eee_get = r8153_get_eee;
  3459. ops->eee_set = r8153_set_eee;
  3460. ops->in_nway = rtl8153_in_nway;
  3461. ops->hw_phy_cfg = r8153_hw_phy_cfg;
  3462. ops->autosuspend_en = rtl8153_runtime_enable;
  3463. break;
  3464. default:
  3465. ret = -ENODEV;
  3466. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3467. break;
  3468. }
  3469. return ret;
  3470. }
  3471. static int rtl8152_probe(struct usb_interface *intf,
  3472. const struct usb_device_id *id)
  3473. {
  3474. struct usb_device *udev = interface_to_usbdev(intf);
  3475. struct r8152 *tp;
  3476. struct net_device *netdev;
  3477. int ret;
  3478. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3479. usb_driver_set_configuration(udev, 1);
  3480. return -ENODEV;
  3481. }
  3482. usb_reset_device(udev);
  3483. netdev = alloc_etherdev(sizeof(struct r8152));
  3484. if (!netdev) {
  3485. dev_err(&intf->dev, "Out of memory\n");
  3486. return -ENOMEM;
  3487. }
  3488. SET_NETDEV_DEV(netdev, &intf->dev);
  3489. tp = netdev_priv(netdev);
  3490. tp->msg_enable = 0x7FFF;
  3491. tp->udev = udev;
  3492. tp->netdev = netdev;
  3493. tp->intf = intf;
  3494. r8152b_get_version(tp);
  3495. ret = rtl_ops_init(tp);
  3496. if (ret)
  3497. goto out;
  3498. mutex_init(&tp->control);
  3499. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3500. INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
  3501. netdev->netdev_ops = &rtl8152_netdev_ops;
  3502. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3503. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3504. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3505. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3506. NETIF_F_HW_VLAN_CTAG_TX;
  3507. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3508. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3509. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3510. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3511. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3512. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3513. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3514. if (tp->version == RTL_VER_01) {
  3515. netdev->features &= ~NETIF_F_RXCSUM;
  3516. netdev->hw_features &= ~NETIF_F_RXCSUM;
  3517. }
  3518. netdev->ethtool_ops = &ops;
  3519. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3520. tp->mii.dev = netdev;
  3521. tp->mii.mdio_read = read_mii_word;
  3522. tp->mii.mdio_write = write_mii_word;
  3523. tp->mii.phy_id_mask = 0x3f;
  3524. tp->mii.reg_num_mask = 0x1f;
  3525. tp->mii.phy_id = R8152_PHY_ID;
  3526. switch (udev->speed) {
  3527. case USB_SPEED_SUPER:
  3528. case USB_SPEED_SUPER_PLUS:
  3529. tp->coalesce = COALESCE_SUPER;
  3530. break;
  3531. case USB_SPEED_HIGH:
  3532. tp->coalesce = COALESCE_HIGH;
  3533. break;
  3534. default:
  3535. tp->coalesce = COALESCE_SLOW;
  3536. break;
  3537. }
  3538. tp->autoneg = AUTONEG_ENABLE;
  3539. tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
  3540. tp->duplex = DUPLEX_FULL;
  3541. intf->needs_remote_wakeup = 1;
  3542. tp->rtl_ops.init(tp);
  3543. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  3544. set_ethernet_addr(tp);
  3545. usb_set_intfdata(intf, tp);
  3546. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3547. ret = register_netdev(netdev);
  3548. if (ret != 0) {
  3549. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3550. goto out1;
  3551. }
  3552. if (!rtl_can_wakeup(tp))
  3553. __rtl_set_wol(tp, 0);
  3554. tp->saved_wolopts = __rtl_get_wol(tp);
  3555. if (tp->saved_wolopts)
  3556. device_set_wakeup_enable(&udev->dev, true);
  3557. else
  3558. device_set_wakeup_enable(&udev->dev, false);
  3559. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3560. return 0;
  3561. out1:
  3562. netif_napi_del(&tp->napi);
  3563. usb_set_intfdata(intf, NULL);
  3564. out:
  3565. free_netdev(netdev);
  3566. return ret;
  3567. }
  3568. static void rtl8152_disconnect(struct usb_interface *intf)
  3569. {
  3570. struct r8152 *tp = usb_get_intfdata(intf);
  3571. usb_set_intfdata(intf, NULL);
  3572. if (tp) {
  3573. struct usb_device *udev = tp->udev;
  3574. if (udev->state == USB_STATE_NOTATTACHED)
  3575. set_bit(RTL8152_UNPLUG, &tp->flags);
  3576. netif_napi_del(&tp->napi);
  3577. unregister_netdev(tp->netdev);
  3578. cancel_delayed_work_sync(&tp->hw_phy_work);
  3579. tp->rtl_ops.unload(tp);
  3580. free_netdev(tp->netdev);
  3581. }
  3582. }
  3583. #define REALTEK_USB_DEVICE(vend, prod) \
  3584. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3585. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3586. .idVendor = (vend), \
  3587. .idProduct = (prod), \
  3588. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3589. }, \
  3590. { \
  3591. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3592. USB_DEVICE_ID_MATCH_DEVICE, \
  3593. .idVendor = (vend), \
  3594. .idProduct = (prod), \
  3595. .bInterfaceClass = USB_CLASS_COMM, \
  3596. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3597. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3598. /* table of devices that work with this driver */
  3599. static struct usb_device_id rtl8152_table[] = {
  3600. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3601. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3602. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3603. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
  3604. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
  3605. {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
  3606. {}
  3607. };
  3608. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3609. static struct usb_driver rtl8152_driver = {
  3610. .name = MODULENAME,
  3611. .id_table = rtl8152_table,
  3612. .probe = rtl8152_probe,
  3613. .disconnect = rtl8152_disconnect,
  3614. .suspend = rtl8152_suspend,
  3615. .resume = rtl8152_resume,
  3616. .reset_resume = rtl8152_reset_resume,
  3617. .pre_reset = rtl8152_pre_reset,
  3618. .post_reset = rtl8152_post_reset,
  3619. .supports_autosuspend = 1,
  3620. .disable_hub_initiated_lpm = 1,
  3621. };
  3622. module_usb_driver(rtl8152_driver);
  3623. MODULE_AUTHOR(DRIVER_AUTHOR);
  3624. MODULE_DESCRIPTION(DRIVER_DESC);
  3625. MODULE_LICENSE("GPL");
  3626. MODULE_VERSION(DRIVER_VERSION);