industrialio-buffer-dmaengine.c 5.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208
  1. /*
  2. * Copyright 2014-2015 Analog Devices Inc.
  3. * Author: Lars-Peter Clausen <lars@metafoo.de>
  4. *
  5. * Licensed under the GPL-2 or later.
  6. */
  7. #include <linux/slab.h>
  8. #include <linux/kernel.h>
  9. #include <linux/dmaengine.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/err.h>
  13. #include <linux/iio/iio.h>
  14. #include <linux/iio/buffer.h>
  15. #include <linux/iio/buffer-dma.h>
  16. #include <linux/iio/buffer-dmaengine.h>
  17. /*
  18. * The IIO DMAengine buffer combines the generic IIO DMA buffer infrastructure
  19. * with the DMAengine framework. The generic IIO DMA buffer infrastructure is
  20. * used to manage the buffer memory and implement the IIO buffer operations
  21. * while the DMAengine framework is used to perform the DMA transfers. Combined
  22. * this results in a device independent fully functional DMA buffer
  23. * implementation that can be used by device drivers for peripherals which are
  24. * connected to a DMA controller which has a DMAengine driver implementation.
  25. */
  26. struct dmaengine_buffer {
  27. struct iio_dma_buffer_queue queue;
  28. struct dma_chan *chan;
  29. struct list_head active;
  30. size_t align;
  31. size_t max_size;
  32. };
  33. static struct dmaengine_buffer *iio_buffer_to_dmaengine_buffer(
  34. struct iio_buffer *buffer)
  35. {
  36. return container_of(buffer, struct dmaengine_buffer, queue.buffer);
  37. }
  38. static void iio_dmaengine_buffer_block_done(void *data)
  39. {
  40. struct iio_dma_buffer_block *block = data;
  41. unsigned long flags;
  42. spin_lock_irqsave(&block->queue->list_lock, flags);
  43. list_del(&block->head);
  44. spin_unlock_irqrestore(&block->queue->list_lock, flags);
  45. iio_dma_buffer_block_done(block);
  46. }
  47. static int iio_dmaengine_buffer_submit_block(struct iio_dma_buffer_queue *queue,
  48. struct iio_dma_buffer_block *block)
  49. {
  50. struct dmaengine_buffer *dmaengine_buffer =
  51. iio_buffer_to_dmaengine_buffer(&queue->buffer);
  52. struct dma_async_tx_descriptor *desc;
  53. dma_cookie_t cookie;
  54. block->bytes_used = min(block->size, dmaengine_buffer->max_size);
  55. block->bytes_used = rounddown(block->bytes_used,
  56. dmaengine_buffer->align);
  57. desc = dmaengine_prep_slave_single(dmaengine_buffer->chan,
  58. block->phys_addr, block->bytes_used, DMA_DEV_TO_MEM,
  59. DMA_PREP_INTERRUPT);
  60. if (!desc)
  61. return -ENOMEM;
  62. desc->callback = iio_dmaengine_buffer_block_done;
  63. desc->callback_param = block;
  64. cookie = dmaengine_submit(desc);
  65. if (dma_submit_error(cookie))
  66. return dma_submit_error(cookie);
  67. spin_lock_irq(&dmaengine_buffer->queue.list_lock);
  68. list_add_tail(&block->head, &dmaengine_buffer->active);
  69. spin_unlock_irq(&dmaengine_buffer->queue.list_lock);
  70. dma_async_issue_pending(dmaengine_buffer->chan);
  71. return 0;
  72. }
  73. static void iio_dmaengine_buffer_abort(struct iio_dma_buffer_queue *queue)
  74. {
  75. struct dmaengine_buffer *dmaengine_buffer =
  76. iio_buffer_to_dmaengine_buffer(&queue->buffer);
  77. dmaengine_terminate_sync(dmaengine_buffer->chan);
  78. iio_dma_buffer_block_list_abort(queue, &dmaengine_buffer->active);
  79. }
  80. static void iio_dmaengine_buffer_release(struct iio_buffer *buf)
  81. {
  82. struct dmaengine_buffer *dmaengine_buffer =
  83. iio_buffer_to_dmaengine_buffer(buf);
  84. iio_dma_buffer_release(&dmaengine_buffer->queue);
  85. kfree(dmaengine_buffer);
  86. }
  87. static const struct iio_buffer_access_funcs iio_dmaengine_buffer_ops = {
  88. .read_first_n = iio_dma_buffer_read,
  89. .set_bytes_per_datum = iio_dma_buffer_set_bytes_per_datum,
  90. .set_length = iio_dma_buffer_set_length,
  91. .request_update = iio_dma_buffer_request_update,
  92. .enable = iio_dma_buffer_enable,
  93. .disable = iio_dma_buffer_disable,
  94. .data_available = iio_dma_buffer_data_available,
  95. .release = iio_dmaengine_buffer_release,
  96. .modes = INDIO_BUFFER_HARDWARE,
  97. .flags = INDIO_BUFFER_FLAG_FIXED_WATERMARK,
  98. };
  99. static const struct iio_dma_buffer_ops iio_dmaengine_default_ops = {
  100. .submit = iio_dmaengine_buffer_submit_block,
  101. .abort = iio_dmaengine_buffer_abort,
  102. };
  103. /**
  104. * iio_dmaengine_buffer_alloc() - Allocate new buffer which uses DMAengine
  105. * @dev: Parent device for the buffer
  106. * @channel: DMA channel name, typically "rx".
  107. *
  108. * This allocates a new IIO buffer which internally uses the DMAengine framework
  109. * to perform its transfers. The parent device will be used to request the DMA
  110. * channel.
  111. *
  112. * Once done using the buffer iio_dmaengine_buffer_free() should be used to
  113. * release it.
  114. */
  115. struct iio_buffer *iio_dmaengine_buffer_alloc(struct device *dev,
  116. const char *channel)
  117. {
  118. struct dmaengine_buffer *dmaengine_buffer;
  119. unsigned int width, src_width, dest_width;
  120. struct dma_slave_caps caps;
  121. struct dma_chan *chan;
  122. int ret;
  123. dmaengine_buffer = kzalloc(sizeof(*dmaengine_buffer), GFP_KERNEL);
  124. if (!dmaengine_buffer)
  125. return ERR_PTR(-ENOMEM);
  126. chan = dma_request_slave_channel_reason(dev, channel);
  127. if (IS_ERR(chan)) {
  128. ret = PTR_ERR(chan);
  129. goto err_free;
  130. }
  131. ret = dma_get_slave_caps(chan, &caps);
  132. if (ret < 0)
  133. goto err_free;
  134. /* Needs to be aligned to the maximum of the minimums */
  135. if (caps.src_addr_widths)
  136. src_width = __ffs(caps.src_addr_widths);
  137. else
  138. src_width = 1;
  139. if (caps.dst_addr_widths)
  140. dest_width = __ffs(caps.dst_addr_widths);
  141. else
  142. dest_width = 1;
  143. width = max(src_width, dest_width);
  144. INIT_LIST_HEAD(&dmaengine_buffer->active);
  145. dmaengine_buffer->chan = chan;
  146. dmaengine_buffer->align = width;
  147. dmaengine_buffer->max_size = dma_get_max_seg_size(chan->device->dev);
  148. iio_dma_buffer_init(&dmaengine_buffer->queue, chan->device->dev,
  149. &iio_dmaengine_default_ops);
  150. dmaengine_buffer->queue.buffer.access = &iio_dmaengine_buffer_ops;
  151. return &dmaengine_buffer->queue.buffer;
  152. err_free:
  153. kfree(dmaengine_buffer);
  154. return ERR_PTR(ret);
  155. }
  156. EXPORT_SYMBOL(iio_dmaengine_buffer_alloc);
  157. /**
  158. * iio_dmaengine_buffer_free() - Free dmaengine buffer
  159. * @buffer: Buffer to free
  160. *
  161. * Frees a buffer previously allocated with iio_dmaengine_buffer_alloc().
  162. */
  163. void iio_dmaengine_buffer_free(struct iio_buffer *buffer)
  164. {
  165. struct dmaengine_buffer *dmaengine_buffer =
  166. iio_buffer_to_dmaengine_buffer(buffer);
  167. iio_dma_buffer_exit(&dmaengine_buffer->queue);
  168. dma_release_channel(dmaengine_buffer->chan);
  169. iio_buffer_put(buffer);
  170. }
  171. EXPORT_SYMBOL_GPL(iio_dmaengine_buffer_free);