ti-cpufreq.c 8.2 KB

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  1. /*
  2. * TI CPUFreq/OPP hw-supported driver
  3. *
  4. * Copyright (C) 2016 Texas Instruments, Inc.
  5. * Dave Gerlach <d-gerlach@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/io.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/pm_opp.h>
  23. #include <linux/regmap.h>
  24. #include <linux/slab.h>
  25. #define REVISION_MASK 0xF
  26. #define REVISION_SHIFT 28
  27. #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
  28. #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
  29. #define DRA7_EFUSE_HAS_OD_MPU_OPP 11
  30. #define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15
  31. #define DRA76_EFUSE_HAS_PLUS_MPU_OPP 18
  32. #define DRA7_EFUSE_HAS_ALL_MPU_OPP 23
  33. #define DRA76_EFUSE_HAS_ALL_MPU_OPP 24
  34. #define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
  35. #define DRA7_EFUSE_OD_MPU_OPP BIT(1)
  36. #define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
  37. #define DRA76_EFUSE_PLUS_MPU_OPP BIT(3)
  38. #define VERSION_COUNT 2
  39. struct ti_cpufreq_data;
  40. struct ti_cpufreq_soc_data {
  41. unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data,
  42. unsigned long efuse);
  43. unsigned long efuse_fallback;
  44. bool multi_regulator;
  45. };
  46. struct ti_cpufreq_data {
  47. struct device *cpu_dev;
  48. struct device_node *opp_node;
  49. struct regmap *opp_efuse;
  50. struct regmap *revision;
  51. const struct ti_cpufreq_soc_data *soc_data;
  52. };
  53. static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data,
  54. unsigned long efuse)
  55. {
  56. if (!efuse)
  57. efuse = opp_data->soc_data->efuse_fallback;
  58. /* AM335x and AM437x use "OPP disable" bits, so invert */
  59. return ~efuse;
  60. }
  61. static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
  62. unsigned long efuse)
  63. {
  64. unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP;
  65. /*
  66. * The efuse on dra7 and am57 parts contains a specific
  67. * value indicating the highest available OPP.
  68. */
  69. switch (efuse) {
  70. case DRA76_EFUSE_HAS_PLUS_MPU_OPP:
  71. case DRA76_EFUSE_HAS_ALL_MPU_OPP:
  72. calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP;
  73. case DRA7_EFUSE_HAS_ALL_MPU_OPP:
  74. case DRA7_EFUSE_HAS_HIGH_MPU_OPP:
  75. calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;
  76. case DRA7_EFUSE_HAS_OD_MPU_OPP:
  77. calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP;
  78. }
  79. return calculated_efuse;
  80. }
  81. static struct ti_cpufreq_soc_data am3x_soc_data = {
  82. .efuse_xlate = amx3_efuse_xlate,
  83. .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
  84. .multi_regulator = false,
  85. };
  86. static struct ti_cpufreq_soc_data am4x_soc_data = {
  87. .efuse_xlate = amx3_efuse_xlate,
  88. .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ,
  89. .multi_regulator = false,
  90. };
  91. static struct ti_cpufreq_soc_data dra7_soc_data = {
  92. .efuse_xlate = dra7_efuse_xlate,
  93. .multi_regulator = true,
  94. };
  95. /**
  96. * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
  97. * @opp_data: pointer to ti_cpufreq_data context
  98. * @efuse_value: Set to the value parsed from efuse
  99. *
  100. * Returns error code if efuse not read properly.
  101. */
  102. static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
  103. u32 *efuse_value)
  104. {
  105. struct device *dev = opp_data->cpu_dev;
  106. struct device_node *np = opp_data->opp_node;
  107. unsigned int efuse_offset;
  108. u32 efuse, efuse_mask, efuse_shift, vals[4];
  109. int ret;
  110. ret = of_property_read_u32_array(np, "ti,syscon-efuse", vals, 4);
  111. if (ret) {
  112. dev_err(dev, "ti,syscon-efuse cannot be read %s: %d\n",
  113. np->full_name, ret);
  114. return ret;
  115. }
  116. efuse_offset = vals[1];
  117. efuse_mask = vals[2];
  118. efuse_shift = vals[3];
  119. ret = regmap_read(opp_data->opp_efuse, efuse_offset, &efuse);
  120. if (ret) {
  121. dev_err(dev,
  122. "Failed to read the efuse value from syscon: %d\n",
  123. ret);
  124. return ret;
  125. }
  126. efuse = (efuse & efuse_mask) >> efuse_shift;
  127. *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse);
  128. return 0;
  129. }
  130. /**
  131. * ti_cpufreq_get_rev() - Parse and return rev value present on SoC
  132. * @opp_data: pointer to ti_cpufreq_data context
  133. * @revision_value: Set to the value parsed from revision register
  134. *
  135. * Returns error code if revision not read properly.
  136. */
  137. static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
  138. u32 *revision_value)
  139. {
  140. struct device *dev = opp_data->cpu_dev;
  141. struct device_node *np = opp_data->opp_node;
  142. unsigned int revision_offset;
  143. u32 revision;
  144. int ret;
  145. ret = of_property_read_u32_index(np, "ti,syscon-rev",
  146. 1, &revision_offset);
  147. if (ret) {
  148. dev_err(dev,
  149. "No revision offset provided %s [%d]\n",
  150. np->full_name, ret);
  151. return ret;
  152. }
  153. ret = regmap_read(opp_data->revision, revision_offset, &revision);
  154. if (ret) {
  155. dev_err(dev,
  156. "Failed to read the revision number from syscon: %d\n",
  157. ret);
  158. return ret;
  159. }
  160. *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK);
  161. return 0;
  162. }
  163. static int ti_cpufreq_setup_syscon_registers(struct ti_cpufreq_data *opp_data)
  164. {
  165. struct device *dev = opp_data->cpu_dev;
  166. struct device_node *np = opp_data->opp_node;
  167. opp_data->opp_efuse = syscon_regmap_lookup_by_phandle(np,
  168. "ti,syscon-efuse");
  169. if (IS_ERR(opp_data->opp_efuse)) {
  170. dev_err(dev,
  171. "\"ti,syscon-efuse\" is missing, cannot use OPPv2 table.\n");
  172. return PTR_ERR(opp_data->opp_efuse);
  173. }
  174. opp_data->revision = syscon_regmap_lookup_by_phandle(np,
  175. "ti,syscon-rev");
  176. if (IS_ERR(opp_data->revision)) {
  177. dev_err(dev,
  178. "\"ti,syscon-rev\" is missing, cannot use OPPv2 table.\n");
  179. return PTR_ERR(opp_data->revision);
  180. }
  181. return 0;
  182. }
  183. static const struct of_device_id ti_cpufreq_of_match[] = {
  184. { .compatible = "ti,am33xx", .data = &am3x_soc_data, },
  185. { .compatible = "ti,am43", .data = &am4x_soc_data, },
  186. { .compatible = "ti,dra7", .data = &dra7_soc_data },
  187. {},
  188. };
  189. static int ti_cpufreq_probe(struct platform_device *pdev)
  190. {
  191. u32 version[VERSION_COUNT];
  192. struct device_node *np;
  193. const struct of_device_id *match;
  194. struct opp_table *ti_opp_table;
  195. struct ti_cpufreq_data *opp_data;
  196. const char * const reg_names[] = {"vdd", "vbb"};
  197. int ret;
  198. np = of_find_node_by_path("/");
  199. match = of_match_node(ti_cpufreq_of_match, np);
  200. if (!match)
  201. return -ENODEV;
  202. opp_data = kzalloc(sizeof(*opp_data), GFP_KERNEL);
  203. if (!opp_data)
  204. return -ENOMEM;
  205. opp_data->soc_data = match->data;
  206. opp_data->cpu_dev = get_cpu_device(0);
  207. if (!opp_data->cpu_dev) {
  208. pr_err("%s: Failed to get device for CPU0\n", __func__);
  209. return -ENODEV;
  210. }
  211. opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev);
  212. if (!opp_data->opp_node) {
  213. dev_info(opp_data->cpu_dev,
  214. "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n");
  215. goto register_cpufreq_dt;
  216. }
  217. ret = ti_cpufreq_setup_syscon_registers(opp_data);
  218. if (ret)
  219. goto fail_put_node;
  220. /*
  221. * OPPs determine whether or not they are supported based on
  222. * two metrics:
  223. * 0 - SoC Revision
  224. * 1 - eFuse value
  225. */
  226. ret = ti_cpufreq_get_rev(opp_data, &version[0]);
  227. if (ret)
  228. goto fail_put_node;
  229. ret = ti_cpufreq_get_efuse(opp_data, &version[1]);
  230. if (ret)
  231. goto fail_put_node;
  232. of_node_put(opp_data->opp_node);
  233. ret = dev_pm_opp_set_supported_hw(opp_data->cpu_dev, version,
  234. VERSION_COUNT);
  235. if (ret) {
  236. dev_err(opp_data->cpu_dev,
  237. "Failed to set supported hardware\n");
  238. goto fail_put_node;
  239. }
  240. if (opp_data->soc_data->multi_regulator) {
  241. ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev,
  242. reg_names,
  243. ARRAY_SIZE(reg_names));
  244. if (IS_ERR(ti_opp_table)) {
  245. dev_pm_opp_put_supported_hw(opp_data->cpu_dev);
  246. return PTR_ERR(ti_opp_table);
  247. }
  248. }
  249. register_cpufreq_dt:
  250. platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
  251. return 0;
  252. fail_put_node:
  253. of_node_put(opp_data->opp_node);
  254. return ret;
  255. }
  256. static int ti_cpufreq_init(void)
  257. {
  258. platform_device_register_simple("ti-cpufreq", -1, NULL, 0);
  259. return 0;
  260. }
  261. module_init(ti_cpufreq_init);
  262. static struct platform_driver ti_cpufreq_driver = {
  263. .probe = ti_cpufreq_probe,
  264. .driver = {
  265. .name = "ti-cpufreq",
  266. },
  267. };
  268. module_platform_driver(ti_cpufreq_driver);
  269. MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver");
  270. MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
  271. MODULE_LICENSE("GPL v2");