powernv-cpufreq.c 27 KB

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  1. /*
  2. * POWERNV cpufreq driver for the IBM POWER processors
  3. *
  4. * (C) Copyright IBM 2014
  5. *
  6. * Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. */
  19. #define pr_fmt(fmt) "powernv-cpufreq: " fmt
  20. #include <linux/kernel.h>
  21. #include <linux/sysfs.h>
  22. #include <linux/cpumask.h>
  23. #include <linux/module.h>
  24. #include <linux/cpufreq.h>
  25. #include <linux/smp.h>
  26. #include <linux/of.h>
  27. #include <linux/reboot.h>
  28. #include <linux/slab.h>
  29. #include <linux/cpu.h>
  30. #include <trace/events/power.h>
  31. #include <asm/cputhreads.h>
  32. #include <asm/firmware.h>
  33. #include <asm/reg.h>
  34. #include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */
  35. #include <asm/opal.h>
  36. #include <linux/timer.h>
  37. #define POWERNV_MAX_PSTATES 256
  38. #define PMSR_PSAFE_ENABLE (1UL << 30)
  39. #define PMSR_SPR_EM_DISABLE (1UL << 31)
  40. #define PMSR_MAX(x) ((x >> 32) & 0xFF)
  41. #define MAX_RAMP_DOWN_TIME 5120
  42. /*
  43. * On an idle system we want the global pstate to ramp-down from max value to
  44. * min over a span of ~5 secs. Also we want it to initially ramp-down slowly and
  45. * then ramp-down rapidly later on.
  46. *
  47. * This gives a percentage rampdown for time elapsed in milliseconds.
  48. * ramp_down_percentage = ((ms * ms) >> 18)
  49. * ~= 3.8 * (sec * sec)
  50. *
  51. * At 0 ms ramp_down_percent = 0
  52. * At 5120 ms ramp_down_percent = 100
  53. */
  54. #define ramp_down_percent(time) ((time * time) >> 18)
  55. /* Interval after which the timer is queued to bring down global pstate */
  56. #define GPSTATE_TIMER_INTERVAL 2000
  57. /**
  58. * struct global_pstate_info - Per policy data structure to maintain history of
  59. * global pstates
  60. * @highest_lpstate_idx: The local pstate index from which we are
  61. * ramping down
  62. * @elapsed_time: Time in ms spent in ramping down from
  63. * highest_lpstate_idx
  64. * @last_sampled_time: Time from boot in ms when global pstates were
  65. * last set
  66. * @last_lpstate_idx, Last set value of local pstate and global
  67. * last_gpstate_idx pstate in terms of cpufreq table index
  68. * @timer: Is used for ramping down if cpu goes idle for
  69. * a long time with global pstate held high
  70. * @gpstate_lock: A spinlock to maintain synchronization between
  71. * routines called by the timer handler and
  72. * governer's target_index calls
  73. */
  74. struct global_pstate_info {
  75. int highest_lpstate_idx;
  76. unsigned int elapsed_time;
  77. unsigned int last_sampled_time;
  78. int last_lpstate_idx;
  79. int last_gpstate_idx;
  80. spinlock_t gpstate_lock;
  81. struct timer_list timer;
  82. };
  83. static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1];
  84. static bool rebooting, throttled, occ_reset;
  85. static const char * const throttle_reason[] = {
  86. "No throttling",
  87. "Power Cap",
  88. "Processor Over Temperature",
  89. "Power Supply Failure",
  90. "Over Current",
  91. "OCC Reset"
  92. };
  93. enum throttle_reason_type {
  94. NO_THROTTLE = 0,
  95. POWERCAP,
  96. CPU_OVERTEMP,
  97. POWER_SUPPLY_FAILURE,
  98. OVERCURRENT,
  99. OCC_RESET_THROTTLE,
  100. OCC_MAX_REASON
  101. };
  102. static struct chip {
  103. unsigned int id;
  104. bool throttled;
  105. bool restore;
  106. u8 throttle_reason;
  107. cpumask_t mask;
  108. struct work_struct throttle;
  109. int throttle_turbo;
  110. int throttle_sub_turbo;
  111. int reason[OCC_MAX_REASON];
  112. } *chips;
  113. static int nr_chips;
  114. static DEFINE_PER_CPU(struct chip *, chip_info);
  115. /*
  116. * Note:
  117. * The set of pstates consists of contiguous integers.
  118. * powernv_pstate_info stores the index of the frequency table for
  119. * max, min and nominal frequencies. It also stores number of
  120. * available frequencies.
  121. *
  122. * powernv_pstate_info.nominal indicates the index to the highest
  123. * non-turbo frequency.
  124. */
  125. static struct powernv_pstate_info {
  126. unsigned int min;
  127. unsigned int max;
  128. unsigned int nominal;
  129. unsigned int nr_pstates;
  130. } powernv_pstate_info;
  131. /* Use following macros for conversions between pstate_id and index */
  132. static inline int idx_to_pstate(unsigned int i)
  133. {
  134. if (unlikely(i >= powernv_pstate_info.nr_pstates)) {
  135. pr_warn_once("index %u is out of bound\n", i);
  136. return powernv_freqs[powernv_pstate_info.nominal].driver_data;
  137. }
  138. return powernv_freqs[i].driver_data;
  139. }
  140. static inline unsigned int pstate_to_idx(int pstate)
  141. {
  142. int min = powernv_freqs[powernv_pstate_info.min].driver_data;
  143. int max = powernv_freqs[powernv_pstate_info.max].driver_data;
  144. if (min > 0) {
  145. if (unlikely((pstate < max) || (pstate > min))) {
  146. pr_warn_once("pstate %d is out of bound\n", pstate);
  147. return powernv_pstate_info.nominal;
  148. }
  149. } else {
  150. if (unlikely((pstate > max) || (pstate < min))) {
  151. pr_warn_once("pstate %d is out of bound\n", pstate);
  152. return powernv_pstate_info.nominal;
  153. }
  154. }
  155. /*
  156. * abs() is deliberately used so that is works with
  157. * both monotonically increasing and decreasing
  158. * pstate values
  159. */
  160. return abs(pstate - idx_to_pstate(powernv_pstate_info.max));
  161. }
  162. static inline void reset_gpstates(struct cpufreq_policy *policy)
  163. {
  164. struct global_pstate_info *gpstates = policy->driver_data;
  165. gpstates->highest_lpstate_idx = 0;
  166. gpstates->elapsed_time = 0;
  167. gpstates->last_sampled_time = 0;
  168. gpstates->last_lpstate_idx = 0;
  169. gpstates->last_gpstate_idx = 0;
  170. }
  171. /*
  172. * Initialize the freq table based on data obtained
  173. * from the firmware passed via device-tree
  174. */
  175. static int init_powernv_pstates(void)
  176. {
  177. struct device_node *power_mgt;
  178. int i, nr_pstates = 0;
  179. const __be32 *pstate_ids, *pstate_freqs;
  180. u32 len_ids, len_freqs;
  181. u32 pstate_min, pstate_max, pstate_nominal;
  182. power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
  183. if (!power_mgt) {
  184. pr_warn("power-mgt node not found\n");
  185. return -ENODEV;
  186. }
  187. if (of_property_read_u32(power_mgt, "ibm,pstate-min", &pstate_min)) {
  188. pr_warn("ibm,pstate-min node not found\n");
  189. return -ENODEV;
  190. }
  191. if (of_property_read_u32(power_mgt, "ibm,pstate-max", &pstate_max)) {
  192. pr_warn("ibm,pstate-max node not found\n");
  193. return -ENODEV;
  194. }
  195. if (of_property_read_u32(power_mgt, "ibm,pstate-nominal",
  196. &pstate_nominal)) {
  197. pr_warn("ibm,pstate-nominal not found\n");
  198. return -ENODEV;
  199. }
  200. pr_info("cpufreq pstate min %d nominal %d max %d\n", pstate_min,
  201. pstate_nominal, pstate_max);
  202. pstate_ids = of_get_property(power_mgt, "ibm,pstate-ids", &len_ids);
  203. if (!pstate_ids) {
  204. pr_warn("ibm,pstate-ids not found\n");
  205. return -ENODEV;
  206. }
  207. pstate_freqs = of_get_property(power_mgt, "ibm,pstate-frequencies-mhz",
  208. &len_freqs);
  209. if (!pstate_freqs) {
  210. pr_warn("ibm,pstate-frequencies-mhz not found\n");
  211. return -ENODEV;
  212. }
  213. if (len_ids != len_freqs) {
  214. pr_warn("Entries in ibm,pstate-ids and "
  215. "ibm,pstate-frequencies-mhz does not match\n");
  216. }
  217. nr_pstates = min(len_ids, len_freqs) / sizeof(u32);
  218. if (!nr_pstates) {
  219. pr_warn("No PStates found\n");
  220. return -ENODEV;
  221. }
  222. powernv_pstate_info.nr_pstates = nr_pstates;
  223. pr_debug("NR PStates %d\n", nr_pstates);
  224. for (i = 0; i < nr_pstates; i++) {
  225. u32 id = be32_to_cpu(pstate_ids[i]);
  226. u32 freq = be32_to_cpu(pstate_freqs[i]);
  227. pr_debug("PState id %d freq %d MHz\n", id, freq);
  228. powernv_freqs[i].frequency = freq * 1000; /* kHz */
  229. powernv_freqs[i].driver_data = id;
  230. if (id == pstate_max)
  231. powernv_pstate_info.max = i;
  232. else if (id == pstate_nominal)
  233. powernv_pstate_info.nominal = i;
  234. else if (id == pstate_min)
  235. powernv_pstate_info.min = i;
  236. }
  237. /* End of list marker entry */
  238. powernv_freqs[i].frequency = CPUFREQ_TABLE_END;
  239. return 0;
  240. }
  241. /* Returns the CPU frequency corresponding to the pstate_id. */
  242. static unsigned int pstate_id_to_freq(int pstate_id)
  243. {
  244. int i;
  245. i = pstate_to_idx(pstate_id);
  246. if (i >= powernv_pstate_info.nr_pstates || i < 0) {
  247. pr_warn("PState id %d outside of PState table, "
  248. "reporting nominal id %d instead\n",
  249. pstate_id, idx_to_pstate(powernv_pstate_info.nominal));
  250. i = powernv_pstate_info.nominal;
  251. }
  252. return powernv_freqs[i].frequency;
  253. }
  254. /*
  255. * cpuinfo_nominal_freq_show - Show the nominal CPU frequency as indicated by
  256. * the firmware
  257. */
  258. static ssize_t cpuinfo_nominal_freq_show(struct cpufreq_policy *policy,
  259. char *buf)
  260. {
  261. return sprintf(buf, "%u\n",
  262. powernv_freqs[powernv_pstate_info.nominal].frequency);
  263. }
  264. struct freq_attr cpufreq_freq_attr_cpuinfo_nominal_freq =
  265. __ATTR_RO(cpuinfo_nominal_freq);
  266. static struct freq_attr *powernv_cpu_freq_attr[] = {
  267. &cpufreq_freq_attr_scaling_available_freqs,
  268. &cpufreq_freq_attr_cpuinfo_nominal_freq,
  269. NULL,
  270. };
  271. #define throttle_attr(name, member) \
  272. static ssize_t name##_show(struct cpufreq_policy *policy, char *buf) \
  273. { \
  274. struct chip *chip = per_cpu(chip_info, policy->cpu); \
  275. \
  276. return sprintf(buf, "%u\n", chip->member); \
  277. } \
  278. \
  279. static struct freq_attr throttle_attr_##name = __ATTR_RO(name) \
  280. throttle_attr(unthrottle, reason[NO_THROTTLE]);
  281. throttle_attr(powercap, reason[POWERCAP]);
  282. throttle_attr(overtemp, reason[CPU_OVERTEMP]);
  283. throttle_attr(supply_fault, reason[POWER_SUPPLY_FAILURE]);
  284. throttle_attr(overcurrent, reason[OVERCURRENT]);
  285. throttle_attr(occ_reset, reason[OCC_RESET_THROTTLE]);
  286. throttle_attr(turbo_stat, throttle_turbo);
  287. throttle_attr(sub_turbo_stat, throttle_sub_turbo);
  288. static struct attribute *throttle_attrs[] = {
  289. &throttle_attr_unthrottle.attr,
  290. &throttle_attr_powercap.attr,
  291. &throttle_attr_overtemp.attr,
  292. &throttle_attr_supply_fault.attr,
  293. &throttle_attr_overcurrent.attr,
  294. &throttle_attr_occ_reset.attr,
  295. &throttle_attr_turbo_stat.attr,
  296. &throttle_attr_sub_turbo_stat.attr,
  297. NULL,
  298. };
  299. static const struct attribute_group throttle_attr_grp = {
  300. .name = "throttle_stats",
  301. .attrs = throttle_attrs,
  302. };
  303. /* Helper routines */
  304. /* Access helpers to power mgt SPR */
  305. static inline unsigned long get_pmspr(unsigned long sprn)
  306. {
  307. switch (sprn) {
  308. case SPRN_PMCR:
  309. return mfspr(SPRN_PMCR);
  310. case SPRN_PMICR:
  311. return mfspr(SPRN_PMICR);
  312. case SPRN_PMSR:
  313. return mfspr(SPRN_PMSR);
  314. }
  315. BUG();
  316. }
  317. static inline void set_pmspr(unsigned long sprn, unsigned long val)
  318. {
  319. switch (sprn) {
  320. case SPRN_PMCR:
  321. mtspr(SPRN_PMCR, val);
  322. return;
  323. case SPRN_PMICR:
  324. mtspr(SPRN_PMICR, val);
  325. return;
  326. }
  327. BUG();
  328. }
  329. /*
  330. * Use objects of this type to query/update
  331. * pstates on a remote CPU via smp_call_function.
  332. */
  333. struct powernv_smp_call_data {
  334. unsigned int freq;
  335. int pstate_id;
  336. int gpstate_id;
  337. };
  338. /*
  339. * powernv_read_cpu_freq: Reads the current frequency on this CPU.
  340. *
  341. * Called via smp_call_function.
  342. *
  343. * Note: The caller of the smp_call_function should pass an argument of
  344. * the type 'struct powernv_smp_call_data *' along with this function.
  345. *
  346. * The current frequency on this CPU will be returned via
  347. * ((struct powernv_smp_call_data *)arg)->freq;
  348. */
  349. static void powernv_read_cpu_freq(void *arg)
  350. {
  351. unsigned long pmspr_val;
  352. s8 local_pstate_id;
  353. struct powernv_smp_call_data *freq_data = arg;
  354. pmspr_val = get_pmspr(SPRN_PMSR);
  355. /*
  356. * The local pstate id corresponds bits 48..55 in the PMSR.
  357. * Note: Watch out for the sign!
  358. */
  359. local_pstate_id = (pmspr_val >> 48) & 0xFF;
  360. freq_data->pstate_id = local_pstate_id;
  361. freq_data->freq = pstate_id_to_freq(freq_data->pstate_id);
  362. pr_debug("cpu %d pmsr %016lX pstate_id %d frequency %d kHz\n",
  363. raw_smp_processor_id(), pmspr_val, freq_data->pstate_id,
  364. freq_data->freq);
  365. }
  366. /*
  367. * powernv_cpufreq_get: Returns the CPU frequency as reported by the
  368. * firmware for CPU 'cpu'. This value is reported through the sysfs
  369. * file cpuinfo_cur_freq.
  370. */
  371. static unsigned int powernv_cpufreq_get(unsigned int cpu)
  372. {
  373. struct powernv_smp_call_data freq_data;
  374. smp_call_function_any(cpu_sibling_mask(cpu), powernv_read_cpu_freq,
  375. &freq_data, 1);
  376. return freq_data.freq;
  377. }
  378. /*
  379. * set_pstate: Sets the pstate on this CPU.
  380. *
  381. * This is called via an smp_call_function.
  382. *
  383. * The caller must ensure that freq_data is of the type
  384. * (struct powernv_smp_call_data *) and the pstate_id which needs to be set
  385. * on this CPU should be present in freq_data->pstate_id.
  386. */
  387. static void set_pstate(void *data)
  388. {
  389. unsigned long val;
  390. struct powernv_smp_call_data *freq_data = data;
  391. unsigned long pstate_ul = freq_data->pstate_id;
  392. unsigned long gpstate_ul = freq_data->gpstate_id;
  393. val = get_pmspr(SPRN_PMCR);
  394. val = val & 0x0000FFFFFFFFFFFFULL;
  395. pstate_ul = pstate_ul & 0xFF;
  396. gpstate_ul = gpstate_ul & 0xFF;
  397. /* Set both global(bits 56..63) and local(bits 48..55) PStates */
  398. val = val | (gpstate_ul << 56) | (pstate_ul << 48);
  399. pr_debug("Setting cpu %d pmcr to %016lX\n",
  400. raw_smp_processor_id(), val);
  401. set_pmspr(SPRN_PMCR, val);
  402. }
  403. /*
  404. * get_nominal_index: Returns the index corresponding to the nominal
  405. * pstate in the cpufreq table
  406. */
  407. static inline unsigned int get_nominal_index(void)
  408. {
  409. return powernv_pstate_info.nominal;
  410. }
  411. static void powernv_cpufreq_throttle_check(void *data)
  412. {
  413. struct chip *chip;
  414. unsigned int cpu = smp_processor_id();
  415. unsigned long pmsr;
  416. int pmsr_pmax;
  417. unsigned int pmsr_pmax_idx;
  418. pmsr = get_pmspr(SPRN_PMSR);
  419. chip = this_cpu_read(chip_info);
  420. /* Check for Pmax Capping */
  421. pmsr_pmax = (s8)PMSR_MAX(pmsr);
  422. pmsr_pmax_idx = pstate_to_idx(pmsr_pmax);
  423. if (pmsr_pmax_idx != powernv_pstate_info.max) {
  424. if (chip->throttled)
  425. goto next;
  426. chip->throttled = true;
  427. if (pmsr_pmax_idx > powernv_pstate_info.nominal) {
  428. pr_warn_once("CPU %d on Chip %u has Pmax(%d) reduced below nominal frequency(%d)\n",
  429. cpu, chip->id, pmsr_pmax,
  430. idx_to_pstate(powernv_pstate_info.nominal));
  431. chip->throttle_sub_turbo++;
  432. } else {
  433. chip->throttle_turbo++;
  434. }
  435. trace_powernv_throttle(chip->id,
  436. throttle_reason[chip->throttle_reason],
  437. pmsr_pmax);
  438. } else if (chip->throttled) {
  439. chip->throttled = false;
  440. trace_powernv_throttle(chip->id,
  441. throttle_reason[chip->throttle_reason],
  442. pmsr_pmax);
  443. }
  444. /* Check if Psafe_mode_active is set in PMSR. */
  445. next:
  446. if (pmsr & PMSR_PSAFE_ENABLE) {
  447. throttled = true;
  448. pr_info("Pstate set to safe frequency\n");
  449. }
  450. /* Check if SPR_EM_DISABLE is set in PMSR */
  451. if (pmsr & PMSR_SPR_EM_DISABLE) {
  452. throttled = true;
  453. pr_info("Frequency Control disabled from OS\n");
  454. }
  455. if (throttled) {
  456. pr_info("PMSR = %16lx\n", pmsr);
  457. pr_warn("CPU Frequency could be throttled\n");
  458. }
  459. }
  460. /**
  461. * calc_global_pstate - Calculate global pstate
  462. * @elapsed_time: Elapsed time in milliseconds
  463. * @local_pstate_idx: New local pstate
  464. * @highest_lpstate_idx: pstate from which its ramping down
  465. *
  466. * Finds the appropriate global pstate based on the pstate from which its
  467. * ramping down and the time elapsed in ramping down. It follows a quadratic
  468. * equation which ensures that it reaches ramping down to pmin in 5sec.
  469. */
  470. static inline int calc_global_pstate(unsigned int elapsed_time,
  471. int highest_lpstate_idx,
  472. int local_pstate_idx)
  473. {
  474. int index_diff;
  475. /*
  476. * Using ramp_down_percent we get the percentage of rampdown
  477. * that we are expecting to be dropping. Difference between
  478. * highest_lpstate_idx and powernv_pstate_info.min will give a absolute
  479. * number of how many pstates we will drop eventually by the end of
  480. * 5 seconds, then just scale it get the number pstates to be dropped.
  481. */
  482. index_diff = ((int)ramp_down_percent(elapsed_time) *
  483. (powernv_pstate_info.min - highest_lpstate_idx)) / 100;
  484. /* Ensure that global pstate is >= to local pstate */
  485. if (highest_lpstate_idx + index_diff >= local_pstate_idx)
  486. return local_pstate_idx;
  487. else
  488. return highest_lpstate_idx + index_diff;
  489. }
  490. static inline void queue_gpstate_timer(struct global_pstate_info *gpstates)
  491. {
  492. unsigned int timer_interval;
  493. /*
  494. * Setting up timer to fire after GPSTATE_TIMER_INTERVAL ms, But
  495. * if it exceeds MAX_RAMP_DOWN_TIME ms for ramp down time.
  496. * Set timer such that it fires exactly at MAX_RAMP_DOWN_TIME
  497. * seconds of ramp down time.
  498. */
  499. if ((gpstates->elapsed_time + GPSTATE_TIMER_INTERVAL)
  500. > MAX_RAMP_DOWN_TIME)
  501. timer_interval = MAX_RAMP_DOWN_TIME - gpstates->elapsed_time;
  502. else
  503. timer_interval = GPSTATE_TIMER_INTERVAL;
  504. mod_timer(&gpstates->timer, jiffies + msecs_to_jiffies(timer_interval));
  505. }
  506. /**
  507. * gpstate_timer_handler
  508. *
  509. * @data: pointer to cpufreq_policy on which timer was queued
  510. *
  511. * This handler brings down the global pstate closer to the local pstate
  512. * according quadratic equation. Queues a new timer if it is still not equal
  513. * to local pstate
  514. */
  515. void gpstate_timer_handler(unsigned long data)
  516. {
  517. struct cpufreq_policy *policy = (struct cpufreq_policy *)data;
  518. struct global_pstate_info *gpstates = policy->driver_data;
  519. int gpstate_idx;
  520. unsigned int time_diff = jiffies_to_msecs(jiffies)
  521. - gpstates->last_sampled_time;
  522. struct powernv_smp_call_data freq_data;
  523. if (!spin_trylock(&gpstates->gpstate_lock))
  524. return;
  525. gpstates->last_sampled_time += time_diff;
  526. gpstates->elapsed_time += time_diff;
  527. freq_data.pstate_id = idx_to_pstate(gpstates->last_lpstate_idx);
  528. if ((gpstates->last_gpstate_idx == gpstates->last_lpstate_idx) ||
  529. (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME)) {
  530. gpstate_idx = pstate_to_idx(freq_data.pstate_id);
  531. reset_gpstates(policy);
  532. gpstates->highest_lpstate_idx = gpstate_idx;
  533. } else {
  534. gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
  535. gpstates->highest_lpstate_idx,
  536. gpstates->last_lpstate_idx);
  537. }
  538. /*
  539. * If local pstate is equal to global pstate, rampdown is over
  540. * So timer is not required to be queued.
  541. */
  542. if (gpstate_idx != gpstates->last_lpstate_idx)
  543. queue_gpstate_timer(gpstates);
  544. freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
  545. gpstates->last_gpstate_idx = pstate_to_idx(freq_data.gpstate_id);
  546. gpstates->last_lpstate_idx = pstate_to_idx(freq_data.pstate_id);
  547. spin_unlock(&gpstates->gpstate_lock);
  548. /* Timer may get migrated to a different cpu on cpu hot unplug */
  549. smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
  550. }
  551. /*
  552. * powernv_cpufreq_target_index: Sets the frequency corresponding to
  553. * the cpufreq table entry indexed by new_index on the cpus in the
  554. * mask policy->cpus
  555. */
  556. static int powernv_cpufreq_target_index(struct cpufreq_policy *policy,
  557. unsigned int new_index)
  558. {
  559. struct powernv_smp_call_data freq_data;
  560. unsigned int cur_msec, gpstate_idx;
  561. struct global_pstate_info *gpstates = policy->driver_data;
  562. if (unlikely(rebooting) && new_index != get_nominal_index())
  563. return 0;
  564. if (!throttled) {
  565. /* we don't want to be preempted while
  566. * checking if the CPU frequency has been throttled
  567. */
  568. preempt_disable();
  569. powernv_cpufreq_throttle_check(NULL);
  570. preempt_enable();
  571. }
  572. cur_msec = jiffies_to_msecs(get_jiffies_64());
  573. spin_lock(&gpstates->gpstate_lock);
  574. freq_data.pstate_id = idx_to_pstate(new_index);
  575. if (!gpstates->last_sampled_time) {
  576. gpstate_idx = new_index;
  577. gpstates->highest_lpstate_idx = new_index;
  578. goto gpstates_done;
  579. }
  580. if (gpstates->last_gpstate_idx < new_index) {
  581. gpstates->elapsed_time += cur_msec -
  582. gpstates->last_sampled_time;
  583. /*
  584. * If its has been ramping down for more than MAX_RAMP_DOWN_TIME
  585. * we should be resetting all global pstate related data. Set it
  586. * equal to local pstate to start fresh.
  587. */
  588. if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) {
  589. reset_gpstates(policy);
  590. gpstates->highest_lpstate_idx = new_index;
  591. gpstate_idx = new_index;
  592. } else {
  593. /* Elaspsed_time is less than 5 seconds, continue to rampdown */
  594. gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
  595. gpstates->highest_lpstate_idx,
  596. new_index);
  597. }
  598. } else {
  599. reset_gpstates(policy);
  600. gpstates->highest_lpstate_idx = new_index;
  601. gpstate_idx = new_index;
  602. }
  603. /*
  604. * If local pstate is equal to global pstate, rampdown is over
  605. * So timer is not required to be queued.
  606. */
  607. if (gpstate_idx != new_index)
  608. queue_gpstate_timer(gpstates);
  609. else
  610. del_timer_sync(&gpstates->timer);
  611. gpstates_done:
  612. freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
  613. gpstates->last_sampled_time = cur_msec;
  614. gpstates->last_gpstate_idx = gpstate_idx;
  615. gpstates->last_lpstate_idx = new_index;
  616. spin_unlock(&gpstates->gpstate_lock);
  617. /*
  618. * Use smp_call_function to send IPI and execute the
  619. * mtspr on target CPU. We could do that without IPI
  620. * if current CPU is within policy->cpus (core)
  621. */
  622. smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
  623. return 0;
  624. }
  625. static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy)
  626. {
  627. int base, i, ret;
  628. struct kernfs_node *kn;
  629. struct global_pstate_info *gpstates;
  630. base = cpu_first_thread_sibling(policy->cpu);
  631. for (i = 0; i < threads_per_core; i++)
  632. cpumask_set_cpu(base + i, policy->cpus);
  633. kn = kernfs_find_and_get(policy->kobj.sd, throttle_attr_grp.name);
  634. if (!kn) {
  635. int ret;
  636. ret = sysfs_create_group(&policy->kobj, &throttle_attr_grp);
  637. if (ret) {
  638. pr_info("Failed to create throttle stats directory for cpu %d\n",
  639. policy->cpu);
  640. return ret;
  641. }
  642. } else {
  643. kernfs_put(kn);
  644. }
  645. gpstates = kzalloc(sizeof(*gpstates), GFP_KERNEL);
  646. if (!gpstates)
  647. return -ENOMEM;
  648. policy->driver_data = gpstates;
  649. /* initialize timer */
  650. init_timer_pinned_deferrable(&gpstates->timer);
  651. gpstates->timer.data = (unsigned long)policy;
  652. gpstates->timer.function = gpstate_timer_handler;
  653. gpstates->timer.expires = jiffies +
  654. msecs_to_jiffies(GPSTATE_TIMER_INTERVAL);
  655. spin_lock_init(&gpstates->gpstate_lock);
  656. ret = cpufreq_table_validate_and_show(policy, powernv_freqs);
  657. if (ret < 0)
  658. kfree(policy->driver_data);
  659. return ret;
  660. }
  661. static int powernv_cpufreq_cpu_exit(struct cpufreq_policy *policy)
  662. {
  663. /* timer is deleted in cpufreq_cpu_stop() */
  664. kfree(policy->driver_data);
  665. return 0;
  666. }
  667. static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb,
  668. unsigned long action, void *unused)
  669. {
  670. int cpu;
  671. struct cpufreq_policy cpu_policy;
  672. rebooting = true;
  673. for_each_online_cpu(cpu) {
  674. cpufreq_get_policy(&cpu_policy, cpu);
  675. powernv_cpufreq_target_index(&cpu_policy, get_nominal_index());
  676. }
  677. return NOTIFY_DONE;
  678. }
  679. static struct notifier_block powernv_cpufreq_reboot_nb = {
  680. .notifier_call = powernv_cpufreq_reboot_notifier,
  681. };
  682. void powernv_cpufreq_work_fn(struct work_struct *work)
  683. {
  684. struct chip *chip = container_of(work, struct chip, throttle);
  685. unsigned int cpu;
  686. cpumask_t mask;
  687. get_online_cpus();
  688. cpumask_and(&mask, &chip->mask, cpu_online_mask);
  689. smp_call_function_any(&mask,
  690. powernv_cpufreq_throttle_check, NULL, 0);
  691. if (!chip->restore)
  692. goto out;
  693. chip->restore = false;
  694. for_each_cpu(cpu, &mask) {
  695. int index;
  696. struct cpufreq_policy policy;
  697. cpufreq_get_policy(&policy, cpu);
  698. index = cpufreq_table_find_index_c(&policy, policy.cur);
  699. powernv_cpufreq_target_index(&policy, index);
  700. cpumask_andnot(&mask, &mask, policy.cpus);
  701. }
  702. out:
  703. put_online_cpus();
  704. }
  705. static int powernv_cpufreq_occ_msg(struct notifier_block *nb,
  706. unsigned long msg_type, void *_msg)
  707. {
  708. struct opal_msg *msg = _msg;
  709. struct opal_occ_msg omsg;
  710. int i;
  711. if (msg_type != OPAL_MSG_OCC)
  712. return 0;
  713. omsg.type = be64_to_cpu(msg->params[0]);
  714. switch (omsg.type) {
  715. case OCC_RESET:
  716. occ_reset = true;
  717. pr_info("OCC (On Chip Controller - enforces hard thermal/power limits) Resetting\n");
  718. /*
  719. * powernv_cpufreq_throttle_check() is called in
  720. * target() callback which can detect the throttle state
  721. * for governors like ondemand.
  722. * But static governors will not call target() often thus
  723. * report throttling here.
  724. */
  725. if (!throttled) {
  726. throttled = true;
  727. pr_warn("CPU frequency is throttled for duration\n");
  728. }
  729. break;
  730. case OCC_LOAD:
  731. pr_info("OCC Loading, CPU frequency is throttled until OCC is started\n");
  732. break;
  733. case OCC_THROTTLE:
  734. omsg.chip = be64_to_cpu(msg->params[1]);
  735. omsg.throttle_status = be64_to_cpu(msg->params[2]);
  736. if (occ_reset) {
  737. occ_reset = false;
  738. throttled = false;
  739. pr_info("OCC Active, CPU frequency is no longer throttled\n");
  740. for (i = 0; i < nr_chips; i++) {
  741. chips[i].restore = true;
  742. schedule_work(&chips[i].throttle);
  743. }
  744. return 0;
  745. }
  746. for (i = 0; i < nr_chips; i++)
  747. if (chips[i].id == omsg.chip)
  748. break;
  749. if (omsg.throttle_status >= 0 &&
  750. omsg.throttle_status <= OCC_MAX_THROTTLE_STATUS) {
  751. chips[i].throttle_reason = omsg.throttle_status;
  752. chips[i].reason[omsg.throttle_status]++;
  753. }
  754. if (!omsg.throttle_status)
  755. chips[i].restore = true;
  756. schedule_work(&chips[i].throttle);
  757. }
  758. return 0;
  759. }
  760. static struct notifier_block powernv_cpufreq_opal_nb = {
  761. .notifier_call = powernv_cpufreq_occ_msg,
  762. .next = NULL,
  763. .priority = 0,
  764. };
  765. static void powernv_cpufreq_stop_cpu(struct cpufreq_policy *policy)
  766. {
  767. struct powernv_smp_call_data freq_data;
  768. struct global_pstate_info *gpstates = policy->driver_data;
  769. freq_data.pstate_id = idx_to_pstate(powernv_pstate_info.min);
  770. freq_data.gpstate_id = idx_to_pstate(powernv_pstate_info.min);
  771. smp_call_function_single(policy->cpu, set_pstate, &freq_data, 1);
  772. del_timer_sync(&gpstates->timer);
  773. }
  774. static struct cpufreq_driver powernv_cpufreq_driver = {
  775. .name = "powernv-cpufreq",
  776. .flags = CPUFREQ_CONST_LOOPS,
  777. .init = powernv_cpufreq_cpu_init,
  778. .exit = powernv_cpufreq_cpu_exit,
  779. .verify = cpufreq_generic_frequency_table_verify,
  780. .target_index = powernv_cpufreq_target_index,
  781. .get = powernv_cpufreq_get,
  782. .stop_cpu = powernv_cpufreq_stop_cpu,
  783. .attr = powernv_cpu_freq_attr,
  784. };
  785. static int init_chip_info(void)
  786. {
  787. unsigned int chip[256];
  788. unsigned int cpu, i;
  789. unsigned int prev_chip_id = UINT_MAX;
  790. for_each_possible_cpu(cpu) {
  791. unsigned int id = cpu_to_chip_id(cpu);
  792. if (prev_chip_id != id) {
  793. prev_chip_id = id;
  794. chip[nr_chips++] = id;
  795. }
  796. }
  797. chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL);
  798. if (!chips)
  799. return -ENOMEM;
  800. for (i = 0; i < nr_chips; i++) {
  801. chips[i].id = chip[i];
  802. cpumask_copy(&chips[i].mask, cpumask_of_node(chip[i]));
  803. INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn);
  804. for_each_cpu(cpu, &chips[i].mask)
  805. per_cpu(chip_info, cpu) = &chips[i];
  806. }
  807. return 0;
  808. }
  809. static inline void clean_chip_info(void)
  810. {
  811. kfree(chips);
  812. }
  813. static inline void unregister_all_notifiers(void)
  814. {
  815. opal_message_notifier_unregister(OPAL_MSG_OCC,
  816. &powernv_cpufreq_opal_nb);
  817. unregister_reboot_notifier(&powernv_cpufreq_reboot_nb);
  818. }
  819. static int __init powernv_cpufreq_init(void)
  820. {
  821. int rc = 0;
  822. /* Don't probe on pseries (guest) platforms */
  823. if (!firmware_has_feature(FW_FEATURE_OPAL))
  824. return -ENODEV;
  825. /* Discover pstates from device tree and init */
  826. rc = init_powernv_pstates();
  827. if (rc)
  828. goto out;
  829. /* Populate chip info */
  830. rc = init_chip_info();
  831. if (rc)
  832. goto out;
  833. register_reboot_notifier(&powernv_cpufreq_reboot_nb);
  834. opal_message_notifier_register(OPAL_MSG_OCC, &powernv_cpufreq_opal_nb);
  835. rc = cpufreq_register_driver(&powernv_cpufreq_driver);
  836. if (!rc)
  837. return 0;
  838. pr_info("Failed to register the cpufreq driver (%d)\n", rc);
  839. unregister_all_notifiers();
  840. clean_chip_info();
  841. out:
  842. pr_info("Platform driver disabled. System does not support PState control\n");
  843. return rc;
  844. }
  845. module_init(powernv_cpufreq_init);
  846. static void __exit powernv_cpufreq_exit(void)
  847. {
  848. cpufreq_unregister_driver(&powernv_cpufreq_driver);
  849. unregister_all_notifiers();
  850. clean_chip_info();
  851. }
  852. module_exit(powernv_cpufreq_exit);
  853. MODULE_LICENSE("GPL");
  854. MODULE_AUTHOR("Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>");