mmcc-msm8974.c 61 KB

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  1. /*
  2. * Copyright (c) 2013, The Linux Foundation. All rights reserved.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/bitops.h>
  15. #include <linux/err.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/clk-provider.h>
  21. #include <linux/regmap.h>
  22. #include <linux/reset-controller.h>
  23. #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
  24. #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
  25. #include "common.h"
  26. #include "clk-regmap.h"
  27. #include "clk-pll.h"
  28. #include "clk-rcg.h"
  29. #include "clk-branch.h"
  30. #include "reset.h"
  31. #include "gdsc.h"
  32. enum {
  33. P_XO,
  34. P_MMPLL0,
  35. P_EDPLINK,
  36. P_MMPLL1,
  37. P_HDMIPLL,
  38. P_GPLL0,
  39. P_EDPVCO,
  40. P_GPLL1,
  41. P_DSI0PLL,
  42. P_DSI0PLL_BYTE,
  43. P_MMPLL2,
  44. P_MMPLL3,
  45. P_DSI1PLL,
  46. P_DSI1PLL_BYTE,
  47. };
  48. static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
  49. { P_XO, 0 },
  50. { P_MMPLL0, 1 },
  51. { P_MMPLL1, 2 },
  52. { P_GPLL0, 5 }
  53. };
  54. static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
  55. "xo",
  56. "mmpll0_vote",
  57. "mmpll1_vote",
  58. "mmss_gpll0_vote",
  59. };
  60. static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
  61. { P_XO, 0 },
  62. { P_MMPLL0, 1 },
  63. { P_HDMIPLL, 4 },
  64. { P_GPLL0, 5 },
  65. { P_DSI0PLL, 2 },
  66. { P_DSI1PLL, 3 }
  67. };
  68. static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
  69. "xo",
  70. "mmpll0_vote",
  71. "hdmipll",
  72. "mmss_gpll0_vote",
  73. "dsi0pll",
  74. "dsi1pll",
  75. };
  76. static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
  77. { P_XO, 0 },
  78. { P_MMPLL0, 1 },
  79. { P_MMPLL1, 2 },
  80. { P_GPLL0, 5 },
  81. { P_MMPLL2, 3 }
  82. };
  83. static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
  84. "xo",
  85. "mmpll0_vote",
  86. "mmpll1_vote",
  87. "mmss_gpll0_vote",
  88. "mmpll2",
  89. };
  90. static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
  91. { P_XO, 0 },
  92. { P_MMPLL0, 1 },
  93. { P_MMPLL1, 2 },
  94. { P_GPLL0, 5 },
  95. { P_MMPLL3, 3 }
  96. };
  97. static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
  98. "xo",
  99. "mmpll0_vote",
  100. "mmpll1_vote",
  101. "mmss_gpll0_vote",
  102. "mmpll3",
  103. };
  104. static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
  105. { P_XO, 0 },
  106. { P_MMPLL0, 1 },
  107. { P_MMPLL1, 2 },
  108. { P_GPLL0, 5 },
  109. { P_GPLL1, 4 }
  110. };
  111. static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
  112. "xo",
  113. "mmpll0_vote",
  114. "mmpll1_vote",
  115. "mmss_gpll0_vote",
  116. "gpll1_vote",
  117. };
  118. static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
  119. { P_XO, 0 },
  120. { P_EDPLINK, 4 },
  121. { P_HDMIPLL, 3 },
  122. { P_EDPVCO, 5 },
  123. { P_DSI0PLL, 1 },
  124. { P_DSI1PLL, 2 }
  125. };
  126. static const char * const mmcc_xo_dsi_hdmi_edp[] = {
  127. "xo",
  128. "edp_link_clk",
  129. "hdmipll",
  130. "edp_vco_div",
  131. "dsi0pll",
  132. "dsi1pll",
  133. };
  134. static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
  135. { P_XO, 0 },
  136. { P_EDPLINK, 4 },
  137. { P_HDMIPLL, 3 },
  138. { P_GPLL0, 5 },
  139. { P_DSI0PLL, 1 },
  140. { P_DSI1PLL, 2 }
  141. };
  142. static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
  143. "xo",
  144. "edp_link_clk",
  145. "hdmipll",
  146. "gpll0_vote",
  147. "dsi0pll",
  148. "dsi1pll",
  149. };
  150. static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
  151. { P_XO, 0 },
  152. { P_EDPLINK, 4 },
  153. { P_HDMIPLL, 3 },
  154. { P_GPLL0, 5 },
  155. { P_DSI0PLL_BYTE, 1 },
  156. { P_DSI1PLL_BYTE, 2 }
  157. };
  158. static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
  159. "xo",
  160. "edp_link_clk",
  161. "hdmipll",
  162. "gpll0_vote",
  163. "dsi0pllbyte",
  164. "dsi1pllbyte",
  165. };
  166. #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  167. static struct clk_pll mmpll0 = {
  168. .l_reg = 0x0004,
  169. .m_reg = 0x0008,
  170. .n_reg = 0x000c,
  171. .config_reg = 0x0014,
  172. .mode_reg = 0x0000,
  173. .status_reg = 0x001c,
  174. .status_bit = 17,
  175. .clkr.hw.init = &(struct clk_init_data){
  176. .name = "mmpll0",
  177. .parent_names = (const char *[]){ "xo" },
  178. .num_parents = 1,
  179. .ops = &clk_pll_ops,
  180. },
  181. };
  182. static struct clk_regmap mmpll0_vote = {
  183. .enable_reg = 0x0100,
  184. .enable_mask = BIT(0),
  185. .hw.init = &(struct clk_init_data){
  186. .name = "mmpll0_vote",
  187. .parent_names = (const char *[]){ "mmpll0" },
  188. .num_parents = 1,
  189. .ops = &clk_pll_vote_ops,
  190. },
  191. };
  192. static struct clk_pll mmpll1 = {
  193. .l_reg = 0x0044,
  194. .m_reg = 0x0048,
  195. .n_reg = 0x004c,
  196. .config_reg = 0x0050,
  197. .mode_reg = 0x0040,
  198. .status_reg = 0x005c,
  199. .status_bit = 17,
  200. .clkr.hw.init = &(struct clk_init_data){
  201. .name = "mmpll1",
  202. .parent_names = (const char *[]){ "xo" },
  203. .num_parents = 1,
  204. .ops = &clk_pll_ops,
  205. },
  206. };
  207. static struct clk_regmap mmpll1_vote = {
  208. .enable_reg = 0x0100,
  209. .enable_mask = BIT(1),
  210. .hw.init = &(struct clk_init_data){
  211. .name = "mmpll1_vote",
  212. .parent_names = (const char *[]){ "mmpll1" },
  213. .num_parents = 1,
  214. .ops = &clk_pll_vote_ops,
  215. },
  216. };
  217. static struct clk_pll mmpll2 = {
  218. .l_reg = 0x4104,
  219. .m_reg = 0x4108,
  220. .n_reg = 0x410c,
  221. .config_reg = 0x4110,
  222. .mode_reg = 0x4100,
  223. .status_reg = 0x411c,
  224. .clkr.hw.init = &(struct clk_init_data){
  225. .name = "mmpll2",
  226. .parent_names = (const char *[]){ "xo" },
  227. .num_parents = 1,
  228. .ops = &clk_pll_ops,
  229. },
  230. };
  231. static struct clk_pll mmpll3 = {
  232. .l_reg = 0x0084,
  233. .m_reg = 0x0088,
  234. .n_reg = 0x008c,
  235. .config_reg = 0x0090,
  236. .mode_reg = 0x0080,
  237. .status_reg = 0x009c,
  238. .status_bit = 17,
  239. .clkr.hw.init = &(struct clk_init_data){
  240. .name = "mmpll3",
  241. .parent_names = (const char *[]){ "xo" },
  242. .num_parents = 1,
  243. .ops = &clk_pll_ops,
  244. },
  245. };
  246. static struct clk_rcg2 mmss_ahb_clk_src = {
  247. .cmd_rcgr = 0x5000,
  248. .hid_width = 5,
  249. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  250. .clkr.hw.init = &(struct clk_init_data){
  251. .name = "mmss_ahb_clk_src",
  252. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  253. .num_parents = 4,
  254. .ops = &clk_rcg2_ops,
  255. },
  256. };
  257. static struct freq_tbl ftbl_mmss_axi_clk[] = {
  258. F( 19200000, P_XO, 1, 0, 0),
  259. F( 37500000, P_GPLL0, 16, 0, 0),
  260. F( 50000000, P_GPLL0, 12, 0, 0),
  261. F( 75000000, P_GPLL0, 8, 0, 0),
  262. F(100000000, P_GPLL0, 6, 0, 0),
  263. F(150000000, P_GPLL0, 4, 0, 0),
  264. F(291750000, P_MMPLL1, 4, 0, 0),
  265. F(400000000, P_MMPLL0, 2, 0, 0),
  266. F(466800000, P_MMPLL1, 2.5, 0, 0),
  267. };
  268. static struct clk_rcg2 mmss_axi_clk_src = {
  269. .cmd_rcgr = 0x5040,
  270. .hid_width = 5,
  271. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  272. .freq_tbl = ftbl_mmss_axi_clk,
  273. .clkr.hw.init = &(struct clk_init_data){
  274. .name = "mmss_axi_clk_src",
  275. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  276. .num_parents = 4,
  277. .ops = &clk_rcg2_ops,
  278. },
  279. };
  280. static struct freq_tbl ftbl_ocmemnoc_clk[] = {
  281. F( 19200000, P_XO, 1, 0, 0),
  282. F( 37500000, P_GPLL0, 16, 0, 0),
  283. F( 50000000, P_GPLL0, 12, 0, 0),
  284. F( 75000000, P_GPLL0, 8, 0, 0),
  285. F(100000000, P_GPLL0, 6, 0, 0),
  286. F(150000000, P_GPLL0, 4, 0, 0),
  287. F(291750000, P_MMPLL1, 4, 0, 0),
  288. F(400000000, P_MMPLL0, 2, 0, 0),
  289. };
  290. static struct clk_rcg2 ocmemnoc_clk_src = {
  291. .cmd_rcgr = 0x5090,
  292. .hid_width = 5,
  293. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  294. .freq_tbl = ftbl_ocmemnoc_clk,
  295. .clkr.hw.init = &(struct clk_init_data){
  296. .name = "ocmemnoc_clk_src",
  297. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  298. .num_parents = 4,
  299. .ops = &clk_rcg2_ops,
  300. },
  301. };
  302. static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
  303. F(100000000, P_GPLL0, 6, 0, 0),
  304. F(200000000, P_MMPLL0, 4, 0, 0),
  305. { }
  306. };
  307. static struct clk_rcg2 csi0_clk_src = {
  308. .cmd_rcgr = 0x3090,
  309. .hid_width = 5,
  310. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  311. .freq_tbl = ftbl_camss_csi0_3_clk,
  312. .clkr.hw.init = &(struct clk_init_data){
  313. .name = "csi0_clk_src",
  314. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  315. .num_parents = 4,
  316. .ops = &clk_rcg2_ops,
  317. },
  318. };
  319. static struct clk_rcg2 csi1_clk_src = {
  320. .cmd_rcgr = 0x3100,
  321. .hid_width = 5,
  322. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  323. .freq_tbl = ftbl_camss_csi0_3_clk,
  324. .clkr.hw.init = &(struct clk_init_data){
  325. .name = "csi1_clk_src",
  326. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  327. .num_parents = 4,
  328. .ops = &clk_rcg2_ops,
  329. },
  330. };
  331. static struct clk_rcg2 csi2_clk_src = {
  332. .cmd_rcgr = 0x3160,
  333. .hid_width = 5,
  334. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  335. .freq_tbl = ftbl_camss_csi0_3_clk,
  336. .clkr.hw.init = &(struct clk_init_data){
  337. .name = "csi2_clk_src",
  338. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  339. .num_parents = 4,
  340. .ops = &clk_rcg2_ops,
  341. },
  342. };
  343. static struct clk_rcg2 csi3_clk_src = {
  344. .cmd_rcgr = 0x31c0,
  345. .hid_width = 5,
  346. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  347. .freq_tbl = ftbl_camss_csi0_3_clk,
  348. .clkr.hw.init = &(struct clk_init_data){
  349. .name = "csi3_clk_src",
  350. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  351. .num_parents = 4,
  352. .ops = &clk_rcg2_ops,
  353. },
  354. };
  355. static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
  356. F(37500000, P_GPLL0, 16, 0, 0),
  357. F(50000000, P_GPLL0, 12, 0, 0),
  358. F(60000000, P_GPLL0, 10, 0, 0),
  359. F(80000000, P_GPLL0, 7.5, 0, 0),
  360. F(100000000, P_GPLL0, 6, 0, 0),
  361. F(109090000, P_GPLL0, 5.5, 0, 0),
  362. F(133330000, P_GPLL0, 4.5, 0, 0),
  363. F(200000000, P_GPLL0, 3, 0, 0),
  364. F(228570000, P_MMPLL0, 3.5, 0, 0),
  365. F(266670000, P_MMPLL0, 3, 0, 0),
  366. F(320000000, P_MMPLL0, 2.5, 0, 0),
  367. F(400000000, P_MMPLL0, 2, 0, 0),
  368. F(465000000, P_MMPLL3, 2, 0, 0),
  369. { }
  370. };
  371. static struct clk_rcg2 vfe0_clk_src = {
  372. .cmd_rcgr = 0x3600,
  373. .hid_width = 5,
  374. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  375. .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
  376. .clkr.hw.init = &(struct clk_init_data){
  377. .name = "vfe0_clk_src",
  378. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  379. .num_parents = 4,
  380. .ops = &clk_rcg2_ops,
  381. },
  382. };
  383. static struct clk_rcg2 vfe1_clk_src = {
  384. .cmd_rcgr = 0x3620,
  385. .hid_width = 5,
  386. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  387. .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
  388. .clkr.hw.init = &(struct clk_init_data){
  389. .name = "vfe1_clk_src",
  390. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  391. .num_parents = 4,
  392. .ops = &clk_rcg2_ops,
  393. },
  394. };
  395. static struct freq_tbl ftbl_mdss_mdp_clk[] = {
  396. F(37500000, P_GPLL0, 16, 0, 0),
  397. F(60000000, P_GPLL0, 10, 0, 0),
  398. F(75000000, P_GPLL0, 8, 0, 0),
  399. F(85710000, P_GPLL0, 7, 0, 0),
  400. F(100000000, P_GPLL0, 6, 0, 0),
  401. F(133330000, P_MMPLL0, 6, 0, 0),
  402. F(160000000, P_MMPLL0, 5, 0, 0),
  403. F(200000000, P_MMPLL0, 4, 0, 0),
  404. F(228570000, P_MMPLL0, 3.5, 0, 0),
  405. F(240000000, P_GPLL0, 2.5, 0, 0),
  406. F(266670000, P_MMPLL0, 3, 0, 0),
  407. F(320000000, P_MMPLL0, 2.5, 0, 0),
  408. { }
  409. };
  410. static struct clk_rcg2 mdp_clk_src = {
  411. .cmd_rcgr = 0x2040,
  412. .hid_width = 5,
  413. .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
  414. .freq_tbl = ftbl_mdss_mdp_clk,
  415. .clkr.hw.init = &(struct clk_init_data){
  416. .name = "mdp_clk_src",
  417. .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
  418. .num_parents = 6,
  419. .ops = &clk_rcg2_ops,
  420. },
  421. };
  422. static struct clk_rcg2 gfx3d_clk_src = {
  423. .cmd_rcgr = 0x4000,
  424. .hid_width = 5,
  425. .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
  426. .clkr.hw.init = &(struct clk_init_data){
  427. .name = "gfx3d_clk_src",
  428. .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
  429. .num_parents = 5,
  430. .ops = &clk_rcg2_ops,
  431. },
  432. };
  433. static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
  434. F(75000000, P_GPLL0, 8, 0, 0),
  435. F(133330000, P_GPLL0, 4.5, 0, 0),
  436. F(200000000, P_GPLL0, 3, 0, 0),
  437. F(228570000, P_MMPLL0, 3.5, 0, 0),
  438. F(266670000, P_MMPLL0, 3, 0, 0),
  439. F(320000000, P_MMPLL0, 2.5, 0, 0),
  440. { }
  441. };
  442. static struct clk_rcg2 jpeg0_clk_src = {
  443. .cmd_rcgr = 0x3500,
  444. .hid_width = 5,
  445. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  446. .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
  447. .clkr.hw.init = &(struct clk_init_data){
  448. .name = "jpeg0_clk_src",
  449. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  450. .num_parents = 4,
  451. .ops = &clk_rcg2_ops,
  452. },
  453. };
  454. static struct clk_rcg2 jpeg1_clk_src = {
  455. .cmd_rcgr = 0x3520,
  456. .hid_width = 5,
  457. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  458. .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
  459. .clkr.hw.init = &(struct clk_init_data){
  460. .name = "jpeg1_clk_src",
  461. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  462. .num_parents = 4,
  463. .ops = &clk_rcg2_ops,
  464. },
  465. };
  466. static struct clk_rcg2 jpeg2_clk_src = {
  467. .cmd_rcgr = 0x3540,
  468. .hid_width = 5,
  469. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  470. .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
  471. .clkr.hw.init = &(struct clk_init_data){
  472. .name = "jpeg2_clk_src",
  473. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  474. .num_parents = 4,
  475. .ops = &clk_rcg2_ops,
  476. },
  477. };
  478. static struct clk_rcg2 pclk0_clk_src = {
  479. .cmd_rcgr = 0x2000,
  480. .mnd_width = 8,
  481. .hid_width = 5,
  482. .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
  483. .clkr.hw.init = &(struct clk_init_data){
  484. .name = "pclk0_clk_src",
  485. .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
  486. .num_parents = 6,
  487. .ops = &clk_pixel_ops,
  488. .flags = CLK_SET_RATE_PARENT,
  489. },
  490. };
  491. static struct clk_rcg2 pclk1_clk_src = {
  492. .cmd_rcgr = 0x2020,
  493. .mnd_width = 8,
  494. .hid_width = 5,
  495. .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
  496. .clkr.hw.init = &(struct clk_init_data){
  497. .name = "pclk1_clk_src",
  498. .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
  499. .num_parents = 6,
  500. .ops = &clk_pixel_ops,
  501. .flags = CLK_SET_RATE_PARENT,
  502. },
  503. };
  504. static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
  505. F(50000000, P_GPLL0, 12, 0, 0),
  506. F(100000000, P_GPLL0, 6, 0, 0),
  507. F(133330000, P_MMPLL0, 6, 0, 0),
  508. F(200000000, P_MMPLL0, 4, 0, 0),
  509. F(266670000, P_MMPLL0, 3, 0, 0),
  510. F(465000000, P_MMPLL3, 2, 0, 0),
  511. { }
  512. };
  513. static struct clk_rcg2 vcodec0_clk_src = {
  514. .cmd_rcgr = 0x1000,
  515. .mnd_width = 8,
  516. .hid_width = 5,
  517. .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
  518. .freq_tbl = ftbl_venus0_vcodec0_clk,
  519. .clkr.hw.init = &(struct clk_init_data){
  520. .name = "vcodec0_clk_src",
  521. .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
  522. .num_parents = 5,
  523. .ops = &clk_rcg2_ops,
  524. },
  525. };
  526. static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
  527. F(19200000, P_XO, 1, 0, 0),
  528. { }
  529. };
  530. static struct clk_rcg2 cci_clk_src = {
  531. .cmd_rcgr = 0x3300,
  532. .hid_width = 5,
  533. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  534. .freq_tbl = ftbl_camss_cci_cci_clk,
  535. .clkr.hw.init = &(struct clk_init_data){
  536. .name = "cci_clk_src",
  537. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  538. .num_parents = 4,
  539. .ops = &clk_rcg2_ops,
  540. },
  541. };
  542. static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
  543. F(10000, P_XO, 16, 1, 120),
  544. F(24000, P_XO, 16, 1, 50),
  545. F(6000000, P_GPLL0, 10, 1, 10),
  546. F(12000000, P_GPLL0, 10, 1, 5),
  547. F(13000000, P_GPLL0, 4, 13, 150),
  548. F(24000000, P_GPLL0, 5, 1, 5),
  549. { }
  550. };
  551. static struct clk_rcg2 camss_gp0_clk_src = {
  552. .cmd_rcgr = 0x3420,
  553. .mnd_width = 8,
  554. .hid_width = 5,
  555. .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
  556. .freq_tbl = ftbl_camss_gp0_1_clk,
  557. .clkr.hw.init = &(struct clk_init_data){
  558. .name = "camss_gp0_clk_src",
  559. .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
  560. .num_parents = 5,
  561. .ops = &clk_rcg2_ops,
  562. },
  563. };
  564. static struct clk_rcg2 camss_gp1_clk_src = {
  565. .cmd_rcgr = 0x3450,
  566. .mnd_width = 8,
  567. .hid_width = 5,
  568. .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
  569. .freq_tbl = ftbl_camss_gp0_1_clk,
  570. .clkr.hw.init = &(struct clk_init_data){
  571. .name = "camss_gp1_clk_src",
  572. .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
  573. .num_parents = 5,
  574. .ops = &clk_rcg2_ops,
  575. },
  576. };
  577. static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
  578. F(4800000, P_XO, 4, 0, 0),
  579. F(6000000, P_GPLL0, 10, 1, 10),
  580. F(8000000, P_GPLL0, 15, 1, 5),
  581. F(9600000, P_XO, 2, 0, 0),
  582. F(16000000, P_GPLL0, 12.5, 1, 3),
  583. F(19200000, P_XO, 1, 0, 0),
  584. F(24000000, P_GPLL0, 5, 1, 5),
  585. F(32000000, P_MMPLL0, 5, 1, 5),
  586. F(48000000, P_GPLL0, 12.5, 0, 0),
  587. F(64000000, P_MMPLL0, 12.5, 0, 0),
  588. F(66670000, P_GPLL0, 9, 0, 0),
  589. { }
  590. };
  591. static struct clk_rcg2 mclk0_clk_src = {
  592. .cmd_rcgr = 0x3360,
  593. .hid_width = 5,
  594. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  595. .freq_tbl = ftbl_camss_mclk0_3_clk,
  596. .clkr.hw.init = &(struct clk_init_data){
  597. .name = "mclk0_clk_src",
  598. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  599. .num_parents = 4,
  600. .ops = &clk_rcg2_ops,
  601. },
  602. };
  603. static struct clk_rcg2 mclk1_clk_src = {
  604. .cmd_rcgr = 0x3390,
  605. .hid_width = 5,
  606. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  607. .freq_tbl = ftbl_camss_mclk0_3_clk,
  608. .clkr.hw.init = &(struct clk_init_data){
  609. .name = "mclk1_clk_src",
  610. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  611. .num_parents = 4,
  612. .ops = &clk_rcg2_ops,
  613. },
  614. };
  615. static struct clk_rcg2 mclk2_clk_src = {
  616. .cmd_rcgr = 0x33c0,
  617. .hid_width = 5,
  618. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  619. .freq_tbl = ftbl_camss_mclk0_3_clk,
  620. .clkr.hw.init = &(struct clk_init_data){
  621. .name = "mclk2_clk_src",
  622. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  623. .num_parents = 4,
  624. .ops = &clk_rcg2_ops,
  625. },
  626. };
  627. static struct clk_rcg2 mclk3_clk_src = {
  628. .cmd_rcgr = 0x33f0,
  629. .hid_width = 5,
  630. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  631. .freq_tbl = ftbl_camss_mclk0_3_clk,
  632. .clkr.hw.init = &(struct clk_init_data){
  633. .name = "mclk3_clk_src",
  634. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  635. .num_parents = 4,
  636. .ops = &clk_rcg2_ops,
  637. },
  638. };
  639. static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
  640. F(100000000, P_GPLL0, 6, 0, 0),
  641. F(200000000, P_MMPLL0, 4, 0, 0),
  642. { }
  643. };
  644. static struct clk_rcg2 csi0phytimer_clk_src = {
  645. .cmd_rcgr = 0x3000,
  646. .hid_width = 5,
  647. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  648. .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
  649. .clkr.hw.init = &(struct clk_init_data){
  650. .name = "csi0phytimer_clk_src",
  651. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  652. .num_parents = 4,
  653. .ops = &clk_rcg2_ops,
  654. },
  655. };
  656. static struct clk_rcg2 csi1phytimer_clk_src = {
  657. .cmd_rcgr = 0x3030,
  658. .hid_width = 5,
  659. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  660. .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
  661. .clkr.hw.init = &(struct clk_init_data){
  662. .name = "csi1phytimer_clk_src",
  663. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  664. .num_parents = 4,
  665. .ops = &clk_rcg2_ops,
  666. },
  667. };
  668. static struct clk_rcg2 csi2phytimer_clk_src = {
  669. .cmd_rcgr = 0x3060,
  670. .hid_width = 5,
  671. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  672. .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
  673. .clkr.hw.init = &(struct clk_init_data){
  674. .name = "csi2phytimer_clk_src",
  675. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  676. .num_parents = 4,
  677. .ops = &clk_rcg2_ops,
  678. },
  679. };
  680. static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
  681. F(133330000, P_GPLL0, 4.5, 0, 0),
  682. F(266670000, P_MMPLL0, 3, 0, 0),
  683. F(320000000, P_MMPLL0, 2.5, 0, 0),
  684. F(400000000, P_MMPLL0, 2, 0, 0),
  685. F(465000000, P_MMPLL3, 2, 0, 0),
  686. { }
  687. };
  688. static struct clk_rcg2 cpp_clk_src = {
  689. .cmd_rcgr = 0x3640,
  690. .hid_width = 5,
  691. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  692. .freq_tbl = ftbl_camss_vfe_cpp_clk,
  693. .clkr.hw.init = &(struct clk_init_data){
  694. .name = "cpp_clk_src",
  695. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  696. .num_parents = 4,
  697. .ops = &clk_rcg2_ops,
  698. },
  699. };
  700. static struct freq_tbl byte_freq_tbl[] = {
  701. { .src = P_DSI0PLL_BYTE },
  702. { }
  703. };
  704. static struct clk_rcg2 byte0_clk_src = {
  705. .cmd_rcgr = 0x2120,
  706. .hid_width = 5,
  707. .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
  708. .freq_tbl = byte_freq_tbl,
  709. .clkr.hw.init = &(struct clk_init_data){
  710. .name = "byte0_clk_src",
  711. .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
  712. .num_parents = 6,
  713. .ops = &clk_byte2_ops,
  714. .flags = CLK_SET_RATE_PARENT,
  715. },
  716. };
  717. static struct clk_rcg2 byte1_clk_src = {
  718. .cmd_rcgr = 0x2140,
  719. .hid_width = 5,
  720. .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
  721. .freq_tbl = byte_freq_tbl,
  722. .clkr.hw.init = &(struct clk_init_data){
  723. .name = "byte1_clk_src",
  724. .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
  725. .num_parents = 6,
  726. .ops = &clk_byte2_ops,
  727. .flags = CLK_SET_RATE_PARENT,
  728. },
  729. };
  730. static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
  731. F(19200000, P_XO, 1, 0, 0),
  732. { }
  733. };
  734. static struct clk_rcg2 edpaux_clk_src = {
  735. .cmd_rcgr = 0x20e0,
  736. .hid_width = 5,
  737. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  738. .freq_tbl = ftbl_mdss_edpaux_clk,
  739. .clkr.hw.init = &(struct clk_init_data){
  740. .name = "edpaux_clk_src",
  741. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  742. .num_parents = 4,
  743. .ops = &clk_rcg2_ops,
  744. },
  745. };
  746. static struct freq_tbl ftbl_mdss_edplink_clk[] = {
  747. F(135000000, P_EDPLINK, 2, 0, 0),
  748. F(270000000, P_EDPLINK, 11, 0, 0),
  749. { }
  750. };
  751. static struct clk_rcg2 edplink_clk_src = {
  752. .cmd_rcgr = 0x20c0,
  753. .hid_width = 5,
  754. .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
  755. .freq_tbl = ftbl_mdss_edplink_clk,
  756. .clkr.hw.init = &(struct clk_init_data){
  757. .name = "edplink_clk_src",
  758. .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
  759. .num_parents = 6,
  760. .ops = &clk_rcg2_ops,
  761. .flags = CLK_SET_RATE_PARENT,
  762. },
  763. };
  764. static struct freq_tbl edp_pixel_freq_tbl[] = {
  765. { .src = P_EDPVCO },
  766. { }
  767. };
  768. static struct clk_rcg2 edppixel_clk_src = {
  769. .cmd_rcgr = 0x20a0,
  770. .mnd_width = 8,
  771. .hid_width = 5,
  772. .parent_map = mmcc_xo_dsi_hdmi_edp_map,
  773. .freq_tbl = edp_pixel_freq_tbl,
  774. .clkr.hw.init = &(struct clk_init_data){
  775. .name = "edppixel_clk_src",
  776. .parent_names = mmcc_xo_dsi_hdmi_edp,
  777. .num_parents = 6,
  778. .ops = &clk_edp_pixel_ops,
  779. },
  780. };
  781. static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
  782. F(19200000, P_XO, 1, 0, 0),
  783. { }
  784. };
  785. static struct clk_rcg2 esc0_clk_src = {
  786. .cmd_rcgr = 0x2160,
  787. .hid_width = 5,
  788. .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
  789. .freq_tbl = ftbl_mdss_esc0_1_clk,
  790. .clkr.hw.init = &(struct clk_init_data){
  791. .name = "esc0_clk_src",
  792. .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
  793. .num_parents = 6,
  794. .ops = &clk_rcg2_ops,
  795. },
  796. };
  797. static struct clk_rcg2 esc1_clk_src = {
  798. .cmd_rcgr = 0x2180,
  799. .hid_width = 5,
  800. .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
  801. .freq_tbl = ftbl_mdss_esc0_1_clk,
  802. .clkr.hw.init = &(struct clk_init_data){
  803. .name = "esc1_clk_src",
  804. .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
  805. .num_parents = 6,
  806. .ops = &clk_rcg2_ops,
  807. },
  808. };
  809. static struct freq_tbl extpclk_freq_tbl[] = {
  810. { .src = P_HDMIPLL },
  811. { }
  812. };
  813. static struct clk_rcg2 extpclk_clk_src = {
  814. .cmd_rcgr = 0x2060,
  815. .hid_width = 5,
  816. .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
  817. .freq_tbl = extpclk_freq_tbl,
  818. .clkr.hw.init = &(struct clk_init_data){
  819. .name = "extpclk_clk_src",
  820. .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
  821. .num_parents = 6,
  822. .ops = &clk_byte_ops,
  823. .flags = CLK_SET_RATE_PARENT,
  824. },
  825. };
  826. static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
  827. F(19200000, P_XO, 1, 0, 0),
  828. { }
  829. };
  830. static struct clk_rcg2 hdmi_clk_src = {
  831. .cmd_rcgr = 0x2100,
  832. .hid_width = 5,
  833. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  834. .freq_tbl = ftbl_mdss_hdmi_clk,
  835. .clkr.hw.init = &(struct clk_init_data){
  836. .name = "hdmi_clk_src",
  837. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  838. .num_parents = 4,
  839. .ops = &clk_rcg2_ops,
  840. },
  841. };
  842. static struct freq_tbl ftbl_mdss_vsync_clk[] = {
  843. F(19200000, P_XO, 1, 0, 0),
  844. { }
  845. };
  846. static struct clk_rcg2 vsync_clk_src = {
  847. .cmd_rcgr = 0x2080,
  848. .hid_width = 5,
  849. .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
  850. .freq_tbl = ftbl_mdss_vsync_clk,
  851. .clkr.hw.init = &(struct clk_init_data){
  852. .name = "vsync_clk_src",
  853. .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
  854. .num_parents = 4,
  855. .ops = &clk_rcg2_ops,
  856. },
  857. };
  858. static struct clk_branch camss_cci_cci_ahb_clk = {
  859. .halt_reg = 0x3348,
  860. .clkr = {
  861. .enable_reg = 0x3348,
  862. .enable_mask = BIT(0),
  863. .hw.init = &(struct clk_init_data){
  864. .name = "camss_cci_cci_ahb_clk",
  865. .parent_names = (const char *[]){
  866. "mmss_ahb_clk_src",
  867. },
  868. .num_parents = 1,
  869. .ops = &clk_branch2_ops,
  870. },
  871. },
  872. };
  873. static struct clk_branch camss_cci_cci_clk = {
  874. .halt_reg = 0x3344,
  875. .clkr = {
  876. .enable_reg = 0x3344,
  877. .enable_mask = BIT(0),
  878. .hw.init = &(struct clk_init_data){
  879. .name = "camss_cci_cci_clk",
  880. .parent_names = (const char *[]){
  881. "cci_clk_src",
  882. },
  883. .num_parents = 1,
  884. .flags = CLK_SET_RATE_PARENT,
  885. .ops = &clk_branch2_ops,
  886. },
  887. },
  888. };
  889. static struct clk_branch camss_csi0_ahb_clk = {
  890. .halt_reg = 0x30bc,
  891. .clkr = {
  892. .enable_reg = 0x30bc,
  893. .enable_mask = BIT(0),
  894. .hw.init = &(struct clk_init_data){
  895. .name = "camss_csi0_ahb_clk",
  896. .parent_names = (const char *[]){
  897. "mmss_ahb_clk_src",
  898. },
  899. .num_parents = 1,
  900. .ops = &clk_branch2_ops,
  901. },
  902. },
  903. };
  904. static struct clk_branch camss_csi0_clk = {
  905. .halt_reg = 0x30b4,
  906. .clkr = {
  907. .enable_reg = 0x30b4,
  908. .enable_mask = BIT(0),
  909. .hw.init = &(struct clk_init_data){
  910. .name = "camss_csi0_clk",
  911. .parent_names = (const char *[]){
  912. "csi0_clk_src",
  913. },
  914. .num_parents = 1,
  915. .flags = CLK_SET_RATE_PARENT,
  916. .ops = &clk_branch2_ops,
  917. },
  918. },
  919. };
  920. static struct clk_branch camss_csi0phy_clk = {
  921. .halt_reg = 0x30c4,
  922. .clkr = {
  923. .enable_reg = 0x30c4,
  924. .enable_mask = BIT(0),
  925. .hw.init = &(struct clk_init_data){
  926. .name = "camss_csi0phy_clk",
  927. .parent_names = (const char *[]){
  928. "csi0_clk_src",
  929. },
  930. .num_parents = 1,
  931. .flags = CLK_SET_RATE_PARENT,
  932. .ops = &clk_branch2_ops,
  933. },
  934. },
  935. };
  936. static struct clk_branch camss_csi0pix_clk = {
  937. .halt_reg = 0x30e4,
  938. .clkr = {
  939. .enable_reg = 0x30e4,
  940. .enable_mask = BIT(0),
  941. .hw.init = &(struct clk_init_data){
  942. .name = "camss_csi0pix_clk",
  943. .parent_names = (const char *[]){
  944. "csi0_clk_src",
  945. },
  946. .num_parents = 1,
  947. .flags = CLK_SET_RATE_PARENT,
  948. .ops = &clk_branch2_ops,
  949. },
  950. },
  951. };
  952. static struct clk_branch camss_csi0rdi_clk = {
  953. .halt_reg = 0x30d4,
  954. .clkr = {
  955. .enable_reg = 0x30d4,
  956. .enable_mask = BIT(0),
  957. .hw.init = &(struct clk_init_data){
  958. .name = "camss_csi0rdi_clk",
  959. .parent_names = (const char *[]){
  960. "csi0_clk_src",
  961. },
  962. .num_parents = 1,
  963. .flags = CLK_SET_RATE_PARENT,
  964. .ops = &clk_branch2_ops,
  965. },
  966. },
  967. };
  968. static struct clk_branch camss_csi1_ahb_clk = {
  969. .halt_reg = 0x3128,
  970. .clkr = {
  971. .enable_reg = 0x3128,
  972. .enable_mask = BIT(0),
  973. .hw.init = &(struct clk_init_data){
  974. .name = "camss_csi1_ahb_clk",
  975. .parent_names = (const char *[]){
  976. "mmss_ahb_clk_src",
  977. },
  978. .num_parents = 1,
  979. .ops = &clk_branch2_ops,
  980. },
  981. },
  982. };
  983. static struct clk_branch camss_csi1_clk = {
  984. .halt_reg = 0x3124,
  985. .clkr = {
  986. .enable_reg = 0x3124,
  987. .enable_mask = BIT(0),
  988. .hw.init = &(struct clk_init_data){
  989. .name = "camss_csi1_clk",
  990. .parent_names = (const char *[]){
  991. "csi1_clk_src",
  992. },
  993. .num_parents = 1,
  994. .flags = CLK_SET_RATE_PARENT,
  995. .ops = &clk_branch2_ops,
  996. },
  997. },
  998. };
  999. static struct clk_branch camss_csi1phy_clk = {
  1000. .halt_reg = 0x3134,
  1001. .clkr = {
  1002. .enable_reg = 0x3134,
  1003. .enable_mask = BIT(0),
  1004. .hw.init = &(struct clk_init_data){
  1005. .name = "camss_csi1phy_clk",
  1006. .parent_names = (const char *[]){
  1007. "csi1_clk_src",
  1008. },
  1009. .num_parents = 1,
  1010. .flags = CLK_SET_RATE_PARENT,
  1011. .ops = &clk_branch2_ops,
  1012. },
  1013. },
  1014. };
  1015. static struct clk_branch camss_csi1pix_clk = {
  1016. .halt_reg = 0x3154,
  1017. .clkr = {
  1018. .enable_reg = 0x3154,
  1019. .enable_mask = BIT(0),
  1020. .hw.init = &(struct clk_init_data){
  1021. .name = "camss_csi1pix_clk",
  1022. .parent_names = (const char *[]){
  1023. "csi1_clk_src",
  1024. },
  1025. .num_parents = 1,
  1026. .flags = CLK_SET_RATE_PARENT,
  1027. .ops = &clk_branch2_ops,
  1028. },
  1029. },
  1030. };
  1031. static struct clk_branch camss_csi1rdi_clk = {
  1032. .halt_reg = 0x3144,
  1033. .clkr = {
  1034. .enable_reg = 0x3144,
  1035. .enable_mask = BIT(0),
  1036. .hw.init = &(struct clk_init_data){
  1037. .name = "camss_csi1rdi_clk",
  1038. .parent_names = (const char *[]){
  1039. "csi1_clk_src",
  1040. },
  1041. .num_parents = 1,
  1042. .flags = CLK_SET_RATE_PARENT,
  1043. .ops = &clk_branch2_ops,
  1044. },
  1045. },
  1046. };
  1047. static struct clk_branch camss_csi2_ahb_clk = {
  1048. .halt_reg = 0x3188,
  1049. .clkr = {
  1050. .enable_reg = 0x3188,
  1051. .enable_mask = BIT(0),
  1052. .hw.init = &(struct clk_init_data){
  1053. .name = "camss_csi2_ahb_clk",
  1054. .parent_names = (const char *[]){
  1055. "mmss_ahb_clk_src",
  1056. },
  1057. .num_parents = 1,
  1058. .ops = &clk_branch2_ops,
  1059. },
  1060. },
  1061. };
  1062. static struct clk_branch camss_csi2_clk = {
  1063. .halt_reg = 0x3184,
  1064. .clkr = {
  1065. .enable_reg = 0x3184,
  1066. .enable_mask = BIT(0),
  1067. .hw.init = &(struct clk_init_data){
  1068. .name = "camss_csi2_clk",
  1069. .parent_names = (const char *[]){
  1070. "csi2_clk_src",
  1071. },
  1072. .num_parents = 1,
  1073. .flags = CLK_SET_RATE_PARENT,
  1074. .ops = &clk_branch2_ops,
  1075. },
  1076. },
  1077. };
  1078. static struct clk_branch camss_csi2phy_clk = {
  1079. .halt_reg = 0x3194,
  1080. .clkr = {
  1081. .enable_reg = 0x3194,
  1082. .enable_mask = BIT(0),
  1083. .hw.init = &(struct clk_init_data){
  1084. .name = "camss_csi2phy_clk",
  1085. .parent_names = (const char *[]){
  1086. "csi2_clk_src",
  1087. },
  1088. .num_parents = 1,
  1089. .flags = CLK_SET_RATE_PARENT,
  1090. .ops = &clk_branch2_ops,
  1091. },
  1092. },
  1093. };
  1094. static struct clk_branch camss_csi2pix_clk = {
  1095. .halt_reg = 0x31b4,
  1096. .clkr = {
  1097. .enable_reg = 0x31b4,
  1098. .enable_mask = BIT(0),
  1099. .hw.init = &(struct clk_init_data){
  1100. .name = "camss_csi2pix_clk",
  1101. .parent_names = (const char *[]){
  1102. "csi2_clk_src",
  1103. },
  1104. .num_parents = 1,
  1105. .flags = CLK_SET_RATE_PARENT,
  1106. .ops = &clk_branch2_ops,
  1107. },
  1108. },
  1109. };
  1110. static struct clk_branch camss_csi2rdi_clk = {
  1111. .halt_reg = 0x31a4,
  1112. .clkr = {
  1113. .enable_reg = 0x31a4,
  1114. .enable_mask = BIT(0),
  1115. .hw.init = &(struct clk_init_data){
  1116. .name = "camss_csi2rdi_clk",
  1117. .parent_names = (const char *[]){
  1118. "csi2_clk_src",
  1119. },
  1120. .num_parents = 1,
  1121. .flags = CLK_SET_RATE_PARENT,
  1122. .ops = &clk_branch2_ops,
  1123. },
  1124. },
  1125. };
  1126. static struct clk_branch camss_csi3_ahb_clk = {
  1127. .halt_reg = 0x31e8,
  1128. .clkr = {
  1129. .enable_reg = 0x31e8,
  1130. .enable_mask = BIT(0),
  1131. .hw.init = &(struct clk_init_data){
  1132. .name = "camss_csi3_ahb_clk",
  1133. .parent_names = (const char *[]){
  1134. "mmss_ahb_clk_src",
  1135. },
  1136. .num_parents = 1,
  1137. .ops = &clk_branch2_ops,
  1138. },
  1139. },
  1140. };
  1141. static struct clk_branch camss_csi3_clk = {
  1142. .halt_reg = 0x31e4,
  1143. .clkr = {
  1144. .enable_reg = 0x31e4,
  1145. .enable_mask = BIT(0),
  1146. .hw.init = &(struct clk_init_data){
  1147. .name = "camss_csi3_clk",
  1148. .parent_names = (const char *[]){
  1149. "csi3_clk_src",
  1150. },
  1151. .num_parents = 1,
  1152. .flags = CLK_SET_RATE_PARENT,
  1153. .ops = &clk_branch2_ops,
  1154. },
  1155. },
  1156. };
  1157. static struct clk_branch camss_csi3phy_clk = {
  1158. .halt_reg = 0x31f4,
  1159. .clkr = {
  1160. .enable_reg = 0x31f4,
  1161. .enable_mask = BIT(0),
  1162. .hw.init = &(struct clk_init_data){
  1163. .name = "camss_csi3phy_clk",
  1164. .parent_names = (const char *[]){
  1165. "csi3_clk_src",
  1166. },
  1167. .num_parents = 1,
  1168. .flags = CLK_SET_RATE_PARENT,
  1169. .ops = &clk_branch2_ops,
  1170. },
  1171. },
  1172. };
  1173. static struct clk_branch camss_csi3pix_clk = {
  1174. .halt_reg = 0x3214,
  1175. .clkr = {
  1176. .enable_reg = 0x3214,
  1177. .enable_mask = BIT(0),
  1178. .hw.init = &(struct clk_init_data){
  1179. .name = "camss_csi3pix_clk",
  1180. .parent_names = (const char *[]){
  1181. "csi3_clk_src",
  1182. },
  1183. .num_parents = 1,
  1184. .flags = CLK_SET_RATE_PARENT,
  1185. .ops = &clk_branch2_ops,
  1186. },
  1187. },
  1188. };
  1189. static struct clk_branch camss_csi3rdi_clk = {
  1190. .halt_reg = 0x3204,
  1191. .clkr = {
  1192. .enable_reg = 0x3204,
  1193. .enable_mask = BIT(0),
  1194. .hw.init = &(struct clk_init_data){
  1195. .name = "camss_csi3rdi_clk",
  1196. .parent_names = (const char *[]){
  1197. "csi3_clk_src",
  1198. },
  1199. .num_parents = 1,
  1200. .flags = CLK_SET_RATE_PARENT,
  1201. .ops = &clk_branch2_ops,
  1202. },
  1203. },
  1204. };
  1205. static struct clk_branch camss_csi_vfe0_clk = {
  1206. .halt_reg = 0x3704,
  1207. .clkr = {
  1208. .enable_reg = 0x3704,
  1209. .enable_mask = BIT(0),
  1210. .hw.init = &(struct clk_init_data){
  1211. .name = "camss_csi_vfe0_clk",
  1212. .parent_names = (const char *[]){
  1213. "vfe0_clk_src",
  1214. },
  1215. .num_parents = 1,
  1216. .flags = CLK_SET_RATE_PARENT,
  1217. .ops = &clk_branch2_ops,
  1218. },
  1219. },
  1220. };
  1221. static struct clk_branch camss_csi_vfe1_clk = {
  1222. .halt_reg = 0x3714,
  1223. .clkr = {
  1224. .enable_reg = 0x3714,
  1225. .enable_mask = BIT(0),
  1226. .hw.init = &(struct clk_init_data){
  1227. .name = "camss_csi_vfe1_clk",
  1228. .parent_names = (const char *[]){
  1229. "vfe1_clk_src",
  1230. },
  1231. .num_parents = 1,
  1232. .flags = CLK_SET_RATE_PARENT,
  1233. .ops = &clk_branch2_ops,
  1234. },
  1235. },
  1236. };
  1237. static struct clk_branch camss_gp0_clk = {
  1238. .halt_reg = 0x3444,
  1239. .clkr = {
  1240. .enable_reg = 0x3444,
  1241. .enable_mask = BIT(0),
  1242. .hw.init = &(struct clk_init_data){
  1243. .name = "camss_gp0_clk",
  1244. .parent_names = (const char *[]){
  1245. "camss_gp0_clk_src",
  1246. },
  1247. .num_parents = 1,
  1248. .flags = CLK_SET_RATE_PARENT,
  1249. .ops = &clk_branch2_ops,
  1250. },
  1251. },
  1252. };
  1253. static struct clk_branch camss_gp1_clk = {
  1254. .halt_reg = 0x3474,
  1255. .clkr = {
  1256. .enable_reg = 0x3474,
  1257. .enable_mask = BIT(0),
  1258. .hw.init = &(struct clk_init_data){
  1259. .name = "camss_gp1_clk",
  1260. .parent_names = (const char *[]){
  1261. "camss_gp1_clk_src",
  1262. },
  1263. .num_parents = 1,
  1264. .flags = CLK_SET_RATE_PARENT,
  1265. .ops = &clk_branch2_ops,
  1266. },
  1267. },
  1268. };
  1269. static struct clk_branch camss_ispif_ahb_clk = {
  1270. .halt_reg = 0x3224,
  1271. .clkr = {
  1272. .enable_reg = 0x3224,
  1273. .enable_mask = BIT(0),
  1274. .hw.init = &(struct clk_init_data){
  1275. .name = "camss_ispif_ahb_clk",
  1276. .parent_names = (const char *[]){
  1277. "mmss_ahb_clk_src",
  1278. },
  1279. .num_parents = 1,
  1280. .ops = &clk_branch2_ops,
  1281. },
  1282. },
  1283. };
  1284. static struct clk_branch camss_jpeg_jpeg0_clk = {
  1285. .halt_reg = 0x35a8,
  1286. .clkr = {
  1287. .enable_reg = 0x35a8,
  1288. .enable_mask = BIT(0),
  1289. .hw.init = &(struct clk_init_data){
  1290. .name = "camss_jpeg_jpeg0_clk",
  1291. .parent_names = (const char *[]){
  1292. "jpeg0_clk_src",
  1293. },
  1294. .num_parents = 1,
  1295. .flags = CLK_SET_RATE_PARENT,
  1296. .ops = &clk_branch2_ops,
  1297. },
  1298. },
  1299. };
  1300. static struct clk_branch camss_jpeg_jpeg1_clk = {
  1301. .halt_reg = 0x35ac,
  1302. .clkr = {
  1303. .enable_reg = 0x35ac,
  1304. .enable_mask = BIT(0),
  1305. .hw.init = &(struct clk_init_data){
  1306. .name = "camss_jpeg_jpeg1_clk",
  1307. .parent_names = (const char *[]){
  1308. "jpeg1_clk_src",
  1309. },
  1310. .num_parents = 1,
  1311. .flags = CLK_SET_RATE_PARENT,
  1312. .ops = &clk_branch2_ops,
  1313. },
  1314. },
  1315. };
  1316. static struct clk_branch camss_jpeg_jpeg2_clk = {
  1317. .halt_reg = 0x35b0,
  1318. .clkr = {
  1319. .enable_reg = 0x35b0,
  1320. .enable_mask = BIT(0),
  1321. .hw.init = &(struct clk_init_data){
  1322. .name = "camss_jpeg_jpeg2_clk",
  1323. .parent_names = (const char *[]){
  1324. "jpeg2_clk_src",
  1325. },
  1326. .num_parents = 1,
  1327. .flags = CLK_SET_RATE_PARENT,
  1328. .ops = &clk_branch2_ops,
  1329. },
  1330. },
  1331. };
  1332. static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
  1333. .halt_reg = 0x35b4,
  1334. .clkr = {
  1335. .enable_reg = 0x35b4,
  1336. .enable_mask = BIT(0),
  1337. .hw.init = &(struct clk_init_data){
  1338. .name = "camss_jpeg_jpeg_ahb_clk",
  1339. .parent_names = (const char *[]){
  1340. "mmss_ahb_clk_src",
  1341. },
  1342. .num_parents = 1,
  1343. .ops = &clk_branch2_ops,
  1344. },
  1345. },
  1346. };
  1347. static struct clk_branch camss_jpeg_jpeg_axi_clk = {
  1348. .halt_reg = 0x35b8,
  1349. .clkr = {
  1350. .enable_reg = 0x35b8,
  1351. .enable_mask = BIT(0),
  1352. .hw.init = &(struct clk_init_data){
  1353. .name = "camss_jpeg_jpeg_axi_clk",
  1354. .parent_names = (const char *[]){
  1355. "mmss_axi_clk_src",
  1356. },
  1357. .num_parents = 1,
  1358. .ops = &clk_branch2_ops,
  1359. },
  1360. },
  1361. };
  1362. static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
  1363. .halt_reg = 0x35bc,
  1364. .clkr = {
  1365. .enable_reg = 0x35bc,
  1366. .enable_mask = BIT(0),
  1367. .hw.init = &(struct clk_init_data){
  1368. .name = "camss_jpeg_jpeg_ocmemnoc_clk",
  1369. .parent_names = (const char *[]){
  1370. "ocmemnoc_clk_src",
  1371. },
  1372. .num_parents = 1,
  1373. .flags = CLK_SET_RATE_PARENT,
  1374. .ops = &clk_branch2_ops,
  1375. },
  1376. },
  1377. };
  1378. static struct clk_branch camss_mclk0_clk = {
  1379. .halt_reg = 0x3384,
  1380. .clkr = {
  1381. .enable_reg = 0x3384,
  1382. .enable_mask = BIT(0),
  1383. .hw.init = &(struct clk_init_data){
  1384. .name = "camss_mclk0_clk",
  1385. .parent_names = (const char *[]){
  1386. "mclk0_clk_src",
  1387. },
  1388. .num_parents = 1,
  1389. .flags = CLK_SET_RATE_PARENT,
  1390. .ops = &clk_branch2_ops,
  1391. },
  1392. },
  1393. };
  1394. static struct clk_branch camss_mclk1_clk = {
  1395. .halt_reg = 0x33b4,
  1396. .clkr = {
  1397. .enable_reg = 0x33b4,
  1398. .enable_mask = BIT(0),
  1399. .hw.init = &(struct clk_init_data){
  1400. .name = "camss_mclk1_clk",
  1401. .parent_names = (const char *[]){
  1402. "mclk1_clk_src",
  1403. },
  1404. .num_parents = 1,
  1405. .flags = CLK_SET_RATE_PARENT,
  1406. .ops = &clk_branch2_ops,
  1407. },
  1408. },
  1409. };
  1410. static struct clk_branch camss_mclk2_clk = {
  1411. .halt_reg = 0x33e4,
  1412. .clkr = {
  1413. .enable_reg = 0x33e4,
  1414. .enable_mask = BIT(0),
  1415. .hw.init = &(struct clk_init_data){
  1416. .name = "camss_mclk2_clk",
  1417. .parent_names = (const char *[]){
  1418. "mclk2_clk_src",
  1419. },
  1420. .num_parents = 1,
  1421. .flags = CLK_SET_RATE_PARENT,
  1422. .ops = &clk_branch2_ops,
  1423. },
  1424. },
  1425. };
  1426. static struct clk_branch camss_mclk3_clk = {
  1427. .halt_reg = 0x3414,
  1428. .clkr = {
  1429. .enable_reg = 0x3414,
  1430. .enable_mask = BIT(0),
  1431. .hw.init = &(struct clk_init_data){
  1432. .name = "camss_mclk3_clk",
  1433. .parent_names = (const char *[]){
  1434. "mclk3_clk_src",
  1435. },
  1436. .num_parents = 1,
  1437. .flags = CLK_SET_RATE_PARENT,
  1438. .ops = &clk_branch2_ops,
  1439. },
  1440. },
  1441. };
  1442. static struct clk_branch camss_micro_ahb_clk = {
  1443. .halt_reg = 0x3494,
  1444. .clkr = {
  1445. .enable_reg = 0x3494,
  1446. .enable_mask = BIT(0),
  1447. .hw.init = &(struct clk_init_data){
  1448. .name = "camss_micro_ahb_clk",
  1449. .parent_names = (const char *[]){
  1450. "mmss_ahb_clk_src",
  1451. },
  1452. .num_parents = 1,
  1453. .ops = &clk_branch2_ops,
  1454. },
  1455. },
  1456. };
  1457. static struct clk_branch camss_phy0_csi0phytimer_clk = {
  1458. .halt_reg = 0x3024,
  1459. .clkr = {
  1460. .enable_reg = 0x3024,
  1461. .enable_mask = BIT(0),
  1462. .hw.init = &(struct clk_init_data){
  1463. .name = "camss_phy0_csi0phytimer_clk",
  1464. .parent_names = (const char *[]){
  1465. "csi0phytimer_clk_src",
  1466. },
  1467. .num_parents = 1,
  1468. .flags = CLK_SET_RATE_PARENT,
  1469. .ops = &clk_branch2_ops,
  1470. },
  1471. },
  1472. };
  1473. static struct clk_branch camss_phy1_csi1phytimer_clk = {
  1474. .halt_reg = 0x3054,
  1475. .clkr = {
  1476. .enable_reg = 0x3054,
  1477. .enable_mask = BIT(0),
  1478. .hw.init = &(struct clk_init_data){
  1479. .name = "camss_phy1_csi1phytimer_clk",
  1480. .parent_names = (const char *[]){
  1481. "csi1phytimer_clk_src",
  1482. },
  1483. .num_parents = 1,
  1484. .flags = CLK_SET_RATE_PARENT,
  1485. .ops = &clk_branch2_ops,
  1486. },
  1487. },
  1488. };
  1489. static struct clk_branch camss_phy2_csi2phytimer_clk = {
  1490. .halt_reg = 0x3084,
  1491. .clkr = {
  1492. .enable_reg = 0x3084,
  1493. .enable_mask = BIT(0),
  1494. .hw.init = &(struct clk_init_data){
  1495. .name = "camss_phy2_csi2phytimer_clk",
  1496. .parent_names = (const char *[]){
  1497. "csi2phytimer_clk_src",
  1498. },
  1499. .num_parents = 1,
  1500. .flags = CLK_SET_RATE_PARENT,
  1501. .ops = &clk_branch2_ops,
  1502. },
  1503. },
  1504. };
  1505. static struct clk_branch camss_top_ahb_clk = {
  1506. .halt_reg = 0x3484,
  1507. .clkr = {
  1508. .enable_reg = 0x3484,
  1509. .enable_mask = BIT(0),
  1510. .hw.init = &(struct clk_init_data){
  1511. .name = "camss_top_ahb_clk",
  1512. .parent_names = (const char *[]){
  1513. "mmss_ahb_clk_src",
  1514. },
  1515. .num_parents = 1,
  1516. .ops = &clk_branch2_ops,
  1517. },
  1518. },
  1519. };
  1520. static struct clk_branch camss_vfe_cpp_ahb_clk = {
  1521. .halt_reg = 0x36b4,
  1522. .clkr = {
  1523. .enable_reg = 0x36b4,
  1524. .enable_mask = BIT(0),
  1525. .hw.init = &(struct clk_init_data){
  1526. .name = "camss_vfe_cpp_ahb_clk",
  1527. .parent_names = (const char *[]){
  1528. "mmss_ahb_clk_src",
  1529. },
  1530. .num_parents = 1,
  1531. .ops = &clk_branch2_ops,
  1532. },
  1533. },
  1534. };
  1535. static struct clk_branch camss_vfe_cpp_clk = {
  1536. .halt_reg = 0x36b0,
  1537. .clkr = {
  1538. .enable_reg = 0x36b0,
  1539. .enable_mask = BIT(0),
  1540. .hw.init = &(struct clk_init_data){
  1541. .name = "camss_vfe_cpp_clk",
  1542. .parent_names = (const char *[]){
  1543. "cpp_clk_src",
  1544. },
  1545. .num_parents = 1,
  1546. .flags = CLK_SET_RATE_PARENT,
  1547. .ops = &clk_branch2_ops,
  1548. },
  1549. },
  1550. };
  1551. static struct clk_branch camss_vfe_vfe0_clk = {
  1552. .halt_reg = 0x36a8,
  1553. .clkr = {
  1554. .enable_reg = 0x36a8,
  1555. .enable_mask = BIT(0),
  1556. .hw.init = &(struct clk_init_data){
  1557. .name = "camss_vfe_vfe0_clk",
  1558. .parent_names = (const char *[]){
  1559. "vfe0_clk_src",
  1560. },
  1561. .num_parents = 1,
  1562. .flags = CLK_SET_RATE_PARENT,
  1563. .ops = &clk_branch2_ops,
  1564. },
  1565. },
  1566. };
  1567. static struct clk_branch camss_vfe_vfe1_clk = {
  1568. .halt_reg = 0x36ac,
  1569. .clkr = {
  1570. .enable_reg = 0x36ac,
  1571. .enable_mask = BIT(0),
  1572. .hw.init = &(struct clk_init_data){
  1573. .name = "camss_vfe_vfe1_clk",
  1574. .parent_names = (const char *[]){
  1575. "vfe1_clk_src",
  1576. },
  1577. .num_parents = 1,
  1578. .flags = CLK_SET_RATE_PARENT,
  1579. .ops = &clk_branch2_ops,
  1580. },
  1581. },
  1582. };
  1583. static struct clk_branch camss_vfe_vfe_ahb_clk = {
  1584. .halt_reg = 0x36b8,
  1585. .clkr = {
  1586. .enable_reg = 0x36b8,
  1587. .enable_mask = BIT(0),
  1588. .hw.init = &(struct clk_init_data){
  1589. .name = "camss_vfe_vfe_ahb_clk",
  1590. .parent_names = (const char *[]){
  1591. "mmss_ahb_clk_src",
  1592. },
  1593. .num_parents = 1,
  1594. .ops = &clk_branch2_ops,
  1595. },
  1596. },
  1597. };
  1598. static struct clk_branch camss_vfe_vfe_axi_clk = {
  1599. .halt_reg = 0x36bc,
  1600. .clkr = {
  1601. .enable_reg = 0x36bc,
  1602. .enable_mask = BIT(0),
  1603. .hw.init = &(struct clk_init_data){
  1604. .name = "camss_vfe_vfe_axi_clk",
  1605. .parent_names = (const char *[]){
  1606. "mmss_axi_clk_src",
  1607. },
  1608. .num_parents = 1,
  1609. .ops = &clk_branch2_ops,
  1610. },
  1611. },
  1612. };
  1613. static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
  1614. .halt_reg = 0x36c0,
  1615. .clkr = {
  1616. .enable_reg = 0x36c0,
  1617. .enable_mask = BIT(0),
  1618. .hw.init = &(struct clk_init_data){
  1619. .name = "camss_vfe_vfe_ocmemnoc_clk",
  1620. .parent_names = (const char *[]){
  1621. "ocmemnoc_clk_src",
  1622. },
  1623. .num_parents = 1,
  1624. .flags = CLK_SET_RATE_PARENT,
  1625. .ops = &clk_branch2_ops,
  1626. },
  1627. },
  1628. };
  1629. static struct clk_branch mdss_ahb_clk = {
  1630. .halt_reg = 0x2308,
  1631. .clkr = {
  1632. .enable_reg = 0x2308,
  1633. .enable_mask = BIT(0),
  1634. .hw.init = &(struct clk_init_data){
  1635. .name = "mdss_ahb_clk",
  1636. .parent_names = (const char *[]){
  1637. "mmss_ahb_clk_src",
  1638. },
  1639. .num_parents = 1,
  1640. .ops = &clk_branch2_ops,
  1641. },
  1642. },
  1643. };
  1644. static struct clk_branch mdss_axi_clk = {
  1645. .halt_reg = 0x2310,
  1646. .clkr = {
  1647. .enable_reg = 0x2310,
  1648. .enable_mask = BIT(0),
  1649. .hw.init = &(struct clk_init_data){
  1650. .name = "mdss_axi_clk",
  1651. .parent_names = (const char *[]){
  1652. "mmss_axi_clk_src",
  1653. },
  1654. .num_parents = 1,
  1655. .flags = CLK_SET_RATE_PARENT,
  1656. .ops = &clk_branch2_ops,
  1657. },
  1658. },
  1659. };
  1660. static struct clk_branch mdss_byte0_clk = {
  1661. .halt_reg = 0x233c,
  1662. .clkr = {
  1663. .enable_reg = 0x233c,
  1664. .enable_mask = BIT(0),
  1665. .hw.init = &(struct clk_init_data){
  1666. .name = "mdss_byte0_clk",
  1667. .parent_names = (const char *[]){
  1668. "byte0_clk_src",
  1669. },
  1670. .num_parents = 1,
  1671. .flags = CLK_SET_RATE_PARENT,
  1672. .ops = &clk_branch2_ops,
  1673. },
  1674. },
  1675. };
  1676. static struct clk_branch mdss_byte1_clk = {
  1677. .halt_reg = 0x2340,
  1678. .clkr = {
  1679. .enable_reg = 0x2340,
  1680. .enable_mask = BIT(0),
  1681. .hw.init = &(struct clk_init_data){
  1682. .name = "mdss_byte1_clk",
  1683. .parent_names = (const char *[]){
  1684. "byte1_clk_src",
  1685. },
  1686. .num_parents = 1,
  1687. .flags = CLK_SET_RATE_PARENT,
  1688. .ops = &clk_branch2_ops,
  1689. },
  1690. },
  1691. };
  1692. static struct clk_branch mdss_edpaux_clk = {
  1693. .halt_reg = 0x2334,
  1694. .clkr = {
  1695. .enable_reg = 0x2334,
  1696. .enable_mask = BIT(0),
  1697. .hw.init = &(struct clk_init_data){
  1698. .name = "mdss_edpaux_clk",
  1699. .parent_names = (const char *[]){
  1700. "edpaux_clk_src",
  1701. },
  1702. .num_parents = 1,
  1703. .flags = CLK_SET_RATE_PARENT,
  1704. .ops = &clk_branch2_ops,
  1705. },
  1706. },
  1707. };
  1708. static struct clk_branch mdss_edplink_clk = {
  1709. .halt_reg = 0x2330,
  1710. .clkr = {
  1711. .enable_reg = 0x2330,
  1712. .enable_mask = BIT(0),
  1713. .hw.init = &(struct clk_init_data){
  1714. .name = "mdss_edplink_clk",
  1715. .parent_names = (const char *[]){
  1716. "edplink_clk_src",
  1717. },
  1718. .num_parents = 1,
  1719. .flags = CLK_SET_RATE_PARENT,
  1720. .ops = &clk_branch2_ops,
  1721. },
  1722. },
  1723. };
  1724. static struct clk_branch mdss_edppixel_clk = {
  1725. .halt_reg = 0x232c,
  1726. .clkr = {
  1727. .enable_reg = 0x232c,
  1728. .enable_mask = BIT(0),
  1729. .hw.init = &(struct clk_init_data){
  1730. .name = "mdss_edppixel_clk",
  1731. .parent_names = (const char *[]){
  1732. "edppixel_clk_src",
  1733. },
  1734. .num_parents = 1,
  1735. .flags = CLK_SET_RATE_PARENT,
  1736. .ops = &clk_branch2_ops,
  1737. },
  1738. },
  1739. };
  1740. static struct clk_branch mdss_esc0_clk = {
  1741. .halt_reg = 0x2344,
  1742. .clkr = {
  1743. .enable_reg = 0x2344,
  1744. .enable_mask = BIT(0),
  1745. .hw.init = &(struct clk_init_data){
  1746. .name = "mdss_esc0_clk",
  1747. .parent_names = (const char *[]){
  1748. "esc0_clk_src",
  1749. },
  1750. .num_parents = 1,
  1751. .flags = CLK_SET_RATE_PARENT,
  1752. .ops = &clk_branch2_ops,
  1753. },
  1754. },
  1755. };
  1756. static struct clk_branch mdss_esc1_clk = {
  1757. .halt_reg = 0x2348,
  1758. .clkr = {
  1759. .enable_reg = 0x2348,
  1760. .enable_mask = BIT(0),
  1761. .hw.init = &(struct clk_init_data){
  1762. .name = "mdss_esc1_clk",
  1763. .parent_names = (const char *[]){
  1764. "esc1_clk_src",
  1765. },
  1766. .num_parents = 1,
  1767. .flags = CLK_SET_RATE_PARENT,
  1768. .ops = &clk_branch2_ops,
  1769. },
  1770. },
  1771. };
  1772. static struct clk_branch mdss_extpclk_clk = {
  1773. .halt_reg = 0x2324,
  1774. .clkr = {
  1775. .enable_reg = 0x2324,
  1776. .enable_mask = BIT(0),
  1777. .hw.init = &(struct clk_init_data){
  1778. .name = "mdss_extpclk_clk",
  1779. .parent_names = (const char *[]){
  1780. "extpclk_clk_src",
  1781. },
  1782. .num_parents = 1,
  1783. .flags = CLK_SET_RATE_PARENT,
  1784. .ops = &clk_branch2_ops,
  1785. },
  1786. },
  1787. };
  1788. static struct clk_branch mdss_hdmi_ahb_clk = {
  1789. .halt_reg = 0x230c,
  1790. .clkr = {
  1791. .enable_reg = 0x230c,
  1792. .enable_mask = BIT(0),
  1793. .hw.init = &(struct clk_init_data){
  1794. .name = "mdss_hdmi_ahb_clk",
  1795. .parent_names = (const char *[]){
  1796. "mmss_ahb_clk_src",
  1797. },
  1798. .num_parents = 1,
  1799. .ops = &clk_branch2_ops,
  1800. },
  1801. },
  1802. };
  1803. static struct clk_branch mdss_hdmi_clk = {
  1804. .halt_reg = 0x2338,
  1805. .clkr = {
  1806. .enable_reg = 0x2338,
  1807. .enable_mask = BIT(0),
  1808. .hw.init = &(struct clk_init_data){
  1809. .name = "mdss_hdmi_clk",
  1810. .parent_names = (const char *[]){
  1811. "hdmi_clk_src",
  1812. },
  1813. .num_parents = 1,
  1814. .flags = CLK_SET_RATE_PARENT,
  1815. .ops = &clk_branch2_ops,
  1816. },
  1817. },
  1818. };
  1819. static struct clk_branch mdss_mdp_clk = {
  1820. .halt_reg = 0x231c,
  1821. .clkr = {
  1822. .enable_reg = 0x231c,
  1823. .enable_mask = BIT(0),
  1824. .hw.init = &(struct clk_init_data){
  1825. .name = "mdss_mdp_clk",
  1826. .parent_names = (const char *[]){
  1827. "mdp_clk_src",
  1828. },
  1829. .num_parents = 1,
  1830. .flags = CLK_SET_RATE_PARENT,
  1831. .ops = &clk_branch2_ops,
  1832. },
  1833. },
  1834. };
  1835. static struct clk_branch mdss_mdp_lut_clk = {
  1836. .halt_reg = 0x2320,
  1837. .clkr = {
  1838. .enable_reg = 0x2320,
  1839. .enable_mask = BIT(0),
  1840. .hw.init = &(struct clk_init_data){
  1841. .name = "mdss_mdp_lut_clk",
  1842. .parent_names = (const char *[]){
  1843. "mdp_clk_src",
  1844. },
  1845. .num_parents = 1,
  1846. .flags = CLK_SET_RATE_PARENT,
  1847. .ops = &clk_branch2_ops,
  1848. },
  1849. },
  1850. };
  1851. static struct clk_branch mdss_pclk0_clk = {
  1852. .halt_reg = 0x2314,
  1853. .clkr = {
  1854. .enable_reg = 0x2314,
  1855. .enable_mask = BIT(0),
  1856. .hw.init = &(struct clk_init_data){
  1857. .name = "mdss_pclk0_clk",
  1858. .parent_names = (const char *[]){
  1859. "pclk0_clk_src",
  1860. },
  1861. .num_parents = 1,
  1862. .flags = CLK_SET_RATE_PARENT,
  1863. .ops = &clk_branch2_ops,
  1864. },
  1865. },
  1866. };
  1867. static struct clk_branch mdss_pclk1_clk = {
  1868. .halt_reg = 0x2318,
  1869. .clkr = {
  1870. .enable_reg = 0x2318,
  1871. .enable_mask = BIT(0),
  1872. .hw.init = &(struct clk_init_data){
  1873. .name = "mdss_pclk1_clk",
  1874. .parent_names = (const char *[]){
  1875. "pclk1_clk_src",
  1876. },
  1877. .num_parents = 1,
  1878. .flags = CLK_SET_RATE_PARENT,
  1879. .ops = &clk_branch2_ops,
  1880. },
  1881. },
  1882. };
  1883. static struct clk_branch mdss_vsync_clk = {
  1884. .halt_reg = 0x2328,
  1885. .clkr = {
  1886. .enable_reg = 0x2328,
  1887. .enable_mask = BIT(0),
  1888. .hw.init = &(struct clk_init_data){
  1889. .name = "mdss_vsync_clk",
  1890. .parent_names = (const char *[]){
  1891. "vsync_clk_src",
  1892. },
  1893. .num_parents = 1,
  1894. .flags = CLK_SET_RATE_PARENT,
  1895. .ops = &clk_branch2_ops,
  1896. },
  1897. },
  1898. };
  1899. static struct clk_branch mmss_misc_ahb_clk = {
  1900. .halt_reg = 0x502c,
  1901. .clkr = {
  1902. .enable_reg = 0x502c,
  1903. .enable_mask = BIT(0),
  1904. .hw.init = &(struct clk_init_data){
  1905. .name = "mmss_misc_ahb_clk",
  1906. .parent_names = (const char *[]){
  1907. "mmss_ahb_clk_src",
  1908. },
  1909. .num_parents = 1,
  1910. .ops = &clk_branch2_ops,
  1911. },
  1912. },
  1913. };
  1914. static struct clk_branch mmss_mmssnoc_ahb_clk = {
  1915. .halt_reg = 0x5024,
  1916. .clkr = {
  1917. .enable_reg = 0x5024,
  1918. .enable_mask = BIT(0),
  1919. .hw.init = &(struct clk_init_data){
  1920. .name = "mmss_mmssnoc_ahb_clk",
  1921. .parent_names = (const char *[]){
  1922. "mmss_ahb_clk_src",
  1923. },
  1924. .num_parents = 1,
  1925. .ops = &clk_branch2_ops,
  1926. .flags = CLK_IGNORE_UNUSED,
  1927. },
  1928. },
  1929. };
  1930. static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
  1931. .halt_reg = 0x5028,
  1932. .clkr = {
  1933. .enable_reg = 0x5028,
  1934. .enable_mask = BIT(0),
  1935. .hw.init = &(struct clk_init_data){
  1936. .name = "mmss_mmssnoc_bto_ahb_clk",
  1937. .parent_names = (const char *[]){
  1938. "mmss_ahb_clk_src",
  1939. },
  1940. .num_parents = 1,
  1941. .ops = &clk_branch2_ops,
  1942. .flags = CLK_IGNORE_UNUSED,
  1943. },
  1944. },
  1945. };
  1946. static struct clk_branch mmss_mmssnoc_axi_clk = {
  1947. .halt_reg = 0x506c,
  1948. .clkr = {
  1949. .enable_reg = 0x506c,
  1950. .enable_mask = BIT(0),
  1951. .hw.init = &(struct clk_init_data){
  1952. .name = "mmss_mmssnoc_axi_clk",
  1953. .parent_names = (const char *[]){
  1954. "mmss_axi_clk_src",
  1955. },
  1956. .num_parents = 1,
  1957. .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
  1958. .ops = &clk_branch2_ops,
  1959. },
  1960. },
  1961. };
  1962. static struct clk_branch mmss_s0_axi_clk = {
  1963. .halt_reg = 0x5064,
  1964. .clkr = {
  1965. .enable_reg = 0x5064,
  1966. .enable_mask = BIT(0),
  1967. .hw.init = &(struct clk_init_data){
  1968. .name = "mmss_s0_axi_clk",
  1969. .parent_names = (const char *[]){
  1970. "mmss_axi_clk_src",
  1971. },
  1972. .num_parents = 1,
  1973. .ops = &clk_branch2_ops,
  1974. .flags = CLK_IGNORE_UNUSED,
  1975. },
  1976. },
  1977. };
  1978. static struct clk_branch ocmemcx_ahb_clk = {
  1979. .halt_reg = 0x405c,
  1980. .clkr = {
  1981. .enable_reg = 0x405c,
  1982. .enable_mask = BIT(0),
  1983. .hw.init = &(struct clk_init_data){
  1984. .name = "ocmemcx_ahb_clk",
  1985. .parent_names = (const char *[]){
  1986. "mmss_ahb_clk_src",
  1987. },
  1988. .num_parents = 1,
  1989. .ops = &clk_branch2_ops,
  1990. },
  1991. },
  1992. };
  1993. static struct clk_branch ocmemcx_ocmemnoc_clk = {
  1994. .halt_reg = 0x4058,
  1995. .clkr = {
  1996. .enable_reg = 0x4058,
  1997. .enable_mask = BIT(0),
  1998. .hw.init = &(struct clk_init_data){
  1999. .name = "ocmemcx_ocmemnoc_clk",
  2000. .parent_names = (const char *[]){
  2001. "ocmemnoc_clk_src",
  2002. },
  2003. .num_parents = 1,
  2004. .flags = CLK_SET_RATE_PARENT,
  2005. .ops = &clk_branch2_ops,
  2006. },
  2007. },
  2008. };
  2009. static struct clk_branch oxili_ocmemgx_clk = {
  2010. .halt_reg = 0x402c,
  2011. .clkr = {
  2012. .enable_reg = 0x402c,
  2013. .enable_mask = BIT(0),
  2014. .hw.init = &(struct clk_init_data){
  2015. .name = "oxili_ocmemgx_clk",
  2016. .parent_names = (const char *[]){
  2017. "gfx3d_clk_src",
  2018. },
  2019. .num_parents = 1,
  2020. .flags = CLK_SET_RATE_PARENT,
  2021. .ops = &clk_branch2_ops,
  2022. },
  2023. },
  2024. };
  2025. static struct clk_branch ocmemnoc_clk = {
  2026. .halt_reg = 0x50b4,
  2027. .clkr = {
  2028. .enable_reg = 0x50b4,
  2029. .enable_mask = BIT(0),
  2030. .hw.init = &(struct clk_init_data){
  2031. .name = "ocmemnoc_clk",
  2032. .parent_names = (const char *[]){
  2033. "ocmemnoc_clk_src",
  2034. },
  2035. .num_parents = 1,
  2036. .flags = CLK_SET_RATE_PARENT,
  2037. .ops = &clk_branch2_ops,
  2038. },
  2039. },
  2040. };
  2041. static struct clk_branch oxili_gfx3d_clk = {
  2042. .halt_reg = 0x4028,
  2043. .clkr = {
  2044. .enable_reg = 0x4028,
  2045. .enable_mask = BIT(0),
  2046. .hw.init = &(struct clk_init_data){
  2047. .name = "oxili_gfx3d_clk",
  2048. .parent_names = (const char *[]){
  2049. "gfx3d_clk_src",
  2050. },
  2051. .num_parents = 1,
  2052. .flags = CLK_SET_RATE_PARENT,
  2053. .ops = &clk_branch2_ops,
  2054. },
  2055. },
  2056. };
  2057. static struct clk_branch oxilicx_ahb_clk = {
  2058. .halt_reg = 0x403c,
  2059. .clkr = {
  2060. .enable_reg = 0x403c,
  2061. .enable_mask = BIT(0),
  2062. .hw.init = &(struct clk_init_data){
  2063. .name = "oxilicx_ahb_clk",
  2064. .parent_names = (const char *[]){
  2065. "mmss_ahb_clk_src",
  2066. },
  2067. .num_parents = 1,
  2068. .ops = &clk_branch2_ops,
  2069. },
  2070. },
  2071. };
  2072. static struct clk_branch oxilicx_axi_clk = {
  2073. .halt_reg = 0x4038,
  2074. .clkr = {
  2075. .enable_reg = 0x4038,
  2076. .enable_mask = BIT(0),
  2077. .hw.init = &(struct clk_init_data){
  2078. .name = "oxilicx_axi_clk",
  2079. .parent_names = (const char *[]){
  2080. "mmss_axi_clk_src",
  2081. },
  2082. .num_parents = 1,
  2083. .ops = &clk_branch2_ops,
  2084. },
  2085. },
  2086. };
  2087. static struct clk_branch venus0_ahb_clk = {
  2088. .halt_reg = 0x1030,
  2089. .clkr = {
  2090. .enable_reg = 0x1030,
  2091. .enable_mask = BIT(0),
  2092. .hw.init = &(struct clk_init_data){
  2093. .name = "venus0_ahb_clk",
  2094. .parent_names = (const char *[]){
  2095. "mmss_ahb_clk_src",
  2096. },
  2097. .num_parents = 1,
  2098. .ops = &clk_branch2_ops,
  2099. },
  2100. },
  2101. };
  2102. static struct clk_branch venus0_axi_clk = {
  2103. .halt_reg = 0x1034,
  2104. .clkr = {
  2105. .enable_reg = 0x1034,
  2106. .enable_mask = BIT(0),
  2107. .hw.init = &(struct clk_init_data){
  2108. .name = "venus0_axi_clk",
  2109. .parent_names = (const char *[]){
  2110. "mmss_axi_clk_src",
  2111. },
  2112. .num_parents = 1,
  2113. .ops = &clk_branch2_ops,
  2114. },
  2115. },
  2116. };
  2117. static struct clk_branch venus0_ocmemnoc_clk = {
  2118. .halt_reg = 0x1038,
  2119. .clkr = {
  2120. .enable_reg = 0x1038,
  2121. .enable_mask = BIT(0),
  2122. .hw.init = &(struct clk_init_data){
  2123. .name = "venus0_ocmemnoc_clk",
  2124. .parent_names = (const char *[]){
  2125. "ocmemnoc_clk_src",
  2126. },
  2127. .num_parents = 1,
  2128. .flags = CLK_SET_RATE_PARENT,
  2129. .ops = &clk_branch2_ops,
  2130. },
  2131. },
  2132. };
  2133. static struct clk_branch venus0_vcodec0_clk = {
  2134. .halt_reg = 0x1028,
  2135. .clkr = {
  2136. .enable_reg = 0x1028,
  2137. .enable_mask = BIT(0),
  2138. .hw.init = &(struct clk_init_data){
  2139. .name = "venus0_vcodec0_clk",
  2140. .parent_names = (const char *[]){
  2141. "vcodec0_clk_src",
  2142. },
  2143. .num_parents = 1,
  2144. .flags = CLK_SET_RATE_PARENT,
  2145. .ops = &clk_branch2_ops,
  2146. },
  2147. },
  2148. };
  2149. static const struct pll_config mmpll1_config = {
  2150. .l = 60,
  2151. .m = 25,
  2152. .n = 32,
  2153. .vco_val = 0x0,
  2154. .vco_mask = 0x3 << 20,
  2155. .pre_div_val = 0x0,
  2156. .pre_div_mask = 0x7 << 12,
  2157. .post_div_val = 0x0,
  2158. .post_div_mask = 0x3 << 8,
  2159. .mn_ena_mask = BIT(24),
  2160. .main_output_mask = BIT(0),
  2161. };
  2162. static struct pll_config mmpll3_config = {
  2163. .l = 48,
  2164. .m = 7,
  2165. .n = 16,
  2166. .vco_val = 0x0,
  2167. .vco_mask = 0x3 << 20,
  2168. .pre_div_val = 0x0,
  2169. .pre_div_mask = 0x7 << 12,
  2170. .post_div_val = 0x0,
  2171. .post_div_mask = 0x3 << 8,
  2172. .mn_ena_mask = BIT(24),
  2173. .main_output_mask = BIT(0),
  2174. .aux_output_mask = BIT(1),
  2175. };
  2176. static struct gdsc venus0_gdsc = {
  2177. .gdscr = 0x1024,
  2178. .cxcs = (unsigned int []){ 0x1028 },
  2179. .cxc_count = 1,
  2180. .resets = (unsigned int []){ VENUS0_RESET },
  2181. .reset_count = 1,
  2182. .pd = {
  2183. .name = "venus0",
  2184. },
  2185. .pwrsts = PWRSTS_ON,
  2186. };
  2187. static struct gdsc mdss_gdsc = {
  2188. .gdscr = 0x2304,
  2189. .cxcs = (unsigned int []){ 0x231c, 0x2320 },
  2190. .cxc_count = 2,
  2191. .pd = {
  2192. .name = "mdss",
  2193. },
  2194. .pwrsts = PWRSTS_RET_ON,
  2195. };
  2196. static struct gdsc camss_jpeg_gdsc = {
  2197. .gdscr = 0x35a4,
  2198. .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
  2199. .cxc_count = 3,
  2200. .pd = {
  2201. .name = "camss_jpeg",
  2202. },
  2203. .pwrsts = PWRSTS_OFF_ON,
  2204. };
  2205. static struct gdsc camss_vfe_gdsc = {
  2206. .gdscr = 0x36a4,
  2207. .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
  2208. .cxc_count = 5,
  2209. .pd = {
  2210. .name = "camss_vfe",
  2211. },
  2212. .pwrsts = PWRSTS_OFF_ON,
  2213. };
  2214. static struct gdsc oxili_gdsc = {
  2215. .gdscr = 0x4024,
  2216. .cxcs = (unsigned int []){ 0x4028 },
  2217. .cxc_count = 1,
  2218. .pd = {
  2219. .name = "oxili",
  2220. },
  2221. .pwrsts = PWRSTS_OFF_ON,
  2222. };
  2223. static struct gdsc oxilicx_gdsc = {
  2224. .gdscr = 0x4034,
  2225. .pd = {
  2226. .name = "oxilicx",
  2227. },
  2228. .parent = &oxili_gdsc.pd,
  2229. .pwrsts = PWRSTS_OFF_ON,
  2230. };
  2231. static struct clk_regmap *mmcc_msm8974_clocks[] = {
  2232. [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
  2233. [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
  2234. [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
  2235. [MMPLL0] = &mmpll0.clkr,
  2236. [MMPLL0_VOTE] = &mmpll0_vote,
  2237. [MMPLL1] = &mmpll1.clkr,
  2238. [MMPLL1_VOTE] = &mmpll1_vote,
  2239. [MMPLL2] = &mmpll2.clkr,
  2240. [MMPLL3] = &mmpll3.clkr,
  2241. [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
  2242. [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
  2243. [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
  2244. [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
  2245. [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
  2246. [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
  2247. [MDP_CLK_SRC] = &mdp_clk_src.clkr,
  2248. [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
  2249. [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
  2250. [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
  2251. [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
  2252. [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
  2253. [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
  2254. [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
  2255. [CCI_CLK_SRC] = &cci_clk_src.clkr,
  2256. [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
  2257. [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
  2258. [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
  2259. [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
  2260. [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
  2261. [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
  2262. [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
  2263. [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
  2264. [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
  2265. [CPP_CLK_SRC] = &cpp_clk_src.clkr,
  2266. [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
  2267. [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
  2268. [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
  2269. [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
  2270. [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
  2271. [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
  2272. [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
  2273. [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
  2274. [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
  2275. [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
  2276. [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
  2277. [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
  2278. [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
  2279. [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
  2280. [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
  2281. [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
  2282. [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
  2283. [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
  2284. [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
  2285. [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
  2286. [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
  2287. [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
  2288. [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
  2289. [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
  2290. [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
  2291. [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
  2292. [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
  2293. [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
  2294. [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
  2295. [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
  2296. [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
  2297. [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
  2298. [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
  2299. [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
  2300. [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
  2301. [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
  2302. [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
  2303. [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
  2304. [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
  2305. [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
  2306. [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
  2307. [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
  2308. [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
  2309. [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
  2310. [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
  2311. [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
  2312. [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
  2313. [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
  2314. [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
  2315. [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
  2316. [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
  2317. [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
  2318. [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
  2319. [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
  2320. [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
  2321. [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
  2322. [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
  2323. [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
  2324. [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
  2325. [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
  2326. [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
  2327. [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
  2328. [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
  2329. [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
  2330. [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
  2331. [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
  2332. [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
  2333. [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
  2334. [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
  2335. [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
  2336. [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
  2337. [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
  2338. [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
  2339. [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
  2340. [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
  2341. [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
  2342. [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
  2343. [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
  2344. [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
  2345. [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
  2346. [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
  2347. [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
  2348. [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
  2349. [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
  2350. [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
  2351. [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
  2352. [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
  2353. [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
  2354. [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
  2355. [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
  2356. [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
  2357. [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
  2358. };
  2359. static const struct qcom_reset_map mmcc_msm8974_resets[] = {
  2360. [SPDM_RESET] = { 0x0200 },
  2361. [SPDM_RM_RESET] = { 0x0300 },
  2362. [VENUS0_RESET] = { 0x1020 },
  2363. [MDSS_RESET] = { 0x2300 },
  2364. [CAMSS_PHY0_RESET] = { 0x3020 },
  2365. [CAMSS_PHY1_RESET] = { 0x3050 },
  2366. [CAMSS_PHY2_RESET] = { 0x3080 },
  2367. [CAMSS_CSI0_RESET] = { 0x30b0 },
  2368. [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
  2369. [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
  2370. [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
  2371. [CAMSS_CSI1_RESET] = { 0x3120 },
  2372. [CAMSS_CSI1PHY_RESET] = { 0x3130 },
  2373. [CAMSS_CSI1RDI_RESET] = { 0x3140 },
  2374. [CAMSS_CSI1PIX_RESET] = { 0x3150 },
  2375. [CAMSS_CSI2_RESET] = { 0x3180 },
  2376. [CAMSS_CSI2PHY_RESET] = { 0x3190 },
  2377. [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
  2378. [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
  2379. [CAMSS_CSI3_RESET] = { 0x31e0 },
  2380. [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
  2381. [CAMSS_CSI3RDI_RESET] = { 0x3200 },
  2382. [CAMSS_CSI3PIX_RESET] = { 0x3210 },
  2383. [CAMSS_ISPIF_RESET] = { 0x3220 },
  2384. [CAMSS_CCI_RESET] = { 0x3340 },
  2385. [CAMSS_MCLK0_RESET] = { 0x3380 },
  2386. [CAMSS_MCLK1_RESET] = { 0x33b0 },
  2387. [CAMSS_MCLK2_RESET] = { 0x33e0 },
  2388. [CAMSS_MCLK3_RESET] = { 0x3410 },
  2389. [CAMSS_GP0_RESET] = { 0x3440 },
  2390. [CAMSS_GP1_RESET] = { 0x3470 },
  2391. [CAMSS_TOP_RESET] = { 0x3480 },
  2392. [CAMSS_MICRO_RESET] = { 0x3490 },
  2393. [CAMSS_JPEG_RESET] = { 0x35a0 },
  2394. [CAMSS_VFE_RESET] = { 0x36a0 },
  2395. [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
  2396. [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
  2397. [OXILI_RESET] = { 0x4020 },
  2398. [OXILICX_RESET] = { 0x4030 },
  2399. [OCMEMCX_RESET] = { 0x4050 },
  2400. [MMSS_RBCRP_RESET] = { 0x4080 },
  2401. [MMSSNOCAHB_RESET] = { 0x5020 },
  2402. [MMSSNOCAXI_RESET] = { 0x5060 },
  2403. [OCMEMNOC_RESET] = { 0x50b0 },
  2404. };
  2405. static struct gdsc *mmcc_msm8974_gdscs[] = {
  2406. [VENUS0_GDSC] = &venus0_gdsc,
  2407. [MDSS_GDSC] = &mdss_gdsc,
  2408. [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
  2409. [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
  2410. [OXILI_GDSC] = &oxili_gdsc,
  2411. [OXILICX_GDSC] = &oxilicx_gdsc,
  2412. };
  2413. static const struct regmap_config mmcc_msm8974_regmap_config = {
  2414. .reg_bits = 32,
  2415. .reg_stride = 4,
  2416. .val_bits = 32,
  2417. .max_register = 0x5104,
  2418. .fast_io = true,
  2419. };
  2420. static const struct qcom_cc_desc mmcc_msm8974_desc = {
  2421. .config = &mmcc_msm8974_regmap_config,
  2422. .clks = mmcc_msm8974_clocks,
  2423. .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
  2424. .resets = mmcc_msm8974_resets,
  2425. .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
  2426. .gdscs = mmcc_msm8974_gdscs,
  2427. .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
  2428. };
  2429. static const struct of_device_id mmcc_msm8974_match_table[] = {
  2430. { .compatible = "qcom,mmcc-msm8974" },
  2431. { }
  2432. };
  2433. MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
  2434. static int mmcc_msm8974_probe(struct platform_device *pdev)
  2435. {
  2436. struct regmap *regmap;
  2437. regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
  2438. if (IS_ERR(regmap))
  2439. return PTR_ERR(regmap);
  2440. clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
  2441. clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
  2442. return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
  2443. }
  2444. static struct platform_driver mmcc_msm8974_driver = {
  2445. .probe = mmcc_msm8974_probe,
  2446. .driver = {
  2447. .name = "mmcc-msm8974",
  2448. .of_match_table = mmcc_msm8974_match_table,
  2449. },
  2450. };
  2451. module_platform_driver(mmcc_msm8974_driver);
  2452. MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
  2453. MODULE_LICENSE("GPL v2");
  2454. MODULE_ALIAS("platform:mmcc-msm8974");