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linux-4.9.59+gitAUTOINC+a75d8e9305-ga75d8e9305
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drivers
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clk
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qcom
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gdsc.h

gdsc.h 2.2 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License version 2 and
    6. 

  6.  * only version 2 as published by the Free Software Foundation.
    7. 

  7.  *
    8. 

  8.  * This program is distributed in the hope that it will be useful,
    9. 

  9.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    10. 

  10.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    11. 

  11.  * GNU General Public License for more details.
    12. 

  12.  */
    13. 

  13. 

  14. #ifndef __QCOM_GDSC_H__
    15. 

  15. #define __QCOM_GDSC_H__
    16. 

  16. 

  17. #include <linux/err.h>
    18. 

  18. #include <linux/pm_domain.h>
    19. 

  19. 

  20. struct regmap;
    21. 

  21. struct reset_controller_dev;
    22. 

  22. 

  23. /**
    24. 

  24.  * struct gdsc - Globally Distributed Switch Controller
    25. 

  25.  * @pd: generic power domain
    26. 

  26.  * @regmap: regmap for MMIO accesses
    27. 

  27.  * @gdscr: gsdc control register
    28. 

  28.  * @gds_hw_ctrl: gds_hw_ctrl register
    29. 

  29.  * @cxcs: offsets of branch registers to toggle mem/periph bits in
    30. 

  30.  * @cxc_count: number of @cxcs
    31. 

  31.  * @pwrsts: Possible powerdomain power states
    32. 

  32.  * @resets: ids of resets associated with this gdsc
    33. 

  33.  * @reset_count: number of @resets
    34. 

  34.  * @rcdev: reset controller
    35. 

  35.  */
    36. 

  36. struct gdsc {
    37. 

  37. 	struct generic_pm_domain	pd;
    38. 

  38. 	struct generic_pm_domain	*parent;
    39. 

  39. 	struct regmap			*regmap;
    40. 

  40. 	unsigned int			gdscr;
    41. 

  41. 	unsigned int			gds_hw_ctrl;
    42. 

  42. 	unsigned int			*cxcs;
    43. 

  43. 	unsigned int			cxc_count;
    44. 

  44. 	const u8			pwrsts;
    45. 

  45. /* Powerdomain allowable state bitfields */
    46. 

  46. #define PWRSTS_OFF		BIT(0)
    47. 

  47. #define PWRSTS_RET		BIT(1)
    48. 

  48. #define PWRSTS_ON		BIT(2)
    49. 

  49. #define PWRSTS_OFF_ON		(PWRSTS_OFF | PWRSTS_ON)
    50. 

  50. #define PWRSTS_RET_ON		(PWRSTS_RET | PWRSTS_ON)
    51. 

  51. 	const u8			flags;
    52. 

  52. #define VOTABLE		BIT(0)
    53. 

  53. 	struct reset_controller_dev	*rcdev;
    54. 

  54. 	unsigned int			*resets;
    55. 

  55. 	unsigned int			reset_count;
    56. 

  56. };
    57. 

  57. 

  58. struct gdsc_desc {
    59. 

  59. 	struct device *dev;
    60. 

  60. 	struct gdsc **scs;
    61. 

  61. 	size_t num;
    62. 

  62. };
    63. 

  63. 

  64. #ifdef CONFIG_QCOM_GDSC
    65. 

  65. int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
    66. 

  66. 		  struct regmap *);
    67. 

  67. void gdsc_unregister(struct gdsc_desc *desc);
    68. 

  68. #else
    69. 

  69. static inline int gdsc_register(struct gdsc_desc *desc,
    70. 

  70. 				struct reset_controller_dev *rcdev,
    71. 

  71. 				struct regmap *r)
    72. 

  72. {
    73. 

  73. 	return -ENOSYS;
    74. 

  74. }
    75. 

  75. 

  76. static inline void gdsc_unregister(struct gdsc_desc *desc) {};
    77. 

  77. #endif /* CONFIG_QCOM_GDSC */
    78. 

  78. #endif /* __QCOM_GDSC_H__ */
    79.