gcc-msm8996.c 90 KB

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  1. /*
  2. * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/bitops.h>
  15. #include <linux/err.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/clk-provider.h>
  21. #include <linux/regmap.h>
  22. #include <linux/reset-controller.h>
  23. #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  24. #include "common.h"
  25. #include "clk-regmap.h"
  26. #include "clk-alpha-pll.h"
  27. #include "clk-rcg.h"
  28. #include "clk-branch.h"
  29. #include "reset.h"
  30. #include "gdsc.h"
  31. #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  32. enum {
  33. P_XO,
  34. P_GPLL0,
  35. P_GPLL2,
  36. P_GPLL3,
  37. P_GPLL1,
  38. P_GPLL2_EARLY,
  39. P_GPLL0_EARLY_DIV,
  40. P_SLEEP_CLK,
  41. P_GPLL4,
  42. P_AUD_REF_CLK,
  43. P_GPLL1_EARLY_DIV
  44. };
  45. static const struct parent_map gcc_sleep_clk_map[] = {
  46. { P_SLEEP_CLK, 5 }
  47. };
  48. static const char * const gcc_sleep_clk[] = {
  49. "sleep_clk"
  50. };
  51. static const struct parent_map gcc_xo_gpll0_map[] = {
  52. { P_XO, 0 },
  53. { P_GPLL0, 1 }
  54. };
  55. static const char * const gcc_xo_gpll0[] = {
  56. "xo",
  57. "gpll0"
  58. };
  59. static const struct parent_map gcc_xo_sleep_clk_map[] = {
  60. { P_XO, 0 },
  61. { P_SLEEP_CLK, 5 }
  62. };
  63. static const char * const gcc_xo_sleep_clk[] = {
  64. "xo",
  65. "sleep_clk"
  66. };
  67. static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
  68. { P_XO, 0 },
  69. { P_GPLL0, 1 },
  70. { P_GPLL0_EARLY_DIV, 6 }
  71. };
  72. static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
  73. "xo",
  74. "gpll0",
  75. "gpll0_early_div"
  76. };
  77. static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  78. { P_XO, 0 },
  79. { P_GPLL0, 1 },
  80. { P_GPLL4, 5 }
  81. };
  82. static const char * const gcc_xo_gpll0_gpll4[] = {
  83. "xo",
  84. "gpll0",
  85. "gpll4"
  86. };
  87. static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
  88. { P_XO, 0 },
  89. { P_GPLL0, 1 },
  90. { P_AUD_REF_CLK, 2 }
  91. };
  92. static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
  93. "xo",
  94. "gpll0",
  95. "aud_ref_clk"
  96. };
  97. static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
  98. { P_XO, 0 },
  99. { P_GPLL0, 1 },
  100. { P_SLEEP_CLK, 5 },
  101. { P_GPLL0_EARLY_DIV, 6 }
  102. };
  103. static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
  104. "xo",
  105. "gpll0",
  106. "sleep_clk",
  107. "gpll0_early_div"
  108. };
  109. static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
  110. { P_XO, 0 },
  111. { P_GPLL0, 1 },
  112. { P_GPLL4, 5 },
  113. { P_GPLL0_EARLY_DIV, 6 }
  114. };
  115. static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
  116. "xo",
  117. "gpll0",
  118. "gpll4",
  119. "gpll0_early_div"
  120. };
  121. static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = {
  122. { P_XO, 0 },
  123. { P_GPLL0, 1 },
  124. { P_GPLL2, 2 },
  125. { P_GPLL3, 3 },
  126. { P_GPLL0_EARLY_DIV, 6 }
  127. };
  128. static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = {
  129. "xo",
  130. "gpll0",
  131. "gpll2",
  132. "gpll3",
  133. "gpll0_early_div"
  134. };
  135. static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
  136. { P_XO, 0 },
  137. { P_GPLL0, 1 },
  138. { P_GPLL1_EARLY_DIV, 3 },
  139. { P_GPLL1, 4 },
  140. { P_GPLL4, 5 },
  141. { P_GPLL0_EARLY_DIV, 6 }
  142. };
  143. static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
  144. "xo",
  145. "gpll0",
  146. "gpll1_early_div",
  147. "gpll1",
  148. "gpll4",
  149. "gpll0_early_div"
  150. };
  151. static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
  152. { P_XO, 0 },
  153. { P_GPLL0, 1 },
  154. { P_GPLL2, 2 },
  155. { P_GPLL3, 3 },
  156. { P_GPLL1, 4 },
  157. { P_GPLL2_EARLY, 5 },
  158. { P_GPLL0_EARLY_DIV, 6 }
  159. };
  160. static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
  161. "xo",
  162. "gpll0",
  163. "gpll2",
  164. "gpll3",
  165. "gpll1",
  166. "gpll2_early",
  167. "gpll0_early_div"
  168. };
  169. static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = {
  170. { P_XO, 0 },
  171. { P_GPLL0, 1 },
  172. { P_GPLL2, 2 },
  173. { P_GPLL3, 3 },
  174. { P_GPLL1, 4 },
  175. { P_GPLL4, 5 },
  176. { P_GPLL0_EARLY_DIV, 6 }
  177. };
  178. static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {
  179. "xo",
  180. "gpll0",
  181. "gpll2",
  182. "gpll3",
  183. "gpll1",
  184. "gpll4",
  185. "gpll0_early_div"
  186. };
  187. static struct clk_fixed_factor xo = {
  188. .mult = 1,
  189. .div = 1,
  190. .hw.init = &(struct clk_init_data){
  191. .name = "xo",
  192. .parent_names = (const char *[]){ "xo_board" },
  193. .num_parents = 1,
  194. .ops = &clk_fixed_factor_ops,
  195. },
  196. };
  197. static struct clk_alpha_pll gpll0_early = {
  198. .offset = 0x00000,
  199. .clkr = {
  200. .enable_reg = 0x52000,
  201. .enable_mask = BIT(0),
  202. .hw.init = &(struct clk_init_data){
  203. .name = "gpll0_early",
  204. .parent_names = (const char *[]){ "xo" },
  205. .num_parents = 1,
  206. .ops = &clk_alpha_pll_ops,
  207. },
  208. },
  209. };
  210. static struct clk_fixed_factor gpll0_early_div = {
  211. .mult = 1,
  212. .div = 2,
  213. .hw.init = &(struct clk_init_data){
  214. .name = "gpll0_early_div",
  215. .parent_names = (const char *[]){ "gpll0_early" },
  216. .num_parents = 1,
  217. .ops = &clk_fixed_factor_ops,
  218. },
  219. };
  220. static struct clk_alpha_pll_postdiv gpll0 = {
  221. .offset = 0x00000,
  222. .clkr.hw.init = &(struct clk_init_data){
  223. .name = "gpll0",
  224. .parent_names = (const char *[]){ "gpll0_early" },
  225. .num_parents = 1,
  226. .ops = &clk_alpha_pll_postdiv_ops,
  227. },
  228. };
  229. static struct clk_alpha_pll gpll4_early = {
  230. .offset = 0x77000,
  231. .clkr = {
  232. .enable_reg = 0x52000,
  233. .enable_mask = BIT(4),
  234. .hw.init = &(struct clk_init_data){
  235. .name = "gpll4_early",
  236. .parent_names = (const char *[]){ "xo" },
  237. .num_parents = 1,
  238. .ops = &clk_alpha_pll_ops,
  239. },
  240. },
  241. };
  242. static struct clk_alpha_pll_postdiv gpll4 = {
  243. .offset = 0x77000,
  244. .clkr.hw.init = &(struct clk_init_data){
  245. .name = "gpll4",
  246. .parent_names = (const char *[]){ "gpll4_early" },
  247. .num_parents = 1,
  248. .ops = &clk_alpha_pll_postdiv_ops,
  249. },
  250. };
  251. static const struct freq_tbl ftbl_system_noc_clk_src[] = {
  252. F(19200000, P_XO, 1, 0, 0),
  253. F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
  254. F(100000000, P_GPLL0, 6, 0, 0),
  255. F(150000000, P_GPLL0, 4, 0, 0),
  256. F(200000000, P_GPLL0, 3, 0, 0),
  257. F(240000000, P_GPLL0, 2.5, 0, 0),
  258. { }
  259. };
  260. static struct clk_rcg2 system_noc_clk_src = {
  261. .cmd_rcgr = 0x0401c,
  262. .hid_width = 5,
  263. .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
  264. .freq_tbl = ftbl_system_noc_clk_src,
  265. .clkr.hw.init = &(struct clk_init_data){
  266. .name = "system_noc_clk_src",
  267. .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
  268. .num_parents = 7,
  269. .ops = &clk_rcg2_ops,
  270. },
  271. };
  272. static const struct freq_tbl ftbl_config_noc_clk_src[] = {
  273. F(19200000, P_XO, 1, 0, 0),
  274. F(37500000, P_GPLL0, 16, 0, 0),
  275. F(75000000, P_GPLL0, 8, 0, 0),
  276. { }
  277. };
  278. static struct clk_rcg2 config_noc_clk_src = {
  279. .cmd_rcgr = 0x0500c,
  280. .hid_width = 5,
  281. .parent_map = gcc_xo_gpll0_map,
  282. .freq_tbl = ftbl_config_noc_clk_src,
  283. .clkr.hw.init = &(struct clk_init_data){
  284. .name = "config_noc_clk_src",
  285. .parent_names = gcc_xo_gpll0,
  286. .num_parents = 2,
  287. .ops = &clk_rcg2_ops,
  288. },
  289. };
  290. static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
  291. F(19200000, P_XO, 1, 0, 0),
  292. F(37500000, P_GPLL0, 16, 0, 0),
  293. F(50000000, P_GPLL0, 12, 0, 0),
  294. F(75000000, P_GPLL0, 8, 0, 0),
  295. F(100000000, P_GPLL0, 6, 0, 0),
  296. { }
  297. };
  298. static struct clk_rcg2 periph_noc_clk_src = {
  299. .cmd_rcgr = 0x06014,
  300. .hid_width = 5,
  301. .parent_map = gcc_xo_gpll0_map,
  302. .freq_tbl = ftbl_periph_noc_clk_src,
  303. .clkr.hw.init = &(struct clk_init_data){
  304. .name = "periph_noc_clk_src",
  305. .parent_names = gcc_xo_gpll0,
  306. .num_parents = 2,
  307. .ops = &clk_rcg2_ops,
  308. },
  309. };
  310. static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
  311. F(19200000, P_XO, 1, 0, 0),
  312. F(120000000, P_GPLL0, 5, 0, 0),
  313. F(150000000, P_GPLL0, 4, 0, 0),
  314. { }
  315. };
  316. static struct clk_rcg2 usb30_master_clk_src = {
  317. .cmd_rcgr = 0x0f014,
  318. .mnd_width = 8,
  319. .hid_width = 5,
  320. .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
  321. .freq_tbl = ftbl_usb30_master_clk_src,
  322. .clkr.hw.init = &(struct clk_init_data){
  323. .name = "usb30_master_clk_src",
  324. .parent_names = gcc_xo_gpll0_gpll0_early_div,
  325. .num_parents = 3,
  326. .ops = &clk_rcg2_ops,
  327. },
  328. };
  329. static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
  330. F(19200000, P_XO, 1, 0, 0),
  331. { }
  332. };
  333. static struct clk_rcg2 usb30_mock_utmi_clk_src = {
  334. .cmd_rcgr = 0x0f028,
  335. .hid_width = 5,
  336. .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
  337. .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
  338. .clkr.hw.init = &(struct clk_init_data){
  339. .name = "usb30_mock_utmi_clk_src",
  340. .parent_names = gcc_xo_gpll0_gpll0_early_div,
  341. .num_parents = 3,
  342. .ops = &clk_rcg2_ops,
  343. },
  344. };
  345. static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
  346. F(1200000, P_XO, 16, 0, 0),
  347. { }
  348. };
  349. static struct clk_rcg2 usb3_phy_aux_clk_src = {
  350. .cmd_rcgr = 0x5000c,
  351. .hid_width = 5,
  352. .parent_map = gcc_xo_sleep_clk_map,
  353. .freq_tbl = ftbl_usb3_phy_aux_clk_src,
  354. .clkr.hw.init = &(struct clk_init_data){
  355. .name = "usb3_phy_aux_clk_src",
  356. .parent_names = gcc_xo_sleep_clk,
  357. .num_parents = 2,
  358. .ops = &clk_rcg2_ops,
  359. },
  360. };
  361. static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
  362. F(120000000, P_GPLL0, 5, 0, 0),
  363. { }
  364. };
  365. static struct clk_rcg2 usb20_master_clk_src = {
  366. .cmd_rcgr = 0x12010,
  367. .mnd_width = 8,
  368. .hid_width = 5,
  369. .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
  370. .freq_tbl = ftbl_usb20_master_clk_src,
  371. .clkr.hw.init = &(struct clk_init_data){
  372. .name = "usb20_master_clk_src",
  373. .parent_names = gcc_xo_gpll0_gpll0_early_div,
  374. .num_parents = 3,
  375. .ops = &clk_rcg2_ops,
  376. },
  377. };
  378. static struct clk_rcg2 usb20_mock_utmi_clk_src = {
  379. .cmd_rcgr = 0x12024,
  380. .hid_width = 5,
  381. .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
  382. .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
  383. .clkr.hw.init = &(struct clk_init_data){
  384. .name = "usb20_mock_utmi_clk_src",
  385. .parent_names = gcc_xo_gpll0_gpll0_early_div,
  386. .num_parents = 3,
  387. .ops = &clk_rcg2_ops,
  388. },
  389. };
  390. static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
  391. F(144000, P_XO, 16, 3, 25),
  392. F(400000, P_XO, 12, 1, 4),
  393. F(20000000, P_GPLL0, 15, 1, 2),
  394. F(25000000, P_GPLL0, 12, 1, 2),
  395. F(50000000, P_GPLL0, 12, 0, 0),
  396. F(96000000, P_GPLL4, 4, 0, 0),
  397. F(192000000, P_GPLL4, 2, 0, 0),
  398. F(384000000, P_GPLL4, 1, 0, 0),
  399. { }
  400. };
  401. static struct clk_rcg2 sdcc1_apps_clk_src = {
  402. .cmd_rcgr = 0x13010,
  403. .mnd_width = 8,
  404. .hid_width = 5,
  405. .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
  406. .freq_tbl = ftbl_sdcc1_apps_clk_src,
  407. .clkr.hw.init = &(struct clk_init_data){
  408. .name = "sdcc1_apps_clk_src",
  409. .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
  410. .num_parents = 4,
  411. .ops = &clk_rcg2_ops,
  412. },
  413. };
  414. static struct clk_rcg2 sdcc1_ice_core_clk_src = {
  415. .cmd_rcgr = 0x13024,
  416. .hid_width = 5,
  417. .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
  418. .clkr.hw.init = &(struct clk_init_data){
  419. .name = "sdcc1_ice_core_clk_src",
  420. .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
  421. .num_parents = 4,
  422. .ops = &clk_rcg2_ops,
  423. },
  424. };
  425. static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
  426. F(144000, P_XO, 16, 3, 25),
  427. F(400000, P_XO, 12, 1, 4),
  428. F(20000000, P_GPLL0, 15, 1, 2),
  429. F(25000000, P_GPLL0, 12, 1, 2),
  430. F(50000000, P_GPLL0, 12, 0, 0),
  431. F(100000000, P_GPLL0, 6, 0, 0),
  432. F(200000000, P_GPLL0, 3, 0, 0),
  433. { }
  434. };
  435. static struct clk_rcg2 sdcc2_apps_clk_src = {
  436. .cmd_rcgr = 0x14010,
  437. .mnd_width = 8,
  438. .hid_width = 5,
  439. .parent_map = gcc_xo_gpll0_gpll4_map,
  440. .freq_tbl = ftbl_sdcc2_apps_clk_src,
  441. .clkr.hw.init = &(struct clk_init_data){
  442. .name = "sdcc2_apps_clk_src",
  443. .parent_names = gcc_xo_gpll0_gpll4,
  444. .num_parents = 3,
  445. .ops = &clk_rcg2_ops,
  446. },
  447. };
  448. static struct clk_rcg2 sdcc3_apps_clk_src = {
  449. .cmd_rcgr = 0x15010,
  450. .mnd_width = 8,
  451. .hid_width = 5,
  452. .parent_map = gcc_xo_gpll0_gpll4_map,
  453. .freq_tbl = ftbl_sdcc2_apps_clk_src,
  454. .clkr.hw.init = &(struct clk_init_data){
  455. .name = "sdcc3_apps_clk_src",
  456. .parent_names = gcc_xo_gpll0_gpll4,
  457. .num_parents = 3,
  458. .ops = &clk_rcg2_ops,
  459. },
  460. };
  461. static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
  462. F(144000, P_XO, 16, 3, 25),
  463. F(400000, P_XO, 12, 1, 4),
  464. F(20000000, P_GPLL0, 15, 1, 2),
  465. F(25000000, P_GPLL0, 12, 1, 2),
  466. F(50000000, P_GPLL0, 12, 0, 0),
  467. F(100000000, P_GPLL0, 6, 0, 0),
  468. { }
  469. };
  470. static struct clk_rcg2 sdcc4_apps_clk_src = {
  471. .cmd_rcgr = 0x16010,
  472. .mnd_width = 8,
  473. .hid_width = 5,
  474. .parent_map = gcc_xo_gpll0_map,
  475. .freq_tbl = ftbl_sdcc4_apps_clk_src,
  476. .clkr.hw.init = &(struct clk_init_data){
  477. .name = "sdcc4_apps_clk_src",
  478. .parent_names = gcc_xo_gpll0,
  479. .num_parents = 2,
  480. .ops = &clk_rcg2_ops,
  481. },
  482. };
  483. static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
  484. F(960000, P_XO, 10, 1, 2),
  485. F(4800000, P_XO, 4, 0, 0),
  486. F(9600000, P_XO, 2, 0, 0),
  487. F(15000000, P_GPLL0, 10, 1, 4),
  488. F(19200000, P_XO, 1, 0, 0),
  489. F(25000000, P_GPLL0, 12, 1, 2),
  490. F(50000000, P_GPLL0, 12, 0, 0),
  491. { }
  492. };
  493. static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
  494. .cmd_rcgr = 0x1900c,
  495. .mnd_width = 8,
  496. .hid_width = 5,
  497. .parent_map = gcc_xo_gpll0_map,
  498. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  499. .clkr.hw.init = &(struct clk_init_data){
  500. .name = "blsp1_qup1_spi_apps_clk_src",
  501. .parent_names = gcc_xo_gpll0,
  502. .num_parents = 2,
  503. .ops = &clk_rcg2_ops,
  504. },
  505. };
  506. static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
  507. F(19200000, P_XO, 1, 0, 0),
  508. F(50000000, P_GPLL0, 12, 0, 0),
  509. { }
  510. };
  511. static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
  512. .cmd_rcgr = 0x19020,
  513. .hid_width = 5,
  514. .parent_map = gcc_xo_gpll0_map,
  515. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  516. .clkr.hw.init = &(struct clk_init_data){
  517. .name = "blsp1_qup1_i2c_apps_clk_src",
  518. .parent_names = gcc_xo_gpll0,
  519. .num_parents = 2,
  520. .ops = &clk_rcg2_ops,
  521. },
  522. };
  523. static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
  524. F(3686400, P_GPLL0, 1, 96, 15625),
  525. F(7372800, P_GPLL0, 1, 192, 15625),
  526. F(14745600, P_GPLL0, 1, 384, 15625),
  527. F(16000000, P_GPLL0, 5, 2, 15),
  528. F(19200000, P_XO, 1, 0, 0),
  529. F(24000000, P_GPLL0, 5, 1, 5),
  530. F(32000000, P_GPLL0, 1, 4, 75),
  531. F(40000000, P_GPLL0, 15, 0, 0),
  532. F(46400000, P_GPLL0, 1, 29, 375),
  533. F(48000000, P_GPLL0, 12.5, 0, 0),
  534. F(51200000, P_GPLL0, 1, 32, 375),
  535. F(56000000, P_GPLL0, 1, 7, 75),
  536. F(58982400, P_GPLL0, 1, 1536, 15625),
  537. F(60000000, P_GPLL0, 10, 0, 0),
  538. F(63157895, P_GPLL0, 9.5, 0, 0),
  539. { }
  540. };
  541. static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
  542. .cmd_rcgr = 0x1a00c,
  543. .mnd_width = 16,
  544. .hid_width = 5,
  545. .parent_map = gcc_xo_gpll0_map,
  546. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  547. .clkr.hw.init = &(struct clk_init_data){
  548. .name = "blsp1_uart1_apps_clk_src",
  549. .parent_names = gcc_xo_gpll0,
  550. .num_parents = 2,
  551. .ops = &clk_rcg2_ops,
  552. },
  553. };
  554. static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
  555. .cmd_rcgr = 0x1b00c,
  556. .mnd_width = 8,
  557. .hid_width = 5,
  558. .parent_map = gcc_xo_gpll0_map,
  559. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  560. .clkr.hw.init = &(struct clk_init_data){
  561. .name = "blsp1_qup2_spi_apps_clk_src",
  562. .parent_names = gcc_xo_gpll0,
  563. .num_parents = 2,
  564. .ops = &clk_rcg2_ops,
  565. },
  566. };
  567. static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
  568. .cmd_rcgr = 0x1b020,
  569. .hid_width = 5,
  570. .parent_map = gcc_xo_gpll0_map,
  571. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  572. .clkr.hw.init = &(struct clk_init_data){
  573. .name = "blsp1_qup2_i2c_apps_clk_src",
  574. .parent_names = gcc_xo_gpll0,
  575. .num_parents = 2,
  576. .ops = &clk_rcg2_ops,
  577. },
  578. };
  579. static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
  580. .cmd_rcgr = 0x1c00c,
  581. .mnd_width = 16,
  582. .hid_width = 5,
  583. .parent_map = gcc_xo_gpll0_map,
  584. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  585. .clkr.hw.init = &(struct clk_init_data){
  586. .name = "blsp1_uart2_apps_clk_src",
  587. .parent_names = gcc_xo_gpll0,
  588. .num_parents = 2,
  589. .ops = &clk_rcg2_ops,
  590. },
  591. };
  592. static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
  593. .cmd_rcgr = 0x1d00c,
  594. .mnd_width = 8,
  595. .hid_width = 5,
  596. .parent_map = gcc_xo_gpll0_map,
  597. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  598. .clkr.hw.init = &(struct clk_init_data){
  599. .name = "blsp1_qup3_spi_apps_clk_src",
  600. .parent_names = gcc_xo_gpll0,
  601. .num_parents = 2,
  602. .ops = &clk_rcg2_ops,
  603. },
  604. };
  605. static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
  606. .cmd_rcgr = 0x1d020,
  607. .hid_width = 5,
  608. .parent_map = gcc_xo_gpll0_map,
  609. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  610. .clkr.hw.init = &(struct clk_init_data){
  611. .name = "blsp1_qup3_i2c_apps_clk_src",
  612. .parent_names = gcc_xo_gpll0,
  613. .num_parents = 2,
  614. .ops = &clk_rcg2_ops,
  615. },
  616. };
  617. static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
  618. .cmd_rcgr = 0x1e00c,
  619. .mnd_width = 16,
  620. .hid_width = 5,
  621. .parent_map = gcc_xo_gpll0_map,
  622. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  623. .clkr.hw.init = &(struct clk_init_data){
  624. .name = "blsp1_uart3_apps_clk_src",
  625. .parent_names = gcc_xo_gpll0,
  626. .num_parents = 2,
  627. .ops = &clk_rcg2_ops,
  628. },
  629. };
  630. static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
  631. .cmd_rcgr = 0x1f00c,
  632. .mnd_width = 8,
  633. .hid_width = 5,
  634. .parent_map = gcc_xo_gpll0_map,
  635. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  636. .clkr.hw.init = &(struct clk_init_data){
  637. .name = "blsp1_qup4_spi_apps_clk_src",
  638. .parent_names = gcc_xo_gpll0,
  639. .num_parents = 2,
  640. .ops = &clk_rcg2_ops,
  641. },
  642. };
  643. static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
  644. .cmd_rcgr = 0x1f020,
  645. .hid_width = 5,
  646. .parent_map = gcc_xo_gpll0_map,
  647. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  648. .clkr.hw.init = &(struct clk_init_data){
  649. .name = "blsp1_qup4_i2c_apps_clk_src",
  650. .parent_names = gcc_xo_gpll0,
  651. .num_parents = 2,
  652. .ops = &clk_rcg2_ops,
  653. },
  654. };
  655. static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
  656. .cmd_rcgr = 0x2000c,
  657. .mnd_width = 16,
  658. .hid_width = 5,
  659. .parent_map = gcc_xo_gpll0_map,
  660. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  661. .clkr.hw.init = &(struct clk_init_data){
  662. .name = "blsp1_uart4_apps_clk_src",
  663. .parent_names = gcc_xo_gpll0,
  664. .num_parents = 2,
  665. .ops = &clk_rcg2_ops,
  666. },
  667. };
  668. static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
  669. .cmd_rcgr = 0x2100c,
  670. .mnd_width = 8,
  671. .hid_width = 5,
  672. .parent_map = gcc_xo_gpll0_map,
  673. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  674. .clkr.hw.init = &(struct clk_init_data){
  675. .name = "blsp1_qup5_spi_apps_clk_src",
  676. .parent_names = gcc_xo_gpll0,
  677. .num_parents = 2,
  678. .ops = &clk_rcg2_ops,
  679. },
  680. };
  681. static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
  682. .cmd_rcgr = 0x21020,
  683. .hid_width = 5,
  684. .parent_map = gcc_xo_gpll0_map,
  685. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  686. .clkr.hw.init = &(struct clk_init_data){
  687. .name = "blsp1_qup5_i2c_apps_clk_src",
  688. .parent_names = gcc_xo_gpll0,
  689. .num_parents = 2,
  690. .ops = &clk_rcg2_ops,
  691. },
  692. };
  693. static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
  694. .cmd_rcgr = 0x2200c,
  695. .mnd_width = 16,
  696. .hid_width = 5,
  697. .parent_map = gcc_xo_gpll0_map,
  698. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  699. .clkr.hw.init = &(struct clk_init_data){
  700. .name = "blsp1_uart5_apps_clk_src",
  701. .parent_names = gcc_xo_gpll0,
  702. .num_parents = 2,
  703. .ops = &clk_rcg2_ops,
  704. },
  705. };
  706. static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
  707. .cmd_rcgr = 0x2300c,
  708. .mnd_width = 8,
  709. .hid_width = 5,
  710. .parent_map = gcc_xo_gpll0_map,
  711. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  712. .clkr.hw.init = &(struct clk_init_data){
  713. .name = "blsp1_qup6_spi_apps_clk_src",
  714. .parent_names = gcc_xo_gpll0,
  715. .num_parents = 2,
  716. .ops = &clk_rcg2_ops,
  717. },
  718. };
  719. static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
  720. .cmd_rcgr = 0x23020,
  721. .hid_width = 5,
  722. .parent_map = gcc_xo_gpll0_map,
  723. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  724. .clkr.hw.init = &(struct clk_init_data){
  725. .name = "blsp1_qup6_i2c_apps_clk_src",
  726. .parent_names = gcc_xo_gpll0,
  727. .num_parents = 2,
  728. .ops = &clk_rcg2_ops,
  729. },
  730. };
  731. static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
  732. .cmd_rcgr = 0x2400c,
  733. .mnd_width = 16,
  734. .hid_width = 5,
  735. .parent_map = gcc_xo_gpll0_map,
  736. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  737. .clkr.hw.init = &(struct clk_init_data){
  738. .name = "blsp1_uart6_apps_clk_src",
  739. .parent_names = gcc_xo_gpll0,
  740. .num_parents = 2,
  741. .ops = &clk_rcg2_ops,
  742. },
  743. };
  744. static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
  745. .cmd_rcgr = 0x2600c,
  746. .mnd_width = 8,
  747. .hid_width = 5,
  748. .parent_map = gcc_xo_gpll0_map,
  749. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  750. .clkr.hw.init = &(struct clk_init_data){
  751. .name = "blsp2_qup1_spi_apps_clk_src",
  752. .parent_names = gcc_xo_gpll0,
  753. .num_parents = 2,
  754. .ops = &clk_rcg2_ops,
  755. },
  756. };
  757. static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
  758. .cmd_rcgr = 0x26020,
  759. .hid_width = 5,
  760. .parent_map = gcc_xo_gpll0_map,
  761. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  762. .clkr.hw.init = &(struct clk_init_data){
  763. .name = "blsp2_qup1_i2c_apps_clk_src",
  764. .parent_names = gcc_xo_gpll0,
  765. .num_parents = 2,
  766. .ops = &clk_rcg2_ops,
  767. },
  768. };
  769. static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
  770. .cmd_rcgr = 0x2700c,
  771. .mnd_width = 16,
  772. .hid_width = 5,
  773. .parent_map = gcc_xo_gpll0_map,
  774. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  775. .clkr.hw.init = &(struct clk_init_data){
  776. .name = "blsp2_uart1_apps_clk_src",
  777. .parent_names = gcc_xo_gpll0,
  778. .num_parents = 2,
  779. .ops = &clk_rcg2_ops,
  780. },
  781. };
  782. static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
  783. .cmd_rcgr = 0x2800c,
  784. .mnd_width = 8,
  785. .hid_width = 5,
  786. .parent_map = gcc_xo_gpll0_map,
  787. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  788. .clkr.hw.init = &(struct clk_init_data){
  789. .name = "blsp2_qup2_spi_apps_clk_src",
  790. .parent_names = gcc_xo_gpll0,
  791. .num_parents = 2,
  792. .ops = &clk_rcg2_ops,
  793. },
  794. };
  795. static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
  796. .cmd_rcgr = 0x28020,
  797. .hid_width = 5,
  798. .parent_map = gcc_xo_gpll0_map,
  799. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  800. .clkr.hw.init = &(struct clk_init_data){
  801. .name = "blsp2_qup2_i2c_apps_clk_src",
  802. .parent_names = gcc_xo_gpll0,
  803. .num_parents = 2,
  804. .ops = &clk_rcg2_ops,
  805. },
  806. };
  807. static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
  808. .cmd_rcgr = 0x2900c,
  809. .mnd_width = 16,
  810. .hid_width = 5,
  811. .parent_map = gcc_xo_gpll0_map,
  812. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  813. .clkr.hw.init = &(struct clk_init_data){
  814. .name = "blsp2_uart2_apps_clk_src",
  815. .parent_names = gcc_xo_gpll0,
  816. .num_parents = 2,
  817. .ops = &clk_rcg2_ops,
  818. },
  819. };
  820. static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
  821. .cmd_rcgr = 0x2a00c,
  822. .mnd_width = 8,
  823. .hid_width = 5,
  824. .parent_map = gcc_xo_gpll0_map,
  825. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  826. .clkr.hw.init = &(struct clk_init_data){
  827. .name = "blsp2_qup3_spi_apps_clk_src",
  828. .parent_names = gcc_xo_gpll0,
  829. .num_parents = 2,
  830. .ops = &clk_rcg2_ops,
  831. },
  832. };
  833. static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
  834. .cmd_rcgr = 0x2a020,
  835. .hid_width = 5,
  836. .parent_map = gcc_xo_gpll0_map,
  837. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  838. .clkr.hw.init = &(struct clk_init_data){
  839. .name = "blsp2_qup3_i2c_apps_clk_src",
  840. .parent_names = gcc_xo_gpll0,
  841. .num_parents = 2,
  842. .ops = &clk_rcg2_ops,
  843. },
  844. };
  845. static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
  846. .cmd_rcgr = 0x2b00c,
  847. .mnd_width = 16,
  848. .hid_width = 5,
  849. .parent_map = gcc_xo_gpll0_map,
  850. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  851. .clkr.hw.init = &(struct clk_init_data){
  852. .name = "blsp2_uart3_apps_clk_src",
  853. .parent_names = gcc_xo_gpll0,
  854. .num_parents = 2,
  855. .ops = &clk_rcg2_ops,
  856. },
  857. };
  858. static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
  859. .cmd_rcgr = 0x2c00c,
  860. .mnd_width = 8,
  861. .hid_width = 5,
  862. .parent_map = gcc_xo_gpll0_map,
  863. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  864. .clkr.hw.init = &(struct clk_init_data){
  865. .name = "blsp2_qup4_spi_apps_clk_src",
  866. .parent_names = gcc_xo_gpll0,
  867. .num_parents = 2,
  868. .ops = &clk_rcg2_ops,
  869. },
  870. };
  871. static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
  872. .cmd_rcgr = 0x2c020,
  873. .hid_width = 5,
  874. .parent_map = gcc_xo_gpll0_map,
  875. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  876. .clkr.hw.init = &(struct clk_init_data){
  877. .name = "blsp2_qup4_i2c_apps_clk_src",
  878. .parent_names = gcc_xo_gpll0,
  879. .num_parents = 2,
  880. .ops = &clk_rcg2_ops,
  881. },
  882. };
  883. static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
  884. .cmd_rcgr = 0x2d00c,
  885. .mnd_width = 16,
  886. .hid_width = 5,
  887. .parent_map = gcc_xo_gpll0_map,
  888. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  889. .clkr.hw.init = &(struct clk_init_data){
  890. .name = "blsp2_uart4_apps_clk_src",
  891. .parent_names = gcc_xo_gpll0,
  892. .num_parents = 2,
  893. .ops = &clk_rcg2_ops,
  894. },
  895. };
  896. static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
  897. .cmd_rcgr = 0x2e00c,
  898. .mnd_width = 8,
  899. .hid_width = 5,
  900. .parent_map = gcc_xo_gpll0_map,
  901. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  902. .clkr.hw.init = &(struct clk_init_data){
  903. .name = "blsp2_qup5_spi_apps_clk_src",
  904. .parent_names = gcc_xo_gpll0,
  905. .num_parents = 2,
  906. .ops = &clk_rcg2_ops,
  907. },
  908. };
  909. static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
  910. .cmd_rcgr = 0x2e020,
  911. .hid_width = 5,
  912. .parent_map = gcc_xo_gpll0_map,
  913. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  914. .clkr.hw.init = &(struct clk_init_data){
  915. .name = "blsp2_qup5_i2c_apps_clk_src",
  916. .parent_names = gcc_xo_gpll0,
  917. .num_parents = 2,
  918. .ops = &clk_rcg2_ops,
  919. },
  920. };
  921. static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
  922. .cmd_rcgr = 0x2f00c,
  923. .mnd_width = 16,
  924. .hid_width = 5,
  925. .parent_map = gcc_xo_gpll0_map,
  926. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  927. .clkr.hw.init = &(struct clk_init_data){
  928. .name = "blsp2_uart5_apps_clk_src",
  929. .parent_names = gcc_xo_gpll0,
  930. .num_parents = 2,
  931. .ops = &clk_rcg2_ops,
  932. },
  933. };
  934. static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
  935. .cmd_rcgr = 0x3000c,
  936. .mnd_width = 8,
  937. .hid_width = 5,
  938. .parent_map = gcc_xo_gpll0_map,
  939. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  940. .clkr.hw.init = &(struct clk_init_data){
  941. .name = "blsp2_qup6_spi_apps_clk_src",
  942. .parent_names = gcc_xo_gpll0,
  943. .num_parents = 2,
  944. .ops = &clk_rcg2_ops,
  945. },
  946. };
  947. static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
  948. .cmd_rcgr = 0x30020,
  949. .hid_width = 5,
  950. .parent_map = gcc_xo_gpll0_map,
  951. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  952. .clkr.hw.init = &(struct clk_init_data){
  953. .name = "blsp2_qup6_i2c_apps_clk_src",
  954. .parent_names = gcc_xo_gpll0,
  955. .num_parents = 2,
  956. .ops = &clk_rcg2_ops,
  957. },
  958. };
  959. static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
  960. .cmd_rcgr = 0x3100c,
  961. .mnd_width = 16,
  962. .hid_width = 5,
  963. .parent_map = gcc_xo_gpll0_map,
  964. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  965. .clkr.hw.init = &(struct clk_init_data){
  966. .name = "blsp2_uart6_apps_clk_src",
  967. .parent_names = gcc_xo_gpll0,
  968. .num_parents = 2,
  969. .ops = &clk_rcg2_ops,
  970. },
  971. };
  972. static const struct freq_tbl ftbl_pdm2_clk_src[] = {
  973. F(60000000, P_GPLL0, 10, 0, 0),
  974. { }
  975. };
  976. static struct clk_rcg2 pdm2_clk_src = {
  977. .cmd_rcgr = 0x33010,
  978. .hid_width = 5,
  979. .parent_map = gcc_xo_gpll0_map,
  980. .freq_tbl = ftbl_pdm2_clk_src,
  981. .clkr.hw.init = &(struct clk_init_data){
  982. .name = "pdm2_clk_src",
  983. .parent_names = gcc_xo_gpll0,
  984. .num_parents = 2,
  985. .ops = &clk_rcg2_ops,
  986. },
  987. };
  988. static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
  989. F(105495, P_XO, 1, 1, 182),
  990. { }
  991. };
  992. static struct clk_rcg2 tsif_ref_clk_src = {
  993. .cmd_rcgr = 0x36010,
  994. .mnd_width = 8,
  995. .hid_width = 5,
  996. .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
  997. .freq_tbl = ftbl_tsif_ref_clk_src,
  998. .clkr.hw.init = &(struct clk_init_data){
  999. .name = "tsif_ref_clk_src",
  1000. .parent_names = gcc_xo_gpll0_aud_ref_clk,
  1001. .num_parents = 3,
  1002. .ops = &clk_rcg2_ops,
  1003. },
  1004. };
  1005. static struct clk_rcg2 gcc_sleep_clk_src = {
  1006. .cmd_rcgr = 0x43014,
  1007. .hid_width = 5,
  1008. .parent_map = gcc_sleep_clk_map,
  1009. .clkr.hw.init = &(struct clk_init_data){
  1010. .name = "gcc_sleep_clk_src",
  1011. .parent_names = gcc_sleep_clk,
  1012. .num_parents = 1,
  1013. .ops = &clk_rcg2_ops,
  1014. },
  1015. };
  1016. static struct clk_rcg2 hmss_rbcpr_clk_src = {
  1017. .cmd_rcgr = 0x48040,
  1018. .hid_width = 5,
  1019. .parent_map = gcc_xo_gpll0_map,
  1020. .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
  1021. .clkr.hw.init = &(struct clk_init_data){
  1022. .name = "hmss_rbcpr_clk_src",
  1023. .parent_names = gcc_xo_gpll0,
  1024. .num_parents = 2,
  1025. .ops = &clk_rcg2_ops,
  1026. },
  1027. };
  1028. static struct clk_rcg2 hmss_gpll0_clk_src = {
  1029. .cmd_rcgr = 0x48058,
  1030. .hid_width = 5,
  1031. .parent_map = gcc_xo_gpll0_map,
  1032. .clkr.hw.init = &(struct clk_init_data){
  1033. .name = "hmss_gpll0_clk_src",
  1034. .parent_names = gcc_xo_gpll0,
  1035. .num_parents = 2,
  1036. .ops = &clk_rcg2_ops,
  1037. },
  1038. };
  1039. static const struct freq_tbl ftbl_gp1_clk_src[] = {
  1040. F(19200000, P_XO, 1, 0, 0),
  1041. F(100000000, P_GPLL0, 6, 0, 0),
  1042. F(200000000, P_GPLL0, 3, 0, 0),
  1043. { }
  1044. };
  1045. static struct clk_rcg2 gp1_clk_src = {
  1046. .cmd_rcgr = 0x64004,
  1047. .mnd_width = 8,
  1048. .hid_width = 5,
  1049. .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
  1050. .freq_tbl = ftbl_gp1_clk_src,
  1051. .clkr.hw.init = &(struct clk_init_data){
  1052. .name = "gp1_clk_src",
  1053. .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
  1054. .num_parents = 4,
  1055. .ops = &clk_rcg2_ops,
  1056. },
  1057. };
  1058. static struct clk_rcg2 gp2_clk_src = {
  1059. .cmd_rcgr = 0x65004,
  1060. .mnd_width = 8,
  1061. .hid_width = 5,
  1062. .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
  1063. .freq_tbl = ftbl_gp1_clk_src,
  1064. .clkr.hw.init = &(struct clk_init_data){
  1065. .name = "gp2_clk_src",
  1066. .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
  1067. .num_parents = 4,
  1068. .ops = &clk_rcg2_ops,
  1069. },
  1070. };
  1071. static struct clk_rcg2 gp3_clk_src = {
  1072. .cmd_rcgr = 0x66004,
  1073. .mnd_width = 8,
  1074. .hid_width = 5,
  1075. .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
  1076. .freq_tbl = ftbl_gp1_clk_src,
  1077. .clkr.hw.init = &(struct clk_init_data){
  1078. .name = "gp3_clk_src",
  1079. .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
  1080. .num_parents = 4,
  1081. .ops = &clk_rcg2_ops,
  1082. },
  1083. };
  1084. static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
  1085. F(1010526, P_XO, 1, 1, 19),
  1086. { }
  1087. };
  1088. static struct clk_rcg2 pcie_aux_clk_src = {
  1089. .cmd_rcgr = 0x6c000,
  1090. .mnd_width = 16,
  1091. .hid_width = 5,
  1092. .parent_map = gcc_xo_sleep_clk_map,
  1093. .freq_tbl = ftbl_pcie_aux_clk_src,
  1094. .clkr.hw.init = &(struct clk_init_data){
  1095. .name = "pcie_aux_clk_src",
  1096. .parent_names = gcc_xo_sleep_clk,
  1097. .num_parents = 2,
  1098. .ops = &clk_rcg2_ops,
  1099. },
  1100. };
  1101. static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
  1102. F(100000000, P_GPLL0, 6, 0, 0),
  1103. F(200000000, P_GPLL0, 3, 0, 0),
  1104. F(240000000, P_GPLL0, 2.5, 0, 0),
  1105. { }
  1106. };
  1107. static struct clk_rcg2 ufs_axi_clk_src = {
  1108. .cmd_rcgr = 0x75024,
  1109. .mnd_width = 8,
  1110. .hid_width = 5,
  1111. .parent_map = gcc_xo_gpll0_map,
  1112. .freq_tbl = ftbl_ufs_axi_clk_src,
  1113. .clkr.hw.init = &(struct clk_init_data){
  1114. .name = "ufs_axi_clk_src",
  1115. .parent_names = gcc_xo_gpll0,
  1116. .num_parents = 2,
  1117. .ops = &clk_rcg2_ops,
  1118. },
  1119. };
  1120. static struct clk_rcg2 ufs_ice_core_clk_src = {
  1121. .cmd_rcgr = 0x76014,
  1122. .hid_width = 5,
  1123. .parent_map = gcc_xo_gpll0_map,
  1124. .clkr.hw.init = &(struct clk_init_data){
  1125. .name = "ufs_ice_core_clk_src",
  1126. .parent_names = gcc_xo_gpll0,
  1127. .num_parents = 2,
  1128. .ops = &clk_rcg2_ops,
  1129. },
  1130. };
  1131. static struct clk_rcg2 qspi_ser_clk_src = {
  1132. .cmd_rcgr = 0x8b00c,
  1133. .hid_width = 5,
  1134. .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
  1135. .clkr.hw.init = &(struct clk_init_data){
  1136. .name = "qspi_ser_clk_src",
  1137. .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
  1138. .num_parents = 6,
  1139. .ops = &clk_rcg2_ops,
  1140. },
  1141. };
  1142. static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
  1143. .halt_reg = 0x0f03c,
  1144. .clkr = {
  1145. .enable_reg = 0x0f03c,
  1146. .enable_mask = BIT(0),
  1147. .hw.init = &(struct clk_init_data){
  1148. .name = "gcc_sys_noc_usb3_axi_clk",
  1149. .parent_names = (const char *[]){ "usb30_master_clk_src" },
  1150. .num_parents = 1,
  1151. .flags = CLK_SET_RATE_PARENT,
  1152. .ops = &clk_branch2_ops,
  1153. },
  1154. },
  1155. };
  1156. static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
  1157. .halt_reg = 0x75038,
  1158. .clkr = {
  1159. .enable_reg = 0x75038,
  1160. .enable_mask = BIT(0),
  1161. .hw.init = &(struct clk_init_data){
  1162. .name = "gcc_sys_noc_ufs_axi_clk",
  1163. .parent_names = (const char *[]){ "ufs_axi_clk_src" },
  1164. .num_parents = 1,
  1165. .flags = CLK_SET_RATE_PARENT,
  1166. .ops = &clk_branch2_ops,
  1167. },
  1168. },
  1169. };
  1170. static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
  1171. .halt_reg = 0x6010,
  1172. .clkr = {
  1173. .enable_reg = 0x6010,
  1174. .enable_mask = BIT(0),
  1175. .hw.init = &(struct clk_init_data){
  1176. .name = "gcc_periph_noc_usb20_ahb_clk",
  1177. .parent_names = (const char *[]){ "usb20_master_clk_src" },
  1178. .num_parents = 1,
  1179. .flags = CLK_SET_RATE_PARENT,
  1180. .ops = &clk_branch2_ops,
  1181. },
  1182. },
  1183. };
  1184. static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
  1185. .halt_reg = 0x9008,
  1186. .clkr = {
  1187. .enable_reg = 0x9008,
  1188. .enable_mask = BIT(0),
  1189. .hw.init = &(struct clk_init_data){
  1190. .name = "gcc_mmss_noc_cfg_ahb_clk",
  1191. .parent_names = (const char *[]){ "config_noc_clk_src" },
  1192. .num_parents = 1,
  1193. .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
  1194. .ops = &clk_branch2_ops,
  1195. },
  1196. },
  1197. };
  1198. static struct clk_branch gcc_mmss_bimc_gfx_clk = {
  1199. .halt_reg = 0x9010,
  1200. .clkr = {
  1201. .enable_reg = 0x9010,
  1202. .enable_mask = BIT(0),
  1203. .hw.init = &(struct clk_init_data){
  1204. .name = "gcc_mmss_bimc_gfx_clk",
  1205. .flags = CLK_SET_RATE_PARENT,
  1206. .ops = &clk_branch2_ops,
  1207. },
  1208. },
  1209. };
  1210. static struct clk_branch gcc_usb30_master_clk = {
  1211. .halt_reg = 0x0f008,
  1212. .clkr = {
  1213. .enable_reg = 0x0f008,
  1214. .enable_mask = BIT(0),
  1215. .hw.init = &(struct clk_init_data){
  1216. .name = "gcc_usb30_master_clk",
  1217. .parent_names = (const char *[]){ "usb30_master_clk_src" },
  1218. .num_parents = 1,
  1219. .flags = CLK_SET_RATE_PARENT,
  1220. .ops = &clk_branch2_ops,
  1221. },
  1222. },
  1223. };
  1224. static struct clk_branch gcc_usb30_sleep_clk = {
  1225. .halt_reg = 0x0f00c,
  1226. .clkr = {
  1227. .enable_reg = 0x0f00c,
  1228. .enable_mask = BIT(0),
  1229. .hw.init = &(struct clk_init_data){
  1230. .name = "gcc_usb30_sleep_clk",
  1231. .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
  1232. .num_parents = 1,
  1233. .flags = CLK_SET_RATE_PARENT,
  1234. .ops = &clk_branch2_ops,
  1235. },
  1236. },
  1237. };
  1238. static struct clk_branch gcc_usb30_mock_utmi_clk = {
  1239. .halt_reg = 0x0f010,
  1240. .clkr = {
  1241. .enable_reg = 0x0f010,
  1242. .enable_mask = BIT(0),
  1243. .hw.init = &(struct clk_init_data){
  1244. .name = "gcc_usb30_mock_utmi_clk",
  1245. .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
  1246. .num_parents = 1,
  1247. .flags = CLK_SET_RATE_PARENT,
  1248. .ops = &clk_branch2_ops,
  1249. },
  1250. },
  1251. };
  1252. static struct clk_branch gcc_usb3_phy_aux_clk = {
  1253. .halt_reg = 0x50000,
  1254. .clkr = {
  1255. .enable_reg = 0x50000,
  1256. .enable_mask = BIT(0),
  1257. .hw.init = &(struct clk_init_data){
  1258. .name = "gcc_usb3_phy_aux_clk",
  1259. .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
  1260. .num_parents = 1,
  1261. .flags = CLK_SET_RATE_PARENT,
  1262. .ops = &clk_branch2_ops,
  1263. },
  1264. },
  1265. };
  1266. static struct clk_branch gcc_usb3_phy_pipe_clk = {
  1267. .halt_reg = 0x50004,
  1268. .clkr = {
  1269. .enable_reg = 0x50004,
  1270. .enable_mask = BIT(0),
  1271. .hw.init = &(struct clk_init_data){
  1272. .name = "gcc_usb3_phy_pipe_clk",
  1273. .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
  1274. .num_parents = 1,
  1275. .flags = CLK_SET_RATE_PARENT,
  1276. .ops = &clk_branch2_ops,
  1277. },
  1278. },
  1279. };
  1280. static struct clk_branch gcc_usb20_master_clk = {
  1281. .halt_reg = 0x12004,
  1282. .clkr = {
  1283. .enable_reg = 0x12004,
  1284. .enable_mask = BIT(0),
  1285. .hw.init = &(struct clk_init_data){
  1286. .name = "gcc_usb20_master_clk",
  1287. .parent_names = (const char *[]){ "usb20_master_clk_src" },
  1288. .num_parents = 1,
  1289. .flags = CLK_SET_RATE_PARENT,
  1290. .ops = &clk_branch2_ops,
  1291. },
  1292. },
  1293. };
  1294. static struct clk_branch gcc_usb20_sleep_clk = {
  1295. .halt_reg = 0x12008,
  1296. .clkr = {
  1297. .enable_reg = 0x12008,
  1298. .enable_mask = BIT(0),
  1299. .hw.init = &(struct clk_init_data){
  1300. .name = "gcc_usb20_sleep_clk",
  1301. .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
  1302. .num_parents = 1,
  1303. .flags = CLK_SET_RATE_PARENT,
  1304. .ops = &clk_branch2_ops,
  1305. },
  1306. },
  1307. };
  1308. static struct clk_branch gcc_usb20_mock_utmi_clk = {
  1309. .halt_reg = 0x1200c,
  1310. .clkr = {
  1311. .enable_reg = 0x1200c,
  1312. .enable_mask = BIT(0),
  1313. .hw.init = &(struct clk_init_data){
  1314. .name = "gcc_usb20_mock_utmi_clk",
  1315. .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
  1316. .num_parents = 1,
  1317. .flags = CLK_SET_RATE_PARENT,
  1318. .ops = &clk_branch2_ops,
  1319. },
  1320. },
  1321. };
  1322. static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
  1323. .halt_reg = 0x6a004,
  1324. .clkr = {
  1325. .enable_reg = 0x6a004,
  1326. .enable_mask = BIT(0),
  1327. .hw.init = &(struct clk_init_data){
  1328. .name = "gcc_usb_phy_cfg_ahb2phy_clk",
  1329. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  1330. .num_parents = 1,
  1331. .flags = CLK_SET_RATE_PARENT,
  1332. .ops = &clk_branch2_ops,
  1333. },
  1334. },
  1335. };
  1336. static struct clk_branch gcc_sdcc1_apps_clk = {
  1337. .halt_reg = 0x13004,
  1338. .clkr = {
  1339. .enable_reg = 0x13004,
  1340. .enable_mask = BIT(0),
  1341. .hw.init = &(struct clk_init_data){
  1342. .name = "gcc_sdcc1_apps_clk",
  1343. .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
  1344. .num_parents = 1,
  1345. .flags = CLK_SET_RATE_PARENT,
  1346. .ops = &clk_branch2_ops,
  1347. },
  1348. },
  1349. };
  1350. static struct clk_branch gcc_sdcc1_ahb_clk = {
  1351. .halt_reg = 0x13008,
  1352. .clkr = {
  1353. .enable_reg = 0x13008,
  1354. .enable_mask = BIT(0),
  1355. .hw.init = &(struct clk_init_data){
  1356. .name = "gcc_sdcc1_ahb_clk",
  1357. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  1358. .num_parents = 1,
  1359. .flags = CLK_SET_RATE_PARENT,
  1360. .ops = &clk_branch2_ops,
  1361. },
  1362. },
  1363. };
  1364. static struct clk_branch gcc_sdcc1_ice_core_clk = {
  1365. .halt_reg = 0x13038,
  1366. .clkr = {
  1367. .enable_reg = 0x13038,
  1368. .enable_mask = BIT(0),
  1369. .hw.init = &(struct clk_init_data){
  1370. .name = "gcc_sdcc1_ice_core_clk",
  1371. .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
  1372. .num_parents = 1,
  1373. .flags = CLK_SET_RATE_PARENT,
  1374. .ops = &clk_branch2_ops,
  1375. },
  1376. },
  1377. };
  1378. static struct clk_branch gcc_sdcc2_apps_clk = {
  1379. .halt_reg = 0x14004,
  1380. .clkr = {
  1381. .enable_reg = 0x14004,
  1382. .enable_mask = BIT(0),
  1383. .hw.init = &(struct clk_init_data){
  1384. .name = "gcc_sdcc2_apps_clk",
  1385. .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
  1386. .num_parents = 1,
  1387. .flags = CLK_SET_RATE_PARENT,
  1388. .ops = &clk_branch2_ops,
  1389. },
  1390. },
  1391. };
  1392. static struct clk_branch gcc_sdcc2_ahb_clk = {
  1393. .halt_reg = 0x14008,
  1394. .clkr = {
  1395. .enable_reg = 0x14008,
  1396. .enable_mask = BIT(0),
  1397. .hw.init = &(struct clk_init_data){
  1398. .name = "gcc_sdcc2_ahb_clk",
  1399. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  1400. .num_parents = 1,
  1401. .flags = CLK_SET_RATE_PARENT,
  1402. .ops = &clk_branch2_ops,
  1403. },
  1404. },
  1405. };
  1406. static struct clk_branch gcc_sdcc3_apps_clk = {
  1407. .halt_reg = 0x15004,
  1408. .clkr = {
  1409. .enable_reg = 0x15004,
  1410. .enable_mask = BIT(0),
  1411. .hw.init = &(struct clk_init_data){
  1412. .name = "gcc_sdcc3_apps_clk",
  1413. .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
  1414. .num_parents = 1,
  1415. .flags = CLK_SET_RATE_PARENT,
  1416. .ops = &clk_branch2_ops,
  1417. },
  1418. },
  1419. };
  1420. static struct clk_branch gcc_sdcc3_ahb_clk = {
  1421. .halt_reg = 0x15008,
  1422. .clkr = {
  1423. .enable_reg = 0x15008,
  1424. .enable_mask = BIT(0),
  1425. .hw.init = &(struct clk_init_data){
  1426. .name = "gcc_sdcc3_ahb_clk",
  1427. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  1428. .num_parents = 1,
  1429. .flags = CLK_SET_RATE_PARENT,
  1430. .ops = &clk_branch2_ops,
  1431. },
  1432. },
  1433. };
  1434. static struct clk_branch gcc_sdcc4_apps_clk = {
  1435. .halt_reg = 0x16004,
  1436. .clkr = {
  1437. .enable_reg = 0x16004,
  1438. .enable_mask = BIT(0),
  1439. .hw.init = &(struct clk_init_data){
  1440. .name = "gcc_sdcc4_apps_clk",
  1441. .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
  1442. .num_parents = 1,
  1443. .flags = CLK_SET_RATE_PARENT,
  1444. .ops = &clk_branch2_ops,
  1445. },
  1446. },
  1447. };
  1448. static struct clk_branch gcc_sdcc4_ahb_clk = {
  1449. .halt_reg = 0x16008,
  1450. .clkr = {
  1451. .enable_reg = 0x16008,
  1452. .enable_mask = BIT(0),
  1453. .hw.init = &(struct clk_init_data){
  1454. .name = "gcc_sdcc4_ahb_clk",
  1455. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  1456. .num_parents = 1,
  1457. .flags = CLK_SET_RATE_PARENT,
  1458. .ops = &clk_branch2_ops,
  1459. },
  1460. },
  1461. };
  1462. static struct clk_branch gcc_blsp1_ahb_clk = {
  1463. .halt_reg = 0x17004,
  1464. .halt_check = BRANCH_HALT_VOTED,
  1465. .clkr = {
  1466. .enable_reg = 0x52004,
  1467. .enable_mask = BIT(17),
  1468. .hw.init = &(struct clk_init_data){
  1469. .name = "gcc_blsp1_ahb_clk",
  1470. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  1471. .num_parents = 1,
  1472. .flags = CLK_SET_RATE_PARENT,
  1473. .ops = &clk_branch2_ops,
  1474. },
  1475. },
  1476. };
  1477. static struct clk_branch gcc_blsp1_sleep_clk = {
  1478. .halt_reg = 0x17008,
  1479. .halt_check = BRANCH_HALT_VOTED,
  1480. .clkr = {
  1481. .enable_reg = 0x52004,
  1482. .enable_mask = BIT(16),
  1483. .hw.init = &(struct clk_init_data){
  1484. .name = "gcc_blsp1_sleep_clk",
  1485. .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
  1486. .num_parents = 1,
  1487. .flags = CLK_SET_RATE_PARENT,
  1488. .ops = &clk_branch2_ops,
  1489. },
  1490. },
  1491. };
  1492. static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
  1493. .halt_reg = 0x19004,
  1494. .clkr = {
  1495. .enable_reg = 0x19004,
  1496. .enable_mask = BIT(0),
  1497. .hw.init = &(struct clk_init_data){
  1498. .name = "gcc_blsp1_qup1_spi_apps_clk",
  1499. .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
  1500. .num_parents = 1,
  1501. .flags = CLK_SET_RATE_PARENT,
  1502. .ops = &clk_branch2_ops,
  1503. },
  1504. },
  1505. };
  1506. static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
  1507. .halt_reg = 0x19008,
  1508. .clkr = {
  1509. .enable_reg = 0x19008,
  1510. .enable_mask = BIT(0),
  1511. .hw.init = &(struct clk_init_data){
  1512. .name = "gcc_blsp1_qup1_i2c_apps_clk",
  1513. .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
  1514. .num_parents = 1,
  1515. .flags = CLK_SET_RATE_PARENT,
  1516. .ops = &clk_branch2_ops,
  1517. },
  1518. },
  1519. };
  1520. static struct clk_branch gcc_blsp1_uart1_apps_clk = {
  1521. .halt_reg = 0x1a004,
  1522. .clkr = {
  1523. .enable_reg = 0x1a004,
  1524. .enable_mask = BIT(0),
  1525. .hw.init = &(struct clk_init_data){
  1526. .name = "gcc_blsp1_uart1_apps_clk",
  1527. .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
  1528. .num_parents = 1,
  1529. .flags = CLK_SET_RATE_PARENT,
  1530. .ops = &clk_branch2_ops,
  1531. },
  1532. },
  1533. };
  1534. static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
  1535. .halt_reg = 0x1b004,
  1536. .clkr = {
  1537. .enable_reg = 0x1b004,
  1538. .enable_mask = BIT(0),
  1539. .hw.init = &(struct clk_init_data){
  1540. .name = "gcc_blsp1_qup2_spi_apps_clk",
  1541. .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
  1542. .num_parents = 1,
  1543. .flags = CLK_SET_RATE_PARENT,
  1544. .ops = &clk_branch2_ops,
  1545. },
  1546. },
  1547. };
  1548. static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
  1549. .halt_reg = 0x1b008,
  1550. .clkr = {
  1551. .enable_reg = 0x1b008,
  1552. .enable_mask = BIT(0),
  1553. .hw.init = &(struct clk_init_data){
  1554. .name = "gcc_blsp1_qup2_i2c_apps_clk",
  1555. .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
  1556. .num_parents = 1,
  1557. .flags = CLK_SET_RATE_PARENT,
  1558. .ops = &clk_branch2_ops,
  1559. },
  1560. },
  1561. };
  1562. static struct clk_branch gcc_blsp1_uart2_apps_clk = {
  1563. .halt_reg = 0x1c004,
  1564. .clkr = {
  1565. .enable_reg = 0x1c004,
  1566. .enable_mask = BIT(0),
  1567. .hw.init = &(struct clk_init_data){
  1568. .name = "gcc_blsp1_uart2_apps_clk",
  1569. .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
  1570. .num_parents = 1,
  1571. .flags = CLK_SET_RATE_PARENT,
  1572. .ops = &clk_branch2_ops,
  1573. },
  1574. },
  1575. };
  1576. static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
  1577. .halt_reg = 0x1d004,
  1578. .clkr = {
  1579. .enable_reg = 0x1d004,
  1580. .enable_mask = BIT(0),
  1581. .hw.init = &(struct clk_init_data){
  1582. .name = "gcc_blsp1_qup3_spi_apps_clk",
  1583. .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
  1584. .num_parents = 1,
  1585. .flags = CLK_SET_RATE_PARENT,
  1586. .ops = &clk_branch2_ops,
  1587. },
  1588. },
  1589. };
  1590. static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
  1591. .halt_reg = 0x1d008,
  1592. .clkr = {
  1593. .enable_reg = 0x1d008,
  1594. .enable_mask = BIT(0),
  1595. .hw.init = &(struct clk_init_data){
  1596. .name = "gcc_blsp1_qup3_i2c_apps_clk",
  1597. .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
  1598. .num_parents = 1,
  1599. .flags = CLK_SET_RATE_PARENT,
  1600. .ops = &clk_branch2_ops,
  1601. },
  1602. },
  1603. };
  1604. static struct clk_branch gcc_blsp1_uart3_apps_clk = {
  1605. .halt_reg = 0x1e004,
  1606. .clkr = {
  1607. .enable_reg = 0x1e004,
  1608. .enable_mask = BIT(0),
  1609. .hw.init = &(struct clk_init_data){
  1610. .name = "gcc_blsp1_uart3_apps_clk",
  1611. .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
  1612. .num_parents = 1,
  1613. .flags = CLK_SET_RATE_PARENT,
  1614. .ops = &clk_branch2_ops,
  1615. },
  1616. },
  1617. };
  1618. static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
  1619. .halt_reg = 0x1f004,
  1620. .clkr = {
  1621. .enable_reg = 0x1f004,
  1622. .enable_mask = BIT(0),
  1623. .hw.init = &(struct clk_init_data){
  1624. .name = "gcc_blsp1_qup4_spi_apps_clk",
  1625. .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
  1626. .num_parents = 1,
  1627. .flags = CLK_SET_RATE_PARENT,
  1628. .ops = &clk_branch2_ops,
  1629. },
  1630. },
  1631. };
  1632. static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
  1633. .halt_reg = 0x1f008,
  1634. .clkr = {
  1635. .enable_reg = 0x1f008,
  1636. .enable_mask = BIT(0),
  1637. .hw.init = &(struct clk_init_data){
  1638. .name = "gcc_blsp1_qup4_i2c_apps_clk",
  1639. .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
  1640. .num_parents = 1,
  1641. .flags = CLK_SET_RATE_PARENT,
  1642. .ops = &clk_branch2_ops,
  1643. },
  1644. },
  1645. };
  1646. static struct clk_branch gcc_blsp1_uart4_apps_clk = {
  1647. .halt_reg = 0x20004,
  1648. .clkr = {
  1649. .enable_reg = 0x20004,
  1650. .enable_mask = BIT(0),
  1651. .hw.init = &(struct clk_init_data){
  1652. .name = "gcc_blsp1_uart4_apps_clk",
  1653. .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
  1654. .num_parents = 1,
  1655. .flags = CLK_SET_RATE_PARENT,
  1656. .ops = &clk_branch2_ops,
  1657. },
  1658. },
  1659. };
  1660. static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
  1661. .halt_reg = 0x21004,
  1662. .clkr = {
  1663. .enable_reg = 0x21004,
  1664. .enable_mask = BIT(0),
  1665. .hw.init = &(struct clk_init_data){
  1666. .name = "gcc_blsp1_qup5_spi_apps_clk",
  1667. .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
  1668. .num_parents = 1,
  1669. .flags = CLK_SET_RATE_PARENT,
  1670. .ops = &clk_branch2_ops,
  1671. },
  1672. },
  1673. };
  1674. static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
  1675. .halt_reg = 0x21008,
  1676. .clkr = {
  1677. .enable_reg = 0x21008,
  1678. .enable_mask = BIT(0),
  1679. .hw.init = &(struct clk_init_data){
  1680. .name = "gcc_blsp1_qup5_i2c_apps_clk",
  1681. .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
  1682. .num_parents = 1,
  1683. .flags = CLK_SET_RATE_PARENT,
  1684. .ops = &clk_branch2_ops,
  1685. },
  1686. },
  1687. };
  1688. static struct clk_branch gcc_blsp1_uart5_apps_clk = {
  1689. .halt_reg = 0x22004,
  1690. .clkr = {
  1691. .enable_reg = 0x22004,
  1692. .enable_mask = BIT(0),
  1693. .hw.init = &(struct clk_init_data){
  1694. .name = "gcc_blsp1_uart5_apps_clk",
  1695. .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
  1696. .num_parents = 1,
  1697. .flags = CLK_SET_RATE_PARENT,
  1698. .ops = &clk_branch2_ops,
  1699. },
  1700. },
  1701. };
  1702. static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
  1703. .halt_reg = 0x23004,
  1704. .clkr = {
  1705. .enable_reg = 0x23004,
  1706. .enable_mask = BIT(0),
  1707. .hw.init = &(struct clk_init_data){
  1708. .name = "gcc_blsp1_qup6_spi_apps_clk",
  1709. .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
  1710. .num_parents = 1,
  1711. .flags = CLK_SET_RATE_PARENT,
  1712. .ops = &clk_branch2_ops,
  1713. },
  1714. },
  1715. };
  1716. static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
  1717. .halt_reg = 0x23008,
  1718. .clkr = {
  1719. .enable_reg = 0x23008,
  1720. .enable_mask = BIT(0),
  1721. .hw.init = &(struct clk_init_data){
  1722. .name = "gcc_blsp1_qup6_i2c_apps_clk",
  1723. .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
  1724. .num_parents = 1,
  1725. .flags = CLK_SET_RATE_PARENT,
  1726. .ops = &clk_branch2_ops,
  1727. },
  1728. },
  1729. };
  1730. static struct clk_branch gcc_blsp1_uart6_apps_clk = {
  1731. .halt_reg = 0x24004,
  1732. .clkr = {
  1733. .enable_reg = 0x24004,
  1734. .enable_mask = BIT(0),
  1735. .hw.init = &(struct clk_init_data){
  1736. .name = "gcc_blsp1_uart6_apps_clk",
  1737. .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
  1738. .num_parents = 1,
  1739. .flags = CLK_SET_RATE_PARENT,
  1740. .ops = &clk_branch2_ops,
  1741. },
  1742. },
  1743. };
  1744. static struct clk_branch gcc_blsp2_ahb_clk = {
  1745. .halt_reg = 0x25004,
  1746. .halt_check = BRANCH_HALT_VOTED,
  1747. .clkr = {
  1748. .enable_reg = 0x52004,
  1749. .enable_mask = BIT(15),
  1750. .hw.init = &(struct clk_init_data){
  1751. .name = "gcc_blsp2_ahb_clk",
  1752. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  1753. .num_parents = 1,
  1754. .flags = CLK_SET_RATE_PARENT,
  1755. .ops = &clk_branch2_ops,
  1756. },
  1757. },
  1758. };
  1759. static struct clk_branch gcc_blsp2_sleep_clk = {
  1760. .halt_reg = 0x25008,
  1761. .halt_check = BRANCH_HALT_VOTED,
  1762. .clkr = {
  1763. .enable_reg = 0x52004,
  1764. .enable_mask = BIT(14),
  1765. .hw.init = &(struct clk_init_data){
  1766. .name = "gcc_blsp2_sleep_clk",
  1767. .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
  1768. .num_parents = 1,
  1769. .flags = CLK_SET_RATE_PARENT,
  1770. .ops = &clk_branch2_ops,
  1771. },
  1772. },
  1773. };
  1774. static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
  1775. .halt_reg = 0x26004,
  1776. .clkr = {
  1777. .enable_reg = 0x26004,
  1778. .enable_mask = BIT(0),
  1779. .hw.init = &(struct clk_init_data){
  1780. .name = "gcc_blsp2_qup1_spi_apps_clk",
  1781. .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
  1782. .num_parents = 1,
  1783. .flags = CLK_SET_RATE_PARENT,
  1784. .ops = &clk_branch2_ops,
  1785. },
  1786. },
  1787. };
  1788. static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
  1789. .halt_reg = 0x26008,
  1790. .clkr = {
  1791. .enable_reg = 0x26008,
  1792. .enable_mask = BIT(0),
  1793. .hw.init = &(struct clk_init_data){
  1794. .name = "gcc_blsp2_qup1_i2c_apps_clk",
  1795. .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
  1796. .num_parents = 1,
  1797. .flags = CLK_SET_RATE_PARENT,
  1798. .ops = &clk_branch2_ops,
  1799. },
  1800. },
  1801. };
  1802. static struct clk_branch gcc_blsp2_uart1_apps_clk = {
  1803. .halt_reg = 0x27004,
  1804. .clkr = {
  1805. .enable_reg = 0x27004,
  1806. .enable_mask = BIT(0),
  1807. .hw.init = &(struct clk_init_data){
  1808. .name = "gcc_blsp2_uart1_apps_clk",
  1809. .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
  1810. .num_parents = 1,
  1811. .flags = CLK_SET_RATE_PARENT,
  1812. .ops = &clk_branch2_ops,
  1813. },
  1814. },
  1815. };
  1816. static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
  1817. .halt_reg = 0x28004,
  1818. .clkr = {
  1819. .enable_reg = 0x28004,
  1820. .enable_mask = BIT(0),
  1821. .hw.init = &(struct clk_init_data){
  1822. .name = "gcc_blsp2_qup2_spi_apps_clk",
  1823. .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
  1824. .num_parents = 1,
  1825. .flags = CLK_SET_RATE_PARENT,
  1826. .ops = &clk_branch2_ops,
  1827. },
  1828. },
  1829. };
  1830. static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
  1831. .halt_reg = 0x28008,
  1832. .clkr = {
  1833. .enable_reg = 0x28008,
  1834. .enable_mask = BIT(0),
  1835. .hw.init = &(struct clk_init_data){
  1836. .name = "gcc_blsp2_qup2_i2c_apps_clk",
  1837. .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
  1838. .num_parents = 1,
  1839. .flags = CLK_SET_RATE_PARENT,
  1840. .ops = &clk_branch2_ops,
  1841. },
  1842. },
  1843. };
  1844. static struct clk_branch gcc_blsp2_uart2_apps_clk = {
  1845. .halt_reg = 0x29004,
  1846. .clkr = {
  1847. .enable_reg = 0x29004,
  1848. .enable_mask = BIT(0),
  1849. .hw.init = &(struct clk_init_data){
  1850. .name = "gcc_blsp2_uart2_apps_clk",
  1851. .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
  1852. .num_parents = 1,
  1853. .flags = CLK_SET_RATE_PARENT,
  1854. .ops = &clk_branch2_ops,
  1855. },
  1856. },
  1857. };
  1858. static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
  1859. .halt_reg = 0x2a004,
  1860. .clkr = {
  1861. .enable_reg = 0x2a004,
  1862. .enable_mask = BIT(0),
  1863. .hw.init = &(struct clk_init_data){
  1864. .name = "gcc_blsp2_qup3_spi_apps_clk",
  1865. .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
  1866. .num_parents = 1,
  1867. .flags = CLK_SET_RATE_PARENT,
  1868. .ops = &clk_branch2_ops,
  1869. },
  1870. },
  1871. };
  1872. static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
  1873. .halt_reg = 0x2a008,
  1874. .clkr = {
  1875. .enable_reg = 0x2a008,
  1876. .enable_mask = BIT(0),
  1877. .hw.init = &(struct clk_init_data){
  1878. .name = "gcc_blsp2_qup3_i2c_apps_clk",
  1879. .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
  1880. .num_parents = 1,
  1881. .flags = CLK_SET_RATE_PARENT,
  1882. .ops = &clk_branch2_ops,
  1883. },
  1884. },
  1885. };
  1886. static struct clk_branch gcc_blsp2_uart3_apps_clk = {
  1887. .halt_reg = 0x2b004,
  1888. .clkr = {
  1889. .enable_reg = 0x2b004,
  1890. .enable_mask = BIT(0),
  1891. .hw.init = &(struct clk_init_data){
  1892. .name = "gcc_blsp2_uart3_apps_clk",
  1893. .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
  1894. .num_parents = 1,
  1895. .flags = CLK_SET_RATE_PARENT,
  1896. .ops = &clk_branch2_ops,
  1897. },
  1898. },
  1899. };
  1900. static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
  1901. .halt_reg = 0x2c004,
  1902. .clkr = {
  1903. .enable_reg = 0x2c004,
  1904. .enable_mask = BIT(0),
  1905. .hw.init = &(struct clk_init_data){
  1906. .name = "gcc_blsp2_qup4_spi_apps_clk",
  1907. .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
  1908. .num_parents = 1,
  1909. .flags = CLK_SET_RATE_PARENT,
  1910. .ops = &clk_branch2_ops,
  1911. },
  1912. },
  1913. };
  1914. static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
  1915. .halt_reg = 0x2c008,
  1916. .clkr = {
  1917. .enable_reg = 0x2c008,
  1918. .enable_mask = BIT(0),
  1919. .hw.init = &(struct clk_init_data){
  1920. .name = "gcc_blsp2_qup4_i2c_apps_clk",
  1921. .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
  1922. .num_parents = 1,
  1923. .flags = CLK_SET_RATE_PARENT,
  1924. .ops = &clk_branch2_ops,
  1925. },
  1926. },
  1927. };
  1928. static struct clk_branch gcc_blsp2_uart4_apps_clk = {
  1929. .halt_reg = 0x2d004,
  1930. .clkr = {
  1931. .enable_reg = 0x2d004,
  1932. .enable_mask = BIT(0),
  1933. .hw.init = &(struct clk_init_data){
  1934. .name = "gcc_blsp2_uart4_apps_clk",
  1935. .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
  1936. .num_parents = 1,
  1937. .flags = CLK_SET_RATE_PARENT,
  1938. .ops = &clk_branch2_ops,
  1939. },
  1940. },
  1941. };
  1942. static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
  1943. .halt_reg = 0x2e004,
  1944. .clkr = {
  1945. .enable_reg = 0x2e004,
  1946. .enable_mask = BIT(0),
  1947. .hw.init = &(struct clk_init_data){
  1948. .name = "gcc_blsp2_qup5_spi_apps_clk",
  1949. .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
  1950. .num_parents = 1,
  1951. .flags = CLK_SET_RATE_PARENT,
  1952. .ops = &clk_branch2_ops,
  1953. },
  1954. },
  1955. };
  1956. static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
  1957. .halt_reg = 0x2e008,
  1958. .clkr = {
  1959. .enable_reg = 0x2e008,
  1960. .enable_mask = BIT(0),
  1961. .hw.init = &(struct clk_init_data){
  1962. .name = "gcc_blsp2_qup5_i2c_apps_clk",
  1963. .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
  1964. .num_parents = 1,
  1965. .flags = CLK_SET_RATE_PARENT,
  1966. .ops = &clk_branch2_ops,
  1967. },
  1968. },
  1969. };
  1970. static struct clk_branch gcc_blsp2_uart5_apps_clk = {
  1971. .halt_reg = 0x2f004,
  1972. .clkr = {
  1973. .enable_reg = 0x2f004,
  1974. .enable_mask = BIT(0),
  1975. .hw.init = &(struct clk_init_data){
  1976. .name = "gcc_blsp2_uart5_apps_clk",
  1977. .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
  1978. .num_parents = 1,
  1979. .flags = CLK_SET_RATE_PARENT,
  1980. .ops = &clk_branch2_ops,
  1981. },
  1982. },
  1983. };
  1984. static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
  1985. .halt_reg = 0x30004,
  1986. .clkr = {
  1987. .enable_reg = 0x30004,
  1988. .enable_mask = BIT(0),
  1989. .hw.init = &(struct clk_init_data){
  1990. .name = "gcc_blsp2_qup6_spi_apps_clk",
  1991. .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
  1992. .num_parents = 1,
  1993. .flags = CLK_SET_RATE_PARENT,
  1994. .ops = &clk_branch2_ops,
  1995. },
  1996. },
  1997. };
  1998. static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
  1999. .halt_reg = 0x30008,
  2000. .clkr = {
  2001. .enable_reg = 0x30008,
  2002. .enable_mask = BIT(0),
  2003. .hw.init = &(struct clk_init_data){
  2004. .name = "gcc_blsp2_qup6_i2c_apps_clk",
  2005. .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
  2006. .num_parents = 1,
  2007. .flags = CLK_SET_RATE_PARENT,
  2008. .ops = &clk_branch2_ops,
  2009. },
  2010. },
  2011. };
  2012. static struct clk_branch gcc_blsp2_uart6_apps_clk = {
  2013. .halt_reg = 0x31004,
  2014. .clkr = {
  2015. .enable_reg = 0x31004,
  2016. .enable_mask = BIT(0),
  2017. .hw.init = &(struct clk_init_data){
  2018. .name = "gcc_blsp2_uart6_apps_clk",
  2019. .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
  2020. .num_parents = 1,
  2021. .flags = CLK_SET_RATE_PARENT,
  2022. .ops = &clk_branch2_ops,
  2023. },
  2024. },
  2025. };
  2026. static struct clk_branch gcc_pdm_ahb_clk = {
  2027. .halt_reg = 0x33004,
  2028. .clkr = {
  2029. .enable_reg = 0x33004,
  2030. .enable_mask = BIT(0),
  2031. .hw.init = &(struct clk_init_data){
  2032. .name = "gcc_pdm_ahb_clk",
  2033. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  2034. .num_parents = 1,
  2035. .flags = CLK_SET_RATE_PARENT,
  2036. .ops = &clk_branch2_ops,
  2037. },
  2038. },
  2039. };
  2040. static struct clk_branch gcc_pdm2_clk = {
  2041. .halt_reg = 0x3300c,
  2042. .clkr = {
  2043. .enable_reg = 0x3300c,
  2044. .enable_mask = BIT(0),
  2045. .hw.init = &(struct clk_init_data){
  2046. .name = "gcc_pdm2_clk",
  2047. .parent_names = (const char *[]){ "pdm2_clk_src" },
  2048. .num_parents = 1,
  2049. .flags = CLK_SET_RATE_PARENT,
  2050. .ops = &clk_branch2_ops,
  2051. },
  2052. },
  2053. };
  2054. static struct clk_branch gcc_prng_ahb_clk = {
  2055. .halt_reg = 0x34004,
  2056. .halt_check = BRANCH_HALT_VOTED,
  2057. .clkr = {
  2058. .enable_reg = 0x52004,
  2059. .enable_mask = BIT(13),
  2060. .hw.init = &(struct clk_init_data){
  2061. .name = "gcc_prng_ahb_clk",
  2062. .parent_names = (const char *[]){ "config_noc_clk_src" },
  2063. .num_parents = 1,
  2064. .flags = CLK_SET_RATE_PARENT,
  2065. .ops = &clk_branch2_ops,
  2066. },
  2067. },
  2068. };
  2069. static struct clk_branch gcc_tsif_ahb_clk = {
  2070. .halt_reg = 0x36004,
  2071. .clkr = {
  2072. .enable_reg = 0x36004,
  2073. .enable_mask = BIT(0),
  2074. .hw.init = &(struct clk_init_data){
  2075. .name = "gcc_tsif_ahb_clk",
  2076. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  2077. .num_parents = 1,
  2078. .flags = CLK_SET_RATE_PARENT,
  2079. .ops = &clk_branch2_ops,
  2080. },
  2081. },
  2082. };
  2083. static struct clk_branch gcc_tsif_ref_clk = {
  2084. .halt_reg = 0x36008,
  2085. .clkr = {
  2086. .enable_reg = 0x36008,
  2087. .enable_mask = BIT(0),
  2088. .hw.init = &(struct clk_init_data){
  2089. .name = "gcc_tsif_ref_clk",
  2090. .parent_names = (const char *[]){ "tsif_ref_clk_src" },
  2091. .num_parents = 1,
  2092. .flags = CLK_SET_RATE_PARENT,
  2093. .ops = &clk_branch2_ops,
  2094. },
  2095. },
  2096. };
  2097. static struct clk_branch gcc_tsif_inactivity_timers_clk = {
  2098. .halt_reg = 0x3600c,
  2099. .clkr = {
  2100. .enable_reg = 0x3600c,
  2101. .enable_mask = BIT(0),
  2102. .hw.init = &(struct clk_init_data){
  2103. .name = "gcc_tsif_inactivity_timers_clk",
  2104. .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
  2105. .num_parents = 1,
  2106. .flags = CLK_SET_RATE_PARENT,
  2107. .ops = &clk_branch2_ops,
  2108. },
  2109. },
  2110. };
  2111. static struct clk_branch gcc_boot_rom_ahb_clk = {
  2112. .halt_reg = 0x38004,
  2113. .halt_check = BRANCH_HALT_VOTED,
  2114. .clkr = {
  2115. .enable_reg = 0x52004,
  2116. .enable_mask = BIT(10),
  2117. .hw.init = &(struct clk_init_data){
  2118. .name = "gcc_boot_rom_ahb_clk",
  2119. .parent_names = (const char *[]){ "config_noc_clk_src" },
  2120. .num_parents = 1,
  2121. .flags = CLK_SET_RATE_PARENT,
  2122. .ops = &clk_branch2_ops,
  2123. },
  2124. },
  2125. };
  2126. static struct clk_branch gcc_bimc_gfx_clk = {
  2127. .halt_reg = 0x46018,
  2128. .clkr = {
  2129. .enable_reg = 0x46018,
  2130. .enable_mask = BIT(0),
  2131. .hw.init = &(struct clk_init_data){
  2132. .name = "gcc_bimc_gfx_clk",
  2133. .flags = CLK_SET_RATE_PARENT,
  2134. .ops = &clk_branch2_ops,
  2135. },
  2136. },
  2137. };
  2138. static struct clk_branch gcc_hmss_rbcpr_clk = {
  2139. .halt_reg = 0x4800c,
  2140. .clkr = {
  2141. .enable_reg = 0x4800c,
  2142. .enable_mask = BIT(0),
  2143. .hw.init = &(struct clk_init_data){
  2144. .name = "gcc_hmss_rbcpr_clk",
  2145. .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
  2146. .num_parents = 1,
  2147. .flags = CLK_SET_RATE_PARENT,
  2148. .ops = &clk_branch2_ops,
  2149. },
  2150. },
  2151. };
  2152. static struct clk_branch gcc_gp1_clk = {
  2153. .halt_reg = 0x64000,
  2154. .clkr = {
  2155. .enable_reg = 0x64000,
  2156. .enable_mask = BIT(0),
  2157. .hw.init = &(struct clk_init_data){
  2158. .name = "gcc_gp1_clk",
  2159. .parent_names = (const char *[]){ "gp1_clk_src" },
  2160. .num_parents = 1,
  2161. .flags = CLK_SET_RATE_PARENT,
  2162. .ops = &clk_branch2_ops,
  2163. },
  2164. },
  2165. };
  2166. static struct clk_branch gcc_gp2_clk = {
  2167. .halt_reg = 0x65000,
  2168. .clkr = {
  2169. .enable_reg = 0x65000,
  2170. .enable_mask = BIT(0),
  2171. .hw.init = &(struct clk_init_data){
  2172. .name = "gcc_gp2_clk",
  2173. .parent_names = (const char *[]){ "gp2_clk_src" },
  2174. .num_parents = 1,
  2175. .flags = CLK_SET_RATE_PARENT,
  2176. .ops = &clk_branch2_ops,
  2177. },
  2178. },
  2179. };
  2180. static struct clk_branch gcc_gp3_clk = {
  2181. .halt_reg = 0x66000,
  2182. .clkr = {
  2183. .enable_reg = 0x66000,
  2184. .enable_mask = BIT(0),
  2185. .hw.init = &(struct clk_init_data){
  2186. .name = "gcc_gp3_clk",
  2187. .parent_names = (const char *[]){ "gp3_clk_src" },
  2188. .num_parents = 1,
  2189. .flags = CLK_SET_RATE_PARENT,
  2190. .ops = &clk_branch2_ops,
  2191. },
  2192. },
  2193. };
  2194. static struct clk_branch gcc_pcie_0_slv_axi_clk = {
  2195. .halt_reg = 0x6b008,
  2196. .clkr = {
  2197. .enable_reg = 0x6b008,
  2198. .enable_mask = BIT(0),
  2199. .hw.init = &(struct clk_init_data){
  2200. .name = "gcc_pcie_0_slv_axi_clk",
  2201. .parent_names = (const char *[]){ "system_noc_clk_src" },
  2202. .num_parents = 1,
  2203. .flags = CLK_SET_RATE_PARENT,
  2204. .ops = &clk_branch2_ops,
  2205. },
  2206. },
  2207. };
  2208. static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
  2209. .halt_reg = 0x6b00c,
  2210. .clkr = {
  2211. .enable_reg = 0x6b00c,
  2212. .enable_mask = BIT(0),
  2213. .hw.init = &(struct clk_init_data){
  2214. .name = "gcc_pcie_0_mstr_axi_clk",
  2215. .parent_names = (const char *[]){ "system_noc_clk_src" },
  2216. .num_parents = 1,
  2217. .flags = CLK_SET_RATE_PARENT,
  2218. .ops = &clk_branch2_ops,
  2219. },
  2220. },
  2221. };
  2222. static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
  2223. .halt_reg = 0x6b010,
  2224. .clkr = {
  2225. .enable_reg = 0x6b010,
  2226. .enable_mask = BIT(0),
  2227. .hw.init = &(struct clk_init_data){
  2228. .name = "gcc_pcie_0_cfg_ahb_clk",
  2229. .parent_names = (const char *[]){ "config_noc_clk_src" },
  2230. .num_parents = 1,
  2231. .flags = CLK_SET_RATE_PARENT,
  2232. .ops = &clk_branch2_ops,
  2233. },
  2234. },
  2235. };
  2236. static struct clk_branch gcc_pcie_0_aux_clk = {
  2237. .halt_reg = 0x6b014,
  2238. .clkr = {
  2239. .enable_reg = 0x6b014,
  2240. .enable_mask = BIT(0),
  2241. .hw.init = &(struct clk_init_data){
  2242. .name = "gcc_pcie_0_aux_clk",
  2243. .parent_names = (const char *[]){ "pcie_aux_clk_src" },
  2244. .num_parents = 1,
  2245. .flags = CLK_SET_RATE_PARENT,
  2246. .ops = &clk_branch2_ops,
  2247. },
  2248. },
  2249. };
  2250. static struct clk_branch gcc_pcie_0_pipe_clk = {
  2251. .halt_reg = 0x6b018,
  2252. .clkr = {
  2253. .enable_reg = 0x6b018,
  2254. .enable_mask = BIT(0),
  2255. .hw.init = &(struct clk_init_data){
  2256. .name = "gcc_pcie_0_pipe_clk",
  2257. .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
  2258. .num_parents = 1,
  2259. .flags = CLK_SET_RATE_PARENT,
  2260. .ops = &clk_branch2_ops,
  2261. },
  2262. },
  2263. };
  2264. static struct clk_branch gcc_pcie_1_slv_axi_clk = {
  2265. .halt_reg = 0x6d008,
  2266. .clkr = {
  2267. .enable_reg = 0x6d008,
  2268. .enable_mask = BIT(0),
  2269. .hw.init = &(struct clk_init_data){
  2270. .name = "gcc_pcie_1_slv_axi_clk",
  2271. .parent_names = (const char *[]){ "system_noc_clk_src" },
  2272. .num_parents = 1,
  2273. .flags = CLK_SET_RATE_PARENT,
  2274. .ops = &clk_branch2_ops,
  2275. },
  2276. },
  2277. };
  2278. static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
  2279. .halt_reg = 0x6d00c,
  2280. .clkr = {
  2281. .enable_reg = 0x6d00c,
  2282. .enable_mask = BIT(0),
  2283. .hw.init = &(struct clk_init_data){
  2284. .name = "gcc_pcie_1_mstr_axi_clk",
  2285. .parent_names = (const char *[]){ "system_noc_clk_src" },
  2286. .num_parents = 1,
  2287. .flags = CLK_SET_RATE_PARENT,
  2288. .ops = &clk_branch2_ops,
  2289. },
  2290. },
  2291. };
  2292. static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
  2293. .halt_reg = 0x6d010,
  2294. .clkr = {
  2295. .enable_reg = 0x6d010,
  2296. .enable_mask = BIT(0),
  2297. .hw.init = &(struct clk_init_data){
  2298. .name = "gcc_pcie_1_cfg_ahb_clk",
  2299. .parent_names = (const char *[]){ "config_noc_clk_src" },
  2300. .num_parents = 1,
  2301. .flags = CLK_SET_RATE_PARENT,
  2302. .ops = &clk_branch2_ops,
  2303. },
  2304. },
  2305. };
  2306. static struct clk_branch gcc_pcie_1_aux_clk = {
  2307. .halt_reg = 0x6d014,
  2308. .clkr = {
  2309. .enable_reg = 0x6d014,
  2310. .enable_mask = BIT(0),
  2311. .hw.init = &(struct clk_init_data){
  2312. .name = "gcc_pcie_1_aux_clk",
  2313. .parent_names = (const char *[]){ "pcie_aux_clk_src" },
  2314. .num_parents = 1,
  2315. .flags = CLK_SET_RATE_PARENT,
  2316. .ops = &clk_branch2_ops,
  2317. },
  2318. },
  2319. };
  2320. static struct clk_branch gcc_pcie_1_pipe_clk = {
  2321. .halt_reg = 0x6d018,
  2322. .clkr = {
  2323. .enable_reg = 0x6d018,
  2324. .enable_mask = BIT(0),
  2325. .hw.init = &(struct clk_init_data){
  2326. .name = "gcc_pcie_1_pipe_clk",
  2327. .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
  2328. .num_parents = 1,
  2329. .flags = CLK_SET_RATE_PARENT,
  2330. .ops = &clk_branch2_ops,
  2331. },
  2332. },
  2333. };
  2334. static struct clk_branch gcc_pcie_2_slv_axi_clk = {
  2335. .halt_reg = 0x6e008,
  2336. .clkr = {
  2337. .enable_reg = 0x6e008,
  2338. .enable_mask = BIT(0),
  2339. .hw.init = &(struct clk_init_data){
  2340. .name = "gcc_pcie_2_slv_axi_clk",
  2341. .parent_names = (const char *[]){ "system_noc_clk_src" },
  2342. .num_parents = 1,
  2343. .flags = CLK_SET_RATE_PARENT,
  2344. .ops = &clk_branch2_ops,
  2345. },
  2346. },
  2347. };
  2348. static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
  2349. .halt_reg = 0x6e00c,
  2350. .clkr = {
  2351. .enable_reg = 0x6e00c,
  2352. .enable_mask = BIT(0),
  2353. .hw.init = &(struct clk_init_data){
  2354. .name = "gcc_pcie_2_mstr_axi_clk",
  2355. .parent_names = (const char *[]){ "system_noc_clk_src" },
  2356. .num_parents = 1,
  2357. .flags = CLK_SET_RATE_PARENT,
  2358. .ops = &clk_branch2_ops,
  2359. },
  2360. },
  2361. };
  2362. static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
  2363. .halt_reg = 0x6e010,
  2364. .clkr = {
  2365. .enable_reg = 0x6e010,
  2366. .enable_mask = BIT(0),
  2367. .hw.init = &(struct clk_init_data){
  2368. .name = "gcc_pcie_2_cfg_ahb_clk",
  2369. .parent_names = (const char *[]){ "config_noc_clk_src" },
  2370. .num_parents = 1,
  2371. .flags = CLK_SET_RATE_PARENT,
  2372. .ops = &clk_branch2_ops,
  2373. },
  2374. },
  2375. };
  2376. static struct clk_branch gcc_pcie_2_aux_clk = {
  2377. .halt_reg = 0x6e014,
  2378. .clkr = {
  2379. .enable_reg = 0x6e014,
  2380. .enable_mask = BIT(0),
  2381. .hw.init = &(struct clk_init_data){
  2382. .name = "gcc_pcie_2_aux_clk",
  2383. .parent_names = (const char *[]){ "pcie_aux_clk_src" },
  2384. .num_parents = 1,
  2385. .flags = CLK_SET_RATE_PARENT,
  2386. .ops = &clk_branch2_ops,
  2387. },
  2388. },
  2389. };
  2390. static struct clk_branch gcc_pcie_2_pipe_clk = {
  2391. .halt_reg = 0x6e018,
  2392. .clkr = {
  2393. .enable_reg = 0x6e018,
  2394. .enable_mask = BIT(0),
  2395. .hw.init = &(struct clk_init_data){
  2396. .name = "gcc_pcie_2_pipe_clk",
  2397. .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
  2398. .num_parents = 1,
  2399. .flags = CLK_SET_RATE_PARENT,
  2400. .ops = &clk_branch2_ops,
  2401. },
  2402. },
  2403. };
  2404. static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
  2405. .halt_reg = 0x6f004,
  2406. .clkr = {
  2407. .enable_reg = 0x6f004,
  2408. .enable_mask = BIT(0),
  2409. .hw.init = &(struct clk_init_data){
  2410. .name = "gcc_pcie_phy_cfg_ahb_clk",
  2411. .parent_names = (const char *[]){ "config_noc_clk_src" },
  2412. .num_parents = 1,
  2413. .flags = CLK_SET_RATE_PARENT,
  2414. .ops = &clk_branch2_ops,
  2415. },
  2416. },
  2417. };
  2418. static struct clk_branch gcc_pcie_phy_aux_clk = {
  2419. .halt_reg = 0x6f008,
  2420. .clkr = {
  2421. .enable_reg = 0x6f008,
  2422. .enable_mask = BIT(0),
  2423. .hw.init = &(struct clk_init_data){
  2424. .name = "gcc_pcie_phy_aux_clk",
  2425. .parent_names = (const char *[]){ "pcie_aux_clk_src" },
  2426. .num_parents = 1,
  2427. .flags = CLK_SET_RATE_PARENT,
  2428. .ops = &clk_branch2_ops,
  2429. },
  2430. },
  2431. };
  2432. static struct clk_branch gcc_ufs_axi_clk = {
  2433. .halt_reg = 0x75008,
  2434. .clkr = {
  2435. .enable_reg = 0x75008,
  2436. .enable_mask = BIT(0),
  2437. .hw.init = &(struct clk_init_data){
  2438. .name = "gcc_ufs_axi_clk",
  2439. .parent_names = (const char *[]){ "ufs_axi_clk_src" },
  2440. .num_parents = 1,
  2441. .flags = CLK_SET_RATE_PARENT,
  2442. .ops = &clk_branch2_ops,
  2443. },
  2444. },
  2445. };
  2446. static struct clk_branch gcc_ufs_ahb_clk = {
  2447. .halt_reg = 0x7500c,
  2448. .clkr = {
  2449. .enable_reg = 0x7500c,
  2450. .enable_mask = BIT(0),
  2451. .hw.init = &(struct clk_init_data){
  2452. .name = "gcc_ufs_ahb_clk",
  2453. .parent_names = (const char *[]){ "config_noc_clk_src" },
  2454. .num_parents = 1,
  2455. .flags = CLK_SET_RATE_PARENT,
  2456. .ops = &clk_branch2_ops,
  2457. },
  2458. },
  2459. };
  2460. static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
  2461. .mult = 1,
  2462. .div = 16,
  2463. .hw.init = &(struct clk_init_data){
  2464. .name = "ufs_tx_cfg_clk_src",
  2465. .parent_names = (const char *[]){ "ufs_axi_clk_src" },
  2466. .num_parents = 1,
  2467. .flags = CLK_SET_RATE_PARENT,
  2468. .ops = &clk_fixed_factor_ops,
  2469. },
  2470. };
  2471. static struct clk_branch gcc_ufs_tx_cfg_clk = {
  2472. .halt_reg = 0x75010,
  2473. .clkr = {
  2474. .enable_reg = 0x75010,
  2475. .enable_mask = BIT(0),
  2476. .hw.init = &(struct clk_init_data){
  2477. .name = "gcc_ufs_tx_cfg_clk",
  2478. .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
  2479. .num_parents = 1,
  2480. .flags = CLK_SET_RATE_PARENT,
  2481. .ops = &clk_branch2_ops,
  2482. },
  2483. },
  2484. };
  2485. static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
  2486. .mult = 1,
  2487. .div = 16,
  2488. .hw.init = &(struct clk_init_data){
  2489. .name = "ufs_rx_cfg_clk_src",
  2490. .parent_names = (const char *[]){ "ufs_axi_clk_src" },
  2491. .num_parents = 1,
  2492. .flags = CLK_SET_RATE_PARENT,
  2493. .ops = &clk_fixed_factor_ops,
  2494. },
  2495. };
  2496. static struct clk_branch gcc_ufs_rx_cfg_clk = {
  2497. .halt_reg = 0x75014,
  2498. .clkr = {
  2499. .enable_reg = 0x75014,
  2500. .enable_mask = BIT(0),
  2501. .hw.init = &(struct clk_init_data){
  2502. .name = "gcc_ufs_rx_cfg_clk",
  2503. .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
  2504. .num_parents = 1,
  2505. .flags = CLK_SET_RATE_PARENT,
  2506. .ops = &clk_branch2_ops,
  2507. },
  2508. },
  2509. };
  2510. static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
  2511. .halt_reg = 0x75018,
  2512. .clkr = {
  2513. .enable_reg = 0x75018,
  2514. .enable_mask = BIT(0),
  2515. .hw.init = &(struct clk_init_data){
  2516. .name = "gcc_ufs_tx_symbol_0_clk",
  2517. .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
  2518. .num_parents = 1,
  2519. .flags = CLK_SET_RATE_PARENT,
  2520. .ops = &clk_branch2_ops,
  2521. },
  2522. },
  2523. };
  2524. static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
  2525. .halt_reg = 0x7501c,
  2526. .clkr = {
  2527. .enable_reg = 0x7501c,
  2528. .enable_mask = BIT(0),
  2529. .hw.init = &(struct clk_init_data){
  2530. .name = "gcc_ufs_rx_symbol_0_clk",
  2531. .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
  2532. .num_parents = 1,
  2533. .flags = CLK_SET_RATE_PARENT,
  2534. .ops = &clk_branch2_ops,
  2535. },
  2536. },
  2537. };
  2538. static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
  2539. .halt_reg = 0x75020,
  2540. .clkr = {
  2541. .enable_reg = 0x75020,
  2542. .enable_mask = BIT(0),
  2543. .hw.init = &(struct clk_init_data){
  2544. .name = "gcc_ufs_rx_symbol_1_clk",
  2545. .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
  2546. .num_parents = 1,
  2547. .flags = CLK_SET_RATE_PARENT,
  2548. .ops = &clk_branch2_ops,
  2549. },
  2550. },
  2551. };
  2552. static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
  2553. .mult = 1,
  2554. .div = 2,
  2555. .hw.init = &(struct clk_init_data){
  2556. .name = "ufs_ice_core_postdiv_clk_src",
  2557. .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
  2558. .num_parents = 1,
  2559. .flags = CLK_SET_RATE_PARENT,
  2560. .ops = &clk_fixed_factor_ops,
  2561. },
  2562. };
  2563. static struct clk_branch gcc_ufs_unipro_core_clk = {
  2564. .halt_reg = 0x7600c,
  2565. .clkr = {
  2566. .enable_reg = 0x7600c,
  2567. .enable_mask = BIT(0),
  2568. .hw.init = &(struct clk_init_data){
  2569. .name = "gcc_ufs_unipro_core_clk",
  2570. .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
  2571. .num_parents = 1,
  2572. .flags = CLK_SET_RATE_PARENT,
  2573. .ops = &clk_branch2_ops,
  2574. },
  2575. },
  2576. };
  2577. static struct clk_branch gcc_ufs_ice_core_clk = {
  2578. .halt_reg = 0x76010,
  2579. .clkr = {
  2580. .enable_reg = 0x76010,
  2581. .enable_mask = BIT(0),
  2582. .hw.init = &(struct clk_init_data){
  2583. .name = "gcc_ufs_ice_core_clk",
  2584. .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
  2585. .num_parents = 1,
  2586. .flags = CLK_SET_RATE_PARENT,
  2587. .ops = &clk_branch2_ops,
  2588. },
  2589. },
  2590. };
  2591. static struct clk_branch gcc_ufs_sys_clk_core_clk = {
  2592. .halt_check = BRANCH_HALT_DELAY,
  2593. .clkr = {
  2594. .enable_reg = 0x76030,
  2595. .enable_mask = BIT(0),
  2596. .hw.init = &(struct clk_init_data){
  2597. .name = "gcc_ufs_sys_clk_core_clk",
  2598. .ops = &clk_branch2_ops,
  2599. },
  2600. },
  2601. };
  2602. static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
  2603. .halt_check = BRANCH_HALT_DELAY,
  2604. .clkr = {
  2605. .enable_reg = 0x76034,
  2606. .enable_mask = BIT(0),
  2607. .hw.init = &(struct clk_init_data){
  2608. .name = "gcc_ufs_tx_symbol_clk_core_clk",
  2609. .ops = &clk_branch2_ops,
  2610. },
  2611. },
  2612. };
  2613. static struct clk_branch gcc_aggre0_snoc_axi_clk = {
  2614. .halt_reg = 0x81008,
  2615. .clkr = {
  2616. .enable_reg = 0x81008,
  2617. .enable_mask = BIT(0),
  2618. .hw.init = &(struct clk_init_data){
  2619. .name = "gcc_aggre0_snoc_axi_clk",
  2620. .parent_names = (const char *[]){ "system_noc_clk_src" },
  2621. .num_parents = 1,
  2622. .flags = CLK_SET_RATE_PARENT,
  2623. .ops = &clk_branch2_ops,
  2624. },
  2625. },
  2626. };
  2627. static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
  2628. .halt_reg = 0x8100c,
  2629. .clkr = {
  2630. .enable_reg = 0x8100c,
  2631. .enable_mask = BIT(0),
  2632. .hw.init = &(struct clk_init_data){
  2633. .name = "gcc_aggre0_cnoc_ahb_clk",
  2634. .parent_names = (const char *[]){ "config_noc_clk_src" },
  2635. .num_parents = 1,
  2636. .flags = CLK_SET_RATE_PARENT,
  2637. .ops = &clk_branch2_ops,
  2638. },
  2639. },
  2640. };
  2641. static struct clk_branch gcc_smmu_aggre0_axi_clk = {
  2642. .halt_reg = 0x81014,
  2643. .clkr = {
  2644. .enable_reg = 0x81014,
  2645. .enable_mask = BIT(0),
  2646. .hw.init = &(struct clk_init_data){
  2647. .name = "gcc_smmu_aggre0_axi_clk",
  2648. .parent_names = (const char *[]){ "system_noc_clk_src" },
  2649. .num_parents = 1,
  2650. .flags = CLK_SET_RATE_PARENT,
  2651. .ops = &clk_branch2_ops,
  2652. },
  2653. },
  2654. };
  2655. static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
  2656. .halt_reg = 0x81018,
  2657. .clkr = {
  2658. .enable_reg = 0x81018,
  2659. .enable_mask = BIT(0),
  2660. .hw.init = &(struct clk_init_data){
  2661. .name = "gcc_smmu_aggre0_ahb_clk",
  2662. .parent_names = (const char *[]){ "config_noc_clk_src" },
  2663. .num_parents = 1,
  2664. .flags = CLK_SET_RATE_PARENT,
  2665. .ops = &clk_branch2_ops,
  2666. },
  2667. },
  2668. };
  2669. static struct clk_branch gcc_aggre2_ufs_axi_clk = {
  2670. .halt_reg = 0x83014,
  2671. .clkr = {
  2672. .enable_reg = 0x83014,
  2673. .enable_mask = BIT(0),
  2674. .hw.init = &(struct clk_init_data){
  2675. .name = "gcc_aggre2_ufs_axi_clk",
  2676. .parent_names = (const char *[]){ "ufs_axi_clk_src" },
  2677. .num_parents = 1,
  2678. .flags = CLK_SET_RATE_PARENT,
  2679. .ops = &clk_branch2_ops,
  2680. },
  2681. },
  2682. };
  2683. static struct clk_branch gcc_aggre2_usb3_axi_clk = {
  2684. .halt_reg = 0x83018,
  2685. .clkr = {
  2686. .enable_reg = 0x83018,
  2687. .enable_mask = BIT(0),
  2688. .hw.init = &(struct clk_init_data){
  2689. .name = "gcc_aggre2_usb3_axi_clk",
  2690. .parent_names = (const char *[]){ "usb30_master_clk_src" },
  2691. .num_parents = 1,
  2692. .flags = CLK_SET_RATE_PARENT,
  2693. .ops = &clk_branch2_ops,
  2694. },
  2695. },
  2696. };
  2697. static struct clk_branch gcc_qspi_ahb_clk = {
  2698. .halt_reg = 0x8b004,
  2699. .clkr = {
  2700. .enable_reg = 0x8b004,
  2701. .enable_mask = BIT(0),
  2702. .hw.init = &(struct clk_init_data){
  2703. .name = "gcc_qspi_ahb_clk",
  2704. .parent_names = (const char *[]){ "periph_noc_clk_src" },
  2705. .num_parents = 1,
  2706. .flags = CLK_SET_RATE_PARENT,
  2707. .ops = &clk_branch2_ops,
  2708. },
  2709. },
  2710. };
  2711. static struct clk_branch gcc_qspi_ser_clk = {
  2712. .halt_reg = 0x8b008,
  2713. .clkr = {
  2714. .enable_reg = 0x8b008,
  2715. .enable_mask = BIT(0),
  2716. .hw.init = &(struct clk_init_data){
  2717. .name = "gcc_qspi_ser_clk",
  2718. .parent_names = (const char *[]){ "qspi_ser_clk_src" },
  2719. .num_parents = 1,
  2720. .flags = CLK_SET_RATE_PARENT,
  2721. .ops = &clk_branch2_ops,
  2722. },
  2723. },
  2724. };
  2725. static struct clk_branch gcc_usb3_clkref_clk = {
  2726. .halt_reg = 0x8800C,
  2727. .clkr = {
  2728. .enable_reg = 0x8800C,
  2729. .enable_mask = BIT(0),
  2730. .hw.init = &(struct clk_init_data){
  2731. .name = "gcc_usb3_clkref_clk",
  2732. .parent_names = (const char *[]){ "xo" },
  2733. .num_parents = 1,
  2734. .ops = &clk_branch2_ops,
  2735. },
  2736. },
  2737. };
  2738. static struct clk_branch gcc_hdmi_clkref_clk = {
  2739. .halt_reg = 0x88000,
  2740. .clkr = {
  2741. .enable_reg = 0x88000,
  2742. .enable_mask = BIT(0),
  2743. .hw.init = &(struct clk_init_data){
  2744. .name = "gcc_hdmi_clkref_clk",
  2745. .parent_names = (const char *[]){ "xo" },
  2746. .num_parents = 1,
  2747. .ops = &clk_branch2_ops,
  2748. },
  2749. },
  2750. };
  2751. static struct clk_branch gcc_ufs_clkref_clk = {
  2752. .halt_reg = 0x88008,
  2753. .clkr = {
  2754. .enable_reg = 0x88008,
  2755. .enable_mask = BIT(0),
  2756. .hw.init = &(struct clk_init_data){
  2757. .name = "gcc_ufs_clkref_clk",
  2758. .parent_names = (const char *[]){ "xo" },
  2759. .num_parents = 1,
  2760. .ops = &clk_branch2_ops,
  2761. },
  2762. },
  2763. };
  2764. static struct clk_branch gcc_pcie_clkref_clk = {
  2765. .halt_reg = 0x88010,
  2766. .clkr = {
  2767. .enable_reg = 0x88010,
  2768. .enable_mask = BIT(0),
  2769. .hw.init = &(struct clk_init_data){
  2770. .name = "gcc_pcie_clkref_clk",
  2771. .parent_names = (const char *[]){ "xo" },
  2772. .num_parents = 1,
  2773. .ops = &clk_branch2_ops,
  2774. },
  2775. },
  2776. };
  2777. static struct clk_branch gcc_rx2_usb2_clkref_clk = {
  2778. .halt_reg = 0x88014,
  2779. .clkr = {
  2780. .enable_reg = 0x88014,
  2781. .enable_mask = BIT(0),
  2782. .hw.init = &(struct clk_init_data){
  2783. .name = "gcc_rx2_usb2_clkref_clk",
  2784. .parent_names = (const char *[]){ "xo" },
  2785. .num_parents = 1,
  2786. .ops = &clk_branch2_ops,
  2787. },
  2788. },
  2789. };
  2790. static struct clk_branch gcc_rx1_usb2_clkref_clk = {
  2791. .halt_reg = 0x88018,
  2792. .clkr = {
  2793. .enable_reg = 0x88018,
  2794. .enable_mask = BIT(0),
  2795. .hw.init = &(struct clk_init_data){
  2796. .name = "gcc_rx1_usb2_clkref_clk",
  2797. .parent_names = (const char *[]){ "xo" },
  2798. .num_parents = 1,
  2799. .ops = &clk_branch2_ops,
  2800. },
  2801. },
  2802. };
  2803. static struct clk_hw *gcc_msm8996_hws[] = {
  2804. &xo.hw,
  2805. &gpll0_early_div.hw,
  2806. &ufs_tx_cfg_clk_src.hw,
  2807. &ufs_rx_cfg_clk_src.hw,
  2808. &ufs_ice_core_postdiv_clk_src.hw,
  2809. };
  2810. static struct gdsc aggre0_noc_gdsc = {
  2811. .gdscr = 0x81004,
  2812. .gds_hw_ctrl = 0x81028,
  2813. .pd = {
  2814. .name = "aggre0_noc",
  2815. },
  2816. .pwrsts = PWRSTS_OFF_ON,
  2817. .flags = VOTABLE,
  2818. };
  2819. static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
  2820. .gdscr = 0x7d024,
  2821. .pd = {
  2822. .name = "hlos1_vote_aggre0_noc",
  2823. },
  2824. .pwrsts = PWRSTS_OFF_ON,
  2825. .flags = VOTABLE,
  2826. };
  2827. static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
  2828. .gdscr = 0x7d034,
  2829. .pd = {
  2830. .name = "hlos1_vote_lpass_adsp",
  2831. },
  2832. .pwrsts = PWRSTS_OFF_ON,
  2833. .flags = VOTABLE,
  2834. };
  2835. static struct gdsc hlos1_vote_lpass_core_gdsc = {
  2836. .gdscr = 0x7d038,
  2837. .pd = {
  2838. .name = "hlos1_vote_lpass_core",
  2839. },
  2840. .pwrsts = PWRSTS_OFF_ON,
  2841. .flags = VOTABLE,
  2842. };
  2843. static struct gdsc usb30_gdsc = {
  2844. .gdscr = 0xf004,
  2845. .pd = {
  2846. .name = "usb30",
  2847. },
  2848. .pwrsts = PWRSTS_OFF_ON,
  2849. };
  2850. static struct gdsc pcie0_gdsc = {
  2851. .gdscr = 0x6b004,
  2852. .pd = {
  2853. .name = "pcie0",
  2854. },
  2855. .pwrsts = PWRSTS_OFF_ON,
  2856. };
  2857. static struct gdsc pcie1_gdsc = {
  2858. .gdscr = 0x6d004,
  2859. .pd = {
  2860. .name = "pcie1",
  2861. },
  2862. .pwrsts = PWRSTS_OFF_ON,
  2863. };
  2864. static struct gdsc pcie2_gdsc = {
  2865. .gdscr = 0x6e004,
  2866. .pd = {
  2867. .name = "pcie2",
  2868. },
  2869. .pwrsts = PWRSTS_OFF_ON,
  2870. };
  2871. static struct gdsc ufs_gdsc = {
  2872. .gdscr = 0x75004,
  2873. .pd = {
  2874. .name = "ufs",
  2875. },
  2876. .pwrsts = PWRSTS_OFF_ON,
  2877. };
  2878. static struct clk_regmap *gcc_msm8996_clocks[] = {
  2879. [GPLL0_EARLY] = &gpll0_early.clkr,
  2880. [GPLL0] = &gpll0.clkr,
  2881. [GPLL4_EARLY] = &gpll4_early.clkr,
  2882. [GPLL4] = &gpll4.clkr,
  2883. [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
  2884. [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
  2885. [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
  2886. [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
  2887. [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
  2888. [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
  2889. [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
  2890. [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
  2891. [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
  2892. [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
  2893. [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
  2894. [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
  2895. [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
  2896. [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
  2897. [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
  2898. [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
  2899. [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
  2900. [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
  2901. [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
  2902. [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
  2903. [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
  2904. [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
  2905. [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
  2906. [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
  2907. [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
  2908. [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
  2909. [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
  2910. [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
  2911. [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
  2912. [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
  2913. [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
  2914. [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
  2915. [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
  2916. [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
  2917. [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
  2918. [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
  2919. [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
  2920. [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
  2921. [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
  2922. [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
  2923. [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
  2924. [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
  2925. [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
  2926. [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
  2927. [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
  2928. [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
  2929. [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
  2930. [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
  2931. [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
  2932. [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
  2933. [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
  2934. [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
  2935. [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
  2936. [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
  2937. [GP1_CLK_SRC] = &gp1_clk_src.clkr,
  2938. [GP2_CLK_SRC] = &gp2_clk_src.clkr,
  2939. [GP3_CLK_SRC] = &gp3_clk_src.clkr,
  2940. [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
  2941. [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
  2942. [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
  2943. [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
  2944. [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
  2945. [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
  2946. [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
  2947. [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
  2948. [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
  2949. [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
  2950. [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
  2951. [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
  2952. [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
  2953. [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
  2954. [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
  2955. [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
  2956. [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
  2957. [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
  2958. [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
  2959. [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
  2960. [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
  2961. [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
  2962. [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
  2963. [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
  2964. [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
  2965. [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
  2966. [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
  2967. [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
  2968. [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
  2969. [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
  2970. [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
  2971. [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
  2972. [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
  2973. [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
  2974. [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
  2975. [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
  2976. [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
  2977. [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
  2978. [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
  2979. [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
  2980. [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
  2981. [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
  2982. [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
  2983. [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
  2984. [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
  2985. [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
  2986. [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
  2987. [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
  2988. [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
  2989. [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
  2990. [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
  2991. [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
  2992. [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
  2993. [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
  2994. [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
  2995. [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
  2996. [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
  2997. [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
  2998. [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
  2999. [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
  3000. [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
  3001. [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
  3002. [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
  3003. [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
  3004. [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
  3005. [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
  3006. [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
  3007. [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
  3008. [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
  3009. [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
  3010. [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
  3011. [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
  3012. [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
  3013. [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
  3014. [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
  3015. [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
  3016. [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
  3017. [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
  3018. [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
  3019. [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
  3020. [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
  3021. [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
  3022. [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
  3023. [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
  3024. [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
  3025. [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
  3026. [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
  3027. [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
  3028. [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
  3029. [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
  3030. [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
  3031. [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
  3032. [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
  3033. [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
  3034. [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
  3035. [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
  3036. [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
  3037. [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
  3038. [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
  3039. [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
  3040. [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
  3041. [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
  3042. [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
  3043. [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
  3044. [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
  3045. [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
  3046. [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
  3047. [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
  3048. [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
  3049. [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
  3050. [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
  3051. [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
  3052. [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
  3053. [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
  3054. [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
  3055. [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
  3056. [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
  3057. [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
  3058. [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
  3059. [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
  3060. [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
  3061. };
  3062. static struct gdsc *gcc_msm8996_gdscs[] = {
  3063. [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
  3064. [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
  3065. [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
  3066. [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
  3067. [USB30_GDSC] = &usb30_gdsc,
  3068. [PCIE0_GDSC] = &pcie0_gdsc,
  3069. [PCIE1_GDSC] = &pcie1_gdsc,
  3070. [PCIE2_GDSC] = &pcie2_gdsc,
  3071. [UFS_GDSC] = &ufs_gdsc,
  3072. };
  3073. static const struct qcom_reset_map gcc_msm8996_resets[] = {
  3074. [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
  3075. [GCC_CONFIG_NOC_BCR] = { 0x5000 },
  3076. [GCC_PERIPH_NOC_BCR] = { 0x6000 },
  3077. [GCC_IMEM_BCR] = { 0x8000 },
  3078. [GCC_MMSS_BCR] = { 0x9000 },
  3079. [GCC_PIMEM_BCR] = { 0x0a000 },
  3080. [GCC_QDSS_BCR] = { 0x0c000 },
  3081. [GCC_USB_30_BCR] = { 0x0f000 },
  3082. [GCC_USB_20_BCR] = { 0x12000 },
  3083. [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
  3084. [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
  3085. [GCC_USB3_PHY_BCR] = { 0x50020 },
  3086. [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
  3087. [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
  3088. [GCC_SDCC1_BCR] = { 0x13000 },
  3089. [GCC_SDCC2_BCR] = { 0x14000 },
  3090. [GCC_SDCC3_BCR] = { 0x15000 },
  3091. [GCC_SDCC4_BCR] = { 0x16000 },
  3092. [GCC_BLSP1_BCR] = { 0x17000 },
  3093. [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
  3094. [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
  3095. [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
  3096. [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
  3097. [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
  3098. [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
  3099. [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
  3100. [GCC_BLSP1_UART4_BCR] = { 0x20000 },
  3101. [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
  3102. [GCC_BLSP1_UART5_BCR] = { 0x22000 },
  3103. [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
  3104. [GCC_BLSP1_UART6_BCR] = { 0x24000 },
  3105. [GCC_BLSP2_BCR] = { 0x25000 },
  3106. [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
  3107. [GCC_BLSP2_UART1_BCR] = { 0x27000 },
  3108. [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
  3109. [GCC_BLSP2_UART2_BCR] = { 0x29000 },
  3110. [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
  3111. [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
  3112. [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
  3113. [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
  3114. [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
  3115. [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
  3116. [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
  3117. [GCC_BLSP2_UART6_BCR] = { 0x31000 },
  3118. [GCC_PDM_BCR] = { 0x33000 },
  3119. [GCC_PRNG_BCR] = { 0x34000 },
  3120. [GCC_TSIF_BCR] = { 0x36000 },
  3121. [GCC_TCSR_BCR] = { 0x37000 },
  3122. [GCC_BOOT_ROM_BCR] = { 0x38000 },
  3123. [GCC_MSG_RAM_BCR] = { 0x39000 },
  3124. [GCC_TLMM_BCR] = { 0x3a000 },
  3125. [GCC_MPM_BCR] = { 0x3b000 },
  3126. [GCC_SEC_CTRL_BCR] = { 0x3d000 },
  3127. [GCC_SPMI_BCR] = { 0x3f000 },
  3128. [GCC_SPDM_BCR] = { 0x40000 },
  3129. [GCC_CE1_BCR] = { 0x41000 },
  3130. [GCC_BIMC_BCR] = { 0x44000 },
  3131. [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
  3132. [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
  3133. [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
  3134. [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
  3135. [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
  3136. [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
  3137. [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
  3138. [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
  3139. [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
  3140. [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
  3141. [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
  3142. [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
  3143. [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
  3144. [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
  3145. [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
  3146. [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
  3147. [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
  3148. [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
  3149. [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
  3150. [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
  3151. [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
  3152. [GCC_APB2JTAG_BCR] = { 0x4c000 },
  3153. [GCC_RBCPR_CX_BCR] = { 0x4e000 },
  3154. [GCC_RBCPR_MX_BCR] = { 0x4f000 },
  3155. [GCC_PCIE_0_BCR] = { 0x6b000 },
  3156. [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
  3157. [GCC_PCIE_1_BCR] = { 0x6d000 },
  3158. [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
  3159. [GCC_PCIE_2_BCR] = { 0x6e000 },
  3160. [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
  3161. [GCC_PCIE_PHY_BCR] = { 0x6f000 },
  3162. [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
  3163. [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
  3164. [GCC_DCD_BCR] = { 0x70000 },
  3165. [GCC_OBT_ODT_BCR] = { 0x73000 },
  3166. [GCC_UFS_BCR] = { 0x75000 },
  3167. [GCC_SSC_BCR] = { 0x63000 },
  3168. [GCC_VS_BCR] = { 0x7a000 },
  3169. [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
  3170. [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
  3171. [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
  3172. [GCC_DCC_BCR] = { 0x84000 },
  3173. [GCC_IPA_BCR] = { 0x89000 },
  3174. [GCC_QSPI_BCR] = { 0x8b000 },
  3175. [GCC_SKL_BCR] = { 0x8c000 },
  3176. [GCC_MSMPU_BCR] = { 0x8d000 },
  3177. [GCC_MSS_Q6_BCR] = { 0x8e000 },
  3178. [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
  3179. };
  3180. static const struct regmap_config gcc_msm8996_regmap_config = {
  3181. .reg_bits = 32,
  3182. .reg_stride = 4,
  3183. .val_bits = 32,
  3184. .max_register = 0x8f010,
  3185. .fast_io = true,
  3186. };
  3187. static const struct qcom_cc_desc gcc_msm8996_desc = {
  3188. .config = &gcc_msm8996_regmap_config,
  3189. .clks = gcc_msm8996_clocks,
  3190. .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
  3191. .resets = gcc_msm8996_resets,
  3192. .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
  3193. .gdscs = gcc_msm8996_gdscs,
  3194. .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
  3195. };
  3196. static const struct of_device_id gcc_msm8996_match_table[] = {
  3197. { .compatible = "qcom,gcc-msm8996" },
  3198. { }
  3199. };
  3200. MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
  3201. static int gcc_msm8996_probe(struct platform_device *pdev)
  3202. {
  3203. struct device *dev = &pdev->dev;
  3204. int i, ret;
  3205. struct regmap *regmap;
  3206. regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
  3207. if (IS_ERR(regmap))
  3208. return PTR_ERR(regmap);
  3209. /*
  3210. * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
  3211. * turned off by hardware during certain apps low power modes.
  3212. */
  3213. regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
  3214. for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
  3215. ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
  3216. if (ret)
  3217. return ret;
  3218. }
  3219. return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
  3220. }
  3221. static struct platform_driver gcc_msm8996_driver = {
  3222. .probe = gcc_msm8996_probe,
  3223. .driver = {
  3224. .name = "gcc-msm8996",
  3225. .of_match_table = gcc_msm8996_match_table,
  3226. },
  3227. };
  3228. static int __init gcc_msm8996_init(void)
  3229. {
  3230. return platform_driver_register(&gcc_msm8996_driver);
  3231. }
  3232. core_initcall(gcc_msm8996_init);
  3233. static void __exit gcc_msm8996_exit(void)
  3234. {
  3235. platform_driver_unregister(&gcc_msm8996_driver);
  3236. }
  3237. module_exit(gcc_msm8996_exit);
  3238. MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
  3239. MODULE_LICENSE("GPL v2");
  3240. MODULE_ALIAS("platform:gcc-msm8996");