gcc-ipq806x.c 65 KB

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  1. /*
  2. * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/bitops.h>
  15. #include <linux/err.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/clk-provider.h>
  21. #include <linux/regmap.h>
  22. #include <linux/reset-controller.h>
  23. #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  24. #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  25. #include "common.h"
  26. #include "clk-regmap.h"
  27. #include "clk-pll.h"
  28. #include "clk-rcg.h"
  29. #include "clk-branch.h"
  30. #include "reset.h"
  31. static struct clk_pll pll0 = {
  32. .l_reg = 0x30c4,
  33. .m_reg = 0x30c8,
  34. .n_reg = 0x30cc,
  35. .config_reg = 0x30d4,
  36. .mode_reg = 0x30c0,
  37. .status_reg = 0x30d8,
  38. .status_bit = 16,
  39. .clkr.hw.init = &(struct clk_init_data){
  40. .name = "pll0",
  41. .parent_names = (const char *[]){ "pxo" },
  42. .num_parents = 1,
  43. .ops = &clk_pll_ops,
  44. },
  45. };
  46. static struct clk_regmap pll0_vote = {
  47. .enable_reg = 0x34c0,
  48. .enable_mask = BIT(0),
  49. .hw.init = &(struct clk_init_data){
  50. .name = "pll0_vote",
  51. .parent_names = (const char *[]){ "pll0" },
  52. .num_parents = 1,
  53. .ops = &clk_pll_vote_ops,
  54. },
  55. };
  56. static struct clk_pll pll3 = {
  57. .l_reg = 0x3164,
  58. .m_reg = 0x3168,
  59. .n_reg = 0x316c,
  60. .config_reg = 0x3174,
  61. .mode_reg = 0x3160,
  62. .status_reg = 0x3178,
  63. .status_bit = 16,
  64. .clkr.hw.init = &(struct clk_init_data){
  65. .name = "pll3",
  66. .parent_names = (const char *[]){ "pxo" },
  67. .num_parents = 1,
  68. .ops = &clk_pll_ops,
  69. },
  70. };
  71. static struct clk_regmap pll4_vote = {
  72. .enable_reg = 0x34c0,
  73. .enable_mask = BIT(4),
  74. .hw.init = &(struct clk_init_data){
  75. .name = "pll4_vote",
  76. .parent_names = (const char *[]){ "pll4" },
  77. .num_parents = 1,
  78. .ops = &clk_pll_vote_ops,
  79. },
  80. };
  81. static struct clk_pll pll8 = {
  82. .l_reg = 0x3144,
  83. .m_reg = 0x3148,
  84. .n_reg = 0x314c,
  85. .config_reg = 0x3154,
  86. .mode_reg = 0x3140,
  87. .status_reg = 0x3158,
  88. .status_bit = 16,
  89. .clkr.hw.init = &(struct clk_init_data){
  90. .name = "pll8",
  91. .parent_names = (const char *[]){ "pxo" },
  92. .num_parents = 1,
  93. .ops = &clk_pll_ops,
  94. },
  95. };
  96. static struct clk_regmap pll8_vote = {
  97. .enable_reg = 0x34c0,
  98. .enable_mask = BIT(8),
  99. .hw.init = &(struct clk_init_data){
  100. .name = "pll8_vote",
  101. .parent_names = (const char *[]){ "pll8" },
  102. .num_parents = 1,
  103. .ops = &clk_pll_vote_ops,
  104. },
  105. };
  106. static struct clk_pll pll14 = {
  107. .l_reg = 0x31c4,
  108. .m_reg = 0x31c8,
  109. .n_reg = 0x31cc,
  110. .config_reg = 0x31d4,
  111. .mode_reg = 0x31c0,
  112. .status_reg = 0x31d8,
  113. .status_bit = 16,
  114. .clkr.hw.init = &(struct clk_init_data){
  115. .name = "pll14",
  116. .parent_names = (const char *[]){ "pxo" },
  117. .num_parents = 1,
  118. .ops = &clk_pll_ops,
  119. },
  120. };
  121. static struct clk_regmap pll14_vote = {
  122. .enable_reg = 0x34c0,
  123. .enable_mask = BIT(14),
  124. .hw.init = &(struct clk_init_data){
  125. .name = "pll14_vote",
  126. .parent_names = (const char *[]){ "pll14" },
  127. .num_parents = 1,
  128. .ops = &clk_pll_vote_ops,
  129. },
  130. };
  131. #define NSS_PLL_RATE(f, _l, _m, _n, i) \
  132. { \
  133. .freq = f, \
  134. .l = _l, \
  135. .m = _m, \
  136. .n = _n, \
  137. .ibits = i, \
  138. }
  139. static struct pll_freq_tbl pll18_freq_tbl[] = {
  140. NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
  141. NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
  142. };
  143. static struct clk_pll pll18 = {
  144. .l_reg = 0x31a4,
  145. .m_reg = 0x31a8,
  146. .n_reg = 0x31ac,
  147. .config_reg = 0x31b4,
  148. .mode_reg = 0x31a0,
  149. .status_reg = 0x31b8,
  150. .status_bit = 16,
  151. .post_div_shift = 16,
  152. .post_div_width = 1,
  153. .freq_tbl = pll18_freq_tbl,
  154. .clkr.hw.init = &(struct clk_init_data){
  155. .name = "pll18",
  156. .parent_names = (const char *[]){ "pxo" },
  157. .num_parents = 1,
  158. .ops = &clk_pll_ops,
  159. },
  160. };
  161. enum {
  162. P_PXO,
  163. P_PLL8,
  164. P_PLL3,
  165. P_PLL0,
  166. P_CXO,
  167. P_PLL14,
  168. P_PLL18,
  169. };
  170. static const struct parent_map gcc_pxo_pll8_map[] = {
  171. { P_PXO, 0 },
  172. { P_PLL8, 3 }
  173. };
  174. static const char * const gcc_pxo_pll8[] = {
  175. "pxo",
  176. "pll8_vote",
  177. };
  178. static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
  179. { P_PXO, 0 },
  180. { P_PLL8, 3 },
  181. { P_CXO, 5 }
  182. };
  183. static const char * const gcc_pxo_pll8_cxo[] = {
  184. "pxo",
  185. "pll8_vote",
  186. "cxo",
  187. };
  188. static const struct parent_map gcc_pxo_pll3_map[] = {
  189. { P_PXO, 0 },
  190. { P_PLL3, 1 }
  191. };
  192. static const struct parent_map gcc_pxo_pll3_sata_map[] = {
  193. { P_PXO, 0 },
  194. { P_PLL3, 6 }
  195. };
  196. static const char * const gcc_pxo_pll3[] = {
  197. "pxo",
  198. "pll3",
  199. };
  200. static const struct parent_map gcc_pxo_pll8_pll0[] = {
  201. { P_PXO, 0 },
  202. { P_PLL8, 3 },
  203. { P_PLL0, 2 }
  204. };
  205. static const char * const gcc_pxo_pll8_pll0_map[] = {
  206. "pxo",
  207. "pll8_vote",
  208. "pll0_vote",
  209. };
  210. static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
  211. { P_PXO, 0 },
  212. { P_PLL8, 4 },
  213. { P_PLL0, 2 },
  214. { P_PLL14, 5 },
  215. { P_PLL18, 1 }
  216. };
  217. static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
  218. "pxo",
  219. "pll8_vote",
  220. "pll0_vote",
  221. "pll14",
  222. "pll18",
  223. };
  224. static struct freq_tbl clk_tbl_gsbi_uart[] = {
  225. { 1843200, P_PLL8, 2, 6, 625 },
  226. { 3686400, P_PLL8, 2, 12, 625 },
  227. { 7372800, P_PLL8, 2, 24, 625 },
  228. { 14745600, P_PLL8, 2, 48, 625 },
  229. { 16000000, P_PLL8, 4, 1, 6 },
  230. { 24000000, P_PLL8, 4, 1, 4 },
  231. { 32000000, P_PLL8, 4, 1, 3 },
  232. { 40000000, P_PLL8, 1, 5, 48 },
  233. { 46400000, P_PLL8, 1, 29, 240 },
  234. { 48000000, P_PLL8, 4, 1, 2 },
  235. { 51200000, P_PLL8, 1, 2, 15 },
  236. { 56000000, P_PLL8, 1, 7, 48 },
  237. { 58982400, P_PLL8, 1, 96, 625 },
  238. { 64000000, P_PLL8, 2, 1, 3 },
  239. { }
  240. };
  241. static struct clk_rcg gsbi1_uart_src = {
  242. .ns_reg = 0x29d4,
  243. .md_reg = 0x29d0,
  244. .mn = {
  245. .mnctr_en_bit = 8,
  246. .mnctr_reset_bit = 7,
  247. .mnctr_mode_shift = 5,
  248. .n_val_shift = 16,
  249. .m_val_shift = 16,
  250. .width = 16,
  251. },
  252. .p = {
  253. .pre_div_shift = 3,
  254. .pre_div_width = 2,
  255. },
  256. .s = {
  257. .src_sel_shift = 0,
  258. .parent_map = gcc_pxo_pll8_map,
  259. },
  260. .freq_tbl = clk_tbl_gsbi_uart,
  261. .clkr = {
  262. .enable_reg = 0x29d4,
  263. .enable_mask = BIT(11),
  264. .hw.init = &(struct clk_init_data){
  265. .name = "gsbi1_uart_src",
  266. .parent_names = gcc_pxo_pll8,
  267. .num_parents = 2,
  268. .ops = &clk_rcg_ops,
  269. .flags = CLK_SET_PARENT_GATE,
  270. },
  271. },
  272. };
  273. static struct clk_branch gsbi1_uart_clk = {
  274. .halt_reg = 0x2fcc,
  275. .halt_bit = 12,
  276. .clkr = {
  277. .enable_reg = 0x29d4,
  278. .enable_mask = BIT(9),
  279. .hw.init = &(struct clk_init_data){
  280. .name = "gsbi1_uart_clk",
  281. .parent_names = (const char *[]){
  282. "gsbi1_uart_src",
  283. },
  284. .num_parents = 1,
  285. .ops = &clk_branch_ops,
  286. .flags = CLK_SET_RATE_PARENT,
  287. },
  288. },
  289. };
  290. static struct clk_rcg gsbi2_uart_src = {
  291. .ns_reg = 0x29f4,
  292. .md_reg = 0x29f0,
  293. .mn = {
  294. .mnctr_en_bit = 8,
  295. .mnctr_reset_bit = 7,
  296. .mnctr_mode_shift = 5,
  297. .n_val_shift = 16,
  298. .m_val_shift = 16,
  299. .width = 16,
  300. },
  301. .p = {
  302. .pre_div_shift = 3,
  303. .pre_div_width = 2,
  304. },
  305. .s = {
  306. .src_sel_shift = 0,
  307. .parent_map = gcc_pxo_pll8_map,
  308. },
  309. .freq_tbl = clk_tbl_gsbi_uart,
  310. .clkr = {
  311. .enable_reg = 0x29f4,
  312. .enable_mask = BIT(11),
  313. .hw.init = &(struct clk_init_data){
  314. .name = "gsbi2_uart_src",
  315. .parent_names = gcc_pxo_pll8,
  316. .num_parents = 2,
  317. .ops = &clk_rcg_ops,
  318. .flags = CLK_SET_PARENT_GATE,
  319. },
  320. },
  321. };
  322. static struct clk_branch gsbi2_uart_clk = {
  323. .halt_reg = 0x2fcc,
  324. .halt_bit = 8,
  325. .clkr = {
  326. .enable_reg = 0x29f4,
  327. .enable_mask = BIT(9),
  328. .hw.init = &(struct clk_init_data){
  329. .name = "gsbi2_uart_clk",
  330. .parent_names = (const char *[]){
  331. "gsbi2_uart_src",
  332. },
  333. .num_parents = 1,
  334. .ops = &clk_branch_ops,
  335. .flags = CLK_SET_RATE_PARENT,
  336. },
  337. },
  338. };
  339. static struct clk_rcg gsbi4_uart_src = {
  340. .ns_reg = 0x2a34,
  341. .md_reg = 0x2a30,
  342. .mn = {
  343. .mnctr_en_bit = 8,
  344. .mnctr_reset_bit = 7,
  345. .mnctr_mode_shift = 5,
  346. .n_val_shift = 16,
  347. .m_val_shift = 16,
  348. .width = 16,
  349. },
  350. .p = {
  351. .pre_div_shift = 3,
  352. .pre_div_width = 2,
  353. },
  354. .s = {
  355. .src_sel_shift = 0,
  356. .parent_map = gcc_pxo_pll8_map,
  357. },
  358. .freq_tbl = clk_tbl_gsbi_uart,
  359. .clkr = {
  360. .enable_reg = 0x2a34,
  361. .enable_mask = BIT(11),
  362. .hw.init = &(struct clk_init_data){
  363. .name = "gsbi4_uart_src",
  364. .parent_names = gcc_pxo_pll8,
  365. .num_parents = 2,
  366. .ops = &clk_rcg_ops,
  367. .flags = CLK_SET_PARENT_GATE,
  368. },
  369. },
  370. };
  371. static struct clk_branch gsbi4_uart_clk = {
  372. .halt_reg = 0x2fd0,
  373. .halt_bit = 26,
  374. .clkr = {
  375. .enable_reg = 0x2a34,
  376. .enable_mask = BIT(9),
  377. .hw.init = &(struct clk_init_data){
  378. .name = "gsbi4_uart_clk",
  379. .parent_names = (const char *[]){
  380. "gsbi4_uart_src",
  381. },
  382. .num_parents = 1,
  383. .ops = &clk_branch_ops,
  384. .flags = CLK_SET_RATE_PARENT,
  385. },
  386. },
  387. };
  388. static struct clk_rcg gsbi5_uart_src = {
  389. .ns_reg = 0x2a54,
  390. .md_reg = 0x2a50,
  391. .mn = {
  392. .mnctr_en_bit = 8,
  393. .mnctr_reset_bit = 7,
  394. .mnctr_mode_shift = 5,
  395. .n_val_shift = 16,
  396. .m_val_shift = 16,
  397. .width = 16,
  398. },
  399. .p = {
  400. .pre_div_shift = 3,
  401. .pre_div_width = 2,
  402. },
  403. .s = {
  404. .src_sel_shift = 0,
  405. .parent_map = gcc_pxo_pll8_map,
  406. },
  407. .freq_tbl = clk_tbl_gsbi_uart,
  408. .clkr = {
  409. .enable_reg = 0x2a54,
  410. .enable_mask = BIT(11),
  411. .hw.init = &(struct clk_init_data){
  412. .name = "gsbi5_uart_src",
  413. .parent_names = gcc_pxo_pll8,
  414. .num_parents = 2,
  415. .ops = &clk_rcg_ops,
  416. .flags = CLK_SET_PARENT_GATE,
  417. },
  418. },
  419. };
  420. static struct clk_branch gsbi5_uart_clk = {
  421. .halt_reg = 0x2fd0,
  422. .halt_bit = 22,
  423. .clkr = {
  424. .enable_reg = 0x2a54,
  425. .enable_mask = BIT(9),
  426. .hw.init = &(struct clk_init_data){
  427. .name = "gsbi5_uart_clk",
  428. .parent_names = (const char *[]){
  429. "gsbi5_uart_src",
  430. },
  431. .num_parents = 1,
  432. .ops = &clk_branch_ops,
  433. .flags = CLK_SET_RATE_PARENT,
  434. },
  435. },
  436. };
  437. static struct clk_rcg gsbi6_uart_src = {
  438. .ns_reg = 0x2a74,
  439. .md_reg = 0x2a70,
  440. .mn = {
  441. .mnctr_en_bit = 8,
  442. .mnctr_reset_bit = 7,
  443. .mnctr_mode_shift = 5,
  444. .n_val_shift = 16,
  445. .m_val_shift = 16,
  446. .width = 16,
  447. },
  448. .p = {
  449. .pre_div_shift = 3,
  450. .pre_div_width = 2,
  451. },
  452. .s = {
  453. .src_sel_shift = 0,
  454. .parent_map = gcc_pxo_pll8_map,
  455. },
  456. .freq_tbl = clk_tbl_gsbi_uart,
  457. .clkr = {
  458. .enable_reg = 0x2a74,
  459. .enable_mask = BIT(11),
  460. .hw.init = &(struct clk_init_data){
  461. .name = "gsbi6_uart_src",
  462. .parent_names = gcc_pxo_pll8,
  463. .num_parents = 2,
  464. .ops = &clk_rcg_ops,
  465. .flags = CLK_SET_PARENT_GATE,
  466. },
  467. },
  468. };
  469. static struct clk_branch gsbi6_uart_clk = {
  470. .halt_reg = 0x2fd0,
  471. .halt_bit = 18,
  472. .clkr = {
  473. .enable_reg = 0x2a74,
  474. .enable_mask = BIT(9),
  475. .hw.init = &(struct clk_init_data){
  476. .name = "gsbi6_uart_clk",
  477. .parent_names = (const char *[]){
  478. "gsbi6_uart_src",
  479. },
  480. .num_parents = 1,
  481. .ops = &clk_branch_ops,
  482. .flags = CLK_SET_RATE_PARENT,
  483. },
  484. },
  485. };
  486. static struct clk_rcg gsbi7_uart_src = {
  487. .ns_reg = 0x2a94,
  488. .md_reg = 0x2a90,
  489. .mn = {
  490. .mnctr_en_bit = 8,
  491. .mnctr_reset_bit = 7,
  492. .mnctr_mode_shift = 5,
  493. .n_val_shift = 16,
  494. .m_val_shift = 16,
  495. .width = 16,
  496. },
  497. .p = {
  498. .pre_div_shift = 3,
  499. .pre_div_width = 2,
  500. },
  501. .s = {
  502. .src_sel_shift = 0,
  503. .parent_map = gcc_pxo_pll8_map,
  504. },
  505. .freq_tbl = clk_tbl_gsbi_uart,
  506. .clkr = {
  507. .enable_reg = 0x2a94,
  508. .enable_mask = BIT(11),
  509. .hw.init = &(struct clk_init_data){
  510. .name = "gsbi7_uart_src",
  511. .parent_names = gcc_pxo_pll8,
  512. .num_parents = 2,
  513. .ops = &clk_rcg_ops,
  514. .flags = CLK_SET_PARENT_GATE,
  515. },
  516. },
  517. };
  518. static struct clk_branch gsbi7_uart_clk = {
  519. .halt_reg = 0x2fd0,
  520. .halt_bit = 14,
  521. .clkr = {
  522. .enable_reg = 0x2a94,
  523. .enable_mask = BIT(9),
  524. .hw.init = &(struct clk_init_data){
  525. .name = "gsbi7_uart_clk",
  526. .parent_names = (const char *[]){
  527. "gsbi7_uart_src",
  528. },
  529. .num_parents = 1,
  530. .ops = &clk_branch_ops,
  531. .flags = CLK_SET_RATE_PARENT,
  532. },
  533. },
  534. };
  535. static struct freq_tbl clk_tbl_gsbi_qup[] = {
  536. { 1100000, P_PXO, 1, 2, 49 },
  537. { 5400000, P_PXO, 1, 1, 5 },
  538. { 10800000, P_PXO, 1, 2, 5 },
  539. { 15060000, P_PLL8, 1, 2, 51 },
  540. { 24000000, P_PLL8, 4, 1, 4 },
  541. { 25000000, P_PXO, 1, 0, 0 },
  542. { 25600000, P_PLL8, 1, 1, 15 },
  543. { 48000000, P_PLL8, 4, 1, 2 },
  544. { 51200000, P_PLL8, 1, 2, 15 },
  545. { }
  546. };
  547. static struct clk_rcg gsbi1_qup_src = {
  548. .ns_reg = 0x29cc,
  549. .md_reg = 0x29c8,
  550. .mn = {
  551. .mnctr_en_bit = 8,
  552. .mnctr_reset_bit = 7,
  553. .mnctr_mode_shift = 5,
  554. .n_val_shift = 16,
  555. .m_val_shift = 16,
  556. .width = 8,
  557. },
  558. .p = {
  559. .pre_div_shift = 3,
  560. .pre_div_width = 2,
  561. },
  562. .s = {
  563. .src_sel_shift = 0,
  564. .parent_map = gcc_pxo_pll8_map,
  565. },
  566. .freq_tbl = clk_tbl_gsbi_qup,
  567. .clkr = {
  568. .enable_reg = 0x29cc,
  569. .enable_mask = BIT(11),
  570. .hw.init = &(struct clk_init_data){
  571. .name = "gsbi1_qup_src",
  572. .parent_names = gcc_pxo_pll8,
  573. .num_parents = 2,
  574. .ops = &clk_rcg_ops,
  575. .flags = CLK_SET_PARENT_GATE,
  576. },
  577. },
  578. };
  579. static struct clk_branch gsbi1_qup_clk = {
  580. .halt_reg = 0x2fcc,
  581. .halt_bit = 11,
  582. .clkr = {
  583. .enable_reg = 0x29cc,
  584. .enable_mask = BIT(9),
  585. .hw.init = &(struct clk_init_data){
  586. .name = "gsbi1_qup_clk",
  587. .parent_names = (const char *[]){ "gsbi1_qup_src" },
  588. .num_parents = 1,
  589. .ops = &clk_branch_ops,
  590. .flags = CLK_SET_RATE_PARENT,
  591. },
  592. },
  593. };
  594. static struct clk_rcg gsbi2_qup_src = {
  595. .ns_reg = 0x29ec,
  596. .md_reg = 0x29e8,
  597. .mn = {
  598. .mnctr_en_bit = 8,
  599. .mnctr_reset_bit = 7,
  600. .mnctr_mode_shift = 5,
  601. .n_val_shift = 16,
  602. .m_val_shift = 16,
  603. .width = 8,
  604. },
  605. .p = {
  606. .pre_div_shift = 3,
  607. .pre_div_width = 2,
  608. },
  609. .s = {
  610. .src_sel_shift = 0,
  611. .parent_map = gcc_pxo_pll8_map,
  612. },
  613. .freq_tbl = clk_tbl_gsbi_qup,
  614. .clkr = {
  615. .enable_reg = 0x29ec,
  616. .enable_mask = BIT(11),
  617. .hw.init = &(struct clk_init_data){
  618. .name = "gsbi2_qup_src",
  619. .parent_names = gcc_pxo_pll8,
  620. .num_parents = 2,
  621. .ops = &clk_rcg_ops,
  622. .flags = CLK_SET_PARENT_GATE,
  623. },
  624. },
  625. };
  626. static struct clk_branch gsbi2_qup_clk = {
  627. .halt_reg = 0x2fcc,
  628. .halt_bit = 6,
  629. .clkr = {
  630. .enable_reg = 0x29ec,
  631. .enable_mask = BIT(9),
  632. .hw.init = &(struct clk_init_data){
  633. .name = "gsbi2_qup_clk",
  634. .parent_names = (const char *[]){ "gsbi2_qup_src" },
  635. .num_parents = 1,
  636. .ops = &clk_branch_ops,
  637. .flags = CLK_SET_RATE_PARENT,
  638. },
  639. },
  640. };
  641. static struct clk_rcg gsbi4_qup_src = {
  642. .ns_reg = 0x2a2c,
  643. .md_reg = 0x2a28,
  644. .mn = {
  645. .mnctr_en_bit = 8,
  646. .mnctr_reset_bit = 7,
  647. .mnctr_mode_shift = 5,
  648. .n_val_shift = 16,
  649. .m_val_shift = 16,
  650. .width = 8,
  651. },
  652. .p = {
  653. .pre_div_shift = 3,
  654. .pre_div_width = 2,
  655. },
  656. .s = {
  657. .src_sel_shift = 0,
  658. .parent_map = gcc_pxo_pll8_map,
  659. },
  660. .freq_tbl = clk_tbl_gsbi_qup,
  661. .clkr = {
  662. .enable_reg = 0x2a2c,
  663. .enable_mask = BIT(11),
  664. .hw.init = &(struct clk_init_data){
  665. .name = "gsbi4_qup_src",
  666. .parent_names = gcc_pxo_pll8,
  667. .num_parents = 2,
  668. .ops = &clk_rcg_ops,
  669. .flags = CLK_SET_PARENT_GATE,
  670. },
  671. },
  672. };
  673. static struct clk_branch gsbi4_qup_clk = {
  674. .halt_reg = 0x2fd0,
  675. .halt_bit = 24,
  676. .clkr = {
  677. .enable_reg = 0x2a2c,
  678. .enable_mask = BIT(9),
  679. .hw.init = &(struct clk_init_data){
  680. .name = "gsbi4_qup_clk",
  681. .parent_names = (const char *[]){ "gsbi4_qup_src" },
  682. .num_parents = 1,
  683. .ops = &clk_branch_ops,
  684. .flags = CLK_SET_RATE_PARENT,
  685. },
  686. },
  687. };
  688. static struct clk_rcg gsbi5_qup_src = {
  689. .ns_reg = 0x2a4c,
  690. .md_reg = 0x2a48,
  691. .mn = {
  692. .mnctr_en_bit = 8,
  693. .mnctr_reset_bit = 7,
  694. .mnctr_mode_shift = 5,
  695. .n_val_shift = 16,
  696. .m_val_shift = 16,
  697. .width = 8,
  698. },
  699. .p = {
  700. .pre_div_shift = 3,
  701. .pre_div_width = 2,
  702. },
  703. .s = {
  704. .src_sel_shift = 0,
  705. .parent_map = gcc_pxo_pll8_map,
  706. },
  707. .freq_tbl = clk_tbl_gsbi_qup,
  708. .clkr = {
  709. .enable_reg = 0x2a4c,
  710. .enable_mask = BIT(11),
  711. .hw.init = &(struct clk_init_data){
  712. .name = "gsbi5_qup_src",
  713. .parent_names = gcc_pxo_pll8,
  714. .num_parents = 2,
  715. .ops = &clk_rcg_ops,
  716. .flags = CLK_SET_PARENT_GATE,
  717. },
  718. },
  719. };
  720. static struct clk_branch gsbi5_qup_clk = {
  721. .halt_reg = 0x2fd0,
  722. .halt_bit = 20,
  723. .clkr = {
  724. .enable_reg = 0x2a4c,
  725. .enable_mask = BIT(9),
  726. .hw.init = &(struct clk_init_data){
  727. .name = "gsbi5_qup_clk",
  728. .parent_names = (const char *[]){ "gsbi5_qup_src" },
  729. .num_parents = 1,
  730. .ops = &clk_branch_ops,
  731. .flags = CLK_SET_RATE_PARENT,
  732. },
  733. },
  734. };
  735. static struct clk_rcg gsbi6_qup_src = {
  736. .ns_reg = 0x2a6c,
  737. .md_reg = 0x2a68,
  738. .mn = {
  739. .mnctr_en_bit = 8,
  740. .mnctr_reset_bit = 7,
  741. .mnctr_mode_shift = 5,
  742. .n_val_shift = 16,
  743. .m_val_shift = 16,
  744. .width = 8,
  745. },
  746. .p = {
  747. .pre_div_shift = 3,
  748. .pre_div_width = 2,
  749. },
  750. .s = {
  751. .src_sel_shift = 0,
  752. .parent_map = gcc_pxo_pll8_map,
  753. },
  754. .freq_tbl = clk_tbl_gsbi_qup,
  755. .clkr = {
  756. .enable_reg = 0x2a6c,
  757. .enable_mask = BIT(11),
  758. .hw.init = &(struct clk_init_data){
  759. .name = "gsbi6_qup_src",
  760. .parent_names = gcc_pxo_pll8,
  761. .num_parents = 2,
  762. .ops = &clk_rcg_ops,
  763. .flags = CLK_SET_PARENT_GATE,
  764. },
  765. },
  766. };
  767. static struct clk_branch gsbi6_qup_clk = {
  768. .halt_reg = 0x2fd0,
  769. .halt_bit = 16,
  770. .clkr = {
  771. .enable_reg = 0x2a6c,
  772. .enable_mask = BIT(9),
  773. .hw.init = &(struct clk_init_data){
  774. .name = "gsbi6_qup_clk",
  775. .parent_names = (const char *[]){ "gsbi6_qup_src" },
  776. .num_parents = 1,
  777. .ops = &clk_branch_ops,
  778. .flags = CLK_SET_RATE_PARENT,
  779. },
  780. },
  781. };
  782. static struct clk_rcg gsbi7_qup_src = {
  783. .ns_reg = 0x2a8c,
  784. .md_reg = 0x2a88,
  785. .mn = {
  786. .mnctr_en_bit = 8,
  787. .mnctr_reset_bit = 7,
  788. .mnctr_mode_shift = 5,
  789. .n_val_shift = 16,
  790. .m_val_shift = 16,
  791. .width = 8,
  792. },
  793. .p = {
  794. .pre_div_shift = 3,
  795. .pre_div_width = 2,
  796. },
  797. .s = {
  798. .src_sel_shift = 0,
  799. .parent_map = gcc_pxo_pll8_map,
  800. },
  801. .freq_tbl = clk_tbl_gsbi_qup,
  802. .clkr = {
  803. .enable_reg = 0x2a8c,
  804. .enable_mask = BIT(11),
  805. .hw.init = &(struct clk_init_data){
  806. .name = "gsbi7_qup_src",
  807. .parent_names = gcc_pxo_pll8,
  808. .num_parents = 2,
  809. .ops = &clk_rcg_ops,
  810. .flags = CLK_SET_PARENT_GATE,
  811. },
  812. },
  813. };
  814. static struct clk_branch gsbi7_qup_clk = {
  815. .halt_reg = 0x2fd0,
  816. .halt_bit = 12,
  817. .clkr = {
  818. .enable_reg = 0x2a8c,
  819. .enable_mask = BIT(9),
  820. .hw.init = &(struct clk_init_data){
  821. .name = "gsbi7_qup_clk",
  822. .parent_names = (const char *[]){ "gsbi7_qup_src" },
  823. .num_parents = 1,
  824. .ops = &clk_branch_ops,
  825. .flags = CLK_SET_RATE_PARENT,
  826. },
  827. },
  828. };
  829. static struct clk_branch gsbi1_h_clk = {
  830. .hwcg_reg = 0x29c0,
  831. .hwcg_bit = 6,
  832. .halt_reg = 0x2fcc,
  833. .halt_bit = 13,
  834. .clkr = {
  835. .enable_reg = 0x29c0,
  836. .enable_mask = BIT(4),
  837. .hw.init = &(struct clk_init_data){
  838. .name = "gsbi1_h_clk",
  839. .ops = &clk_branch_ops,
  840. },
  841. },
  842. };
  843. static struct clk_branch gsbi2_h_clk = {
  844. .hwcg_reg = 0x29e0,
  845. .hwcg_bit = 6,
  846. .halt_reg = 0x2fcc,
  847. .halt_bit = 9,
  848. .clkr = {
  849. .enable_reg = 0x29e0,
  850. .enable_mask = BIT(4),
  851. .hw.init = &(struct clk_init_data){
  852. .name = "gsbi2_h_clk",
  853. .ops = &clk_branch_ops,
  854. },
  855. },
  856. };
  857. static struct clk_branch gsbi4_h_clk = {
  858. .hwcg_reg = 0x2a20,
  859. .hwcg_bit = 6,
  860. .halt_reg = 0x2fd0,
  861. .halt_bit = 27,
  862. .clkr = {
  863. .enable_reg = 0x2a20,
  864. .enable_mask = BIT(4),
  865. .hw.init = &(struct clk_init_data){
  866. .name = "gsbi4_h_clk",
  867. .ops = &clk_branch_ops,
  868. },
  869. },
  870. };
  871. static struct clk_branch gsbi5_h_clk = {
  872. .hwcg_reg = 0x2a40,
  873. .hwcg_bit = 6,
  874. .halt_reg = 0x2fd0,
  875. .halt_bit = 23,
  876. .clkr = {
  877. .enable_reg = 0x2a40,
  878. .enable_mask = BIT(4),
  879. .hw.init = &(struct clk_init_data){
  880. .name = "gsbi5_h_clk",
  881. .ops = &clk_branch_ops,
  882. },
  883. },
  884. };
  885. static struct clk_branch gsbi6_h_clk = {
  886. .hwcg_reg = 0x2a60,
  887. .hwcg_bit = 6,
  888. .halt_reg = 0x2fd0,
  889. .halt_bit = 19,
  890. .clkr = {
  891. .enable_reg = 0x2a60,
  892. .enable_mask = BIT(4),
  893. .hw.init = &(struct clk_init_data){
  894. .name = "gsbi6_h_clk",
  895. .ops = &clk_branch_ops,
  896. },
  897. },
  898. };
  899. static struct clk_branch gsbi7_h_clk = {
  900. .hwcg_reg = 0x2a80,
  901. .hwcg_bit = 6,
  902. .halt_reg = 0x2fd0,
  903. .halt_bit = 15,
  904. .clkr = {
  905. .enable_reg = 0x2a80,
  906. .enable_mask = BIT(4),
  907. .hw.init = &(struct clk_init_data){
  908. .name = "gsbi7_h_clk",
  909. .ops = &clk_branch_ops,
  910. },
  911. },
  912. };
  913. static const struct freq_tbl clk_tbl_gp[] = {
  914. { 12500000, P_PXO, 2, 0, 0 },
  915. { 25000000, P_PXO, 1, 0, 0 },
  916. { 64000000, P_PLL8, 2, 1, 3 },
  917. { 76800000, P_PLL8, 1, 1, 5 },
  918. { 96000000, P_PLL8, 4, 0, 0 },
  919. { 128000000, P_PLL8, 3, 0, 0 },
  920. { 192000000, P_PLL8, 2, 0, 0 },
  921. { }
  922. };
  923. static struct clk_rcg gp0_src = {
  924. .ns_reg = 0x2d24,
  925. .md_reg = 0x2d00,
  926. .mn = {
  927. .mnctr_en_bit = 8,
  928. .mnctr_reset_bit = 7,
  929. .mnctr_mode_shift = 5,
  930. .n_val_shift = 16,
  931. .m_val_shift = 16,
  932. .width = 8,
  933. },
  934. .p = {
  935. .pre_div_shift = 3,
  936. .pre_div_width = 2,
  937. },
  938. .s = {
  939. .src_sel_shift = 0,
  940. .parent_map = gcc_pxo_pll8_cxo_map,
  941. },
  942. .freq_tbl = clk_tbl_gp,
  943. .clkr = {
  944. .enable_reg = 0x2d24,
  945. .enable_mask = BIT(11),
  946. .hw.init = &(struct clk_init_data){
  947. .name = "gp0_src",
  948. .parent_names = gcc_pxo_pll8_cxo,
  949. .num_parents = 3,
  950. .ops = &clk_rcg_ops,
  951. .flags = CLK_SET_PARENT_GATE,
  952. },
  953. }
  954. };
  955. static struct clk_branch gp0_clk = {
  956. .halt_reg = 0x2fd8,
  957. .halt_bit = 7,
  958. .clkr = {
  959. .enable_reg = 0x2d24,
  960. .enable_mask = BIT(9),
  961. .hw.init = &(struct clk_init_data){
  962. .name = "gp0_clk",
  963. .parent_names = (const char *[]){ "gp0_src" },
  964. .num_parents = 1,
  965. .ops = &clk_branch_ops,
  966. .flags = CLK_SET_RATE_PARENT,
  967. },
  968. },
  969. };
  970. static struct clk_rcg gp1_src = {
  971. .ns_reg = 0x2d44,
  972. .md_reg = 0x2d40,
  973. .mn = {
  974. .mnctr_en_bit = 8,
  975. .mnctr_reset_bit = 7,
  976. .mnctr_mode_shift = 5,
  977. .n_val_shift = 16,
  978. .m_val_shift = 16,
  979. .width = 8,
  980. },
  981. .p = {
  982. .pre_div_shift = 3,
  983. .pre_div_width = 2,
  984. },
  985. .s = {
  986. .src_sel_shift = 0,
  987. .parent_map = gcc_pxo_pll8_cxo_map,
  988. },
  989. .freq_tbl = clk_tbl_gp,
  990. .clkr = {
  991. .enable_reg = 0x2d44,
  992. .enable_mask = BIT(11),
  993. .hw.init = &(struct clk_init_data){
  994. .name = "gp1_src",
  995. .parent_names = gcc_pxo_pll8_cxo,
  996. .num_parents = 3,
  997. .ops = &clk_rcg_ops,
  998. .flags = CLK_SET_RATE_GATE,
  999. },
  1000. }
  1001. };
  1002. static struct clk_branch gp1_clk = {
  1003. .halt_reg = 0x2fd8,
  1004. .halt_bit = 6,
  1005. .clkr = {
  1006. .enable_reg = 0x2d44,
  1007. .enable_mask = BIT(9),
  1008. .hw.init = &(struct clk_init_data){
  1009. .name = "gp1_clk",
  1010. .parent_names = (const char *[]){ "gp1_src" },
  1011. .num_parents = 1,
  1012. .ops = &clk_branch_ops,
  1013. .flags = CLK_SET_RATE_PARENT,
  1014. },
  1015. },
  1016. };
  1017. static struct clk_rcg gp2_src = {
  1018. .ns_reg = 0x2d64,
  1019. .md_reg = 0x2d60,
  1020. .mn = {
  1021. .mnctr_en_bit = 8,
  1022. .mnctr_reset_bit = 7,
  1023. .mnctr_mode_shift = 5,
  1024. .n_val_shift = 16,
  1025. .m_val_shift = 16,
  1026. .width = 8,
  1027. },
  1028. .p = {
  1029. .pre_div_shift = 3,
  1030. .pre_div_width = 2,
  1031. },
  1032. .s = {
  1033. .src_sel_shift = 0,
  1034. .parent_map = gcc_pxo_pll8_cxo_map,
  1035. },
  1036. .freq_tbl = clk_tbl_gp,
  1037. .clkr = {
  1038. .enable_reg = 0x2d64,
  1039. .enable_mask = BIT(11),
  1040. .hw.init = &(struct clk_init_data){
  1041. .name = "gp2_src",
  1042. .parent_names = gcc_pxo_pll8_cxo,
  1043. .num_parents = 3,
  1044. .ops = &clk_rcg_ops,
  1045. .flags = CLK_SET_RATE_GATE,
  1046. },
  1047. }
  1048. };
  1049. static struct clk_branch gp2_clk = {
  1050. .halt_reg = 0x2fd8,
  1051. .halt_bit = 5,
  1052. .clkr = {
  1053. .enable_reg = 0x2d64,
  1054. .enable_mask = BIT(9),
  1055. .hw.init = &(struct clk_init_data){
  1056. .name = "gp2_clk",
  1057. .parent_names = (const char *[]){ "gp2_src" },
  1058. .num_parents = 1,
  1059. .ops = &clk_branch_ops,
  1060. .flags = CLK_SET_RATE_PARENT,
  1061. },
  1062. },
  1063. };
  1064. static struct clk_branch pmem_clk = {
  1065. .hwcg_reg = 0x25a0,
  1066. .hwcg_bit = 6,
  1067. .halt_reg = 0x2fc8,
  1068. .halt_bit = 20,
  1069. .clkr = {
  1070. .enable_reg = 0x25a0,
  1071. .enable_mask = BIT(4),
  1072. .hw.init = &(struct clk_init_data){
  1073. .name = "pmem_clk",
  1074. .ops = &clk_branch_ops,
  1075. },
  1076. },
  1077. };
  1078. static struct clk_rcg prng_src = {
  1079. .ns_reg = 0x2e80,
  1080. .p = {
  1081. .pre_div_shift = 3,
  1082. .pre_div_width = 4,
  1083. },
  1084. .s = {
  1085. .src_sel_shift = 0,
  1086. .parent_map = gcc_pxo_pll8_map,
  1087. },
  1088. .clkr = {
  1089. .hw.init = &(struct clk_init_data){
  1090. .name = "prng_src",
  1091. .parent_names = gcc_pxo_pll8,
  1092. .num_parents = 2,
  1093. .ops = &clk_rcg_ops,
  1094. },
  1095. },
  1096. };
  1097. static struct clk_branch prng_clk = {
  1098. .halt_reg = 0x2fd8,
  1099. .halt_check = BRANCH_HALT_VOTED,
  1100. .halt_bit = 10,
  1101. .clkr = {
  1102. .enable_reg = 0x3080,
  1103. .enable_mask = BIT(10),
  1104. .hw.init = &(struct clk_init_data){
  1105. .name = "prng_clk",
  1106. .parent_names = (const char *[]){ "prng_src" },
  1107. .num_parents = 1,
  1108. .ops = &clk_branch_ops,
  1109. },
  1110. },
  1111. };
  1112. static const struct freq_tbl clk_tbl_sdc[] = {
  1113. { 200000, P_PXO, 2, 2, 125 },
  1114. { 400000, P_PLL8, 4, 1, 240 },
  1115. { 16000000, P_PLL8, 4, 1, 6 },
  1116. { 17070000, P_PLL8, 1, 2, 45 },
  1117. { 20210000, P_PLL8, 1, 1, 19 },
  1118. { 24000000, P_PLL8, 4, 1, 4 },
  1119. { 48000000, P_PLL8, 4, 1, 2 },
  1120. { 64000000, P_PLL8, 3, 1, 2 },
  1121. { 96000000, P_PLL8, 4, 0, 0 },
  1122. { 192000000, P_PLL8, 2, 0, 0 },
  1123. { }
  1124. };
  1125. static struct clk_rcg sdc1_src = {
  1126. .ns_reg = 0x282c,
  1127. .md_reg = 0x2828,
  1128. .mn = {
  1129. .mnctr_en_bit = 8,
  1130. .mnctr_reset_bit = 7,
  1131. .mnctr_mode_shift = 5,
  1132. .n_val_shift = 16,
  1133. .m_val_shift = 16,
  1134. .width = 8,
  1135. },
  1136. .p = {
  1137. .pre_div_shift = 3,
  1138. .pre_div_width = 2,
  1139. },
  1140. .s = {
  1141. .src_sel_shift = 0,
  1142. .parent_map = gcc_pxo_pll8_map,
  1143. },
  1144. .freq_tbl = clk_tbl_sdc,
  1145. .clkr = {
  1146. .enable_reg = 0x282c,
  1147. .enable_mask = BIT(11),
  1148. .hw.init = &(struct clk_init_data){
  1149. .name = "sdc1_src",
  1150. .parent_names = gcc_pxo_pll8,
  1151. .num_parents = 2,
  1152. .ops = &clk_rcg_ops,
  1153. .flags = CLK_SET_RATE_GATE,
  1154. },
  1155. }
  1156. };
  1157. static struct clk_branch sdc1_clk = {
  1158. .halt_reg = 0x2fc8,
  1159. .halt_bit = 6,
  1160. .clkr = {
  1161. .enable_reg = 0x282c,
  1162. .enable_mask = BIT(9),
  1163. .hw.init = &(struct clk_init_data){
  1164. .name = "sdc1_clk",
  1165. .parent_names = (const char *[]){ "sdc1_src" },
  1166. .num_parents = 1,
  1167. .ops = &clk_branch_ops,
  1168. .flags = CLK_SET_RATE_PARENT,
  1169. },
  1170. },
  1171. };
  1172. static struct clk_rcg sdc3_src = {
  1173. .ns_reg = 0x286c,
  1174. .md_reg = 0x2868,
  1175. .mn = {
  1176. .mnctr_en_bit = 8,
  1177. .mnctr_reset_bit = 7,
  1178. .mnctr_mode_shift = 5,
  1179. .n_val_shift = 16,
  1180. .m_val_shift = 16,
  1181. .width = 8,
  1182. },
  1183. .p = {
  1184. .pre_div_shift = 3,
  1185. .pre_div_width = 2,
  1186. },
  1187. .s = {
  1188. .src_sel_shift = 0,
  1189. .parent_map = gcc_pxo_pll8_map,
  1190. },
  1191. .freq_tbl = clk_tbl_sdc,
  1192. .clkr = {
  1193. .enable_reg = 0x286c,
  1194. .enable_mask = BIT(11),
  1195. .hw.init = &(struct clk_init_data){
  1196. .name = "sdc3_src",
  1197. .parent_names = gcc_pxo_pll8,
  1198. .num_parents = 2,
  1199. .ops = &clk_rcg_ops,
  1200. .flags = CLK_SET_RATE_GATE,
  1201. },
  1202. }
  1203. };
  1204. static struct clk_branch sdc3_clk = {
  1205. .halt_reg = 0x2fc8,
  1206. .halt_bit = 4,
  1207. .clkr = {
  1208. .enable_reg = 0x286c,
  1209. .enable_mask = BIT(9),
  1210. .hw.init = &(struct clk_init_data){
  1211. .name = "sdc3_clk",
  1212. .parent_names = (const char *[]){ "sdc3_src" },
  1213. .num_parents = 1,
  1214. .ops = &clk_branch_ops,
  1215. .flags = CLK_SET_RATE_PARENT,
  1216. },
  1217. },
  1218. };
  1219. static struct clk_branch sdc1_h_clk = {
  1220. .hwcg_reg = 0x2820,
  1221. .hwcg_bit = 6,
  1222. .halt_reg = 0x2fc8,
  1223. .halt_bit = 11,
  1224. .clkr = {
  1225. .enable_reg = 0x2820,
  1226. .enable_mask = BIT(4),
  1227. .hw.init = &(struct clk_init_data){
  1228. .name = "sdc1_h_clk",
  1229. .ops = &clk_branch_ops,
  1230. },
  1231. },
  1232. };
  1233. static struct clk_branch sdc3_h_clk = {
  1234. .hwcg_reg = 0x2860,
  1235. .hwcg_bit = 6,
  1236. .halt_reg = 0x2fc8,
  1237. .halt_bit = 9,
  1238. .clkr = {
  1239. .enable_reg = 0x2860,
  1240. .enable_mask = BIT(4),
  1241. .hw.init = &(struct clk_init_data){
  1242. .name = "sdc3_h_clk",
  1243. .ops = &clk_branch_ops,
  1244. },
  1245. },
  1246. };
  1247. static const struct freq_tbl clk_tbl_tsif_ref[] = {
  1248. { 105000, P_PXO, 1, 1, 256 },
  1249. { }
  1250. };
  1251. static struct clk_rcg tsif_ref_src = {
  1252. .ns_reg = 0x2710,
  1253. .md_reg = 0x270c,
  1254. .mn = {
  1255. .mnctr_en_bit = 8,
  1256. .mnctr_reset_bit = 7,
  1257. .mnctr_mode_shift = 5,
  1258. .n_val_shift = 16,
  1259. .m_val_shift = 16,
  1260. .width = 16,
  1261. },
  1262. .p = {
  1263. .pre_div_shift = 3,
  1264. .pre_div_width = 2,
  1265. },
  1266. .s = {
  1267. .src_sel_shift = 0,
  1268. .parent_map = gcc_pxo_pll8_map,
  1269. },
  1270. .freq_tbl = clk_tbl_tsif_ref,
  1271. .clkr = {
  1272. .enable_reg = 0x2710,
  1273. .enable_mask = BIT(11),
  1274. .hw.init = &(struct clk_init_data){
  1275. .name = "tsif_ref_src",
  1276. .parent_names = gcc_pxo_pll8,
  1277. .num_parents = 2,
  1278. .ops = &clk_rcg_ops,
  1279. .flags = CLK_SET_RATE_GATE,
  1280. },
  1281. }
  1282. };
  1283. static struct clk_branch tsif_ref_clk = {
  1284. .halt_reg = 0x2fd4,
  1285. .halt_bit = 5,
  1286. .clkr = {
  1287. .enable_reg = 0x2710,
  1288. .enable_mask = BIT(9),
  1289. .hw.init = &(struct clk_init_data){
  1290. .name = "tsif_ref_clk",
  1291. .parent_names = (const char *[]){ "tsif_ref_src" },
  1292. .num_parents = 1,
  1293. .ops = &clk_branch_ops,
  1294. .flags = CLK_SET_RATE_PARENT,
  1295. },
  1296. },
  1297. };
  1298. static struct clk_branch tsif_h_clk = {
  1299. .hwcg_reg = 0x2700,
  1300. .hwcg_bit = 6,
  1301. .halt_reg = 0x2fd4,
  1302. .halt_bit = 7,
  1303. .clkr = {
  1304. .enable_reg = 0x2700,
  1305. .enable_mask = BIT(4),
  1306. .hw.init = &(struct clk_init_data){
  1307. .name = "tsif_h_clk",
  1308. .ops = &clk_branch_ops,
  1309. },
  1310. },
  1311. };
  1312. static struct clk_branch dma_bam_h_clk = {
  1313. .hwcg_reg = 0x25c0,
  1314. .hwcg_bit = 6,
  1315. .halt_reg = 0x2fc8,
  1316. .halt_bit = 12,
  1317. .clkr = {
  1318. .enable_reg = 0x25c0,
  1319. .enable_mask = BIT(4),
  1320. .hw.init = &(struct clk_init_data){
  1321. .name = "dma_bam_h_clk",
  1322. .ops = &clk_branch_ops,
  1323. },
  1324. },
  1325. };
  1326. static struct clk_branch adm0_clk = {
  1327. .halt_reg = 0x2fdc,
  1328. .halt_check = BRANCH_HALT_VOTED,
  1329. .halt_bit = 12,
  1330. .clkr = {
  1331. .enable_reg = 0x3080,
  1332. .enable_mask = BIT(2),
  1333. .hw.init = &(struct clk_init_data){
  1334. .name = "adm0_clk",
  1335. .ops = &clk_branch_ops,
  1336. },
  1337. },
  1338. };
  1339. static struct clk_branch adm0_pbus_clk = {
  1340. .hwcg_reg = 0x2208,
  1341. .hwcg_bit = 6,
  1342. .halt_reg = 0x2fdc,
  1343. .halt_check = BRANCH_HALT_VOTED,
  1344. .halt_bit = 11,
  1345. .clkr = {
  1346. .enable_reg = 0x3080,
  1347. .enable_mask = BIT(3),
  1348. .hw.init = &(struct clk_init_data){
  1349. .name = "adm0_pbus_clk",
  1350. .ops = &clk_branch_ops,
  1351. },
  1352. },
  1353. };
  1354. static struct clk_branch pmic_arb0_h_clk = {
  1355. .halt_reg = 0x2fd8,
  1356. .halt_check = BRANCH_HALT_VOTED,
  1357. .halt_bit = 22,
  1358. .clkr = {
  1359. .enable_reg = 0x3080,
  1360. .enable_mask = BIT(8),
  1361. .hw.init = &(struct clk_init_data){
  1362. .name = "pmic_arb0_h_clk",
  1363. .ops = &clk_branch_ops,
  1364. },
  1365. },
  1366. };
  1367. static struct clk_branch pmic_arb1_h_clk = {
  1368. .halt_reg = 0x2fd8,
  1369. .halt_check = BRANCH_HALT_VOTED,
  1370. .halt_bit = 21,
  1371. .clkr = {
  1372. .enable_reg = 0x3080,
  1373. .enable_mask = BIT(9),
  1374. .hw.init = &(struct clk_init_data){
  1375. .name = "pmic_arb1_h_clk",
  1376. .ops = &clk_branch_ops,
  1377. },
  1378. },
  1379. };
  1380. static struct clk_branch pmic_ssbi2_clk = {
  1381. .halt_reg = 0x2fd8,
  1382. .halt_check = BRANCH_HALT_VOTED,
  1383. .halt_bit = 23,
  1384. .clkr = {
  1385. .enable_reg = 0x3080,
  1386. .enable_mask = BIT(7),
  1387. .hw.init = &(struct clk_init_data){
  1388. .name = "pmic_ssbi2_clk",
  1389. .ops = &clk_branch_ops,
  1390. },
  1391. },
  1392. };
  1393. static struct clk_branch rpm_msg_ram_h_clk = {
  1394. .hwcg_reg = 0x27e0,
  1395. .hwcg_bit = 6,
  1396. .halt_reg = 0x2fd8,
  1397. .halt_check = BRANCH_HALT_VOTED,
  1398. .halt_bit = 12,
  1399. .clkr = {
  1400. .enable_reg = 0x3080,
  1401. .enable_mask = BIT(6),
  1402. .hw.init = &(struct clk_init_data){
  1403. .name = "rpm_msg_ram_h_clk",
  1404. .ops = &clk_branch_ops,
  1405. },
  1406. },
  1407. };
  1408. static const struct freq_tbl clk_tbl_pcie_ref[] = {
  1409. { 100000000, P_PLL3, 12, 0, 0 },
  1410. { }
  1411. };
  1412. static struct clk_rcg pcie_ref_src = {
  1413. .ns_reg = 0x3860,
  1414. .p = {
  1415. .pre_div_shift = 3,
  1416. .pre_div_width = 4,
  1417. },
  1418. .s = {
  1419. .src_sel_shift = 0,
  1420. .parent_map = gcc_pxo_pll3_map,
  1421. },
  1422. .freq_tbl = clk_tbl_pcie_ref,
  1423. .clkr = {
  1424. .enable_reg = 0x3860,
  1425. .enable_mask = BIT(11),
  1426. .hw.init = &(struct clk_init_data){
  1427. .name = "pcie_ref_src",
  1428. .parent_names = gcc_pxo_pll3,
  1429. .num_parents = 2,
  1430. .ops = &clk_rcg_ops,
  1431. .flags = CLK_SET_RATE_GATE,
  1432. },
  1433. },
  1434. };
  1435. static struct clk_branch pcie_ref_src_clk = {
  1436. .halt_reg = 0x2fdc,
  1437. .halt_bit = 30,
  1438. .clkr = {
  1439. .enable_reg = 0x3860,
  1440. .enable_mask = BIT(9),
  1441. .hw.init = &(struct clk_init_data){
  1442. .name = "pcie_ref_src_clk",
  1443. .parent_names = (const char *[]){ "pcie_ref_src" },
  1444. .num_parents = 1,
  1445. .ops = &clk_branch_ops,
  1446. .flags = CLK_SET_RATE_PARENT,
  1447. },
  1448. },
  1449. };
  1450. static struct clk_branch pcie_a_clk = {
  1451. .halt_reg = 0x2fc0,
  1452. .halt_bit = 13,
  1453. .clkr = {
  1454. .enable_reg = 0x22c0,
  1455. .enable_mask = BIT(4),
  1456. .hw.init = &(struct clk_init_data){
  1457. .name = "pcie_a_clk",
  1458. .ops = &clk_branch_ops,
  1459. },
  1460. },
  1461. };
  1462. static struct clk_branch pcie_aux_clk = {
  1463. .halt_reg = 0x2fdc,
  1464. .halt_bit = 31,
  1465. .clkr = {
  1466. .enable_reg = 0x22c8,
  1467. .enable_mask = BIT(4),
  1468. .hw.init = &(struct clk_init_data){
  1469. .name = "pcie_aux_clk",
  1470. .ops = &clk_branch_ops,
  1471. },
  1472. },
  1473. };
  1474. static struct clk_branch pcie_h_clk = {
  1475. .halt_reg = 0x2fd4,
  1476. .halt_bit = 8,
  1477. .clkr = {
  1478. .enable_reg = 0x22cc,
  1479. .enable_mask = BIT(4),
  1480. .hw.init = &(struct clk_init_data){
  1481. .name = "pcie_h_clk",
  1482. .ops = &clk_branch_ops,
  1483. },
  1484. },
  1485. };
  1486. static struct clk_branch pcie_phy_clk = {
  1487. .halt_reg = 0x2fdc,
  1488. .halt_bit = 29,
  1489. .clkr = {
  1490. .enable_reg = 0x22d0,
  1491. .enable_mask = BIT(4),
  1492. .hw.init = &(struct clk_init_data){
  1493. .name = "pcie_phy_clk",
  1494. .ops = &clk_branch_ops,
  1495. },
  1496. },
  1497. };
  1498. static struct clk_rcg pcie1_ref_src = {
  1499. .ns_reg = 0x3aa0,
  1500. .p = {
  1501. .pre_div_shift = 3,
  1502. .pre_div_width = 4,
  1503. },
  1504. .s = {
  1505. .src_sel_shift = 0,
  1506. .parent_map = gcc_pxo_pll3_map,
  1507. },
  1508. .freq_tbl = clk_tbl_pcie_ref,
  1509. .clkr = {
  1510. .enable_reg = 0x3aa0,
  1511. .enable_mask = BIT(11),
  1512. .hw.init = &(struct clk_init_data){
  1513. .name = "pcie1_ref_src",
  1514. .parent_names = gcc_pxo_pll3,
  1515. .num_parents = 2,
  1516. .ops = &clk_rcg_ops,
  1517. .flags = CLK_SET_RATE_GATE,
  1518. },
  1519. },
  1520. };
  1521. static struct clk_branch pcie1_ref_src_clk = {
  1522. .halt_reg = 0x2fdc,
  1523. .halt_bit = 27,
  1524. .clkr = {
  1525. .enable_reg = 0x3aa0,
  1526. .enable_mask = BIT(9),
  1527. .hw.init = &(struct clk_init_data){
  1528. .name = "pcie1_ref_src_clk",
  1529. .parent_names = (const char *[]){ "pcie1_ref_src" },
  1530. .num_parents = 1,
  1531. .ops = &clk_branch_ops,
  1532. .flags = CLK_SET_RATE_PARENT,
  1533. },
  1534. },
  1535. };
  1536. static struct clk_branch pcie1_a_clk = {
  1537. .halt_reg = 0x2fc0,
  1538. .halt_bit = 10,
  1539. .clkr = {
  1540. .enable_reg = 0x3a80,
  1541. .enable_mask = BIT(4),
  1542. .hw.init = &(struct clk_init_data){
  1543. .name = "pcie1_a_clk",
  1544. .ops = &clk_branch_ops,
  1545. },
  1546. },
  1547. };
  1548. static struct clk_branch pcie1_aux_clk = {
  1549. .halt_reg = 0x2fdc,
  1550. .halt_bit = 28,
  1551. .clkr = {
  1552. .enable_reg = 0x3a88,
  1553. .enable_mask = BIT(4),
  1554. .hw.init = &(struct clk_init_data){
  1555. .name = "pcie1_aux_clk",
  1556. .ops = &clk_branch_ops,
  1557. },
  1558. },
  1559. };
  1560. static struct clk_branch pcie1_h_clk = {
  1561. .halt_reg = 0x2fd4,
  1562. .halt_bit = 9,
  1563. .clkr = {
  1564. .enable_reg = 0x3a8c,
  1565. .enable_mask = BIT(4),
  1566. .hw.init = &(struct clk_init_data){
  1567. .name = "pcie1_h_clk",
  1568. .ops = &clk_branch_ops,
  1569. },
  1570. },
  1571. };
  1572. static struct clk_branch pcie1_phy_clk = {
  1573. .halt_reg = 0x2fdc,
  1574. .halt_bit = 26,
  1575. .clkr = {
  1576. .enable_reg = 0x3a90,
  1577. .enable_mask = BIT(4),
  1578. .hw.init = &(struct clk_init_data){
  1579. .name = "pcie1_phy_clk",
  1580. .ops = &clk_branch_ops,
  1581. },
  1582. },
  1583. };
  1584. static struct clk_rcg pcie2_ref_src = {
  1585. .ns_reg = 0x3ae0,
  1586. .p = {
  1587. .pre_div_shift = 3,
  1588. .pre_div_width = 4,
  1589. },
  1590. .s = {
  1591. .src_sel_shift = 0,
  1592. .parent_map = gcc_pxo_pll3_map,
  1593. },
  1594. .freq_tbl = clk_tbl_pcie_ref,
  1595. .clkr = {
  1596. .enable_reg = 0x3ae0,
  1597. .enable_mask = BIT(11),
  1598. .hw.init = &(struct clk_init_data){
  1599. .name = "pcie2_ref_src",
  1600. .parent_names = gcc_pxo_pll3,
  1601. .num_parents = 2,
  1602. .ops = &clk_rcg_ops,
  1603. .flags = CLK_SET_RATE_GATE,
  1604. },
  1605. },
  1606. };
  1607. static struct clk_branch pcie2_ref_src_clk = {
  1608. .halt_reg = 0x2fdc,
  1609. .halt_bit = 24,
  1610. .clkr = {
  1611. .enable_reg = 0x3ae0,
  1612. .enable_mask = BIT(9),
  1613. .hw.init = &(struct clk_init_data){
  1614. .name = "pcie2_ref_src_clk",
  1615. .parent_names = (const char *[]){ "pcie2_ref_src" },
  1616. .num_parents = 1,
  1617. .ops = &clk_branch_ops,
  1618. .flags = CLK_SET_RATE_PARENT,
  1619. },
  1620. },
  1621. };
  1622. static struct clk_branch pcie2_a_clk = {
  1623. .halt_reg = 0x2fc0,
  1624. .halt_bit = 9,
  1625. .clkr = {
  1626. .enable_reg = 0x3ac0,
  1627. .enable_mask = BIT(4),
  1628. .hw.init = &(struct clk_init_data){
  1629. .name = "pcie2_a_clk",
  1630. .ops = &clk_branch_ops,
  1631. },
  1632. },
  1633. };
  1634. static struct clk_branch pcie2_aux_clk = {
  1635. .halt_reg = 0x2fdc,
  1636. .halt_bit = 25,
  1637. .clkr = {
  1638. .enable_reg = 0x3ac8,
  1639. .enable_mask = BIT(4),
  1640. .hw.init = &(struct clk_init_data){
  1641. .name = "pcie2_aux_clk",
  1642. .ops = &clk_branch_ops,
  1643. },
  1644. },
  1645. };
  1646. static struct clk_branch pcie2_h_clk = {
  1647. .halt_reg = 0x2fd4,
  1648. .halt_bit = 10,
  1649. .clkr = {
  1650. .enable_reg = 0x3acc,
  1651. .enable_mask = BIT(4),
  1652. .hw.init = &(struct clk_init_data){
  1653. .name = "pcie2_h_clk",
  1654. .ops = &clk_branch_ops,
  1655. },
  1656. },
  1657. };
  1658. static struct clk_branch pcie2_phy_clk = {
  1659. .halt_reg = 0x2fdc,
  1660. .halt_bit = 23,
  1661. .clkr = {
  1662. .enable_reg = 0x3ad0,
  1663. .enable_mask = BIT(4),
  1664. .hw.init = &(struct clk_init_data){
  1665. .name = "pcie2_phy_clk",
  1666. .ops = &clk_branch_ops,
  1667. },
  1668. },
  1669. };
  1670. static const struct freq_tbl clk_tbl_sata_ref[] = {
  1671. { 100000000, P_PLL3, 12, 0, 0 },
  1672. { }
  1673. };
  1674. static struct clk_rcg sata_ref_src = {
  1675. .ns_reg = 0x2c08,
  1676. .p = {
  1677. .pre_div_shift = 3,
  1678. .pre_div_width = 4,
  1679. },
  1680. .s = {
  1681. .src_sel_shift = 0,
  1682. .parent_map = gcc_pxo_pll3_sata_map,
  1683. },
  1684. .freq_tbl = clk_tbl_sata_ref,
  1685. .clkr = {
  1686. .enable_reg = 0x2c08,
  1687. .enable_mask = BIT(7),
  1688. .hw.init = &(struct clk_init_data){
  1689. .name = "sata_ref_src",
  1690. .parent_names = gcc_pxo_pll3,
  1691. .num_parents = 2,
  1692. .ops = &clk_rcg_ops,
  1693. .flags = CLK_SET_RATE_GATE,
  1694. },
  1695. },
  1696. };
  1697. static struct clk_branch sata_rxoob_clk = {
  1698. .halt_reg = 0x2fdc,
  1699. .halt_bit = 20,
  1700. .clkr = {
  1701. .enable_reg = 0x2c0c,
  1702. .enable_mask = BIT(4),
  1703. .hw.init = &(struct clk_init_data){
  1704. .name = "sata_rxoob_clk",
  1705. .parent_names = (const char *[]){ "sata_ref_src" },
  1706. .num_parents = 1,
  1707. .ops = &clk_branch_ops,
  1708. .flags = CLK_SET_RATE_PARENT,
  1709. },
  1710. },
  1711. };
  1712. static struct clk_branch sata_pmalive_clk = {
  1713. .halt_reg = 0x2fdc,
  1714. .halt_bit = 19,
  1715. .clkr = {
  1716. .enable_reg = 0x2c10,
  1717. .enable_mask = BIT(4),
  1718. .hw.init = &(struct clk_init_data){
  1719. .name = "sata_pmalive_clk",
  1720. .parent_names = (const char *[]){ "sata_ref_src" },
  1721. .num_parents = 1,
  1722. .ops = &clk_branch_ops,
  1723. .flags = CLK_SET_RATE_PARENT,
  1724. },
  1725. },
  1726. };
  1727. static struct clk_branch sata_phy_ref_clk = {
  1728. .halt_reg = 0x2fdc,
  1729. .halt_bit = 18,
  1730. .clkr = {
  1731. .enable_reg = 0x2c14,
  1732. .enable_mask = BIT(4),
  1733. .hw.init = &(struct clk_init_data){
  1734. .name = "sata_phy_ref_clk",
  1735. .parent_names = (const char *[]){ "pxo" },
  1736. .num_parents = 1,
  1737. .ops = &clk_branch_ops,
  1738. },
  1739. },
  1740. };
  1741. static struct clk_branch sata_a_clk = {
  1742. .halt_reg = 0x2fc0,
  1743. .halt_bit = 12,
  1744. .clkr = {
  1745. .enable_reg = 0x2c20,
  1746. .enable_mask = BIT(4),
  1747. .hw.init = &(struct clk_init_data){
  1748. .name = "sata_a_clk",
  1749. .ops = &clk_branch_ops,
  1750. },
  1751. },
  1752. };
  1753. static struct clk_branch sata_h_clk = {
  1754. .halt_reg = 0x2fdc,
  1755. .halt_bit = 21,
  1756. .clkr = {
  1757. .enable_reg = 0x2c00,
  1758. .enable_mask = BIT(4),
  1759. .hw.init = &(struct clk_init_data){
  1760. .name = "sata_h_clk",
  1761. .ops = &clk_branch_ops,
  1762. },
  1763. },
  1764. };
  1765. static struct clk_branch sfab_sata_s_h_clk = {
  1766. .halt_reg = 0x2fc4,
  1767. .halt_bit = 14,
  1768. .clkr = {
  1769. .enable_reg = 0x2480,
  1770. .enable_mask = BIT(4),
  1771. .hw.init = &(struct clk_init_data){
  1772. .name = "sfab_sata_s_h_clk",
  1773. .ops = &clk_branch_ops,
  1774. },
  1775. },
  1776. };
  1777. static struct clk_branch sata_phy_cfg_clk = {
  1778. .halt_reg = 0x2fcc,
  1779. .halt_bit = 14,
  1780. .clkr = {
  1781. .enable_reg = 0x2c40,
  1782. .enable_mask = BIT(4),
  1783. .hw.init = &(struct clk_init_data){
  1784. .name = "sata_phy_cfg_clk",
  1785. .ops = &clk_branch_ops,
  1786. },
  1787. },
  1788. };
  1789. static const struct freq_tbl clk_tbl_usb30_master[] = {
  1790. { 125000000, P_PLL0, 1, 5, 32 },
  1791. { }
  1792. };
  1793. static struct clk_rcg usb30_master_clk_src = {
  1794. .ns_reg = 0x3b2c,
  1795. .md_reg = 0x3b28,
  1796. .mn = {
  1797. .mnctr_en_bit = 8,
  1798. .mnctr_reset_bit = 7,
  1799. .mnctr_mode_shift = 5,
  1800. .n_val_shift = 16,
  1801. .m_val_shift = 16,
  1802. .width = 8,
  1803. },
  1804. .p = {
  1805. .pre_div_shift = 3,
  1806. .pre_div_width = 2,
  1807. },
  1808. .s = {
  1809. .src_sel_shift = 0,
  1810. .parent_map = gcc_pxo_pll8_pll0,
  1811. },
  1812. .freq_tbl = clk_tbl_usb30_master,
  1813. .clkr = {
  1814. .enable_reg = 0x3b2c,
  1815. .enable_mask = BIT(11),
  1816. .hw.init = &(struct clk_init_data){
  1817. .name = "usb30_master_ref_src",
  1818. .parent_names = gcc_pxo_pll8_pll0_map,
  1819. .num_parents = 3,
  1820. .ops = &clk_rcg_ops,
  1821. .flags = CLK_SET_RATE_GATE,
  1822. },
  1823. },
  1824. };
  1825. static struct clk_branch usb30_0_branch_clk = {
  1826. .halt_reg = 0x2fc4,
  1827. .halt_bit = 22,
  1828. .clkr = {
  1829. .enable_reg = 0x3b24,
  1830. .enable_mask = BIT(4),
  1831. .hw.init = &(struct clk_init_data){
  1832. .name = "usb30_0_branch_clk",
  1833. .parent_names = (const char *[]){ "usb30_master_ref_src", },
  1834. .num_parents = 1,
  1835. .ops = &clk_branch_ops,
  1836. .flags = CLK_SET_RATE_PARENT,
  1837. },
  1838. },
  1839. };
  1840. static struct clk_branch usb30_1_branch_clk = {
  1841. .halt_reg = 0x2fc4,
  1842. .halt_bit = 17,
  1843. .clkr = {
  1844. .enable_reg = 0x3b34,
  1845. .enable_mask = BIT(4),
  1846. .hw.init = &(struct clk_init_data){
  1847. .name = "usb30_1_branch_clk",
  1848. .parent_names = (const char *[]){ "usb30_master_ref_src", },
  1849. .num_parents = 1,
  1850. .ops = &clk_branch_ops,
  1851. .flags = CLK_SET_RATE_PARENT,
  1852. },
  1853. },
  1854. };
  1855. static const struct freq_tbl clk_tbl_usb30_utmi[] = {
  1856. { 60000000, P_PLL8, 1, 5, 32 },
  1857. { }
  1858. };
  1859. static struct clk_rcg usb30_utmi_clk = {
  1860. .ns_reg = 0x3b44,
  1861. .md_reg = 0x3b40,
  1862. .mn = {
  1863. .mnctr_en_bit = 8,
  1864. .mnctr_reset_bit = 7,
  1865. .mnctr_mode_shift = 5,
  1866. .n_val_shift = 16,
  1867. .m_val_shift = 16,
  1868. .width = 8,
  1869. },
  1870. .p = {
  1871. .pre_div_shift = 3,
  1872. .pre_div_width = 2,
  1873. },
  1874. .s = {
  1875. .src_sel_shift = 0,
  1876. .parent_map = gcc_pxo_pll8_pll0,
  1877. },
  1878. .freq_tbl = clk_tbl_usb30_utmi,
  1879. .clkr = {
  1880. .enable_reg = 0x3b44,
  1881. .enable_mask = BIT(11),
  1882. .hw.init = &(struct clk_init_data){
  1883. .name = "usb30_utmi_clk",
  1884. .parent_names = gcc_pxo_pll8_pll0_map,
  1885. .num_parents = 3,
  1886. .ops = &clk_rcg_ops,
  1887. .flags = CLK_SET_RATE_GATE,
  1888. },
  1889. },
  1890. };
  1891. static struct clk_branch usb30_0_utmi_clk_ctl = {
  1892. .halt_reg = 0x2fc4,
  1893. .halt_bit = 21,
  1894. .clkr = {
  1895. .enable_reg = 0x3b48,
  1896. .enable_mask = BIT(4),
  1897. .hw.init = &(struct clk_init_data){
  1898. .name = "usb30_0_utmi_clk_ctl",
  1899. .parent_names = (const char *[]){ "usb30_utmi_clk", },
  1900. .num_parents = 1,
  1901. .ops = &clk_branch_ops,
  1902. .flags = CLK_SET_RATE_PARENT,
  1903. },
  1904. },
  1905. };
  1906. static struct clk_branch usb30_1_utmi_clk_ctl = {
  1907. .halt_reg = 0x2fc4,
  1908. .halt_bit = 15,
  1909. .clkr = {
  1910. .enable_reg = 0x3b4c,
  1911. .enable_mask = BIT(4),
  1912. .hw.init = &(struct clk_init_data){
  1913. .name = "usb30_1_utmi_clk_ctl",
  1914. .parent_names = (const char *[]){ "usb30_utmi_clk", },
  1915. .num_parents = 1,
  1916. .ops = &clk_branch_ops,
  1917. .flags = CLK_SET_RATE_PARENT,
  1918. },
  1919. },
  1920. };
  1921. static const struct freq_tbl clk_tbl_usb[] = {
  1922. { 60000000, P_PLL8, 1, 5, 32 },
  1923. { }
  1924. };
  1925. static struct clk_rcg usb_hs1_xcvr_clk_src = {
  1926. .ns_reg = 0x290C,
  1927. .md_reg = 0x2908,
  1928. .mn = {
  1929. .mnctr_en_bit = 8,
  1930. .mnctr_reset_bit = 7,
  1931. .mnctr_mode_shift = 5,
  1932. .n_val_shift = 16,
  1933. .m_val_shift = 16,
  1934. .width = 8,
  1935. },
  1936. .p = {
  1937. .pre_div_shift = 3,
  1938. .pre_div_width = 2,
  1939. },
  1940. .s = {
  1941. .src_sel_shift = 0,
  1942. .parent_map = gcc_pxo_pll8_pll0,
  1943. },
  1944. .freq_tbl = clk_tbl_usb,
  1945. .clkr = {
  1946. .enable_reg = 0x2968,
  1947. .enable_mask = BIT(11),
  1948. .hw.init = &(struct clk_init_data){
  1949. .name = "usb_hs1_xcvr_src",
  1950. .parent_names = gcc_pxo_pll8_pll0_map,
  1951. .num_parents = 3,
  1952. .ops = &clk_rcg_ops,
  1953. .flags = CLK_SET_RATE_GATE,
  1954. },
  1955. },
  1956. };
  1957. static struct clk_branch usb_hs1_xcvr_clk = {
  1958. .halt_reg = 0x2fcc,
  1959. .halt_bit = 17,
  1960. .clkr = {
  1961. .enable_reg = 0x290c,
  1962. .enable_mask = BIT(9),
  1963. .hw.init = &(struct clk_init_data){
  1964. .name = "usb_hs1_xcvr_clk",
  1965. .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
  1966. .num_parents = 1,
  1967. .ops = &clk_branch_ops,
  1968. .flags = CLK_SET_RATE_PARENT,
  1969. },
  1970. },
  1971. };
  1972. static struct clk_branch usb_hs1_h_clk = {
  1973. .hwcg_reg = 0x2900,
  1974. .hwcg_bit = 6,
  1975. .halt_reg = 0x2fc8,
  1976. .halt_bit = 1,
  1977. .clkr = {
  1978. .enable_reg = 0x2900,
  1979. .enable_mask = BIT(4),
  1980. .hw.init = &(struct clk_init_data){
  1981. .name = "usb_hs1_h_clk",
  1982. .ops = &clk_branch_ops,
  1983. },
  1984. },
  1985. };
  1986. static struct clk_rcg usb_fs1_xcvr_clk_src = {
  1987. .ns_reg = 0x2968,
  1988. .md_reg = 0x2964,
  1989. .mn = {
  1990. .mnctr_en_bit = 8,
  1991. .mnctr_reset_bit = 7,
  1992. .mnctr_mode_shift = 5,
  1993. .n_val_shift = 16,
  1994. .m_val_shift = 16,
  1995. .width = 8,
  1996. },
  1997. .p = {
  1998. .pre_div_shift = 3,
  1999. .pre_div_width = 2,
  2000. },
  2001. .s = {
  2002. .src_sel_shift = 0,
  2003. .parent_map = gcc_pxo_pll8_pll0,
  2004. },
  2005. .freq_tbl = clk_tbl_usb,
  2006. .clkr = {
  2007. .enable_reg = 0x2968,
  2008. .enable_mask = BIT(11),
  2009. .hw.init = &(struct clk_init_data){
  2010. .name = "usb_fs1_xcvr_src",
  2011. .parent_names = gcc_pxo_pll8_pll0_map,
  2012. .num_parents = 3,
  2013. .ops = &clk_rcg_ops,
  2014. .flags = CLK_SET_RATE_GATE,
  2015. },
  2016. },
  2017. };
  2018. static struct clk_branch usb_fs1_xcvr_clk = {
  2019. .halt_reg = 0x2fcc,
  2020. .halt_bit = 17,
  2021. .clkr = {
  2022. .enable_reg = 0x2968,
  2023. .enable_mask = BIT(9),
  2024. .hw.init = &(struct clk_init_data){
  2025. .name = "usb_fs1_xcvr_clk",
  2026. .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
  2027. .num_parents = 1,
  2028. .ops = &clk_branch_ops,
  2029. .flags = CLK_SET_RATE_PARENT,
  2030. },
  2031. },
  2032. };
  2033. static struct clk_branch usb_fs1_sys_clk = {
  2034. .halt_reg = 0x2fcc,
  2035. .halt_bit = 18,
  2036. .clkr = {
  2037. .enable_reg = 0x296c,
  2038. .enable_mask = BIT(4),
  2039. .hw.init = &(struct clk_init_data){
  2040. .name = "usb_fs1_sys_clk",
  2041. .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
  2042. .num_parents = 1,
  2043. .ops = &clk_branch_ops,
  2044. .flags = CLK_SET_RATE_PARENT,
  2045. },
  2046. },
  2047. };
  2048. static struct clk_branch usb_fs1_h_clk = {
  2049. .halt_reg = 0x2fcc,
  2050. .halt_bit = 19,
  2051. .clkr = {
  2052. .enable_reg = 0x2960,
  2053. .enable_mask = BIT(4),
  2054. .hw.init = &(struct clk_init_data){
  2055. .name = "usb_fs1_h_clk",
  2056. .ops = &clk_branch_ops,
  2057. },
  2058. },
  2059. };
  2060. static struct clk_branch ebi2_clk = {
  2061. .hwcg_reg = 0x3b00,
  2062. .hwcg_bit = 6,
  2063. .halt_reg = 0x2fcc,
  2064. .halt_bit = 1,
  2065. .clkr = {
  2066. .enable_reg = 0x3b00,
  2067. .enable_mask = BIT(4),
  2068. .hw.init = &(struct clk_init_data){
  2069. .name = "ebi2_clk",
  2070. .ops = &clk_branch_ops,
  2071. },
  2072. },
  2073. };
  2074. static struct clk_branch ebi2_aon_clk = {
  2075. .halt_reg = 0x2fcc,
  2076. .halt_bit = 0,
  2077. .clkr = {
  2078. .enable_reg = 0x3b00,
  2079. .enable_mask = BIT(8),
  2080. .hw.init = &(struct clk_init_data){
  2081. .name = "ebi2_always_on_clk",
  2082. .ops = &clk_branch_ops,
  2083. },
  2084. },
  2085. };
  2086. static const struct freq_tbl clk_tbl_gmac[] = {
  2087. { 133000000, P_PLL0, 1, 50, 301 },
  2088. { 266000000, P_PLL0, 1, 127, 382 },
  2089. { }
  2090. };
  2091. static struct clk_dyn_rcg gmac_core1_src = {
  2092. .ns_reg[0] = 0x3cac,
  2093. .ns_reg[1] = 0x3cb0,
  2094. .md_reg[0] = 0x3ca4,
  2095. .md_reg[1] = 0x3ca8,
  2096. .bank_reg = 0x3ca0,
  2097. .mn[0] = {
  2098. .mnctr_en_bit = 8,
  2099. .mnctr_reset_bit = 7,
  2100. .mnctr_mode_shift = 5,
  2101. .n_val_shift = 16,
  2102. .m_val_shift = 16,
  2103. .width = 8,
  2104. },
  2105. .mn[1] = {
  2106. .mnctr_en_bit = 8,
  2107. .mnctr_reset_bit = 7,
  2108. .mnctr_mode_shift = 5,
  2109. .n_val_shift = 16,
  2110. .m_val_shift = 16,
  2111. .width = 8,
  2112. },
  2113. .s[0] = {
  2114. .src_sel_shift = 0,
  2115. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2116. },
  2117. .s[1] = {
  2118. .src_sel_shift = 0,
  2119. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2120. },
  2121. .p[0] = {
  2122. .pre_div_shift = 3,
  2123. .pre_div_width = 2,
  2124. },
  2125. .p[1] = {
  2126. .pre_div_shift = 3,
  2127. .pre_div_width = 2,
  2128. },
  2129. .mux_sel_bit = 0,
  2130. .freq_tbl = clk_tbl_gmac,
  2131. .clkr = {
  2132. .enable_reg = 0x3ca0,
  2133. .enable_mask = BIT(1),
  2134. .hw.init = &(struct clk_init_data){
  2135. .name = "gmac_core1_src",
  2136. .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
  2137. .num_parents = 5,
  2138. .ops = &clk_dyn_rcg_ops,
  2139. },
  2140. },
  2141. };
  2142. static struct clk_branch gmac_core1_clk = {
  2143. .halt_reg = 0x3c20,
  2144. .halt_bit = 4,
  2145. .hwcg_reg = 0x3cb4,
  2146. .hwcg_bit = 6,
  2147. .clkr = {
  2148. .enable_reg = 0x3cb4,
  2149. .enable_mask = BIT(4),
  2150. .hw.init = &(struct clk_init_data){
  2151. .name = "gmac_core1_clk",
  2152. .parent_names = (const char *[]){
  2153. "gmac_core1_src",
  2154. },
  2155. .num_parents = 1,
  2156. .ops = &clk_branch_ops,
  2157. .flags = CLK_SET_RATE_PARENT,
  2158. },
  2159. },
  2160. };
  2161. static struct clk_dyn_rcg gmac_core2_src = {
  2162. .ns_reg[0] = 0x3ccc,
  2163. .ns_reg[1] = 0x3cd0,
  2164. .md_reg[0] = 0x3cc4,
  2165. .md_reg[1] = 0x3cc8,
  2166. .bank_reg = 0x3ca0,
  2167. .mn[0] = {
  2168. .mnctr_en_bit = 8,
  2169. .mnctr_reset_bit = 7,
  2170. .mnctr_mode_shift = 5,
  2171. .n_val_shift = 16,
  2172. .m_val_shift = 16,
  2173. .width = 8,
  2174. },
  2175. .mn[1] = {
  2176. .mnctr_en_bit = 8,
  2177. .mnctr_reset_bit = 7,
  2178. .mnctr_mode_shift = 5,
  2179. .n_val_shift = 16,
  2180. .m_val_shift = 16,
  2181. .width = 8,
  2182. },
  2183. .s[0] = {
  2184. .src_sel_shift = 0,
  2185. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2186. },
  2187. .s[1] = {
  2188. .src_sel_shift = 0,
  2189. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2190. },
  2191. .p[0] = {
  2192. .pre_div_shift = 3,
  2193. .pre_div_width = 2,
  2194. },
  2195. .p[1] = {
  2196. .pre_div_shift = 3,
  2197. .pre_div_width = 2,
  2198. },
  2199. .mux_sel_bit = 0,
  2200. .freq_tbl = clk_tbl_gmac,
  2201. .clkr = {
  2202. .enable_reg = 0x3cc0,
  2203. .enable_mask = BIT(1),
  2204. .hw.init = &(struct clk_init_data){
  2205. .name = "gmac_core2_src",
  2206. .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
  2207. .num_parents = 5,
  2208. .ops = &clk_dyn_rcg_ops,
  2209. },
  2210. },
  2211. };
  2212. static struct clk_branch gmac_core2_clk = {
  2213. .halt_reg = 0x3c20,
  2214. .halt_bit = 5,
  2215. .hwcg_reg = 0x3cd4,
  2216. .hwcg_bit = 6,
  2217. .clkr = {
  2218. .enable_reg = 0x3cd4,
  2219. .enable_mask = BIT(4),
  2220. .hw.init = &(struct clk_init_data){
  2221. .name = "gmac_core2_clk",
  2222. .parent_names = (const char *[]){
  2223. "gmac_core2_src",
  2224. },
  2225. .num_parents = 1,
  2226. .ops = &clk_branch_ops,
  2227. .flags = CLK_SET_RATE_PARENT,
  2228. },
  2229. },
  2230. };
  2231. static struct clk_dyn_rcg gmac_core3_src = {
  2232. .ns_reg[0] = 0x3cec,
  2233. .ns_reg[1] = 0x3cf0,
  2234. .md_reg[0] = 0x3ce4,
  2235. .md_reg[1] = 0x3ce8,
  2236. .bank_reg = 0x3ce0,
  2237. .mn[0] = {
  2238. .mnctr_en_bit = 8,
  2239. .mnctr_reset_bit = 7,
  2240. .mnctr_mode_shift = 5,
  2241. .n_val_shift = 16,
  2242. .m_val_shift = 16,
  2243. .width = 8,
  2244. },
  2245. .mn[1] = {
  2246. .mnctr_en_bit = 8,
  2247. .mnctr_reset_bit = 7,
  2248. .mnctr_mode_shift = 5,
  2249. .n_val_shift = 16,
  2250. .m_val_shift = 16,
  2251. .width = 8,
  2252. },
  2253. .s[0] = {
  2254. .src_sel_shift = 0,
  2255. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2256. },
  2257. .s[1] = {
  2258. .src_sel_shift = 0,
  2259. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2260. },
  2261. .p[0] = {
  2262. .pre_div_shift = 3,
  2263. .pre_div_width = 2,
  2264. },
  2265. .p[1] = {
  2266. .pre_div_shift = 3,
  2267. .pre_div_width = 2,
  2268. },
  2269. .mux_sel_bit = 0,
  2270. .freq_tbl = clk_tbl_gmac,
  2271. .clkr = {
  2272. .enable_reg = 0x3ce0,
  2273. .enable_mask = BIT(1),
  2274. .hw.init = &(struct clk_init_data){
  2275. .name = "gmac_core3_src",
  2276. .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
  2277. .num_parents = 5,
  2278. .ops = &clk_dyn_rcg_ops,
  2279. },
  2280. },
  2281. };
  2282. static struct clk_branch gmac_core3_clk = {
  2283. .halt_reg = 0x3c20,
  2284. .halt_bit = 6,
  2285. .hwcg_reg = 0x3cf4,
  2286. .hwcg_bit = 6,
  2287. .clkr = {
  2288. .enable_reg = 0x3cf4,
  2289. .enable_mask = BIT(4),
  2290. .hw.init = &(struct clk_init_data){
  2291. .name = "gmac_core3_clk",
  2292. .parent_names = (const char *[]){
  2293. "gmac_core3_src",
  2294. },
  2295. .num_parents = 1,
  2296. .ops = &clk_branch_ops,
  2297. .flags = CLK_SET_RATE_PARENT,
  2298. },
  2299. },
  2300. };
  2301. static struct clk_dyn_rcg gmac_core4_src = {
  2302. .ns_reg[0] = 0x3d0c,
  2303. .ns_reg[1] = 0x3d10,
  2304. .md_reg[0] = 0x3d04,
  2305. .md_reg[1] = 0x3d08,
  2306. .bank_reg = 0x3d00,
  2307. .mn[0] = {
  2308. .mnctr_en_bit = 8,
  2309. .mnctr_reset_bit = 7,
  2310. .mnctr_mode_shift = 5,
  2311. .n_val_shift = 16,
  2312. .m_val_shift = 16,
  2313. .width = 8,
  2314. },
  2315. .mn[1] = {
  2316. .mnctr_en_bit = 8,
  2317. .mnctr_reset_bit = 7,
  2318. .mnctr_mode_shift = 5,
  2319. .n_val_shift = 16,
  2320. .m_val_shift = 16,
  2321. .width = 8,
  2322. },
  2323. .s[0] = {
  2324. .src_sel_shift = 0,
  2325. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2326. },
  2327. .s[1] = {
  2328. .src_sel_shift = 0,
  2329. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2330. },
  2331. .p[0] = {
  2332. .pre_div_shift = 3,
  2333. .pre_div_width = 2,
  2334. },
  2335. .p[1] = {
  2336. .pre_div_shift = 3,
  2337. .pre_div_width = 2,
  2338. },
  2339. .mux_sel_bit = 0,
  2340. .freq_tbl = clk_tbl_gmac,
  2341. .clkr = {
  2342. .enable_reg = 0x3d00,
  2343. .enable_mask = BIT(1),
  2344. .hw.init = &(struct clk_init_data){
  2345. .name = "gmac_core4_src",
  2346. .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
  2347. .num_parents = 5,
  2348. .ops = &clk_dyn_rcg_ops,
  2349. },
  2350. },
  2351. };
  2352. static struct clk_branch gmac_core4_clk = {
  2353. .halt_reg = 0x3c20,
  2354. .halt_bit = 7,
  2355. .hwcg_reg = 0x3d14,
  2356. .hwcg_bit = 6,
  2357. .clkr = {
  2358. .enable_reg = 0x3d14,
  2359. .enable_mask = BIT(4),
  2360. .hw.init = &(struct clk_init_data){
  2361. .name = "gmac_core4_clk",
  2362. .parent_names = (const char *[]){
  2363. "gmac_core4_src",
  2364. },
  2365. .num_parents = 1,
  2366. .ops = &clk_branch_ops,
  2367. .flags = CLK_SET_RATE_PARENT,
  2368. },
  2369. },
  2370. };
  2371. static const struct freq_tbl clk_tbl_nss_tcm[] = {
  2372. { 266000000, P_PLL0, 3, 0, 0 },
  2373. { 400000000, P_PLL0, 2, 0, 0 },
  2374. { }
  2375. };
  2376. static struct clk_dyn_rcg nss_tcm_src = {
  2377. .ns_reg[0] = 0x3dc4,
  2378. .ns_reg[1] = 0x3dc8,
  2379. .bank_reg = 0x3dc0,
  2380. .s[0] = {
  2381. .src_sel_shift = 0,
  2382. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2383. },
  2384. .s[1] = {
  2385. .src_sel_shift = 0,
  2386. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2387. },
  2388. .p[0] = {
  2389. .pre_div_shift = 3,
  2390. .pre_div_width = 4,
  2391. },
  2392. .p[1] = {
  2393. .pre_div_shift = 3,
  2394. .pre_div_width = 4,
  2395. },
  2396. .mux_sel_bit = 0,
  2397. .freq_tbl = clk_tbl_nss_tcm,
  2398. .clkr = {
  2399. .enable_reg = 0x3dc0,
  2400. .enable_mask = BIT(1),
  2401. .hw.init = &(struct clk_init_data){
  2402. .name = "nss_tcm_src",
  2403. .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
  2404. .num_parents = 5,
  2405. .ops = &clk_dyn_rcg_ops,
  2406. },
  2407. },
  2408. };
  2409. static struct clk_branch nss_tcm_clk = {
  2410. .halt_reg = 0x3c20,
  2411. .halt_bit = 14,
  2412. .clkr = {
  2413. .enable_reg = 0x3dd0,
  2414. .enable_mask = BIT(6) | BIT(4),
  2415. .hw.init = &(struct clk_init_data){
  2416. .name = "nss_tcm_clk",
  2417. .parent_names = (const char *[]){
  2418. "nss_tcm_src",
  2419. },
  2420. .num_parents = 1,
  2421. .ops = &clk_branch_ops,
  2422. .flags = CLK_SET_RATE_PARENT,
  2423. },
  2424. },
  2425. };
  2426. static const struct freq_tbl clk_tbl_nss[] = {
  2427. { 110000000, P_PLL18, 1, 1, 5 },
  2428. { 275000000, P_PLL18, 2, 0, 0 },
  2429. { 550000000, P_PLL18, 1, 0, 0 },
  2430. { 733000000, P_PLL18, 1, 0, 0 },
  2431. { }
  2432. };
  2433. static struct clk_dyn_rcg ubi32_core1_src_clk = {
  2434. .ns_reg[0] = 0x3d2c,
  2435. .ns_reg[1] = 0x3d30,
  2436. .md_reg[0] = 0x3d24,
  2437. .md_reg[1] = 0x3d28,
  2438. .bank_reg = 0x3d20,
  2439. .mn[0] = {
  2440. .mnctr_en_bit = 8,
  2441. .mnctr_reset_bit = 7,
  2442. .mnctr_mode_shift = 5,
  2443. .n_val_shift = 16,
  2444. .m_val_shift = 16,
  2445. .width = 8,
  2446. },
  2447. .mn[1] = {
  2448. .mnctr_en_bit = 8,
  2449. .mnctr_reset_bit = 7,
  2450. .mnctr_mode_shift = 5,
  2451. .n_val_shift = 16,
  2452. .m_val_shift = 16,
  2453. .width = 8,
  2454. },
  2455. .s[0] = {
  2456. .src_sel_shift = 0,
  2457. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2458. },
  2459. .s[1] = {
  2460. .src_sel_shift = 0,
  2461. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2462. },
  2463. .p[0] = {
  2464. .pre_div_shift = 3,
  2465. .pre_div_width = 2,
  2466. },
  2467. .p[1] = {
  2468. .pre_div_shift = 3,
  2469. .pre_div_width = 2,
  2470. },
  2471. .mux_sel_bit = 0,
  2472. .freq_tbl = clk_tbl_nss,
  2473. .clkr = {
  2474. .enable_reg = 0x3d20,
  2475. .enable_mask = BIT(1),
  2476. .hw.init = &(struct clk_init_data){
  2477. .name = "ubi32_core1_src_clk",
  2478. .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
  2479. .num_parents = 5,
  2480. .ops = &clk_dyn_rcg_ops,
  2481. .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
  2482. },
  2483. },
  2484. };
  2485. static struct clk_dyn_rcg ubi32_core2_src_clk = {
  2486. .ns_reg[0] = 0x3d4c,
  2487. .ns_reg[1] = 0x3d50,
  2488. .md_reg[0] = 0x3d44,
  2489. .md_reg[1] = 0x3d48,
  2490. .bank_reg = 0x3d40,
  2491. .mn[0] = {
  2492. .mnctr_en_bit = 8,
  2493. .mnctr_reset_bit = 7,
  2494. .mnctr_mode_shift = 5,
  2495. .n_val_shift = 16,
  2496. .m_val_shift = 16,
  2497. .width = 8,
  2498. },
  2499. .mn[1] = {
  2500. .mnctr_en_bit = 8,
  2501. .mnctr_reset_bit = 7,
  2502. .mnctr_mode_shift = 5,
  2503. .n_val_shift = 16,
  2504. .m_val_shift = 16,
  2505. .width = 8,
  2506. },
  2507. .s[0] = {
  2508. .src_sel_shift = 0,
  2509. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2510. },
  2511. .s[1] = {
  2512. .src_sel_shift = 0,
  2513. .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
  2514. },
  2515. .p[0] = {
  2516. .pre_div_shift = 3,
  2517. .pre_div_width = 2,
  2518. },
  2519. .p[1] = {
  2520. .pre_div_shift = 3,
  2521. .pre_div_width = 2,
  2522. },
  2523. .mux_sel_bit = 0,
  2524. .freq_tbl = clk_tbl_nss,
  2525. .clkr = {
  2526. .enable_reg = 0x3d40,
  2527. .enable_mask = BIT(1),
  2528. .hw.init = &(struct clk_init_data){
  2529. .name = "ubi32_core2_src_clk",
  2530. .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
  2531. .num_parents = 5,
  2532. .ops = &clk_dyn_rcg_ops,
  2533. .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
  2534. },
  2535. },
  2536. };
  2537. static struct clk_regmap *gcc_ipq806x_clks[] = {
  2538. [PLL0] = &pll0.clkr,
  2539. [PLL0_VOTE] = &pll0_vote,
  2540. [PLL3] = &pll3.clkr,
  2541. [PLL4_VOTE] = &pll4_vote,
  2542. [PLL8] = &pll8.clkr,
  2543. [PLL8_VOTE] = &pll8_vote,
  2544. [PLL14] = &pll14.clkr,
  2545. [PLL14_VOTE] = &pll14_vote,
  2546. [PLL18] = &pll18.clkr,
  2547. [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
  2548. [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
  2549. [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
  2550. [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
  2551. [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
  2552. [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
  2553. [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
  2554. [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
  2555. [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
  2556. [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
  2557. [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
  2558. [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
  2559. [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
  2560. [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
  2561. [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
  2562. [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
  2563. [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
  2564. [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
  2565. [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
  2566. [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
  2567. [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
  2568. [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
  2569. [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
  2570. [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
  2571. [GP0_SRC] = &gp0_src.clkr,
  2572. [GP0_CLK] = &gp0_clk.clkr,
  2573. [GP1_SRC] = &gp1_src.clkr,
  2574. [GP1_CLK] = &gp1_clk.clkr,
  2575. [GP2_SRC] = &gp2_src.clkr,
  2576. [GP2_CLK] = &gp2_clk.clkr,
  2577. [PMEM_A_CLK] = &pmem_clk.clkr,
  2578. [PRNG_SRC] = &prng_src.clkr,
  2579. [PRNG_CLK] = &prng_clk.clkr,
  2580. [SDC1_SRC] = &sdc1_src.clkr,
  2581. [SDC1_CLK] = &sdc1_clk.clkr,
  2582. [SDC3_SRC] = &sdc3_src.clkr,
  2583. [SDC3_CLK] = &sdc3_clk.clkr,
  2584. [TSIF_REF_SRC] = &tsif_ref_src.clkr,
  2585. [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
  2586. [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
  2587. [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
  2588. [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
  2589. [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
  2590. [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
  2591. [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
  2592. [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
  2593. [TSIF_H_CLK] = &tsif_h_clk.clkr,
  2594. [SDC1_H_CLK] = &sdc1_h_clk.clkr,
  2595. [SDC3_H_CLK] = &sdc3_h_clk.clkr,
  2596. [ADM0_CLK] = &adm0_clk.clkr,
  2597. [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
  2598. [PCIE_A_CLK] = &pcie_a_clk.clkr,
  2599. [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
  2600. [PCIE_H_CLK] = &pcie_h_clk.clkr,
  2601. [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
  2602. [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
  2603. [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
  2604. [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
  2605. [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
  2606. [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
  2607. [SATA_H_CLK] = &sata_h_clk.clkr,
  2608. [SATA_CLK_SRC] = &sata_ref_src.clkr,
  2609. [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
  2610. [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
  2611. [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
  2612. [SATA_A_CLK] = &sata_a_clk.clkr,
  2613. [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
  2614. [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
  2615. [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
  2616. [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
  2617. [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
  2618. [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
  2619. [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
  2620. [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
  2621. [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
  2622. [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
  2623. [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
  2624. [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
  2625. [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
  2626. [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
  2627. [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
  2628. [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
  2629. [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
  2630. [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
  2631. [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
  2632. [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
  2633. [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
  2634. [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
  2635. [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
  2636. [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
  2637. [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
  2638. [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
  2639. [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
  2640. [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
  2641. [EBI2_CLK] = &ebi2_clk.clkr,
  2642. [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
  2643. [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
  2644. [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
  2645. [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
  2646. [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
  2647. [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
  2648. [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
  2649. [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
  2650. [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
  2651. [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
  2652. [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
  2653. [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
  2654. [NSSTCM_CLK] = &nss_tcm_clk.clkr,
  2655. };
  2656. static const struct qcom_reset_map gcc_ipq806x_resets[] = {
  2657. [QDSS_STM_RESET] = { 0x2060, 6 },
  2658. [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
  2659. [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
  2660. [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
  2661. [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
  2662. [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
  2663. [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
  2664. [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
  2665. [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
  2666. [ADM0_C2_RESET] = { 0x220c, 4 },
  2667. [ADM0_C1_RESET] = { 0x220c, 3 },
  2668. [ADM0_C0_RESET] = { 0x220c, 2 },
  2669. [ADM0_PBUS_RESET] = { 0x220c, 1 },
  2670. [ADM0_RESET] = { 0x220c, 0 },
  2671. [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
  2672. [QDSS_POR_RESET] = { 0x2260, 4 },
  2673. [QDSS_TSCTR_RESET] = { 0x2260, 3 },
  2674. [QDSS_HRESET_RESET] = { 0x2260, 2 },
  2675. [QDSS_AXI_RESET] = { 0x2260, 1 },
  2676. [QDSS_DBG_RESET] = { 0x2260, 0 },
  2677. [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
  2678. [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
  2679. [PCIE_EXT_RESET] = { 0x22dc, 6 },
  2680. [PCIE_PHY_RESET] = { 0x22dc, 5 },
  2681. [PCIE_PCI_RESET] = { 0x22dc, 4 },
  2682. [PCIE_POR_RESET] = { 0x22dc, 3 },
  2683. [PCIE_HCLK_RESET] = { 0x22dc, 2 },
  2684. [PCIE_ACLK_RESET] = { 0x22dc, 0 },
  2685. [SFAB_LPASS_RESET] = { 0x23a0, 7 },
  2686. [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
  2687. [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
  2688. [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
  2689. [SFAB_SATA_S_RESET] = { 0x2480, 7 },
  2690. [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
  2691. [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
  2692. [DFAB_SWAY0_RESET] = { 0x2540, 7 },
  2693. [DFAB_SWAY1_RESET] = { 0x2544, 7 },
  2694. [DFAB_ARB0_RESET] = { 0x2560, 7 },
  2695. [DFAB_ARB1_RESET] = { 0x2564, 7 },
  2696. [PPSS_PROC_RESET] = { 0x2594, 1 },
  2697. [PPSS_RESET] = { 0x2594, 0 },
  2698. [DMA_BAM_RESET] = { 0x25c0, 7 },
  2699. [SPS_TIC_H_RESET] = { 0x2600, 7 },
  2700. [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
  2701. [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
  2702. [TSIF_H_RESET] = { 0x2700, 7 },
  2703. [CE1_H_RESET] = { 0x2720, 7 },
  2704. [CE1_CORE_RESET] = { 0x2724, 7 },
  2705. [CE1_SLEEP_RESET] = { 0x2728, 7 },
  2706. [CE2_H_RESET] = { 0x2740, 7 },
  2707. [CE2_CORE_RESET] = { 0x2744, 7 },
  2708. [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
  2709. [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
  2710. [RPM_PROC_RESET] = { 0x27c0, 7 },
  2711. [PMIC_SSBI2_RESET] = { 0x280c, 12 },
  2712. [SDC1_RESET] = { 0x2830, 0 },
  2713. [SDC2_RESET] = { 0x2850, 0 },
  2714. [SDC3_RESET] = { 0x2870, 0 },
  2715. [SDC4_RESET] = { 0x2890, 0 },
  2716. [USB_HS1_RESET] = { 0x2910, 0 },
  2717. [USB_HSIC_RESET] = { 0x2934, 0 },
  2718. [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
  2719. [USB_FS1_RESET] = { 0x2974, 0 },
  2720. [GSBI1_RESET] = { 0x29dc, 0 },
  2721. [GSBI2_RESET] = { 0x29fc, 0 },
  2722. [GSBI3_RESET] = { 0x2a1c, 0 },
  2723. [GSBI4_RESET] = { 0x2a3c, 0 },
  2724. [GSBI5_RESET] = { 0x2a5c, 0 },
  2725. [GSBI6_RESET] = { 0x2a7c, 0 },
  2726. [GSBI7_RESET] = { 0x2a9c, 0 },
  2727. [SPDM_RESET] = { 0x2b6c, 0 },
  2728. [SEC_CTRL_RESET] = { 0x2b80, 7 },
  2729. [TLMM_H_RESET] = { 0x2ba0, 7 },
  2730. [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
  2731. [SATA_RESET] = { 0x2c1c, 0 },
  2732. [TSSC_RESET] = { 0x2ca0, 7 },
  2733. [PDM_RESET] = { 0x2cc0, 12 },
  2734. [MPM_H_RESET] = { 0x2da0, 7 },
  2735. [MPM_RESET] = { 0x2da4, 0 },
  2736. [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
  2737. [PRNG_RESET] = { 0x2e80, 12 },
  2738. [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
  2739. [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
  2740. [CE3_SLEEP_RESET] = { 0x36d0, 7 },
  2741. [PCIE_1_M_RESET] = { 0x3a98, 1 },
  2742. [PCIE_1_S_RESET] = { 0x3a98, 0 },
  2743. [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
  2744. [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
  2745. [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
  2746. [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
  2747. [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
  2748. [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
  2749. [PCIE_2_M_RESET] = { 0x3ad8, 1 },
  2750. [PCIE_2_S_RESET] = { 0x3ad8, 0 },
  2751. [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
  2752. [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
  2753. [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
  2754. [PCIE_2_POR_RESET] = { 0x3adc, 3 },
  2755. [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
  2756. [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
  2757. [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
  2758. [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
  2759. [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
  2760. [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
  2761. [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
  2762. [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
  2763. [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
  2764. [USB30_0_PHY_RESET] = { 0x3b50, 0 },
  2765. [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
  2766. [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
  2767. [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
  2768. [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
  2769. [USB30_1_PHY_RESET] = { 0x3b58, 0 },
  2770. [NSSFB0_RESET] = { 0x3b60, 6 },
  2771. [NSSFB1_RESET] = { 0x3b60, 7 },
  2772. [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
  2773. [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
  2774. [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
  2775. [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
  2776. [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
  2777. [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
  2778. [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
  2779. [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
  2780. [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
  2781. [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
  2782. [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
  2783. [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
  2784. [GMAC_AHB_RESET] = { 0x3e24, 0 },
  2785. [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
  2786. [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
  2787. [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
  2788. [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
  2789. [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
  2790. [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
  2791. [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
  2792. [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
  2793. [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
  2794. [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
  2795. [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
  2796. [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
  2797. [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
  2798. [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
  2799. [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
  2800. [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
  2801. [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
  2802. [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
  2803. [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
  2804. [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
  2805. [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
  2806. [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
  2807. [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
  2808. [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
  2809. [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
  2810. [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
  2811. [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
  2812. [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
  2813. [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
  2814. };
  2815. static const struct regmap_config gcc_ipq806x_regmap_config = {
  2816. .reg_bits = 32,
  2817. .reg_stride = 4,
  2818. .val_bits = 32,
  2819. .max_register = 0x3e40,
  2820. .fast_io = true,
  2821. };
  2822. static const struct qcom_cc_desc gcc_ipq806x_desc = {
  2823. .config = &gcc_ipq806x_regmap_config,
  2824. .clks = gcc_ipq806x_clks,
  2825. .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
  2826. .resets = gcc_ipq806x_resets,
  2827. .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
  2828. };
  2829. static const struct of_device_id gcc_ipq806x_match_table[] = {
  2830. { .compatible = "qcom,gcc-ipq8064" },
  2831. { }
  2832. };
  2833. MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
  2834. static int gcc_ipq806x_probe(struct platform_device *pdev)
  2835. {
  2836. struct device *dev = &pdev->dev;
  2837. struct regmap *regmap;
  2838. int ret;
  2839. ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
  2840. if (ret)
  2841. return ret;
  2842. ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
  2843. if (ret)
  2844. return ret;
  2845. ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
  2846. if (ret)
  2847. return ret;
  2848. regmap = dev_get_regmap(dev, NULL);
  2849. if (!regmap)
  2850. return -ENODEV;
  2851. /* Setup PLL18 static bits */
  2852. regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
  2853. regmap_write(regmap, 0x31b0, 0x3080);
  2854. /* Set GMAC footswitch sleep/wakeup values */
  2855. regmap_write(regmap, 0x3cb8, 8);
  2856. regmap_write(regmap, 0x3cd8, 8);
  2857. regmap_write(regmap, 0x3cf8, 8);
  2858. regmap_write(regmap, 0x3d18, 8);
  2859. return 0;
  2860. }
  2861. static struct platform_driver gcc_ipq806x_driver = {
  2862. .probe = gcc_ipq806x_probe,
  2863. .driver = {
  2864. .name = "gcc-ipq806x",
  2865. .of_match_table = gcc_ipq806x_match_table,
  2866. },
  2867. };
  2868. static int __init gcc_ipq806x_init(void)
  2869. {
  2870. return platform_driver_register(&gcc_ipq806x_driver);
  2871. }
  2872. core_initcall(gcc_ipq806x_init);
  2873. static void __exit gcc_ipq806x_exit(void)
  2874. {
  2875. platform_driver_unregister(&gcc_ipq806x_driver);
  2876. }
  2877. module_exit(gcc_ipq806x_exit);
  2878. MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
  2879. MODULE_LICENSE("GPL v2");
  2880. MODULE_ALIAS("platform:gcc-ipq806x");