gcc-ipq4019.c 32 KB

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  1. /*
  2. * Copyright (c) 2015 The Linux Foundation. All rights reserved.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/err.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_device.h>
  19. #include <linux/clk-provider.h>
  20. #include <linux/regmap.h>
  21. #include <linux/reset-controller.h>
  22. #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
  23. #include "common.h"
  24. #include "clk-regmap.h"
  25. #include "clk-rcg.h"
  26. #include "clk-branch.h"
  27. #include "reset.h"
  28. enum {
  29. P_XO,
  30. P_FEPLL200,
  31. P_FEPLL500,
  32. P_DDRPLL,
  33. P_FEPLLWCSS2G,
  34. P_FEPLLWCSS5G,
  35. P_FEPLL125DLY,
  36. P_DDRPLLAPSS,
  37. };
  38. static struct parent_map gcc_xo_200_500_map[] = {
  39. { P_XO, 0 },
  40. { P_FEPLL200, 1 },
  41. { P_FEPLL500, 2 },
  42. };
  43. static const char * const gcc_xo_200_500[] = {
  44. "xo",
  45. "fepll200",
  46. "fepll500",
  47. };
  48. static struct parent_map gcc_xo_200_map[] = {
  49. { P_XO, 0 },
  50. { P_FEPLL200, 1 },
  51. };
  52. static const char * const gcc_xo_200[] = {
  53. "xo",
  54. "fepll200",
  55. };
  56. static struct parent_map gcc_xo_200_spi_map[] = {
  57. { P_XO, 0 },
  58. { P_FEPLL200, 2 },
  59. };
  60. static const char * const gcc_xo_200_spi[] = {
  61. "xo",
  62. "fepll200",
  63. };
  64. static struct parent_map gcc_xo_sdcc1_500_map[] = {
  65. { P_XO, 0 },
  66. { P_DDRPLL, 1 },
  67. { P_FEPLL500, 2 },
  68. };
  69. static const char * const gcc_xo_sdcc1_500[] = {
  70. "xo",
  71. "ddrpll",
  72. "fepll500",
  73. };
  74. static struct parent_map gcc_xo_wcss2g_map[] = {
  75. { P_XO, 0 },
  76. { P_FEPLLWCSS2G, 1 },
  77. };
  78. static const char * const gcc_xo_wcss2g[] = {
  79. "xo",
  80. "fepllwcss2g",
  81. };
  82. static struct parent_map gcc_xo_wcss5g_map[] = {
  83. { P_XO, 0 },
  84. { P_FEPLLWCSS5G, 1 },
  85. };
  86. static const char * const gcc_xo_wcss5g[] = {
  87. "xo",
  88. "fepllwcss5g",
  89. };
  90. static struct parent_map gcc_xo_125_dly_map[] = {
  91. { P_XO, 0 },
  92. { P_FEPLL125DLY, 1 },
  93. };
  94. static const char * const gcc_xo_125_dly[] = {
  95. "xo",
  96. "fepll125dly",
  97. };
  98. static struct parent_map gcc_xo_ddr_500_200_map[] = {
  99. { P_XO, 0 },
  100. { P_FEPLL200, 3 },
  101. { P_FEPLL500, 2 },
  102. { P_DDRPLLAPSS, 1 },
  103. };
  104. static const char * const gcc_xo_ddr_500_200[] = {
  105. "xo",
  106. "fepll200",
  107. "fepll500",
  108. "ddrpllapss",
  109. };
  110. #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  111. static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
  112. F(48000000, P_XO, 1, 0, 0),
  113. F(200000000, P_FEPLL200, 1, 0, 0),
  114. { }
  115. };
  116. static struct clk_rcg2 audio_clk_src = {
  117. .cmd_rcgr = 0x1b000,
  118. .hid_width = 5,
  119. .parent_map = gcc_xo_200_map,
  120. .freq_tbl = ftbl_gcc_audio_pwm_clk,
  121. .clkr.hw.init = &(struct clk_init_data){
  122. .name = "audio_clk_src",
  123. .parent_names = gcc_xo_200,
  124. .num_parents = 2,
  125. .ops = &clk_rcg2_ops,
  126. },
  127. };
  128. static struct clk_branch gcc_audio_ahb_clk = {
  129. .halt_reg = 0x1b010,
  130. .clkr = {
  131. .enable_reg = 0x1b010,
  132. .enable_mask = BIT(0),
  133. .hw.init = &(struct clk_init_data){
  134. .name = "gcc_audio_ahb_clk",
  135. .parent_names = (const char *[]){
  136. "pcnoc_clk_src",
  137. },
  138. .flags = CLK_SET_RATE_PARENT,
  139. .num_parents = 1,
  140. .ops = &clk_branch2_ops,
  141. },
  142. },
  143. };
  144. static struct clk_branch gcc_audio_pwm_clk = {
  145. .halt_reg = 0x1b00C,
  146. .clkr = {
  147. .enable_reg = 0x1b00C,
  148. .enable_mask = BIT(0),
  149. .hw.init = &(struct clk_init_data){
  150. .name = "gcc_audio_pwm_clk",
  151. .parent_names = (const char *[]){
  152. "audio_clk_src",
  153. },
  154. .flags = CLK_SET_RATE_PARENT,
  155. .num_parents = 1,
  156. .ops = &clk_branch2_ops,
  157. },
  158. },
  159. };
  160. static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = {
  161. F(19200000, P_XO, 1, 2, 5),
  162. F(24000000, P_XO, 1, 1, 2),
  163. { }
  164. };
  165. static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
  166. .cmd_rcgr = 0x200c,
  167. .hid_width = 5,
  168. .parent_map = gcc_xo_200_map,
  169. .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
  170. .clkr.hw.init = &(struct clk_init_data){
  171. .name = "blsp1_qup1_i2c_apps_clk_src",
  172. .parent_names = gcc_xo_200,
  173. .num_parents = 2,
  174. .ops = &clk_rcg2_ops,
  175. },
  176. };
  177. static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
  178. .halt_reg = 0x2008,
  179. .clkr = {
  180. .enable_reg = 0x2008,
  181. .enable_mask = BIT(0),
  182. .hw.init = &(struct clk_init_data){
  183. .name = "gcc_blsp1_qup1_i2c_apps_clk",
  184. .parent_names = (const char *[]){
  185. "blsp1_qup1_i2c_apps_clk_src",
  186. },
  187. .num_parents = 1,
  188. .ops = &clk_branch2_ops,
  189. .flags = CLK_SET_RATE_PARENT,
  190. },
  191. },
  192. };
  193. static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
  194. .cmd_rcgr = 0x3000,
  195. .hid_width = 5,
  196. .parent_map = gcc_xo_200_map,
  197. .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
  198. .clkr.hw.init = &(struct clk_init_data){
  199. .name = "blsp1_qup2_i2c_apps_clk_src",
  200. .parent_names = gcc_xo_200,
  201. .num_parents = 2,
  202. .ops = &clk_rcg2_ops,
  203. },
  204. };
  205. static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
  206. .halt_reg = 0x3010,
  207. .clkr = {
  208. .enable_reg = 0x3010,
  209. .enable_mask = BIT(0),
  210. .hw.init = &(struct clk_init_data){
  211. .name = "gcc_blsp1_qup2_i2c_apps_clk",
  212. .parent_names = (const char *[]){
  213. "blsp1_qup2_i2c_apps_clk_src",
  214. },
  215. .num_parents = 1,
  216. .ops = &clk_branch2_ops,
  217. .flags = CLK_SET_RATE_PARENT,
  218. },
  219. },
  220. };
  221. static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_spi_apps_clk[] = {
  222. F(960000, P_XO, 12, 1, 4),
  223. F(4800000, P_XO, 1, 1, 10),
  224. F(9600000, P_XO, 1, 1, 5),
  225. F(15000000, P_XO, 1, 1, 3),
  226. F(19200000, P_XO, 1, 2, 5),
  227. F(24000000, P_XO, 1, 1, 2),
  228. F(48000000, P_XO, 1, 0, 0),
  229. { }
  230. };
  231. static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
  232. .cmd_rcgr = 0x2024,
  233. .mnd_width = 8,
  234. .hid_width = 5,
  235. .parent_map = gcc_xo_200_spi_map,
  236. .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
  237. .clkr.hw.init = &(struct clk_init_data){
  238. .name = "blsp1_qup1_spi_apps_clk_src",
  239. .parent_names = gcc_xo_200_spi,
  240. .num_parents = 2,
  241. .ops = &clk_rcg2_ops,
  242. },
  243. };
  244. static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
  245. .halt_reg = 0x2004,
  246. .clkr = {
  247. .enable_reg = 0x2004,
  248. .enable_mask = BIT(0),
  249. .hw.init = &(struct clk_init_data){
  250. .name = "gcc_blsp1_qup1_spi_apps_clk",
  251. .parent_names = (const char *[]){
  252. "blsp1_qup1_spi_apps_clk_src",
  253. },
  254. .num_parents = 1,
  255. .ops = &clk_branch2_ops,
  256. .flags = CLK_SET_RATE_PARENT,
  257. },
  258. },
  259. };
  260. static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
  261. .cmd_rcgr = 0x3014,
  262. .mnd_width = 8,
  263. .hid_width = 5,
  264. .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
  265. .parent_map = gcc_xo_200_spi_map,
  266. .clkr.hw.init = &(struct clk_init_data){
  267. .name = "blsp1_qup2_spi_apps_clk_src",
  268. .parent_names = gcc_xo_200_spi,
  269. .num_parents = 2,
  270. .ops = &clk_rcg2_ops,
  271. },
  272. };
  273. static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
  274. .halt_reg = 0x300c,
  275. .clkr = {
  276. .enable_reg = 0x300c,
  277. .enable_mask = BIT(0),
  278. .hw.init = &(struct clk_init_data){
  279. .name = "gcc_blsp1_qup2_spi_apps_clk",
  280. .parent_names = (const char *[]){
  281. "blsp1_qup2_spi_apps_clk_src",
  282. },
  283. .num_parents = 1,
  284. .ops = &clk_branch2_ops,
  285. .flags = CLK_SET_RATE_PARENT,
  286. },
  287. },
  288. };
  289. static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = {
  290. F(1843200, P_FEPLL200, 1, 144, 15625),
  291. F(3686400, P_FEPLL200, 1, 288, 15625),
  292. F(7372800, P_FEPLL200, 1, 576, 15625),
  293. F(14745600, P_FEPLL200, 1, 1152, 15625),
  294. F(16000000, P_FEPLL200, 1, 2, 25),
  295. F(24000000, P_XO, 1, 1, 2),
  296. F(32000000, P_FEPLL200, 1, 4, 25),
  297. F(40000000, P_FEPLL200, 1, 1, 5),
  298. F(46400000, P_FEPLL200, 1, 29, 125),
  299. F(48000000, P_XO, 1, 0, 0),
  300. { }
  301. };
  302. static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
  303. .cmd_rcgr = 0x2044,
  304. .mnd_width = 16,
  305. .hid_width = 5,
  306. .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
  307. .parent_map = gcc_xo_200_spi_map,
  308. .clkr.hw.init = &(struct clk_init_data){
  309. .name = "blsp1_uart1_apps_clk_src",
  310. .parent_names = gcc_xo_200_spi,
  311. .num_parents = 2,
  312. .ops = &clk_rcg2_ops,
  313. },
  314. };
  315. static struct clk_branch gcc_blsp1_uart1_apps_clk = {
  316. .halt_reg = 0x203c,
  317. .clkr = {
  318. .enable_reg = 0x203c,
  319. .enable_mask = BIT(0),
  320. .hw.init = &(struct clk_init_data){
  321. .name = "gcc_blsp1_uart1_apps_clk",
  322. .parent_names = (const char *[]){
  323. "blsp1_uart1_apps_clk_src",
  324. },
  325. .flags = CLK_SET_RATE_PARENT,
  326. .num_parents = 1,
  327. .ops = &clk_branch2_ops,
  328. },
  329. },
  330. };
  331. static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
  332. .cmd_rcgr = 0x3034,
  333. .mnd_width = 16,
  334. .hid_width = 5,
  335. .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
  336. .parent_map = gcc_xo_200_spi_map,
  337. .clkr.hw.init = &(struct clk_init_data){
  338. .name = "blsp1_uart2_apps_clk_src",
  339. .parent_names = gcc_xo_200_spi,
  340. .num_parents = 2,
  341. .ops = &clk_rcg2_ops,
  342. },
  343. };
  344. static struct clk_branch gcc_blsp1_uart2_apps_clk = {
  345. .halt_reg = 0x302c,
  346. .clkr = {
  347. .enable_reg = 0x302c,
  348. .enable_mask = BIT(0),
  349. .hw.init = &(struct clk_init_data){
  350. .name = "gcc_blsp1_uart2_apps_clk",
  351. .parent_names = (const char *[]){
  352. "blsp1_uart2_apps_clk_src",
  353. },
  354. .num_parents = 1,
  355. .ops = &clk_branch2_ops,
  356. .flags = CLK_SET_RATE_PARENT,
  357. },
  358. },
  359. };
  360. static const struct freq_tbl ftbl_gcc_gp_clk[] = {
  361. F(1250000, P_FEPLL200, 1, 16, 0),
  362. F(2500000, P_FEPLL200, 1, 8, 0),
  363. F(5000000, P_FEPLL200, 1, 4, 0),
  364. { }
  365. };
  366. static struct clk_rcg2 gp1_clk_src = {
  367. .cmd_rcgr = 0x8004,
  368. .mnd_width = 8,
  369. .hid_width = 5,
  370. .freq_tbl = ftbl_gcc_gp_clk,
  371. .parent_map = gcc_xo_200_map,
  372. .clkr.hw.init = &(struct clk_init_data){
  373. .name = "gp1_clk_src",
  374. .parent_names = gcc_xo_200,
  375. .num_parents = 2,
  376. .ops = &clk_rcg2_ops,
  377. },
  378. };
  379. static struct clk_branch gcc_gp1_clk = {
  380. .halt_reg = 0x8000,
  381. .clkr = {
  382. .enable_reg = 0x8000,
  383. .enable_mask = BIT(0),
  384. .hw.init = &(struct clk_init_data){
  385. .name = "gcc_gp1_clk",
  386. .parent_names = (const char *[]){
  387. "gp1_clk_src",
  388. },
  389. .num_parents = 1,
  390. .ops = &clk_branch2_ops,
  391. .flags = CLK_SET_RATE_PARENT,
  392. },
  393. },
  394. };
  395. static struct clk_rcg2 gp2_clk_src = {
  396. .cmd_rcgr = 0x9004,
  397. .mnd_width = 8,
  398. .hid_width = 5,
  399. .freq_tbl = ftbl_gcc_gp_clk,
  400. .parent_map = gcc_xo_200_map,
  401. .clkr.hw.init = &(struct clk_init_data){
  402. .name = "gp2_clk_src",
  403. .parent_names = gcc_xo_200,
  404. .num_parents = 2,
  405. .ops = &clk_rcg2_ops,
  406. },
  407. };
  408. static struct clk_branch gcc_gp2_clk = {
  409. .halt_reg = 0x9000,
  410. .clkr = {
  411. .enable_reg = 0x9000,
  412. .enable_mask = BIT(0),
  413. .hw.init = &(struct clk_init_data){
  414. .name = "gcc_gp2_clk",
  415. .parent_names = (const char *[]){
  416. "gp2_clk_src",
  417. },
  418. .num_parents = 1,
  419. .ops = &clk_branch2_ops,
  420. .flags = CLK_SET_RATE_PARENT,
  421. },
  422. },
  423. };
  424. static struct clk_rcg2 gp3_clk_src = {
  425. .cmd_rcgr = 0xa004,
  426. .mnd_width = 8,
  427. .hid_width = 5,
  428. .freq_tbl = ftbl_gcc_gp_clk,
  429. .parent_map = gcc_xo_200_map,
  430. .clkr.hw.init = &(struct clk_init_data){
  431. .name = "gp3_clk_src",
  432. .parent_names = gcc_xo_200,
  433. .num_parents = 2,
  434. .ops = &clk_rcg2_ops,
  435. },
  436. };
  437. static struct clk_branch gcc_gp3_clk = {
  438. .halt_reg = 0xa000,
  439. .clkr = {
  440. .enable_reg = 0xa000,
  441. .enable_mask = BIT(0),
  442. .hw.init = &(struct clk_init_data){
  443. .name = "gcc_gp3_clk",
  444. .parent_names = (const char *[]){
  445. "gp3_clk_src",
  446. },
  447. .num_parents = 1,
  448. .ops = &clk_branch2_ops,
  449. .flags = CLK_SET_RATE_PARENT,
  450. },
  451. },
  452. };
  453. static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
  454. F(144000, P_XO, 1, 3, 240),
  455. F(400000, P_XO, 1, 1, 0),
  456. F(20000000, P_FEPLL500, 1, 1, 25),
  457. F(25000000, P_FEPLL500, 1, 1, 20),
  458. F(50000000, P_FEPLL500, 1, 1, 10),
  459. F(100000000, P_FEPLL500, 1, 1, 5),
  460. F(193000000, P_DDRPLL, 1, 0, 0),
  461. { }
  462. };
  463. static struct clk_rcg2 sdcc1_apps_clk_src = {
  464. .cmd_rcgr = 0x18004,
  465. .hid_width = 5,
  466. .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
  467. .parent_map = gcc_xo_sdcc1_500_map,
  468. .clkr.hw.init = &(struct clk_init_data){
  469. .name = "sdcc1_apps_clk_src",
  470. .parent_names = gcc_xo_sdcc1_500,
  471. .num_parents = 3,
  472. .ops = &clk_rcg2_ops,
  473. .flags = CLK_SET_RATE_PARENT,
  474. },
  475. };
  476. static const struct freq_tbl ftbl_gcc_apps_clk[] = {
  477. F(48000000, P_XO, 1, 0, 0),
  478. F(200000000, P_FEPLL200, 1, 0, 0),
  479. F(500000000, P_FEPLL500, 1, 0, 0),
  480. F(626000000, P_DDRPLLAPSS, 1, 0, 0),
  481. { }
  482. };
  483. static struct clk_rcg2 apps_clk_src = {
  484. .cmd_rcgr = 0x1900c,
  485. .hid_width = 5,
  486. .freq_tbl = ftbl_gcc_apps_clk,
  487. .parent_map = gcc_xo_ddr_500_200_map,
  488. .clkr.hw.init = &(struct clk_init_data){
  489. .name = "apps_clk_src",
  490. .parent_names = gcc_xo_ddr_500_200,
  491. .num_parents = 4,
  492. .ops = &clk_rcg2_ops,
  493. },
  494. };
  495. static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = {
  496. F(48000000, P_XO, 1, 0, 0),
  497. F(100000000, P_FEPLL200, 2, 0, 0),
  498. { }
  499. };
  500. static struct clk_rcg2 apps_ahb_clk_src = {
  501. .cmd_rcgr = 0x19014,
  502. .hid_width = 5,
  503. .parent_map = gcc_xo_200_500_map,
  504. .freq_tbl = ftbl_gcc_apps_ahb_clk,
  505. .clkr.hw.init = &(struct clk_init_data){
  506. .name = "apps_ahb_clk_src",
  507. .parent_names = gcc_xo_200_500,
  508. .num_parents = 3,
  509. .ops = &clk_rcg2_ops,
  510. },
  511. };
  512. static struct clk_branch gcc_apss_ahb_clk = {
  513. .halt_reg = 0x19004,
  514. .halt_check = BRANCH_HALT_VOTED,
  515. .clkr = {
  516. .enable_reg = 0x6000,
  517. .enable_mask = BIT(14),
  518. .hw.init = &(struct clk_init_data){
  519. .name = "gcc_apss_ahb_clk",
  520. .parent_names = (const char *[]){
  521. "apps_ahb_clk_src",
  522. },
  523. .num_parents = 1,
  524. .ops = &clk_branch2_ops,
  525. .flags = CLK_SET_RATE_PARENT,
  526. },
  527. },
  528. };
  529. static struct clk_branch gcc_blsp1_ahb_clk = {
  530. .halt_reg = 0x1008,
  531. .halt_check = BRANCH_HALT_VOTED,
  532. .clkr = {
  533. .enable_reg = 0x6000,
  534. .enable_mask = BIT(10),
  535. .hw.init = &(struct clk_init_data){
  536. .name = "gcc_blsp1_ahb_clk",
  537. .parent_names = (const char *[]){
  538. "pcnoc_clk_src",
  539. },
  540. .num_parents = 1,
  541. .ops = &clk_branch2_ops,
  542. },
  543. },
  544. };
  545. static struct clk_branch gcc_dcd_xo_clk = {
  546. .halt_reg = 0x2103c,
  547. .clkr = {
  548. .enable_reg = 0x2103c,
  549. .enable_mask = BIT(0),
  550. .hw.init = &(struct clk_init_data){
  551. .name = "gcc_dcd_xo_clk",
  552. .parent_names = (const char *[]){
  553. "xo",
  554. },
  555. .num_parents = 1,
  556. .ops = &clk_branch2_ops,
  557. },
  558. },
  559. };
  560. static struct clk_branch gcc_boot_rom_ahb_clk = {
  561. .halt_reg = 0x1300c,
  562. .clkr = {
  563. .enable_reg = 0x1300c,
  564. .enable_mask = BIT(0),
  565. .hw.init = &(struct clk_init_data){
  566. .name = "gcc_boot_rom_ahb_clk",
  567. .parent_names = (const char *[]){
  568. "pcnoc_clk_src",
  569. },
  570. .num_parents = 1,
  571. .ops = &clk_branch2_ops,
  572. .flags = CLK_SET_RATE_PARENT,
  573. },
  574. },
  575. };
  576. static struct clk_branch gcc_crypto_ahb_clk = {
  577. .halt_reg = 0x16024,
  578. .halt_check = BRANCH_HALT_VOTED,
  579. .clkr = {
  580. .enable_reg = 0x6000,
  581. .enable_mask = BIT(0),
  582. .hw.init = &(struct clk_init_data){
  583. .name = "gcc_crypto_ahb_clk",
  584. .parent_names = (const char *[]){
  585. "pcnoc_clk_src",
  586. },
  587. .num_parents = 1,
  588. .ops = &clk_branch2_ops,
  589. },
  590. },
  591. };
  592. static struct clk_branch gcc_crypto_axi_clk = {
  593. .halt_reg = 0x16020,
  594. .halt_check = BRANCH_HALT_VOTED,
  595. .clkr = {
  596. .enable_reg = 0x6000,
  597. .enable_mask = BIT(1),
  598. .hw.init = &(struct clk_init_data){
  599. .name = "gcc_crypto_axi_clk",
  600. .parent_names = (const char *[]){
  601. "fepll125",
  602. },
  603. .num_parents = 1,
  604. .ops = &clk_branch2_ops,
  605. },
  606. },
  607. };
  608. static struct clk_branch gcc_crypto_clk = {
  609. .halt_reg = 0x1601c,
  610. .halt_check = BRANCH_HALT_VOTED,
  611. .clkr = {
  612. .enable_reg = 0x6000,
  613. .enable_mask = BIT(2),
  614. .hw.init = &(struct clk_init_data){
  615. .name = "gcc_crypto_clk",
  616. .parent_names = (const char *[]){
  617. "fepll125",
  618. },
  619. .num_parents = 1,
  620. .ops = &clk_branch2_ops,
  621. },
  622. },
  623. };
  624. static struct clk_branch gcc_ess_clk = {
  625. .halt_reg = 0x12010,
  626. .clkr = {
  627. .enable_reg = 0x12010,
  628. .enable_mask = BIT(0),
  629. .hw.init = &(struct clk_init_data){
  630. .name = "gcc_ess_clk",
  631. .parent_names = (const char *[]){
  632. "fephy_125m_dly_clk_src",
  633. },
  634. .num_parents = 1,
  635. .ops = &clk_branch2_ops,
  636. .flags = CLK_SET_RATE_PARENT,
  637. },
  638. },
  639. };
  640. static struct clk_branch gcc_imem_axi_clk = {
  641. .halt_reg = 0xe004,
  642. .halt_check = BRANCH_HALT_VOTED,
  643. .clkr = {
  644. .enable_reg = 0x6000,
  645. .enable_mask = BIT(17),
  646. .hw.init = &(struct clk_init_data){
  647. .name = "gcc_imem_axi_clk",
  648. .parent_names = (const char *[]){
  649. "fepll200",
  650. },
  651. .num_parents = 1,
  652. .ops = &clk_branch2_ops,
  653. },
  654. },
  655. };
  656. static struct clk_branch gcc_imem_cfg_ahb_clk = {
  657. .halt_reg = 0xe008,
  658. .clkr = {
  659. .enable_reg = 0xe008,
  660. .enable_mask = BIT(0),
  661. .hw.init = &(struct clk_init_data){
  662. .name = "gcc_imem_cfg_ahb_clk",
  663. .parent_names = (const char *[]){
  664. "pcnoc_clk_src",
  665. },
  666. .num_parents = 1,
  667. .ops = &clk_branch2_ops,
  668. },
  669. },
  670. };
  671. static struct clk_branch gcc_pcie_ahb_clk = {
  672. .halt_reg = 0x1d00c,
  673. .clkr = {
  674. .enable_reg = 0x1d00c,
  675. .enable_mask = BIT(0),
  676. .hw.init = &(struct clk_init_data){
  677. .name = "gcc_pcie_ahb_clk",
  678. .parent_names = (const char *[]){
  679. "pcnoc_clk_src",
  680. },
  681. .num_parents = 1,
  682. .ops = &clk_branch2_ops,
  683. },
  684. },
  685. };
  686. static struct clk_branch gcc_pcie_axi_m_clk = {
  687. .halt_reg = 0x1d004,
  688. .clkr = {
  689. .enable_reg = 0x1d004,
  690. .enable_mask = BIT(0),
  691. .hw.init = &(struct clk_init_data){
  692. .name = "gcc_pcie_axi_m_clk",
  693. .parent_names = (const char *[]){
  694. "fepll200",
  695. },
  696. .num_parents = 1,
  697. .ops = &clk_branch2_ops,
  698. },
  699. },
  700. };
  701. static struct clk_branch gcc_pcie_axi_s_clk = {
  702. .halt_reg = 0x1d008,
  703. .clkr = {
  704. .enable_reg = 0x1d008,
  705. .enable_mask = BIT(0),
  706. .hw.init = &(struct clk_init_data){
  707. .name = "gcc_pcie_axi_s_clk",
  708. .parent_names = (const char *[]){
  709. "fepll200",
  710. },
  711. .num_parents = 1,
  712. .ops = &clk_branch2_ops,
  713. },
  714. },
  715. };
  716. static struct clk_branch gcc_prng_ahb_clk = {
  717. .halt_reg = 0x13004,
  718. .halt_check = BRANCH_HALT_VOTED,
  719. .clkr = {
  720. .enable_reg = 0x6000,
  721. .enable_mask = BIT(8),
  722. .hw.init = &(struct clk_init_data){
  723. .name = "gcc_prng_ahb_clk",
  724. .parent_names = (const char *[]){
  725. "pcnoc_clk_src",
  726. },
  727. .num_parents = 1,
  728. .ops = &clk_branch2_ops,
  729. },
  730. },
  731. };
  732. static struct clk_branch gcc_qpic_ahb_clk = {
  733. .halt_reg = 0x1c008,
  734. .clkr = {
  735. .enable_reg = 0x1c008,
  736. .enable_mask = BIT(0),
  737. .hw.init = &(struct clk_init_data){
  738. .name = "gcc_qpic_ahb_clk",
  739. .parent_names = (const char *[]){
  740. "pcnoc_clk_src",
  741. },
  742. .num_parents = 1,
  743. .ops = &clk_branch2_ops,
  744. },
  745. },
  746. };
  747. static struct clk_branch gcc_qpic_clk = {
  748. .halt_reg = 0x1c004,
  749. .clkr = {
  750. .enable_reg = 0x1c004,
  751. .enable_mask = BIT(0),
  752. .hw.init = &(struct clk_init_data){
  753. .name = "gcc_qpic_clk",
  754. .parent_names = (const char *[]){
  755. "pcnoc_clk_src",
  756. },
  757. .num_parents = 1,
  758. .ops = &clk_branch2_ops,
  759. },
  760. },
  761. };
  762. static struct clk_branch gcc_sdcc1_ahb_clk = {
  763. .halt_reg = 0x18010,
  764. .clkr = {
  765. .enable_reg = 0x18010,
  766. .enable_mask = BIT(0),
  767. .hw.init = &(struct clk_init_data){
  768. .name = "gcc_sdcc1_ahb_clk",
  769. .parent_names = (const char *[]){
  770. "pcnoc_clk_src",
  771. },
  772. .num_parents = 1,
  773. .ops = &clk_branch2_ops,
  774. },
  775. },
  776. };
  777. static struct clk_branch gcc_sdcc1_apps_clk = {
  778. .halt_reg = 0x1800c,
  779. .clkr = {
  780. .enable_reg = 0x1800c,
  781. .enable_mask = BIT(0),
  782. .hw.init = &(struct clk_init_data){
  783. .name = "gcc_sdcc1_apps_clk",
  784. .parent_names = (const char *[]){
  785. "sdcc1_apps_clk_src",
  786. },
  787. .num_parents = 1,
  788. .ops = &clk_branch2_ops,
  789. .flags = CLK_SET_RATE_PARENT,
  790. },
  791. },
  792. };
  793. static struct clk_branch gcc_tlmm_ahb_clk = {
  794. .halt_reg = 0x5004,
  795. .halt_check = BRANCH_HALT_VOTED,
  796. .clkr = {
  797. .enable_reg = 0x6000,
  798. .enable_mask = BIT(5),
  799. .hw.init = &(struct clk_init_data){
  800. .name = "gcc_tlmm_ahb_clk",
  801. .parent_names = (const char *[]){
  802. "pcnoc_clk_src",
  803. },
  804. .num_parents = 1,
  805. .ops = &clk_branch2_ops,
  806. },
  807. },
  808. };
  809. static struct clk_branch gcc_usb2_master_clk = {
  810. .halt_reg = 0x1e00c,
  811. .clkr = {
  812. .enable_reg = 0x1e00c,
  813. .enable_mask = BIT(0),
  814. .hw.init = &(struct clk_init_data){
  815. .name = "gcc_usb2_master_clk",
  816. .parent_names = (const char *[]){
  817. "pcnoc_clk_src",
  818. },
  819. .num_parents = 1,
  820. .ops = &clk_branch2_ops,
  821. },
  822. },
  823. };
  824. static struct clk_branch gcc_usb2_sleep_clk = {
  825. .halt_reg = 0x1e010,
  826. .clkr = {
  827. .enable_reg = 0x1e010,
  828. .enable_mask = BIT(0),
  829. .hw.init = &(struct clk_init_data){
  830. .name = "gcc_usb2_sleep_clk",
  831. .parent_names = (const char *[]){
  832. "gcc_sleep_clk_src",
  833. },
  834. .num_parents = 1,
  835. .ops = &clk_branch2_ops,
  836. },
  837. },
  838. };
  839. static struct clk_branch gcc_usb2_mock_utmi_clk = {
  840. .halt_reg = 0x1e014,
  841. .clkr = {
  842. .enable_reg = 0x1e014,
  843. .enable_mask = BIT(0),
  844. .hw.init = &(struct clk_init_data){
  845. .name = "gcc_usb2_mock_utmi_clk",
  846. .parent_names = (const char *[]){
  847. "usb30_mock_utmi_clk_src",
  848. },
  849. .num_parents = 1,
  850. .ops = &clk_branch2_ops,
  851. .flags = CLK_SET_RATE_PARENT,
  852. },
  853. },
  854. };
  855. static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
  856. F(2000000, P_FEPLL200, 10, 0, 0),
  857. { }
  858. };
  859. static struct clk_rcg2 usb30_mock_utmi_clk_src = {
  860. .cmd_rcgr = 0x1e000,
  861. .hid_width = 5,
  862. .parent_map = gcc_xo_200_map,
  863. .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
  864. .clkr.hw.init = &(struct clk_init_data){
  865. .name = "usb30_mock_utmi_clk_src",
  866. .parent_names = gcc_xo_200,
  867. .num_parents = 2,
  868. .ops = &clk_rcg2_ops,
  869. },
  870. };
  871. static struct clk_branch gcc_usb3_master_clk = {
  872. .halt_reg = 0x1e028,
  873. .clkr = {
  874. .enable_reg = 0x1e028,
  875. .enable_mask = BIT(0),
  876. .hw.init = &(struct clk_init_data){
  877. .name = "gcc_usb3_master_clk",
  878. .parent_names = (const char *[]){
  879. "fepll125",
  880. },
  881. .num_parents = 1,
  882. .ops = &clk_branch2_ops,
  883. },
  884. },
  885. };
  886. static struct clk_branch gcc_usb3_sleep_clk = {
  887. .halt_reg = 0x1e02C,
  888. .clkr = {
  889. .enable_reg = 0x1e02C,
  890. .enable_mask = BIT(0),
  891. .hw.init = &(struct clk_init_data){
  892. .name = "gcc_usb3_sleep_clk",
  893. .parent_names = (const char *[]){
  894. "gcc_sleep_clk_src",
  895. },
  896. .num_parents = 1,
  897. .ops = &clk_branch2_ops,
  898. },
  899. },
  900. };
  901. static struct clk_branch gcc_usb3_mock_utmi_clk = {
  902. .halt_reg = 0x1e030,
  903. .clkr = {
  904. .enable_reg = 0x1e030,
  905. .enable_mask = BIT(0),
  906. .hw.init = &(struct clk_init_data){
  907. .name = "gcc_usb3_mock_utmi_clk",
  908. .parent_names = (const char *[]){
  909. "usb30_mock_utmi_clk_src",
  910. },
  911. .num_parents = 1,
  912. .ops = &clk_branch2_ops,
  913. .flags = CLK_SET_RATE_PARENT,
  914. },
  915. },
  916. };
  917. static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = {
  918. F(125000000, P_FEPLL125DLY, 1, 0, 0),
  919. { }
  920. };
  921. static struct clk_rcg2 fephy_125m_dly_clk_src = {
  922. .cmd_rcgr = 0x12000,
  923. .hid_width = 5,
  924. .parent_map = gcc_xo_125_dly_map,
  925. .freq_tbl = ftbl_gcc_fephy_dly_clk,
  926. .clkr.hw.init = &(struct clk_init_data){
  927. .name = "fephy_125m_dly_clk_src",
  928. .parent_names = gcc_xo_125_dly,
  929. .num_parents = 2,
  930. .ops = &clk_rcg2_ops,
  931. },
  932. };
  933. static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = {
  934. F(48000000, P_XO, 1, 0, 0),
  935. F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
  936. { }
  937. };
  938. static struct clk_rcg2 wcss2g_clk_src = {
  939. .cmd_rcgr = 0x1f000,
  940. .hid_width = 5,
  941. .freq_tbl = ftbl_gcc_wcss2g_clk,
  942. .parent_map = gcc_xo_wcss2g_map,
  943. .clkr.hw.init = &(struct clk_init_data){
  944. .name = "wcss2g_clk_src",
  945. .parent_names = gcc_xo_wcss2g,
  946. .num_parents = 2,
  947. .ops = &clk_rcg2_ops,
  948. .flags = CLK_SET_RATE_PARENT,
  949. },
  950. };
  951. static struct clk_branch gcc_wcss2g_clk = {
  952. .halt_reg = 0x1f00C,
  953. .clkr = {
  954. .enable_reg = 0x1f00C,
  955. .enable_mask = BIT(0),
  956. .hw.init = &(struct clk_init_data){
  957. .name = "gcc_wcss2g_clk",
  958. .parent_names = (const char *[]){
  959. "wcss2g_clk_src",
  960. },
  961. .num_parents = 1,
  962. .ops = &clk_branch2_ops,
  963. .flags = CLK_SET_RATE_PARENT,
  964. },
  965. },
  966. };
  967. static struct clk_branch gcc_wcss2g_ref_clk = {
  968. .halt_reg = 0x1f00C,
  969. .clkr = {
  970. .enable_reg = 0x1f00C,
  971. .enable_mask = BIT(0),
  972. .hw.init = &(struct clk_init_data){
  973. .name = "gcc_wcss2g_ref_clk",
  974. .parent_names = (const char *[]){
  975. "xo",
  976. },
  977. .num_parents = 1,
  978. .ops = &clk_branch2_ops,
  979. .flags = CLK_SET_RATE_PARENT,
  980. },
  981. },
  982. };
  983. static struct clk_branch gcc_wcss2g_rtc_clk = {
  984. .halt_reg = 0x1f010,
  985. .clkr = {
  986. .enable_reg = 0x1f010,
  987. .enable_mask = BIT(0),
  988. .hw.init = &(struct clk_init_data){
  989. .name = "gcc_wcss2g_rtc_clk",
  990. .parent_names = (const char *[]){
  991. "gcc_sleep_clk_src",
  992. },
  993. .num_parents = 1,
  994. .ops = &clk_branch2_ops,
  995. },
  996. },
  997. };
  998. static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = {
  999. F(48000000, P_XO, 1, 0, 0),
  1000. F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
  1001. { }
  1002. };
  1003. static struct clk_rcg2 wcss5g_clk_src = {
  1004. .cmd_rcgr = 0x20000,
  1005. .hid_width = 5,
  1006. .parent_map = gcc_xo_wcss5g_map,
  1007. .freq_tbl = ftbl_gcc_wcss5g_clk,
  1008. .clkr.hw.init = &(struct clk_init_data){
  1009. .name = "wcss5g_clk_src",
  1010. .parent_names = gcc_xo_wcss5g,
  1011. .num_parents = 2,
  1012. .ops = &clk_rcg2_ops,
  1013. },
  1014. };
  1015. static struct clk_branch gcc_wcss5g_clk = {
  1016. .halt_reg = 0x2000c,
  1017. .clkr = {
  1018. .enable_reg = 0x2000c,
  1019. .enable_mask = BIT(0),
  1020. .hw.init = &(struct clk_init_data){
  1021. .name = "gcc_wcss5g_clk",
  1022. .parent_names = (const char *[]){
  1023. "wcss5g_clk_src",
  1024. },
  1025. .num_parents = 1,
  1026. .ops = &clk_branch2_ops,
  1027. .flags = CLK_SET_RATE_PARENT,
  1028. },
  1029. },
  1030. };
  1031. static struct clk_branch gcc_wcss5g_ref_clk = {
  1032. .halt_reg = 0x2000c,
  1033. .clkr = {
  1034. .enable_reg = 0x2000c,
  1035. .enable_mask = BIT(0),
  1036. .hw.init = &(struct clk_init_data){
  1037. .name = "gcc_wcss5g_ref_clk",
  1038. .parent_names = (const char *[]){
  1039. "xo",
  1040. },
  1041. .num_parents = 1,
  1042. .ops = &clk_branch2_ops,
  1043. .flags = CLK_SET_RATE_PARENT,
  1044. },
  1045. },
  1046. };
  1047. static struct clk_branch gcc_wcss5g_rtc_clk = {
  1048. .halt_reg = 0x20010,
  1049. .clkr = {
  1050. .enable_reg = 0x20010,
  1051. .enable_mask = BIT(0),
  1052. .hw.init = &(struct clk_init_data){
  1053. .name = "gcc_wcss5g_rtc_clk",
  1054. .parent_names = (const char *[]){
  1055. "gcc_sleep_clk_src",
  1056. },
  1057. .num_parents = 1,
  1058. .ops = &clk_branch2_ops,
  1059. .flags = CLK_SET_RATE_PARENT,
  1060. },
  1061. },
  1062. };
  1063. static struct clk_regmap *gcc_ipq4019_clocks[] = {
  1064. [AUDIO_CLK_SRC] = &audio_clk_src.clkr,
  1065. [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
  1066. [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
  1067. [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
  1068. [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
  1069. [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
  1070. [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
  1071. [GCC_USB3_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
  1072. [GCC_APPS_CLK_SRC] = &apps_clk_src.clkr,
  1073. [GCC_APPS_AHB_CLK_SRC] = &apps_ahb_clk_src.clkr,
  1074. [GP1_CLK_SRC] = &gp1_clk_src.clkr,
  1075. [GP2_CLK_SRC] = &gp2_clk_src.clkr,
  1076. [GP3_CLK_SRC] = &gp3_clk_src.clkr,
  1077. [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
  1078. [FEPHY_125M_DLY_CLK_SRC] = &fephy_125m_dly_clk_src.clkr,
  1079. [WCSS2G_CLK_SRC] = &wcss2g_clk_src.clkr,
  1080. [WCSS5G_CLK_SRC] = &wcss5g_clk_src.clkr,
  1081. [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
  1082. [GCC_AUDIO_AHB_CLK] = &gcc_audio_ahb_clk.clkr,
  1083. [GCC_AUDIO_PWM_CLK] = &gcc_audio_pwm_clk.clkr,
  1084. [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
  1085. [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
  1086. [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
  1087. [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
  1088. [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
  1089. [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
  1090. [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
  1091. [GCC_DCD_XO_CLK] = &gcc_dcd_xo_clk.clkr,
  1092. [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
  1093. [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
  1094. [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
  1095. [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
  1096. [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
  1097. [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
  1098. [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
  1099. [GCC_ESS_CLK] = &gcc_ess_clk.clkr,
  1100. [GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
  1101. [GCC_IMEM_CFG_AHB_CLK] = &gcc_imem_cfg_ahb_clk.clkr,
  1102. [GCC_PCIE_AHB_CLK] = &gcc_pcie_ahb_clk.clkr,
  1103. [GCC_PCIE_AXI_M_CLK] = &gcc_pcie_axi_m_clk.clkr,
  1104. [GCC_PCIE_AXI_S_CLK] = &gcc_pcie_axi_s_clk.clkr,
  1105. [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
  1106. [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
  1107. [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
  1108. [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
  1109. [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
  1110. [GCC_TLMM_AHB_CLK] = &gcc_tlmm_ahb_clk.clkr,
  1111. [GCC_USB2_MASTER_CLK] = &gcc_usb2_master_clk.clkr,
  1112. [GCC_USB2_SLEEP_CLK] = &gcc_usb2_sleep_clk.clkr,
  1113. [GCC_USB2_MOCK_UTMI_CLK] = &gcc_usb2_mock_utmi_clk.clkr,
  1114. [GCC_USB3_MASTER_CLK] = &gcc_usb3_master_clk.clkr,
  1115. [GCC_USB3_SLEEP_CLK] = &gcc_usb3_sleep_clk.clkr,
  1116. [GCC_USB3_MOCK_UTMI_CLK] = &gcc_usb3_mock_utmi_clk.clkr,
  1117. [GCC_WCSS2G_CLK] = &gcc_wcss2g_clk.clkr,
  1118. [GCC_WCSS2G_REF_CLK] = &gcc_wcss2g_ref_clk.clkr,
  1119. [GCC_WCSS2G_RTC_CLK] = &gcc_wcss2g_rtc_clk.clkr,
  1120. [GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr,
  1121. [GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr,
  1122. [GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr,
  1123. };
  1124. static const struct qcom_reset_map gcc_ipq4019_resets[] = {
  1125. [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
  1126. [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
  1127. [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
  1128. [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
  1129. [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
  1130. [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
  1131. [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
  1132. [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
  1133. [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
  1134. [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
  1135. [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
  1136. [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
  1137. [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
  1138. [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
  1139. [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
  1140. [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
  1141. [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
  1142. [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
  1143. [PCIE_AHB_ARES] = { 0x1d010, 10 },
  1144. [PCIE_PWR_ARES] = { 0x1d010, 9 },
  1145. [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
  1146. [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
  1147. [PCIE_PHY_ARES] = { 0x1d010, 6 },
  1148. [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
  1149. [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
  1150. [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
  1151. [PCIE_PIPE_ARES] = { 0x1d010, 2 },
  1152. [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
  1153. [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
  1154. [ESS_RESET] = { 0x12008, 0},
  1155. [GCC_BLSP1_BCR] = {0x01000, 0},
  1156. [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
  1157. [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
  1158. [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
  1159. [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
  1160. [GCC_BIMC_BCR] = {0x04000, 0},
  1161. [GCC_TLMM_BCR] = {0x05000, 0},
  1162. [GCC_IMEM_BCR] = {0x0E000, 0},
  1163. [GCC_ESS_BCR] = {0x12008, 0},
  1164. [GCC_PRNG_BCR] = {0x13000, 0},
  1165. [GCC_BOOT_ROM_BCR] = {0x13008, 0},
  1166. [GCC_CRYPTO_BCR] = {0x16000, 0},
  1167. [GCC_SDCC1_BCR] = {0x18000, 0},
  1168. [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
  1169. [GCC_AUDIO_BCR] = {0x1B008, 0},
  1170. [GCC_QPIC_BCR] = {0x1C000, 0},
  1171. [GCC_PCIE_BCR] = {0x1D000, 0},
  1172. [GCC_USB2_BCR] = {0x1E008, 0},
  1173. [GCC_USB2_PHY_BCR] = {0x1E018, 0},
  1174. [GCC_USB3_BCR] = {0x1E024, 0},
  1175. [GCC_USB3_PHY_BCR] = {0x1E034, 0},
  1176. [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
  1177. [GCC_PCNOC_BCR] = {0x2102C, 0},
  1178. [GCC_DCD_BCR] = {0x21038, 0},
  1179. [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
  1180. [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
  1181. [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
  1182. [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
  1183. [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
  1184. [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
  1185. [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
  1186. [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
  1187. [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
  1188. [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
  1189. [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
  1190. [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
  1191. [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
  1192. [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
  1193. [GCC_TCSR_BCR] = {0x22000, 0},
  1194. [GCC_MPM_BCR] = {0x24000, 0},
  1195. [GCC_SPDM_BCR] = {0x25000, 0},
  1196. };
  1197. static const struct regmap_config gcc_ipq4019_regmap_config = {
  1198. .reg_bits = 32,
  1199. .reg_stride = 4,
  1200. .val_bits = 32,
  1201. .max_register = 0x2dfff,
  1202. .fast_io = true,
  1203. };
  1204. static const struct qcom_cc_desc gcc_ipq4019_desc = {
  1205. .config = &gcc_ipq4019_regmap_config,
  1206. .clks = gcc_ipq4019_clocks,
  1207. .num_clks = ARRAY_SIZE(gcc_ipq4019_clocks),
  1208. .resets = gcc_ipq4019_resets,
  1209. .num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
  1210. };
  1211. static const struct of_device_id gcc_ipq4019_match_table[] = {
  1212. { .compatible = "qcom,gcc-ipq4019" },
  1213. { }
  1214. };
  1215. MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
  1216. static int gcc_ipq4019_probe(struct platform_device *pdev)
  1217. {
  1218. struct device *dev = &pdev->dev;
  1219. clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000);
  1220. clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000);
  1221. clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000);
  1222. clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000);
  1223. clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000);
  1224. clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000);
  1225. clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000);
  1226. return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
  1227. }
  1228. static struct platform_driver gcc_ipq4019_driver = {
  1229. .probe = gcc_ipq4019_probe,
  1230. .driver = {
  1231. .name = "qcom,gcc-ipq4019",
  1232. .of_match_table = gcc_ipq4019_match_table,
  1233. },
  1234. };
  1235. static int __init gcc_ipq4019_init(void)
  1236. {
  1237. return platform_driver_register(&gcc_ipq4019_driver);
  1238. }
  1239. core_initcall(gcc_ipq4019_init);
  1240. static void __exit gcc_ipq4019_exit(void)
  1241. {
  1242. platform_driver_unregister(&gcc_ipq4019_driver);
  1243. }
  1244. module_exit(gcc_ipq4019_exit);
  1245. MODULE_ALIAS("platform:gcc-ipq4019");
  1246. MODULE_LICENSE("GPL v2");
  1247. MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver");