[Improve][AW-Regular][Makefile][AW-Regular am335x-evm.dts]

2022-08-02 / EASON YANG
Action:
1. Improve: Changed configutation dts file for new PMIC.
2. Improve: Chagned configutation for new PMIC TPS65217 definition.

File:
1. [AW-Regular]am335x-evm.dts
Action 1

2. Makefile
Action 2

FIRMWARE VERSION:V0.71.XX.XXXX.PX

Makefile

@@ -547,7 +547,7 @@ AW-Regular-uboot:
 	@echo    Building U-boot
 	@echo ===================================
 	@cp -f $(UBOOT_INSTALL_DIR)/arch/arm/dts/[AW-Regular]am335x-evm.dts $(UBOOT_INSTALL_DIR)/arch/arm/dts/am335x-evm.dts
-	$(MAKE) -j $(MAKE_JOBS) -C $(UBOOT_INSTALL_DIR) CROSS_COMPILE=$(CROSS_COMPILE) FLASH_IC=MT29F8G08_BCH16 DDR_IC=MT41K256M16HA125E_303 PMIC=TPS65910
+	$(MAKE) -j $(MAKE_JOBS) -C $(UBOOT_INSTALL_DIR) CROSS_COMPILE=$(CROSS_COMPILE) FLASH_IC=MT29F8G08_BCH16 DDR_IC=MT41K256M16HA125E_303 PMIC=TPS65217
 	@cp -f $(UBOOT_INSTALL_DIR)/MLO EVSE/Projects/AW-Regular/Images/
 	@cp -f $(UBOOT_INSTALL_DIR)/u-boot.img EVSE/Projects/AW-Regular/Images/
 	@cp -f $(UBOOT_INSTALL_DIR)/spl/u-boot-spl.bin EVSE/Projects/AW-Regular/Images/

board-support/linux-4.9.59+gitAUTOINC+a75d8e9305-ga75d8e9305/arch/arm/boot/dts/[AW-Regular]am335x-evm.dts

@@ -25,7 +25,7 @@
 
 	cpus {
 		cpu@0 {
-			cpu0-supply = <&vdd1_reg>;
+			cpu0-supply = <&dcdc2_reg>;
 		};
 	};
 
@@ -65,7 +65,7 @@
 		
 			/** Offset: 0x800 */
 			/** GPIO 0 */ 
-			0x144 (PIN_INPUT | MUX_MODE7)    			/* RMII1_REF_CLK		=>	GPIO0_29 */	/*USB 0 OCP detection*/
+			0x144 (PIN_INPUT | MUX_MODE7)    		/* RMII1_REF_CLK	=>	GPIO0_29 */	/*USB 0 OCP detection*/
 			0x1B0 (PIN_OUTPUT | MUX_MODE7)			/*XDMA_EVENT_INTR0	=>	GPIO0_19 */	/*AM_RFID_RST*/
 			0x1B4 (PIN_INPUT | MUX_MODE7)			/*XDMA_EVENT_INTR1	=>	GPIO0_20 */	/*AM_RFID_ICC*/
 			/** GPIO 1 */			
@@ -80,6 +80,7 @@
 			0x0E8 (PIN_INPUT | MUX_MODE7)			/*LCD_PCLK	=>	GPIO2_24*/	/*communication board proximity*/
 			0x0E0 (PIN_OUTPUT | MUX_MODE7)			/*LCD_VSYNC	=>	GPIO2_22*/	/*Breath LED*/
 			/** GPIO 3 */
+			0x1A0 (PIN_OUTPUT | MUX_MODE7)          /* MCASP0_AXR1  =>  GPIO3_18 */ /*control 4G reset pin*/
 			0x1A8 (PIN_OUTPUT | MUX_MODE7)			/* MCASP0_AXR1	=>	GPIO3_20 */	/*control MCU to output CP PWM*/
 		>;
 	};
@@ -323,8 +324,8 @@
 	status = "okay";
 	clock-frequency = <400000>;
 
-	tps: tps@2d {
-		reg = <0x2d>;
+	tps: tps@24 {
+		reg = <0x24>;
 	};
 
 /*	rtc0: rtc@51 {
@@ -406,7 +407,7 @@
 	pinctrl-0 = <&nandflash_pins_default>;
 	pinctrl-1 = <&nandflash_pins_sleep>;
 	/*ranges = <0 0 0x08000000 0x10000000>;*/	/* CS0: NAND */
-	ranges = <0 0 0x08000000 0x80000000>;	/*+++ vern,NAND,20181030 ---*/
+	ranges = <0 0 0x08000000 0x40000000>;	/*+++ vern,NAND,20181030 ---*/
 	nand@0,0 {
 		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
@@ -500,85 +501,74 @@
 		};
 		partition@13 {
 			label = "Storage";
-			reg = <0x0A200000 0x75E00000>;
+			reg = <0x0A200000 0x35E00000>;
 		};
 	};
 };
 
-#include "tps65910.dtsi"
+/include/ "tps65217.dtsi"
 
 &tps {
-	vcc1-supply = <&vbat>;
-	vcc2-supply = <&vbat>;
-	vcc3-supply = <&vbat>;
-	vcc4-supply = <&vbat>;
-	vcc5-supply = <&vbat>;
-	vcc6-supply = <&vbat>;
-	vcc7-supply = <&vbat>;
-	vccio-supply = <&vbat>;
+	/*
+	 * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
+	 * mode") at poweroff.  Most BeagleBone versions do not support RTC-only
+	 * mode and risk hardware damage if this mode is entered.
+	 *
+	 * For details, see linux-omap mailing list May 2015 thread
+	 *	[PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
+	 * In particular, messages:
+	 *	http://www.spinics.net/lists/linux-omap/msg118585.html
+	 *	http://www.spinics.net/lists/linux-omap/msg118615.html
+	 *
+	 * You can override this later with
+	 *	&tps {  /delete-property/ ti,pmic-shutdown-controller;  }
+	 * if you want to use RTC-only mode and made sure you are not affected
+	 * by the hardware problems. (Tip: double-check by performing a current
+	 * measurement after shutdown: it should be less than 1 mA.)
+	 */
+	ti,pmic-shutdown-controller;
 
 	regulators {
-		vrtc_reg: regulator@0 {
+		dcdc1_reg: regulator@0 {
+			regulator-name = "vdds_dpr";
 			regulator-always-on;
 		};
 
-		vio_reg: regulator@1 {
-			regulator-always-on;
-		};
-
-		vdd1_reg: regulator@2 {
-			/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
+		dcdc2_reg: regulator@1 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 			regulator-name = "vdd_mpu";
-			regulator-min-microvolt = <912500>;
-			regulator-max-microvolt = <1378000>;
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <1351500>;
 			regulator-boot-on;
 			regulator-always-on;
 		};
 
-		vdd2_reg: regulator@3 {
+		dcdc3_reg: regulator@2 {
 			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 			regulator-name = "vdd_core";
-			regulator-min-microvolt = <912500>;
+			regulator-min-microvolt = <925000>;
 			regulator-max-microvolt = <1150000>;
 			regulator-boot-on;
 			regulator-always-on;
 		};
 
-		vdd3_reg: regulator@4 {
-			regulator-always-on;
-		};
-
-		vdig1_reg: regulator@5 {
+		ldo1_reg: regulator@3 {
+			regulator-name = "vio,vrtc,vdds";
 			regulator-always-on;
 		};
 
-		vdig2_reg: regulator@6 {
+		ldo2_reg: regulator@4 {
+			regulator-name = "vdd_3v3aux";
 			regulator-always-on;
 		};
 
-		vpll_reg: regulator@7 {
+		ldo3_reg: regulator@5 {
+			regulator-name = "vdd_1v8";
 			regulator-always-on;
 		};
 
-		vdac_reg: regulator@8 {
-			regulator-always-on;
-		};
-
-		vaux1_reg: regulator@9 {
-			regulator-always-on;
-		};
-
-		vaux2_reg: regulator@10 {
-			regulator-always-on;
-		};
-
-		vaux33_reg: regulator@11 {
-			regulator-always-on;
-		};
-
-		vmmc_reg: regulator@12 {
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <3300000>;
+		ldo4_reg: regulator@6 {
+			regulator-name = "vdd_3v3a";
 			regulator-always-on;
 		};
 	};
@@ -604,6 +594,7 @@
  	phy-mode = "mii";
 
 };
+
 #if 0
 &cpsw_emac1 {
 	phy_id = <&davinci_mdio>, <2>;
@@ -628,7 +619,7 @@
 
 &mmc1 {
 	status = "okay";
-	vmmc-supply = <&vmmc_reg>;
+	vmmc-supply = <&ldo4_reg>;
 	bus-width = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins_default>;