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-/*
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- * Definitions for DDR memories based on JEDEC specs
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- *
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- * Copyright (C) 2012 Texas Instruments, Inc.
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- *
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- * Aneesh V <aneesh@ti.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- */
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-#ifndef __LINUX_JEDEC_DDR_H
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-#define __LINUX_JEDEC_DDR_H
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-
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-#include <linux/types.h>
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-
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-/* DDR Densities */
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-#define DDR_DENSITY_64Mb 1
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-#define DDR_DENSITY_128Mb 2
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-#define DDR_DENSITY_256Mb 3
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-#define DDR_DENSITY_512Mb 4
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-#define DDR_DENSITY_1Gb 5
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-#define DDR_DENSITY_2Gb 6
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-#define DDR_DENSITY_4Gb 7
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-#define DDR_DENSITY_8Gb 8
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-#define DDR_DENSITY_16Gb 9
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-#define DDR_DENSITY_32Gb 10
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-
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-/* DDR type */
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-#define DDR_TYPE_DDR2 1
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-#define DDR_TYPE_DDR3 2
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-#define DDR_TYPE_LPDDR2_S4 3
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-#define DDR_TYPE_LPDDR2_S2 4
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-#define DDR_TYPE_LPDDR2_NVM 5
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-
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-/* DDR IO width */
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-#define DDR_IO_WIDTH_4 1
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-#define DDR_IO_WIDTH_8 2
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-#define DDR_IO_WIDTH_16 3
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-#define DDR_IO_WIDTH_32 4
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-
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-/* Number of Row bits */
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-#define R9 9
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-#define R10 10
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-#define R11 11
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-#define R12 12
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-#define R13 13
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-#define R14 14
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-#define R15 15
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-#define R16 16
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-
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-/* Number of Column bits */
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-#define C7 7
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-#define C8 8
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-#define C9 9
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-#define C10 10
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-#define C11 11
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-#define C12 12
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-
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-/* Number of Banks */
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-#define B1 0
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-#define B2 1
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-#define B4 2
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-#define B8 3
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-
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-/* Refresh rate in nano-seconds */
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-#define T_REFI_15_6 15600
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-#define T_REFI_7_8 7800
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-#define T_REFI_3_9 3900
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-
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-/* tRFC values */
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-#define T_RFC_90 90000
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-#define T_RFC_110 110000
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-#define T_RFC_130 130000
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-#define T_RFC_160 160000
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-#define T_RFC_210 210000
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-#define T_RFC_300 300000
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-#define T_RFC_350 350000
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-
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-/* Mode register numbers */
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-#define DDR_MR0 0
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-#define DDR_MR1 1
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-#define DDR_MR2 2
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-#define DDR_MR3 3
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-#define DDR_MR4 4
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-#define DDR_MR5 5
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-#define DDR_MR6 6
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-#define DDR_MR7 7
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-#define DDR_MR8 8
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-#define DDR_MR9 9
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-#define DDR_MR10 10
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-#define DDR_MR11 11
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-#define DDR_MR16 16
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-#define DDR_MR17 17
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-#define DDR_MR18 18
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-
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-/*
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- * LPDDR2 related defines
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- */
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-
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-/* MR4 register fields */
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-#define MR4_SDRAM_REF_RATE_SHIFT 0
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-#define MR4_SDRAM_REF_RATE_MASK 7
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-#define MR4_TUF_SHIFT 7
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-#define MR4_TUF_MASK (1 << 7)
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-
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-/* MR4 SDRAM Refresh Rate field values */
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-#define SDRAM_TEMP_NOMINAL 0x3
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-#define SDRAM_TEMP_RESERVED_4 0x4
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-#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
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-#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
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-#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
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-
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-#define NUM_DDR_ADDR_TABLE_ENTRIES 11
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-#define NUM_DDR_TIMING_TABLE_ENTRIES 4
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-
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-/* Structure for DDR addressing info from the JEDEC spec */
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-struct lpddr2_addressing {
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- u32 num_banks;
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- u32 tREFI_ns;
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- u32 tRFCab_ps;
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-};
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-
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-/*
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- * Structure for timings from the LPDDR2 datasheet
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- * All parameters are in pico seconds(ps) unless explicitly indicated
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- * with a suffix like tRAS_max_ns below
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- */
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-struct lpddr2_timings {
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- u32 max_freq;
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- u32 min_freq;
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- u32 tRPab;
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- u32 tRCD;
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- u32 tWR;
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- u32 tRAS_min;
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- u32 tRRD;
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- u32 tWTR;
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- u32 tXP;
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- u32 tRTP;
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- u32 tCKESR;
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- u32 tDQSCK_max;
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- u32 tDQSCK_max_derated;
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- u32 tFAW;
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- u32 tZQCS;
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- u32 tZQCL;
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- u32 tZQinit;
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- u32 tRAS_max_ns;
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-};
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-
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-/*
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- * Min value for some parameters in terms of number of tCK cycles(nCK)
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- * Please set to zero parameters that are not valid for a given memory
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- * type
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- */
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-struct lpddr2_min_tck {
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- u32 tRPab;
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- u32 tRCD;
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- u32 tWR;
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- u32 tRASmin;
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- u32 tRRD;
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- u32 tWTR;
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- u32 tXP;
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- u32 tRTP;
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- u32 tCKE;
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- u32 tCKESR;
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- u32 tFAW;
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-};
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-
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-extern const struct lpddr2_addressing
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- lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
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-extern const struct lpddr2_timings
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- lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
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-extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
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-
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-#endif /* __LINUX_JEDEC_DDR_H */
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