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@@ -0,0 +1,776 @@
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+/*
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+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+/dts-v1/;
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+
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+#include "am33xx.dtsi"
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+#include <dt-bindings/interrupt-controller/irq.h>
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+
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+/ {
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+ model = "TI AM335x EVM";
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+ compatible = "ti,am335x-evm", "ti,am33xx";
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+
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+ chosen {
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+ stdout-path = &uart0;
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+ tick-timer = &timer2;
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+ };
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+
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+ cpus {
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+ cpu@0 {
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+ cpu0-supply = <&dcdc2_reg>;
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+ };
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+ };
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+
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+ memory {
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+ device_type = "memory";
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+ //reg = <0x80000000 0x10000000>; /* 256 MB */
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+ reg = <0x80000000 0x20000000>; /* 512 MB */ /* +++ vern,512MB DDR ,20181030 ---*/
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+ };
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+
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+ vbat: fixedregulator@0 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vbat";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-boot-on;
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+ };
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+
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+ lis3_reg: fixedregulator@1 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "lis3_reg";
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+ regulator-boot-on;
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+ };
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+
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+ wlan_en_reg: fixedregulator@2 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "wlan-en-regulator";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+
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+ /* WLAN_EN GPIO for this board - Bank1, pin16 */
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+ gpio = <&gpio1 16 0>;
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+
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+ /* WLAN card specific delay */
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+ startup-delay-us = <70000>;
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+ enable-active-high;
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+ };
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+
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+ matrix_keypad: matrix_keypad@0 {
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+ compatible = "gpio-matrix-keypad";
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+ debounce-delay-ms = <5>;
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+ col-scan-delay-us = <2>;
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+
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+ row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
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+ &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
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+ &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
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+
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+ col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
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+ &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
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+
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+ linux,keymap = <0x0000008b /* MENU */
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+ 0x0100009e /* BACK */
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+ 0x02000069 /* LEFT */
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+ 0x0001006a /* RIGHT */
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+ 0x0101001c /* ENTER */
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+ 0x0201006c>; /* DOWN */
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+ };
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+
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+ gpio_keys: volume_keys@0 {
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+ compatible = "gpio-keys";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ autorepeat;
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+
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+ switch@9 {
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+ label = "volume-up";
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+ linux,code = <115>;
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+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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+ gpio-key,wakeup;
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+ };
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+
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+ switch@10 {
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+ label = "volume-down";
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+ linux,code = <114>;
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+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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+ gpio-key,wakeup;
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+ };
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+ };
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+
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+ backlight {
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+ compatible = "pwm-backlight";
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+ pwms = <&ecap0 0 50000 0>;
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+ brightness-levels = <0 51 53 56 62 75 101 152 255>;
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+ default-brightness-level = <8>;
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+ };
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+
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+ panel {
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+ compatible = "ti,tilcdc,panel";
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&lcd_pins_s0>;
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+ panel-info {
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+ ac-bias = <255>;
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+ ac-bias-intrpt = <0>;
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+ dma-burst-sz = <16>;
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+ bpp = <32>;
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+ fdd = <0x80>;
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+ sync-edge = <0>;
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+ sync-ctrl = <1>;
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+ raster-order = <0>;
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+ fifo-th = <0>;
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+ };
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+
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+ display-timings {
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+ 800x480p62 {
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+ clock-frequency = <30000000>;
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+ hactive = <800>;
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+ vactive = <480>;
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+ hfront-porch = <39>;
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+ hback-porch = <39>;
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+ hsync-len = <47>;
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+ vback-porch = <29>;
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+ vfront-porch = <13>;
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+ vsync-len = <2>;
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+ hsync-active = <1>;
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+ vsync-active = <1>;
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+ };
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+ };
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+ };
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+
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+ sound {
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+ compatible = "ti,da830-evm-audio";
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+ ti,model = "AM335x-EVM";
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+ ti,audio-codec = <&tlv320aic3106>;
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+ ti,mcasp-controller = <&mcasp1>;
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+ ti,codec-clock-rate = <12000000>;
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+ ti,audio-routing =
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+ "Headphone Jack", "HPLOUT",
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+ "Headphone Jack", "HPROUT",
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+ "LINE1L", "Line In",
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+ "LINE1R", "Line In";
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+ };
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+};
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+
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+&am33xx_pinmux {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
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+
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+ matrix_keypad_s0: matrix_keypad_s0 {
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+ pinctrl-single,pins = <
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+ 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
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+ 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
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+ 0x60 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.gpio1_24 */
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+ 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
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+ 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
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+ 0x6c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
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+ >;
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+ };
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+
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+ volume_keys_s0: volume_keys_s0 {
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+ pinctrl-single,pins = <
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+ 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
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+ 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
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+ >;
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+ };
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+
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+ i2c0_pins: pinmux_i2c0_pins {
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+ pinctrl-single,pins = <
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+ 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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+ 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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+ >;
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+ };
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+
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+ i2c1_pins: pinmux_i2c1_pins {
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+ pinctrl-single,pins = <
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+ 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
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+ 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
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+ >;
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+ };
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+
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+ uart0_pins: pinmux_uart0_pins {
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+ pinctrl-single,pins = <
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+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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+ >;
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+ };
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+
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+ uart1_pins: pinmux_uart1_pins {
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+ pinctrl-single,pins = <
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+ 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
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+ 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
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+ 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
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+ 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
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+ >;
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+ };
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+
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+ clkout2_pin: pinmux_clkout2_pin {
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+ pinctrl-single,pins = <
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+ 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
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+ >;
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+ };
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+
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+ nandflash_pins_s0: nandflash_pins_s0 {
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+ pinctrl-single,pins = <
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+ 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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+ 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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+ 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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+ 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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+ 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
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+ 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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+ 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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+ 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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+ 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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+ 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
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+ >;
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+ };
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+
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+ ecap0_pins: backlight_pins {
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+ pinctrl-single,pins = <
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+ 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
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+ >;
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+ };
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+
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+ cpsw_default: cpsw_default {
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+ pinctrl-single,pins = <
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+ /* Slave 1 */
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+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* MII1_RX_ER.gmii1_rxerr */
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+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
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+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_txclk.mii1_txclk */
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+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
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+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd3.rgmii1_rd3 */
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+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd2.rgmii1_rd2 */
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+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd1.rgmii1_rd1 */
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+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd0.rgmii1_rd0 */
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+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
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+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.rgmii1_td3 */
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+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.rgmii1_td2 */
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+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.rgmii1_td1 */
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+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.rgmii1_td0 */
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+ >;
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+ };
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+
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+ cpsw_sleep: cpsw_sleep {
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+ pinctrl-single,pins = <
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+ /* Slave 1 reset value */
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+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* MII1_RX_ER.gmii1_rxerr */
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+ //0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* MII1_COL.gmii1_col */
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+ //0x10C (PIN_INPUT_PULLDOWN | MUX_MODE7) /* MII1_CRS.gmii1_crs */
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+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ >;
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+ };
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+
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+ davinci_mdio_default: davinci_mdio_default {
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+ pinctrl-single,pins = <
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+ /* MDIO */
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+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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+ >;
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+ };
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+
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+ davinci_mdio_sleep: davinci_mdio_sleep {
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+ pinctrl-single,pins = <
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+ /* MDIO reset value */
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+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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+ >;
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+ };
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+
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+ #if 0
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+ mmc1_pins: pinmux_mmc1_pins {
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+ pinctrl-single,pins = <
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+ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
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+ >;
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+ };
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+ #endif
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+ mmc1_pins_default: pinmux_mmc1_pins {
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+ pinctrl-single,pins = <
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+ 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
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+ 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
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+ 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
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+ 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
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+ 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
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+ 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
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+ /*0x0A8 (PIN_INPUT | MUX_MODE7)*/ /* LCD_DATA2.GPIO2_8 */
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+ 0x08C (PIN_INPUT | MUX_MODE7) /* GPMC_CLK.GPIO2_1 */
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+ >;
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+ };
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+ mmc3_pins: pinmux_mmc3_pins {
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+ pinctrl-single,pins = <
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+ 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
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+ 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
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+ 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
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+ 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
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+ 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
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+ 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
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+ >;
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+ };
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+
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+ wlan_pins: pinmux_wlan_pins {
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+ pinctrl-single,pins = <
|
|
|
+ 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
|
|
|
+ 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
|
|
|
+ 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
|
|
|
+ >;
|
|
|
+ };
|
|
|
+
|
|
|
+ lcd_pins_s0: lcd_pins_s0 {
|
|
|
+ pinctrl-single,pins = <
|
|
|
+ 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
|
|
|
+ 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
|
|
|
+ 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
|
|
|
+ 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
|
|
|
+ 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
|
|
|
+ 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
|
|
|
+ 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
|
|
|
+ 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
|
|
|
+ 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
|
|
|
+ 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
|
|
|
+ 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
|
|
|
+ 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
|
|
|
+ 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
|
|
|
+ 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
|
|
|
+ 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
|
|
|
+ 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
|
|
|
+ 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
|
|
|
+ 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
|
|
|
+ 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
|
|
|
+ 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
|
|
|
+ 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
|
|
|
+ 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
|
|
|
+ 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
|
|
|
+ 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
|
|
|
+ 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
|
|
|
+ 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
|
|
|
+ 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
|
|
|
+ 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
|
|
|
+ >;
|
|
|
+ };
|
|
|
+#if 0
|
|
|
+ am335x_evm_audio_pins: am335x_evm_audio_pins {
|
|
|
+ pinctrl-single,pins = <
|
|
|
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
|
|
|
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
|
|
|
+ 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
|
|
|
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
|
|
|
+ >;
|
|
|
+ };
|
|
|
+#endif
|
|
|
+ dcan1_pins_default: dcan1_pins_default {
|
|
|
+ pinctrl-single,pins = <
|
|
|
+ 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
|
|
|
+ 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
|
|
|
+ >;
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&uart0 {
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&uart0_pins>;
|
|
|
+
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&uart1 {
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&uart1_pins>;
|
|
|
+
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&i2c0 {
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&i2c0_pins>;
|
|
|
+
|
|
|
+ status = "okay";
|
|
|
+ clock-frequency = <400000>;
|
|
|
+
|
|
|
+ tps: tps@24 {
|
|
|
+ reg = <0x24>;
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&usb {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&usb_ctrl_mod {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&usb0_phy {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&usb1_phy {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&usb0 {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&usb1 {
|
|
|
+ status = "okay";
|
|
|
+ dr_mode = "host";
|
|
|
+};
|
|
|
+
|
|
|
+&cppi41dma {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&i2c1 {
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
|
+
|
|
|
+ status = "okay";
|
|
|
+ clock-frequency = <100000>;
|
|
|
+
|
|
|
+ lis331dlh: lis331dlh@18 {
|
|
|
+ compatible = "st,lis331dlh", "st,lis3lv02d";
|
|
|
+ reg = <0x18>;
|
|
|
+ Vdd-supply = <&lis3_reg>;
|
|
|
+ Vdd_IO-supply = <&lis3_reg>;
|
|
|
+
|
|
|
+ st,click-single-x;
|
|
|
+ st,click-single-y;
|
|
|
+ st,click-single-z;
|
|
|
+ st,click-thresh-x = <10>;
|
|
|
+ st,click-thresh-y = <10>;
|
|
|
+ st,click-thresh-z = <10>;
|
|
|
+ st,irq1-click;
|
|
|
+ st,irq2-click;
|
|
|
+ st,wakeup-x-lo;
|
|
|
+ st,wakeup-x-hi;
|
|
|
+ st,wakeup-y-lo;
|
|
|
+ st,wakeup-y-hi;
|
|
|
+ st,wakeup-z-lo;
|
|
|
+ st,wakeup-z-hi;
|
|
|
+ st,min-limit-x = <120>;
|
|
|
+ st,min-limit-y = <120>;
|
|
|
+ st,min-limit-z = <140>;
|
|
|
+ st,max-limit-x = <550>;
|
|
|
+ st,max-limit-y = <550>;
|
|
|
+ st,max-limit-z = <750>;
|
|
|
+ };
|
|
|
+
|
|
|
+ tsl2550: tsl2550@39 {
|
|
|
+ compatible = "taos,tsl2550";
|
|
|
+ reg = <0x39>;
|
|
|
+ };
|
|
|
+
|
|
|
+ tmp275: tmp275@48 {
|
|
|
+ compatible = "ti,tmp275";
|
|
|
+ reg = <0x48>;
|
|
|
+ };
|
|
|
+
|
|
|
+ tlv320aic3106: tlv320aic3106@1b {
|
|
|
+ compatible = "ti,tlv320aic3106";
|
|
|
+ reg = <0x1b>;
|
|
|
+ status = "okay";
|
|
|
+
|
|
|
+ /* Regulators */
|
|
|
+ AVDD-supply = <&ldo2_reg>;
|
|
|
+ IOVDD-supply = <&ldo2_reg>;
|
|
|
+ DRVDD-supply = <&ldo2_reg>;
|
|
|
+ DVDD-supply = <&vbat>;
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&lcdc {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&elm {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&epwmss0 {
|
|
|
+ status = "okay";
|
|
|
+
|
|
|
+ ecap0: ecap@48300100 {
|
|
|
+ status = "okay";
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&ecap0_pins>;
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&gpmc {
|
|
|
+ status = "okay";
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&nandflash_pins_s0>;
|
|
|
+ /*ranges = <0 0 0x08000000 0x1000000>;*/ /* CS0: 16MB for NAND */
|
|
|
+ ranges = <0 0 0x08000000 0x40000000>; /*+++ vern,NAND,20181030 ---*/
|
|
|
+ nand@0,0 {
|
|
|
+ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
|
|
+ ti,nand-ecc-opt = "bch16";
|
|
|
+ ti,elm-id = <&elm>;
|
|
|
+ nand-bus-width = <8>;
|
|
|
+ gpmc,device-width = <1>;
|
|
|
+ gpmc,sync-clk-ps = <0>;
|
|
|
+ gpmc,cs-on-ns = <0>;
|
|
|
+ gpmc,cs-rd-off-ns = <44>;
|
|
|
+ gpmc,cs-wr-off-ns = <44>;
|
|
|
+ gpmc,adv-on-ns = <6>;
|
|
|
+ gpmc,adv-rd-off-ns = <34>;
|
|
|
+ gpmc,adv-wr-off-ns = <44>;
|
|
|
+ gpmc,we-on-ns = <0>;
|
|
|
+ gpmc,we-off-ns = <40>;
|
|
|
+ gpmc,oe-on-ns = <0>;
|
|
|
+ gpmc,oe-off-ns = <54>;
|
|
|
+ gpmc,access-ns = <64>;
|
|
|
+ gpmc,rd-cycle-ns = <82>;
|
|
|
+ gpmc,wr-cycle-ns = <82>;
|
|
|
+ gpmc,wait-on-read = "true";
|
|
|
+ gpmc,wait-on-write = "true";
|
|
|
+ gpmc,bus-turnaround-ns = <0>;
|
|
|
+ gpmc,cycle2cycle-delay-ns = <0>;
|
|
|
+ gpmc,clk-activation-ns = <0>;
|
|
|
+ gpmc,wait-monitoring-ns = <0>;
|
|
|
+ gpmc,wr-access-ns = <40>;
|
|
|
+ gpmc,wr-data-mux-bus-ns = <0>;
|
|
|
+ /* MTD partition table */
|
|
|
+ /* All SPL-* partitions are sized to minimal length
|
|
|
+ * which can be independently programmable. For
|
|
|
+ * NAND flash this is equal to size of erase-block */
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+ partition@0 {
|
|
|
+ label = "SPL";
|
|
|
+ reg = <0x00000000 0x00080000>;
|
|
|
+ };
|
|
|
+ partition@1 {
|
|
|
+ label = "Primary u-boot";
|
|
|
+ reg = <0x00080000 0x00100000>;
|
|
|
+ };
|
|
|
+ partition@2 {
|
|
|
+ label = "u-boot-env";
|
|
|
+ reg = <0x00180000 0x00080000>;
|
|
|
+ };
|
|
|
+ partition@3 {
|
|
|
+ label = "Secondary u-boot";
|
|
|
+ reg = <0x00200000 0x00100000>;
|
|
|
+ };
|
|
|
+ partition@4 {
|
|
|
+ label = "Primary dtb";
|
|
|
+ reg = <0x00300000 0x00080000>;
|
|
|
+ };
|
|
|
+ partition@5 {
|
|
|
+ label = "Secondary dtb";
|
|
|
+ reg = <0x00380000 0x00080000>;
|
|
|
+ };
|
|
|
+ partition@6 {
|
|
|
+ label = "Primary kernel";
|
|
|
+ reg = <0x00400000 0x00A00000>;
|
|
|
+ };
|
|
|
+ partition@7 {
|
|
|
+ label = "Secondary kernel";
|
|
|
+ reg = <0x00E00000 0x00A00000>;
|
|
|
+ };
|
|
|
+ partition@8 {
|
|
|
+ label = "Primary rootfs";
|
|
|
+ reg = <0x03000000 0x03000000>;
|
|
|
+ };
|
|
|
+ partition@9 {
|
|
|
+ label = "Secondary rootfs";
|
|
|
+ reg = <0x06000000 0x03000000>;
|
|
|
+ };
|
|
|
+ partition@10 {
|
|
|
+ label = "Primary user configuration";
|
|
|
+ reg = <0x09000000 0x00600000>;
|
|
|
+ };
|
|
|
+ partition@11 {
|
|
|
+ label = "Secondary user configuration";
|
|
|
+ reg = <0x09600000 0x00600000>;
|
|
|
+ };
|
|
|
+ partition@12 {
|
|
|
+ label = "Factory default configuration";
|
|
|
+ reg = <0x09C00000 0x00600000>;
|
|
|
+ };
|
|
|
+ partition@13 {
|
|
|
+ label = "Storage";
|
|
|
+ reg = <0x0A200000 0x35E00000>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+/include/ "tps65217.dtsi"
|
|
|
+
|
|
|
+&tps {
|
|
|
+ /*
|
|
|
+ * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
|
|
|
+ * mode") at poweroff. Most BeagleBone versions do not support RTC-only
|
|
|
+ * mode and risk hardware damage if this mode is entered.
|
|
|
+ *
|
|
|
+ * For details, see linux-omap mailing list May 2015 thread
|
|
|
+ * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
|
|
|
+ * In particular, messages:
|
|
|
+ * http://www.spinics.net/lists/linux-omap/msg118585.html
|
|
|
+ * http://www.spinics.net/lists/linux-omap/msg118615.html
|
|
|
+ *
|
|
|
+ * You can override this later with
|
|
|
+ * &tps { /delete-property/ ti,pmic-shutdown-controller; }
|
|
|
+ * if you want to use RTC-only mode and made sure you are not affected
|
|
|
+ * by the hardware problems. (Tip: double-check by performing a current
|
|
|
+ * measurement after shutdown: it should be less than 1 mA.)
|
|
|
+ */
|
|
|
+ ti,pmic-shutdown-controller;
|
|
|
+
|
|
|
+ regulators {
|
|
|
+ dcdc1_reg: regulator@0 {
|
|
|
+ regulator-name = "vdds_dpr";
|
|
|
+ regulator-always-on;
|
|
|
+ };
|
|
|
+
|
|
|
+ dcdc2_reg: regulator@1 {
|
|
|
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
|
|
+ regulator-name = "vdd_mpu";
|
|
|
+ regulator-min-microvolt = <925000>;
|
|
|
+ regulator-max-microvolt = <1325000>;
|
|
|
+ regulator-boot-on;
|
|
|
+ regulator-always-on;
|
|
|
+ };
|
|
|
+
|
|
|
+ dcdc3_reg: regulator@2 {
|
|
|
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
|
|
+ regulator-name = "vdd_core";
|
|
|
+ regulator-min-microvolt = <925000>;
|
|
|
+ regulator-max-microvolt = <1150000>;
|
|
|
+ regulator-boot-on;
|
|
|
+ regulator-always-on;
|
|
|
+ };
|
|
|
+
|
|
|
+ ldo1_reg: regulator@3 {
|
|
|
+ regulator-name = "vio,vrtc,vdds";
|
|
|
+ regulator-always-on;
|
|
|
+ };
|
|
|
+
|
|
|
+ ldo2_reg: regulator@4 {
|
|
|
+ regulator-name = "vdd_3v3aux";
|
|
|
+ regulator-always-on;
|
|
|
+ };
|
|
|
+
|
|
|
+ ldo3_reg: regulator@5 {
|
|
|
+ regulator-name = "vdd_1v8";
|
|
|
+ regulator-always-on;
|
|
|
+ };
|
|
|
+
|
|
|
+ ldo4_reg: regulator@6 {
|
|
|
+ regulator-name = "vdd_3v3a";
|
|
|
+ regulator-always-on;
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&mac {
|
|
|
+ pinctrl-names = "default", "sleep";
|
|
|
+ pinctrl-0 = <&cpsw_default>;
|
|
|
+ pinctrl-1 = <&cpsw_sleep>;
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&davinci_mdio {
|
|
|
+ pinctrl-names = "default", "sleep";
|
|
|
+ pinctrl-0 = <&davinci_mdio_default>;
|
|
|
+ pinctrl-1 = <&davinci_mdio_sleep>;
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&cpsw_emac0 {
|
|
|
+ phy_id = <&davinci_mdio>, <1>;
|
|
|
+ phy-mode = "mii";
|
|
|
+};
|
|
|
+
|
|
|
+&cpsw_emac1 {
|
|
|
+ phy_id = <&davinci_mdio>, <2>;
|
|
|
+ phy-mode = "mii";
|
|
|
+};
|
|
|
+
|
|
|
+&tscadc {
|
|
|
+ status = "okay";
|
|
|
+ tsc {
|
|
|
+ ti,wires = <4>;
|
|
|
+ ti,x-plate-resistance = <200>;
|
|
|
+ ti,coordinate-readouts = <5>;
|
|
|
+ ti,wire-config = <0x00 0x11 0x22 0x33>;
|
|
|
+ ti,charge-delay = <0x400>;
|
|
|
+ };
|
|
|
+
|
|
|
+ adc {
|
|
|
+ ti,adc-channels = <4 5 6 7>;
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&mmc1 {
|
|
|
+ status = "okay";
|
|
|
+ vmmc-supply = <&ldo4_reg>;
|
|
|
+ bus-width = <4>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&mmc1_pins_default>;
|
|
|
+ cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
|
|
+};
|
|
|
+
|
|
|
+
|
|
|
+&mmc3 {
|
|
|
+ /* these are on the crossbar and are outlined in the
|
|
|
+ xbar-event-map element */
|
|
|
+ dmas = <&edma 12
|
|
|
+ &edma 13>;
|
|
|
+ dma-names = "tx", "rx";
|
|
|
+ status = "okay";
|
|
|
+ vmmc-supply = <&wlan_en_reg>;
|
|
|
+ bus-width = <4>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&mmc3_pins &wlan_pins>;
|
|
|
+ ti,non-removable;
|
|
|
+ ti,needs-special-hs-handling;
|
|
|
+ cap-power-off-card;
|
|
|
+ keep-power-in-suspend;
|
|
|
+
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ wlcore: wlcore@0 {
|
|
|
+ compatible = "ti,wl1835";
|
|
|
+ reg = <2>;
|
|
|
+ interrupt-parent = <&gpio3>;
|
|
|
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&edma {
|
|
|
+ ti,edma-xbar-event-map = /bits/ 16 <1 12
|
|
|
+ 2 13>;
|
|
|
+};
|
|
|
+
|
|
|
+&sham {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&aes {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&dcan1 {
|
|
|
+ status = "disabled"; /* Enable only if Profile 1 is selected */
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&dcan1_pins_default>;
|
|
|
+};
|
