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@@ -25,7 +25,7 @@
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cpus {
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cpu@0 {
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- cpu0-supply = <&vdd1_reg>;
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+ cpu0-supply = <&dcdc2_reg>;
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};
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};
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@@ -68,8 +68,12 @@
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0x144 (PIN_INPUT | MUX_MODE7) /* RMII1_REF_CLK => GPIO0_29 */ /*USB 0 OCP detection*/
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0x1B0 (PIN_OUTPUT | MUX_MODE7) /*XDMA_EVENT_INTR0 => GPIO0_19 */ /*AM_RFID_RST*/
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0x1B4 (PIN_INPUT | MUX_MODE7) /*XDMA_EVENT_INTR1 => GPIO0_20 */ /*AM_RFID_ICC*/
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- /** GPIO 1 */
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+ /** GPIO 1 */
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+ 0x060 (PIN_OUTPUT | MUX_MODE7) /*GPIO1_24*/
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+ 0x06C (PIN_OUTPUT | MUX_MODE7) /* (V17) gpmc_a11.gpio1[27] */
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+
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/** GPIO 2 */
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+ 0x088 (PIN_INPUT | MUX_MODE7) /* CCS=>GPMC_CSn3.GPIO2_0*/
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0x08C (PIN_OUTPUT | MUX_MODE7) /*GPMC_CLK => GPIO2_1*/ /*Speaker*/
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0x0A0 (PIN_OUTPUT | MUX_MODE7) /*LCD_DATA0 => GPIO2_6*/ /*Panel LED control-BB_LEDR1*/
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0x0A4 (PIN_OUTPUT | MUX_MODE7) /*LCD_DATA1 => GPIO2_7*/ /*Panel LED control-BB_LEDG1*/
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@@ -79,7 +83,11 @@
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0x0B4 (PIN_OUTPUT | MUX_MODE7) /*LCD_DATA5 => GPIO2_11*/ /*Panel LED control-BB_LEDB2*/
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0x0E8 (PIN_INPUT | MUX_MODE7) /*LCD_PCLK => GPIO2_24*/ /*communication board proximity*/
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0x0E0 (PIN_OUTPUT | MUX_MODE7) /*LCD_VSYNC => GPIO2_22*/ /*Breath LED*/
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+ 0x0EC (PIN_OUTPUT | MUX_MODE7) /* CCSEthernet-Reset=>LCD_AC_BIAS_EN.GPIO2_25*/
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+
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/** GPIO 3 */
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+ 0x1A0 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR1 => GPIO3_18 */ /*control 4G reset pin*/
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+ 0x1A4 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_FSR.GPIO3_19 */
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0x1A8 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR1 => GPIO3_20 */ /*control MCU to output CP PWM*/
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>;
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};
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@@ -274,9 +282,16 @@
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pinctrl-single,pins =<
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0x0A4 (PIN_OUTPUT | MUX_MODE3) /* LCD_DATA1.eHRPWM2B */
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>;
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- };
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-
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+ };
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#endif
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+ spi1_pins: spi1_pins {
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+ pinctrl-single,pins = <
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+ AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE3) /* MCASP0_ACLKX.AM_SPI1_SCLK */
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+ AM33XX_IOPAD(0x994, PIN_INPUT_PULLUP | MUX_MODE3) /* MCASP0_FSX.AM_SPI1_D0 */
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+ AM33XX_IOPAD(0x998, PIN_OUTPUT_PULLUP | MUX_MODE3) /* MCASP0_AXR0.AM_SPI1_D1 */
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+ AM33XX_IOPAD(0x99C, PIN_OUTPUT_PULLUP | MUX_MODE3) /* MCASP0_AHCLKR.AM_SPI1_CS0 */
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+ >;
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+ };
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};
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@@ -323,8 +338,8 @@
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status = "okay";
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clock-frequency = <400000>;
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- tps: tps@2d {
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- reg = <0x2d>;
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+ tps: tps@24 {
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+ reg = <0x24>;
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};
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/* rtc0: rtc@51 {
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@@ -406,7 +421,7 @@
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pinctrl-0 = <&nandflash_pins_default>;
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pinctrl-1 = <&nandflash_pins_sleep>;
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/*ranges = <0 0 0x08000000 0x10000000>;*/ /* CS0: NAND */
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- ranges = <0 0 0x08000000 0x80000000>; /*+++ vern,NAND,20181030 ---*/
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+ ranges = <0 0 0x08000000 0x40000000>; /*+++ vern,NAND,20181030 ---*/
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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@@ -500,85 +515,74 @@
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};
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partition@13 {
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label = "Storage";
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- reg = <0x0A200000 0x75E00000>;
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+ reg = <0x0A200000 0x35E00000>;
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};
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};
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};
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-#include "tps65910.dtsi"
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+/include/ "tps65217.dtsi"
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&tps {
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- vcc1-supply = <&vbat>;
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- vcc2-supply = <&vbat>;
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- vcc3-supply = <&vbat>;
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- vcc4-supply = <&vbat>;
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- vcc5-supply = <&vbat>;
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- vcc6-supply = <&vbat>;
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- vcc7-supply = <&vbat>;
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- vccio-supply = <&vbat>;
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+ /*
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+ * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
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+ * mode") at poweroff. Most BeagleBone versions do not support RTC-only
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+ * mode and risk hardware damage if this mode is entered.
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+ *
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+ * For details, see linux-omap mailing list May 2015 thread
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+ * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
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+ * In particular, messages:
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+ * http://www.spinics.net/lists/linux-omap/msg118585.html
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+ * http://www.spinics.net/lists/linux-omap/msg118615.html
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+ *
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+ * You can override this later with
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+ * &tps { /delete-property/ ti,pmic-shutdown-controller; }
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+ * if you want to use RTC-only mode and made sure you are not affected
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+ * by the hardware problems. (Tip: double-check by performing a current
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+ * measurement after shutdown: it should be less than 1 mA.)
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+ */
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+ ti,pmic-shutdown-controller;
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regulators {
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- vrtc_reg: regulator@0 {
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+ dcdc1_reg: regulator@0 {
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+ regulator-name = "vdds_dpr";
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regulator-always-on;
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};
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- vio_reg: regulator@1 {
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- regulator-always-on;
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- };
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-
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- vdd1_reg: regulator@2 {
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- /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
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+ dcdc2_reg: regulator@1 {
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+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
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regulator-name = "vdd_mpu";
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- regulator-min-microvolt = <912500>;
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- regulator-max-microvolt = <1378000>;
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+ regulator-min-microvolt = <1100000>;
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+ regulator-max-microvolt = <1351500>;
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regulator-boot-on;
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regulator-always-on;
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};
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- vdd2_reg: regulator@3 {
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+ dcdc3_reg: regulator@2 {
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/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
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regulator-name = "vdd_core";
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- regulator-min-microvolt = <912500>;
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+ regulator-min-microvolt = <925000>;
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regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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regulator-always-on;
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};
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- vdd3_reg: regulator@4 {
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- regulator-always-on;
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- };
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-
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- vdig1_reg: regulator@5 {
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+ ldo1_reg: regulator@3 {
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+ regulator-name = "vio,vrtc,vdds";
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regulator-always-on;
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};
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- vdig2_reg: regulator@6 {
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+ ldo2_reg: regulator@4 {
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+ regulator-name = "vdd_3v3aux";
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regulator-always-on;
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};
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- vpll_reg: regulator@7 {
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+ ldo3_reg: regulator@5 {
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+ regulator-name = "vdd_1v8";
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regulator-always-on;
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};
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- vdac_reg: regulator@8 {
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- regulator-always-on;
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- };
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-
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- vaux1_reg: regulator@9 {
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- regulator-always-on;
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- };
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-
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- vaux2_reg: regulator@10 {
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- regulator-always-on;
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- };
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-
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- vaux33_reg: regulator@11 {
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- regulator-always-on;
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- };
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-
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- vmmc_reg: regulator@12 {
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- regulator-min-microvolt = <1800000>;
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- regulator-max-microvolt = <3300000>;
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+ ldo4_reg: regulator@6 {
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+ regulator-name = "vdd_3v3a";
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regulator-always-on;
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};
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};
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@@ -604,6 +608,7 @@
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phy-mode = "mii";
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};
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+
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#if 0
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&cpsw_emac1 {
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phy_id = <&davinci_mdio>, <2>;
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@@ -628,7 +633,7 @@
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&mmc1 {
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status = "okay";
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- vmmc-supply = <&vmmc_reg>;
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+ vmmc-supply = <&ldo4_reg>;
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins_default>;
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@@ -665,3 +670,27 @@
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pinctrl-0 = <&dcan1_pins_default>;
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};
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#endif
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+
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+/*
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+The QCA7000 acts as a SPI slave and uses Mode 3: CPOL=1, CPHA=1.
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+SPI data width is 8 bit. The SPI CLK period should not be less than 83.3 ns
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+The SPI should be used in burst mode, meaning that the chip select is held low during a complete SPI message.
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+ Note: The SPI lines between Host CPU and QCA7000 should be kept as short as possible.
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+
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+*/
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+&spi1 {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1_pins>;
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+ qca7000@0 {
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+ compatible = "qca,qca7000";
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+ reg = <0>;
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+ interrupt-parent = <&gpio2>; /* GPIO2_0 */
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+ interrupts = <0 1>; /* GPIO2_0 */
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+ spi-cpha; /* SPI mode: CPHA=1 */
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+ spi-cpol; /* SPI mode: CPOL=1 */
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+ spi-max-frequency = <10000000>; /* freq: 10MHz */
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+ qca,legacy-mode = <0>; /* Burst mode */
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+ };
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+};
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+
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