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@@ -78,7 +78,7 @@
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0x034 (PIN_OUTPUT | MUX_MODE7) /* GPMC_AD13.GPIO1_13*/
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0x038 (PIN_INPUT | MUX_MODE7) /* GPMC_AD14.GPIO1_14*/
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0x03C (PIN_OUTPUT | MUX_MODE7) /* GPMC_AD15.GPIO1_15*/
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- 0x078 (PIN_INPUT | MUX_MODE7) /* GPMC_BEn1.GPIO1_28*/
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+ /*0x078 (PIN_INPUT | MUX_MODE7) *//* GPMC_BEn1.GPIO1_28*/
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/** GPIO 2 */
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0x088 (PIN_INPUT | MUX_MODE7) /* CCS=>GPMC_CSn3.GPIO2_0*/
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@@ -92,9 +92,9 @@
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0x0C4 (PIN_OUTPUT | MUX_MODE7) /* LCD_DATA9.GPIO2_15*/
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0x0CC (PIN_OUTPUT | MUX_MODE7) /* LCD_DATA11.GPIO2_17*/
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0x0E0 (PIN_OUTPUT | MUX_MODE7) /* CCS=>LCD_VSYNC.GPIO2_22*/
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- 0x0E4 (PIN_OUTPUT | MUX_MODE7) /* CCS=>LCD_HSYNC.GPIO2_23*/
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+ 0x0E4 (PIN_INPUT | MUX_MODE7) /* CCS=>LCD_HSYNC.GPIO2_23*/
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0x0E8 (PIN_OUTPUT | MUX_MODE7) /* CCS=>LCD_PCLK.GPIO2_24*/
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- 0x0EC (PIN_OUTPUT | MUX_MODE7) /* CCS=>LCD_AC_BIAS_EN.GPIO2_25*/
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+ 0x0EC (PIN_INPUT | MUX_MODE7) /* CCS=>LCD_AC_BIAS_EN.GPIO2_25*/
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/** GPIO 3 */
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0x108 (PIN_OUTPUT | MUX_MODE7) /* MII1_COL.GPIO3_0 */
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@@ -102,6 +102,7 @@
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0x1A4 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_FSR.GPIO3_19 */
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0x1A8 (PIN_INPUT | MUX_MODE7) /* MCASP0_AXR1.GPIO3_20 */
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/*0x1AC (PIN_INPUT | MUX_MODE7) *//* CCS=>MCASP0_AHCLKX.GPIO3_21 */
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+
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>;
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};
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@@ -125,7 +126,7 @@
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0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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-
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+
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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0x10C (PIN_INPUT_PULLUP | MUX_MODE6) /* MII1_CRS.AM_UART2_RXD */
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@@ -202,66 +203,46 @@
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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-
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- /* Slave 1 */
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- 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
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- 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
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- 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
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- 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
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- 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
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- 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
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- 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
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- 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
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- 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
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- 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
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- 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
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- 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
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-
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- /* Slave 2 */
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- 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
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- 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
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- 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
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- 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
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- 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
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- 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
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- 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
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- 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
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- 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
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- 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
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- 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
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- 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
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+
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+ AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ben1.mii2_col */
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+ /*AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) */ /* GPMC_CSn3.rmii2_crs_dv*/
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+ /*AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE1)*/ /* gpmc_wpn.mii2_rxerr */
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+ AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a6.mii2_txclk */
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+ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
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+ AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
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+ AM33XX_IOPAD(0x860, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
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+ AM33XX_IOPAD(0x864, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
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+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
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+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
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+ AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a0.mii2_txen */
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+ AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
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+ AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
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+ AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
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+ AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
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+
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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- 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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- 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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-
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- /* Slave 2 */
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- 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.rgmii2_tctl */
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- 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.rgmii2_rctl */
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- 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.rgmii2_td3 */
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- 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.rgmii2_td2 */
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- 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.rgmii2_td1 */
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- 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.rgmii2_td0 */
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- 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.rgmii2_tclk */
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- 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.rgmii2_rclk */
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- 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.rgmii2_rd3 */
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- 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.rgmii2_rd2 */
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- 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.rgmii2_rd1 */
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- 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.rgmii2_rd0 */
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+
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+ /*AM33XX_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)*/ /* GPMC_CSn3.rmii2_crs_dv*/
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+ AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.mii2_txen */
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+ AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mii2_rxdv */
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+ AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mii2_txd3 */
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+ AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mii2_txd2 */
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+ AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.mii2_txd1 */
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+ AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.mii2_txd0 */
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+ AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.mii2_txclk */
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+ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.mii2_rxclk */
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+ AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.mii2_rxd3 */
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+ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.mii2_rxd2 */
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+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.mii2_rxd1 */
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+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.mii2_rxd0 */
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+ /*AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE7)*/ /* gpmc_wpn.mii2_rxerr */
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+ AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben1.mii2_col */
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+
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>;
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};
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@@ -334,6 +315,13 @@
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AM33XX_IOPAD(0x964, MUX_MODE0)
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>;
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};
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+
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+ EXTINTn_NMI {
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+ compatible = "ti, EXTINTn";
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+ status = "okay";
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+ interrupt-parent = <&intc>;
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+ interrupts = <7>;
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+} ;
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};
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@@ -386,11 +374,11 @@
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reg = <0x2d>;
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};
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-/* rtc0: rtc@51 {
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+ rtc0: rtc@51 {
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compatible = "nxp,pcf85063";
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reg = <0x51>;
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};
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-*/
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+
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};
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&i2c1 {
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@@ -399,11 +387,6 @@
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status = "okay";
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clock-frequency = <400000>;
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-
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- rtc0: rtc@51 {
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- compatible = "nxp,pcf85063";
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- reg = <0x51>;
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- };
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};
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&usb {
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@@ -539,27 +522,27 @@
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};
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partition@8 {
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label = "Primary rootfs";
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- reg = <0x03000000 0x03000000>;
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+ reg = <0x01800000 0x03000000>;
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};
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partition@9 {
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label = "Secondary rootfs";
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- reg = <0x06000000 0x03000000>;
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+ reg = <0x04800000 0x03000000>;
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};
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partition@10 {
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label = "Primary user configuration";
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- reg = <0x09000000 0x00600000>;
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+ reg = <0x07800000 0x00600000>;
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};
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partition@11 {
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label = "Secondary user configuration";
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- reg = <0x09600000 0x00600000>;
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+ reg = <0x07E00000 0x00600000>;
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};
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partition@12 {
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label = "Factory default configuration";
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- reg = <0x09C00000 0x00600000>;
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+ reg = <0x08400000 0x00600000>;
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};
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partition@13 {
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label = "Storage";
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- reg = <0x0A200000 0x75E00000>;
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+ reg = <0x08A00000 0x77600000>;
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};
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};
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};
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@@ -642,13 +625,12 @@
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};
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};
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};
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-#if 0
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+
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&mac {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&cpsw_default>;
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pinctrl-1 = <&cpsw_sleep>;
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status = "okay";
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- dual_emac;
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};
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&davinci_mdio {
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@@ -659,15 +641,12 @@
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};
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&cpsw_emac0 {
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- phy_id = <&davinci_mdio>, <0>;
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- phy-mode = "rgmii-txid";
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-};
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-
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-&cpsw_emac1 {
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phy_id = <&davinci_mdio>, <1>;
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- phy-mode = "rgmii-txid";
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+ phy-mode = "mii";
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};
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-#endif
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+
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+
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+
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&tscadc {
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status = "okay";
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/*tsc {
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@@ -678,10 +657,11 @@
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};*/
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adc {
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- ti,adc-channels = <0 1 2 3 4 5 6 7>;
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+ ti,adc-channels = <0 1 2 3>;
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};
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};
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+
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&mmc1 {
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status = "okay";
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vmmc-supply = <&vmmc_reg>;
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@@ -753,3 +733,6 @@ The SPI should be used in burst mode, meaning that the chip select is held low d
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pinctrl-0 = <&ecap0_pins>;
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};
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};
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+
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+
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+
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