|
@@ -64,25 +64,38 @@
|
|
|
pinctrl-single,pins = <
|
|
|
|
|
|
/** Offset: 0x800 */
|
|
|
- /** GPIO 0 */
|
|
|
+ /** GPIO 0 */
|
|
|
+ 0x020 (PIN_INPUT | MUX_MODE7) /* GPMC_AD8 => GPIO0_22 */ /*ID BD1_1*/
|
|
|
+ 0x024 (PIN_INPUT | MUX_MODE7) /* GPMC_AD9 => GPIO0_23 */ /*ID BD1_2*/
|
|
|
+ 0x028 (PIN_INPUT | MUX_MODE7) /* GPMC_AD10 => GPIO0_26 */ /*IO BD1_1*/
|
|
|
+ 0x02C (PIN_INPUT | MUX_MODE7) /* GPMC_AD11 => GPIO0_27 */ /*IO BD1_2*/
|
|
|
0x144 (PIN_INPUT | MUX_MODE7) /* RMII1_REF_CLK => GPIO0_29 */ /*USB 0 OCP detection*/
|
|
|
0x1B0 (PIN_OUTPUT | MUX_MODE7) /*XDMA_EVENT_INTR0 => GPIO0_19 */ /*AM_RFID_RST*/
|
|
|
0x1B4 (PIN_INPUT | MUX_MODE7) /*XDMA_EVENT_INTR1 => GPIO0_20 */ /*AM_RFID_ICC*/
|
|
|
- /** GPIO 1 */
|
|
|
+
|
|
|
+ /** GPIO 1 */
|
|
|
+ 0x030 (PIN_INPUT | MUX_MODE7) /* GPMC_AD12 => GPIO1_12 */ /*ID BD2_1*/
|
|
|
+ 0x034 (PIN_INPUT | MUX_MODE7) /* GPMC_AD13 => GPIO1_13 */ /*ID BD2_2*/
|
|
|
+ 0x038 (PIN_INPUT | MUX_MODE7) /* GPMC_AD14 => GPIO1_14 */ /*IO BD2_1*/
|
|
|
+ 0x03C (PIN_INPUT | MUX_MODE7) /* GPMC_AD15 => GPIO1_15 */ /*IO BD2_2*/
|
|
|
+
|
|
|
/** GPIO 2 */
|
|
|
- 0x088 (PIN_INPUT | MUX_MODE7) /* CCS=>GPMC_CSn3.GPIO2_0*/
|
|
|
- 0x08C (PIN_OUTPUT | MUX_MODE7) /*GPMC_CLK => GPIO2_1*/ /*Speaker*/
|
|
|
- 0x0A0 (PIN_OUTPUT | MUX_MODE7) /*LCD_DATA0 => GPIO2_6*/ /*Panel LED control-BB_LEDR1*/
|
|
|
- 0x0A4 (PIN_OUTPUT | MUX_MODE7) /*LCD_DATA1 => GPIO2_7*/ /*Panel LED control-BB_LEDG1*/
|
|
|
- 0x0A8 (PIN_OUTPUT | MUX_MODE7) /*LCD_DATA2 => GPIO2_8*/ /*Panel LED control-BB_LEDB1*/
|
|
|
- 0x0AC (PIN_OUTPUT | MUX_MODE7) /*LCD_DATA3 => GPIO2_9*/ /*Panel LED control-BB_LEDR2*/
|
|
|
- 0x0B0 (PIN_OUTPUT | MUX_MODE7) /*LCD_DATA4 => GPIO2_10*/ /*Panel LED control-BB_LEDG2*/
|
|
|
- 0x0B4 (PIN_OUTPUT | MUX_MODE7) /*LCD_DATA5 => GPIO2_11*/ /*Panel LED control-BB_LEDB2*/
|
|
|
- 0x0E8 (PIN_INPUT | MUX_MODE7) /*LCD_PCLK => GPIO2_24*/ /*communication board proximity*/
|
|
|
- 0x0E0 (PIN_OUTPUT | MUX_MODE7) /*LCD_VSYNC => GPIO2_22*/ /*Breath LED*/
|
|
|
+ 0x0EC (PIN_OUTPUT | MUX_MODE7) /*LCD_AC_BIAS_EN => GPIO2_25*/ /*RS-485 for module DE control*/
|
|
|
+ 0x0E4 (PIN_OUTPUT | MUX_MODE7) /*LCD_HSYNC => GPIO2_23*/ /*RS-485 for module RE control*/
|
|
|
+ 0x0E8 (PIN_INPUT | MUX_MODE7) /*LCD_PCLK => GPIO2_24*/ /*CCS communication board 1 proximity*/
|
|
|
+ 0x0E0 (PIN_INPUT | MUX_MODE7) /*LCD_VSYNC => GPIO2_22*/ /*CCS communication board 2 proximity*/
|
|
|
+
|
|
|
/** GPIO 3 */
|
|
|
- 0x1A0 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR1 => GPIO3_18 */ /*control 4G reset pin*/
|
|
|
- 0x1A8 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR1 => GPIO3_20 */ /*control MCU to output CP PWM*/
|
|
|
+ AM33XX_IOPAD(0x9e4, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* (C14) EMU0.gpio3[7] */ /*CP open/short feature enable/disable, pull low for default enable*/
|
|
|
+ AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (B14) EMU1.gpio3[8] */ /*4G module reset, pull high to reset when entry kernel, after Application start, it should be pull low.*/
|
|
|
+ 0x194 (PIN_INPUT | MUX_MODE7) /*MCASP0_FSX => GPIO3_15*/ /*Emergency Stop button detect*/
|
|
|
+ 0x1A0 (PIN_INPUT | MUX_MODE7) /*MCASP0_ACLKR => GPIO3_18*/ /*USB1 OCP detect*/
|
|
|
+ 0x19C (PIN_INPUT | MUX_MODE7) /*MCASP0_AHCLKR => GPIO3_17*/ /*Emergency IO for AM3352 and STM32F407*/
|
|
|
+ 0x190 (PIN_OUTPUT | MUX_MODE7) /*MCASP0_ACLKX => GPIO3_14*/ /*Ethernet PHY reset*/
|
|
|
+ 0x1A4 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_FSR => GPIO3_19 */ /*SMR Enable control_1*/
|
|
|
+ 0x198 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR0 => GPIO3_16 */ /*CSU board function OK indicator.*/
|
|
|
+ 0x1A8 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR1 => GPIO3_20 */ /*SMR Enable control_2*/
|
|
|
+
|
|
|
>;
|
|
|
};
|
|
|
|
|
@@ -127,14 +140,14 @@
|
|
|
0x164 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ECAP0_IN_PWM0_OUT => uart3_txd */
|
|
|
>;
|
|
|
};
|
|
|
-#if 0
|
|
|
+
|
|
|
uart5_pins: pinmux_uart5_pins {
|
|
|
pinctrl-single,pins = <
|
|
|
- 0x0C0 (PIN_INPUT_PULLUP | MUX_MODE4) /* LCD_DATA8 => UART5_RXD*/
|
|
|
- 0x0C4 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* LCD_DATA9 => UART5_TXD*/
|
|
|
+ 0x0C0 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* LCD_DATA8 => DUART5_TX*/
|
|
|
+ 0x0C4 (PIN_INPUT_PULLUP | MUX_MODE4) /* LCD_DATA9 => UART5_RX*/
|
|
|
>;
|
|
|
};
|
|
|
-#endif
|
|
|
+
|
|
|
clkout2_pin: pinmux_clkout2_pin {
|
|
|
pinctrl-single,pins = <
|
|
|
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
|
@@ -185,12 +198,12 @@
|
|
|
pinctrl-single,pins = <
|
|
|
|
|
|
/* Slave 1 */
|
|
|
- //0x108 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* MII1_COL.gmii1_col */
|
|
|
- //0x10C(PIN_INPUT_PULLDOWN | MUX_MODE0) /* MII1_CRS.MII1_CRS */
|
|
|
+ 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* MII1_COL.gmii1_col */
|
|
|
+ 0x10C(PIN_INPUT_PULLUP | MUX_MODE0) /* MII1_CRS.MII1_CRS */
|
|
|
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* MII1_RX_ER.gmii1_rxerr */
|
|
|
- 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
|
|
|
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
|
|
|
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
|
|
|
+ 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
|
|
|
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.rgmii1_rd3 */
|
|
|
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.rgmii1_rd2 */
|
|
|
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.rgmii1_rd1 */
|
|
@@ -199,7 +212,24 @@
|
|
|
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.rgmii1_td3 */
|
|
|
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.rgmii1_td2 */
|
|
|
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.rgmii1_td1 */
|
|
|
- 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.rgmii1_td0 */
|
|
|
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.rgmii1_td0 */
|
|
|
+
|
|
|
+ /* Slave 2 */
|
|
|
+ AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ben1.mii2_col */
|
|
|
+ AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) /* GPMC_CSn3.rmii2_crs_dv*/
|
|
|
+ /*AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE1)*/ /* gpmc_wpn.mii2_rxerr */
|
|
|
+ AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a6.mii2_txclk */
|
|
|
+ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
|
|
|
+ AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
|
|
|
+ AM33XX_IOPAD(0x860, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
|
|
|
+ AM33XX_IOPAD(0x864, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
|
|
|
+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
|
|
|
+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
|
|
|
+ AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a0.mii2_txen */
|
|
|
+ AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
|
|
|
+ AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
|
|
|
+ AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
|
|
|
+ AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
|
|
|
|
|
|
>;
|
|
|
};
|
|
@@ -220,6 +250,23 @@
|
|
|
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
|
+ /* Slave 2 */
|
|
|
+ AM33XX_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* GPMC_CSn3.rmii2_crs_dv*/
|
|
|
+ AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.mii2_txen */
|
|
|
+ AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mii2_rxdv */
|
|
|
+ AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mii2_txd3 */
|
|
|
+ AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mii2_txd2 */
|
|
|
+ AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.mii2_txd1 */
|
|
|
+ AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.mii2_txd0 */
|
|
|
+ AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.mii2_txclk */
|
|
|
+ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.mii2_rxclk */
|
|
|
+ AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.mii2_rxd3 */
|
|
|
+ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.mii2_rxd2 */
|
|
|
+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.mii2_rxd1 */
|
|
|
+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.mii2_rxd0 */
|
|
|
+ /*AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE7)*/ /* gpmc_wpn.mii2_rxerr */
|
|
|
+ AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben1.mii2_col */
|
|
|
+
|
|
|
>;
|
|
|
};
|
|
|
|
|
@@ -258,14 +305,14 @@
|
|
|
0x17C (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn => d_can0_rx */
|
|
|
>;
|
|
|
};
|
|
|
-#if 0
|
|
|
+
|
|
|
dcan1_pins_default: dcan1_pins_default {
|
|
|
pinctrl-single,pins = <
|
|
|
0x168 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* UART0_CTSn => d_can1_tx */
|
|
|
0x16C (PIN_INPUT_PULLDOWN | MUX_MODE2) /* UART0_RTSn => d_can1_rx */
|
|
|
>;
|
|
|
};
|
|
|
-
|
|
|
+#if 0
|
|
|
ehrpwm1_pins: ehrpwm1_pins {
|
|
|
pinctrl-single,pins = <
|
|
|
0x0C8 (PIN_OUTPUT | MUX_MODE2) /* LCD_DATA10.eHRPWM1A */
|
|
@@ -276,16 +323,9 @@
|
|
|
pinctrl-single,pins =<
|
|
|
0x0A4 (PIN_OUTPUT | MUX_MODE3) /* LCD_DATA1.eHRPWM2B */
|
|
|
>;
|
|
|
- };
|
|
|
+ };
|
|
|
+
|
|
|
#endif
|
|
|
- spi1_pins: spi1_pins {
|
|
|
- pinctrl-single,pins = <
|
|
|
- AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE3) /* MCASP0_ACLKX.AM_SPI1_SCLK */
|
|
|
- AM33XX_IOPAD(0x994, PIN_INPUT_PULLUP | MUX_MODE3) /* MCASP0_FSX.AM_SPI1_D0 */
|
|
|
- AM33XX_IOPAD(0x998, PIN_OUTPUT_PULLUP | MUX_MODE3) /* MCASP0_AXR0.AM_SPI1_D1 */
|
|
|
- AM33XX_IOPAD(0x99C, PIN_OUTPUT_PULLUP | MUX_MODE3) /* MCASP0_AHCLKR.AM_SPI1_CS0 */
|
|
|
- >;
|
|
|
- };
|
|
|
};
|
|
|
|
|
|
|
|
@@ -317,14 +357,14 @@
|
|
|
|
|
|
status = "okay";
|
|
|
};
|
|
|
-#if 0
|
|
|
+
|
|
|
&uart5 {
|
|
|
pinctrl-names = "default";
|
|
|
pinctrl-0 = <&uart5_pins>;
|
|
|
|
|
|
status = "okay";
|
|
|
};
|
|
|
-#endif
|
|
|
+
|
|
|
&i2c0 {
|
|
|
pinctrl-names = "default";
|
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
@@ -335,11 +375,11 @@
|
|
|
tps: tps@2d {
|
|
|
reg = <0x2d>;
|
|
|
};
|
|
|
-
|
|
|
+
|
|
|
/* rtc0: rtc@51 {
|
|
|
- compatible = "nxp,pcf85063";
|
|
|
- reg = <0x51>;
|
|
|
- };*/
|
|
|
+ compatible = "nxp,pcf85063";
|
|
|
+ reg = <0x51>;
|
|
|
+ };*/
|
|
|
};
|
|
|
#if 1
|
|
|
&i2c1 {
|
|
@@ -353,7 +393,6 @@
|
|
|
compatible = "nxp,pcf85063";
|
|
|
reg = <0x51>;
|
|
|
};
|
|
|
-
|
|
|
};
|
|
|
#endif
|
|
|
&usb {
|
|
@@ -509,7 +548,7 @@
|
|
|
};
|
|
|
partition@13 {
|
|
|
label = "Storage";
|
|
|
- reg = <0x0A200000 0x35E00000>;
|
|
|
+ reg = <0x0A200000 0x75E00000>;
|
|
|
};
|
|
|
};
|
|
|
};
|
|
@@ -597,6 +636,7 @@
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
pinctrl-0 = <&cpsw_default>;
|
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
|
+ dual_emac = <1>;
|
|
|
status = "okay";
|
|
|
};
|
|
|
|
|
@@ -605,21 +645,19 @@
|
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
|
status = "okay";
|
|
|
- //reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
|
|
|
};
|
|
|
|
|
|
&cpsw_emac0 {
|
|
|
phy_id = <&davinci_mdio>, <1>;
|
|
|
phy-mode = "mii";
|
|
|
-
|
|
|
+ dual_emac_res_vlan = <1>;
|
|
|
};
|
|
|
-#if 0
|
|
|
+
|
|
|
&cpsw_emac1 {
|
|
|
phy_id = <&davinci_mdio>, <2>;
|
|
|
phy-mode = "mii";
|
|
|
-
|
|
|
+ dual_emac_res_vlan = <2>;
|
|
|
};
|
|
|
-#endif
|
|
|
|
|
|
&tscadc {
|
|
|
status = "okay";
|
|
@@ -667,35 +705,9 @@
|
|
|
pinctrl-names = "default";
|
|
|
pinctrl-0 = <&dcan0_pins_default>;
|
|
|
};
|
|
|
-#if 0
|
|
|
+
|
|
|
&dcan1 {
|
|
|
status = "okay";
|
|
|
pinctrl-names = "default";
|
|
|
pinctrl-0 = <&dcan1_pins_default>;
|
|
|
};
|
|
|
-#endif
|
|
|
-
|
|
|
-/*
|
|
|
-The QCA7000 acts as a SPI slave and uses Mode 3: CPOL=1, CPHA=1.
|
|
|
-SPI data width is 8 bit. The SPI CLK period should not be less than 83.3 ns
|
|
|
-The SPI should be used in burst mode, meaning that the chip select is held low during a complete SPI message.
|
|
|
- Note: The SPI lines between Host CPU and QCA7000 should be kept as short as possible.
|
|
|
-
|
|
|
-*/
|
|
|
-&spi1 {
|
|
|
- status = "okay";
|
|
|
- pinctrl-names = "default";
|
|
|
- pinctrl-0 = <&spi1_pins>;
|
|
|
- qca7000@0 {
|
|
|
- compatible = "qca,qca7000";
|
|
|
- reg = <0>;
|
|
|
- interrupt-parent = <&gpio2>; /* GPIO2_0 */
|
|
|
- interrupts = <0 1>; /* GPIO2_0 */
|
|
|
- spi-cpha; /* SPI mode: CPHA=1 */
|
|
|
- spi-cpol; /* SPI mode: CPOL=1 */
|
|
|
- spi-max-frequency = <10000000>; /* freq: 10MHz */
|
|
|
- qca,legacy-mode = <0>; /* Burst mode */
|
|
|
- };
|
|
|
-};
|
|
|
-
|
|
|
-
|