cslr_unicache_ctm.h 20 KB

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  1. /********************************************************************
  2. * Copyright (C) 2013-2014 Texas Instruments Incorporated.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. *
  11. * Redistributions in binary form must reproduce the above copyright
  12. * notice, this list of conditions and the following disclaimer in the
  13. * documentation and/or other materials provided with the
  14. * distribution.
  15. *
  16. * Neither the name of Texas Instruments Incorporated nor the names of
  17. * its contributors may be used to endorse or promote products derived
  18. * from this software without specific prior written permission.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. *
  32. */
  33. #ifndef CSLR_UNICACHECTM_H_
  34. #define CSLR_UNICACHECTM_H_
  35. #ifdef __cplusplus
  36. extern "C"
  37. {
  38. #endif
  39. #include <ti/csl/cslr.h>
  40. #include <ti/csl/tistdtypes.h>
  41. /**************************************************************************
  42. * Register Overlay Structure for __ALL__
  43. **************************************************************************/
  44. typedef struct {
  45. volatile Uint32 CTCNTL;
  46. volatile Uint8 RSVD0[28];
  47. volatile Uint32 CTSTMCNTL;
  48. volatile Uint32 CTSTMMSTID;
  49. volatile Uint32 CTSTMINTVL;
  50. volatile Uint32 CTSTMSEL;
  51. volatile Uint8 RSVD1[16];
  52. volatile Uint32 TINTVLR[2];
  53. volatile Uint8 RSVD2[52];
  54. volatile Uint32 CTDBGNUM;
  55. volatile Uint8 RSVD3[112];
  56. volatile Uint32 CTGNBL;
  57. volatile Uint8 RSVD4[4];
  58. volatile Uint32 CTGRST;
  59. volatile Uint8 RSVD5[4];
  60. volatile Uint32 CTCR_WT[2];
  61. volatile Uint32 CTCR_WOT[6];
  62. volatile Uint8 RSVD6[96];
  63. volatile Uint32 CTCNTR[8];
  64. } CSL_UnicacheCtmRegs;
  65. /**************************************************************************
  66. * Register Macros
  67. **************************************************************************/
  68. /* CTCNTL */
  69. #define CSL_UNICACHECTM_CTCNTL (0x0U)
  70. /* This register contains the control and status settings for STM export */
  71. #define CSL_UNICACHECTM_CTSTMCNTL (0x20U)
  72. /* CTSTMMSTID */
  73. #define CSL_UNICACHECTM_CTSTMMSTID (0x24U)
  74. /* CTSTMINTVL */
  75. #define CSL_UNICACHECTM_CTSTMINTVL (0x28U)
  76. /* These registers mark the counters selected for export in the CSM */
  77. #define CSL_UNICACHECTM_CTSTMSEL (0x2CU)
  78. /* These registers contain the interval match value for the corresponding
  79. * timers in the SCTM */
  80. #define CSL_UNICACHECTM_TINTVLR(i) (0x40U + ((i) * (0x4U)))
  81. /* Counter Timer Number Debug Event Register */
  82. #define CSL_UNICACHECTM_CTDBGNUM (0x7CU)
  83. /* Counter Timer Debug Event Register */
  84. #define CSL_UNICACHECTM_CTDBGEVT(i) (0x80U + ((i) * (0x4U)))
  85. /* These registers provide for simultaneous enable/disable of 32 counters */
  86. #define CSL_UNICACHECTM_CTGNBL (0xF0U)
  87. /* These registers provide for simultaneous reset of 32 counters */
  88. #define CSL_UNICACHECTM_CTGRST (0xF8U)
  89. /* These registers contain the control and status settings for a single
  90. * counter in the module. There will be a CTCR for every counter in the module
  91. * (WT: with timer) */
  92. #define CSL_UNICACHECTM_CTCR_WT(i) (0x100U + ((i) * (0x4U)))
  93. /* These registers contain the control and status settings for a single
  94. * counter in the module. There will be a CTCR for every counter in the module
  95. * (WOT: without timer) */
  96. #define CSL_UNICACHECTM_CTCR_WOT(i) (0x108U + ((i) * (0x4U)))
  97. /* These registers contain the value of an individual counter in the moduel.
  98. * There will be a CTCNTR for every counter in the module */
  99. #define CSL_UNICACHECTM_CTCNTR(i) (0x180U + ((i) * (0x4U)))
  100. /**************************************************************************
  101. * Field Definition Macros
  102. **************************************************************************/
  103. /* CTCNTL */
  104. #define CSL_UNICACHECTM_CTCNTL_ENBL_MASK (0x00000001U)
  105. #define CSL_UNICACHECTM_CTCNTL_ENBL_SHIFT (0U)
  106. #define CSL_UNICACHECTM_CTCNTL_ENBL_RESETVAL (0x00000000U)
  107. #define CSL_UNICACHECTM_CTCNTL_ENBL_DISABLE (0x00000000U)
  108. #define CSL_UNICACHECTM_CTCNTL_ENBL_ENABLE (0x00000001U)
  109. #define CSL_UNICACHECTM_CTCNTL_IDLEMODE_MASK (0x00000006U)
  110. #define CSL_UNICACHECTM_CTCNTL_IDLEMODE_SHIFT (1U)
  111. #define CSL_UNICACHECTM_CTCNTL_IDLEMODE_RESETVAL (0x00000002U)
  112. #define CSL_UNICACHECTM_CTCNTL_IDLEMODE_FORCE_IDLE (0x00000000U)
  113. #define CSL_UNICACHECTM_CTCNTL_IDLEMODE_NO_IDLE (0x00000001U)
  114. #define CSL_UNICACHECTM_CTCNTL_IDLEMODE_SMART_IDLE (0x00000002U)
  115. #define CSL_UNICACHECTM_CTCNTL_IDLEMODE_SMART_IDLE_WAKEUP (0x00000003U)
  116. #define CSL_UNICACHECTM_CTCNTL_REVID_MASK (0x00000078U)
  117. #define CSL_UNICACHECTM_CTCNTL_REVID_SHIFT (3U)
  118. #define CSL_UNICACHECTM_CTCNTL_REVID_RESETVAL (0x00000001U)
  119. #define CSL_UNICACHECTM_CTCNTL_REVID_MAX (0x0000000fU)
  120. #define CSL_UNICACHECTM_CTCNTL_NUMCNTR_MASK (0x00001F80U)
  121. #define CSL_UNICACHECTM_CTCNTL_NUMCNTR_SHIFT (7U)
  122. #define CSL_UNICACHECTM_CTCNTL_NUMCNTR_RESETVAL (0x00000008U)
  123. #define CSL_UNICACHECTM_CTCNTL_NUMCNTR_MAX (0x0000003fU)
  124. #define CSL_UNICACHECTM_CTCNTL_NUMTIMR_MASK (0x0003E000U)
  125. #define CSL_UNICACHECTM_CTCNTL_NUMTIMR_SHIFT (13U)
  126. #define CSL_UNICACHECTM_CTCNTL_NUMTIMR_RESETVAL (0x00000002U)
  127. #define CSL_UNICACHECTM_CTCNTL_NUMTIMR_MAX (0x0000001fU)
  128. #define CSL_UNICACHECTM_CTCNTL_NUMINPT_MASK (0x03FC0000U)
  129. #define CSL_UNICACHECTM_CTCNTL_NUMINPT_SHIFT (18U)
  130. #define CSL_UNICACHECTM_CTCNTL_NUMINPT_RESETVAL (0x00000020U)
  131. #define CSL_UNICACHECTM_CTCNTL_NUMINPT_MAX (0x000000ffU)
  132. #define CSL_UNICACHECTM_CTCNTL_NUMSTM_MASK (0xFC000000U)
  133. #define CSL_UNICACHECTM_CTCNTL_NUMSTM_SHIFT (26U)
  134. #define CSL_UNICACHECTM_CTCNTL_NUMSTM_RESETVAL (0x00000000U)
  135. #define CSL_UNICACHECTM_CTCNTL_NUMSTM_MAX (0x0000003fU)
  136. #define CSL_UNICACHECTM_CTCNTL_RESETVAL (0x0080440cU)
  137. /* CTSTMCNTL */
  138. #define CSL_UNICACHECTM_CTSTMCNTL_ENBL_MASK (0x00000001U)
  139. #define CSL_UNICACHECTM_CTSTMCNTL_ENBL_SHIFT (0U)
  140. #define CSL_UNICACHECTM_CTSTMCNTL_ENBL_RESETVAL (0x00000000U)
  141. #define CSL_UNICACHECTM_CTSTMCNTL_ENBL_DISABLE (0x00000000U)
  142. #define CSL_UNICACHECTM_CTSTMCNTL_ENBL_ENABLE (0x00000001U)
  143. #define CSL_UNICACHECTM_CTSTMCNTL_SENDOVR_MASK (0x00000002U)
  144. #define CSL_UNICACHECTM_CTSTMCNTL_SENDOVR_SHIFT (1U)
  145. #define CSL_UNICACHECTM_CTSTMCNTL_SENDOVR_RESETVAL (0x00000001U)
  146. #define CSL_UNICACHECTM_CTSTMCNTL_SENDOVR_MAX (0x00000001U)
  147. #define CSL_UNICACHECTM_CTSTMCNTL_CSMXPORT_MASK (0x00000004U)
  148. #define CSL_UNICACHECTM_CTSTMCNTL_CSMXPORT_SHIFT (2U)
  149. #define CSL_UNICACHECTM_CTSTMCNTL_CSMXPORT_RESETVAL (0x00000000U)
  150. #define CSL_UNICACHECTM_CTSTMCNTL_CSMXPORT_MAX (0x00000001U)
  151. #define CSL_UNICACHECTM_CTSTMCNTL_CCMVAIL_MASK (0x00000008U)
  152. #define CSL_UNICACHECTM_CTSTMCNTL_CCMVAIL_SHIFT (3U)
  153. #define CSL_UNICACHECTM_CTSTMCNTL_CCMVAIL_RESETVAL (0x00000000U)
  154. #define CSL_UNICACHECTM_CTSTMCNTL_CCMVAIL_MAX (0x00000001U)
  155. #define CSL_UNICACHECTM_CTSTMCNTL_CCMXPORT_MASK (0x00000010U)
  156. #define CSL_UNICACHECTM_CTSTMCNTL_CCMXPORT_SHIFT (4U)
  157. #define CSL_UNICACHECTM_CTSTMCNTL_CCMXPORT_RESETVAL (0x00000000U)
  158. #define CSL_UNICACHECTM_CTSTMCNTL_CCMXPORT_MAX (0x00000001U)
  159. #define CSL_UNICACHECTM_CTSTMCNTL_NUMXPORT_MASK (0x000003E0U)
  160. #define CSL_UNICACHECTM_CTSTMCNTL_NUMXPORT_SHIFT (5U)
  161. #define CSL_UNICACHECTM_CTSTMCNTL_NUMXPORT_RESETVAL (0x00000000U)
  162. #define CSL_UNICACHECTM_CTSTMCNTL_NUMXPORT_MAX (0x0000001fU)
  163. #define CSL_UNICACHECTM_CTSTMCNTL_XPORTACT_MASK (0x00000400U)
  164. #define CSL_UNICACHECTM_CTSTMCNTL_XPORTACT_SHIFT (10U)
  165. #define CSL_UNICACHECTM_CTSTMCNTL_XPORTACT_RESETVAL (0x00000000U)
  166. #define CSL_UNICACHECTM_CTSTMCNTL_XPORTACT_MAX (0x00000001U)
  167. #define CSL_UNICACHECTM_CTSTMCNTL_RESETVAL (0x00000002U)
  168. /* CTSTMMSTID */
  169. #define CSL_UNICACHECTM_CTSTMMSTID_MASTID_MASK (0x0000007FU)
  170. #define CSL_UNICACHECTM_CTSTMMSTID_MASTID_SHIFT (0U)
  171. #define CSL_UNICACHECTM_CTSTMMSTID_MASTID_RESETVAL (0x00000000U)
  172. #define CSL_UNICACHECTM_CTSTMMSTID_MASTID_MAX (0x0000007fU)
  173. #define CSL_UNICACHECTM_CTSTMMSTID_RESETVAL (0x00000000U)
  174. /* CTSTMINTVL */
  175. #define CSL_UNICACHECTM_CTSTMINTVL_INTERVAL_MASK (0x0000FFFFU)
  176. #define CSL_UNICACHECTM_CTSTMINTVL_INTERVAL_SHIFT (0U)
  177. #define CSL_UNICACHECTM_CTSTMINTVL_INTERVAL_RESETVAL (0x00000000U)
  178. #define CSL_UNICACHECTM_CTSTMINTVL_INTERVAL_MAX (0x0000ffffU)
  179. #define CSL_UNICACHECTM_CTSTMINTVL_RESETVAL (0x00000000U)
  180. /* CTSTMSEL */
  181. #define CSL_UNICACHECTM_CTSTMSEL_COUNTSEL_MASK (0xFFFFFFFFU)
  182. #define CSL_UNICACHECTM_CTSTMSEL_COUNTSEL_SHIFT (0U)
  183. #define CSL_UNICACHECTM_CTSTMSEL_COUNTSEL_RESETVAL (0x00000000U)
  184. #define CSL_UNICACHECTM_CTSTMSEL_COUNTSEL_MAX (0xffffffffU)
  185. #define CSL_UNICACHECTM_CTSTMSEL_RESETVAL (0x00000000U)
  186. /* TINTVLR */
  187. #define CSL_UNICACHECTM_TINTVLR_INTERVAL_MASK (0xFFFFFFFFU)
  188. #define CSL_UNICACHECTM_TINTVLR_INTERVAL_SHIFT (0U)
  189. #define CSL_UNICACHECTM_TINTVLR_INTERVAL_RESETVAL (0x00000000U)
  190. #define CSL_UNICACHECTM_TINTVLR_INTERVAL_MAX (0xffffffffU)
  191. #define CSL_UNICACHECTM_TINTVLR_RESETVAL (0x00000000U)
  192. /* CTDBGNUM */
  193. #define CSL_UNICACHECTM_CTDBGNUM_NUMEVT_MASK (0x00000007U)
  194. #define CSL_UNICACHECTM_CTDBGNUM_NUMEVT_SHIFT (0U)
  195. #define CSL_UNICACHECTM_CTDBGNUM_NUMEVT_RESETVAL (0x00000000U)
  196. #define CSL_UNICACHECTM_CTDBGNUM_NUMEVT_MAX (0x00000007U)
  197. #define CSL_UNICACHECTM_CTDBGNUM_RESETVAL (0x00000000U)
  198. /* CTDBGEVT */
  199. #define CSL_UNICACHECTM_CTDBGEVT_INPSEL_MASK (0x000000FFU)
  200. #define CSL_UNICACHECTM_CTDBGEVT_INPSEL_SHIFT (0U)
  201. #define CSL_UNICACHECTM_CTDBGEVT_INPSEL_RESETVAL (0x00000000U)
  202. #define CSL_UNICACHECTM_CTDBGEVT_INPSEL_MAX (0x000000ffU)
  203. #define CSL_UNICACHECTM_CTDBGEVT_RESETVAL (0x00000000U)
  204. /* CTGNBL */
  205. #define CSL_UNICACHECTM_CTGNBL_ENABLE_MASK (0x000000FFU)
  206. #define CSL_UNICACHECTM_CTGNBL_ENABLE_SHIFT (0U)
  207. #define CSL_UNICACHECTM_CTGNBL_ENABLE_RESETVAL (0x00000000U)
  208. #define CSL_UNICACHECTM_CTGNBL_ENABLE_MAX (0x000000ffU)
  209. #define CSL_UNICACHECTM_CTGNBL_RESETVAL (0x00000000U)
  210. /* CTGRST */
  211. #define CSL_UNICACHECTM_CTGRST_RESET_MASK (0x000000FFU)
  212. #define CSL_UNICACHECTM_CTGRST_RESET_SHIFT (0U)
  213. #define CSL_UNICACHECTM_CTGRST_RESET_RESETVAL (0x00000000U)
  214. #define CSL_UNICACHECTM_CTGRST_RESET_MAX (0x000000ffU)
  215. #define CSL_UNICACHECTM_CTGRST_RESETVAL (0x00000000U)
  216. /* CTCR_WT */
  217. #define CSL_UNICACHECTM_CTCR_WT_ENBL_MASK (0x00000001U)
  218. #define CSL_UNICACHECTM_CTCR_WT_ENBL_SHIFT (0U)
  219. #define CSL_UNICACHECTM_CTCR_WT_ENBL_RESETVAL (0x00000000U)
  220. #define CSL_UNICACHECTM_CTCR_WT_ENBL_MAX (0x00000001U)
  221. #define CSL_UNICACHECTM_CTCR_WT_RESET_MASK (0x00000002U)
  222. #define CSL_UNICACHECTM_CTCR_WT_RESET_SHIFT (1U)
  223. #define CSL_UNICACHECTM_CTCR_WT_RESET_RESETVAL (0x00000000U)
  224. #define CSL_UNICACHECTM_CTCR_WT_RESET_MAX (0x00000001U)
  225. #define CSL_UNICACHECTM_CTCR_WT_CHAIN_MASK (0x00000004U)
  226. #define CSL_UNICACHECTM_CTCR_WT_CHAIN_SHIFT (2U)
  227. #define CSL_UNICACHECTM_CTCR_WT_CHAIN_RESETVAL (0x00000000U)
  228. #define CSL_UNICACHECTM_CTCR_WT_CHAIN_MAX (0x00000001U)
  229. #define CSL_UNICACHECTM_CTCR_WT_DURMODE_MASK (0x00000008U)
  230. #define CSL_UNICACHECTM_CTCR_WT_DURMODE_SHIFT (3U)
  231. #define CSL_UNICACHECTM_CTCR_WT_DURMODE_RESETVAL (0x00000000U)
  232. #define CSL_UNICACHECTM_CTCR_WT_DURMODE_MAX (0x00000001U)
  233. #define CSL_UNICACHECTM_CTCR_WT_FREE_MASK (0x00000010U)
  234. #define CSL_UNICACHECTM_CTCR_WT_FREE_SHIFT (4U)
  235. #define CSL_UNICACHECTM_CTCR_WT_FREE_RESETVAL (0x00000000U)
  236. #define CSL_UNICACHECTM_CTCR_WT_FREE_MAX (0x00000001U)
  237. #define CSL_UNICACHECTM_CTCR_WT_IDLE_MASK (0x00000020U)
  238. #define CSL_UNICACHECTM_CTCR_WT_IDLE_SHIFT (5U)
  239. #define CSL_UNICACHECTM_CTCR_WT_IDLE_RESETVAL (0x00000000U)
  240. #define CSL_UNICACHECTM_CTCR_WT_IDLE_MAX (0x00000001U)
  241. #define CSL_UNICACHECTM_CTCR_WT_OVRFLW_MASK (0x00000040U)
  242. #define CSL_UNICACHECTM_CTCR_WT_OVRFLW_SHIFT (6U)
  243. #define CSL_UNICACHECTM_CTCR_WT_OVRFLW_RESETVAL (0x00000000U)
  244. #define CSL_UNICACHECTM_CTCR_WT_OVRFLW_MAX (0x00000001U)
  245. #define CSL_UNICACHECTM_CTCR_WT_INT_MASK (0x00000100U)
  246. #define CSL_UNICACHECTM_CTCR_WT_INT_SHIFT (8U)
  247. #define CSL_UNICACHECTM_CTCR_WT_INT_RESETVAL (0x00000000U)
  248. #define CSL_UNICACHECTM_CTCR_WT_INT_MAX (0x00000001U)
  249. #define CSL_UNICACHECTM_CTCR_WT_DBG_MASK (0x00000200U)
  250. #define CSL_UNICACHECTM_CTCR_WT_DBG_SHIFT (9U)
  251. #define CSL_UNICACHECTM_CTCR_WT_DBG_RESETVAL (0x00000000U)
  252. #define CSL_UNICACHECTM_CTCR_WT_DBG_MAX (0x00000001U)
  253. #define CSL_UNICACHECTM_CTCR_WT_RESTART_MASK (0x00000400U)
  254. #define CSL_UNICACHECTM_CTCR_WT_RESTART_SHIFT (10U)
  255. #define CSL_UNICACHECTM_CTCR_WT_RESTART_RESETVAL (0x00000000U)
  256. #define CSL_UNICACHECTM_CTCR_WT_RESTART_MAX (0x00000001U)
  257. #define CSL_UNICACHECTM_CTCR_WT_INPSEL_MASK (0x001F0000U)
  258. #define CSL_UNICACHECTM_CTCR_WT_INPSEL_SHIFT (16U)
  259. #define CSL_UNICACHECTM_CTCR_WT_INPSEL_RESETVAL (0x00000000U)
  260. #define CSL_UNICACHECTM_CTCR_WT_INPSEL_MAX (0x0000001fU)
  261. #define CSL_UNICACHECTM_CTCR_WT_RESETVAL (0x00000000U)
  262. /* CTCR_WOT */
  263. #define CSL_UNICACHECTM_CTCR_WOT_ENBL_MASK (0x00000001U)
  264. #define CSL_UNICACHECTM_CTCR_WOT_ENBL_SHIFT (0U)
  265. #define CSL_UNICACHECTM_CTCR_WOT_ENBL_RESETVAL (0x00000000U)
  266. #define CSL_UNICACHECTM_CTCR_WOT_ENBL_MAX (0x00000001U)
  267. #define CSL_UNICACHECTM_CTCR_WOT_RESET_MASK (0x00000002U)
  268. #define CSL_UNICACHECTM_CTCR_WOT_RESET_SHIFT (1U)
  269. #define CSL_UNICACHECTM_CTCR_WOT_RESET_RESETVAL (0x00000000U)
  270. #define CSL_UNICACHECTM_CTCR_WOT_RESET_MAX (0x00000001U)
  271. #define CSL_UNICACHECTM_CTCR_WOT_CHAIN_MASK (0x00000004U)
  272. #define CSL_UNICACHECTM_CTCR_WOT_CHAIN_SHIFT (2U)
  273. #define CSL_UNICACHECTM_CTCR_WOT_CHAIN_RESETVAL (0x00000000U)
  274. #define CSL_UNICACHECTM_CTCR_WOT_CHAIN_MAX (0x00000001U)
  275. #define CSL_UNICACHECTM_CTCR_WOT_DURMODE_MASK (0x00000008U)
  276. #define CSL_UNICACHECTM_CTCR_WOT_DURMODE_SHIFT (3U)
  277. #define CSL_UNICACHECTM_CTCR_WOT_DURMODE_RESETVAL (0x00000000U)
  278. #define CSL_UNICACHECTM_CTCR_WOT_DURMODE_MAX (0x00000001U)
  279. #define CSL_UNICACHECTM_CTCR_WOT_FREE_MASK (0x00000010U)
  280. #define CSL_UNICACHECTM_CTCR_WOT_FREE_SHIFT (4U)
  281. #define CSL_UNICACHECTM_CTCR_WOT_FREE_RESETVAL (0x00000000U)
  282. #define CSL_UNICACHECTM_CTCR_WOT_FREE_MAX (0x00000001U)
  283. #define CSL_UNICACHECTM_CTCR_WOT_IDLE_MASK (0x00000020U)
  284. #define CSL_UNICACHECTM_CTCR_WOT_IDLE_SHIFT (5U)
  285. #define CSL_UNICACHECTM_CTCR_WOT_IDLE_RESETVAL (0x00000000U)
  286. #define CSL_UNICACHECTM_CTCR_WOT_IDLE_MAX (0x00000001U)
  287. #define CSL_UNICACHECTM_CTCR_WOT_OVRFLW_MASK (0x00000040U)
  288. #define CSL_UNICACHECTM_CTCR_WOT_OVRFLW_SHIFT (6U)
  289. #define CSL_UNICACHECTM_CTCR_WOT_OVRFLW_RESETVAL (0x00000000U)
  290. #define CSL_UNICACHECTM_CTCR_WOT_OVRFLW_MAX (0x00000001U)
  291. #define CSL_UNICACHECTM_CTCR_WOT_INT_MASK (0x00000100U)
  292. #define CSL_UNICACHECTM_CTCR_WOT_INT_SHIFT (8U)
  293. #define CSL_UNICACHECTM_CTCR_WOT_INT_RESETVAL (0x00000000U)
  294. #define CSL_UNICACHECTM_CTCR_WOT_INT_MAX (0x00000001U)
  295. #define CSL_UNICACHECTM_CTCR_WOT_DBG_MASK (0x00000200U)
  296. #define CSL_UNICACHECTM_CTCR_WOT_DBG_SHIFT (9U)
  297. #define CSL_UNICACHECTM_CTCR_WOT_DBG_RESETVAL (0x00000000U)
  298. #define CSL_UNICACHECTM_CTCR_WOT_DBG_MAX (0x00000001U)
  299. #define CSL_UNICACHECTM_CTCR_WOT_RESTART_MASK (0x00000400U)
  300. #define CSL_UNICACHECTM_CTCR_WOT_RESTART_SHIFT (10U)
  301. #define CSL_UNICACHECTM_CTCR_WOT_RESTART_RESETVAL (0x00000000U)
  302. #define CSL_UNICACHECTM_CTCR_WOT_RESTART_MAX (0x00000001U)
  303. #define CSL_UNICACHECTM_CTCR_WOT_INPSEL_MASK (0x001F0000U)
  304. #define CSL_UNICACHECTM_CTCR_WOT_INPSEL_SHIFT (16U)
  305. #define CSL_UNICACHECTM_CTCR_WOT_INPSEL_RESETVAL (0x00000000U)
  306. #define CSL_UNICACHECTM_CTCR_WOT_INPSEL_MAX (0x0000001fU)
  307. #define CSL_UNICACHECTM_CTCR_WOT_RESETVAL (0x00000000U)
  308. /* CTCNTR */
  309. #define CSL_UNICACHECTM_CTCNTR_COUNT_MASK (0xFFFFFFFFU)
  310. #define CSL_UNICACHECTM_CTCNTR_COUNT_SHIFT (0U)
  311. #define CSL_UNICACHECTM_CTCNTR_COUNT_RESETVAL (0x00000000U)
  312. #define CSL_UNICACHECTM_CTCNTR_COUNT_MAX (0xffffffffU)
  313. #define CSL_UNICACHECTM_CTCNTR_RESETVAL (0x00000000U)
  314. #ifdef __cplusplus
  315. }
  316. #endif
  317. #endif