cslr_spi.h 85 KB

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  1. /********************************************************************
  2. * Copyright ((uint32_t)C) 2013-2016 Texas Instruments Incorporated.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. *
  11. * Redistributions in binary form must reproduce the above copyright
  12. * notice, this list of conditions and the following disclaimer in the
  13. * documentation and/or other materials provided with the
  14. * distribution.
  15. *
  16. * Neither the name of Texas Instruments Incorporated nor the names of
  17. * its contributors may be used to endorse or promote products derived
  18. * from this software without specific prior written permission.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. *
  32. */
  33. #ifndef CSLR_SPI_H
  34. #define CSLR_SPI_H
  35. #ifdef __cplusplus
  36. extern "C"
  37. {
  38. #endif
  39. #include <ti/csl/cslr.h>
  40. #include <ti/csl/tistdtypes.h>
  41. /**************************************************************************
  42. * Register Overlay Structure for TOP_LEVEL
  43. **************************************************************************/
  44. typedef struct {
  45. volatile Uint32 SPIGCR0;
  46. volatile Uint32 SPIGCR1;
  47. volatile Uint32 SPIINT0;
  48. volatile Uint32 SPILVL;
  49. volatile Uint32 SPIFLG;
  50. volatile Uint32 SPIPC0;
  51. volatile Uint32 SPIPC1;
  52. volatile Uint32 SPIPC2;
  53. volatile Uint32 SPIPC3;
  54. volatile Uint32 SPIPC4;
  55. volatile Uint32 SPIPC5;
  56. volatile Uint32 SPIPC6;
  57. volatile Uint32 SPIPC7;
  58. volatile Uint32 SPIPC8;
  59. volatile Uint32 SPIDAT0;
  60. volatile Uint32 SPIDAT1;
  61. volatile Uint32 SPIBUF;
  62. volatile Uint32 SPIEMU;
  63. volatile Uint32 SPIDELAY;
  64. volatile Uint32 SPIDEF;
  65. volatile Uint32 SPIFMT[4];
  66. volatile Uint32 INTVEC[2];
  67. volatile Uint32 SPISRSEL;
  68. volatile Uint32 SPIPMCTRL;
  69. volatile Uint32 MIBSPIE;
  70. volatile Uint32 TGITENST;
  71. volatile Uint32 TGITENCR;
  72. volatile Uint8 RSVD0[4];
  73. volatile Uint32 TGITLVST;
  74. volatile Uint32 TGITLVCR;
  75. volatile Uint8 RSVD1[8];
  76. volatile Uint32 TGINTFLAG;
  77. volatile Uint32 LTGPEND;
  78. volatile Uint32 TGCTRL[4];
  79. volatile Uint8 RSVD2[48];
  80. volatile Uint32 DMACTRL[4];
  81. volatile Uint8 RSVD3[16];
  82. volatile Uint32 DMACOUNT[8];
  83. volatile Uint32 DMA0CNTL;
  84. volatile Uint8 RSVD4[4];
  85. volatile Uint32 UERRCTRL;
  86. volatile Uint32 UERRSTAT;
  87. volatile Uint32 UERRADDR1;
  88. volatile Uint32 UERRADDR0;
  89. volatile Uint32 RXOVRN_BUF_ADDR;
  90. volatile Uint32 IOLPBKTSTCR;
  91. volatile Uint8 RSVD5[196];
  92. volatile Uint32 SPIREV;
  93. } CSL_SpiRegs;
  94. /**************************************************************************
  95. * Register Macros
  96. **************************************************************************/
  97. #define CSL_SPI_SPIGCR0 ((uint32_t)0x0U)
  98. #define CSL_SPI_SPIGCR1 ((uint32_t)0x4U)
  99. #define CSL_SPI_SPIINT0 ((uint32_t)0x8U)
  100. #define CSL_SPI_SPILVL ((uint32_t)0xCU)
  101. #define CSL_SPI_SPIFLG ((uint32_t)0x10U)
  102. #define CSL_SPI_SPIPC0 ((uint32_t)0x14U)
  103. #define CSL_SPI_SPIPC1 ((uint32_t)0x18U)
  104. #define CSL_SPI_SPIPC2 ((uint32_t)0x1CU)
  105. #define CSL_SPI_SPIPC3 ((uint32_t)0x20U)
  106. #define CSL_SPI_SPIPC4 ((uint32_t)0x24U)
  107. #define CSL_SPI_SPIPC5 ((uint32_t)0x28U)
  108. #define CSL_SPI_SPIPC6 ((uint32_t)0x2CU)
  109. #define CSL_SPI_SPIPC7 ((uint32_t)0x30U)
  110. #define CSL_SPI_SPIPC8 ((uint32_t)0x34U)
  111. #define CSL_SPI_SPIDAT0 ((uint32_t)0x38U)
  112. #define CSL_SPI_SPIDAT1 ((uint32_t)0x3CU)
  113. #define CSL_SPI_SPIBUF ((uint32_t)0x40U)
  114. #define CSL_SPI_SPIEMU ((uint32_t)0x44U)
  115. #define CSL_SPI_SPIDELAY ((uint32_t)0x48U)
  116. #define CSL_SPI_SPIDEF ((uint32_t)0x4CU)
  117. #define CSL_SPI_SPIFMT(i) ((uint32_t)0x50U + ((i) * 4U))
  118. #define CSL_SPI_INTVEC(i) ((uint32_t)0x60U + ((i) * 4U))
  119. #define CSL_SPI_SPISRSEL ((uint32_t)0x68U)
  120. #define CSL_SPI_SPIPMCTRL ((uint32_t)0x6CU)
  121. #define CSL_SPI_MIBSPIE ((uint32_t)0x70U)
  122. #define CSL_SPI_TGITENST ((uint32_t)0x74U)
  123. #define CSL_SPI_TGITENCR ((uint32_t)0x78U)
  124. #define CSL_SPI_TGITLVST ((uint32_t)0x80U)
  125. #define CSL_SPI_TGITLVCR ((uint32_t)0x84U)
  126. #define CSL_SPI_TGINTFLAG ((uint32_t)0x90U)
  127. #define CSL_SPI_LTGPEND ((uint32_t)0x94U)
  128. #define CSL_SPI_TGCTRL(i) ((uint32_t)0x98U + ((i) * 4U))
  129. #define CSL_SPI_DMACTRL(i) ((uint32_t)0xD8U + ((i) * 4U))
  130. #define CSL_SPI_DMACOUNT(i) ((uint32_t)0xF8U + ((i) * 4U))
  131. #define CSL_SPI_DMA0CNTL ((uint32_t)0x118U)
  132. #define CSL_SPI_UERRCTRL ((uint32_t)0x120U)
  133. #define CSL_SPI_UERRSTAT ((uint32_t)0x124U)
  134. #define CSL_SPI_UERRADDR1 ((uint32_t)0x128U)
  135. #define CSL_SPI_UERRADDR0 ((uint32_t)0x12CU)
  136. #define CSL_SPI_RXOVRN_BUF_ADDR ((uint32_t)0x130U)
  137. #define CSL_SPI_IOLPBKTSTCR ((uint32_t)0x134U)
  138. #define CSL_SPI_SPIREV ((uint32_t)0x1FCU)
  139. /**************************************************************************
  140. * Field Definition Macros
  141. **************************************************************************/
  142. /* SPIGCR0 */
  143. #define CSL_SPI_SPIGCR0_RESET_MASK ((uint32_t)0x00000001u)
  144. #define CSL_SPI_SPIGCR0_RESET_SHIFT ((uint32_t)0x00000000u)
  145. #define CSL_SPI_SPIGCR0_RESET_RESETVAL ((uint32_t)0x00000000u)
  146. /*----RESET Tokens----*/
  147. #define CSL_SPI_SPIGCR0_RESET_IN_RESET ((uint32_t)0x00000000u)
  148. #define CSL_SPI_SPIGCR0_RESET_OUT_OF_RESET ((uint32_t)0x00000001u)
  149. #define CSL_SPI_SPIGCR0_RESETVAL ((uint32_t)0x00000000u)
  150. /* SPIGCR1 */
  151. #define CSL_SPI_SPIGCR1_ENABLE_MASK ((uint32_t)0x01000000u)
  152. #define CSL_SPI_SPIGCR1_ENABLE_SHIFT ((uint32_t)0x00000018u)
  153. #define CSL_SPI_SPIGCR1_ENABLE_RESETVAL ((uint32_t)0x00000000u)
  154. /*----ENABLE Tokens----*/
  155. #define CSL_SPI_SPIGCR1_ENABLE_DISABLE ((uint32_t)0x00000000u)
  156. #define CSL_SPI_SPIGCR1_ENABLE_ENABLE ((uint32_t)0x00000001u)
  157. #define CSL_SPI_SPIGCR1_LOOPBACK_MASK ((uint32_t)0x00010000u)
  158. #define CSL_SPI_SPIGCR1_LOOPBACK_SHIFT ((uint32_t)0x00000010u)
  159. #define CSL_SPI_SPIGCR1_LOOPBACK_RESETVAL ((uint32_t)0x00000000u)
  160. /*----LOOPBACK Tokens----*/
  161. #define CSL_SPI_SPIGCR1_LOOPBACK_DISABLE ((uint32_t)0x00000000u)
  162. #define CSL_SPI_SPIGCR1_LOOPBACK_ENABLE ((uint32_t)0x00000001u)
  163. #define CSL_SPI_SPIGCR1_POWERDOWN_MASK ((uint32_t)0x00000100u)
  164. #define CSL_SPI_SPIGCR1_POWERDOWN_SHIFT ((uint32_t)0x00000008u)
  165. #define CSL_SPI_SPIGCR1_POWERDOWN_RESETVAL ((uint32_t)0x00000000u)
  166. /*----POWERDOWN Tokens----*/
  167. #define CSL_SPI_SPIGCR1_POWERDOWN_DISABLE ((uint32_t)0x00000000u)
  168. #define CSL_SPI_SPIGCR1_POWERDOWN_ENABLE ((uint32_t)0x00000001u)
  169. #define CSL_SPI_SPIGCR1_CLKMOD_MASK ((uint32_t)0x00000002u)
  170. #define CSL_SPI_SPIGCR1_CLKMOD_SHIFT ((uint32_t)0x00000001u)
  171. #define CSL_SPI_SPIGCR1_CLKMOD_RESETVAL ((uint32_t)0x00000000u)
  172. /*----CLKMOD Tokens----*/
  173. #define CSL_SPI_SPIGCR1_CLKMOD_EXTERNAL ((uint32_t)0x00000000u)
  174. #define CSL_SPI_SPIGCR1_CLKMOD_INTERNAL ((uint32_t)0x00000001u)
  175. #define CSL_SPI_SPIGCR1_MASTER_MASK ((uint32_t)0x00000001u)
  176. #define CSL_SPI_SPIGCR1_MASTER_SHIFT ((uint32_t)0x00000000u)
  177. #define CSL_SPI_SPIGCR1_MASTER_RESETVAL ((uint32_t)0x00000000u)
  178. /*----MASTER Tokens----*/
  179. #define CSL_SPI_SPIGCR1_MASTER_SLAVE ((uint32_t)0x00000000u)
  180. #define CSL_SPI_SPIGCR1_MASTER_MASTER ((uint32_t)0x00000001u)
  181. #define CSL_SPI_SPIGCR1_RESETVAL ((uint32_t)0x00000000u)
  182. /* SPIINT0 */
  183. #define CSL_SPI_SPIINT0_ENABLEHIGHZ_MASK ((uint32_t)0x01000000u)
  184. #define CSL_SPI_SPIINT0_ENABLEHIGHZ_SHIFT ((uint32_t)0x00000018u)
  185. #define CSL_SPI_SPIINT0_ENABLEHIGHZ_RESETVAL ((uint32_t)0x00000000u)
  186. /*----ENABLEHIGHZ Tokens----*/
  187. #define CSL_SPI_SPIINT0_ENABLEHIGHZ_DISABLE ((uint32_t)0x00000000u)
  188. #define CSL_SPI_SPIINT0_ENABLEHIGHZ_ENABLE ((uint32_t)0x00000001u)
  189. #define CSL_SPI_SPIINT0_DMAREQEN_MASK ((uint32_t)0x00010000u)
  190. #define CSL_SPI_SPIINT0_DMAREQEN_SHIFT ((uint32_t)0x00000010u)
  191. #define CSL_SPI_SPIINT0_DMAREQEN_RESETVAL ((uint32_t)0x00000000u)
  192. /*----DMAREQEN Tokens----*/
  193. #define CSL_SPI_SPIINT0_DMAREQEN_DISABLE ((uint32_t)0x00000000u)
  194. #define CSL_SPI_SPIINT0_DMAREQEN_ENABLE ((uint32_t)0x00000001u)
  195. #define CSL_SPI_SPIINT0_TXINTENA_MASK ((uint32_t)0x00000200u)
  196. #define CSL_SPI_SPIINT0_TXINTENA_SHIFT ((uint32_t)0x00000009u)
  197. #define CSL_SPI_SPIINT0_TXINTENA_RESETVAL ((uint32_t)0x00000000u)
  198. /*----TXINTENA Tokens----*/
  199. #define CSL_SPI_SPIINT0_TXINTENA_DISABLE ((uint32_t)0x00000000u)
  200. #define CSL_SPI_SPIINT0_TXINTENA_ENABLE ((uint32_t)0x00000001u)
  201. #define CSL_SPI_SPIINT0_RXINTENA_MASK ((uint32_t)0x00000100u)
  202. #define CSL_SPI_SPIINT0_RXINTENA_SHIFT ((uint32_t)0x00000008u)
  203. #define CSL_SPI_SPIINT0_RXINTENA_RESETVAL ((uint32_t)0x00000000u)
  204. /*----RXINTENA Tokens----*/
  205. #define CSL_SPI_SPIINT0_RXINTENA_DISABLE ((uint32_t)0x00000000u)
  206. #define CSL_SPI_SPIINT0_RXINTENA_ENABLE ((uint32_t)0x00000001u)
  207. #define CSL_SPI_SPIINT0_OVRNINTENA_MASK ((uint32_t)0x00000040u)
  208. #define CSL_SPI_SPIINT0_OVRNINTENA_SHIFT ((uint32_t)0x00000006u)
  209. #define CSL_SPI_SPIINT0_OVRNINTENA_RESETVAL ((uint32_t)0x00000000u)
  210. /*----OVRNINTENA Tokens----*/
  211. #define CSL_SPI_SPIINT0_OVRNINTENA_DISABLE ((uint32_t)0x00000000u)
  212. #define CSL_SPI_SPIINT0_OVRNINTENA_ENABLE ((uint32_t)0x00000001u)
  213. #define CSL_SPI_SPIINT0_BITERRENA_MASK ((uint32_t)0x00000010u)
  214. #define CSL_SPI_SPIINT0_BITERRENA_SHIFT ((uint32_t)0x00000004u)
  215. #define CSL_SPI_SPIINT0_BITERRENA_RESETVAL ((uint32_t)0x00000000u)
  216. /*----BITERRENA Tokens----*/
  217. #define CSL_SPI_SPIINT0_BITERRENA_DISABLE ((uint32_t)0x00000000u)
  218. #define CSL_SPI_SPIINT0_BITERRENA_ENABLE ((uint32_t)0x00000001u)
  219. #define CSL_SPI_SPIINT0_DESYNCENA_MASK ((uint32_t)0x00000008u)
  220. #define CSL_SPI_SPIINT0_DESYNCENA_SHIFT ((uint32_t)0x00000003u)
  221. #define CSL_SPI_SPIINT0_DESYNCENA_RESETVAL ((uint32_t)0x00000000u)
  222. /*----DESYNCENA Tokens----*/
  223. #define CSL_SPI_SPIINT0_DESYNCENA_DISABLE ((uint32_t)0x00000000u)
  224. #define CSL_SPI_SPIINT0_DESYNCENA_ENABLE ((uint32_t)0x00000001u)
  225. #define CSL_SPI_SPIINT0_PARERRENA_MASK ((uint32_t)0x00000004u)
  226. #define CSL_SPI_SPIINT0_PARERRENA_SHIFT ((uint32_t)0x00000002u)
  227. #define CSL_SPI_SPIINT0_PARERRENA_RESETVAL ((uint32_t)0x00000000u)
  228. /*----PARERRENA Tokens----*/
  229. #define CSL_SPI_SPIINT0_PARERRENA_DISABLE ((uint32_t)0x00000000u)
  230. #define CSL_SPI_SPIINT0_PARERRENA_ENABLE ((uint32_t)0x00000001u)
  231. #define CSL_SPI_SPIINT0_TIMEOUTENA_MASK ((uint32_t)0x00000002u)
  232. #define CSL_SPI_SPIINT0_TIMEOUTENA_SHIFT ((uint32_t)0x00000001u)
  233. #define CSL_SPI_SPIINT0_TIMEOUTENA_RESETVAL ((uint32_t)0x00000000u)
  234. /*----TIMEOUTENA Tokens----*/
  235. #define CSL_SPI_SPIINT0_TIMEOUTENA_DISABLE ((uint32_t)0x00000000u)
  236. #define CSL_SPI_SPIINT0_TIMEOUTENA_ENABLE ((uint32_t)0x00000001u)
  237. #define CSL_SPI_SPIINT0_DLENERRENA_MASK ((uint32_t)0x00000001u)
  238. #define CSL_SPI_SPIINT0_DLENERRENA_SHIFT ((uint32_t)0x00000000u)
  239. #define CSL_SPI_SPIINT0_DLENERRENA_RESETVAL ((uint32_t)0x00000000u)
  240. /*----DLENERRENA Tokens----*/
  241. #define CSL_SPI_SPIINT0_DLENERRENA_DISABLE ((uint32_t)0x00000000u)
  242. #define CSL_SPI_SPIINT0_DLENERRENA_ENABLE ((uint32_t)0x00000001u)
  243. #define CSL_SPI_SPIINT0_RESETVAL ((uint32_t)0x00000000u)
  244. /* SPILVL */
  245. #define CSL_SPI_SPILVL_TXINTLVL_MASK ((uint32_t)0x00000200u)
  246. #define CSL_SPI_SPILVL_TXINTLVL_SHIFT ((uint32_t)0x00000009u)
  247. #define CSL_SPI_SPILVL_TXINTLVL_RESETVAL ((uint32_t)0x00000000u)
  248. /*----TXINTLVL Tokens----*/
  249. #define CSL_SPI_SPILVL_TXINTLVL_INT0 ((uint32_t)0x00000000u)
  250. #define CSL_SPI_SPILVL_TXINTLVL_INT1 ((uint32_t)0x00000001u)
  251. #define CSL_SPI_SPILVL_RXINTLVL_MASK ((uint32_t)0x00000100u)
  252. #define CSL_SPI_SPILVL_RXINTLVL_SHIFT ((uint32_t)0x00000008u)
  253. #define CSL_SPI_SPILVL_RXINTLVL_RESETVAL ((uint32_t)0x00000000u)
  254. /*----RXINTLVL Tokens----*/
  255. #define CSL_SPI_SPILVL_RXINTLVL_INT0 ((uint32_t)0x00000000u)
  256. #define CSL_SPI_SPILVL_RXINTLVL_INT1 ((uint32_t)0x00000001u)
  257. #define CSL_SPI_SPILVL_OVRNINTLVL_MASK ((uint32_t)0x00000040u)
  258. #define CSL_SPI_SPILVL_OVRNINTLVL_SHIFT ((uint32_t)0x00000006u)
  259. #define CSL_SPI_SPILVL_OVRNINTLVL_RESETVAL ((uint32_t)0x00000000u)
  260. /*----OVRNINTLVL Tokens----*/
  261. #define CSL_SPI_SPILVL_OVRNINTLVL_INT0 ((uint32_t)0x00000000u)
  262. #define CSL_SPI_SPILVL_OVRNINTLVL_INT1 ((uint32_t)0x00000001u)
  263. #define CSL_SPI_SPILVL_BITERRLVL_MASK ((uint32_t)0x00000010u)
  264. #define CSL_SPI_SPILVL_BITERRLVL_SHIFT ((uint32_t)0x00000004u)
  265. #define CSL_SPI_SPILVL_BITERRLVL_RESETVAL ((uint32_t)0x00000000u)
  266. /*----BITERRLVL Tokens----*/
  267. #define CSL_SPI_SPILVL_BITERRLVL_INT0 ((uint32_t)0x00000000u)
  268. #define CSL_SPI_SPILVL_BITERRLVL_INT1 ((uint32_t)0x00000001u)
  269. #define CSL_SPI_SPILVL_DESYNCLVL_MASK ((uint32_t)0x00000008u)
  270. #define CSL_SPI_SPILVL_DESYNCLVL_SHIFT ((uint32_t)0x00000003u)
  271. #define CSL_SPI_SPILVL_DESYNCLVL_RESETVAL ((uint32_t)0x00000000u)
  272. /*----DESYNCLVL Tokens----*/
  273. #define CSL_SPI_SPILVL_DESYNCLVL_INT0 ((uint32_t)0x00000000u)
  274. #define CSL_SPI_SPILVL_DESYNCLVL_INT1 ((uint32_t)0x00000001u)
  275. #define CSL_SPI_SPILVL_PARERRLVL_MASK ((uint32_t)0x00000004u)
  276. #define CSL_SPI_SPILVL_PARERRLVL_SHIFT ((uint32_t)0x00000002u)
  277. #define CSL_SPI_SPILVL_PARERRLVL_RESETVAL ((uint32_t)0x00000000u)
  278. /*----PARERRLVL Tokens----*/
  279. #define CSL_SPI_SPILVL_PARERRLVL_INT0 ((uint32_t)0x00000000u)
  280. #define CSL_SPI_SPILVL_PARERRLVL_INT1 ((uint32_t)0x00000001u)
  281. #define CSL_SPI_SPILVL_TIMEOUTLVL_MASK ((uint32_t)0x00000002u)
  282. #define CSL_SPI_SPILVL_TIMEOUTLVL_SHIFT ((uint32_t)0x00000001u)
  283. #define CSL_SPI_SPILVL_TIMEOUTLVL_RESETVAL ((uint32_t)0x00000000u)
  284. /*----TIMEOUTLVL Tokens----*/
  285. #define CSL_SPI_SPILVL_TIMEOUTLVL_INT0 ((uint32_t)0x00000000u)
  286. #define CSL_SPI_SPILVL_TIMEOUTLVL_INT1 ((uint32_t)0x00000001u)
  287. #define CSL_SPI_SPILVL_DLENERRLVL_MASK ((uint32_t)0x00000001u)
  288. #define CSL_SPI_SPILVL_DLENERRLVL_SHIFT ((uint32_t)0x00000000u)
  289. #define CSL_SPI_SPILVL_DLENERRLVL_RESETVAL ((uint32_t)0x00000000u)
  290. /*----DLENERRLVL Tokens----*/
  291. #define CSL_SPI_SPILVL_DLENERRLVL_INT0 ((uint32_t)0x00000000u)
  292. #define CSL_SPI_SPILVL_DLENERRLVL_INT1 ((uint32_t)0x00000001u)
  293. #define CSL_SPI_SPILVL_RESETVAL ((uint32_t)0x00000000u)
  294. /* SPIFLG */
  295. #define CSL_SPI_SPIFLG_TXINTFLG_MASK ((uint32_t)0x00000200u)
  296. #define CSL_SPI_SPIFLG_TXINTFLG_SHIFT ((uint32_t)0x00000009u)
  297. #define CSL_SPI_SPIFLG_TXINTFLG_RESETVAL ((uint32_t)0x00000000u)
  298. /*----TXINTFLG Tokens----*/
  299. #define CSL_SPI_SPIFLG_TXINTFLG_NO_EMPTY ((uint32_t)0x00000000u)
  300. #define CSL_SPI_SPIFLG_TXINTFLG_EMPTY ((uint32_t)0x00000001u)
  301. #define CSL_SPI_SPIFLG_RXINTFLG_MASK ((uint32_t)0x00000100u)
  302. #define CSL_SPI_SPIFLG_RXINTFLG_SHIFT ((uint32_t)0x00000008u)
  303. #define CSL_SPI_SPIFLG_RXINTFLG_RESETVAL ((uint32_t)0x00000000u)
  304. /*----RXINTFLG Tokens----*/
  305. #define CSL_SPI_SPIFLG_RXINTFLG_NO_FULL ((uint32_t)0x00000000u)
  306. #define CSL_SPI_SPIFLG_RXINTFLG_FULL ((uint32_t)0x00000001u)
  307. #define CSL_SPI_SPIFLG_OVRNINTFLG_MASK ((uint32_t)0x00000040u)
  308. #define CSL_SPI_SPIFLG_OVRNINTFLG_SHIFT ((uint32_t)0x00000006u)
  309. #define CSL_SPI_SPIFLG_OVRNINTFLG_RESETVAL ((uint32_t)0x00000000u)
  310. /*----OVRNINTFLG Tokens----*/
  311. #define CSL_SPI_SPIFLG_OVRNINTFLG_NO_ERROR ((uint32_t)0x00000000u)
  312. #define CSL_SPI_SPIFLG_OVRNINTFLG_ERROR ((uint32_t)0x00000001u)
  313. #define CSL_SPI_SPIFLG_BITERRFLG_MASK ((uint32_t)0x00000010u)
  314. #define CSL_SPI_SPIFLG_BITERRFLG_SHIFT ((uint32_t)0x00000004u)
  315. #define CSL_SPI_SPIFLG_BITERRFLG_RESETVAL ((uint32_t)0x00000000u)
  316. /*----BITERRFLG Tokens----*/
  317. #define CSL_SPI_SPIFLG_BITERRFLG_NO_ERROR ((uint32_t)0x00000000u)
  318. #define CSL_SPI_SPIFLG_BITERRFLG_ERROR ((uint32_t)0x00000001u)
  319. #define CSL_SPI_SPIFLG_DESYNCFLG_MASK ((uint32_t)0x00000008u)
  320. #define CSL_SPI_SPIFLG_DESYNCFLG_SHIFT ((uint32_t)0x00000003u)
  321. #define CSL_SPI_SPIFLG_DESYNCFLG_RESETVAL ((uint32_t)0x00000000u)
  322. /*----DESYNCFLG Tokens----*/
  323. #define CSL_SPI_SPIFLG_DESYNCFLG_NO_ERROR ((uint32_t)0x00000000u)
  324. #define CSL_SPI_SPIFLG_DESYNCFLG_ERROR ((uint32_t)0x00000001u)
  325. #define CSL_SPI_SPIFLG_PARERRFLG_MASK ((uint32_t)0x00000004u)
  326. #define CSL_SPI_SPIFLG_PARERRFLG_SHIFT ((uint32_t)0x00000002u)
  327. #define CSL_SPI_SPIFLG_PARERRFLG_RESETVAL ((uint32_t)0x00000000u)
  328. /*----PARERRFLG Tokens----*/
  329. #define CSL_SPI_SPIFLG_PARERRFLG_NO_ERROR ((uint32_t)0x00000000u)
  330. #define CSL_SPI_SPIFLG_PARERRFLG_ERROR ((uint32_t)0x00000001u)
  331. #define CSL_SPI_SPIFLG_TIMEOUTFLG_MASK ((uint32_t)0x00000002u)
  332. #define CSL_SPI_SPIFLG_TIMEOUTFLG_SHIFT ((uint32_t)0x00000001u)
  333. #define CSL_SPI_SPIFLG_TIMEOUTFLG_RESETVAL ((uint32_t)0x00000000u)
  334. /*----TIMEOUTFLG Tokens----*/
  335. #define CSL_SPI_SPIFLG_TIMEOUTFLG_NO_ERROR ((uint32_t)0x00000000u)
  336. #define CSL_SPI_SPIFLG_TIMEOUTFLG_ERROR ((uint32_t)0x00000001u)
  337. #define CSL_SPI_SPIFLG_DLENERRFLG_MASK ((uint32_t)0x00000001u)
  338. #define CSL_SPI_SPIFLG_DLENERRFLG_SHIFT ((uint32_t)0x00000000u)
  339. #define CSL_SPI_SPIFLG_DLENERRFLG_RESETVAL ((uint32_t)0x00000000u)
  340. /*----DLENERRFLG Tokens----*/
  341. #define CSL_SPI_SPIFLG_DLENERRFLG_NO_ERROR ((uint32_t)0x00000000u)
  342. #define CSL_SPI_SPIFLG_DLENERRFLG_ERROR ((uint32_t)0x00000001u)
  343. #define CSL_SPI_SPIFLG_RESETVAL ((uint32_t)0x00000000u)
  344. /* SPIPC0 */
  345. #define CSL_SPI_SPIPC0_SOMIFUN_MASK ((uint32_t)0x00000800u)
  346. #define CSL_SPI_SPIPC0_SOMIFUN_SHIFT ((uint32_t)0x0000000Bu)
  347. #define CSL_SPI_SPIPC0_SOMIFUN_RESETVAL ((uint32_t)0x00000000u)
  348. /*----SOMIFUN Tokens----*/
  349. #define CSL_SPI_SPIPC0_SOMIFUN_GPIO ((uint32_t)0x00000000u)
  350. #define CSL_SPI_SPIPC0_SOMIFUN_SPI ((uint32_t)0x00000001u)
  351. #define CSL_SPI_SPIPC0_SIMOFUN_MASK ((uint32_t)0x00000400u)
  352. #define CSL_SPI_SPIPC0_SIMOFUN_SHIFT ((uint32_t)0x0000000Au)
  353. #define CSL_SPI_SPIPC0_SIMOFUN_RESETVAL ((uint32_t)0x00000000u)
  354. /*----SIMOFUN Tokens----*/
  355. #define CSL_SPI_SPIPC0_SIMOFUN_GPIO ((uint32_t)0x00000000u)
  356. #define CSL_SPI_SPIPC0_SIMOFUN_SPI ((uint32_t)0x00000001u)
  357. #define CSL_SPI_SPIPC0_CLKFUN_MASK ((uint32_t)0x00000200u)
  358. #define CSL_SPI_SPIPC0_CLKFUN_SHIFT ((uint32_t)0x00000009u)
  359. #define CSL_SPI_SPIPC0_CLKFUN_RESETVAL ((uint32_t)0x00000000u)
  360. /*----CLKFUN Tokens----*/
  361. #define CSL_SPI_SPIPC0_CLKFUN_GPIO ((uint32_t)0x00000000u)
  362. #define CSL_SPI_SPIPC0_CLKFUN_SPI ((uint32_t)0x00000001u)
  363. #define CSL_SPI_SPIPC0_ENAFUN_MASK ((uint32_t)0x00000100u)
  364. #define CSL_SPI_SPIPC0_ENAFUN_SHIFT ((uint32_t)0x00000008u)
  365. #define CSL_SPI_SPIPC0_ENAFUN_RESETVAL ((uint32_t)0x00000000u)
  366. /*----ENAFUN Tokens----*/
  367. #define CSL_SPI_SPIPC0_ENAFUN_GPIO ((uint32_t)0x00000000u)
  368. #define CSL_SPI_SPIPC0_ENAFUN_SPI ((uint32_t)0x00000001u)
  369. #define CSL_SPI_SPIPC0_SCS0FUN7_MASK ((uint32_t)0x00000080u)
  370. #define CSL_SPI_SPIPC0_SCS0FUN7_SHIFT ((uint32_t)0x00000007u)
  371. #define CSL_SPI_SPIPC0_SCS0FUN7_RESETVAL ((uint32_t)0x00000000u)
  372. /*----SCS0FUN7 Tokens----*/
  373. #define CSL_SPI_SPIPC0_SCS0FUN7_GPIO ((uint32_t)0x00000000u)
  374. #define CSL_SPI_SPIPC0_SCS0FUN7_SPI ((uint32_t)0x00000001u)
  375. #define CSL_SPI_SPIPC0_SCS0FUN6_MASK ((uint32_t)0x00000040u)
  376. #define CSL_SPI_SPIPC0_SCS0FUN6_SHIFT ((uint32_t)0x00000006u)
  377. #define CSL_SPI_SPIPC0_SCS0FUN6_RESETVAL ((uint32_t)0x00000000u)
  378. /*----SCS0FUN6 Tokens----*/
  379. #define CSL_SPI_SPIPC0_SCS0FUN6_GPIO ((uint32_t)0x00000000u)
  380. #define CSL_SPI_SPIPC0_SCS0FUN6_SPI ((uint32_t)0x00000001u)
  381. #define CSL_SPI_SPIPC0_SCS0FUN5_MASK ((uint32_t)0x00000020u)
  382. #define CSL_SPI_SPIPC0_SCS0FUN5_SHIFT ((uint32_t)0x00000005u)
  383. #define CSL_SPI_SPIPC0_SCS0FUN5_RESETVAL ((uint32_t)0x00000000u)
  384. /*----SCS0FUN5 Tokens----*/
  385. #define CSL_SPI_SPIPC0_SCS0FUN5_GPIO ((uint32_t)0x00000000u)
  386. #define CSL_SPI_SPIPC0_SCS0FUN5_SPI ((uint32_t)0x00000001u)
  387. #define CSL_SPI_SPIPC0_SCS0FUN4_MASK ((uint32_t)0x00000010u)
  388. #define CSL_SPI_SPIPC0_SCS0FUN4_SHIFT ((uint32_t)0x00000004u)
  389. #define CSL_SPI_SPIPC0_SCS0FUN4_RESETVAL ((uint32_t)0x00000000u)
  390. /*----SCS0FUN4 Tokens----*/
  391. #define CSL_SPI_SPIPC0_SCS0FUN4_GPIO ((uint32_t)0x00000000u)
  392. #define CSL_SPI_SPIPC0_SCS0FUN4_SPI ((uint32_t)0x00000001u)
  393. #define CSL_SPI_SPIPC0_SCS0FUN3_MASK ((uint32_t)0x00000008u)
  394. #define CSL_SPI_SPIPC0_SCS0FUN3_SHIFT ((uint32_t)0x00000003u)
  395. #define CSL_SPI_SPIPC0_SCS0FUN3_RESETVAL ((uint32_t)0x00000000u)
  396. /*----SCS0FUN3 Tokens----*/
  397. #define CSL_SPI_SPIPC0_SCS0FUN3_GPIO ((uint32_t)0x00000000u)
  398. #define CSL_SPI_SPIPC0_SCS0FUN3_SPI ((uint32_t)0x00000001u)
  399. #define CSL_SPI_SPIPC0_SCS0FUN2_MASK ((uint32_t)0x00000004u)
  400. #define CSL_SPI_SPIPC0_SCS0FUN2_SHIFT ((uint32_t)0x00000002u)
  401. #define CSL_SPI_SPIPC0_SCS0FUN2_RESETVAL ((uint32_t)0x00000000u)
  402. /*----SCS0FUN2 Tokens----*/
  403. #define CSL_SPI_SPIPC0_SCS0FUN2_GPIO ((uint32_t)0x00000000u)
  404. #define CSL_SPI_SPIPC0_SCS0FUN2_SPI ((uint32_t)0x00000001u)
  405. #define CSL_SPI_SPIPC0_SCS0FUN1_MASK ((uint32_t)0x00000002u)
  406. #define CSL_SPI_SPIPC0_SCS0FUN1_SHIFT ((uint32_t)0x00000001u)
  407. #define CSL_SPI_SPIPC0_SCS0FUN1_RESETVAL ((uint32_t)0x00000000u)
  408. /*----SCS0FUN1 Tokens----*/
  409. #define CSL_SPI_SPIPC0_SCS0FUN1_GPIO ((uint32_t)0x00000000u)
  410. #define CSL_SPI_SPIPC0_SCS0FUN1_SPI ((uint32_t)0x00000001u)
  411. #define CSL_SPI_SPIPC0_SCS0FUN0_MASK ((uint32_t)0x00000001u)
  412. #define CSL_SPI_SPIPC0_SCS0FUN0_SHIFT ((uint32_t)0x00000000u)
  413. #define CSL_SPI_SPIPC0_SCS0FUN0_RESETVAL ((uint32_t)0x00000000u)
  414. /*----SCS0FUN0 Tokens----*/
  415. #define CSL_SPI_SPIPC0_SCS0FUN0_GPIO ((uint32_t)0x00000000u)
  416. #define CSL_SPI_SPIPC0_SCS0FUN0_SPI ((uint32_t)0x00000001u)
  417. #define CSL_SPI_SPIPC0_RESETVAL ((uint32_t)0x00000000u)
  418. /* SPIPC1 */
  419. #define CSL_SPI_SPIPC1_SOMIDIR_MASK ((uint32_t)0x00000800u)
  420. #define CSL_SPI_SPIPC1_SOMIDIR_SHIFT ((uint32_t)0x0000000Bu)
  421. #define CSL_SPI_SPIPC1_SOMIDIR_RESETVAL ((uint32_t)0x00000000u)
  422. /*----SOMIDIR Tokens----*/
  423. #define CSL_SPI_SPIPC1_SOMIDIR_INPUT ((uint32_t)0x00000000u)
  424. #define CSL_SPI_SPIPC1_SOMIDIR_OUTPUT ((uint32_t)0x00000001u)
  425. #define CSL_SPI_SPIPC1_SIMODIR_MASK ((uint32_t)0x00000400u)
  426. #define CSL_SPI_SPIPC1_SIMODIR_SHIFT ((uint32_t)0x0000000Au)
  427. #define CSL_SPI_SPIPC1_SIMODIR_RESETVAL ((uint32_t)0x00000000u)
  428. /*----SIMODIR Tokens----*/
  429. #define CSL_SPI_SPIPC1_SIMODIR_INPUT ((uint32_t)0x00000000u)
  430. #define CSL_SPI_SPIPC1_SIMODIR_OUTPUT ((uint32_t)0x00000001u)
  431. #define CSL_SPI_SPIPC1_CLKDIR_MASK ((uint32_t)0x00000200u)
  432. #define CSL_SPI_SPIPC1_CLKDIR_SHIFT ((uint32_t)0x00000009u)
  433. #define CSL_SPI_SPIPC1_CLKDIR_RESETVAL ((uint32_t)0x00000000u)
  434. /*----CLKDIR Tokens----*/
  435. #define CSL_SPI_SPIPC1_CLKDIR_INPUT ((uint32_t)0x00000000u)
  436. #define CSL_SPI_SPIPC1_CLKDIR_OUTPUT ((uint32_t)0x00000001u)
  437. #define CSL_SPI_SPIPC1_ENADIR_MASK ((uint32_t)0x00000100u)
  438. #define CSL_SPI_SPIPC1_ENADIR_SHIFT ((uint32_t)0x00000008u)
  439. #define CSL_SPI_SPIPC1_ENADIR_RESETVAL ((uint32_t)0x00000000u)
  440. /*----ENADIR Tokens----*/
  441. #define CSL_SPI_SPIPC1_ENADIR_INPUT ((uint32_t)0x00000000u)
  442. #define CSL_SPI_SPIPC1_ENADIR_OUTPUT ((uint32_t)0x00000001u)
  443. #define CSL_SPI_SPIPC1_SCS0DIR7_MASK ((uint32_t)0x00000080u)
  444. #define CSL_SPI_SPIPC1_SCS0DIR7_SHIFT ((uint32_t)0x00000007u)
  445. #define CSL_SPI_SPIPC1_SCS0DIR7_RESETVAL ((uint32_t)0x00000000u)
  446. /*----SCS0DIR7 Tokens----*/
  447. #define CSL_SPI_SPIPC1_SCS0DIR7_INPUT ((uint32_t)0x00000000u)
  448. #define CSL_SPI_SPIPC1_SCS0DIR7_OUTPUT ((uint32_t)0x00000001u)
  449. #define CSL_SPI_SPIPC1_SCS0DIR6_MASK ((uint32_t)0x00000040u)
  450. #define CSL_SPI_SPIPC1_SCS0DIR6_SHIFT ((uint32_t)0x00000006u)
  451. #define CSL_SPI_SPIPC1_SCS0DIR6_RESETVAL ((uint32_t)0x00000000u)
  452. /*----SCS0DIR6 Tokens----*/
  453. #define CSL_SPI_SPIPC1_SCS0DIR6_INPUT ((uint32_t)0x00000000u)
  454. #define CSL_SPI_SPIPC1_SCS0DIR6_OUTPUT ((uint32_t)0x00000001u)
  455. #define CSL_SPI_SPIPC1_SCS0DIR5_MASK ((uint32_t)0x00000020u)
  456. #define CSL_SPI_SPIPC1_SCS0DIR5_SHIFT ((uint32_t)0x00000005u)
  457. #define CSL_SPI_SPIPC1_SCS0DIR5_RESETVAL ((uint32_t)0x00000000u)
  458. /*----SCS0DIR5 Tokens----*/
  459. #define CSL_SPI_SPIPC1_SCS0DIR5_INPUT ((uint32_t)0x00000000u)
  460. #define CSL_SPI_SPIPC1_SCS0DIR5_OUTPUT ((uint32_t)0x00000001u)
  461. #define CSL_SPI_SPIPC1_SCS0DIR4_MASK ((uint32_t)0x00000010u)
  462. #define CSL_SPI_SPIPC1_SCS0DIR4_SHIFT ((uint32_t)0x00000004u)
  463. #define CSL_SPI_SPIPC1_SCS0DIR4_RESETVAL ((uint32_t)0x00000000u)
  464. /*----SCS0DIR4 Tokens----*/
  465. #define CSL_SPI_SPIPC1_SCS0DIR4_INPUT ((uint32_t)0x00000000u)
  466. #define CSL_SPI_SPIPC1_SCS0DIR4_OUTPUT ((uint32_t)0x00000001u)
  467. #define CSL_SPI_SPIPC1_SCS0DIR3_MASK ((uint32_t)0x00000008u)
  468. #define CSL_SPI_SPIPC1_SCS0DIR3_SHIFT ((uint32_t)0x00000003u)
  469. #define CSL_SPI_SPIPC1_SCS0DIR3_RESETVAL ((uint32_t)0x00000000u)
  470. /*----SCS0DIR3 Tokens----*/
  471. #define CSL_SPI_SPIPC1_SCS0DIR3_INPUT ((uint32_t)0x00000000u)
  472. #define CSL_SPI_SPIPC1_SCS0DIR3_OUTPUT ((uint32_t)0x00000001u)
  473. #define CSL_SPI_SPIPC1_SCS0DIR2_MASK ((uint32_t)0x00000004u)
  474. #define CSL_SPI_SPIPC1_SCS0DIR2_SHIFT ((uint32_t)0x00000002u)
  475. #define CSL_SPI_SPIPC1_SCS0DIR2_RESETVAL ((uint32_t)0x00000000u)
  476. /*----SCS0DIR2 Tokens----*/
  477. #define CSL_SPI_SPIPC1_SCS0DIR2_INPUT ((uint32_t)0x00000000u)
  478. #define CSL_SPI_SPIPC1_SCS0DIR2_OUTPUT ((uint32_t)0x00000001u)
  479. #define CSL_SPI_SPIPC1_SCS0DIR1_MASK ((uint32_t)0x00000002u)
  480. #define CSL_SPI_SPIPC1_SCS0DIR1_SHIFT ((uint32_t)0x00000001u)
  481. #define CSL_SPI_SPIPC1_SCS0DIR1_RESETVAL ((uint32_t)0x00000000u)
  482. /*----SCS0DIR1 Tokens----*/
  483. #define CSL_SPI_SPIPC1_SCS0DIR1_INPUT ((uint32_t)0x00000000u)
  484. #define CSL_SPI_SPIPC1_SCS0DIR1_OUTPUT ((uint32_t)0x00000001u)
  485. #define CSL_SPI_SPIPC1_SCS0DIR0_MASK ((uint32_t)0x00000001u)
  486. #define CSL_SPI_SPIPC1_SCS0DIR0_SHIFT ((uint32_t)0x00000000u)
  487. #define CSL_SPI_SPIPC1_SCS0DIR0_RESETVAL ((uint32_t)0x00000000u)
  488. /*----SCS0DIR0 Tokens----*/
  489. #define CSL_SPI_SPIPC1_SCS0DIR0_INPUT ((uint32_t)0x00000000u)
  490. #define CSL_SPI_SPIPC1_SCS0DIR0_OUTPUT ((uint32_t)0x00000001u)
  491. #define CSL_SPI_SPIPC1_RESETVAL ((uint32_t)0x00000000u)
  492. /* SPIPC2 */
  493. #define CSL_SPI_SPIPC2_SOMIDIN_MASK ((uint32_t)0x00000800u)
  494. #define CSL_SPI_SPIPC2_SOMIDIN_SHIFT ((uint32_t)0x0000000Bu)
  495. #define CSL_SPI_SPIPC2_SOMIDIN_RESETVAL ((uint32_t)0x00000000u)
  496. /*----SOMIDIN Tokens----*/
  497. #define CSL_SPI_SPIPC2_SOMIDIN_LOW ((uint32_t)0x00000000u)
  498. #define CSL_SPI_SPIPC2_SOMIDIN_HIGH ((uint32_t)0x00000001u)
  499. #define CSL_SPI_SPIPC2_SIMODIN_MASK ((uint32_t)0x00000400u)
  500. #define CSL_SPI_SPIPC2_SIMODIN_SHIFT ((uint32_t)0x0000000Au)
  501. #define CSL_SPI_SPIPC2_SIMODIN_RESETVAL ((uint32_t)0x00000000u)
  502. /*----SIMODIN Tokens----*/
  503. #define CSL_SPI_SPIPC2_SIMODIN_LOW ((uint32_t)0x00000000u)
  504. #define CSL_SPI_SPIPC2_SIMODIN_HIGH ((uint32_t)0x00000001u)
  505. #define CSL_SPI_SPIPC2_CLKDIN_MASK ((uint32_t)0x00000200u)
  506. #define CSL_SPI_SPIPC2_CLKDIN_SHIFT ((uint32_t)0x00000009u)
  507. #define CSL_SPI_SPIPC2_CLKDIN_RESETVAL ((uint32_t)0x00000000u)
  508. /*----CLKDIN Tokens----*/
  509. #define CSL_SPI_SPIPC2_CLKDIN_LOW ((uint32_t)0x00000000u)
  510. #define CSL_SPI_SPIPC2_CLKDIN_HIGH ((uint32_t)0x00000001u)
  511. #define CSL_SPI_SPIPC2_ENADIN_MASK ((uint32_t)0x00000100u)
  512. #define CSL_SPI_SPIPC2_ENADIN_SHIFT ((uint32_t)0x00000008u)
  513. #define CSL_SPI_SPIPC2_ENADIN_RESETVAL ((uint32_t)0x00000000u)
  514. /*----ENADIN Tokens----*/
  515. #define CSL_SPI_SPIPC2_ENADIN_LOW ((uint32_t)0x00000000u)
  516. #define CSL_SPI_SPIPC2_ENADIN_HIGH ((uint32_t)0x00000001u)
  517. #define CSL_SPI_SPIPC2_SCS0DIN7_MASK ((uint32_t)0x00000080u)
  518. #define CSL_SPI_SPIPC2_SCS0DIN7_SHIFT ((uint32_t)0x00000007u)
  519. #define CSL_SPI_SPIPC2_SCS0DIN7_RESETVAL ((uint32_t)0x00000000u)
  520. /*----SCS0DIN7 Tokens----*/
  521. #define CSL_SPI_SPIPC2_SCS0DIN7_LOW ((uint32_t)0x00000000u)
  522. #define CSL_SPI_SPIPC2_SCS0DIN7_HIGH ((uint32_t)0x00000001u)
  523. #define CSL_SPI_SPIPC2_SCS0DIN6_MASK ((uint32_t)0x00000040u)
  524. #define CSL_SPI_SPIPC2_SCS0DIN6_SHIFT ((uint32_t)0x00000006u)
  525. #define CSL_SPI_SPIPC2_SCS0DIN6_RESETVAL ((uint32_t)0x00000000u)
  526. /*----SCS0DIN6 Tokens----*/
  527. #define CSL_SPI_SPIPC2_SCS0DIN6_LOW ((uint32_t)0x00000000u)
  528. #define CSL_SPI_SPIPC2_SCS0DIN6_HIGH ((uint32_t)0x00000001u)
  529. #define CSL_SPI_SPIPC2_SCS0DIN5_MASK ((uint32_t)0x00000020u)
  530. #define CSL_SPI_SPIPC2_SCS0DIN5_SHIFT ((uint32_t)0x00000005u)
  531. #define CSL_SPI_SPIPC2_SCS0DIN5_RESETVAL ((uint32_t)0x00000000u)
  532. /*----SCS0DIN5 Tokens----*/
  533. #define CSL_SPI_SPIPC2_SCS0DIN5_LOW ((uint32_t)0x00000000u)
  534. #define CSL_SPI_SPIPC2_SCS0DIN5_HIGH ((uint32_t)0x00000001u)
  535. #define CSL_SPI_SPIPC2_SCS0DIN4_MASK ((uint32_t)0x00000010u)
  536. #define CSL_SPI_SPIPC2_SCS0DIN4_SHIFT ((uint32_t)0x00000004u)
  537. #define CSL_SPI_SPIPC2_SCS0DIN4_RESETVAL ((uint32_t)0x00000000u)
  538. /*----SCS0DIN4 Tokens----*/
  539. #define CSL_SPI_SPIPC2_SCS0DIN4_LOW ((uint32_t)0x00000000u)
  540. #define CSL_SPI_SPIPC2_SCS0DIN4_HIGH ((uint32_t)0x00000001u)
  541. #define CSL_SPI_SPIPC2_SCS0DIN3_MASK ((uint32_t)0x00000008u)
  542. #define CSL_SPI_SPIPC2_SCS0DIN3_SHIFT ((uint32_t)0x00000003u)
  543. #define CSL_SPI_SPIPC2_SCS0DIN3_RESETVAL ((uint32_t)0x00000000u)
  544. /*----SCS0DIN3 Tokens----*/
  545. #define CSL_SPI_SPIPC2_SCS0DIN3_LOW ((uint32_t)0x00000000u)
  546. #define CSL_SPI_SPIPC2_SCS0DIN3_HIGH ((uint32_t)0x00000001u)
  547. #define CSL_SPI_SPIPC2_SCS0DIN2_MASK ((uint32_t)0x00000004u)
  548. #define CSL_SPI_SPIPC2_SCS0DIN2_SHIFT ((uint32_t)0x00000002u)
  549. #define CSL_SPI_SPIPC2_SCS0DIN2_RESETVAL ((uint32_t)0x00000000u)
  550. /*----SCS0DIN2 Tokens----*/
  551. #define CSL_SPI_SPIPC2_SCS0DIN2_LOW ((uint32_t)0x00000000u)
  552. #define CSL_SPI_SPIPC2_SCS0DIN2_HIGH ((uint32_t)0x00000001u)
  553. #define CSL_SPI_SPIPC2_SCS0DIN1_MASK ((uint32_t)0x00000002u)
  554. #define CSL_SPI_SPIPC2_SCS0DIN1_SHIFT ((uint32_t)0x00000001u)
  555. #define CSL_SPI_SPIPC2_SCS0DIN1_RESETVAL ((uint32_t)0x00000000u)
  556. /*----SCS0DIN1 Tokens----*/
  557. #define CSL_SPI_SPIPC2_SCS0DIN1_LOW ((uint32_t)0x00000000u)
  558. #define CSL_SPI_SPIPC2_SCS0DIN1_HIGH ((uint32_t)0x00000001u)
  559. #define CSL_SPI_SPIPC2_SCS0DIN0_MASK ((uint32_t)0x00000001u)
  560. #define CSL_SPI_SPIPC2_SCS0DIN0_SHIFT ((uint32_t)0x00000000u)
  561. #define CSL_SPI_SPIPC2_SCS0DIN0_RESETVAL ((uint32_t)0x00000000u)
  562. /*----SCS0DIN0 Tokens----*/
  563. #define CSL_SPI_SPIPC2_SCS0DIN0_LOW ((uint32_t)0x00000000u)
  564. #define CSL_SPI_SPIPC2_SCS0DIN0_HIGH ((uint32_t)0x00000001u)
  565. #define CSL_SPI_SPIPC2_RESETVAL ((uint32_t)0x00000000u)
  566. /* SPIPC3 */
  567. #define CSL_SPI_SPIPC3_SOMIDOUT_MASK ((uint32_t)0x00000800u)
  568. #define CSL_SPI_SPIPC3_SOMIDOUT_SHIFT ((uint32_t)0x0000000Bu)
  569. #define CSL_SPI_SPIPC3_SOMIDOUT_RESETVAL ((uint32_t)0x00000000u)
  570. /*----SOMIDOUT Tokens----*/
  571. #define CSL_SPI_SPIPC3_SOMIDOUT_LOW ((uint32_t)0x00000000u)
  572. #define CSL_SPI_SPIPC3_SOMIDOUT_HIGH ((uint32_t)0x00000001u)
  573. #define CSL_SPI_SPIPC3_SIMODOUT_MASK ((uint32_t)0x00000400u)
  574. #define CSL_SPI_SPIPC3_SIMODOUT_SHIFT ((uint32_t)0x0000000Au)
  575. #define CSL_SPI_SPIPC3_SIMODOUT_RESETVAL ((uint32_t)0x00000000u)
  576. /*----SIMODOUT Tokens----*/
  577. #define CSL_SPI_SPIPC3_SIMODOUT_LOW ((uint32_t)0x00000000u)
  578. #define CSL_SPI_SPIPC3_SIMODOUT_HIGH ((uint32_t)0x00000001u)
  579. #define CSL_SPI_SPIPC3_CLKDOUT_MASK ((uint32_t)0x00000200u)
  580. #define CSL_SPI_SPIPC3_CLKDOUT_SHIFT ((uint32_t)0x00000009u)
  581. #define CSL_SPI_SPIPC3_CLKDOUT_RESETVAL ((uint32_t)0x00000000u)
  582. /*----CLKDOUT Tokens----*/
  583. #define CSL_SPI_SPIPC3_CLKDOUT_LOW ((uint32_t)0x00000000u)
  584. #define CSL_SPI_SPIPC3_CLKDOUT_HIGH ((uint32_t)0x00000001u)
  585. #define CSL_SPI_SPIPC3_ENADOUT_MASK ((uint32_t)0x00000100u)
  586. #define CSL_SPI_SPIPC3_ENADOUT_SHIFT ((uint32_t)0x00000008u)
  587. #define CSL_SPI_SPIPC3_ENADOUT_RESETVAL ((uint32_t)0x00000000u)
  588. /*----ENADOUT Tokens----*/
  589. #define CSL_SPI_SPIPC3_ENADOUT_LOW ((uint32_t)0x00000000u)
  590. #define CSL_SPI_SPIPC3_ENADOUT_HIGH ((uint32_t)0x00000001u)
  591. #define CSL_SPI_SPIPC3_SCS0DOUT7_MASK ((uint32_t)0x00000080u)
  592. #define CSL_SPI_SPIPC3_SCS0DOUT7_SHIFT ((uint32_t)0x00000007u)
  593. #define CSL_SPI_SPIPC3_SCS0DOUT7_RESETVAL ((uint32_t)0x00000000u)
  594. /*----SCS0DOUT7 Tokens----*/
  595. #define CSL_SPI_SPIPC3_SCS0DOUT7_LOW ((uint32_t)0x00000000u)
  596. #define CSL_SPI_SPIPC3_SCS0DOUT7_HIGH ((uint32_t)0x00000001u)
  597. #define CSL_SPI_SPIPC3_SCS0DOUT6_MASK ((uint32_t)0x00000040u)
  598. #define CSL_SPI_SPIPC3_SCS0DOUT6_SHIFT ((uint32_t)0x00000006u)
  599. #define CSL_SPI_SPIPC3_SCS0DOUT6_RESETVAL ((uint32_t)0x00000000u)
  600. /*----SCS0DOUT6 Tokens----*/
  601. #define CSL_SPI_SPIPC3_SCS0DOUT6_LOW ((uint32_t)0x00000000u)
  602. #define CSL_SPI_SPIPC3_SCS0DOUT6_HIGH ((uint32_t)0x00000001u)
  603. #define CSL_SPI_SPIPC3_SCS0DOUT5_MASK ((uint32_t)0x00000020u)
  604. #define CSL_SPI_SPIPC3_SCS0DOUT5_SHIFT ((uint32_t)0x00000005u)
  605. #define CSL_SPI_SPIPC3_SCS0DOUT5_RESETVAL ((uint32_t)0x00000000u)
  606. /*----SCS0DOUT5 Tokens----*/
  607. #define CSL_SPI_SPIPC3_SCS0DOUT5_LOW ((uint32_t)0x00000000u)
  608. #define CSL_SPI_SPIPC3_SCS0DOUT5_HIGH ((uint32_t)0x00000001u)
  609. #define CSL_SPI_SPIPC3_SCS0DOUT4_MASK ((uint32_t)0x00000010u)
  610. #define CSL_SPI_SPIPC3_SCS0DOUT4_SHIFT ((uint32_t)0x00000004u)
  611. #define CSL_SPI_SPIPC3_SCS0DOUT4_RESETVAL ((uint32_t)0x00000000u)
  612. /*----SCS0DOUT4 Tokens----*/
  613. #define CSL_SPI_SPIPC3_SCS0DOUT4_LOW ((uint32_t)0x00000000u)
  614. #define CSL_SPI_SPIPC3_SCS0DOUT4_HIGH ((uint32_t)0x00000001u)
  615. #define CSL_SPI_SPIPC3_SCS0DOUT3_MASK ((uint32_t)0x00000008u)
  616. #define CSL_SPI_SPIPC3_SCS0DOUT3_SHIFT ((uint32_t)0x00000003u)
  617. #define CSL_SPI_SPIPC3_SCS0DOUT3_RESETVAL ((uint32_t)0x00000000u)
  618. /*----SCS0DOUT3 Tokens----*/
  619. #define CSL_SPI_SPIPC3_SCS0DOUT3_LOW ((uint32_t)0x00000000u)
  620. #define CSL_SPI_SPIPC3_SCS0DOUT3_HIGH ((uint32_t)0x00000001u)
  621. #define CSL_SPI_SPIPC3_SCS0DOUT2_MASK ((uint32_t)0x00000004u)
  622. #define CSL_SPI_SPIPC3_SCS0DOUT2_SHIFT ((uint32_t)0x00000002u)
  623. #define CSL_SPI_SPIPC3_SCS0DOUT2_RESETVAL ((uint32_t)0x00000000u)
  624. /*----SCS0DOUT2 Tokens----*/
  625. #define CSL_SPI_SPIPC3_SCS0DOUT2_LOW ((uint32_t)0x00000000u)
  626. #define CSL_SPI_SPIPC3_SCS0DOUT2_HIGH ((uint32_t)0x00000001u)
  627. #define CSL_SPI_SPIPC3_SCS0DOUT1_MASK ((uint32_t)0x00000002u)
  628. #define CSL_SPI_SPIPC3_SCS0DOUT1_SHIFT ((uint32_t)0x00000001u)
  629. #define CSL_SPI_SPIPC3_SCS0DOUT1_RESETVAL ((uint32_t)0x00000000u)
  630. /*----SCS0DOUT1 Tokens----*/
  631. #define CSL_SPI_SPIPC3_SCS0DOUT1_LOW ((uint32_t)0x00000000u)
  632. #define CSL_SPI_SPIPC3_SCS0DOUT1_HIGH ((uint32_t)0x00000001u)
  633. #define CSL_SPI_SPIPC3_SCS0DOUT0_MASK ((uint32_t)0x00000001u)
  634. #define CSL_SPI_SPIPC3_SCS0DOUT0_SHIFT ((uint32_t)0x00000000u)
  635. #define CSL_SPI_SPIPC3_SCS0DOUT0_RESETVAL ((uint32_t)0x00000000u)
  636. /*----SCS0DOUT0 Tokens----*/
  637. #define CSL_SPI_SPIPC3_SCS0DOUT0_LOW ((uint32_t)0x00000000u)
  638. #define CSL_SPI_SPIPC3_SCS0DOUT0_HIGH ((uint32_t)0x00000001u)
  639. #define CSL_SPI_SPIPC3_RESETVAL ((uint32_t)0x00000000u)
  640. /* SPIPC4 */
  641. #define CSL_SPI_SPIPC4_SOMISET_MASK ((uint32_t)0x00000800u)
  642. #define CSL_SPI_SPIPC4_SOMISET_SHIFT ((uint32_t)0x0000000Bu)
  643. #define CSL_SPI_SPIPC4_SOMISET_RESETVAL ((uint32_t)0x00000000u)
  644. /*----SOMISET Tokens----*/
  645. #define CSL_SPI_SPIPC4_SOMISET_NO_EFFECT ((uint32_t)0x00000000u)
  646. #define CSL_SPI_SPIPC4_SOMISET_SET ((uint32_t)0x00000001u)
  647. #define CSL_SPI_SPIPC4_SIMOSET_MASK ((uint32_t)0x00000400u)
  648. #define CSL_SPI_SPIPC4_SIMOSET_SHIFT ((uint32_t)0x0000000Au)
  649. #define CSL_SPI_SPIPC4_SIMOSET_RESETVAL ((uint32_t)0x00000000u)
  650. /*----SIMOSET Tokens----*/
  651. #define CSL_SPI_SPIPC4_SIMOSET_NO_EFFECT ((uint32_t)0x00000000u)
  652. #define CSL_SPI_SPIPC4_SIMOSET_SET ((uint32_t)0x00000001u)
  653. #define CSL_SPI_SPIPC4_CLKSET_MASK ((uint32_t)0x00000200u)
  654. #define CSL_SPI_SPIPC4_CLKSET_SHIFT ((uint32_t)0x00000009u)
  655. #define CSL_SPI_SPIPC4_CLKSET_RESETVAL ((uint32_t)0x00000000u)
  656. /*----CLKSET Tokens----*/
  657. #define CSL_SPI_SPIPC4_CLKSET_NO_EFFECT ((uint32_t)0x00000000u)
  658. #define CSL_SPI_SPIPC4_CLKSET_SET ((uint32_t)0x00000001u)
  659. #define CSL_SPI_SPIPC4_ENASET_MASK ((uint32_t)0x00000100u)
  660. #define CSL_SPI_SPIPC4_ENASET_SHIFT ((uint32_t)0x00000008u)
  661. #define CSL_SPI_SPIPC4_ENASET_RESETVAL ((uint32_t)0x00000000u)
  662. /*----ENASET Tokens----*/
  663. #define CSL_SPI_SPIPC4_ENASET_NO_EFFECT ((uint32_t)0x00000000u)
  664. #define CSL_SPI_SPIPC4_ENASET_SET ((uint32_t)0x00000001u)
  665. #define CSL_SPI_SPIPC4_SCS0SET7_MASK ((uint32_t)0x00000080u)
  666. #define CSL_SPI_SPIPC4_SCS0SET7_SHIFT ((uint32_t)0x00000007u)
  667. #define CSL_SPI_SPIPC4_SCS0SET7_RESETVAL ((uint32_t)0x00000000u)
  668. /*----SCS0SET7 Tokens----*/
  669. #define CSL_SPI_SPIPC4_SCS0SET7_NO_EFFECT ((uint32_t)0x00000000u)
  670. #define CSL_SPI_SPIPC4_SCS0SET7_SET ((uint32_t)0x00000001u)
  671. #define CSL_SPI_SPIPC4_SCS0SET6_MASK ((uint32_t)0x00000040u)
  672. #define CSL_SPI_SPIPC4_SCS0SET6_SHIFT ((uint32_t)0x00000006u)
  673. #define CSL_SPI_SPIPC4_SCS0SET6_RESETVAL ((uint32_t)0x00000000u)
  674. /*----SCS0SET6 Tokens----*/
  675. #define CSL_SPI_SPIPC4_SCS0SET6_NO_EFFECT ((uint32_t)0x00000000u)
  676. #define CSL_SPI_SPIPC4_SCS0SET6_SET ((uint32_t)0x00000001u)
  677. #define CSL_SPI_SPIPC4_SCS0SET5_MASK ((uint32_t)0x00000020u)
  678. #define CSL_SPI_SPIPC4_SCS0SET5_SHIFT ((uint32_t)0x00000005u)
  679. #define CSL_SPI_SPIPC4_SCS0SET5_RESETVAL ((uint32_t)0x00000000u)
  680. /*----SCS0SET5 Tokens----*/
  681. #define CSL_SPI_SPIPC4_SCS0SET5_NO_EFFECT ((uint32_t)0x00000000u)
  682. #define CSL_SPI_SPIPC4_SCS0SET5_SET ((uint32_t)0x00000001u)
  683. #define CSL_SPI_SPIPC4_SCS0SET4_MASK ((uint32_t)0x00000010u)
  684. #define CSL_SPI_SPIPC4_SCS0SET4_SHIFT ((uint32_t)0x00000004u)
  685. #define CSL_SPI_SPIPC4_SCS0SET4_RESETVAL ((uint32_t)0x00000000u)
  686. /*----SCS0SET4 Tokens----*/
  687. #define CSL_SPI_SPIPC4_SCS0SET4_NO_EFFECT ((uint32_t)0x00000000u)
  688. #define CSL_SPI_SPIPC4_SCS0SET4_SET ((uint32_t)0x00000001u)
  689. #define CSL_SPI_SPIPC4_SCS0SET3_MASK ((uint32_t)0x00000008u)
  690. #define CSL_SPI_SPIPC4_SCS0SET3_SHIFT ((uint32_t)0x00000003u)
  691. #define CSL_SPI_SPIPC4_SCS0SET3_RESETVAL ((uint32_t)0x00000000u)
  692. /*----SCS0SET3 Tokens----*/
  693. #define CSL_SPI_SPIPC4_SCS0SET3_NO_EFFECT ((uint32_t)0x00000000u)
  694. #define CSL_SPI_SPIPC4_SCS0SET3_SET ((uint32_t)0x00000001u)
  695. #define CSL_SPI_SPIPC4_SCS0SET2_MASK ((uint32_t)0x00000004u)
  696. #define CSL_SPI_SPIPC4_SCS0SET2_SHIFT ((uint32_t)0x00000002u)
  697. #define CSL_SPI_SPIPC4_SCS0SET2_RESETVAL ((uint32_t)0x00000000u)
  698. /*----SCS0SET2 Tokens----*/
  699. #define CSL_SPI_SPIPC4_SCS0SET2_NO_EFFECT ((uint32_t)0x00000000u)
  700. #define CSL_SPI_SPIPC4_SCS0SET2_SET ((uint32_t)0x00000001u)
  701. #define CSL_SPI_SPIPC4_SCS0SET1_MASK ((uint32_t)0x00000002u)
  702. #define CSL_SPI_SPIPC4_SCS0SET1_SHIFT ((uint32_t)0x00000001u)
  703. #define CSL_SPI_SPIPC4_SCS0SET1_RESETVAL ((uint32_t)0x00000000u)
  704. /*----SCS0SET1 Tokens----*/
  705. #define CSL_SPI_SPIPC4_SCS0SET1_NO_EFFECT ((uint32_t)0x00000000u)
  706. #define CSL_SPI_SPIPC4_SCS0SET1_SET ((uint32_t)0x00000001u)
  707. #define CSL_SPI_SPIPC4_SCS0SET0_MASK ((uint32_t)0x00000001u)
  708. #define CSL_SPI_SPIPC4_SCS0SET0_SHIFT ((uint32_t)0x00000000u)
  709. #define CSL_SPI_SPIPC4_SCS0SET0_RESETVAL ((uint32_t)0x00000000u)
  710. /*----SCS0SET0 Tokens----*/
  711. #define CSL_SPI_SPIPC4_SCS0SET0_NO_EFFECT ((uint32_t)0x00000000u)
  712. #define CSL_SPI_SPIPC4_SCS0SET0_SET ((uint32_t)0x00000001u)
  713. #define CSL_SPI_SPIPC4_RESETVAL ((uint32_t)0x00000000u)
  714. /* SPIPC5 */
  715. #define CSL_SPI_SPIPC5_SOMICLR_MASK ((uint32_t)0x00000800u)
  716. #define CSL_SPI_SPIPC5_SOMICLR_SHIFT ((uint32_t)0x0000000Bu)
  717. #define CSL_SPI_SPIPC5_SOMICLR_RESETVAL ((uint32_t)0x00000000u)
  718. /*----SOMICLR Tokens----*/
  719. #define CSL_SPI_SPIPC5_SOMICLR_NO_EFFECT ((uint32_t)0x00000000u)
  720. #define CSL_SPI_SPIPC5_SOMICLR_CLEAR ((uint32_t)0x00000001u)
  721. #define CSL_SPI_SPIPC5_SIMOCLR_MASK ((uint32_t)0x00000400u)
  722. #define CSL_SPI_SPIPC5_SIMOCLR_SHIFT ((uint32_t)0x0000000Au)
  723. #define CSL_SPI_SPIPC5_SIMOCLR_RESETVAL ((uint32_t)0x00000000u)
  724. /*----SIMOCLR Tokens----*/
  725. #define CSL_SPI_SPIPC5_SIMOCLR_NO_EFFECT ((uint32_t)0x00000000u)
  726. #define CSL_SPI_SPIPC5_SIMOCLR_CLEAR ((uint32_t)0x00000001u)
  727. #define CSL_SPI_SPIPC5_CLKCLR_MASK ((uint32_t)0x00000200u)
  728. #define CSL_SPI_SPIPC5_CLKCLR_SHIFT ((uint32_t)0x00000009u)
  729. #define CSL_SPI_SPIPC5_CLKCLR_RESETVAL ((uint32_t)0x00000000u)
  730. /*----CLKCLR Tokens----*/
  731. #define CSL_SPI_SPIPC5_CLKCLR_NO_EFFECT ((uint32_t)0x00000000u)
  732. #define CSL_SPI_SPIPC5_CLKCLR_CLEAR ((uint32_t)0x00000001u)
  733. #define CSL_SPI_SPIPC5_ENACLR_MASK ((uint32_t)0x00000100u)
  734. #define CSL_SPI_SPIPC5_ENACLR_SHIFT ((uint32_t)0x00000008u)
  735. #define CSL_SPI_SPIPC5_ENACLR_RESETVAL ((uint32_t)0x00000000u)
  736. /*----ENACLR Tokens----*/
  737. #define CSL_SPI_SPIPC5_ENACLR_NO_EFFECT ((uint32_t)0x00000000u)
  738. #define CSL_SPI_SPIPC5_ENACLR_CLEAR ((uint32_t)0x00000001u)
  739. #define CSL_SPI_SPIPC5_SCS0CLR7_MASK ((uint32_t)0x00000080u)
  740. #define CSL_SPI_SPIPC5_SCS0CLR7_SHIFT ((uint32_t)0x00000007u)
  741. #define CSL_SPI_SPIPC5_SCS0CLR7_RESETVAL ((uint32_t)0x00000000u)
  742. /*----SCS0CLR7 Tokens----*/
  743. #define CSL_SPI_SPIPC5_SCS0CLR7_NO_EFFECT ((uint32_t)0x00000000u)
  744. #define CSL_SPI_SPIPC5_SCS0CLR7_CLEAR ((uint32_t)0x00000001u)
  745. #define CSL_SPI_SPIPC5_SCS0CLR6_MASK ((uint32_t)0x00000040u)
  746. #define CSL_SPI_SPIPC5_SCS0CLR6_SHIFT ((uint32_t)0x00000006u)
  747. #define CSL_SPI_SPIPC5_SCS0CLR6_RESETVAL ((uint32_t)0x00000000u)
  748. /*----SCS0CLR6 Tokens----*/
  749. #define CSL_SPI_SPIPC5_SCS0CLR6_NO_EFFECT ((uint32_t)0x00000000u)
  750. #define CSL_SPI_SPIPC5_SCS0CLR6_CLEAR ((uint32_t)0x00000001u)
  751. #define CSL_SPI_SPIPC5_SCS0CLR5_MASK ((uint32_t)0x00000020u)
  752. #define CSL_SPI_SPIPC5_SCS0CLR5_SHIFT ((uint32_t)0x00000005u)
  753. #define CSL_SPI_SPIPC5_SCS0CLR5_RESETVAL ((uint32_t)0x00000000u)
  754. /*----SCS0CLR5 Tokens----*/
  755. #define CSL_SPI_SPIPC5_SCS0CLR5_NO_EFFECT ((uint32_t)0x00000000u)
  756. #define CSL_SPI_SPIPC5_SCS0CLR5_CLEAR ((uint32_t)0x00000001u)
  757. #define CSL_SPI_SPIPC5_SCS0CLR4_MASK ((uint32_t)0x00000010u)
  758. #define CSL_SPI_SPIPC5_SCS0CLR4_SHIFT ((uint32_t)0x00000004u)
  759. #define CSL_SPI_SPIPC5_SCS0CLR4_RESETVAL ((uint32_t)0x00000000u)
  760. /*----SCS0CLR4 Tokens----*/
  761. #define CSL_SPI_SPIPC5_SCS0CLR4_NO_EFFECT ((uint32_t)0x00000000u)
  762. #define CSL_SPI_SPIPC5_SCS0CLR4_CLEAR ((uint32_t)0x00000001u)
  763. #define CSL_SPI_SPIPC5_SCS0CLR3_MASK ((uint32_t)0x00000008u)
  764. #define CSL_SPI_SPIPC5_SCS0CLR3_SHIFT ((uint32_t)0x00000003u)
  765. #define CSL_SPI_SPIPC5_SCS0CLR3_RESETVAL ((uint32_t)0x00000000u)
  766. /*----SCS0CLR3 Tokens----*/
  767. #define CSL_SPI_SPIPC5_SCS0CLR3_NO_EFFECT ((uint32_t)0x00000000u)
  768. #define CSL_SPI_SPIPC5_SCS0CLR3_CLEAR ((uint32_t)0x00000001u)
  769. #define CSL_SPI_SPIPC5_SCS0CLR2_MASK ((uint32_t)0x00000004u)
  770. #define CSL_SPI_SPIPC5_SCS0CLR2_SHIFT ((uint32_t)0x00000002u)
  771. #define CSL_SPI_SPIPC5_SCS0CLR2_RESETVAL ((uint32_t)0x00000000u)
  772. /*----SCS0CLR2 Tokens----*/
  773. #define CSL_SPI_SPIPC5_SCS0CLR2_NO_EFFECT ((uint32_t)0x00000000u)
  774. #define CSL_SPI_SPIPC5_SCS0CLR2_CLEAR ((uint32_t)0x00000001u)
  775. #define CSL_SPI_SPIPC5_SCS0CLR1_MASK ((uint32_t)0x00000002u)
  776. #define CSL_SPI_SPIPC5_SCS0CLR1_SHIFT ((uint32_t)0x00000001u)
  777. #define CSL_SPI_SPIPC5_SCS0CLR1_RESETVAL ((uint32_t)0x00000000u)
  778. /*----SCS0CLR1 Tokens----*/
  779. #define CSL_SPI_SPIPC5_SCS0CLR1_NO_EFFECT ((uint32_t)0x00000000u)
  780. #define CSL_SPI_SPIPC5_SCS0CLR1_CLEAR ((uint32_t)0x00000001u)
  781. #define CSL_SPI_SPIPC5_SCS0CLR0_MASK ((uint32_t)0x00000001u)
  782. #define CSL_SPI_SPIPC5_SCS0CLR0_SHIFT ((uint32_t)0x00000000u)
  783. #define CSL_SPI_SPIPC5_SCS0CLR0_RESETVAL ((uint32_t)0x00000000u)
  784. /*----SCS0CLR0 Tokens----*/
  785. #define CSL_SPI_SPIPC5_SCS0CLR0_NO_EFFECT ((uint32_t)0x00000000u)
  786. #define CSL_SPI_SPIPC5_SCS0CLR0_CLEAR ((uint32_t)0x00000001u)
  787. #define CSL_SPI_SPIPC5_RESETVAL ((uint32_t)0x00000000u)
  788. /* SPIDAT0 */
  789. #define CSL_SPI_SPIDAT0_TXDATA_MASK ((uint32_t)0x0000FFFFu)
  790. #define CSL_SPI_SPIDAT0_TXDATA_SHIFT ((uint32_t)0x00000000u)
  791. #define CSL_SPI_SPIDAT0_TXDATA_RESETVAL ((uint32_t)0x00000000u)
  792. #define CSL_SPI_SPIDAT0_RESETVAL ((uint32_t)0x00000000u)
  793. /* SPIDAT1 */
  794. #define CSL_SPI_SPIDAT1_CSHOLD_MASK ((uint32_t)0x10000000u)
  795. #define CSL_SPI_SPIDAT1_CSHOLD_SHIFT ((uint32_t)0x0000001Cu)
  796. #define CSL_SPI_SPIDAT1_CSHOLD_RESETVAL ((uint32_t)0x00000000u)
  797. /*----CSHOLD Tokens----*/
  798. #define CSL_SPI_SPIDAT1_CSHOLD_DISABLE ((uint32_t)0x00000000u)
  799. #define CSL_SPI_SPIDAT1_CSHOLD_ENABLE ((uint32_t)0x00000001u)
  800. #define CSL_SPI_SPIDAT1_WDEL_MASK ((uint32_t)0x04000000u)
  801. #define CSL_SPI_SPIDAT1_WDEL_SHIFT ((uint32_t)0x0000001Au)
  802. #define CSL_SPI_SPIDAT1_WDEL_RESETVAL ((uint32_t)0x00000000u)
  803. /*----WDEL Tokens----*/
  804. #define CSL_SPI_SPIDAT1_WDEL_DISABLE ((uint32_t)0x00000000u)
  805. #define CSL_SPI_SPIDAT1_WDEL_ENABLE ((uint32_t)0x00000001u)
  806. #define CSL_SPI_SPIDAT1_DFSEL_MASK ((uint32_t)0x03000000u)
  807. #define CSL_SPI_SPIDAT1_DFSEL_SHIFT ((uint32_t)0x00000018u)
  808. #define CSL_SPI_SPIDAT1_DFSEL_RESETVAL ((uint32_t)0x00000000u)
  809. /*----DFSEL Tokens----*/
  810. #define CSL_SPI_SPIDAT1_DFSEL_FORMAT0 ((uint32_t)0x00000000u)
  811. #define CSL_SPI_SPIDAT1_DFSEL_FORMAT1 ((uint32_t)0x00000001u)
  812. #define CSL_SPI_SPIDAT1_DFSEL_FORMAT2 ((uint32_t)0x00000002u)
  813. #define CSL_SPI_SPIDAT1_DFSEL_FORMAT3 ((uint32_t)0x00000003u)
  814. #define CSL_SPI_SPIDAT1_CSNR_MASK ((uint32_t)0x00FF0000u)
  815. #define CSL_SPI_SPIDAT1_CSNR_SHIFT ((uint32_t)0x00000010u)
  816. #define CSL_SPI_SPIDAT1_CSNR_RESETVAL ((uint32_t)0x00000000u)
  817. #define CSL_SPI_SPIDAT1_TXDATA_MASK ((uint32_t)0x0000FFFFu)
  818. #define CSL_SPI_SPIDAT1_TXDATA_SHIFT ((uint32_t)0x00000000u)
  819. #define CSL_SPI_SPIDAT1_TXDATA_RESETVAL ((uint32_t)0x00000000u)
  820. #define CSL_SPI_SPIDAT1_RESETVAL ((uint32_t)0x00000000u)
  821. /* SPIBUF */
  822. #define CSL_SPI_SPIBUF_RXEMPTY_MASK ((uint32_t)0x80000000u)
  823. #define CSL_SPI_SPIBUF_RXEMPTY_SHIFT ((uint32_t)0x0000001Fu)
  824. #define CSL_SPI_SPIBUF_RXEMPTY_RESETVAL ((uint32_t)0x00000001u)
  825. /*----RXEMPTY Tokens----*/
  826. #define CSL_SPI_SPIBUF_RXEMPTY_NO_EMPTY ((uint32_t)0x00000000u)
  827. #define CSL_SPI_SPIBUF_RXEMPTY_EMPTY ((uint32_t)0x00000001u)
  828. #define CSL_SPI_SPIBUF_RXOVR_MASK ((uint32_t)0x40000000u)
  829. #define CSL_SPI_SPIBUF_RXOVR_SHIFT ((uint32_t)0x0000001Eu)
  830. #define CSL_SPI_SPIBUF_RXOVR_RESETVAL ((uint32_t)0x00000000u)
  831. /*----RXOVR Tokens----*/
  832. #define CSL_SPI_SPIBUF_RXOVR_NO_ERROR ((uint32_t)0x00000000u)
  833. #define CSL_SPI_SPIBUF_RXOVR_ERROR ((uint32_t)0x00000001u)
  834. #define CSL_SPI_SPIBUF_TXFULL_MASK ((uint32_t)0x20000000u)
  835. #define CSL_SPI_SPIBUF_TXFULL_SHIFT ((uint32_t)0x0000001Du)
  836. #define CSL_SPI_SPIBUF_TXFULL_RESETVAL ((uint32_t)0x00000000u)
  837. /*----TXFULL Tokens----*/
  838. #define CSL_SPI_SPIBUF_TXFULL_NO_FULL ((uint32_t)0x00000000u)
  839. #define CSL_SPI_SPIBUF_TXFULL_FULL ((uint32_t)0x00000001u)
  840. #define CSL_SPI_SPIBUF_BITERR_MASK ((uint32_t)0x10000000u)
  841. #define CSL_SPI_SPIBUF_BITERR_SHIFT ((uint32_t)0x0000001Cu)
  842. #define CSL_SPI_SPIBUF_BITERR_RESETVAL ((uint32_t)0x00000000u)
  843. /*----BITERR Tokens----*/
  844. #define CSL_SPI_SPIBUF_BITERR_NO_ERROR ((uint32_t)0x00000000u)
  845. #define CSL_SPI_SPIBUF_BITERR_ERROR ((uint32_t)0x00000001u)
  846. #define CSL_SPI_SPIBUF_DESYNC_MASK ((uint32_t)0x08000000u)
  847. #define CSL_SPI_SPIBUF_DESYNC_SHIFT ((uint32_t)0x0000001Bu)
  848. #define CSL_SPI_SPIBUF_DESYNC_RESETVAL ((uint32_t)0x00000000u)
  849. /*----DESYNC Tokens----*/
  850. #define CSL_SPI_SPIBUF_DESYNC_NO_ERROR ((uint32_t)0x00000000u)
  851. #define CSL_SPI_SPIBUF_DESYNC_ERROR ((uint32_t)0x00000001u)
  852. #define CSL_SPI_SPIBUF_PARERR_MASK ((uint32_t)0x04000000u)
  853. #define CSL_SPI_SPIBUF_PARERR_SHIFT ((uint32_t)0x0000001Au)
  854. #define CSL_SPI_SPIBUF_PARERR_RESETVAL ((uint32_t)0x00000000u)
  855. /*----PARERR Tokens----*/
  856. #define CSL_SPI_SPIBUF_PARERR_NO_ERROR ((uint32_t)0x00000000u)
  857. #define CSL_SPI_SPIBUF_PARERR_ERROR ((uint32_t)0x00000001u)
  858. #define CSL_SPI_SPIBUF_TIMEOUT_MASK ((uint32_t)0x02000000u)
  859. #define CSL_SPI_SPIBUF_TIMEOUT_SHIFT ((uint32_t)0x00000019u)
  860. #define CSL_SPI_SPIBUF_TIMEOUT_RESETVAL ((uint32_t)0x00000000u)
  861. /*----TIMEOUT Tokens----*/
  862. #define CSL_SPI_SPIBUF_TIMEOUT_NO_ERROR ((uint32_t)0x00000000u)
  863. #define CSL_SPI_SPIBUF_TIMEOUT_ERROR ((uint32_t)0x00000001u)
  864. #define CSL_SPI_SPIBUF_DLENERR_MASK ((uint32_t)0x01000000u)
  865. #define CSL_SPI_SPIBUF_DLENERR_SHIFT ((uint32_t)0x00000018u)
  866. #define CSL_SPI_SPIBUF_DLENERR_RESETVAL ((uint32_t)0x00000000u)
  867. /*----DLENERR Tokens----*/
  868. #define CSL_SPI_SPIBUF_DLENERR_NO_ERROR ((uint32_t)0x00000000u)
  869. #define CSL_SPI_SPIBUF_DLENERR_ERROR ((uint32_t)0x00000001u)
  870. #define CSL_SPI_SPIBUF_RXDATA_MASK ((uint32_t)0x0000FFFFu)
  871. #define CSL_SPI_SPIBUF_RXDATA_SHIFT ((uint32_t)0x00000000u)
  872. #define CSL_SPI_SPIBUF_RXDATA_RESETVAL ((uint32_t)0x00000000u)
  873. #define CSL_SPI_SPIBUF_RESETVAL ((uint32_t)0x80000000u)
  874. /* SPIEMU */
  875. #define CSL_SPI_SPIEMU_RXDATA_MASK ((uint32_t)0x0000FFFFu)
  876. #define CSL_SPI_SPIEMU_RXDATA_SHIFT ((uint32_t)0x00000000u)
  877. #define CSL_SPI_SPIEMU_RXDATA_RESETVAL ((uint32_t)0x00000000u)
  878. #define CSL_SPI_SPIEMU_RESETVAL ((uint32_t)0x00000000u)
  879. /* SPIDELAY */
  880. #define CSL_SPI_SPIDELAY_C2TDELAY_MASK ((uint32_t)0xFF000000u)
  881. #define CSL_SPI_SPIDELAY_C2TDELAY_SHIFT ((uint32_t)0x00000018u)
  882. #define CSL_SPI_SPIDELAY_C2TDELAY_RESETVAL ((uint32_t)0x00000000u)
  883. #define CSL_SPI_SPIDELAY_T2CDELAY_MASK ((uint32_t)0x00FF0000u)
  884. #define CSL_SPI_SPIDELAY_T2CDELAY_SHIFT ((uint32_t)0x00000010u)
  885. #define CSL_SPI_SPIDELAY_T2CDELAY_RESETVAL ((uint32_t)0x00000000u)
  886. #define CSL_SPI_SPIDELAY_T2EDELAY_MASK ((uint32_t)0x0000FF00u)
  887. #define CSL_SPI_SPIDELAY_T2EDELAY_SHIFT ((uint32_t)0x00000008u)
  888. #define CSL_SPI_SPIDELAY_T2EDELAY_RESETVAL ((uint32_t)0x00000000u)
  889. #define CSL_SPI_SPIDELAY_C2EDELAY_MASK ((uint32_t)0x000000FFu)
  890. #define CSL_SPI_SPIDELAY_C2EDELAY_SHIFT ((uint32_t)0x00000000u)
  891. #define CSL_SPI_SPIDELAY_C2EDELAY_RESETVAL ((uint32_t)0x00000000u)
  892. #define CSL_SPI_SPIDELAY_RESETVAL ((uint32_t)0x00000000u)
  893. /* SPIDEF */
  894. #define CSL_SPI_SPIDEF_CSDEF0_MASK ((uint32_t)0x00000001u)
  895. #define CSL_SPI_SPIDEF_CSDEF0_SHIFT ((uint32_t)0x00000000u)
  896. #define CSL_SPI_SPIDEF_CSDEF0_RESETVAL ((uint32_t)0x00000001u)
  897. /*----CSDEF0 Tokens----*/
  898. #define CSL_SPI_SPIDEF_CSDEF0_LOW ((uint32_t)0x00000000u)
  899. #define CSL_SPI_SPIDEF_CSDEF0_HIGH ((uint32_t)0x00000001u)
  900. #define CSL_SPI_SPIDEF_RESETVAL ((uint32_t)0x00000001u)
  901. /* SPIFMT */
  902. #define CSL_SPI_SPIFMT_WDELAY_MASK ((uint32_t)0x3F000000u)
  903. #define CSL_SPI_SPIFMT_WDELAY_SHIFT ((uint32_t)0x00000018u)
  904. #define CSL_SPI_SPIFMT_WDELAY_RESETVAL ((uint32_t)0x00000000u)
  905. #define CSL_SPI_SPIFMT_PARPOL_MASK ((uint32_t)0x00800000u)
  906. #define CSL_SPI_SPIFMT_PARPOL_SHIFT ((uint32_t)0x00000017u)
  907. #define CSL_SPI_SPIFMT_PARPOL_RESETVAL ((uint32_t)0x00000000u)
  908. /*----PARPOL Tokens----*/
  909. #define CSL_SPI_SPIFMT_PARPOL_EVEN ((uint32_t)0x00000000u)
  910. #define CSL_SPI_SPIFMT_PARPOL_ODD ((uint32_t)0x00000001u)
  911. #define CSL_SPI_SPIFMT_PARENA_MASK ((uint32_t)0x00400000u)
  912. #define CSL_SPI_SPIFMT_PARENA_SHIFT ((uint32_t)0x00000016u)
  913. #define CSL_SPI_SPIFMT_PARENA_RESETVAL ((uint32_t)0x00000000u)
  914. /*----PARENA Tokens----*/
  915. #define CSL_SPI_SPIFMT_PARENA_DISABLE ((uint32_t)0x00000000u)
  916. #define CSL_SPI_SPIFMT_PARENA_ENABLE ((uint32_t)0x00000001u)
  917. #define CSL_SPI_SPIFMT_WAITENA_MASK ((uint32_t)0x00200000u)
  918. #define CSL_SPI_SPIFMT_WAITENA_SHIFT ((uint32_t)0x00000015u)
  919. #define CSL_SPI_SPIFMT_WAITENA_RESETVAL ((uint32_t)0x00000000u)
  920. /*----WAITENA Tokens----*/
  921. #define CSL_SPI_SPIFMT_WAITENA_DISABLE ((uint32_t)0x00000000u)
  922. #define CSL_SPI_SPIFMT_WAITENA_ENABLE ((uint32_t)0x00000001u)
  923. #define CSL_SPI_SPIFMT_SHIFTDIR_MASK ((uint32_t)0x00100000u)
  924. #define CSL_SPI_SPIFMT_SHIFTDIR_SHIFT ((uint32_t)0x00000014u)
  925. #define CSL_SPI_SPIFMT_SHIFTDIR_RESETVAL ((uint32_t)0x00000000u)
  926. /*----SHIFTDIR Tokens----*/
  927. #define CSL_SPI_SPIFMT_SHIFTDIR_MSB ((uint32_t)0x00000000u)
  928. #define CSL_SPI_SPIFMT_SHIFTDIR_LSB ((uint32_t)0x00000001u)
  929. #define CSL_SPI_SPIFMT_DISCSTIMERS_MASK ((uint32_t)0x00040000u)
  930. #define CSL_SPI_SPIFMT_DISCSTIMERS_SHIFT ((uint32_t)0x00000012u)
  931. #define CSL_SPI_SPIFMT_DISCSTIMERS_RESETVAL ((uint32_t)0x00000000u)
  932. /*----DISCSTIMERS Tokens----*/
  933. #define CSL_SPI_SPIFMT_DISCSTIMERS_DISABLE ((uint32_t)0x00000000u)
  934. #define CSL_SPI_SPIFMT_DISCSTIMERS_ENABLE ((uint32_t)0x00000001u)
  935. #define CSL_SPI_SPIFMT_POLARITY_MASK ((uint32_t)0x00020000u)
  936. #define CSL_SPI_SPIFMT_POLARITY_SHIFT ((uint32_t)0x00000011u)
  937. #define CSL_SPI_SPIFMT_POLARITY_RESETVAL ((uint32_t)0x00000000u)
  938. /*----POLARITY Tokens----*/
  939. #define CSL_SPI_SPIFMT_POLARITY_LOW ((uint32_t)0x00000000u)
  940. #define CSL_SPI_SPIFMT_POLARITY_HIGH ((uint32_t)0x00000001u)
  941. #define CSL_SPI_SPIFMT_PHASE_MASK ((uint32_t)0x00010000u)
  942. #define CSL_SPI_SPIFMT_PHASE_SHIFT ((uint32_t)0x00000010u)
  943. #define CSL_SPI_SPIFMT_PHASE_RESETVAL ((uint32_t)0x00000000u)
  944. /*----PHASE Tokens----*/
  945. #define CSL_SPI_SPIFMT_PHASE_NO_DELAY ((uint32_t)0x00000000u)
  946. #define CSL_SPI_SPIFMT_PHASE_DELAY ((uint32_t)0x00000001u)
  947. #define CSL_SPI_SPIFMT_PRESCALE_MASK ((uint32_t)0x0000FF00u)
  948. #define CSL_SPI_SPIFMT_PRESCALE_SHIFT ((uint32_t)0x00000008u)
  949. #define CSL_SPI_SPIFMT_PRESCALE_RESETVAL ((uint32_t)0x00000000u)
  950. #define CSL_SPI_SPIFMT_CHARLEN_MASK ((uint32_t)0x0000001Fu)
  951. #define CSL_SPI_SPIFMT_CHARLEN_SHIFT ((uint32_t)0x00000000u)
  952. #define CSL_SPI_SPIFMT_CHARLEN_RESETVAL ((uint32_t)0x00000000u)
  953. #define CSL_SPI_SPIFMT_RESETVAL ((uint32_t)0x00000000u)
  954. /* INTVEC */
  955. #define CSL_SPI_INTVEC_INTVECT_MASK ((uint32_t)0x0000003Eu)
  956. #define CSL_SPI_INTVEC_INTVECT_SHIFT ((uint32_t)0x00000001u)
  957. #define CSL_SPI_INTVEC_INTVECT_RESETVAL ((uint32_t)0x00000000u)
  958. #define CSL_SPI_INTVEC_RESETVAL ((uint32_t)0x00000000u)
  959. /* SPISRSEL */
  960. #define CSL_SPI_SPISRSEL_SCS9PSRS_SHIFT ((uint32_t)0u)
  961. #define CSL_SPI_SPISRSEL_SCS9PSRS_MASK ((uint32_t)0x000000FFu)
  962. #define CSL_SPI_SPISRSEL_SCS9PSRS_RESETVAL ((uint32_t)0x00000000u)
  963. #define CSL_SPI_SPISRSEL_SCS9PSRS_MAX ((uint32_t)0x000000ffu)
  964. #define CSL_SPI_SPISRSEL_ENAPSRS_SHIFT ((uint32_t)8u)
  965. #define CSL_SPI_SPISRSEL_ENAPSRS_MASK ((uint32_t)0x00000100u)
  966. #define CSL_SPI_SPISRSEL_ENAPSRS_RESETVAL ((uint32_t)0x00000000u)
  967. #define CSL_SPI_SPISRSEL_ENAPSRS_MAX ((uint32_t)0x00000001u)
  968. #define CSL_SPI_SPISRSEL_CLKPSRS_SHIFT ((uint32_t)9u)
  969. #define CSL_SPI_SPISRSEL_CLKPSRS_MASK ((uint32_t)0x00000200u)
  970. #define CSL_SPI_SPISRSEL_CLKPSRS_RESETVAL ((uint32_t)0x00000000u)
  971. #define CSL_SPI_SPISRSEL_CLKPSRS_MAX ((uint32_t)0x00000001u)
  972. #define CSL_SPI_SPISRSEL_SOMIPSRS_SHIFT ((uint32_t)10u)
  973. #define CSL_SPI_SPISRSEL_SOMIPSRS_MASK ((uint32_t)0x00000400u)
  974. #define CSL_SPI_SPISRSEL_SOMIPSRS_RESETVAL ((uint32_t)0x00000000u)
  975. #define CSL_SPI_SPISRSEL_SOMIPSRS_MAX ((uint32_t)0x00000001u)
  976. #define CSL_SPI_SPISRSEL_SOMOPSRS_SHIFT ((uint32_t)11u)
  977. #define CSL_SPI_SPISRSEL_SOMOPSRS_MASK ((uint32_t)0x00000800u)
  978. #define CSL_SPI_SPISRSEL_SOMOPSRS_RESETVAL ((uint32_t)0x00000000u)
  979. #define CSL_SPI_SPISRSEL_SOMOPSRS_MAX ((uint32_t)0x00000001u)
  980. #define CSL_SPI_SPISRSEL_SOMO9PSRS_SHIFT ((uint32_t)16u)
  981. #define CSL_SPI_SPISRSEL_SOMO9PSRS_MASK ((uint32_t)0x00FF0000u)
  982. #define CSL_SPI_SPISRSEL_SOMO9PSRS_RESETVAL ((uint32_t)0x00000000u)
  983. #define CSL_SPI_SPISRSEL_SOMO9PSRS_MAX ((uint32_t)0x000000ffu)
  984. #define CSL_SPI_SPISRSEL_SOMI9PSRS_SHIFT ((uint32_t)24u)
  985. #define CSL_SPI_SPISRSEL_SOMI9PSRS_MASK ((uint32_t)0xFF000000u)
  986. #define CSL_SPI_SPISRSEL_SOMI9PSRS_RESETVAL ((uint32_t)0x00000000u)
  987. #define CSL_SPI_SPISRSEL_SOMI9PSRS_MAX ((uint32_t)0x000000ffu)
  988. #define CSL_SPI_SPISRSEL_RESETVAL ((uint32_t)0x00000000u)
  989. /* SPIPMCTRL */
  990. #define CSL_SPI_SPIPMCTRL_PMODE0_SHIFT ((uint32_t)0u)
  991. #define CSL_SPI_SPIPMCTRL_PMODE0_MASK ((uint32_t)0x00000003u)
  992. #define CSL_SPI_SPIPMCTRL_PMODE0_RESETVAL ((uint32_t)0x00000000u)
  993. #define CSL_SPI_SPIPMCTRL_PMODE0_MAX ((uint32_t)0x00000003u)
  994. #define CSL_SPI_SPIPMCTRL_MMODE0_SHIFT ((uint32_t)2u)
  995. #define CSL_SPI_SPIPMCTRL_MMODE0_MASK ((uint32_t)0x0000001Cu)
  996. #define CSL_SPI_SPIPMCTRL_MMODE0_RESETVAL ((uint32_t)0x00000000u)
  997. #define CSL_SPI_SPIPMCTRL_MMODE0_MAX ((uint32_t)0x00000007u)
  998. #define CSL_SPI_SPIPMCTRL_MODECLKPOL0_SHIFT ((uint32_t)5u)
  999. #define CSL_SPI_SPIPMCTRL_MODECLKPOL0_MASK ((uint32_t)0x00000020u)
  1000. #define CSL_SPI_SPIPMCTRL_MODECLKPOL0_RESETVAL ((uint32_t)0x00000000u)
  1001. #define CSL_SPI_SPIPMCTRL_MODECLKPOL0_MAX ((uint32_t)0x00000001u)
  1002. #define CSL_SPI_SPIPMCTRL_PMODE1_SHIFT ((uint32_t)8u)
  1003. #define CSL_SPI_SPIPMCTRL_PMODE1_MASK ((uint32_t)0x00000300u)
  1004. #define CSL_SPI_SPIPMCTRL_PMODE1_RESETVAL ((uint32_t)0x00000000u)
  1005. #define CSL_SPI_SPIPMCTRL_PMODE1_MAX ((uint32_t)0x00000003u)
  1006. #define CSL_SPI_SPIPMCTRL_MMODE1_SHIFT ((uint32_t)10u)
  1007. #define CSL_SPI_SPIPMCTRL_MMODE1_MASK ((uint32_t)0x00001C00u)
  1008. #define CSL_SPI_SPIPMCTRL_MMODE1_RESETVAL ((uint32_t)0x00000000u)
  1009. #define CSL_SPI_SPIPMCTRL_MMODE1_MAX ((uint32_t)0x00000007u)
  1010. #define CSL_SPI_SPIPMCTRL_MODECLKPOL1_SHIFT ((uint32_t)13u)
  1011. #define CSL_SPI_SPIPMCTRL_MODECLKPOL1_MASK ((uint32_t)0x00002000u)
  1012. #define CSL_SPI_SPIPMCTRL_MODECLKPOL1_RESETVAL ((uint32_t)0x00000000u)
  1013. #define CSL_SPI_SPIPMCTRL_MODECLKPOL1_MAX ((uint32_t)0x00000001u)
  1014. #define CSL_SPI_SPIPMCTRL_PMODE2_SHIFT ((uint32_t)16u)
  1015. #define CSL_SPI_SPIPMCTRL_PMODE2_MASK ((uint32_t)0x00030000u)
  1016. #define CSL_SPI_SPIPMCTRL_PMODE2_RESETVAL ((uint32_t)0x00000000u)
  1017. #define CSL_SPI_SPIPMCTRL_PMODE2_MAX ((uint32_t)0x00000003u)
  1018. #define CSL_SPI_SPIPMCTRL_MMODE2_SHIFT ((uint32_t)18u)
  1019. #define CSL_SPI_SPIPMCTRL_MMODE2_MASK ((uint32_t)0x001C0000u)
  1020. #define CSL_SPI_SPIPMCTRL_MMODE2_RESETVAL ((uint32_t)0x00000000u)
  1021. #define CSL_SPI_SPIPMCTRL_MMODE2_MAX ((uint32_t)0x00000007u)
  1022. #define CSL_SPI_SPIPMCTRL_MODECLKPOL2_SHIFT ((uint32_t)21u)
  1023. #define CSL_SPI_SPIPMCTRL_MODECLKPOL2_MASK ((uint32_t)0x00200000u)
  1024. #define CSL_SPI_SPIPMCTRL_MODECLKPOL2_RESETVAL ((uint32_t)0x00000000u)
  1025. #define CSL_SPI_SPIPMCTRL_MODECLKPOL2_MAX ((uint32_t)0x00000001u)
  1026. #define CSL_SPI_SPIPMCTRL_PMODE3_SHIFT ((uint32_t)24u)
  1027. #define CSL_SPI_SPIPMCTRL_PMODE3_MASK ((uint32_t)0x03000000u)
  1028. #define CSL_SPI_SPIPMCTRL_PMODE3_RESETVAL ((uint32_t)0x00000000u)
  1029. #define CSL_SPI_SPIPMCTRL_PMODE3_MAX ((uint32_t)0x00000003u)
  1030. #define CSL_SPI_SPIPMCTRL_MMODE3_SHIFT ((uint32_t)26u)
  1031. #define CSL_SPI_SPIPMCTRL_MMODE3_MASK ((uint32_t)0x1C000000u)
  1032. #define CSL_SPI_SPIPMCTRL_MMODE3_RESETVAL ((uint32_t)0x00000000u)
  1033. #define CSL_SPI_SPIPMCTRL_MMODE3_MAX ((uint32_t)0x00000007u)
  1034. #define CSL_SPI_SPIPMCTRL_MODECLKPOL3_SHIFT ((uint32_t)29u)
  1035. #define CSL_SPI_SPIPMCTRL_MODECLKPOL3_MASK ((uint32_t)0x20000000u)
  1036. #define CSL_SPI_SPIPMCTRL_MODECLKPOL3_RESETVAL ((uint32_t)0x00000000u)
  1037. #define CSL_SPI_SPIPMCTRL_MODECLKPOL3_MAX ((uint32_t)0x00000001u)
  1038. #define CSL_SPI_SPIPMCTRL_RESETVAL ((uint32_t)0x00000000u)
  1039. /* MIBSPIE */
  1040. #define CSL_SPI_MIBSPIE_MSPIENA_SHIFT ((uint32_t)0u)
  1041. #define CSL_SPI_MIBSPIE_MSPIENA_MASK ((uint32_t)0x00000001u)
  1042. #define CSL_SPI_MIBSPIE_MSPIENA_RESETVAL ((uint32_t)0x00000000u)
  1043. #define CSL_SPI_MIBSPIE_MSPIENA_MAX ((uint32_t)0x00000001u)
  1044. #define CSL_SPI_MIBSPIE_RXRAMACCESS_SHIFT ((uint32_t)16u)
  1045. #define CSL_SPI_MIBSPIE_RXRAMACCESS_MASK ((uint32_t)0x00010000u)
  1046. #define CSL_SPI_MIBSPIE_RXRAMACCESS_RESETVAL ((uint32_t)0x00000000u)
  1047. #define CSL_SPI_MIBSPIE_RXRAMACCESS_MAX ((uint32_t)0x00000001u)
  1048. #define CSL_SPI_MIBSPIE_RESETVAL ((uint32_t)0x00000000u)
  1049. /* TGITENST */
  1050. #define CSL_SPI_TGITENST_SETINTENSUS_SHIFT ((uint32_t)0u)
  1051. #define CSL_SPI_TGITENST_SETINTENSUS_MASK ((uint32_t)0x0000FFFFu)
  1052. #define CSL_SPI_TGITENST_SETINTENSUS_RESETVAL ((uint32_t)0x00000000u)
  1053. #define CSL_SPI_TGITENST_SETINTENSUS_MAX ((uint32_t)0x0000ffffu)
  1054. #define CSL_SPI_TGITENST_SETINTENRDY_SHIFT ((uint32_t)16u)
  1055. #define CSL_SPI_TGITENST_SETINTENRDY_MASK ((uint32_t)0xFFFF0000u)
  1056. #define CSL_SPI_TGITENST_SETINTENRDY_RESETVAL ((uint32_t)0x00000000u)
  1057. #define CSL_SPI_TGITENST_SETINTENRDY_MAX ((uint32_t)0x0000ffffu)
  1058. #define CSL_SPI_TGITENST_RESETVAL ((uint32_t)0x00000000u)
  1059. /* TGITENCR */
  1060. #define CSL_SPI_TGITENCR_CLRINTENSUS_SHIFT ((uint32_t)0u)
  1061. #define CSL_SPI_TGITENCR_CLRINTENSUS_MASK ((uint32_t)0x0000FFFFu)
  1062. #define CSL_SPI_TGITENCR_CLRINTENSUS_RESETVAL ((uint32_t)0x00000000u)
  1063. #define CSL_SPI_TGITENCR_CLRINTENSUS_MAX ((uint32_t)0x0000ffffu)
  1064. #define CSL_SPI_TGITENCR_CLRINTENRDY_SHIFT ((uint32_t)16u)
  1065. #define CSL_SPI_TGITENCR_CLRINTENRDY_MASK ((uint32_t)0xFFFF0000u)
  1066. #define CSL_SPI_TGITENCR_CLRINTENRDY_RESETVAL ((uint32_t)0x00000000u)
  1067. #define CSL_SPI_TGITENCR_CLRINTENRDY_MAX ((uint32_t)0x0000ffffu)
  1068. #define CSL_SPI_TGITENCR_RESETVAL ((uint32_t)0x00000000u)
  1069. /* TGITLVST */
  1070. #define CSL_SPI_TGITLVST_SETINTLVLSUS_SHIFT ((uint32_t)0u)
  1071. #define CSL_SPI_TGITLVST_SETINTLVLSUS_MASK ((uint32_t)0x0000FFFFu)
  1072. #define CSL_SPI_TGITLVST_SETINTLVLSUS_RESETVAL ((uint32_t)0x00000000u)
  1073. #define CSL_SPI_TGITLVST_SETINTLVLSUS_MAX ((uint32_t)0x0000ffffu)
  1074. #define CSL_SPI_TGITLVST_SETINTLVLRDY_SHIFT ((uint32_t)16u)
  1075. #define CSL_SPI_TGITLVST_SETINTLVLRDY_MASK ((uint32_t)0xFFFF0000u)
  1076. #define CSL_SPI_TGITLVST_SETINTLVLRDY_RESETVAL ((uint32_t)0x00000000u)
  1077. #define CSL_SPI_TGITLVST_SETINTLVLRDY_MAX ((uint32_t)0x0000ffffu)
  1078. #define CSL_SPI_TGITLVST_RESETVAL ((uint32_t)0x00000000u)
  1079. /* TGITLVCR */
  1080. #define CSL_SPI_TGITLVCR_CLRINTLVLSUS_SHIFT ((uint32_t)0u)
  1081. #define CSL_SPI_TGITLVCR_CLRINTLVLSUS_MASK ((uint32_t)0x0000FFFFu)
  1082. #define CSL_SPI_TGITLVCR_CLRINTLVLSUS_RESETVAL ((uint32_t)0x00000000u)
  1083. #define CSL_SPI_TGITLVCR_CLRINTLVLSUS_MAX ((uint32_t)0x0000ffffu)
  1084. #define CSL_SPI_TGITLVCR_CLRINTLVLRDY_SHIFT ((uint32_t)16u)
  1085. #define CSL_SPI_TGITLVCR_CLRINTLVLRDY_MASK ((uint32_t)0xFFFF0000u)
  1086. #define CSL_SPI_TGITLVCR_CLRINTLVLRDY_RESETVAL ((uint32_t)0x00000000u)
  1087. #define CSL_SPI_TGITLVCR_CLRINTLVLRDY_MAX ((uint32_t)0x0000ffffu)
  1088. #define CSL_SPI_TGITLVCR_RESETVAL ((uint32_t)0x00000000u)
  1089. /* TGINTFLAG */
  1090. #define CSL_SPI_TGINTFLAG_TICKVALUE_SHIFT ((uint32_t)0u)
  1091. #define CSL_SPI_TGINTFLAG_TICKVALUE_MASK ((uint32_t)0x0000FFFFu)
  1092. #define CSL_SPI_TGINTFLAG_TICKVALUE_RESETVAL ((uint32_t)0x00000000u)
  1093. #define CSL_SPI_TGINTFLAG_TICKVALUE_MAX ((uint32_t)0x0000ffffu)
  1094. #define CSL_SPI_TGINTFLAG_CLKCTRL_SHIFT ((uint32_t)28u)
  1095. #define CSL_SPI_TGINTFLAG_CLKCTRL_MASK ((uint32_t)0x30000000u)
  1096. #define CSL_SPI_TGINTFLAG_CLKCTRL_RESETVAL ((uint32_t)0x00000000u)
  1097. #define CSL_SPI_TGINTFLAG_CLKCTRL_MAX ((uint32_t)0x00000003u)
  1098. #define CSL_SPI_TGINTFLAG_RELOAD_SHIFT ((uint32_t)30u)
  1099. #define CSL_SPI_TGINTFLAG_RELOAD_MASK ((uint32_t)0x40000000u)
  1100. #define CSL_SPI_TGINTFLAG_RELOAD_RESETVAL ((uint32_t)0x00000000u)
  1101. #define CSL_SPI_TGINTFLAG_RELOAD_MAX ((uint32_t)0x00000001u)
  1102. #define CSL_SPI_TGINTFLAG_TICKEN_SHIFT ((uint32_t)31u)
  1103. #define CSL_SPI_TGINTFLAG_TICKEN_MASK ((uint32_t)0x80000000u)
  1104. #define CSL_SPI_TGINTFLAG_TICKEN_RESETVAL ((uint32_t)0x00000000u)
  1105. #define CSL_SPI_TGINTFLAG_TICKEN_MAX ((uint32_t)0x00000001u)
  1106. #define CSL_SPI_TGINTFLAG_RESETVAL ((uint32_t)0x00000000u)
  1107. /* LTGPEND */
  1108. #define CSL_SPI_LTGPEND_LPEND_SHIFT ((uint32_t)8u)
  1109. #define CSL_SPI_LTGPEND_LPEND_MASK ((uint32_t)0x00007F00u)
  1110. #define CSL_SPI_LTGPEND_LPEND_RESETVAL ((uint32_t)0x00000000u)
  1111. #define CSL_SPI_LTGPEND_LPEND_MAX ((uint32_t)0x0000007fu)
  1112. #define CSL_SPI_LTGPEND_TGINSERVICE_SHIFT ((uint32_t)24u)
  1113. #define CSL_SPI_LTGPEND_TGINSERVICE_MASK ((uint32_t)0x1F000000u)
  1114. #define CSL_SPI_LTGPEND_TGINSERVICE_RESETVAL ((uint32_t)0x00000000u)
  1115. #define CSL_SPI_LTGPEND_TGINSERVICE_MAX ((uint32_t)0x0000001fu)
  1116. #define CSL_SPI_LTGPEND_RESETVAL ((uint32_t)0x00000000u)
  1117. /* TGCTRL */
  1118. #define CSL_SPI_TGCTRL_PCURRENT_SHIFT ((uint32_t)0u)
  1119. #define CSL_SPI_TGCTRL_PCURRENT_MASK ((uint32_t)0x0000007Fu)
  1120. #define CSL_SPI_TGCTRL_PCURRENT_RESETVAL ((uint32_t)0x00000000u)
  1121. #define CSL_SPI_TGCTRL_PCURRENT_MAX ((uint32_t)0x0000007fu)
  1122. #define CSL_SPI_TGCTRL_PSTART_SHIFT ((uint32_t)8u)
  1123. #define CSL_SPI_TGCTRL_PSTART_MASK ((uint32_t)0x00007F00u)
  1124. #define CSL_SPI_TGCTRL_PSTART_RESETVAL ((uint32_t)0x00000000u)
  1125. #define CSL_SPI_TGCTRL_PSTART_MAX ((uint32_t)0x0000007fu)
  1126. #define CSL_SPI_TGCTRL_TRIGSRC_SHIFT ((uint32_t)16u)
  1127. #define CSL_SPI_TGCTRL_TRIGSRC_MASK ((uint32_t)0x000F0000u)
  1128. #define CSL_SPI_TGCTRL_TRIGSRC_RESETVAL ((uint32_t)0x00000000u)
  1129. #define CSL_SPI_TGCTRL_TRIGSRC_MAX ((uint32_t)0x0000000fu)
  1130. #define CSL_SPI_TGCTRL_TRGEVT_SHIFT ((uint32_t)20u)
  1131. #define CSL_SPI_TGCTRL_TRGEVT_MASK ((uint32_t)0x00F00000u)
  1132. #define CSL_SPI_TGCTRL_TRGEVT_RESETVAL ((uint32_t)0x00000000u)
  1133. #define CSL_SPI_TGCTRL_TRGEVT_MAX ((uint32_t)0x0000000fu)
  1134. #define CSL_SPI_TGCTRL_TGTD_SHIFT ((uint32_t)28u)
  1135. #define CSL_SPI_TGCTRL_TGTD_MASK ((uint32_t)0x10000000u)
  1136. #define CSL_SPI_TGCTRL_TGTD_RESETVAL ((uint32_t)0x00000000u)
  1137. #define CSL_SPI_TGCTRL_TGTD_MAX ((uint32_t)0x00000001u)
  1138. #define CSL_SPI_TGCTRL_PRST_SHIFT ((uint32_t)29u)
  1139. #define CSL_SPI_TGCTRL_PRST_MASK ((uint32_t)0x20000000u)
  1140. #define CSL_SPI_TGCTRL_PRST_RESETVAL ((uint32_t)0x00000000u)
  1141. #define CSL_SPI_TGCTRL_PRST_MAX ((uint32_t)0x00000001u)
  1142. #define CSL_SPI_TGCTRL_ONESHOT_SHIFT ((uint32_t)30u)
  1143. #define CSL_SPI_TGCTRL_ONESHOT_MASK ((uint32_t)0x40000000u)
  1144. #define CSL_SPI_TGCTRL_ONESHOT_RESETVAL ((uint32_t)0x00000000u)
  1145. #define CSL_SPI_TGCTRL_ONESHOT_MAX ((uint32_t)0x00000001u)
  1146. #define CSL_SPI_TGCTRL_TGENA_SHIFT ((uint32_t)31u)
  1147. #define CSL_SPI_TGCTRL_TGENA_MASK ((uint32_t)0x80000000u)
  1148. #define CSL_SPI_TGCTRL_TGENA_RESETVAL ((uint32_t)0x00000000u)
  1149. #define CSL_SPI_TGCTRL_TGENA_MAX ((uint32_t)0x00000001u)
  1150. #define CSL_SPI_TGCTRL_RESETVAL ((uint32_t)0x00000000u)
  1151. /* DMACTRL */
  1152. #define CSL_SPI_DMACTRL_COUNT_SHIFT ((uint32_t)0u)
  1153. #define CSL_SPI_DMACTRL_COUNT_MASK ((uint32_t)0x0000003Fu)
  1154. #define CSL_SPI_DMACTRL_COUNT_RESETVAL ((uint32_t)0x00000000u)
  1155. #define CSL_SPI_DMACTRL_COUNT_MAX ((uint32_t)0x0000003fu)
  1156. #define CSL_SPI_DMACTRL_COUNTBIT17_SHIFT ((uint32_t)6u)
  1157. #define CSL_SPI_DMACTRL_COUNTBIT17_MASK ((uint32_t)0x00000040u)
  1158. #define CSL_SPI_DMACTRL_COUNTBIT17_RESETVAL ((uint32_t)0x00000000u)
  1159. #define CSL_SPI_DMACTRL_COUNTBIT17_MAX ((uint32_t)0x00000001u)
  1160. #define CSL_SPI_DMACTRL_ICOUNT_SHIFT ((uint32_t)8u)
  1161. #define CSL_SPI_DMACTRL_ICOUNT_MASK ((uint32_t)0x00001F00u)
  1162. #define CSL_SPI_DMACTRL_ICOUNT_RESETVAL ((uint32_t)0x00000000u)
  1163. #define CSL_SPI_DMACTRL_ICOUNT_MAX ((uint32_t)0x0000001fu)
  1164. #define CSL_SPI_DMACTRL_NOBRK_SHIFT ((uint32_t)13u)
  1165. #define CSL_SPI_DMACTRL_NOBRK_MASK ((uint32_t)0x00002000u)
  1166. #define CSL_SPI_DMACTRL_NOBRK_RESETVAL ((uint32_t)0x00000000u)
  1167. #define CSL_SPI_DMACTRL_NOBRK_MAX ((uint32_t)0x00000001u)
  1168. #define CSL_SPI_DMACTRL_TXDMAENA_SHIFT ((uint32_t)14u)
  1169. #define CSL_SPI_DMACTRL_TXDMAENA_MASK ((uint32_t)0x00004000u)
  1170. #define CSL_SPI_DMACTRL_TXDMAENA_RESETVAL ((uint32_t)0x00000000u)
  1171. #define CSL_SPI_DMACTRL_TXDMAENA_MAX ((uint32_t)0x00000001u)
  1172. #define CSL_SPI_DMACTRL_RXDMAENA_SHIFT ((uint32_t)15u)
  1173. #define CSL_SPI_DMACTRL_RXDMAENA_MASK ((uint32_t)0x00008000u)
  1174. #define CSL_SPI_DMACTRL_RXDMAENA_RESETVAL ((uint32_t)0x00000000u)
  1175. #define CSL_SPI_DMACTRL_RXDMAENA_MAX ((uint32_t)0x00000001u)
  1176. #define CSL_SPI_DMACTRL_TXDMA_MAP_SHIFT ((uint32_t)16u)
  1177. #define CSL_SPI_DMACTRL_TXDMA_MAP_MASK ((uint32_t)0x000F0000u)
  1178. #define CSL_SPI_DMACTRL_TXDMA_MAP_RESETVAL ((uint32_t)0x00000000u)
  1179. #define CSL_SPI_DMACTRL_TXDMA_MAP_MAX ((uint32_t)0x0000000fu)
  1180. #define CSL_SPI_DMACTRL_RXDMA_MAP_SHIFT ((uint32_t)20u)
  1181. #define CSL_SPI_DMACTRL_RXDMA_MAP_MASK ((uint32_t)0x00F00000u)
  1182. #define CSL_SPI_DMACTRL_RXDMA_MAP_RESETVAL ((uint32_t)0x00000000u)
  1183. #define CSL_SPI_DMACTRL_RXDMA_MAP_MAX ((uint32_t)0x0000000fu)
  1184. #define CSL_SPI_DMACTRL_BUFID_SHIFT ((uint32_t)24u)
  1185. #define CSL_SPI_DMACTRL_BUFID_MASK ((uint32_t)0x7F000000u)
  1186. #define CSL_SPI_DMACTRL_BUFID_RESETVAL ((uint32_t)0x00000000u)
  1187. #define CSL_SPI_DMACTRL_BUFID_MAX ((uint32_t)0x0000007fu)
  1188. #define CSL_SPI_DMACTRL_ONESHOT_SHIFT ((uint32_t)31u)
  1189. #define CSL_SPI_DMACTRL_ONESHOT_MASK ((uint32_t)0x80000000u)
  1190. #define CSL_SPI_DMACTRL_ONESHOT_RESETVAL ((uint32_t)0x00000000u)
  1191. #define CSL_SPI_DMACTRL_ONESHOT_MAX ((uint32_t)0x00000001u)
  1192. #define CSL_SPI_DMACTRL_RESETVAL ((uint32_t)0x00000000u)
  1193. /* DMACOUNT */
  1194. #define CSL_SPI_DMACOUNT_COUNT_SHIFT ((uint32_t)0u)
  1195. #define CSL_SPI_DMACOUNT_COUNT_MASK ((uint32_t)0x0000FFFFu)
  1196. #define CSL_SPI_DMACOUNT_COUNT_RESETVAL ((uint32_t)0x00000000u)
  1197. #define CSL_SPI_DMACOUNT_COUNT_MAX ((uint32_t)0x0000ffffu)
  1198. #define CSL_SPI_DMACOUNT_ICOUNT_SHIFT ((uint32_t)16u)
  1199. #define CSL_SPI_DMACOUNT_ICOUNT_MASK ((uint32_t)0xFFFF0000u)
  1200. #define CSL_SPI_DMACOUNT_ICOUNT_RESETVAL ((uint32_t)0x00000000u)
  1201. #define CSL_SPI_DMACOUNT_ICOUNT_MAX ((uint32_t)0x0000ffffu)
  1202. #define CSL_SPI_DMACOUNT_RESETVAL ((uint32_t)0x00000000u)
  1203. /* DMA0CNTL */
  1204. #define CSL_SPI_DMA0CNTL_LARGECOUNT_SHIFT ((uint32_t)0u)
  1205. #define CSL_SPI_DMA0CNTL_LARGECOUNT_MASK ((uint32_t)0x00000001u)
  1206. #define CSL_SPI_DMA0CNTL_LARGECOUNT_RESETVAL ((uint32_t)0x00000000u)
  1207. #define CSL_SPI_DMA0CNTL_LARGECOUNT_MAX ((uint32_t)0x00000001u)
  1208. #define CSL_SPI_DMA0CNTL_RESETVAL ((uint32_t)0x00000000u)
  1209. /* UERRCTRL */
  1210. #define CSL_SPI_UERRCTRL_EDEN_SHIFT ((uint32_t)0u)
  1211. #define CSL_SPI_UERRCTRL_EDEN_MASK ((uint32_t)0x0000000Fu)
  1212. #define CSL_SPI_UERRCTRL_EDEN_RESETVAL ((uint32_t)0x00000000u)
  1213. #define CSL_SPI_UERRCTRL_EDEN_MAX ((uint32_t)0x0000000fu)
  1214. #define CSL_SPI_UERRCTRL_PTESTEN_SHIFT ((uint32_t)8u)
  1215. #define CSL_SPI_UERRCTRL_PTESTEN_MASK ((uint32_t)0x00000100u)
  1216. #define CSL_SPI_UERRCTRL_PTESTEN_RESETVAL ((uint32_t)0x00000000u)
  1217. #define CSL_SPI_UERRCTRL_PTESTEN_MAX ((uint32_t)0x00000001u)
  1218. #define CSL_SPI_UERRCTRL_RESETVAL ((uint32_t)0x00000000u)
  1219. /* UERRSTAT */
  1220. #define CSL_SPI_UERRSTAT_EDFLG0_SHIFT ((uint32_t)0u)
  1221. #define CSL_SPI_UERRSTAT_EDFLG0_MASK ((uint32_t)0x00000001u)
  1222. #define CSL_SPI_UERRSTAT_EDFLG0_RESETVAL ((uint32_t)0x00000000u)
  1223. #define CSL_SPI_UERRSTAT_EDFLG0_MAX ((uint32_t)0x00000001u)
  1224. #define CSL_SPI_UERRSTAT_EDFLG1_SHIFT ((uint32_t)1u)
  1225. #define CSL_SPI_UERRSTAT_EDFLG1_MASK ((uint32_t)0x00000002u)
  1226. #define CSL_SPI_UERRSTAT_EDFLG1_RESETVAL ((uint32_t)0x00000000u)
  1227. #define CSL_SPI_UERRSTAT_EDFLG1_MAX ((uint32_t)0x00000001u)
  1228. #define CSL_SPI_UERRSTAT_RESETVAL ((uint32_t)0x00000000u)
  1229. /* UERRADDR1 */
  1230. #define CSL_SPI_UERRADDR1_UERRADDR1_SHIFT ((uint32_t)0u)
  1231. #define CSL_SPI_UERRADDR1_UERRADDR1_MASK ((uint32_t)0x000003FFu)
  1232. #define CSL_SPI_UERRADDR1_UERRADDR1_RESETVAL ((uint32_t)0x00000000u)
  1233. #define CSL_SPI_UERRADDR1_UERRADDR1_MAX ((uint32_t)0x000003ffu)
  1234. #define CSL_SPI_UERRADDR1_RESETVAL ((uint32_t)0x00000000u)
  1235. /* UERRADDR0 */
  1236. #define CSL_SPI_UERRADDR0_UERRADDR0_SHIFT ((uint32_t)0u)
  1237. #define CSL_SPI_UERRADDR0_UERRADDR0_MASK ((uint32_t)0x000001FFu)
  1238. #define CSL_SPI_UERRADDR0_UERRADDR0_RESETVAL ((uint32_t)0x00000000u)
  1239. #define CSL_SPI_UERRADDR0_UERRADDR0_MAX ((uint32_t)0x000001ffu)
  1240. #define CSL_SPI_UERRADDR0_RESETVAL ((uint32_t)0x00000000u)
  1241. /* RXOVRN_BUF_ADDR */
  1242. #define CSL_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_SHIFT ((uint32_t)0u)
  1243. #define CSL_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_MASK ((uint32_t)0x000003FFu)
  1244. #define CSL_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_RESETVAL ((uint32_t)0x00000000u)
  1245. #define CSL_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_MAX ((uint32_t)0x000003ffu)
  1246. #define CSL_SPI_RXOVRN_BUF_ADDR_RESETVAL ((uint32_t)0x00000000u)
  1247. /* IOLPBKTSTCR */
  1248. #define CSL_SPI_IOLPBKTSTCR_RXPENA_SHIFT ((uint32_t)0u)
  1249. #define CSL_SPI_IOLPBKTSTCR_RXPENA_MASK ((uint32_t)0x00000001u)
  1250. #define CSL_SPI_IOLPBKTSTCR_RXPENA_RESETVAL ((uint32_t)0x00000000u)
  1251. #define CSL_SPI_IOLPBKTSTCR_RXPENA_MAX ((uint32_t)0x00000001u)
  1252. #define CSL_SPI_IOLPBKTSTCR_LPBKTYPE_SHIFT ((uint32_t)1u)
  1253. #define CSL_SPI_IOLPBKTSTCR_LPBKTYPE_MASK ((uint32_t)0x00000002u)
  1254. #define CSL_SPI_IOLPBKTSTCR_LPBKTYPE_RESETVAL ((uint32_t)0x00000000u)
  1255. #define CSL_SPI_IOLPBKTSTCR_LPBKTYPE_MAX ((uint32_t)0x00000001u)
  1256. #define CSL_SPI_IOLPBKTSTCR_CTRLSCSPINERR_SHIFT ((uint32_t)2u)
  1257. #define CSL_SPI_IOLPBKTSTCR_CTRLSCSPINERR_MASK ((uint32_t)0x00000004u)
  1258. #define CSL_SPI_IOLPBKTSTCR_CTRLSCSPINERR_RESETVAL ((uint32_t)0x00000000u)
  1259. #define CSL_SPI_IOLPBKTSTCR_CTRLSCSPINERR_MAX ((uint32_t)0x00000001u)
  1260. #define CSL_SPI_IOLPBKTSTCR_ERRSCSPIN_SHIFT ((uint32_t)3u)
  1261. #define CSL_SPI_IOLPBKTSTCR_ERRSCSPIN_MASK ((uint32_t)0x00000078u)
  1262. #define CSL_SPI_IOLPBKTSTCR_ERRSCSPIN_RESETVAL ((uint32_t)0x00000000u)
  1263. #define CSL_SPI_IOLPBKTSTCR_ERRSCSPIN_MAX ((uint32_t)0x0000000fu)
  1264. #define CSL_SPI_IOLPBKTSTCR_IPLPBKTSTENA_SHIFT ((uint32_t)8u)
  1265. #define CSL_SPI_IOLPBKTSTCR_IPLPBKTSTENA_MASK ((uint32_t)0x00000F00u)
  1266. #define CSL_SPI_IOLPBKTSTCR_IPLPBKTSTENA_RESETVAL ((uint32_t)0x00000000u)
  1267. #define CSL_SPI_IOLPBKTSTCR_IPLPBKTSTENA_MAX ((uint32_t)0x0000000fu)
  1268. #define CSL_SPI_IOLPBKTSTCR_CTRLDLENERR_SHIFT ((uint32_t)16u)
  1269. #define CSL_SPI_IOLPBKTSTCR_CTRLDLENERR_MASK ((uint32_t)0x00010000u)
  1270. #define CSL_SPI_IOLPBKTSTCR_CTRLDLENERR_RESETVAL ((uint32_t)0x00000000u)
  1271. #define CSL_SPI_IOLPBKTSTCR_CTRLDLENERR_MAX ((uint32_t)0x00000001u)
  1272. #define CSL_SPI_IOLPBKTSTCR_CTRLTIMEOUT_SHIFT ((uint32_t)17u)
  1273. #define CSL_SPI_IOLPBKTSTCR_CTRLTIMEOUT_MASK ((uint32_t)0x00020000u)
  1274. #define CSL_SPI_IOLPBKTSTCR_CTRLTIMEOUT_RESETVAL ((uint32_t)0x00000000u)
  1275. #define CSL_SPI_IOLPBKTSTCR_CTRLTIMEOUT_MAX ((uint32_t)0x00000001u)
  1276. #define CSL_SPI_IOLPBKTSTCR_CTRLPARERR_SHIFT ((uint32_t)18u)
  1277. #define CSL_SPI_IOLPBKTSTCR_CTRLPARERR_MASK ((uint32_t)0x00040000u)
  1278. #define CSL_SPI_IOLPBKTSTCR_CTRLPARERR_RESETVAL ((uint32_t)0x00000000u)
  1279. #define CSL_SPI_IOLPBKTSTCR_CTRLPARERR_MAX ((uint32_t)0x00000001u)
  1280. #define CSL_SPI_IOLPBKTSTCR_CTRLDESYNC_SHIFT ((uint32_t)19u)
  1281. #define CSL_SPI_IOLPBKTSTCR_CTRLDESYNC_MASK ((uint32_t)0x00080000u)
  1282. #define CSL_SPI_IOLPBKTSTCR_CTRLDESYNC_RESETVAL ((uint32_t)0x00000000u)
  1283. #define CSL_SPI_IOLPBKTSTCR_CTRLDESYNC_MAX ((uint32_t)0x00000001u)
  1284. #define CSL_SPI_IOLPBKTSTCR_CTRLBITERR_SHIFT ((uint32_t)20u)
  1285. #define CSL_SPI_IOLPBKTSTCR_CTRLBITERR_MASK ((uint32_t)0x00100000u)
  1286. #define CSL_SPI_IOLPBKTSTCR_CTRLBITERR_RESETVAL ((uint32_t)0x00000000u)
  1287. #define CSL_SPI_IOLPBKTSTCR_CTRLBITERR_MAX ((uint32_t)0x00000001u)
  1288. #define CSL_SPI_IOLPBKTSTCR_SCSFAILFLG_SHIFT ((uint32_t)24u)
  1289. #define CSL_SPI_IOLPBKTSTCR_SCSFAILFLG_MASK ((uint32_t)0x01000000u)
  1290. #define CSL_SPI_IOLPBKTSTCR_SCSFAILFLG_RESETVAL ((uint32_t)0x00000000u)
  1291. #define CSL_SPI_IOLPBKTSTCR_SCSFAILFLG_MAX ((uint32_t)0x00000001u)
  1292. #define CSL_SPI_IOLPBKTSTCR_RESETVAL ((uint32_t)0x00000000u)
  1293. /* SPIREV */
  1294. #define CSL_SPI_SPIREV_MINOR_SHIFT ((uint32_t)0u)
  1295. #define CSL_SPI_SPIREV_MINOR_MASK ((uint32_t)0x0000003Fu)
  1296. #define CSL_SPI_SPIREV_MINOR_RESETVAL ((uint32_t)0x00000000u)
  1297. #define CSL_SPI_SPIREV_MINOR_MAX ((uint32_t)0x0000003fu)
  1298. #define CSL_SPI_SPIREV_CUSTOM_SHIFT ((uint32_t)6u)
  1299. #define CSL_SPI_SPIREV_CUSTOM_MASK ((uint32_t)0x000000C0u)
  1300. #define CSL_SPI_SPIREV_CUSTOM_RESETVAL ((uint32_t)0x00000000u)
  1301. #define CSL_SPI_SPIREV_CUSTOM_MAX ((uint32_t)0x00000003u)
  1302. #define CSL_SPI_SPIREV_MAJOR_SHIFT ((uint32_t)8u)
  1303. #define CSL_SPI_SPIREV_MAJOR_MASK ((uint32_t)0x00000700u)
  1304. #define CSL_SPI_SPIREV_MAJOR_RESETVAL ((uint32_t)0x00000000u)
  1305. #define CSL_SPI_SPIREV_MAJOR_MAX ((uint32_t)0x00000007u)
  1306. #define CSL_SPI_SPIREV_RTL_SHIFT ((uint32_t)11u)
  1307. #define CSL_SPI_SPIREV_RTL_MASK ((uint32_t)0x0000F800u)
  1308. #define CSL_SPI_SPIREV_RTL_RESETVAL ((uint32_t)0x00000000u)
  1309. #define CSL_SPI_SPIREV_RTL_MAX ((uint32_t)0x0000001fu)
  1310. #define CSL_SPI_SPIREV_FUNC_SHIFT ((uint32_t)16u)
  1311. #define CSL_SPI_SPIREV_FUNC_MASK ((uint32_t)0x0FFF0000u)
  1312. #define CSL_SPI_SPIREV_FUNC_RESETVAL ((uint32_t)0x00000000u)
  1313. #define CSL_SPI_SPIREV_FUNC_MAX ((uint32_t)0x00000fffu)
  1314. #define CSL_SPI_SPIREV_SCHEME_SHIFT ((uint32_t)30u)
  1315. #define CSL_SPI_SPIREV_SCHEME_MASK ((uint32_t)0xC0000000u)
  1316. #define CSL_SPI_SPIREV_SCHEME_RESETVAL ((uint32_t)0x00000000u)
  1317. #define CSL_SPI_SPIREV_SCHEME_MAX ((uint32_t)0x00000003u)
  1318. #define CSL_SPI_SPIREV_RESETVAL ((uint32_t)0x00000000u)
  1319. #ifdef __cplusplus
  1320. }
  1321. #endif
  1322. #endif