cslr_eve_tpcc.h 718 KB

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  1. /********************************************************************
  2. * Copyright (C) 2013-2014 Texas Instruments Incorporated.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. *
  11. * Redistributions in binary form must reproduce the above copyright
  12. * notice, this list of conditions and the following disclaimer in the
  13. * documentation and/or other materials provided with the
  14. * distribution.
  15. *
  16. * Neither the name of Texas Instruments Incorporated nor the names of
  17. * its contributors may be used to endorse or promote products derived
  18. * from this software without specific prior written permission.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. *
  32. */
  33. #ifndef CSLR_EVETPCC_H_
  34. #define CSLR_EVETPCC_H_
  35. #ifdef __cplusplus
  36. extern "C"
  37. {
  38. #endif
  39. #include <ti/csl/cslr.h>
  40. #include <ti/csl/tistdtypes.h>
  41. /**************************************************************************
  42. * Register Overlay Structure for QRAEN
  43. **************************************************************************/
  44. typedef struct {
  45. volatile Uint32 QRAEN[8];
  46. } CSL_EvetpccQraenRegs;
  47. /**************************************************************************
  48. * Register Overlay Structure for CONFIG
  49. **************************************************************************/
  50. typedef struct {
  51. volatile Uint32 QSTATN[2];
  52. volatile Uint8 RSVD0[24];
  53. volatile Uint32 QWMTHRA;
  54. volatile Uint32 QWMTHRB;
  55. volatile Uint8 RSVD1[24];
  56. volatile Uint32 CCSTAT;
  57. volatile Uint8 RSVD2[188];
  58. volatile Uint32 AETCTL;
  59. volatile Uint32 AETSTAT;
  60. volatile Uint32 AETCMD;
  61. volatile Uint8 RSVD3[244];
  62. volatile Uint32 MPFAR;
  63. volatile Uint32 MPFSR;
  64. volatile Uint32 MPFCR;
  65. volatile Uint32 MPPAG;
  66. volatile Uint32 MPPAN[8];
  67. volatile Uint8 RSVD4[2000];
  68. volatile Uint32 ER;
  69. volatile Uint32 ERH;
  70. volatile Uint32 ECR;
  71. volatile Uint32 ECRH;
  72. volatile Uint32 ESR;
  73. volatile Uint32 ESRH;
  74. volatile Uint32 CER;
  75. volatile Uint32 CERH;
  76. volatile Uint32 EER;
  77. volatile Uint32 EERH;
  78. volatile Uint32 EECR;
  79. volatile Uint32 EECRH;
  80. volatile Uint32 EESR;
  81. volatile Uint32 EESRH;
  82. volatile Uint32 SER;
  83. volatile Uint32 SERH;
  84. volatile Uint32 SECR;
  85. volatile Uint32 SECRH;
  86. volatile Uint8 RSVD5[8];
  87. volatile Uint32 IER;
  88. volatile Uint32 IERH;
  89. volatile Uint32 IECR;
  90. volatile Uint32 IECRH;
  91. volatile Uint32 IESR;
  92. volatile Uint32 IESRH;
  93. volatile Uint32 IPR;
  94. volatile Uint32 IPRH;
  95. volatile Uint32 ICR;
  96. volatile Uint32 ICRH;
  97. volatile Uint32 IEVAL;
  98. volatile Uint8 RSVD6[4];
  99. volatile Uint32 QER;
  100. volatile Uint32 QEER;
  101. volatile Uint32 QEECR;
  102. volatile Uint32 QEESR;
  103. volatile Uint32 QSER;
  104. volatile Uint32 QSECR;
  105. } CSL_EvetpccConfigRegs;
  106. /**************************************************************************
  107. * Register Overlay Structure for SHADOW_N
  108. **************************************************************************/
  109. typedef struct {
  110. volatile Uint32 ER_RN;
  111. volatile Uint32 ERH_RN;
  112. volatile Uint32 ECR_RN;
  113. volatile Uint32 ECRH_RN;
  114. volatile Uint32 ESR_RN;
  115. volatile Uint32 ESRH_RN;
  116. volatile Uint32 CER_RN;
  117. volatile Uint32 CERH_RN;
  118. volatile Uint32 EER_RN;
  119. volatile Uint32 EERH_RN;
  120. volatile Uint32 EECR_RN;
  121. volatile Uint32 EECRH_RN;
  122. volatile Uint32 EESR_RN;
  123. volatile Uint32 EESRH_RN;
  124. volatile Uint32 SER_RN;
  125. volatile Uint32 SERH_RN;
  126. volatile Uint32 SECR_RN;
  127. volatile Uint32 SECRH_RN;
  128. volatile Uint8 RSVD0[8];
  129. volatile Uint32 IER_RN;
  130. volatile Uint32 IERH_RN;
  131. volatile Uint32 IECR_RN;
  132. volatile Uint32 IECRH_RN;
  133. volatile Uint32 IESR_RN;
  134. volatile Uint32 IESRH_RN;
  135. volatile Uint32 IPR_RN;
  136. volatile Uint32 IPRH_RN;
  137. volatile Uint32 ICR_RN;
  138. volatile Uint32 ICRH_RN;
  139. volatile Uint32 IEVAL_RN;
  140. volatile Uint8 RSVD1[4];
  141. volatile Uint32 QER_RN;
  142. volatile Uint32 QEER_RN;
  143. volatile Uint32 QEECR_RN;
  144. volatile Uint32 QEESR_RN;
  145. volatile Uint32 QSER_RN;
  146. volatile Uint32 QSECR_RN;
  147. volatile Uint8 RSVD2[360];
  148. } CSL_EvetpccShadow_nRegs;
  149. /**************************************************************************
  150. * Register Overlay Structure for PARAMSET
  151. **************************************************************************/
  152. typedef struct {
  153. volatile Uint32 OPT;
  154. volatile Uint32 SRC;
  155. volatile Uint32 ABCNT;
  156. volatile Uint32 DST;
  157. volatile Uint32 BIDX;
  158. volatile Uint32 LNK;
  159. volatile Uint32 CIDX;
  160. volatile Uint32 CCNT;
  161. } CSL_EvetpccParamsetRegs;
  162. /**************************************************************************
  163. * Register Overlay Structure
  164. **************************************************************************/
  165. typedef struct {
  166. volatile Uint32 PID;
  167. volatile Uint32 CCCFG;
  168. volatile Uint8 RSVD0[244];
  169. volatile Uint32 CLKGDIS;
  170. volatile Uint32 DCHMAPN[16];
  171. volatile Uint8 RSVD1[192];
  172. volatile Uint32 QCHMAPN[8];
  173. volatile Uint8 RSVD2[32];
  174. volatile Uint32 DMAQNUMN[2];
  175. volatile Uint8 RSVD3[24];
  176. volatile Uint32 QDMAQNUM;
  177. volatile Uint8 RSVD4[28];
  178. volatile Uint32 QUETCMAP;
  179. volatile Uint32 QUEPRI;
  180. volatile Uint8 RSVD5[120];
  181. volatile Uint32 EMR;
  182. volatile Uint32 EMRH;
  183. volatile Uint32 EMCR;
  184. volatile Uint32 EMCRH;
  185. volatile Uint32 QEMR;
  186. volatile Uint32 QEMCR;
  187. volatile Uint32 CCERR;
  188. volatile Uint32 CCERRCLR;
  189. volatile Uint32 EEVAL;
  190. volatile Uint8 RSVD6[92];
  191. CSL_EvetpccQraenRegs QRAEN;
  192. volatile Uint8 RSVD7[608];
  193. CSL_EvetpccConfigRegs CONFIG;
  194. volatile Uint8 RSVD8[3944];
  195. CSL_EvetpccShadow_nRegs SHADOW_N[8];
  196. volatile Uint8 RSVD9[4096];
  197. CSL_EvetpccParamsetRegs PARAMSET[128];
  198. } CSL_EveTpccRegs;
  199. /**************************************************************************
  200. * Register Macros
  201. **************************************************************************/
  202. /* Peripheral ID Register */
  203. #define CSL_EVETPCC_PID (0x0U)
  204. /* CC Configuration Register */
  205. #define CSL_EVETPCC_CCCFG (0x4U)
  206. /* Auto Clock Gate Disable */
  207. #define CSL_EVETPCC_CLKGDIS (0xFCU)
  208. /* DMA Channel N Mapping Register */
  209. #define CSL_EVETPCC_DCHMAPN(i) (0x100U + ((i) * (0x4U)))
  210. /* QDMA Channel N Mapping Register */
  211. #define CSL_EVETPCC_QCHMAPN(i) (0x200U + ((i) * (0x4U)))
  212. /* DMA Queue Number Register n Contains the Event queue number to be used for
  213. * the corresponding DMA Channel. */
  214. #define CSL_EVETPCC_DMAQNUMN(i) (0x240U + ((i) * (0x4U)))
  215. /* QDMA Queue Number Register Contains the Event queue number to be used for
  216. * the corresponding QDMA Channel. */
  217. #define CSL_EVETPCC_QDMAQNUM (0x260U)
  218. /* Queue to TC Mapping */
  219. #define CSL_EVETPCC_QUETCMAP (0x280U)
  220. /* Queue Priority */
  221. #define CSL_EVETPCC_QUEPRI (0x284U)
  222. /* Event Missed Register: The Event Missed register is set if 2 events are
  223. * received without the first event being cleared or if a Null TR is serviced.
  224. * Chained events (CER), Set Events (ESR), and normal events (ER) are treated
  225. * individually. If any bit in the EMR register is set (and all errors
  226. * (including QEMR/CCERR) were previously clear), then an error will be
  227. * signaled with TPCC error interrupt. */
  228. #define CSL_EVETPCC_EMR (0x300U)
  229. /* Event Missed Register (High Part): The Event Missed register is set if 2
  230. * events are received without the first event being cleared or if a Null TR
  231. * is serviced. Chained events (CER), Set Events (ESR), and normal events (ER)
  232. * are treated individually. If any bit in the EMR register is set (and all
  233. * errors (including QEMR/CCERR) were previously clear), then an error will be
  234. * signaled with TPCC error interrupt. */
  235. #define CSL_EVETPCC_EMRH (0x304U)
  236. /* Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the
  237. * EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits
  238. * must be cleared before additional error interrupts will be asserted by CC. */
  239. #define CSL_EVETPCC_EMCR (0x308U)
  240. /* Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En
  241. * bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect..
  242. * All error bits must be cleared before additional error interrupts will be
  243. * asserted by CC. */
  244. #define CSL_EVETPCC_EMCRH (0x30CU)
  245. /* QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA
  246. * events are detected without the first event being cleared or if a Null TR
  247. * is serviced.. If any bit in the QEMR register is set (and all errors
  248. * (including EMR/CCERR) were previously clear), then an error will be
  249. * signaled with TPCC error interrupt. */
  250. #define CSL_EVETPCC_QEMR (0x310U)
  251. /* QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit
  252. * causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All
  253. * error bits must be cleared before additional error interrupts will be
  254. * asserted by CC. */
  255. #define CSL_EVETPCC_QEMCR (0x314U)
  256. /* CC Error Register */
  257. #define CSL_EVETPCC_CCERR (0x318U)
  258. /* CC Error Clear Register */
  259. #define CSL_EVETPCC_CCERRCLR (0x31CU)
  260. /* Error Eval Register */
  261. #define CSL_EVETPCC_EEVAL (0x320U)
  262. /* QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via
  263. * Region M address space to Bit N in any QDMA Channel Register are not
  264. * allowed. Reads will return 'b0 on Bit N and writes will not modify the
  265. * state of bit N. Enabled interrupt bits for bit N do not contribute to the
  266. * generation of the TPCC region M interrupt. En = 1 : Accesses via Region M
  267. * address space to Bit N in any QDMA Channel Register are allowed. Reads will
  268. * return the value from Bit N and writes will modify the state of bit N.
  269. * Enabled interrupt bits for bit N do contribute to the generation of the
  270. * TPCC region n interrupt. */
  271. #define CSL_EVETPCC_QRAEN(i) (0x380U + ((i) * (0x4U)))
  272. /* QSTATn Register Set */
  273. #define CSL_EVETPCC_QSTATN(i) (0x600U + ((i) * (0x4U)))
  274. /* Queue Threshold A, for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit
  275. * is set when the number of Events in QueueN at an instant in time (visible
  276. * via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn.
  277. * Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11
  278. * disables threshold errors. */
  279. #define CSL_EVETPCC_QWMTHRA (0x620U)
  280. /* Queue Threshold B, for Q[7:4]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit
  281. * is set when the number of Events in QueueN at an instant in time (visible
  282. * via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn.
  283. * Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11
  284. * disables threshold errors. */
  285. #define CSL_EVETPCC_QWMTHRB (0x624U)
  286. /* CC Status Register */
  287. #define CSL_EVETPCC_CCSTAT (0x640U)
  288. /* Advanced Event Trigger Control */
  289. #define CSL_EVETPCC_AETCTL (0x700U)
  290. /* Advanced Event Trigger Stat */
  291. #define CSL_EVETPCC_AETSTAT (0x704U)
  292. /* AET Command */
  293. #define CSL_EVETPCC_AETCMD (0x708U)
  294. /* Memory Protection Fault Address */
  295. #define CSL_EVETPCC_MPFAR (0x800U)
  296. /* Memory Protection Fault Status Register */
  297. #define CSL_EVETPCC_MPFSR (0x804U)
  298. /* Memory Protection Fault Command Register */
  299. #define CSL_EVETPCC_MPFCR (0x808U)
  300. /* Memory Protection Page Attribute for Global registers */
  301. #define CSL_EVETPCC_MPPAG (0x80CU)
  302. /* MP Permission Attribute for DMA Region n */
  303. #define CSL_EVETPCC_MPPAN(i) (0x810U + ((i) * (0x4U)))
  304. /* Event Register: If ER.En bit is set and the EER.En bit is also set, then
  305. * the corresponding DMA channel is prioritized vs. other pending DMA events
  306. * for submission to the TC. ER.En bit is set when the input event #n
  307. * transitions from inactive (low) to active (high), regardless of the state
  308. * of EER.En bit. ER.En bit is cleared when the corresponding event is
  309. * prioritized and serviced. If the ER.En bit is already set and a new
  310. * inactive to active transition is detected on the input event #n input AND
  311. * the corresponding bit in the EER register is set, then the corresponding
  312. * bit in the Event Missed Register is set. Event N can be cleared via sw by
  313. * writing a '1' to the ECR pseudo-register. */
  314. #define CSL_EVETPCC_ER (0x1000U)
  315. /* Event Register (High Part): If ERH.En bit is set and the EERH.En bit is
  316. * also set, then the corresponding DMA channel is prioritized vs. other
  317. * pending DMA events for submission to the TC. ERH.En bit is set when the
  318. * input event #n transitions from inactive (low) to active (high), regardless
  319. * of the state of EERH.En bit. ER.En bit is cleared when the corresponding
  320. * event is prioritized and serviced. If the ERH.En bit is already set and a
  321. * new inactive to active transition is detected on the input event #n input
  322. * AND the corresponding bit in the EERH register is set, then the
  323. * corresponding bit in the Event Missed Register is set. Event N can be
  324. * cleared via sw by writing a '1' to the ECRH pseudo-register. */
  325. #define CSL_EVETPCC_ERH (0x1004U)
  326. /* Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En
  327. * bit to be cleared. CPU write of '0' has no effect. */
  328. #define CSL_EVETPCC_ECR (0x1008U)
  329. /* Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit
  330. * causes the ERH.En bit to be cleared. CPU write of '0' has no effect. */
  331. #define CSL_EVETPCC_ECRH (0x100CU)
  332. /* Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit
  333. * to be set. CPU write of '0' has no effect. */
  334. #define CSL_EVETPCC_ESR (0x1010U)
  335. /* Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes
  336. * the ERH.En bit to be set. CPU write of '0' has no effect. */
  337. #define CSL_EVETPCC_ESRH (0x1014U)
  338. /* Chained Event Register: If CER.En bit is set (regardless of state of
  339. * EER.En), then the corresponding DMA channel is prioritized vs. other
  340. * pending DMA events for submission to the TC. CER.En bit is set when a
  341. * chaining completion code is returned from one of the 3PTCs via the
  342. * completion interface, or is generated internally via Early Completion path.
  343. * CER.En bit is cleared when the corresponding event is prioritized and
  344. * serviced. If the CER.En bit is already set and the corresponding chaining
  345. * completion code is returned from the TC, then the corresponding bit in the
  346. * Event Missed Register is set. CER.En cannot be set or cleared via software. */
  347. #define CSL_EVETPCC_CER (0x1018U)
  348. /* Chained Event Register (High Part): If CERH.En bit is set (regardless of
  349. * state of EERH.En), then the corresponding DMA channel is prioritized vs.
  350. * other pending DMA events for submission to the TC. CERH.En bit is set when
  351. * a chaining completion code is returned from one of the 3PTCs via the
  352. * completion interface, or is generated internally via Early Completion path.
  353. * CERH.En bit is cleared when the corresponding event is prioritized and
  354. * serviced. If the CERH.En bit is already set and the corresponding chaining
  355. * completion code is returned from the TC, then the corresponding bit in the
  356. * Event Missed Register is set. CERH.En cannot be set or cleared via
  357. * software. */
  358. #define CSL_EVETPCC_CERH (0x101CU)
  359. /* Event Enable Register: Enables DMA transfers for ER.En pending events.
  360. * ER.En is set based on externally asserted events (via tpcc_eventN_pi). This
  361. * register has no effect on Chained Event Register (CER) or Event Set
  362. * Register (ESR). Note that if a bit is set in ER.En while EER.En is
  363. * disabled, no action is taken. If EER.En is enabled at a later point (and
  364. * ER.En has not been cleared via SW) then the event will be recognized as a
  365. * valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via
  366. * writes to EESR and can be disabled via writes to EECR register. EER.En = 0:
  367. * ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled
  368. * to trigger DMA transfers. */
  369. #define CSL_EVETPCC_EER (0x1020U)
  370. /* Event Enable Register (High Part): Enables DMA transfers for ERH.En pending
  371. * events. ERH.En is set based on externally asserted events (via
  372. * tpcc_eventN_pi). This register has no effect on Chained Event Register
  373. * (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En
  374. * while EERH.En is disabled, no action is taken. If EERH.En is enabled at a
  375. * later point (and ERH.En has not been cleared via SW) then the event will be
  376. * recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events
  377. * can be enabled via writes to EESRH and can be disabled via writes to EECRH
  378. * register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers.
  379. * EERH.En = 1: ER.En is enabled to trigger DMA transfers. */
  380. #define CSL_EVETPCC_EERH (0x1024U)
  381. /* Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the
  382. * EER.En bit to be cleared. CPU write of '0' has no effect.. */
  383. #define CSL_EVETPCC_EECR (0x1028U)
  384. /* Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En
  385. * bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.. */
  386. #define CSL_EVETPCC_EECRH (0x102CU)
  387. /* Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the
  388. * EER.En bit to be set. CPU write of '0' has no effect.. */
  389. #define CSL_EVETPCC_EESR (0x1030U)
  390. /* Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit
  391. * causes the EERH.En bit to be set. CPU write of '0' has no effect.. */
  392. #define CSL_EVETPCC_EESRH (0x1034U)
  393. /* Secondary Event Register: The secondary event register is used along with
  394. * the Event Register (ER) to provide information on the state of an Event. En
  395. * = 0 : Event is not currently in the Event Queue. En = 1 : Event is
  396. * currently stored in Event Queue. Event arbiter will not prioritize
  397. * additional events. */
  398. #define CSL_EVETPCC_SER (0x1038U)
  399. /* Secondary Event Register (High Part): The secondary event register is used
  400. * along with the Event Register (ERH) to provide information on the state of
  401. * an Event. En = 0 : Event is not currently in the Event Queue. En = 1 :
  402. * Event is currently stored in Event Queue. Event arbiter will not prioritize
  403. * additional events. */
  404. #define CSL_EVETPCC_SERH (0x103CU)
  405. /* Secondary Event Clear Register: The secondary event clear register is used
  406. * to clear the status of the SER registers. CPU write of '1' to the SECR.En
  407. * bit clears the SER register. CPU write of '0' has no effect. */
  408. #define CSL_EVETPCC_SECR (0x1040U)
  409. /* Secondary Event Clear Register (High Part): The secondary event clear
  410. * register is used to clear the status of the SERH registers. CPU write of
  411. * '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no
  412. * effect. */
  413. #define CSL_EVETPCC_SECRH (0x1044U)
  414. /* Int Enable Register: IER.In is not directly writeable. Interrupts can be
  415. * enabled via writes to IESR and can be disabled via writes to IECR register.
  416. * IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS
  417. * enabled for interrupts. */
  418. #define CSL_EVETPCC_IER (0x1050U)
  419. /* Int Enable Register (High Part): IERH.In is not directly writeable.
  420. * Interrupts can be enabled via writes to IESRH and can be disabled via
  421. * writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for
  422. * interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts. */
  423. #define CSL_EVETPCC_IERH (0x1054U)
  424. /* Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the
  425. * IER.In bit to be cleared. CPU write of '0' has no effect.. */
  426. #define CSL_EVETPCC_IECR (0x1058U)
  427. /* Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit
  428. * causes the IERH.In bit to be cleared. CPU write of '0' has no effect.. */
  429. #define CSL_EVETPCC_IECRH (0x105CU)
  430. /* Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the
  431. * IESR.In bit to be set. CPU write of '0' has no effect.. */
  432. #define CSL_EVETPCC_IESR (0x1060U)
  433. /* Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit
  434. * causes the IESRH.In bit to be set. CPU write of '0' has no effect.. */
  435. #define CSL_EVETPCC_IESRH (0x1064U)
  436. /* Interrupt Pending Register: IPR.In bit is set when a interrupt completion
  437. * code with TCC of N is detected. IPR.In bit is cleared via software by
  438. * writing a '1' to ICR.In bit. */
  439. #define CSL_EVETPCC_IPR (0x1068U)
  440. /* Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt
  441. * completion code with TCC of N is detected. IPRH.In bit is cleared via
  442. * software by writing a '1' to ICRH.In bit. */
  443. #define CSL_EVETPCC_IPRH (0x106CU)
  444. /* Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the
  445. * IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits
  446. * must be cleared before additional interrupts will be asserted by CC. */
  447. #define CSL_EVETPCC_ICR (0x1070U)
  448. /* Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit
  449. * causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All
  450. * IPRH.In bits must be cleared before additional interrupts will be asserted
  451. * by CC. */
  452. #define CSL_EVETPCC_ICRH (0x1074U)
  453. /* Interrupt Eval Register */
  454. #define CSL_EVETPCC_IEVAL (0x1078U)
  455. /* QDMA Event Register: If QER.En bit is set, then the corresponding QDMA
  456. * channel is prioritized vs. other qdma events for submission to the TC.
  457. * QER.En bit is set when a vbus write byte matches the address defined in the
  458. * QCHMAPn register. QER.En bit is cleared when the corresponding event is
  459. * prioritized and serviced. QER.En is also cleared when user writes a '1' to
  460. * the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is
  461. * detected due to user write to QDMA trigger location and QEER register is
  462. * set, then the corresponding bit in the QDMA Event Missed Register is set. */
  463. #define CSL_EVETPCC_QER (0x1080U)
  464. /* QDMA Event Enable Register: Enabled/disabled QDMA address comparator for
  465. * QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be
  466. * enabled via writes to QEESR and can be disabled via writes to QEECR
  467. * register. QEER.En = 1, The corresponding QDMA channel comparator is enabled
  468. * and Events will be recognized and latched in QER.En. QEER.En = 0, The
  469. * corresponding QDMA channel comparator is disabled. Events will not be
  470. * recognized/latched in QER.En. */
  471. #define CSL_EVETPCC_QEER (0x1084U)
  472. /* QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit
  473. * causes the QEER.En bit to be cleared. CPU write of '0' has no effect.. */
  474. #define CSL_EVETPCC_QEECR (0x1088U)
  475. /* QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes
  476. * the QEESR.En bit to be set. CPU write of '0' has no effect.. */
  477. #define CSL_EVETPCC_QEESR (0x108CU)
  478. /* QDMA Secondary Event Register: The QDMA secondary event register is used
  479. * along with the QDMA Event Register (QER) to provide information on the
  480. * state of a QDMA Event. En = 0 : Event is not currently in the Event Queue.
  481. * En = 1 : Event is currently stored in Event Queue. Event arbiter will not
  482. * prioritize additional events. */
  483. #define CSL_EVETPCC_QSER (0x1090U)
  484. /* QDMA Secondary Event Clear Register: The secondary event clear register is
  485. * used to clear the status of the QSER and QER register (note that this is
  486. * slightly different than the SER operation, which does not clear the ER.En
  487. * register). CPU write of '1' to the QSECR.En bit clears the QSER.En and
  488. * QER.En register fields. CPU write of '0' has no effect.. */
  489. #define CSL_EVETPCC_QSECR (0x1094U)
  490. /* Interrupt Eval Register */
  491. #define CSL_EVETPCC_IEVAL_RN(n) (0x2078U + ((n) * (0x200U)))
  492. /* Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit
  493. * causes the IESRH.In bit to be set. CPU write of '0' has no effect.. */
  494. #define CSL_EVETPCC_IESRH_RN(n) (0x2064U + ((n) * (0x200U)))
  495. /* Secondary Event Register: The secondary event register is used along with
  496. * the Event Register (ER) to provide information on the state of an Event. En
  497. * = 0 : Event is not currently in the Event Queue. En = 1 : Event is
  498. * currently stored in Event Queue. Event arbiter will not prioritize
  499. * additional events. */
  500. #define CSL_EVETPCC_SER_RN(n) (0x2038U + ((n) * (0x200U)))
  501. /* Secondary Event Register (High Part): The secondary event register is used
  502. * along with the Event Register (ERH) to provide information on the state of
  503. * an Event. En = 0 : Event is not currently in the Event Queue. En = 1 :
  504. * Event is currently stored in Event Queue. Event arbiter will not prioritize
  505. * additional events. */
  506. #define CSL_EVETPCC_SERH_RN(n) (0x203CU + ((n) * (0x200U)))
  507. /* Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit
  508. * to be set. CPU write of '0' has no effect. */
  509. #define CSL_EVETPCC_ESR_RN(n) (0x2010U + ((n) * (0x200U)))
  510. /* Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the
  511. * EER.En bit to be cleared. CPU write of '0' has no effect.. */
  512. #define CSL_EVETPCC_EECR_RN(n) (0x2028U + ((n) * (0x200U)))
  513. /* Event Register: If ER.En bit is set and the EER.En bit is also set, then
  514. * the corresponding DMA channel is prioritized vs. other pending DMA events
  515. * for submission to the TC. ER.En bit is set when the input event #n
  516. * transitions from inactive (low) to active (high), regardless of the state
  517. * of EER.En bit. ER.En bit is cleared when the corresponding event is
  518. * prioritized and serviced. If the ER.En bit is already set and a new
  519. * inactive to active transition is detected on the input event #n input AND
  520. * the corresponding bit in the EER register is set, then the corresponding
  521. * bit in the Event Missed Register is set. Event N can be cleared via sw by
  522. * writing a '1' to the ECR pseudo-register. */
  523. #define CSL_EVETPCC_ER_RN(n) (0x2000U + ((n) * (0x200U)))
  524. /* Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit
  525. * causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All
  526. * IPRH.In bits must be cleared before additional interrupts will be asserted
  527. * by CC. */
  528. #define CSL_EVETPCC_ICRH_RN(n) (0x2074U + ((n) * (0x200U)))
  529. /* Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En
  530. * bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.. */
  531. #define CSL_EVETPCC_EECRH_RN(n) (0x202CU + ((n) * (0x200U)))
  532. /* Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the
  533. * IESR.In bit to be set. CPU write of '0' has no effect.. */
  534. #define CSL_EVETPCC_IESR_RN(n) (0x2060U + ((n) * (0x200U)))
  535. /* Secondary Event Clear Register: The secondary event clear register is used
  536. * to clear the status of the SER registers. CPU write of '1' to the SECR.En
  537. * bit clears the SER register. CPU write of '0' has no effect. */
  538. #define CSL_EVETPCC_SECR_RN(n) (0x2040U + ((n) * (0x200U)))
  539. /* Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the
  540. * EER.En bit to be set. CPU write of '0' has no effect.. */
  541. #define CSL_EVETPCC_EESR_RN(n) (0x2030U + ((n) * (0x200U)))
  542. /* QDMA Event Register: If QER.En bit is set, then the corresponding QDMA
  543. * channel is prioritized vs. other qdma events for submission to the TC.
  544. * QER.En bit is set when a vbus write byte matches the address defined in the
  545. * QCHMAPn register. QER.En bit is cleared when the corresponding event is
  546. * prioritized and serviced. QER.En is also cleared when user writes a '1' to
  547. * the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is
  548. * detected due to user write to QDMA trigger location and QEER register is
  549. * set, then the corresponding bit in the QDMA Event Missed Register is set. */
  550. #define CSL_EVETPCC_QER_RN(n) (0x2080U + ((n) * (0x200U)))
  551. /* Secondary Event Clear Register (High Part): The secondary event clear
  552. * register is used to clear the status of the SERH registers. CPU write of
  553. * '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no
  554. * effect. */
  555. #define CSL_EVETPCC_SECRH_RN(n) (0x2044U + ((n) * (0x200U)))
  556. /* Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit
  557. * causes the EERH.En bit to be set. CPU write of '0' has no effect.. */
  558. #define CSL_EVETPCC_EESRH_RN(n) (0x2034U + ((n) * (0x200U)))
  559. /* Int Enable Register: IER.In is not directly writeable. Interrupts can be
  560. * enabled via writes to IESR and can be disabled via writes to IECR register.
  561. * IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS
  562. * enabled for interrupts. */
  563. #define CSL_EVETPCC_IER_RN(n) (0x2050U + ((n) * (0x200U)))
  564. /* QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit
  565. * causes the QEER.En bit to be cleared. CPU write of '0' has no effect.. */
  566. #define CSL_EVETPCC_QEECR_RN(n) (0x2088U + ((n) * (0x200U)))
  567. /* Event Enable Register: Enables DMA transfers for ER.En pending events.
  568. * ER.En is set based on externally asserted events (via tpcc_eventN_pi). This
  569. * register has no effect on Chained Event Register (CER) or Event Set
  570. * Register (ESR). Note that if a bit is set in ER.En while EER.En is
  571. * disabled, no action is taken. If EER.En is enabled at a later point (and
  572. * ER.En has not been cleared via SW) then the event will be recognized as a
  573. * valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via
  574. * writes to EESR and can be disabled via writes to EECR register. EER.En = 0:
  575. * ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled
  576. * to trigger DMA transfers. */
  577. #define CSL_EVETPCC_EER_RN(n) (0x2020U + ((n) * (0x200U)))
  578. /* Chained Event Register (High Part): If CERH.En bit is set (regardless of
  579. * state of EERH.En), then the corresponding DMA channel is prioritized vs.
  580. * other pending DMA events for submission to the TC. CERH.En bit is set when
  581. * a chaining completion code is returned from one of the 3PTCs via the
  582. * completion interface, or is generated internally via Early Completion path.
  583. * CERH.En bit is cleared when the corresponding event is prioritized and
  584. * serviced. If the CERH.En bit is already set and the corresponding chaining
  585. * completion code is returned from the TC, then the corresponding bit in the
  586. * Event Missed Register is set. CERH.En cannot be set or cleared via
  587. * software. */
  588. #define CSL_EVETPCC_CERH_RN(n) (0x201CU + ((n) * (0x200U)))
  589. /* QDMA Event Enable Register: Enabled/disabled QDMA address comparator for
  590. * QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be
  591. * enabled via writes to QEESR and can be disabled via writes to QEECR
  592. * register. QEER.En = 1, The corresponding QDMA channel comparator is enabled
  593. * and Events will be recognized and latched in QER.En. QEER.En = 0, The
  594. * corresponding QDMA channel comparator is disabled. Events will not be
  595. * recognized/latched in QER.En. */
  596. #define CSL_EVETPCC_QEER_RN(n) (0x2084U + ((n) * (0x200U)))
  597. /* QDMA Secondary Event Clear Register: The secondary event clear register is
  598. * used to clear the status of the QSER and QER register (note that this is
  599. * slightly different than the SER operation, which does not clear the ER.En
  600. * register). CPU write of '1' to the QSECR.En bit clears the QSER.En and
  601. * QER.En register fields. CPU write of '0' has no effect.. */
  602. #define CSL_EVETPCC_QSECR_RN(n) (0x2094U + ((n) * (0x200U)))
  603. /* Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit
  604. * causes the ERH.En bit to be cleared. CPU write of '0' has no effect. */
  605. #define CSL_EVETPCC_ECRH_RN(n) (0x200CU + ((n) * (0x200U)))
  606. /* Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the
  607. * IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits
  608. * must be cleared before additional interrupts will be asserted by CC. */
  609. #define CSL_EVETPCC_ICR_RN(n) (0x2070U + ((n) * (0x200U)))
  610. /* Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt
  611. * completion code with TCC of N is detected. IPRH.In bit is cleared via
  612. * software by writing a '1' to ICRH.In bit. */
  613. #define CSL_EVETPCC_IPRH_RN(n) (0x206CU + ((n) * (0x200U)))
  614. /* Chained Event Register: If CER.En bit is set (regardless of state of
  615. * EER.En), then the corresponding DMA channel is prioritized vs. other
  616. * pending DMA events for submission to the TC. CER.En bit is set when a
  617. * chaining completion code is returned from one of the 3PTCs via the
  618. * completion interface, or is generated internally via Early Completion path.
  619. * CER.En bit is cleared when the corresponding event is prioritized and
  620. * serviced. If the CER.En bit is already set and the corresponding chaining
  621. * completion code is returned from the TC, then the corresponding bit in the
  622. * Event Missed Register is set. CER.En cannot be set or cleared via software. */
  623. #define CSL_EVETPCC_CER_RN(n) (0x2018U + ((n) * (0x200U)))
  624. /* Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit
  625. * causes the IERH.In bit to be cleared. CPU write of '0' has no effect.. */
  626. #define CSL_EVETPCC_IECRH_RN(n) (0x205CU + ((n) * (0x200U)))
  627. /* Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the
  628. * IER.In bit to be cleared. CPU write of '0' has no effect.. */
  629. #define CSL_EVETPCC_IECR_RN(n) (0x2058U + ((n) * (0x200U)))
  630. /* QDMA Secondary Event Register: The QDMA secondary event register is used
  631. * along with the QDMA Event Register (QER) to provide information on the
  632. * state of a QDMA Event. En = 0 : Event is not currently in the Event Queue.
  633. * En = 1 : Event is currently stored in Event Queue. Event arbiter will not
  634. * prioritize additional events. */
  635. #define CSL_EVETPCC_QSER_RN(n) (0x2090U + ((n) * (0x200U)))
  636. /* Int Enable Register (High Part): IERH.In is not directly writeable.
  637. * Interrupts can be enabled via writes to IESRH and can be disabled via
  638. * writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for
  639. * interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts. */
  640. #define CSL_EVETPCC_IERH_RN(n) (0x2054U + ((n) * (0x200U)))
  641. /* Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En
  642. * bit to be cleared. CPU write of '0' has no effect. */
  643. #define CSL_EVETPCC_ECR_RN(n) (0x2008U + ((n) * (0x200U)))
  644. /* Event Enable Register (High Part): Enables DMA transfers for ERH.En pending
  645. * events. ERH.En is set based on externally asserted events (via
  646. * tpcc_eventN_pi). This register has no effect on Chained Event Register
  647. * (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En
  648. * while EERH.En is disabled, no action is taken. If EERH.En is enabled at a
  649. * later point (and ERH.En has not been cleared via SW) then the event will be
  650. * recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events
  651. * can be enabled via writes to EESRH and can be disabled via writes to EECRH
  652. * register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers.
  653. * EERH.En = 1: ER.En is enabled to trigger DMA transfers. */
  654. #define CSL_EVETPCC_EERH_RN(n) (0x2024U + ((n) * (0x200U)))
  655. /* Interrupt Pending Register: IPR.In bit is set when a interrupt completion
  656. * code with TCC of N is detected. IPR.In bit is cleared via software by
  657. * writing a '1' to ICR.In bit. */
  658. #define CSL_EVETPCC_IPR_RN(n) (0x2068U + ((n) * (0x200U)))
  659. /* Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes
  660. * the ERH.En bit to be set. CPU write of '0' has no effect. */
  661. #define CSL_EVETPCC_ESRH_RN(n) (0x2014U + ((n) * (0x200U)))
  662. /* QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes
  663. * the QEESR.En bit to be set. CPU write of '0' has no effect.. */
  664. #define CSL_EVETPCC_QEESR_RN(n) (0x208CU + ((n) * (0x200U)))
  665. /* Event Register (High Part): If ERH.En bit is set and the EERH.En bit is
  666. * also set, then the corresponding DMA channel is prioritized vs. other
  667. * pending DMA events for submission to the TC. ERH.En bit is set when the
  668. * input event #n transitions from inactive (low) to active (high), regardless
  669. * of the state of EERH.En bit. ER.En bit is cleared when the corresponding
  670. * event is prioritized and serviced. If the ERH.En bit is already set and a
  671. * new inactive to active transition is detected on the input event #n input
  672. * AND the corresponding bit in the EERH register is set, then the
  673. * corresponding bit in the Event Missed Register is set. Event N can be
  674. * cleared via sw by writing a '1' to the ECRH pseudo-register. */
  675. #define CSL_EVETPCC_ERH_RN(n) (0x2004U + ((n) * (0x200U)))
  676. /* Options Parameter */
  677. #define CSL_EVETPCC_OPT(n) (0x4000U + ((n) * (0x20U)))
  678. /* Source Address */
  679. #define CSL_EVETPCC_SRC(n) (0x4004U + ((n) * (0x20U)))
  680. /* A and B byte count */
  681. #define CSL_EVETPCC_ABCNT(n) (0x4008U + ((n) * (0x20U)))
  682. /* BIDX */
  683. #define CSL_EVETPCC_BIDX(n) (0x4010U + ((n) * (0x20U)))
  684. /* Link and Reload parameters */
  685. #define CSL_EVETPCC_LNK(n) (0x4014U + ((n) * (0x20U)))
  686. /* CIDX */
  687. #define CSL_EVETPCC_CIDX(n) (0x4018U + ((n) * (0x20U)))
  688. /* C byte count */
  689. #define CSL_EVETPCC_CCNT(n) (0x401CU + ((n) * (0x20U)))
  690. /* Destination Address */
  691. #define CSL_EVETPCC_DST(n) (0x400CU + ((n) * (0x20U)))
  692. /**************************************************************************
  693. * Field Definition Macros
  694. **************************************************************************/
  695. /* PID */
  696. #define CSL_EVETPCC_PID_MINOR_MASK (0x0000003FU)
  697. #define CSL_EVETPCC_PID_MINOR_SHIFT (0U)
  698. #define CSL_EVETPCC_PID_MINOR_RESETVAL (0x00000000U)
  699. #define CSL_EVETPCC_PID_MINOR_MAX (0x0000003fU)
  700. #define CSL_EVETPCC_PID_CUSTOM_MASK (0x000000C0U)
  701. #define CSL_EVETPCC_PID_CUSTOM_SHIFT (6U)
  702. #define CSL_EVETPCC_PID_CUSTOM_RESETVAL (0x00000000U)
  703. #define CSL_EVETPCC_PID_CUSTOM_MAX (0x00000003U)
  704. #define CSL_EVETPCC_PID_MAJOR_MASK (0x00000700U)
  705. #define CSL_EVETPCC_PID_MAJOR_SHIFT (8U)
  706. #define CSL_EVETPCC_PID_MAJOR_RESETVAL (0x00000003U)
  707. #define CSL_EVETPCC_PID_MAJOR_MAX (0x00000007U)
  708. #define CSL_EVETPCC_PID_RTL_MASK (0x0000F800U)
  709. #define CSL_EVETPCC_PID_RTL_SHIFT (11U)
  710. #define CSL_EVETPCC_PID_RTL_RESETVAL (0x00000000U)
  711. #define CSL_EVETPCC_PID_RTL_MAX (0x0000001fU)
  712. #define CSL_EVETPCC_PID_FUNC_MASK (0x0FFF0000U)
  713. #define CSL_EVETPCC_PID_FUNC_SHIFT (16U)
  714. #define CSL_EVETPCC_PID_FUNC_RESETVAL (0x00000001U)
  715. #define CSL_EVETPCC_PID_FUNC_MAX (0x00000fffU)
  716. #define CSL_EVETPCC_PID_SCHEME_MASK (0xC0000000U)
  717. #define CSL_EVETPCC_PID_SCHEME_SHIFT (30U)
  718. #define CSL_EVETPCC_PID_SCHEME_RESETVAL (0x00000001U)
  719. #define CSL_EVETPCC_PID_SCHEME_MAX (0x00000003U)
  720. #define CSL_EVETPCC_PID_RESETVAL (0x40010300U)
  721. /* CCCFG */
  722. #define CSL_EVETPCC_CCCFG_NUMTC_MASK (0x00070000U)
  723. #define CSL_EVETPCC_CCCFG_NUMTC_SHIFT (16U)
  724. #define CSL_EVETPCC_CCCFG_NUMTC_RESETVAL (0x00000001U)
  725. #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC7 (0x00000006U)
  726. #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC4 (0x00000003U)
  727. #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC1 (0x00000000U)
  728. #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC6 (0x00000005U)
  729. #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC8 (0x00000007U)
  730. #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC5 (0x00000004U)
  731. #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC3 (0x00000002U)
  732. #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC2 (0x00000001U)
  733. #define CSL_EVETPCC_CCCFG_NUMREGN_MASK (0x00300000U)
  734. #define CSL_EVETPCC_CCCFG_NUMREGN_SHIFT (20U)
  735. #define CSL_EVETPCC_CCCFG_NUMREGN_RESETVAL (0x00000003U)
  736. #define CSL_EVETPCC_CCCFG_NUMREGN_NUMREG4 (0x00000002U)
  737. #define CSL_EVETPCC_CCCFG_NUMREGN_NUMREG8 (0x00000003U)
  738. #define CSL_EVETPCC_CCCFG_NUMREGN_NUMREG0 (0x00000000U)
  739. #define CSL_EVETPCC_CCCFG_NUMREGN_NUMREG2 (0x00000001U)
  740. #define CSL_EVETPCC_CCCFG_NUMINTCH_MASK (0x00000700U)
  741. #define CSL_EVETPCC_CCCFG_NUMINTCH_SHIFT (8U)
  742. #define CSL_EVETPCC_CCCFG_NUMINTCH_RESETVAL (0x00000004U)
  743. #define CSL_EVETPCC_CCCFG_NUMINTCH_NUMINTCH32 (0x00000003U)
  744. #define CSL_EVETPCC_CCCFG_NUMINTCH_NUMINTCH64 (0x00000004U)
  745. #define CSL_EVETPCC_CCCFG_NUMINTCH_NUMINTCH16 (0x00000002U)
  746. #define CSL_EVETPCC_CCCFG_NUMINTCH_NUMINTCH8 (0x00000001U)
  747. #define CSL_EVETPCC_CCCFG_NUMPAENTRY_MASK (0x00007000U)
  748. #define CSL_EVETPCC_CCCFG_NUMPAENTRY_SHIFT (12U)
  749. #define CSL_EVETPCC_CCCFG_NUMPAENTRY_RESETVAL (0x00000003U)
  750. #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES16 (0x00000000U)
  751. #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES32 (0x00000001U)
  752. #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES64 (0x00000002U)
  753. #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES128 (0x00000003U)
  754. #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES256 (0x00000004U)
  755. #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES512 (0x00000005U)
  756. #define CSL_EVETPCC_CCCFG_CHMAPEXIST_MASK (0x01000000U)
  757. #define CSL_EVETPCC_CCCFG_CHMAPEXIST_SHIFT (24U)
  758. #define CSL_EVETPCC_CCCFG_CHMAPEXIST_RESETVAL (0x00000001U)
  759. #define CSL_EVETPCC_CCCFG_CHMAPEXIST_MAX (0x00000001U)
  760. #define CSL_EVETPCC_CCCFG_MPEXIST_MASK (0x02000000U)
  761. #define CSL_EVETPCC_CCCFG_MPEXIST_SHIFT (25U)
  762. #define CSL_EVETPCC_CCCFG_MPEXIST_RESETVAL (0x00000001U)
  763. #define CSL_EVETPCC_CCCFG_MPEXIST_MAX (0x00000001U)
  764. #define CSL_EVETPCC_CCCFG_NUMDMACH_MASK (0x00000007U)
  765. #define CSL_EVETPCC_CCCFG_NUMDMACH_SHIFT (0U)
  766. #define CSL_EVETPCC_CCCFG_NUMDMACH_RESETVAL (0x00000005U)
  767. #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH4 (0x00000001U)
  768. #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH32 (0x00000004U)
  769. #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH8 (0x00000002U)
  770. #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH64 (0x00000005U)
  771. #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH16 (0x00000003U)
  772. #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH0 (0x00000000U)
  773. #define CSL_EVETPCC_CCCFG_NUMQDMACH_MASK (0x00000070U)
  774. #define CSL_EVETPCC_CCCFG_NUMQDMACH_SHIFT (4U)
  775. #define CSL_EVETPCC_CCCFG_NUMQDMACH_RESETVAL (0x00000004U)
  776. #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH4 (0x00000002U)
  777. #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH8 (0x00000004U)
  778. #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH6 (0x00000003U)
  779. #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH0 (0x00000000U)
  780. #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH2 (0x00000001U)
  781. #define CSL_EVETPCC_CCCFG_RESETVAL (0x03313445U)
  782. /* CLKGDIS */
  783. #define CSL_EVETPCC_CLKGDIS_CLKGDIS_MASK (0x00000001U)
  784. #define CSL_EVETPCC_CLKGDIS_CLKGDIS_SHIFT (0U)
  785. #define CSL_EVETPCC_CLKGDIS_CLKGDIS_RESETVAL (0x00000000U)
  786. #define CSL_EVETPCC_CLKGDIS_CLKGDIS_MAX (0x00000001U)
  787. #define CSL_EVETPCC_CLKGDIS_RESETVAL (0x00000000U)
  788. /* DCHMAPN */
  789. #define CSL_EVETPCC_DCHMAPN_PAENTRY_MASK (0x00003FE0U)
  790. #define CSL_EVETPCC_DCHMAPN_PAENTRY_SHIFT (5U)
  791. #define CSL_EVETPCC_DCHMAPN_PAENTRY_RESETVAL (0x00000000U)
  792. #define CSL_EVETPCC_DCHMAPN_PAENTRY_MAX (0x000001ffU)
  793. #define CSL_EVETPCC_DCHMAPN_RESETVAL (0x00000000U)
  794. /* QCHMAPN */
  795. #define CSL_EVETPCC_QCHMAPN_PAENTRY_MASK (0x00003FE0U)
  796. #define CSL_EVETPCC_QCHMAPN_PAENTRY_SHIFT (5U)
  797. #define CSL_EVETPCC_QCHMAPN_PAENTRY_RESETVAL (0x00000000U)
  798. #define CSL_EVETPCC_QCHMAPN_PAENTRY_MAX (0x000001ffU)
  799. #define CSL_EVETPCC_QCHMAPN_TRWORD_MASK (0x0000001CU)
  800. #define CSL_EVETPCC_QCHMAPN_TRWORD_SHIFT (2U)
  801. #define CSL_EVETPCC_QCHMAPN_TRWORD_RESETVAL (0x00000000U)
  802. #define CSL_EVETPCC_QCHMAPN_TRWORD_MAX (0x00000007U)
  803. #define CSL_EVETPCC_QCHMAPN_RESETVAL (0x00000000U)
  804. /* DMAQNUMN */
  805. #define CSL_EVETPCC_DMAQNUMN_E6_MASK (0x07000000U)
  806. #define CSL_EVETPCC_DMAQNUMN_E6_SHIFT (24U)
  807. #define CSL_EVETPCC_DMAQNUMN_E6_RESETVAL (0x00000000U)
  808. #define CSL_EVETPCC_DMAQNUMN_E6_Q3 (0x00000003U)
  809. #define CSL_EVETPCC_DMAQNUMN_E6_Q7 (0x00000007U)
  810. #define CSL_EVETPCC_DMAQNUMN_E6_Q4 (0x00000004U)
  811. #define CSL_EVETPCC_DMAQNUMN_E6_Q6 (0x00000006U)
  812. #define CSL_EVETPCC_DMAQNUMN_E6_Q1 (0x00000001U)
  813. #define CSL_EVETPCC_DMAQNUMN_E6_Q0 (0x00000000U)
  814. #define CSL_EVETPCC_DMAQNUMN_E6_Q5 (0x00000005U)
  815. #define CSL_EVETPCC_DMAQNUMN_E6_Q2 (0x00000002U)
  816. #define CSL_EVETPCC_DMAQNUMN_E2_MASK (0x00000700U)
  817. #define CSL_EVETPCC_DMAQNUMN_E2_SHIFT (8U)
  818. #define CSL_EVETPCC_DMAQNUMN_E2_RESETVAL (0x00000000U)
  819. #define CSL_EVETPCC_DMAQNUMN_E2_Q4 (0x00000004U)
  820. #define CSL_EVETPCC_DMAQNUMN_E2_Q7 (0x00000007U)
  821. #define CSL_EVETPCC_DMAQNUMN_E2_Q1 (0x00000001U)
  822. #define CSL_EVETPCC_DMAQNUMN_E2_Q2 (0x00000002U)
  823. #define CSL_EVETPCC_DMAQNUMN_E2_Q5 (0x00000005U)
  824. #define CSL_EVETPCC_DMAQNUMN_E2_Q0 (0x00000000U)
  825. #define CSL_EVETPCC_DMAQNUMN_E2_Q3 (0x00000003U)
  826. #define CSL_EVETPCC_DMAQNUMN_E2_Q6 (0x00000006U)
  827. #define CSL_EVETPCC_DMAQNUMN_E1_MASK (0x00000070U)
  828. #define CSL_EVETPCC_DMAQNUMN_E1_SHIFT (4U)
  829. #define CSL_EVETPCC_DMAQNUMN_E1_RESETVAL (0x00000000U)
  830. #define CSL_EVETPCC_DMAQNUMN_E1_Q4 (0x00000004U)
  831. #define CSL_EVETPCC_DMAQNUMN_E1_Q3 (0x00000003U)
  832. #define CSL_EVETPCC_DMAQNUMN_E1_Q6 (0x00000006U)
  833. #define CSL_EVETPCC_DMAQNUMN_E1_Q0 (0x00000000U)
  834. #define CSL_EVETPCC_DMAQNUMN_E1_Q1 (0x00000001U)
  835. #define CSL_EVETPCC_DMAQNUMN_E1_Q7 (0x00000007U)
  836. #define CSL_EVETPCC_DMAQNUMN_E1_Q2 (0x00000002U)
  837. #define CSL_EVETPCC_DMAQNUMN_E1_Q5 (0x00000005U)
  838. #define CSL_EVETPCC_DMAQNUMN_E4_MASK (0x00070000U)
  839. #define CSL_EVETPCC_DMAQNUMN_E4_SHIFT (16U)
  840. #define CSL_EVETPCC_DMAQNUMN_E4_RESETVAL (0x00000000U)
  841. #define CSL_EVETPCC_DMAQNUMN_E4_Q1 (0x00000001U)
  842. #define CSL_EVETPCC_DMAQNUMN_E4_Q0 (0x00000000U)
  843. #define CSL_EVETPCC_DMAQNUMN_E4_Q4 (0x00000004U)
  844. #define CSL_EVETPCC_DMAQNUMN_E4_Q2 (0x00000002U)
  845. #define CSL_EVETPCC_DMAQNUMN_E4_Q5 (0x00000005U)
  846. #define CSL_EVETPCC_DMAQNUMN_E4_Q7 (0x00000007U)
  847. #define CSL_EVETPCC_DMAQNUMN_E4_Q3 (0x00000003U)
  848. #define CSL_EVETPCC_DMAQNUMN_E4_Q6 (0x00000006U)
  849. #define CSL_EVETPCC_DMAQNUMN_E3_MASK (0x00007000U)
  850. #define CSL_EVETPCC_DMAQNUMN_E3_SHIFT (12U)
  851. #define CSL_EVETPCC_DMAQNUMN_E3_RESETVAL (0x00000000U)
  852. #define CSL_EVETPCC_DMAQNUMN_E3_Q2 (0x00000002U)
  853. #define CSL_EVETPCC_DMAQNUMN_E3_Q5 (0x00000005U)
  854. #define CSL_EVETPCC_DMAQNUMN_E3_Q0 (0x00000000U)
  855. #define CSL_EVETPCC_DMAQNUMN_E3_Q4 (0x00000004U)
  856. #define CSL_EVETPCC_DMAQNUMN_E3_Q3 (0x00000003U)
  857. #define CSL_EVETPCC_DMAQNUMN_E3_Q6 (0x00000006U)
  858. #define CSL_EVETPCC_DMAQNUMN_E3_Q7 (0x00000007U)
  859. #define CSL_EVETPCC_DMAQNUMN_E3_Q1 (0x00000001U)
  860. #define CSL_EVETPCC_DMAQNUMN_E5_MASK (0x00700000U)
  861. #define CSL_EVETPCC_DMAQNUMN_E5_SHIFT (20U)
  862. #define CSL_EVETPCC_DMAQNUMN_E5_RESETVAL (0x00000000U)
  863. #define CSL_EVETPCC_DMAQNUMN_E5_Q7 (0x00000007U)
  864. #define CSL_EVETPCC_DMAQNUMN_E5_Q1 (0x00000001U)
  865. #define CSL_EVETPCC_DMAQNUMN_E5_Q2 (0x00000002U)
  866. #define CSL_EVETPCC_DMAQNUMN_E5_Q5 (0x00000005U)
  867. #define CSL_EVETPCC_DMAQNUMN_E5_Q3 (0x00000003U)
  868. #define CSL_EVETPCC_DMAQNUMN_E5_Q4 (0x00000004U)
  869. #define CSL_EVETPCC_DMAQNUMN_E5_Q6 (0x00000006U)
  870. #define CSL_EVETPCC_DMAQNUMN_E5_Q0 (0x00000000U)
  871. #define CSL_EVETPCC_DMAQNUMN_E0_MASK (0x00000007U)
  872. #define CSL_EVETPCC_DMAQNUMN_E0_SHIFT (0U)
  873. #define CSL_EVETPCC_DMAQNUMN_E0_RESETVAL (0x00000000U)
  874. #define CSL_EVETPCC_DMAQNUMN_E0_Q5 (0x00000005U)
  875. #define CSL_EVETPCC_DMAQNUMN_E0_Q4 (0x00000004U)
  876. #define CSL_EVETPCC_DMAQNUMN_E0_Q6 (0x00000006U)
  877. #define CSL_EVETPCC_DMAQNUMN_E0_Q1 (0x00000001U)
  878. #define CSL_EVETPCC_DMAQNUMN_E0_Q0 (0x00000000U)
  879. #define CSL_EVETPCC_DMAQNUMN_E0_Q3 (0x00000003U)
  880. #define CSL_EVETPCC_DMAQNUMN_E0_Q2 (0x00000002U)
  881. #define CSL_EVETPCC_DMAQNUMN_E0_Q7 (0x00000007U)
  882. #define CSL_EVETPCC_DMAQNUMN_E7_MASK (0x70000000U)
  883. #define CSL_EVETPCC_DMAQNUMN_E7_SHIFT (28U)
  884. #define CSL_EVETPCC_DMAQNUMN_E7_RESETVAL (0x00000000U)
  885. #define CSL_EVETPCC_DMAQNUMN_E7_Q3 (0x00000003U)
  886. #define CSL_EVETPCC_DMAQNUMN_E7_Q7 (0x00000007U)
  887. #define CSL_EVETPCC_DMAQNUMN_E7_Q6 (0x00000006U)
  888. #define CSL_EVETPCC_DMAQNUMN_E7_Q1 (0x00000001U)
  889. #define CSL_EVETPCC_DMAQNUMN_E7_Q0 (0x00000000U)
  890. #define CSL_EVETPCC_DMAQNUMN_E7_Q4 (0x00000004U)
  891. #define CSL_EVETPCC_DMAQNUMN_E7_Q2 (0x00000002U)
  892. #define CSL_EVETPCC_DMAQNUMN_E7_Q5 (0x00000005U)
  893. #define CSL_EVETPCC_DMAQNUMN_RESETVAL (0x00000000U)
  894. /* QDMAQNUM */
  895. #define CSL_EVETPCC_QDMAQNUM_E5_MASK (0x00700000U)
  896. #define CSL_EVETPCC_QDMAQNUM_E5_SHIFT (20U)
  897. #define CSL_EVETPCC_QDMAQNUM_E5_RESETVAL (0x00000000U)
  898. #define CSL_EVETPCC_QDMAQNUM_E5_Q7 (0x00000007U)
  899. #define CSL_EVETPCC_QDMAQNUM_E5_Q0 (0x00000000U)
  900. #define CSL_EVETPCC_QDMAQNUM_E5_Q3 (0x00000003U)
  901. #define CSL_EVETPCC_QDMAQNUM_E5_Q2 (0x00000002U)
  902. #define CSL_EVETPCC_QDMAQNUM_E5_Q6 (0x00000006U)
  903. #define CSL_EVETPCC_QDMAQNUM_E5_Q4 (0x00000004U)
  904. #define CSL_EVETPCC_QDMAQNUM_E5_Q5 (0x00000005U)
  905. #define CSL_EVETPCC_QDMAQNUM_E5_Q1 (0x00000001U)
  906. #define CSL_EVETPCC_QDMAQNUM_E6_MASK (0x07000000U)
  907. #define CSL_EVETPCC_QDMAQNUM_E6_SHIFT (24U)
  908. #define CSL_EVETPCC_QDMAQNUM_E6_RESETVAL (0x00000000U)
  909. #define CSL_EVETPCC_QDMAQNUM_E6_Q1 (0x00000001U)
  910. #define CSL_EVETPCC_QDMAQNUM_E6_Q5 (0x00000005U)
  911. #define CSL_EVETPCC_QDMAQNUM_E6_Q0 (0x00000000U)
  912. #define CSL_EVETPCC_QDMAQNUM_E6_Q4 (0x00000004U)
  913. #define CSL_EVETPCC_QDMAQNUM_E6_Q7 (0x00000007U)
  914. #define CSL_EVETPCC_QDMAQNUM_E6_Q2 (0x00000002U)
  915. #define CSL_EVETPCC_QDMAQNUM_E6_Q6 (0x00000006U)
  916. #define CSL_EVETPCC_QDMAQNUM_E6_Q3 (0x00000003U)
  917. #define CSL_EVETPCC_QDMAQNUM_E7_MASK (0x70000000U)
  918. #define CSL_EVETPCC_QDMAQNUM_E7_SHIFT (28U)
  919. #define CSL_EVETPCC_QDMAQNUM_E7_RESETVAL (0x00000000U)
  920. #define CSL_EVETPCC_QDMAQNUM_E7_Q0 (0x00000000U)
  921. #define CSL_EVETPCC_QDMAQNUM_E7_Q4 (0x00000004U)
  922. #define CSL_EVETPCC_QDMAQNUM_E7_Q5 (0x00000005U)
  923. #define CSL_EVETPCC_QDMAQNUM_E7_Q3 (0x00000003U)
  924. #define CSL_EVETPCC_QDMAQNUM_E7_Q2 (0x00000002U)
  925. #define CSL_EVETPCC_QDMAQNUM_E7_Q1 (0x00000001U)
  926. #define CSL_EVETPCC_QDMAQNUM_E7_Q6 (0x00000006U)
  927. #define CSL_EVETPCC_QDMAQNUM_E7_Q7 (0x00000007U)
  928. #define CSL_EVETPCC_QDMAQNUM_E4_MASK (0x00070000U)
  929. #define CSL_EVETPCC_QDMAQNUM_E4_SHIFT (16U)
  930. #define CSL_EVETPCC_QDMAQNUM_E4_RESETVAL (0x00000000U)
  931. #define CSL_EVETPCC_QDMAQNUM_E4_Q0 (0x00000000U)
  932. #define CSL_EVETPCC_QDMAQNUM_E4_Q4 (0x00000004U)
  933. #define CSL_EVETPCC_QDMAQNUM_E4_Q6 (0x00000006U)
  934. #define CSL_EVETPCC_QDMAQNUM_E4_Q3 (0x00000003U)
  935. #define CSL_EVETPCC_QDMAQNUM_E4_Q1 (0x00000001U)
  936. #define CSL_EVETPCC_QDMAQNUM_E4_Q2 (0x00000002U)
  937. #define CSL_EVETPCC_QDMAQNUM_E4_Q5 (0x00000005U)
  938. #define CSL_EVETPCC_QDMAQNUM_E4_Q7 (0x00000007U)
  939. #define CSL_EVETPCC_QDMAQNUM_E3_MASK (0x00007000U)
  940. #define CSL_EVETPCC_QDMAQNUM_E3_SHIFT (12U)
  941. #define CSL_EVETPCC_QDMAQNUM_E3_RESETVAL (0x00000000U)
  942. #define CSL_EVETPCC_QDMAQNUM_E3_Q5 (0x00000005U)
  943. #define CSL_EVETPCC_QDMAQNUM_E3_Q7 (0x00000007U)
  944. #define CSL_EVETPCC_QDMAQNUM_E3_Q4 (0x00000004U)
  945. #define CSL_EVETPCC_QDMAQNUM_E3_Q6 (0x00000006U)
  946. #define CSL_EVETPCC_QDMAQNUM_E3_Q3 (0x00000003U)
  947. #define CSL_EVETPCC_QDMAQNUM_E3_Q2 (0x00000002U)
  948. #define CSL_EVETPCC_QDMAQNUM_E3_Q1 (0x00000001U)
  949. #define CSL_EVETPCC_QDMAQNUM_E3_Q0 (0x00000000U)
  950. #define CSL_EVETPCC_QDMAQNUM_E1_MASK (0x00000070U)
  951. #define CSL_EVETPCC_QDMAQNUM_E1_SHIFT (4U)
  952. #define CSL_EVETPCC_QDMAQNUM_E1_RESETVAL (0x00000000U)
  953. #define CSL_EVETPCC_QDMAQNUM_E1_Q3 (0x00000003U)
  954. #define CSL_EVETPCC_QDMAQNUM_E1_Q5 (0x00000005U)
  955. #define CSL_EVETPCC_QDMAQNUM_E1_Q7 (0x00000007U)
  956. #define CSL_EVETPCC_QDMAQNUM_E1_Q1 (0x00000001U)
  957. #define CSL_EVETPCC_QDMAQNUM_E1_Q6 (0x00000006U)
  958. #define CSL_EVETPCC_QDMAQNUM_E1_Q0 (0x00000000U)
  959. #define CSL_EVETPCC_QDMAQNUM_E1_Q4 (0x00000004U)
  960. #define CSL_EVETPCC_QDMAQNUM_E1_Q2 (0x00000002U)
  961. #define CSL_EVETPCC_QDMAQNUM_E0_MASK (0x00000007U)
  962. #define CSL_EVETPCC_QDMAQNUM_E0_SHIFT (0U)
  963. #define CSL_EVETPCC_QDMAQNUM_E0_RESETVAL (0x00000000U)
  964. #define CSL_EVETPCC_QDMAQNUM_E0_Q1 (0x00000001U)
  965. #define CSL_EVETPCC_QDMAQNUM_E0_Q6 (0x00000006U)
  966. #define CSL_EVETPCC_QDMAQNUM_E0_Q3 (0x00000003U)
  967. #define CSL_EVETPCC_QDMAQNUM_E0_Q4 (0x00000004U)
  968. #define CSL_EVETPCC_QDMAQNUM_E0_Q7 (0x00000007U)
  969. #define CSL_EVETPCC_QDMAQNUM_E0_Q2 (0x00000002U)
  970. #define CSL_EVETPCC_QDMAQNUM_E0_Q5 (0x00000005U)
  971. #define CSL_EVETPCC_QDMAQNUM_E0_Q0 (0x00000000U)
  972. #define CSL_EVETPCC_QDMAQNUM_E2_MASK (0x00000700U)
  973. #define CSL_EVETPCC_QDMAQNUM_E2_SHIFT (8U)
  974. #define CSL_EVETPCC_QDMAQNUM_E2_RESETVAL (0x00000000U)
  975. #define CSL_EVETPCC_QDMAQNUM_E2_Q5 (0x00000005U)
  976. #define CSL_EVETPCC_QDMAQNUM_E2_Q7 (0x00000007U)
  977. #define CSL_EVETPCC_QDMAQNUM_E2_Q0 (0x00000000U)
  978. #define CSL_EVETPCC_QDMAQNUM_E2_Q1 (0x00000001U)
  979. #define CSL_EVETPCC_QDMAQNUM_E2_Q2 (0x00000002U)
  980. #define CSL_EVETPCC_QDMAQNUM_E2_Q4 (0x00000004U)
  981. #define CSL_EVETPCC_QDMAQNUM_E2_Q6 (0x00000006U)
  982. #define CSL_EVETPCC_QDMAQNUM_E2_Q3 (0x00000003U)
  983. #define CSL_EVETPCC_QDMAQNUM_RESETVAL (0x00000000U)
  984. /* QUETCMAP */
  985. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_MASK (0x00000007U)
  986. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_SHIFT (0U)
  987. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_RESETVAL (0x00000000U)
  988. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC0 (0x00000000U)
  989. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC1 (0x00000001U)
  990. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC2 (0x00000002U)
  991. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC3 (0x00000003U)
  992. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC4 (0x00000004U)
  993. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC5 (0x00000005U)
  994. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC6 (0x00000006U)
  995. #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC7 (0x00000007U)
  996. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_MASK (0x00000070U)
  997. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_SHIFT (4U)
  998. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_RESETVAL (0x00000001U)
  999. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC1 (0x00000001U)
  1000. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC0 (0x00000000U)
  1001. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC6 (0x00000006U)
  1002. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC2 (0x00000002U)
  1003. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC3 (0x00000003U)
  1004. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC5 (0x00000005U)
  1005. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC7 (0x00000007U)
  1006. #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC4 (0x00000004U)
  1007. #define CSL_EVETPCC_QUETCMAP_RESETVAL (0x00000010U)
  1008. /* QUEPRI */
  1009. #define CSL_EVETPCC_QUEPRI_PRIQ0_MASK (0x00000007U)
  1010. #define CSL_EVETPCC_QUEPRI_PRIQ0_SHIFT (0U)
  1011. #define CSL_EVETPCC_QUEPRI_PRIQ0_RESETVAL (0x00000000U)
  1012. #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY7 (0x00000007U)
  1013. #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY6 (0x00000006U)
  1014. #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY5 (0x00000005U)
  1015. #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY4 (0x00000004U)
  1016. #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY3 (0x00000003U)
  1017. #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY2 (0x00000002U)
  1018. #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY1 (0x00000001U)
  1019. #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY0 (0x00000000U)
  1020. #define CSL_EVETPCC_QUEPRI_PRIQ1_MASK (0x00000070U)
  1021. #define CSL_EVETPCC_QUEPRI_PRIQ1_SHIFT (4U)
  1022. #define CSL_EVETPCC_QUEPRI_PRIQ1_RESETVAL (0x00000000U)
  1023. #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY7 (0x00000007U)
  1024. #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY6 (0x00000006U)
  1025. #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY0 (0x00000000U)
  1026. #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY1 (0x00000001U)
  1027. #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY3 (0x00000003U)
  1028. #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY4 (0x00000004U)
  1029. #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY2 (0x00000002U)
  1030. #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY5 (0x00000005U)
  1031. #define CSL_EVETPCC_QUEPRI_RESETVAL (0x00000000U)
  1032. /* EMR */
  1033. #define CSL_EVETPCC_EMR_E0_MASK (0x00000001U)
  1034. #define CSL_EVETPCC_EMR_E0_SHIFT (0U)
  1035. #define CSL_EVETPCC_EMR_E0_RESETVAL (0x00000000U)
  1036. #define CSL_EVETPCC_EMR_E0_MAX (0x00000001U)
  1037. #define CSL_EVETPCC_EMR_E1_MASK (0x00000002U)
  1038. #define CSL_EVETPCC_EMR_E1_SHIFT (1U)
  1039. #define CSL_EVETPCC_EMR_E1_RESETVAL (0x00000000U)
  1040. #define CSL_EVETPCC_EMR_E1_MAX (0x00000001U)
  1041. #define CSL_EVETPCC_EMR_E2_MASK (0x00000004U)
  1042. #define CSL_EVETPCC_EMR_E2_SHIFT (2U)
  1043. #define CSL_EVETPCC_EMR_E2_RESETVAL (0x00000000U)
  1044. #define CSL_EVETPCC_EMR_E2_MAX (0x00000001U)
  1045. #define CSL_EVETPCC_EMR_E3_MASK (0x00000008U)
  1046. #define CSL_EVETPCC_EMR_E3_SHIFT (3U)
  1047. #define CSL_EVETPCC_EMR_E3_RESETVAL (0x00000000U)
  1048. #define CSL_EVETPCC_EMR_E3_MAX (0x00000001U)
  1049. #define CSL_EVETPCC_EMR_E4_MASK (0x00000010U)
  1050. #define CSL_EVETPCC_EMR_E4_SHIFT (4U)
  1051. #define CSL_EVETPCC_EMR_E4_RESETVAL (0x00000000U)
  1052. #define CSL_EVETPCC_EMR_E4_MAX (0x00000001U)
  1053. #define CSL_EVETPCC_EMR_E5_MASK (0x00000020U)
  1054. #define CSL_EVETPCC_EMR_E5_SHIFT (5U)
  1055. #define CSL_EVETPCC_EMR_E5_RESETVAL (0x00000000U)
  1056. #define CSL_EVETPCC_EMR_E5_MAX (0x00000001U)
  1057. #define CSL_EVETPCC_EMR_E6_MASK (0x00000040U)
  1058. #define CSL_EVETPCC_EMR_E6_SHIFT (6U)
  1059. #define CSL_EVETPCC_EMR_E6_RESETVAL (0x00000000U)
  1060. #define CSL_EVETPCC_EMR_E6_MAX (0x00000001U)
  1061. #define CSL_EVETPCC_EMR_E7_MASK (0x00000080U)
  1062. #define CSL_EVETPCC_EMR_E7_SHIFT (7U)
  1063. #define CSL_EVETPCC_EMR_E7_RESETVAL (0x00000000U)
  1064. #define CSL_EVETPCC_EMR_E7_MAX (0x00000001U)
  1065. #define CSL_EVETPCC_EMR_E8_MASK (0x00000100U)
  1066. #define CSL_EVETPCC_EMR_E8_SHIFT (8U)
  1067. #define CSL_EVETPCC_EMR_E8_RESETVAL (0x00000000U)
  1068. #define CSL_EVETPCC_EMR_E8_MAX (0x00000001U)
  1069. #define CSL_EVETPCC_EMR_E9_MASK (0x00000200U)
  1070. #define CSL_EVETPCC_EMR_E9_SHIFT (9U)
  1071. #define CSL_EVETPCC_EMR_E9_RESETVAL (0x00000000U)
  1072. #define CSL_EVETPCC_EMR_E9_MAX (0x00000001U)
  1073. #define CSL_EVETPCC_EMR_E10_MASK (0x00000400U)
  1074. #define CSL_EVETPCC_EMR_E10_SHIFT (10U)
  1075. #define CSL_EVETPCC_EMR_E10_RESETVAL (0x00000000U)
  1076. #define CSL_EVETPCC_EMR_E10_MAX (0x00000001U)
  1077. #define CSL_EVETPCC_EMR_E11_MASK (0x00000800U)
  1078. #define CSL_EVETPCC_EMR_E11_SHIFT (11U)
  1079. #define CSL_EVETPCC_EMR_E11_RESETVAL (0x00000000U)
  1080. #define CSL_EVETPCC_EMR_E11_MAX (0x00000001U)
  1081. #define CSL_EVETPCC_EMR_E12_MASK (0x00001000U)
  1082. #define CSL_EVETPCC_EMR_E12_SHIFT (12U)
  1083. #define CSL_EVETPCC_EMR_E12_RESETVAL (0x00000000U)
  1084. #define CSL_EVETPCC_EMR_E12_MAX (0x00000001U)
  1085. #define CSL_EVETPCC_EMR_E13_MASK (0x00002000U)
  1086. #define CSL_EVETPCC_EMR_E13_SHIFT (13U)
  1087. #define CSL_EVETPCC_EMR_E13_RESETVAL (0x00000000U)
  1088. #define CSL_EVETPCC_EMR_E13_MAX (0x00000001U)
  1089. #define CSL_EVETPCC_EMR_E14_MASK (0x00004000U)
  1090. #define CSL_EVETPCC_EMR_E14_SHIFT (14U)
  1091. #define CSL_EVETPCC_EMR_E14_RESETVAL (0x00000000U)
  1092. #define CSL_EVETPCC_EMR_E14_MAX (0x00000001U)
  1093. #define CSL_EVETPCC_EMR_E15_MASK (0x00008000U)
  1094. #define CSL_EVETPCC_EMR_E15_SHIFT (15U)
  1095. #define CSL_EVETPCC_EMR_E15_RESETVAL (0x00000000U)
  1096. #define CSL_EVETPCC_EMR_E15_MAX (0x00000001U)
  1097. #define CSL_EVETPCC_EMR_E16_MASK (0x00010000U)
  1098. #define CSL_EVETPCC_EMR_E16_SHIFT (16U)
  1099. #define CSL_EVETPCC_EMR_E16_RESETVAL (0x00000000U)
  1100. #define CSL_EVETPCC_EMR_E16_MAX (0x00000001U)
  1101. #define CSL_EVETPCC_EMR_E17_MASK (0x00020000U)
  1102. #define CSL_EVETPCC_EMR_E17_SHIFT (17U)
  1103. #define CSL_EVETPCC_EMR_E17_RESETVAL (0x00000000U)
  1104. #define CSL_EVETPCC_EMR_E17_MAX (0x00000001U)
  1105. #define CSL_EVETPCC_EMR_E18_MASK (0x00040000U)
  1106. #define CSL_EVETPCC_EMR_E18_SHIFT (18U)
  1107. #define CSL_EVETPCC_EMR_E18_RESETVAL (0x00000000U)
  1108. #define CSL_EVETPCC_EMR_E18_MAX (0x00000001U)
  1109. #define CSL_EVETPCC_EMR_E19_MASK (0x00080000U)
  1110. #define CSL_EVETPCC_EMR_E19_SHIFT (19U)
  1111. #define CSL_EVETPCC_EMR_E19_RESETVAL (0x00000000U)
  1112. #define CSL_EVETPCC_EMR_E19_MAX (0x00000001U)
  1113. #define CSL_EVETPCC_EMR_E20_MASK (0x00100000U)
  1114. #define CSL_EVETPCC_EMR_E20_SHIFT (20U)
  1115. #define CSL_EVETPCC_EMR_E20_RESETVAL (0x00000000U)
  1116. #define CSL_EVETPCC_EMR_E20_MAX (0x00000001U)
  1117. #define CSL_EVETPCC_EMR_E21_MASK (0x00200000U)
  1118. #define CSL_EVETPCC_EMR_E21_SHIFT (21U)
  1119. #define CSL_EVETPCC_EMR_E21_RESETVAL (0x00000000U)
  1120. #define CSL_EVETPCC_EMR_E21_MAX (0x00000001U)
  1121. #define CSL_EVETPCC_EMR_E22_MASK (0x00400000U)
  1122. #define CSL_EVETPCC_EMR_E22_SHIFT (22U)
  1123. #define CSL_EVETPCC_EMR_E22_RESETVAL (0x00000000U)
  1124. #define CSL_EVETPCC_EMR_E22_MAX (0x00000001U)
  1125. #define CSL_EVETPCC_EMR_E23_MASK (0x00800000U)
  1126. #define CSL_EVETPCC_EMR_E23_SHIFT (23U)
  1127. #define CSL_EVETPCC_EMR_E23_RESETVAL (0x00000000U)
  1128. #define CSL_EVETPCC_EMR_E23_MAX (0x00000001U)
  1129. #define CSL_EVETPCC_EMR_E24_MASK (0x01000000U)
  1130. #define CSL_EVETPCC_EMR_E24_SHIFT (24U)
  1131. #define CSL_EVETPCC_EMR_E24_RESETVAL (0x00000000U)
  1132. #define CSL_EVETPCC_EMR_E24_MAX (0x00000001U)
  1133. #define CSL_EVETPCC_EMR_E25_MASK (0x02000000U)
  1134. #define CSL_EVETPCC_EMR_E25_SHIFT (25U)
  1135. #define CSL_EVETPCC_EMR_E25_RESETVAL (0x00000000U)
  1136. #define CSL_EVETPCC_EMR_E25_MAX (0x00000001U)
  1137. #define CSL_EVETPCC_EMR_E26_MASK (0x04000000U)
  1138. #define CSL_EVETPCC_EMR_E26_SHIFT (26U)
  1139. #define CSL_EVETPCC_EMR_E26_RESETVAL (0x00000000U)
  1140. #define CSL_EVETPCC_EMR_E26_MAX (0x00000001U)
  1141. #define CSL_EVETPCC_EMR_E27_MASK (0x08000000U)
  1142. #define CSL_EVETPCC_EMR_E27_SHIFT (27U)
  1143. #define CSL_EVETPCC_EMR_E27_RESETVAL (0x00000000U)
  1144. #define CSL_EVETPCC_EMR_E27_MAX (0x00000001U)
  1145. #define CSL_EVETPCC_EMR_E28_MASK (0x10000000U)
  1146. #define CSL_EVETPCC_EMR_E28_SHIFT (28U)
  1147. #define CSL_EVETPCC_EMR_E28_RESETVAL (0x00000000U)
  1148. #define CSL_EVETPCC_EMR_E28_MAX (0x00000001U)
  1149. #define CSL_EVETPCC_EMR_E29_MASK (0x20000000U)
  1150. #define CSL_EVETPCC_EMR_E29_SHIFT (29U)
  1151. #define CSL_EVETPCC_EMR_E29_RESETVAL (0x00000000U)
  1152. #define CSL_EVETPCC_EMR_E29_MAX (0x00000001U)
  1153. #define CSL_EVETPCC_EMR_E30_MASK (0x40000000U)
  1154. #define CSL_EVETPCC_EMR_E30_SHIFT (30U)
  1155. #define CSL_EVETPCC_EMR_E30_RESETVAL (0x00000000U)
  1156. #define CSL_EVETPCC_EMR_E30_MAX (0x00000001U)
  1157. #define CSL_EVETPCC_EMR_E31_MASK (0x80000000U)
  1158. #define CSL_EVETPCC_EMR_E31_SHIFT (31U)
  1159. #define CSL_EVETPCC_EMR_E31_RESETVAL (0x00000000U)
  1160. #define CSL_EVETPCC_EMR_E31_MAX (0x00000001U)
  1161. #define CSL_EVETPCC_EMR_RESETVAL (0x00000000U)
  1162. /* EMRH */
  1163. #define CSL_EVETPCC_EMRH_E48_MASK (0x00010000U)
  1164. #define CSL_EVETPCC_EMRH_E48_SHIFT (16U)
  1165. #define CSL_EVETPCC_EMRH_E48_RESETVAL (0x00000000U)
  1166. #define CSL_EVETPCC_EMRH_E48_MAX (0x00000001U)
  1167. #define CSL_EVETPCC_EMRH_E33_MASK (0x00000002U)
  1168. #define CSL_EVETPCC_EMRH_E33_SHIFT (1U)
  1169. #define CSL_EVETPCC_EMRH_E33_RESETVAL (0x00000000U)
  1170. #define CSL_EVETPCC_EMRH_E33_MAX (0x00000001U)
  1171. #define CSL_EVETPCC_EMRH_E42_MASK (0x00000400U)
  1172. #define CSL_EVETPCC_EMRH_E42_SHIFT (10U)
  1173. #define CSL_EVETPCC_EMRH_E42_RESETVAL (0x00000000U)
  1174. #define CSL_EVETPCC_EMRH_E42_MAX (0x00000001U)
  1175. #define CSL_EVETPCC_EMRH_E43_MASK (0x00000800U)
  1176. #define CSL_EVETPCC_EMRH_E43_SHIFT (11U)
  1177. #define CSL_EVETPCC_EMRH_E43_RESETVAL (0x00000000U)
  1178. #define CSL_EVETPCC_EMRH_E43_MAX (0x00000001U)
  1179. #define CSL_EVETPCC_EMRH_E45_MASK (0x00002000U)
  1180. #define CSL_EVETPCC_EMRH_E45_SHIFT (13U)
  1181. #define CSL_EVETPCC_EMRH_E45_RESETVAL (0x00000000U)
  1182. #define CSL_EVETPCC_EMRH_E45_MAX (0x00000001U)
  1183. #define CSL_EVETPCC_EMRH_E60_MASK (0x10000000U)
  1184. #define CSL_EVETPCC_EMRH_E60_SHIFT (28U)
  1185. #define CSL_EVETPCC_EMRH_E60_RESETVAL (0x00000000U)
  1186. #define CSL_EVETPCC_EMRH_E60_MAX (0x00000001U)
  1187. #define CSL_EVETPCC_EMRH_E49_MASK (0x00020000U)
  1188. #define CSL_EVETPCC_EMRH_E49_SHIFT (17U)
  1189. #define CSL_EVETPCC_EMRH_E49_RESETVAL (0x00000000U)
  1190. #define CSL_EVETPCC_EMRH_E49_MAX (0x00000001U)
  1191. #define CSL_EVETPCC_EMRH_E54_MASK (0x00400000U)
  1192. #define CSL_EVETPCC_EMRH_E54_SHIFT (22U)
  1193. #define CSL_EVETPCC_EMRH_E54_RESETVAL (0x00000000U)
  1194. #define CSL_EVETPCC_EMRH_E54_MAX (0x00000001U)
  1195. #define CSL_EVETPCC_EMRH_E39_MASK (0x00000080U)
  1196. #define CSL_EVETPCC_EMRH_E39_SHIFT (7U)
  1197. #define CSL_EVETPCC_EMRH_E39_RESETVAL (0x00000000U)
  1198. #define CSL_EVETPCC_EMRH_E39_MAX (0x00000001U)
  1199. #define CSL_EVETPCC_EMRH_E55_MASK (0x00800000U)
  1200. #define CSL_EVETPCC_EMRH_E55_SHIFT (23U)
  1201. #define CSL_EVETPCC_EMRH_E55_RESETVAL (0x00000000U)
  1202. #define CSL_EVETPCC_EMRH_E55_MAX (0x00000001U)
  1203. #define CSL_EVETPCC_EMRH_E53_MASK (0x00200000U)
  1204. #define CSL_EVETPCC_EMRH_E53_SHIFT (21U)
  1205. #define CSL_EVETPCC_EMRH_E53_RESETVAL (0x00000000U)
  1206. #define CSL_EVETPCC_EMRH_E53_MAX (0x00000001U)
  1207. #define CSL_EVETPCC_EMRH_E32_MASK (0x00000001U)
  1208. #define CSL_EVETPCC_EMRH_E32_SHIFT (0U)
  1209. #define CSL_EVETPCC_EMRH_E32_RESETVAL (0x00000000U)
  1210. #define CSL_EVETPCC_EMRH_E32_MAX (0x00000001U)
  1211. #define CSL_EVETPCC_EMRH_E41_MASK (0x00000200U)
  1212. #define CSL_EVETPCC_EMRH_E41_SHIFT (9U)
  1213. #define CSL_EVETPCC_EMRH_E41_RESETVAL (0x00000000U)
  1214. #define CSL_EVETPCC_EMRH_E41_MAX (0x00000001U)
  1215. #define CSL_EVETPCC_EMRH_E47_MASK (0x00008000U)
  1216. #define CSL_EVETPCC_EMRH_E47_SHIFT (15U)
  1217. #define CSL_EVETPCC_EMRH_E47_RESETVAL (0x00000000U)
  1218. #define CSL_EVETPCC_EMRH_E47_MAX (0x00000001U)
  1219. #define CSL_EVETPCC_EMRH_E58_MASK (0x04000000U)
  1220. #define CSL_EVETPCC_EMRH_E58_SHIFT (26U)
  1221. #define CSL_EVETPCC_EMRH_E58_RESETVAL (0x00000000U)
  1222. #define CSL_EVETPCC_EMRH_E58_MAX (0x00000001U)
  1223. #define CSL_EVETPCC_EMRH_E35_MASK (0x00000008U)
  1224. #define CSL_EVETPCC_EMRH_E35_SHIFT (3U)
  1225. #define CSL_EVETPCC_EMRH_E35_RESETVAL (0x00000000U)
  1226. #define CSL_EVETPCC_EMRH_E35_MAX (0x00000001U)
  1227. #define CSL_EVETPCC_EMRH_E34_MASK (0x00000004U)
  1228. #define CSL_EVETPCC_EMRH_E34_SHIFT (2U)
  1229. #define CSL_EVETPCC_EMRH_E34_RESETVAL (0x00000000U)
  1230. #define CSL_EVETPCC_EMRH_E34_MAX (0x00000001U)
  1231. #define CSL_EVETPCC_EMRH_E38_MASK (0x00000040U)
  1232. #define CSL_EVETPCC_EMRH_E38_SHIFT (6U)
  1233. #define CSL_EVETPCC_EMRH_E38_RESETVAL (0x00000000U)
  1234. #define CSL_EVETPCC_EMRH_E38_MAX (0x00000001U)
  1235. #define CSL_EVETPCC_EMRH_E59_MASK (0x08000000U)
  1236. #define CSL_EVETPCC_EMRH_E59_SHIFT (27U)
  1237. #define CSL_EVETPCC_EMRH_E59_RESETVAL (0x00000000U)
  1238. #define CSL_EVETPCC_EMRH_E59_MAX (0x00000001U)
  1239. #define CSL_EVETPCC_EMRH_E37_MASK (0x00000020U)
  1240. #define CSL_EVETPCC_EMRH_E37_SHIFT (5U)
  1241. #define CSL_EVETPCC_EMRH_E37_RESETVAL (0x00000000U)
  1242. #define CSL_EVETPCC_EMRH_E37_MAX (0x00000001U)
  1243. #define CSL_EVETPCC_EMRH_E63_MASK (0x80000000U)
  1244. #define CSL_EVETPCC_EMRH_E63_SHIFT (31U)
  1245. #define CSL_EVETPCC_EMRH_E63_RESETVAL (0x00000000U)
  1246. #define CSL_EVETPCC_EMRH_E63_MAX (0x00000001U)
  1247. #define CSL_EVETPCC_EMRH_E57_MASK (0x02000000U)
  1248. #define CSL_EVETPCC_EMRH_E57_SHIFT (25U)
  1249. #define CSL_EVETPCC_EMRH_E57_RESETVAL (0x00000000U)
  1250. #define CSL_EVETPCC_EMRH_E57_MAX (0x00000001U)
  1251. #define CSL_EVETPCC_EMRH_E62_MASK (0x40000000U)
  1252. #define CSL_EVETPCC_EMRH_E62_SHIFT (30U)
  1253. #define CSL_EVETPCC_EMRH_E62_RESETVAL (0x00000000U)
  1254. #define CSL_EVETPCC_EMRH_E62_MAX (0x00000001U)
  1255. #define CSL_EVETPCC_EMRH_E36_MASK (0x00000010U)
  1256. #define CSL_EVETPCC_EMRH_E36_SHIFT (4U)
  1257. #define CSL_EVETPCC_EMRH_E36_RESETVAL (0x00000000U)
  1258. #define CSL_EVETPCC_EMRH_E36_MAX (0x00000001U)
  1259. #define CSL_EVETPCC_EMRH_E44_MASK (0x00001000U)
  1260. #define CSL_EVETPCC_EMRH_E44_SHIFT (12U)
  1261. #define CSL_EVETPCC_EMRH_E44_RESETVAL (0x00000000U)
  1262. #define CSL_EVETPCC_EMRH_E44_MAX (0x00000001U)
  1263. #define CSL_EVETPCC_EMRH_E56_MASK (0x01000000U)
  1264. #define CSL_EVETPCC_EMRH_E56_SHIFT (24U)
  1265. #define CSL_EVETPCC_EMRH_E56_RESETVAL (0x00000000U)
  1266. #define CSL_EVETPCC_EMRH_E56_MAX (0x00000001U)
  1267. #define CSL_EVETPCC_EMRH_E50_MASK (0x00040000U)
  1268. #define CSL_EVETPCC_EMRH_E50_SHIFT (18U)
  1269. #define CSL_EVETPCC_EMRH_E50_RESETVAL (0x00000000U)
  1270. #define CSL_EVETPCC_EMRH_E50_MAX (0x00000001U)
  1271. #define CSL_EVETPCC_EMRH_E40_MASK (0x00000100U)
  1272. #define CSL_EVETPCC_EMRH_E40_SHIFT (8U)
  1273. #define CSL_EVETPCC_EMRH_E40_RESETVAL (0x00000000U)
  1274. #define CSL_EVETPCC_EMRH_E40_MAX (0x00000001U)
  1275. #define CSL_EVETPCC_EMRH_E46_MASK (0x00004000U)
  1276. #define CSL_EVETPCC_EMRH_E46_SHIFT (14U)
  1277. #define CSL_EVETPCC_EMRH_E46_RESETVAL (0x00000000U)
  1278. #define CSL_EVETPCC_EMRH_E46_MAX (0x00000001U)
  1279. #define CSL_EVETPCC_EMRH_E51_MASK (0x00080000U)
  1280. #define CSL_EVETPCC_EMRH_E51_SHIFT (19U)
  1281. #define CSL_EVETPCC_EMRH_E51_RESETVAL (0x00000000U)
  1282. #define CSL_EVETPCC_EMRH_E51_MAX (0x00000001U)
  1283. #define CSL_EVETPCC_EMRH_E52_MASK (0x00100000U)
  1284. #define CSL_EVETPCC_EMRH_E52_SHIFT (20U)
  1285. #define CSL_EVETPCC_EMRH_E52_RESETVAL (0x00000000U)
  1286. #define CSL_EVETPCC_EMRH_E52_MAX (0x00000001U)
  1287. #define CSL_EVETPCC_EMRH_E61_MASK (0x20000000U)
  1288. #define CSL_EVETPCC_EMRH_E61_SHIFT (29U)
  1289. #define CSL_EVETPCC_EMRH_E61_RESETVAL (0x00000000U)
  1290. #define CSL_EVETPCC_EMRH_E61_MAX (0x00000001U)
  1291. #define CSL_EVETPCC_EMRH_RESETVAL (0x00000000U)
  1292. /* EMCR */
  1293. #define CSL_EVETPCC_EMCR_E10_MASK (0x00000400U)
  1294. #define CSL_EVETPCC_EMCR_E10_SHIFT (10U)
  1295. #define CSL_EVETPCC_EMCR_E10_RESETVAL (0x00000000U)
  1296. #define CSL_EVETPCC_EMCR_E10_MAX (0x00000001U)
  1297. #define CSL_EVETPCC_EMCR_E7_MASK (0x00000080U)
  1298. #define CSL_EVETPCC_EMCR_E7_SHIFT (7U)
  1299. #define CSL_EVETPCC_EMCR_E7_RESETVAL (0x00000000U)
  1300. #define CSL_EVETPCC_EMCR_E7_MAX (0x00000001U)
  1301. #define CSL_EVETPCC_EMCR_E29_MASK (0x20000000U)
  1302. #define CSL_EVETPCC_EMCR_E29_SHIFT (29U)
  1303. #define CSL_EVETPCC_EMCR_E29_RESETVAL (0x00000000U)
  1304. #define CSL_EVETPCC_EMCR_E29_MAX (0x00000001U)
  1305. #define CSL_EVETPCC_EMCR_E30_MASK (0x40000000U)
  1306. #define CSL_EVETPCC_EMCR_E30_SHIFT (30U)
  1307. #define CSL_EVETPCC_EMCR_E30_RESETVAL (0x00000000U)
  1308. #define CSL_EVETPCC_EMCR_E30_MAX (0x00000001U)
  1309. #define CSL_EVETPCC_EMCR_E11_MASK (0x00000800U)
  1310. #define CSL_EVETPCC_EMCR_E11_SHIFT (11U)
  1311. #define CSL_EVETPCC_EMCR_E11_RESETVAL (0x00000000U)
  1312. #define CSL_EVETPCC_EMCR_E11_MAX (0x00000001U)
  1313. #define CSL_EVETPCC_EMCR_E16_MASK (0x00010000U)
  1314. #define CSL_EVETPCC_EMCR_E16_SHIFT (16U)
  1315. #define CSL_EVETPCC_EMCR_E16_RESETVAL (0x00000000U)
  1316. #define CSL_EVETPCC_EMCR_E16_MAX (0x00000001U)
  1317. #define CSL_EVETPCC_EMCR_E2_MASK (0x00000004U)
  1318. #define CSL_EVETPCC_EMCR_E2_SHIFT (2U)
  1319. #define CSL_EVETPCC_EMCR_E2_RESETVAL (0x00000000U)
  1320. #define CSL_EVETPCC_EMCR_E2_MAX (0x00000001U)
  1321. #define CSL_EVETPCC_EMCR_E28_MASK (0x10000000U)
  1322. #define CSL_EVETPCC_EMCR_E28_SHIFT (28U)
  1323. #define CSL_EVETPCC_EMCR_E28_RESETVAL (0x00000000U)
  1324. #define CSL_EVETPCC_EMCR_E28_MAX (0x00000001U)
  1325. #define CSL_EVETPCC_EMCR_E17_MASK (0x00020000U)
  1326. #define CSL_EVETPCC_EMCR_E17_SHIFT (17U)
  1327. #define CSL_EVETPCC_EMCR_E17_RESETVAL (0x00000000U)
  1328. #define CSL_EVETPCC_EMCR_E17_MAX (0x00000001U)
  1329. #define CSL_EVETPCC_EMCR_E12_MASK (0x00001000U)
  1330. #define CSL_EVETPCC_EMCR_E12_SHIFT (12U)
  1331. #define CSL_EVETPCC_EMCR_E12_RESETVAL (0x00000000U)
  1332. #define CSL_EVETPCC_EMCR_E12_MAX (0x00000001U)
  1333. #define CSL_EVETPCC_EMCR_E24_MASK (0x01000000U)
  1334. #define CSL_EVETPCC_EMCR_E24_SHIFT (24U)
  1335. #define CSL_EVETPCC_EMCR_E24_RESETVAL (0x00000000U)
  1336. #define CSL_EVETPCC_EMCR_E24_MAX (0x00000001U)
  1337. #define CSL_EVETPCC_EMCR_E4_MASK (0x00000010U)
  1338. #define CSL_EVETPCC_EMCR_E4_SHIFT (4U)
  1339. #define CSL_EVETPCC_EMCR_E4_RESETVAL (0x00000000U)
  1340. #define CSL_EVETPCC_EMCR_E4_MAX (0x00000001U)
  1341. #define CSL_EVETPCC_EMCR_E25_MASK (0x02000000U)
  1342. #define CSL_EVETPCC_EMCR_E25_SHIFT (25U)
  1343. #define CSL_EVETPCC_EMCR_E25_RESETVAL (0x00000000U)
  1344. #define CSL_EVETPCC_EMCR_E25_MAX (0x00000001U)
  1345. #define CSL_EVETPCC_EMCR_E8_MASK (0x00000100U)
  1346. #define CSL_EVETPCC_EMCR_E8_SHIFT (8U)
  1347. #define CSL_EVETPCC_EMCR_E8_RESETVAL (0x00000000U)
  1348. #define CSL_EVETPCC_EMCR_E8_MAX (0x00000001U)
  1349. #define CSL_EVETPCC_EMCR_E15_MASK (0x00008000U)
  1350. #define CSL_EVETPCC_EMCR_E15_SHIFT (15U)
  1351. #define CSL_EVETPCC_EMCR_E15_RESETVAL (0x00000000U)
  1352. #define CSL_EVETPCC_EMCR_E15_MAX (0x00000001U)
  1353. #define CSL_EVETPCC_EMCR_E31_MASK (0x80000000U)
  1354. #define CSL_EVETPCC_EMCR_E31_SHIFT (31U)
  1355. #define CSL_EVETPCC_EMCR_E31_RESETVAL (0x00000000U)
  1356. #define CSL_EVETPCC_EMCR_E31_MAX (0x00000001U)
  1357. #define CSL_EVETPCC_EMCR_E26_MASK (0x04000000U)
  1358. #define CSL_EVETPCC_EMCR_E26_SHIFT (26U)
  1359. #define CSL_EVETPCC_EMCR_E26_RESETVAL (0x00000000U)
  1360. #define CSL_EVETPCC_EMCR_E26_MAX (0x00000001U)
  1361. #define CSL_EVETPCC_EMCR_E14_MASK (0x00004000U)
  1362. #define CSL_EVETPCC_EMCR_E14_SHIFT (14U)
  1363. #define CSL_EVETPCC_EMCR_E14_RESETVAL (0x00000000U)
  1364. #define CSL_EVETPCC_EMCR_E14_MAX (0x00000001U)
  1365. #define CSL_EVETPCC_EMCR_E9_MASK (0x00000200U)
  1366. #define CSL_EVETPCC_EMCR_E9_SHIFT (9U)
  1367. #define CSL_EVETPCC_EMCR_E9_RESETVAL (0x00000000U)
  1368. #define CSL_EVETPCC_EMCR_E9_MAX (0x00000001U)
  1369. #define CSL_EVETPCC_EMCR_E23_MASK (0x00800000U)
  1370. #define CSL_EVETPCC_EMCR_E23_SHIFT (23U)
  1371. #define CSL_EVETPCC_EMCR_E23_RESETVAL (0x00000000U)
  1372. #define CSL_EVETPCC_EMCR_E23_MAX (0x00000001U)
  1373. #define CSL_EVETPCC_EMCR_E6_MASK (0x00000040U)
  1374. #define CSL_EVETPCC_EMCR_E6_SHIFT (6U)
  1375. #define CSL_EVETPCC_EMCR_E6_RESETVAL (0x00000000U)
  1376. #define CSL_EVETPCC_EMCR_E6_MAX (0x00000001U)
  1377. #define CSL_EVETPCC_EMCR_E13_MASK (0x00002000U)
  1378. #define CSL_EVETPCC_EMCR_E13_SHIFT (13U)
  1379. #define CSL_EVETPCC_EMCR_E13_RESETVAL (0x00000000U)
  1380. #define CSL_EVETPCC_EMCR_E13_MAX (0x00000001U)
  1381. #define CSL_EVETPCC_EMCR_E1_MASK (0x00000002U)
  1382. #define CSL_EVETPCC_EMCR_E1_SHIFT (1U)
  1383. #define CSL_EVETPCC_EMCR_E1_RESETVAL (0x00000000U)
  1384. #define CSL_EVETPCC_EMCR_E1_MAX (0x00000001U)
  1385. #define CSL_EVETPCC_EMCR_E21_MASK (0x00200000U)
  1386. #define CSL_EVETPCC_EMCR_E21_SHIFT (21U)
  1387. #define CSL_EVETPCC_EMCR_E21_RESETVAL (0x00000000U)
  1388. #define CSL_EVETPCC_EMCR_E21_MAX (0x00000001U)
  1389. #define CSL_EVETPCC_EMCR_E22_MASK (0x00400000U)
  1390. #define CSL_EVETPCC_EMCR_E22_SHIFT (22U)
  1391. #define CSL_EVETPCC_EMCR_E22_RESETVAL (0x00000000U)
  1392. #define CSL_EVETPCC_EMCR_E22_MAX (0x00000001U)
  1393. #define CSL_EVETPCC_EMCR_E27_MASK (0x08000000U)
  1394. #define CSL_EVETPCC_EMCR_E27_SHIFT (27U)
  1395. #define CSL_EVETPCC_EMCR_E27_RESETVAL (0x00000000U)
  1396. #define CSL_EVETPCC_EMCR_E27_MAX (0x00000001U)
  1397. #define CSL_EVETPCC_EMCR_E20_MASK (0x00100000U)
  1398. #define CSL_EVETPCC_EMCR_E20_SHIFT (20U)
  1399. #define CSL_EVETPCC_EMCR_E20_RESETVAL (0x00000000U)
  1400. #define CSL_EVETPCC_EMCR_E20_MAX (0x00000001U)
  1401. #define CSL_EVETPCC_EMCR_E19_MASK (0x00080000U)
  1402. #define CSL_EVETPCC_EMCR_E19_SHIFT (19U)
  1403. #define CSL_EVETPCC_EMCR_E19_RESETVAL (0x00000000U)
  1404. #define CSL_EVETPCC_EMCR_E19_MAX (0x00000001U)
  1405. #define CSL_EVETPCC_EMCR_E0_MASK (0x00000001U)
  1406. #define CSL_EVETPCC_EMCR_E0_SHIFT (0U)
  1407. #define CSL_EVETPCC_EMCR_E0_RESETVAL (0x00000000U)
  1408. #define CSL_EVETPCC_EMCR_E0_MAX (0x00000001U)
  1409. #define CSL_EVETPCC_EMCR_E5_MASK (0x00000020U)
  1410. #define CSL_EVETPCC_EMCR_E5_SHIFT (5U)
  1411. #define CSL_EVETPCC_EMCR_E5_RESETVAL (0x00000000U)
  1412. #define CSL_EVETPCC_EMCR_E5_MAX (0x00000001U)
  1413. #define CSL_EVETPCC_EMCR_E3_MASK (0x00000008U)
  1414. #define CSL_EVETPCC_EMCR_E3_SHIFT (3U)
  1415. #define CSL_EVETPCC_EMCR_E3_RESETVAL (0x00000000U)
  1416. #define CSL_EVETPCC_EMCR_E3_MAX (0x00000001U)
  1417. #define CSL_EVETPCC_EMCR_E18_MASK (0x00040000U)
  1418. #define CSL_EVETPCC_EMCR_E18_SHIFT (18U)
  1419. #define CSL_EVETPCC_EMCR_E18_RESETVAL (0x00000000U)
  1420. #define CSL_EVETPCC_EMCR_E18_MAX (0x00000001U)
  1421. #define CSL_EVETPCC_EMCR_RESETVAL (0x00000000U)
  1422. /* EMCRH */
  1423. #define CSL_EVETPCC_EMCRH_E41_MASK (0x00000200U)
  1424. #define CSL_EVETPCC_EMCRH_E41_SHIFT (9U)
  1425. #define CSL_EVETPCC_EMCRH_E41_RESETVAL (0x00000000U)
  1426. #define CSL_EVETPCC_EMCRH_E41_MAX (0x00000001U)
  1427. #define CSL_EVETPCC_EMCRH_E60_MASK (0x10000000U)
  1428. #define CSL_EVETPCC_EMCRH_E60_SHIFT (28U)
  1429. #define CSL_EVETPCC_EMCRH_E60_RESETVAL (0x00000000U)
  1430. #define CSL_EVETPCC_EMCRH_E60_MAX (0x00000001U)
  1431. #define CSL_EVETPCC_EMCRH_E43_MASK (0x00000800U)
  1432. #define CSL_EVETPCC_EMCRH_E43_SHIFT (11U)
  1433. #define CSL_EVETPCC_EMCRH_E43_RESETVAL (0x00000000U)
  1434. #define CSL_EVETPCC_EMCRH_E43_MAX (0x00000001U)
  1435. #define CSL_EVETPCC_EMCRH_E63_MASK (0x80000000U)
  1436. #define CSL_EVETPCC_EMCRH_E63_SHIFT (31U)
  1437. #define CSL_EVETPCC_EMCRH_E63_RESETVAL (0x00000000U)
  1438. #define CSL_EVETPCC_EMCRH_E63_MAX (0x00000001U)
  1439. #define CSL_EVETPCC_EMCRH_E55_MASK (0x00800000U)
  1440. #define CSL_EVETPCC_EMCRH_E55_SHIFT (23U)
  1441. #define CSL_EVETPCC_EMCRH_E55_RESETVAL (0x00000000U)
  1442. #define CSL_EVETPCC_EMCRH_E55_MAX (0x00000001U)
  1443. #define CSL_EVETPCC_EMCRH_E38_MASK (0x00000040U)
  1444. #define CSL_EVETPCC_EMCRH_E38_SHIFT (6U)
  1445. #define CSL_EVETPCC_EMCRH_E38_RESETVAL (0x00000000U)
  1446. #define CSL_EVETPCC_EMCRH_E38_MAX (0x00000001U)
  1447. #define CSL_EVETPCC_EMCRH_E62_MASK (0x40000000U)
  1448. #define CSL_EVETPCC_EMCRH_E62_SHIFT (30U)
  1449. #define CSL_EVETPCC_EMCRH_E62_RESETVAL (0x00000000U)
  1450. #define CSL_EVETPCC_EMCRH_E62_MAX (0x00000001U)
  1451. #define CSL_EVETPCC_EMCRH_E34_MASK (0x00000004U)
  1452. #define CSL_EVETPCC_EMCRH_E34_SHIFT (2U)
  1453. #define CSL_EVETPCC_EMCRH_E34_RESETVAL (0x00000000U)
  1454. #define CSL_EVETPCC_EMCRH_E34_MAX (0x00000001U)
  1455. #define CSL_EVETPCC_EMCRH_E46_MASK (0x00004000U)
  1456. #define CSL_EVETPCC_EMCRH_E46_SHIFT (14U)
  1457. #define CSL_EVETPCC_EMCRH_E46_RESETVAL (0x00000000U)
  1458. #define CSL_EVETPCC_EMCRH_E46_MAX (0x00000001U)
  1459. #define CSL_EVETPCC_EMCRH_E42_MASK (0x00000400U)
  1460. #define CSL_EVETPCC_EMCRH_E42_SHIFT (10U)
  1461. #define CSL_EVETPCC_EMCRH_E42_RESETVAL (0x00000000U)
  1462. #define CSL_EVETPCC_EMCRH_E42_MAX (0x00000001U)
  1463. #define CSL_EVETPCC_EMCRH_E48_MASK (0x00010000U)
  1464. #define CSL_EVETPCC_EMCRH_E48_SHIFT (16U)
  1465. #define CSL_EVETPCC_EMCRH_E48_RESETVAL (0x00000000U)
  1466. #define CSL_EVETPCC_EMCRH_E48_MAX (0x00000001U)
  1467. #define CSL_EVETPCC_EMCRH_E32_MASK (0x00000001U)
  1468. #define CSL_EVETPCC_EMCRH_E32_SHIFT (0U)
  1469. #define CSL_EVETPCC_EMCRH_E32_RESETVAL (0x00000000U)
  1470. #define CSL_EVETPCC_EMCRH_E32_MAX (0x00000001U)
  1471. #define CSL_EVETPCC_EMCRH_E44_MASK (0x00001000U)
  1472. #define CSL_EVETPCC_EMCRH_E44_SHIFT (12U)
  1473. #define CSL_EVETPCC_EMCRH_E44_RESETVAL (0x00000000U)
  1474. #define CSL_EVETPCC_EMCRH_E44_MAX (0x00000001U)
  1475. #define CSL_EVETPCC_EMCRH_E50_MASK (0x00040000U)
  1476. #define CSL_EVETPCC_EMCRH_E50_SHIFT (18U)
  1477. #define CSL_EVETPCC_EMCRH_E50_RESETVAL (0x00000000U)
  1478. #define CSL_EVETPCC_EMCRH_E50_MAX (0x00000001U)
  1479. #define CSL_EVETPCC_EMCRH_E53_MASK (0x00200000U)
  1480. #define CSL_EVETPCC_EMCRH_E53_SHIFT (21U)
  1481. #define CSL_EVETPCC_EMCRH_E53_RESETVAL (0x00000000U)
  1482. #define CSL_EVETPCC_EMCRH_E53_MAX (0x00000001U)
  1483. #define CSL_EVETPCC_EMCRH_E37_MASK (0x00000020U)
  1484. #define CSL_EVETPCC_EMCRH_E37_SHIFT (5U)
  1485. #define CSL_EVETPCC_EMCRH_E37_RESETVAL (0x00000000U)
  1486. #define CSL_EVETPCC_EMCRH_E37_MAX (0x00000001U)
  1487. #define CSL_EVETPCC_EMCRH_E45_MASK (0x00002000U)
  1488. #define CSL_EVETPCC_EMCRH_E45_SHIFT (13U)
  1489. #define CSL_EVETPCC_EMCRH_E45_RESETVAL (0x00000000U)
  1490. #define CSL_EVETPCC_EMCRH_E45_MAX (0x00000001U)
  1491. #define CSL_EVETPCC_EMCRH_E59_MASK (0x08000000U)
  1492. #define CSL_EVETPCC_EMCRH_E59_SHIFT (27U)
  1493. #define CSL_EVETPCC_EMCRH_E59_RESETVAL (0x00000000U)
  1494. #define CSL_EVETPCC_EMCRH_E59_MAX (0x00000001U)
  1495. #define CSL_EVETPCC_EMCRH_E58_MASK (0x04000000U)
  1496. #define CSL_EVETPCC_EMCRH_E58_SHIFT (26U)
  1497. #define CSL_EVETPCC_EMCRH_E58_RESETVAL (0x00000000U)
  1498. #define CSL_EVETPCC_EMCRH_E58_MAX (0x00000001U)
  1499. #define CSL_EVETPCC_EMCRH_E40_MASK (0x00000100U)
  1500. #define CSL_EVETPCC_EMCRH_E40_SHIFT (8U)
  1501. #define CSL_EVETPCC_EMCRH_E40_RESETVAL (0x00000000U)
  1502. #define CSL_EVETPCC_EMCRH_E40_MAX (0x00000001U)
  1503. #define CSL_EVETPCC_EMCRH_E54_MASK (0x00400000U)
  1504. #define CSL_EVETPCC_EMCRH_E54_SHIFT (22U)
  1505. #define CSL_EVETPCC_EMCRH_E54_RESETVAL (0x00000000U)
  1506. #define CSL_EVETPCC_EMCRH_E54_MAX (0x00000001U)
  1507. #define CSL_EVETPCC_EMCRH_E49_MASK (0x00020000U)
  1508. #define CSL_EVETPCC_EMCRH_E49_SHIFT (17U)
  1509. #define CSL_EVETPCC_EMCRH_E49_RESETVAL (0x00000000U)
  1510. #define CSL_EVETPCC_EMCRH_E49_MAX (0x00000001U)
  1511. #define CSL_EVETPCC_EMCRH_E33_MASK (0x00000002U)
  1512. #define CSL_EVETPCC_EMCRH_E33_SHIFT (1U)
  1513. #define CSL_EVETPCC_EMCRH_E33_RESETVAL (0x00000000U)
  1514. #define CSL_EVETPCC_EMCRH_E33_MAX (0x00000001U)
  1515. #define CSL_EVETPCC_EMCRH_E47_MASK (0x00008000U)
  1516. #define CSL_EVETPCC_EMCRH_E47_SHIFT (15U)
  1517. #define CSL_EVETPCC_EMCRH_E47_RESETVAL (0x00000000U)
  1518. #define CSL_EVETPCC_EMCRH_E47_MAX (0x00000001U)
  1519. #define CSL_EVETPCC_EMCRH_E36_MASK (0x00000010U)
  1520. #define CSL_EVETPCC_EMCRH_E36_SHIFT (4U)
  1521. #define CSL_EVETPCC_EMCRH_E36_RESETVAL (0x00000000U)
  1522. #define CSL_EVETPCC_EMCRH_E36_MAX (0x00000001U)
  1523. #define CSL_EVETPCC_EMCRH_E56_MASK (0x01000000U)
  1524. #define CSL_EVETPCC_EMCRH_E56_SHIFT (24U)
  1525. #define CSL_EVETPCC_EMCRH_E56_RESETVAL (0x00000000U)
  1526. #define CSL_EVETPCC_EMCRH_E56_MAX (0x00000001U)
  1527. #define CSL_EVETPCC_EMCRH_E57_MASK (0x02000000U)
  1528. #define CSL_EVETPCC_EMCRH_E57_SHIFT (25U)
  1529. #define CSL_EVETPCC_EMCRH_E57_RESETVAL (0x00000000U)
  1530. #define CSL_EVETPCC_EMCRH_E57_MAX (0x00000001U)
  1531. #define CSL_EVETPCC_EMCRH_E51_MASK (0x00080000U)
  1532. #define CSL_EVETPCC_EMCRH_E51_SHIFT (19U)
  1533. #define CSL_EVETPCC_EMCRH_E51_RESETVAL (0x00000000U)
  1534. #define CSL_EVETPCC_EMCRH_E51_MAX (0x00000001U)
  1535. #define CSL_EVETPCC_EMCRH_E61_MASK (0x20000000U)
  1536. #define CSL_EVETPCC_EMCRH_E61_SHIFT (29U)
  1537. #define CSL_EVETPCC_EMCRH_E61_RESETVAL (0x00000000U)
  1538. #define CSL_EVETPCC_EMCRH_E61_MAX (0x00000001U)
  1539. #define CSL_EVETPCC_EMCRH_E39_MASK (0x00000080U)
  1540. #define CSL_EVETPCC_EMCRH_E39_SHIFT (7U)
  1541. #define CSL_EVETPCC_EMCRH_E39_RESETVAL (0x00000000U)
  1542. #define CSL_EVETPCC_EMCRH_E39_MAX (0x00000001U)
  1543. #define CSL_EVETPCC_EMCRH_E52_MASK (0x00100000U)
  1544. #define CSL_EVETPCC_EMCRH_E52_SHIFT (20U)
  1545. #define CSL_EVETPCC_EMCRH_E52_RESETVAL (0x00000000U)
  1546. #define CSL_EVETPCC_EMCRH_E52_MAX (0x00000001U)
  1547. #define CSL_EVETPCC_EMCRH_E35_MASK (0x00000008U)
  1548. #define CSL_EVETPCC_EMCRH_E35_SHIFT (3U)
  1549. #define CSL_EVETPCC_EMCRH_E35_RESETVAL (0x00000000U)
  1550. #define CSL_EVETPCC_EMCRH_E35_MAX (0x00000001U)
  1551. #define CSL_EVETPCC_EMCRH_RESETVAL (0x00000000U)
  1552. /* QEMR */
  1553. #define CSL_EVETPCC_QEMR_E7_MASK (0x00000080U)
  1554. #define CSL_EVETPCC_QEMR_E7_SHIFT (7U)
  1555. #define CSL_EVETPCC_QEMR_E7_RESETVAL (0x00000000U)
  1556. #define CSL_EVETPCC_QEMR_E7_MAX (0x00000001U)
  1557. #define CSL_EVETPCC_QEMR_E6_MASK (0x00000040U)
  1558. #define CSL_EVETPCC_QEMR_E6_SHIFT (6U)
  1559. #define CSL_EVETPCC_QEMR_E6_RESETVAL (0x00000000U)
  1560. #define CSL_EVETPCC_QEMR_E6_MAX (0x00000001U)
  1561. #define CSL_EVETPCC_QEMR_E5_MASK (0x00000020U)
  1562. #define CSL_EVETPCC_QEMR_E5_SHIFT (5U)
  1563. #define CSL_EVETPCC_QEMR_E5_RESETVAL (0x00000000U)
  1564. #define CSL_EVETPCC_QEMR_E5_MAX (0x00000001U)
  1565. #define CSL_EVETPCC_QEMR_E4_MASK (0x00000010U)
  1566. #define CSL_EVETPCC_QEMR_E4_SHIFT (4U)
  1567. #define CSL_EVETPCC_QEMR_E4_RESETVAL (0x00000000U)
  1568. #define CSL_EVETPCC_QEMR_E4_MAX (0x00000001U)
  1569. #define CSL_EVETPCC_QEMR_E3_MASK (0x00000008U)
  1570. #define CSL_EVETPCC_QEMR_E3_SHIFT (3U)
  1571. #define CSL_EVETPCC_QEMR_E3_RESETVAL (0x00000000U)
  1572. #define CSL_EVETPCC_QEMR_E3_MAX (0x00000001U)
  1573. #define CSL_EVETPCC_QEMR_E2_MASK (0x00000004U)
  1574. #define CSL_EVETPCC_QEMR_E2_SHIFT (2U)
  1575. #define CSL_EVETPCC_QEMR_E2_RESETVAL (0x00000000U)
  1576. #define CSL_EVETPCC_QEMR_E2_MAX (0x00000001U)
  1577. #define CSL_EVETPCC_QEMR_E1_MASK (0x00000002U)
  1578. #define CSL_EVETPCC_QEMR_E1_SHIFT (1U)
  1579. #define CSL_EVETPCC_QEMR_E1_RESETVAL (0x00000000U)
  1580. #define CSL_EVETPCC_QEMR_E1_MAX (0x00000001U)
  1581. #define CSL_EVETPCC_QEMR_E0_MASK (0x00000001U)
  1582. #define CSL_EVETPCC_QEMR_E0_SHIFT (0U)
  1583. #define CSL_EVETPCC_QEMR_E0_RESETVAL (0x00000000U)
  1584. #define CSL_EVETPCC_QEMR_E0_MAX (0x00000001U)
  1585. #define CSL_EVETPCC_QEMR_RESETVAL (0x00000000U)
  1586. /* QEMCR */
  1587. #define CSL_EVETPCC_QEMCR_E7_MASK (0x00000080U)
  1588. #define CSL_EVETPCC_QEMCR_E7_SHIFT (7U)
  1589. #define CSL_EVETPCC_QEMCR_E7_RESETVAL (0x00000000U)
  1590. #define CSL_EVETPCC_QEMCR_E7_MAX (0x00000001U)
  1591. #define CSL_EVETPCC_QEMCR_E6_MASK (0x00000040U)
  1592. #define CSL_EVETPCC_QEMCR_E6_SHIFT (6U)
  1593. #define CSL_EVETPCC_QEMCR_E6_RESETVAL (0x00000000U)
  1594. #define CSL_EVETPCC_QEMCR_E6_MAX (0x00000001U)
  1595. #define CSL_EVETPCC_QEMCR_E5_MASK (0x00000020U)
  1596. #define CSL_EVETPCC_QEMCR_E5_SHIFT (5U)
  1597. #define CSL_EVETPCC_QEMCR_E5_RESETVAL (0x00000000U)
  1598. #define CSL_EVETPCC_QEMCR_E5_MAX (0x00000001U)
  1599. #define CSL_EVETPCC_QEMCR_E4_MASK (0x00000010U)
  1600. #define CSL_EVETPCC_QEMCR_E4_SHIFT (4U)
  1601. #define CSL_EVETPCC_QEMCR_E4_RESETVAL (0x00000000U)
  1602. #define CSL_EVETPCC_QEMCR_E4_MAX (0x00000001U)
  1603. #define CSL_EVETPCC_QEMCR_E3_MASK (0x00000008U)
  1604. #define CSL_EVETPCC_QEMCR_E3_SHIFT (3U)
  1605. #define CSL_EVETPCC_QEMCR_E3_RESETVAL (0x00000000U)
  1606. #define CSL_EVETPCC_QEMCR_E3_MAX (0x00000001U)
  1607. #define CSL_EVETPCC_QEMCR_E2_MASK (0x00000004U)
  1608. #define CSL_EVETPCC_QEMCR_E2_SHIFT (2U)
  1609. #define CSL_EVETPCC_QEMCR_E2_RESETVAL (0x00000000U)
  1610. #define CSL_EVETPCC_QEMCR_E2_MAX (0x00000001U)
  1611. #define CSL_EVETPCC_QEMCR_E1_MASK (0x00000002U)
  1612. #define CSL_EVETPCC_QEMCR_E1_SHIFT (1U)
  1613. #define CSL_EVETPCC_QEMCR_E1_RESETVAL (0x00000000U)
  1614. #define CSL_EVETPCC_QEMCR_E1_MAX (0x00000001U)
  1615. #define CSL_EVETPCC_QEMCR_E0_MASK (0x00000001U)
  1616. #define CSL_EVETPCC_QEMCR_E0_SHIFT (0U)
  1617. #define CSL_EVETPCC_QEMCR_E0_RESETVAL (0x00000000U)
  1618. #define CSL_EVETPCC_QEMCR_E0_MAX (0x00000001U)
  1619. #define CSL_EVETPCC_QEMCR_RESETVAL (0x00000000U)
  1620. /* CCERR */
  1621. #define CSL_EVETPCC_CCERR_QTHRXCD0_MASK (0x00000001U)
  1622. #define CSL_EVETPCC_CCERR_QTHRXCD0_SHIFT (0U)
  1623. #define CSL_EVETPCC_CCERR_QTHRXCD0_RESETVAL (0x00000000U)
  1624. #define CSL_EVETPCC_CCERR_QTHRXCD0_MAX (0x00000001U)
  1625. #define CSL_EVETPCC_CCERR_TCERR_MASK (0x00010000U)
  1626. #define CSL_EVETPCC_CCERR_TCERR_SHIFT (16U)
  1627. #define CSL_EVETPCC_CCERR_TCERR_RESETVAL (0x00000000U)
  1628. #define CSL_EVETPCC_CCERR_TCERR_MAX (0x00000001U)
  1629. #define CSL_EVETPCC_CCERR_QTHRXCD1_MASK (0x00000002U)
  1630. #define CSL_EVETPCC_CCERR_QTHRXCD1_SHIFT (1U)
  1631. #define CSL_EVETPCC_CCERR_QTHRXCD1_RESETVAL (0x00000000U)
  1632. #define CSL_EVETPCC_CCERR_QTHRXCD1_MAX (0x00000001U)
  1633. #define CSL_EVETPCC_CCERR_QTHRXCD2_MASK (0x00000004U)
  1634. #define CSL_EVETPCC_CCERR_QTHRXCD2_SHIFT (2U)
  1635. #define CSL_EVETPCC_CCERR_QTHRXCD2_RESETVAL (0x00000000U)
  1636. #define CSL_EVETPCC_CCERR_QTHRXCD2_MAX (0x00000001U)
  1637. #define CSL_EVETPCC_CCERR_QTHRXCD3_MASK (0x00000008U)
  1638. #define CSL_EVETPCC_CCERR_QTHRXCD3_SHIFT (3U)
  1639. #define CSL_EVETPCC_CCERR_QTHRXCD3_RESETVAL (0x00000000U)
  1640. #define CSL_EVETPCC_CCERR_QTHRXCD3_MAX (0x00000001U)
  1641. #define CSL_EVETPCC_CCERR_QTHRXCD4_MASK (0x00000010U)
  1642. #define CSL_EVETPCC_CCERR_QTHRXCD4_SHIFT (4U)
  1643. #define CSL_EVETPCC_CCERR_QTHRXCD4_RESETVAL (0x00000000U)
  1644. #define CSL_EVETPCC_CCERR_QTHRXCD4_MAX (0x00000001U)
  1645. #define CSL_EVETPCC_CCERR_QTHRXCD5_MASK (0x00000020U)
  1646. #define CSL_EVETPCC_CCERR_QTHRXCD5_SHIFT (5U)
  1647. #define CSL_EVETPCC_CCERR_QTHRXCD5_RESETVAL (0x00000000U)
  1648. #define CSL_EVETPCC_CCERR_QTHRXCD5_MAX (0x00000001U)
  1649. #define CSL_EVETPCC_CCERR_QTHRXCD6_MASK (0x00000040U)
  1650. #define CSL_EVETPCC_CCERR_QTHRXCD6_SHIFT (6U)
  1651. #define CSL_EVETPCC_CCERR_QTHRXCD6_RESETVAL (0x00000000U)
  1652. #define CSL_EVETPCC_CCERR_QTHRXCD6_MAX (0x00000001U)
  1653. #define CSL_EVETPCC_CCERR_QTHRXCD7_MASK (0x00000080U)
  1654. #define CSL_EVETPCC_CCERR_QTHRXCD7_SHIFT (7U)
  1655. #define CSL_EVETPCC_CCERR_QTHRXCD7_RESETVAL (0x00000000U)
  1656. #define CSL_EVETPCC_CCERR_QTHRXCD7_MAX (0x00000001U)
  1657. #define CSL_EVETPCC_CCERR_RESETVAL (0x00000000U)
  1658. /* CCERRCLR */
  1659. #define CSL_EVETPCC_CCERRCLR_QTHRXCD0_MASK (0x00000001U)
  1660. #define CSL_EVETPCC_CCERRCLR_QTHRXCD0_SHIFT (0U)
  1661. #define CSL_EVETPCC_CCERRCLR_QTHRXCD0_RESETVAL (0x00000000U)
  1662. #define CSL_EVETPCC_CCERRCLR_QTHRXCD0_MAX (0x00000001U)
  1663. #define CSL_EVETPCC_CCERRCLR_QTHRXCD1_MASK (0x00000002U)
  1664. #define CSL_EVETPCC_CCERRCLR_QTHRXCD1_SHIFT (1U)
  1665. #define CSL_EVETPCC_CCERRCLR_QTHRXCD1_RESETVAL (0x00000000U)
  1666. #define CSL_EVETPCC_CCERRCLR_QTHRXCD1_MAX (0x00000001U)
  1667. #define CSL_EVETPCC_CCERRCLR_QTHRXCD2_MASK (0x00000004U)
  1668. #define CSL_EVETPCC_CCERRCLR_QTHRXCD2_SHIFT (2U)
  1669. #define CSL_EVETPCC_CCERRCLR_QTHRXCD2_RESETVAL (0x00000000U)
  1670. #define CSL_EVETPCC_CCERRCLR_QTHRXCD2_MAX (0x00000001U)
  1671. #define CSL_EVETPCC_CCERRCLR_QTHRXCD3_MASK (0x00000008U)
  1672. #define CSL_EVETPCC_CCERRCLR_QTHRXCD3_SHIFT (3U)
  1673. #define CSL_EVETPCC_CCERRCLR_QTHRXCD3_RESETVAL (0x00000000U)
  1674. #define CSL_EVETPCC_CCERRCLR_QTHRXCD3_MAX (0x00000001U)
  1675. #define CSL_EVETPCC_CCERRCLR_QTHRXCD4_MASK (0x00000010U)
  1676. #define CSL_EVETPCC_CCERRCLR_QTHRXCD4_SHIFT (4U)
  1677. #define CSL_EVETPCC_CCERRCLR_QTHRXCD4_RESETVAL (0x00000000U)
  1678. #define CSL_EVETPCC_CCERRCLR_QTHRXCD4_MAX (0x00000001U)
  1679. #define CSL_EVETPCC_CCERRCLR_QTHRXCD5_MASK (0x00000020U)
  1680. #define CSL_EVETPCC_CCERRCLR_QTHRXCD5_SHIFT (5U)
  1681. #define CSL_EVETPCC_CCERRCLR_QTHRXCD5_RESETVAL (0x00000000U)
  1682. #define CSL_EVETPCC_CCERRCLR_QTHRXCD5_MAX (0x00000001U)
  1683. #define CSL_EVETPCC_CCERRCLR_QTHRXCD6_MASK (0x00000040U)
  1684. #define CSL_EVETPCC_CCERRCLR_QTHRXCD6_SHIFT (6U)
  1685. #define CSL_EVETPCC_CCERRCLR_QTHRXCD6_RESETVAL (0x00000000U)
  1686. #define CSL_EVETPCC_CCERRCLR_QTHRXCD6_MAX (0x00000001U)
  1687. #define CSL_EVETPCC_CCERRCLR_QTHRXCD7_MASK (0x00000080U)
  1688. #define CSL_EVETPCC_CCERRCLR_QTHRXCD7_SHIFT (7U)
  1689. #define CSL_EVETPCC_CCERRCLR_QTHRXCD7_RESETVAL (0x00000000U)
  1690. #define CSL_EVETPCC_CCERRCLR_QTHRXCD7_MAX (0x00000001U)
  1691. #define CSL_EVETPCC_CCERRCLR_TCERR_MASK (0x00010000U)
  1692. #define CSL_EVETPCC_CCERRCLR_TCERR_SHIFT (16U)
  1693. #define CSL_EVETPCC_CCERRCLR_TCERR_RESETVAL (0x00000000U)
  1694. #define CSL_EVETPCC_CCERRCLR_TCERR_MAX (0x00000001U)
  1695. #define CSL_EVETPCC_CCERRCLR_RESETVAL (0x00000000U)
  1696. /* EEVAL */
  1697. #define CSL_EVETPCC_EEVAL_SET_MASK (0x00000002U)
  1698. #define CSL_EVETPCC_EEVAL_SET_SHIFT (1U)
  1699. #define CSL_EVETPCC_EEVAL_SET_RESETVAL (0x00000000U)
  1700. #define CSL_EVETPCC_EEVAL_SET_MAX (0x00000001U)
  1701. #define CSL_EVETPCC_EEVAL_EVAL_MASK (0x00000001U)
  1702. #define CSL_EVETPCC_EEVAL_EVAL_SHIFT (0U)
  1703. #define CSL_EVETPCC_EEVAL_EVAL_RESETVAL (0x00000000U)
  1704. #define CSL_EVETPCC_EEVAL_EVAL_MAX (0x00000001U)
  1705. #define CSL_EVETPCC_EEVAL_RESETVAL (0x00000000U)
  1706. /* QRAEN */
  1707. #define CSL_EVETPCC_QRAEN_E3_MASK (0x00000008U)
  1708. #define CSL_EVETPCC_QRAEN_E3_SHIFT (3U)
  1709. #define CSL_EVETPCC_QRAEN_E3_RESETVAL (0x00000000U)
  1710. #define CSL_EVETPCC_QRAEN_E3_MAX (0x00000001U)
  1711. #define CSL_EVETPCC_QRAEN_E4_MASK (0x00000010U)
  1712. #define CSL_EVETPCC_QRAEN_E4_SHIFT (4U)
  1713. #define CSL_EVETPCC_QRAEN_E4_RESETVAL (0x00000000U)
  1714. #define CSL_EVETPCC_QRAEN_E4_MAX (0x00000001U)
  1715. #define CSL_EVETPCC_QRAEN_E5_MASK (0x00000020U)
  1716. #define CSL_EVETPCC_QRAEN_E5_SHIFT (5U)
  1717. #define CSL_EVETPCC_QRAEN_E5_RESETVAL (0x00000000U)
  1718. #define CSL_EVETPCC_QRAEN_E5_MAX (0x00000001U)
  1719. #define CSL_EVETPCC_QRAEN_E1_MASK (0x00000002U)
  1720. #define CSL_EVETPCC_QRAEN_E1_SHIFT (1U)
  1721. #define CSL_EVETPCC_QRAEN_E1_RESETVAL (0x00000000U)
  1722. #define CSL_EVETPCC_QRAEN_E1_MAX (0x00000001U)
  1723. #define CSL_EVETPCC_QRAEN_E7_MASK (0x00000080U)
  1724. #define CSL_EVETPCC_QRAEN_E7_SHIFT (7U)
  1725. #define CSL_EVETPCC_QRAEN_E7_RESETVAL (0x00000000U)
  1726. #define CSL_EVETPCC_QRAEN_E7_MAX (0x00000001U)
  1727. #define CSL_EVETPCC_QRAEN_E0_MASK (0x00000001U)
  1728. #define CSL_EVETPCC_QRAEN_E0_SHIFT (0U)
  1729. #define CSL_EVETPCC_QRAEN_E0_RESETVAL (0x00000000U)
  1730. #define CSL_EVETPCC_QRAEN_E0_MAX (0x00000001U)
  1731. #define CSL_EVETPCC_QRAEN_E6_MASK (0x00000040U)
  1732. #define CSL_EVETPCC_QRAEN_E6_SHIFT (6U)
  1733. #define CSL_EVETPCC_QRAEN_E6_RESETVAL (0x00000000U)
  1734. #define CSL_EVETPCC_QRAEN_E6_MAX (0x00000001U)
  1735. #define CSL_EVETPCC_QRAEN_E2_MASK (0x00000004U)
  1736. #define CSL_EVETPCC_QRAEN_E2_SHIFT (2U)
  1737. #define CSL_EVETPCC_QRAEN_E2_RESETVAL (0x00000000U)
  1738. #define CSL_EVETPCC_QRAEN_E2_MAX (0x00000001U)
  1739. #define CSL_EVETPCC_QRAEN_RESETVAL (0x00000000U)
  1740. /* QSTATN */
  1741. #define CSL_EVETPCC_QSTATN_STRTPTR_MASK (0x0000000FU)
  1742. #define CSL_EVETPCC_QSTATN_STRTPTR_SHIFT (0U)
  1743. #define CSL_EVETPCC_QSTATN_STRTPTR_RESETVAL (0x00000000U)
  1744. #define CSL_EVETPCC_QSTATN_STRTPTR_MAX (0x0000000fU)
  1745. #define CSL_EVETPCC_QSTATN_NUMVAL_MASK (0x00001F00U)
  1746. #define CSL_EVETPCC_QSTATN_NUMVAL_SHIFT (8U)
  1747. #define CSL_EVETPCC_QSTATN_NUMVAL_RESETVAL (0x00000000U)
  1748. #define CSL_EVETPCC_QSTATN_NUMVAL_MAX (0x0000001fU)
  1749. #define CSL_EVETPCC_QSTATN_WM_MASK (0x001F0000U)
  1750. #define CSL_EVETPCC_QSTATN_WM_SHIFT (16U)
  1751. #define CSL_EVETPCC_QSTATN_WM_RESETVAL (0x00000000U)
  1752. #define CSL_EVETPCC_QSTATN_WM_MAX (0x0000001fU)
  1753. #define CSL_EVETPCC_QSTATN_THRXCD_MASK (0x01000000U)
  1754. #define CSL_EVETPCC_QSTATN_THRXCD_SHIFT (24U)
  1755. #define CSL_EVETPCC_QSTATN_THRXCD_RESETVAL (0x00000000U)
  1756. #define CSL_EVETPCC_QSTATN_THRXCD_MAX (0x00000001U)
  1757. #define CSL_EVETPCC_QSTATN_RESETVAL (0x00000000U)
  1758. /* QWMTHRA */
  1759. #define CSL_EVETPCC_QWMTHRA_Q1_MASK (0x00001F00U)
  1760. #define CSL_EVETPCC_QWMTHRA_Q1_SHIFT (8U)
  1761. #define CSL_EVETPCC_QWMTHRA_Q1_RESETVAL (0x00000010U)
  1762. #define CSL_EVETPCC_QWMTHRA_Q1_MAX (0x0000001fU)
  1763. #define CSL_EVETPCC_QWMTHRA_Q0_MASK (0x0000001FU)
  1764. #define CSL_EVETPCC_QWMTHRA_Q0_SHIFT (0U)
  1765. #define CSL_EVETPCC_QWMTHRA_Q0_RESETVAL (0x00000010U)
  1766. #define CSL_EVETPCC_QWMTHRA_Q0_MAX (0x0000001fU)
  1767. #define CSL_EVETPCC_QWMTHRA_Q3_MASK (0x1F000000U)
  1768. #define CSL_EVETPCC_QWMTHRA_Q3_SHIFT (24U)
  1769. #define CSL_EVETPCC_QWMTHRA_Q3_RESETVAL (0x00000010U)
  1770. #define CSL_EVETPCC_QWMTHRA_Q3_MAX (0x0000001fU)
  1771. #define CSL_EVETPCC_QWMTHRA_Q2_MASK (0x001F0000U)
  1772. #define CSL_EVETPCC_QWMTHRA_Q2_SHIFT (16U)
  1773. #define CSL_EVETPCC_QWMTHRA_Q2_RESETVAL (0x00000010U)
  1774. #define CSL_EVETPCC_QWMTHRA_Q2_MAX (0x0000001fU)
  1775. #define CSL_EVETPCC_QWMTHRA_RESETVAL (0x10101010U)
  1776. /* QWMTHRB */
  1777. #define CSL_EVETPCC_QWMTHRB_Q6_MASK (0x001F0000U)
  1778. #define CSL_EVETPCC_QWMTHRB_Q6_SHIFT (16U)
  1779. #define CSL_EVETPCC_QWMTHRB_Q6_RESETVAL (0x00000010U)
  1780. #define CSL_EVETPCC_QWMTHRB_Q6_MAX (0x0000001fU)
  1781. #define CSL_EVETPCC_QWMTHRB_Q7_MASK (0x1F000000U)
  1782. #define CSL_EVETPCC_QWMTHRB_Q7_SHIFT (24U)
  1783. #define CSL_EVETPCC_QWMTHRB_Q7_RESETVAL (0x00000010U)
  1784. #define CSL_EVETPCC_QWMTHRB_Q7_MAX (0x0000001fU)
  1785. #define CSL_EVETPCC_QWMTHRB_Q4_MASK (0x0000001FU)
  1786. #define CSL_EVETPCC_QWMTHRB_Q4_SHIFT (0U)
  1787. #define CSL_EVETPCC_QWMTHRB_Q4_RESETVAL (0x00000010U)
  1788. #define CSL_EVETPCC_QWMTHRB_Q4_MAX (0x0000001fU)
  1789. #define CSL_EVETPCC_QWMTHRB_Q5_MASK (0x00001F00U)
  1790. #define CSL_EVETPCC_QWMTHRB_Q5_SHIFT (8U)
  1791. #define CSL_EVETPCC_QWMTHRB_Q5_RESETVAL (0x00000010U)
  1792. #define CSL_EVETPCC_QWMTHRB_Q5_MAX (0x0000001fU)
  1793. #define CSL_EVETPCC_QWMTHRB_RESETVAL (0x10101010U)
  1794. /* CCSTAT */
  1795. #define CSL_EVETPCC_CCSTAT_EVTACTV_MASK (0x00000001U)
  1796. #define CSL_EVETPCC_CCSTAT_EVTACTV_SHIFT (0U)
  1797. #define CSL_EVETPCC_CCSTAT_EVTACTV_RESETVAL (0x00000000U)
  1798. #define CSL_EVETPCC_CCSTAT_EVTACTV_MAX (0x00000001U)
  1799. #define CSL_EVETPCC_CCSTAT_QEVTACTV_MASK (0x00000002U)
  1800. #define CSL_EVETPCC_CCSTAT_QEVTACTV_SHIFT (1U)
  1801. #define CSL_EVETPCC_CCSTAT_QEVTACTV_RESETVAL (0x00000000U)
  1802. #define CSL_EVETPCC_CCSTAT_QEVTACTV_MAX (0x00000001U)
  1803. #define CSL_EVETPCC_CCSTAT_TRACTV_MASK (0x00000004U)
  1804. #define CSL_EVETPCC_CCSTAT_TRACTV_SHIFT (2U)
  1805. #define CSL_EVETPCC_CCSTAT_TRACTV_RESETVAL (0x00000000U)
  1806. #define CSL_EVETPCC_CCSTAT_TRACTV_MAX (0x00000001U)
  1807. #define CSL_EVETPCC_CCSTAT_ACTV_MASK (0x00000010U)
  1808. #define CSL_EVETPCC_CCSTAT_ACTV_SHIFT (4U)
  1809. #define CSL_EVETPCC_CCSTAT_ACTV_RESETVAL (0x00000000U)
  1810. #define CSL_EVETPCC_CCSTAT_ACTV_MAX (0x00000001U)
  1811. #define CSL_EVETPCC_CCSTAT_COMPACTV_MASK (0x00003F00U)
  1812. #define CSL_EVETPCC_CCSTAT_COMPACTV_SHIFT (8U)
  1813. #define CSL_EVETPCC_CCSTAT_COMPACTV_RESETVAL (0x00000000U)
  1814. #define CSL_EVETPCC_CCSTAT_COMPACTV_MAX (0x0000003fU)
  1815. #define CSL_EVETPCC_CCSTAT_QUEACTV0_MASK (0x00010000U)
  1816. #define CSL_EVETPCC_CCSTAT_QUEACTV0_SHIFT (16U)
  1817. #define CSL_EVETPCC_CCSTAT_QUEACTV0_RESETVAL (0x00000000U)
  1818. #define CSL_EVETPCC_CCSTAT_QUEACTV0_MAX (0x00000001U)
  1819. #define CSL_EVETPCC_CCSTAT_QUEACTV1_MASK (0x00020000U)
  1820. #define CSL_EVETPCC_CCSTAT_QUEACTV1_SHIFT (17U)
  1821. #define CSL_EVETPCC_CCSTAT_QUEACTV1_RESETVAL (0x00000000U)
  1822. #define CSL_EVETPCC_CCSTAT_QUEACTV1_MAX (0x00000001U)
  1823. #define CSL_EVETPCC_CCSTAT_QUEACTV2_MASK (0x00040000U)
  1824. #define CSL_EVETPCC_CCSTAT_QUEACTV2_SHIFT (18U)
  1825. #define CSL_EVETPCC_CCSTAT_QUEACTV2_RESETVAL (0x00000000U)
  1826. #define CSL_EVETPCC_CCSTAT_QUEACTV2_MAX (0x00000001U)
  1827. #define CSL_EVETPCC_CCSTAT_QUEACTV3_MASK (0x00080000U)
  1828. #define CSL_EVETPCC_CCSTAT_QUEACTV3_SHIFT (19U)
  1829. #define CSL_EVETPCC_CCSTAT_QUEACTV3_RESETVAL (0x00000000U)
  1830. #define CSL_EVETPCC_CCSTAT_QUEACTV3_MAX (0x00000001U)
  1831. #define CSL_EVETPCC_CCSTAT_QUEACTV4_MASK (0x00100000U)
  1832. #define CSL_EVETPCC_CCSTAT_QUEACTV4_SHIFT (20U)
  1833. #define CSL_EVETPCC_CCSTAT_QUEACTV4_RESETVAL (0x00000000U)
  1834. #define CSL_EVETPCC_CCSTAT_QUEACTV4_MAX (0x00000001U)
  1835. #define CSL_EVETPCC_CCSTAT_QUEACTV5_MASK (0x00200000U)
  1836. #define CSL_EVETPCC_CCSTAT_QUEACTV5_SHIFT (21U)
  1837. #define CSL_EVETPCC_CCSTAT_QUEACTV5_RESETVAL (0x00000000U)
  1838. #define CSL_EVETPCC_CCSTAT_QUEACTV5_MAX (0x00000001U)
  1839. #define CSL_EVETPCC_CCSTAT_QUEACTV6_MASK (0x00400000U)
  1840. #define CSL_EVETPCC_CCSTAT_QUEACTV6_SHIFT (22U)
  1841. #define CSL_EVETPCC_CCSTAT_QUEACTV6_RESETVAL (0x00000000U)
  1842. #define CSL_EVETPCC_CCSTAT_QUEACTV6_MAX (0x00000001U)
  1843. #define CSL_EVETPCC_CCSTAT_QUEACTV7_MASK (0x00800000U)
  1844. #define CSL_EVETPCC_CCSTAT_QUEACTV7_SHIFT (23U)
  1845. #define CSL_EVETPCC_CCSTAT_QUEACTV7_RESETVAL (0x00000000U)
  1846. #define CSL_EVETPCC_CCSTAT_QUEACTV7_MAX (0x00000001U)
  1847. #define CSL_EVETPCC_CCSTAT_RESETVAL (0x00000000U)
  1848. /* AETCTL */
  1849. #define CSL_EVETPCC_AETCTL_TYPE_MASK (0x00000040U)
  1850. #define CSL_EVETPCC_AETCTL_TYPE_SHIFT (6U)
  1851. #define CSL_EVETPCC_AETCTL_TYPE_RESETVAL (0x00000000U)
  1852. #define CSL_EVETPCC_AETCTL_TYPE_MAX (0x00000001U)
  1853. #define CSL_EVETPCC_AETCTL_STRTEVT_MASK (0x0000003FU)
  1854. #define CSL_EVETPCC_AETCTL_STRTEVT_SHIFT (0U)
  1855. #define CSL_EVETPCC_AETCTL_STRTEVT_RESETVAL (0x00000000U)
  1856. #define CSL_EVETPCC_AETCTL_STRTEVT_MAX (0x0000003fU)
  1857. #define CSL_EVETPCC_AETCTL_EN_MASK (0x80000000U)
  1858. #define CSL_EVETPCC_AETCTL_EN_SHIFT (31U)
  1859. #define CSL_EVETPCC_AETCTL_EN_RESETVAL (0x00000000U)
  1860. #define CSL_EVETPCC_AETCTL_EN_MAX (0x00000001U)
  1861. #define CSL_EVETPCC_AETCTL_ENDINT_MASK (0x00003F00U)
  1862. #define CSL_EVETPCC_AETCTL_ENDINT_SHIFT (8U)
  1863. #define CSL_EVETPCC_AETCTL_ENDINT_RESETVAL (0x00000000U)
  1864. #define CSL_EVETPCC_AETCTL_ENDINT_MAX (0x0000003fU)
  1865. #define CSL_EVETPCC_AETCTL_RESETVAL (0x00000000U)
  1866. /* AETSTAT */
  1867. #define CSL_EVETPCC_AETSTAT_STAT_MASK (0x00000001U)
  1868. #define CSL_EVETPCC_AETSTAT_STAT_SHIFT (0U)
  1869. #define CSL_EVETPCC_AETSTAT_STAT_RESETVAL (0x00000000U)
  1870. #define CSL_EVETPCC_AETSTAT_STAT_MAX (0x00000001U)
  1871. #define CSL_EVETPCC_AETSTAT_RESETVAL (0x00000000U)
  1872. /* AETCMD */
  1873. #define CSL_EVETPCC_AETCMD_CLR_MASK (0x00000001U)
  1874. #define CSL_EVETPCC_AETCMD_CLR_SHIFT (0U)
  1875. #define CSL_EVETPCC_AETCMD_CLR_RESETVAL (0x00000000U)
  1876. #define CSL_EVETPCC_AETCMD_CLR_MAX (0x00000001U)
  1877. #define CSL_EVETPCC_AETCMD_RESETVAL (0x00000000U)
  1878. /* MPFAR */
  1879. #define CSL_EVETPCC_MPFAR_FADDR_MASK (0xFFFFFFFFU)
  1880. #define CSL_EVETPCC_MPFAR_FADDR_SHIFT (0U)
  1881. #define CSL_EVETPCC_MPFAR_FADDR_RESETVAL (0x00000000U)
  1882. #define CSL_EVETPCC_MPFAR_FADDR_MAX (0xffffffffU)
  1883. #define CSL_EVETPCC_MPFAR_RESETVAL (0x00000000U)
  1884. /* MPFSR */
  1885. #define CSL_EVETPCC_MPFSR_FID_MASK (0x00001E00U)
  1886. #define CSL_EVETPCC_MPFSR_FID_SHIFT (9U)
  1887. #define CSL_EVETPCC_MPFSR_FID_RESETVAL (0x00000000U)
  1888. #define CSL_EVETPCC_MPFSR_FID_MAX (0x0000000fU)
  1889. #define CSL_EVETPCC_MPFSR_SECE_MASK (0x00000080U)
  1890. #define CSL_EVETPCC_MPFSR_SECE_SHIFT (7U)
  1891. #define CSL_EVETPCC_MPFSR_SECE_RESETVAL (0x00000000U)
  1892. #define CSL_EVETPCC_MPFSR_SECE_MAX (0x00000001U)
  1893. #define CSL_EVETPCC_MPFSR_SXE_MASK (0x00000008U)
  1894. #define CSL_EVETPCC_MPFSR_SXE_SHIFT (3U)
  1895. #define CSL_EVETPCC_MPFSR_SXE_RESETVAL (0x00000000U)
  1896. #define CSL_EVETPCC_MPFSR_SXE_MAX (0x00000001U)
  1897. #define CSL_EVETPCC_MPFSR_URE_MASK (0x00000004U)
  1898. #define CSL_EVETPCC_MPFSR_URE_SHIFT (2U)
  1899. #define CSL_EVETPCC_MPFSR_URE_RESETVAL (0x00000000U)
  1900. #define CSL_EVETPCC_MPFSR_URE_MAX (0x00000001U)
  1901. #define CSL_EVETPCC_MPFSR_SRE_MASK (0x00000020U)
  1902. #define CSL_EVETPCC_MPFSR_SRE_SHIFT (5U)
  1903. #define CSL_EVETPCC_MPFSR_SRE_RESETVAL (0x00000000U)
  1904. #define CSL_EVETPCC_MPFSR_SRE_MAX (0x00000001U)
  1905. #define CSL_EVETPCC_MPFSR_SWE_MASK (0x00000010U)
  1906. #define CSL_EVETPCC_MPFSR_SWE_SHIFT (4U)
  1907. #define CSL_EVETPCC_MPFSR_SWE_RESETVAL (0x00000000U)
  1908. #define CSL_EVETPCC_MPFSR_SWE_MAX (0x00000001U)
  1909. #define CSL_EVETPCC_MPFSR_UWE_MASK (0x00000002U)
  1910. #define CSL_EVETPCC_MPFSR_UWE_SHIFT (1U)
  1911. #define CSL_EVETPCC_MPFSR_UWE_RESETVAL (0x00000000U)
  1912. #define CSL_EVETPCC_MPFSR_UWE_MAX (0x00000001U)
  1913. #define CSL_EVETPCC_MPFSR_UXE_MASK (0x00000001U)
  1914. #define CSL_EVETPCC_MPFSR_UXE_SHIFT (0U)
  1915. #define CSL_EVETPCC_MPFSR_UXE_RESETVAL (0x00000000U)
  1916. #define CSL_EVETPCC_MPFSR_UXE_MAX (0x00000001U)
  1917. #define CSL_EVETPCC_MPFSR_RESETVAL (0x00000000U)
  1918. /* MPFCR */
  1919. #define CSL_EVETPCC_MPFCR_MPFCLR_MASK (0x00000001U)
  1920. #define CSL_EVETPCC_MPFCR_MPFCLR_SHIFT (0U)
  1921. #define CSL_EVETPCC_MPFCR_MPFCLR_RESETVAL (0x00000000U)
  1922. #define CSL_EVETPCC_MPFCR_MPFCLR_MAX (0x00000001U)
  1923. #define CSL_EVETPCC_MPFCR_RESETVAL (0x00000000U)
  1924. /* MPPAG */
  1925. #define CSL_EVETPCC_MPPAG_EMU_MASK (0x00000040U)
  1926. #define CSL_EVETPCC_MPPAG_EMU_SHIFT (6U)
  1927. #define CSL_EVETPCC_MPPAG_EMU_RESETVAL (0x00000001U)
  1928. #define CSL_EVETPCC_MPPAG_EMU_MAX (0x00000001U)
  1929. #define CSL_EVETPCC_MPPAG_EXT_MASK (0x00000200U)
  1930. #define CSL_EVETPCC_MPPAG_EXT_SHIFT (9U)
  1931. #define CSL_EVETPCC_MPPAG_EXT_RESETVAL (0x00000001U)
  1932. #define CSL_EVETPCC_MPPAG_EXT_MAX (0x00000001U)
  1933. #define CSL_EVETPCC_MPPAG_SR_MASK (0x00000020U)
  1934. #define CSL_EVETPCC_MPPAG_SR_SHIFT (5U)
  1935. #define CSL_EVETPCC_MPPAG_SR_RESETVAL (0x00000001U)
  1936. #define CSL_EVETPCC_MPPAG_SR_MAX (0x00000001U)
  1937. #define CSL_EVETPCC_MPPAG_AID4_MASK (0x00004000U)
  1938. #define CSL_EVETPCC_MPPAG_AID4_SHIFT (14U)
  1939. #define CSL_EVETPCC_MPPAG_AID4_RESETVAL (0x00000001U)
  1940. #define CSL_EVETPCC_MPPAG_AID4_MAX (0x00000001U)
  1941. #define CSL_EVETPCC_MPPAG_UR_MASK (0x00000004U)
  1942. #define CSL_EVETPCC_MPPAG_UR_SHIFT (2U)
  1943. #define CSL_EVETPCC_MPPAG_UR_RESETVAL (0x00000001U)
  1944. #define CSL_EVETPCC_MPPAG_UR_MAX (0x00000001U)
  1945. #define CSL_EVETPCC_MPPAG_AID5_MASK (0x00008000U)
  1946. #define CSL_EVETPCC_MPPAG_AID5_SHIFT (15U)
  1947. #define CSL_EVETPCC_MPPAG_AID5_RESETVAL (0x00000001U)
  1948. #define CSL_EVETPCC_MPPAG_AID5_MAX (0x00000001U)
  1949. #define CSL_EVETPCC_MPPAG_NS_MASK (0x00000080U)
  1950. #define CSL_EVETPCC_MPPAG_NS_SHIFT (7U)
  1951. #define CSL_EVETPCC_MPPAG_NS_RESETVAL (0x00000001U)
  1952. #define CSL_EVETPCC_MPPAG_NS_MAX (0x00000001U)
  1953. #define CSL_EVETPCC_MPPAG_SW_MASK (0x00000010U)
  1954. #define CSL_EVETPCC_MPPAG_SW_SHIFT (4U)
  1955. #define CSL_EVETPCC_MPPAG_SW_RESETVAL (0x00000001U)
  1956. #define CSL_EVETPCC_MPPAG_SW_MAX (0x00000001U)
  1957. #define CSL_EVETPCC_MPPAG_UW_MASK (0x00000002U)
  1958. #define CSL_EVETPCC_MPPAG_UW_SHIFT (1U)
  1959. #define CSL_EVETPCC_MPPAG_UW_RESETVAL (0x00000001U)
  1960. #define CSL_EVETPCC_MPPAG_UW_MAX (0x00000001U)
  1961. #define CSL_EVETPCC_MPPAG_AID0_MASK (0x00000400U)
  1962. #define CSL_EVETPCC_MPPAG_AID0_SHIFT (10U)
  1963. #define CSL_EVETPCC_MPPAG_AID0_RESETVAL (0x00000001U)
  1964. #define CSL_EVETPCC_MPPAG_AID0_MAX (0x00000001U)
  1965. #define CSL_EVETPCC_MPPAG_AID1_MASK (0x00000800U)
  1966. #define CSL_EVETPCC_MPPAG_AID1_SHIFT (11U)
  1967. #define CSL_EVETPCC_MPPAG_AID1_RESETVAL (0x00000001U)
  1968. #define CSL_EVETPCC_MPPAG_AID1_MAX (0x00000001U)
  1969. #define CSL_EVETPCC_MPPAG_SX_MASK (0x00000008U)
  1970. #define CSL_EVETPCC_MPPAG_SX_SHIFT (3U)
  1971. #define CSL_EVETPCC_MPPAG_SX_RESETVAL (0x00000000U)
  1972. #define CSL_EVETPCC_MPPAG_SX_MAX (0x00000001U)
  1973. #define CSL_EVETPCC_MPPAG_AID2_MASK (0x00001000U)
  1974. #define CSL_EVETPCC_MPPAG_AID2_SHIFT (12U)
  1975. #define CSL_EVETPCC_MPPAG_AID2_RESETVAL (0x00000001U)
  1976. #define CSL_EVETPCC_MPPAG_AID2_MAX (0x00000001U)
  1977. #define CSL_EVETPCC_MPPAG_UX_MASK (0x00000001U)
  1978. #define CSL_EVETPCC_MPPAG_UX_SHIFT (0U)
  1979. #define CSL_EVETPCC_MPPAG_UX_RESETVAL (0x00000000U)
  1980. #define CSL_EVETPCC_MPPAG_UX_MAX (0x00000001U)
  1981. #define CSL_EVETPCC_MPPAG_AID3_MASK (0x00002000U)
  1982. #define CSL_EVETPCC_MPPAG_AID3_SHIFT (13U)
  1983. #define CSL_EVETPCC_MPPAG_AID3_RESETVAL (0x00000001U)
  1984. #define CSL_EVETPCC_MPPAG_AID3_MAX (0x00000001U)
  1985. #define CSL_EVETPCC_MPPAG_RESETVAL (0x0000fff6U)
  1986. /* MPPAN */
  1987. #define CSL_EVETPCC_MPPAN_AID5_MASK (0x00008000U)
  1988. #define CSL_EVETPCC_MPPAN_AID5_SHIFT (15U)
  1989. #define CSL_EVETPCC_MPPAN_AID5_RESETVAL (0x00000001U)
  1990. #define CSL_EVETPCC_MPPAN_AID5_MAX (0x00000001U)
  1991. #define CSL_EVETPCC_MPPAN_AID4_MASK (0x00004000U)
  1992. #define CSL_EVETPCC_MPPAN_AID4_SHIFT (14U)
  1993. #define CSL_EVETPCC_MPPAN_AID4_RESETVAL (0x00000001U)
  1994. #define CSL_EVETPCC_MPPAN_AID4_MAX (0x00000001U)
  1995. #define CSL_EVETPCC_MPPAN_AID3_MASK (0x00002000U)
  1996. #define CSL_EVETPCC_MPPAN_AID3_SHIFT (13U)
  1997. #define CSL_EVETPCC_MPPAN_AID3_RESETVAL (0x00000001U)
  1998. #define CSL_EVETPCC_MPPAN_AID3_MAX (0x00000001U)
  1999. #define CSL_EVETPCC_MPPAN_AID2_MASK (0x00001000U)
  2000. #define CSL_EVETPCC_MPPAN_AID2_SHIFT (12U)
  2001. #define CSL_EVETPCC_MPPAN_AID2_RESETVAL (0x00000001U)
  2002. #define CSL_EVETPCC_MPPAN_AID2_MAX (0x00000001U)
  2003. #define CSL_EVETPCC_MPPAN_AID1_MASK (0x00000800U)
  2004. #define CSL_EVETPCC_MPPAN_AID1_SHIFT (11U)
  2005. #define CSL_EVETPCC_MPPAN_AID1_RESETVAL (0x00000001U)
  2006. #define CSL_EVETPCC_MPPAN_AID1_MAX (0x00000001U)
  2007. #define CSL_EVETPCC_MPPAN_AID0_MASK (0x00000400U)
  2008. #define CSL_EVETPCC_MPPAN_AID0_SHIFT (10U)
  2009. #define CSL_EVETPCC_MPPAN_AID0_RESETVAL (0x00000001U)
  2010. #define CSL_EVETPCC_MPPAN_AID0_MAX (0x00000001U)
  2011. #define CSL_EVETPCC_MPPAN_EXT_MASK (0x00000200U)
  2012. #define CSL_EVETPCC_MPPAN_EXT_SHIFT (9U)
  2013. #define CSL_EVETPCC_MPPAN_EXT_RESETVAL (0x00000001U)
  2014. #define CSL_EVETPCC_MPPAN_EXT_MAX (0x00000001U)
  2015. #define CSL_EVETPCC_MPPAN_NS_MASK (0x00000080U)
  2016. #define CSL_EVETPCC_MPPAN_NS_SHIFT (7U)
  2017. #define CSL_EVETPCC_MPPAN_NS_RESETVAL (0x00000001U)
  2018. #define CSL_EVETPCC_MPPAN_NS_MAX (0x00000001U)
  2019. #define CSL_EVETPCC_MPPAN_EMU_MASK (0x00000040U)
  2020. #define CSL_EVETPCC_MPPAN_EMU_SHIFT (6U)
  2021. #define CSL_EVETPCC_MPPAN_EMU_RESETVAL (0x00000001U)
  2022. #define CSL_EVETPCC_MPPAN_EMU_MAX (0x00000001U)
  2023. #define CSL_EVETPCC_MPPAN_SR_MASK (0x00000020U)
  2024. #define CSL_EVETPCC_MPPAN_SR_SHIFT (5U)
  2025. #define CSL_EVETPCC_MPPAN_SR_RESETVAL (0x00000001U)
  2026. #define CSL_EVETPCC_MPPAN_SR_MAX (0x00000001U)
  2027. #define CSL_EVETPCC_MPPAN_SW_MASK (0x00000010U)
  2028. #define CSL_EVETPCC_MPPAN_SW_SHIFT (4U)
  2029. #define CSL_EVETPCC_MPPAN_SW_RESETVAL (0x00000001U)
  2030. #define CSL_EVETPCC_MPPAN_SW_MAX (0x00000001U)
  2031. #define CSL_EVETPCC_MPPAN_SX_MASK (0x00000008U)
  2032. #define CSL_EVETPCC_MPPAN_SX_SHIFT (3U)
  2033. #define CSL_EVETPCC_MPPAN_SX_RESETVAL (0x00000000U)
  2034. #define CSL_EVETPCC_MPPAN_SX_MAX (0x00000001U)
  2035. #define CSL_EVETPCC_MPPAN_UR_MASK (0x00000004U)
  2036. #define CSL_EVETPCC_MPPAN_UR_SHIFT (2U)
  2037. #define CSL_EVETPCC_MPPAN_UR_RESETVAL (0x00000001U)
  2038. #define CSL_EVETPCC_MPPAN_UR_MAX (0x00000001U)
  2039. #define CSL_EVETPCC_MPPAN_UW_MASK (0x00000002U)
  2040. #define CSL_EVETPCC_MPPAN_UW_SHIFT (1U)
  2041. #define CSL_EVETPCC_MPPAN_UW_RESETVAL (0x00000001U)
  2042. #define CSL_EVETPCC_MPPAN_UW_MAX (0x00000001U)
  2043. #define CSL_EVETPCC_MPPAN_UX_MASK (0x00000001U)
  2044. #define CSL_EVETPCC_MPPAN_UX_SHIFT (0U)
  2045. #define CSL_EVETPCC_MPPAN_UX_RESETVAL (0x00000000U)
  2046. #define CSL_EVETPCC_MPPAN_UX_MAX (0x00000001U)
  2047. #define CSL_EVETPCC_MPPAN_RESETVAL (0x0000fef6U)
  2048. /* ER */
  2049. #define CSL_EVETPCC_ER_E22_MASK (0x00400000U)
  2050. #define CSL_EVETPCC_ER_E22_SHIFT (22U)
  2051. #define CSL_EVETPCC_ER_E22_RESETVAL (0x00000000U)
  2052. #define CSL_EVETPCC_ER_E22_MAX (0x00000001U)
  2053. #define CSL_EVETPCC_ER_E2_MASK (0x00000004U)
  2054. #define CSL_EVETPCC_ER_E2_SHIFT (2U)
  2055. #define CSL_EVETPCC_ER_E2_RESETVAL (0x00000000U)
  2056. #define CSL_EVETPCC_ER_E2_MAX (0x00000001U)
  2057. #define CSL_EVETPCC_ER_E19_MASK (0x00080000U)
  2058. #define CSL_EVETPCC_ER_E19_SHIFT (19U)
  2059. #define CSL_EVETPCC_ER_E19_RESETVAL (0x00000000U)
  2060. #define CSL_EVETPCC_ER_E19_MAX (0x00000001U)
  2061. #define CSL_EVETPCC_ER_E5_MASK (0x00000020U)
  2062. #define CSL_EVETPCC_ER_E5_SHIFT (5U)
  2063. #define CSL_EVETPCC_ER_E5_RESETVAL (0x00000000U)
  2064. #define CSL_EVETPCC_ER_E5_MAX (0x00000001U)
  2065. #define CSL_EVETPCC_ER_E29_MASK (0x20000000U)
  2066. #define CSL_EVETPCC_ER_E29_SHIFT (29U)
  2067. #define CSL_EVETPCC_ER_E29_RESETVAL (0x00000000U)
  2068. #define CSL_EVETPCC_ER_E29_MAX (0x00000001U)
  2069. #define CSL_EVETPCC_ER_E18_MASK (0x00040000U)
  2070. #define CSL_EVETPCC_ER_E18_SHIFT (18U)
  2071. #define CSL_EVETPCC_ER_E18_RESETVAL (0x00000000U)
  2072. #define CSL_EVETPCC_ER_E18_MAX (0x00000001U)
  2073. #define CSL_EVETPCC_ER_E6_MASK (0x00000040U)
  2074. #define CSL_EVETPCC_ER_E6_SHIFT (6U)
  2075. #define CSL_EVETPCC_ER_E6_RESETVAL (0x00000000U)
  2076. #define CSL_EVETPCC_ER_E6_MAX (0x00000001U)
  2077. #define CSL_EVETPCC_ER_E21_MASK (0x00200000U)
  2078. #define CSL_EVETPCC_ER_E21_SHIFT (21U)
  2079. #define CSL_EVETPCC_ER_E21_RESETVAL (0x00000000U)
  2080. #define CSL_EVETPCC_ER_E21_MAX (0x00000001U)
  2081. #define CSL_EVETPCC_ER_E3_MASK (0x00000008U)
  2082. #define CSL_EVETPCC_ER_E3_SHIFT (3U)
  2083. #define CSL_EVETPCC_ER_E3_RESETVAL (0x00000000U)
  2084. #define CSL_EVETPCC_ER_E3_MAX (0x00000001U)
  2085. #define CSL_EVETPCC_ER_E31_MASK (0x80000000U)
  2086. #define CSL_EVETPCC_ER_E31_SHIFT (31U)
  2087. #define CSL_EVETPCC_ER_E31_RESETVAL (0x00000000U)
  2088. #define CSL_EVETPCC_ER_E31_MAX (0x00000001U)
  2089. #define CSL_EVETPCC_ER_E20_MASK (0x00100000U)
  2090. #define CSL_EVETPCC_ER_E20_SHIFT (20U)
  2091. #define CSL_EVETPCC_ER_E20_RESETVAL (0x00000000U)
  2092. #define CSL_EVETPCC_ER_E20_MAX (0x00000001U)
  2093. #define CSL_EVETPCC_ER_E4_MASK (0x00000010U)
  2094. #define CSL_EVETPCC_ER_E4_SHIFT (4U)
  2095. #define CSL_EVETPCC_ER_E4_RESETVAL (0x00000000U)
  2096. #define CSL_EVETPCC_ER_E4_MAX (0x00000001U)
  2097. #define CSL_EVETPCC_ER_E9_MASK (0x00000200U)
  2098. #define CSL_EVETPCC_ER_E9_SHIFT (9U)
  2099. #define CSL_EVETPCC_ER_E9_RESETVAL (0x00000000U)
  2100. #define CSL_EVETPCC_ER_E9_MAX (0x00000001U)
  2101. #define CSL_EVETPCC_ER_E28_MASK (0x10000000U)
  2102. #define CSL_EVETPCC_ER_E28_SHIFT (28U)
  2103. #define CSL_EVETPCC_ER_E28_RESETVAL (0x00000000U)
  2104. #define CSL_EVETPCC_ER_E28_MAX (0x00000001U)
  2105. #define CSL_EVETPCC_ER_E14_MASK (0x00004000U)
  2106. #define CSL_EVETPCC_ER_E14_SHIFT (14U)
  2107. #define CSL_EVETPCC_ER_E14_RESETVAL (0x00000000U)
  2108. #define CSL_EVETPCC_ER_E14_MAX (0x00000001U)
  2109. #define CSL_EVETPCC_ER_E10_MASK (0x00000400U)
  2110. #define CSL_EVETPCC_ER_E10_SHIFT (10U)
  2111. #define CSL_EVETPCC_ER_E10_RESETVAL (0x00000000U)
  2112. #define CSL_EVETPCC_ER_E10_MAX (0x00000001U)
  2113. #define CSL_EVETPCC_ER_E27_MASK (0x08000000U)
  2114. #define CSL_EVETPCC_ER_E27_SHIFT (27U)
  2115. #define CSL_EVETPCC_ER_E27_RESETVAL (0x00000000U)
  2116. #define CSL_EVETPCC_ER_E27_MAX (0x00000001U)
  2117. #define CSL_EVETPCC_ER_E7_MASK (0x00000080U)
  2118. #define CSL_EVETPCC_ER_E7_SHIFT (7U)
  2119. #define CSL_EVETPCC_ER_E7_RESETVAL (0x00000000U)
  2120. #define CSL_EVETPCC_ER_E7_MAX (0x00000001U)
  2121. #define CSL_EVETPCC_ER_E17_MASK (0x00020000U)
  2122. #define CSL_EVETPCC_ER_E17_SHIFT (17U)
  2123. #define CSL_EVETPCC_ER_E17_RESETVAL (0x00000000U)
  2124. #define CSL_EVETPCC_ER_E17_MAX (0x00000001U)
  2125. #define CSL_EVETPCC_ER_E8_MASK (0x00000100U)
  2126. #define CSL_EVETPCC_ER_E8_SHIFT (8U)
  2127. #define CSL_EVETPCC_ER_E8_RESETVAL (0x00000000U)
  2128. #define CSL_EVETPCC_ER_E8_MAX (0x00000001U)
  2129. #define CSL_EVETPCC_ER_E16_MASK (0x00010000U)
  2130. #define CSL_EVETPCC_ER_E16_SHIFT (16U)
  2131. #define CSL_EVETPCC_ER_E16_RESETVAL (0x00000000U)
  2132. #define CSL_EVETPCC_ER_E16_MAX (0x00000001U)
  2133. #define CSL_EVETPCC_ER_E30_MASK (0x40000000U)
  2134. #define CSL_EVETPCC_ER_E30_SHIFT (30U)
  2135. #define CSL_EVETPCC_ER_E30_RESETVAL (0x00000000U)
  2136. #define CSL_EVETPCC_ER_E30_MAX (0x00000001U)
  2137. #define CSL_EVETPCC_ER_E24_MASK (0x01000000U)
  2138. #define CSL_EVETPCC_ER_E24_SHIFT (24U)
  2139. #define CSL_EVETPCC_ER_E24_RESETVAL (0x00000000U)
  2140. #define CSL_EVETPCC_ER_E24_MAX (0x00000001U)
  2141. #define CSL_EVETPCC_ER_E23_MASK (0x00800000U)
  2142. #define CSL_EVETPCC_ER_E23_SHIFT (23U)
  2143. #define CSL_EVETPCC_ER_E23_RESETVAL (0x00000000U)
  2144. #define CSL_EVETPCC_ER_E23_MAX (0x00000001U)
  2145. #define CSL_EVETPCC_ER_E0_MASK (0x00000001U)
  2146. #define CSL_EVETPCC_ER_E0_SHIFT (0U)
  2147. #define CSL_EVETPCC_ER_E0_RESETVAL (0x00000000U)
  2148. #define CSL_EVETPCC_ER_E0_MAX (0x00000001U)
  2149. #define CSL_EVETPCC_ER_E13_MASK (0x00002000U)
  2150. #define CSL_EVETPCC_ER_E13_SHIFT (13U)
  2151. #define CSL_EVETPCC_ER_E13_RESETVAL (0x00000000U)
  2152. #define CSL_EVETPCC_ER_E13_MAX (0x00000001U)
  2153. #define CSL_EVETPCC_ER_E11_MASK (0x00000800U)
  2154. #define CSL_EVETPCC_ER_E11_SHIFT (11U)
  2155. #define CSL_EVETPCC_ER_E11_RESETVAL (0x00000000U)
  2156. #define CSL_EVETPCC_ER_E11_MAX (0x00000001U)
  2157. #define CSL_EVETPCC_ER_E26_MASK (0x04000000U)
  2158. #define CSL_EVETPCC_ER_E26_SHIFT (26U)
  2159. #define CSL_EVETPCC_ER_E26_RESETVAL (0x00000000U)
  2160. #define CSL_EVETPCC_ER_E26_MAX (0x00000001U)
  2161. #define CSL_EVETPCC_ER_E1_MASK (0x00000002U)
  2162. #define CSL_EVETPCC_ER_E1_SHIFT (1U)
  2163. #define CSL_EVETPCC_ER_E1_RESETVAL (0x00000000U)
  2164. #define CSL_EVETPCC_ER_E1_MAX (0x00000001U)
  2165. #define CSL_EVETPCC_ER_E12_MASK (0x00001000U)
  2166. #define CSL_EVETPCC_ER_E12_SHIFT (12U)
  2167. #define CSL_EVETPCC_ER_E12_RESETVAL (0x00000000U)
  2168. #define CSL_EVETPCC_ER_E12_MAX (0x00000001U)
  2169. #define CSL_EVETPCC_ER_E25_MASK (0x02000000U)
  2170. #define CSL_EVETPCC_ER_E25_SHIFT (25U)
  2171. #define CSL_EVETPCC_ER_E25_RESETVAL (0x00000000U)
  2172. #define CSL_EVETPCC_ER_E25_MAX (0x00000001U)
  2173. #define CSL_EVETPCC_ER_E15_MASK (0x00008000U)
  2174. #define CSL_EVETPCC_ER_E15_SHIFT (15U)
  2175. #define CSL_EVETPCC_ER_E15_RESETVAL (0x00000000U)
  2176. #define CSL_EVETPCC_ER_E15_MAX (0x00000001U)
  2177. #define CSL_EVETPCC_ER_RESETVAL (0x00000000U)
  2178. /* ERH */
  2179. #define CSL_EVETPCC_ERH_E61_MASK (0x20000000U)
  2180. #define CSL_EVETPCC_ERH_E61_SHIFT (29U)
  2181. #define CSL_EVETPCC_ERH_E61_RESETVAL (0x00000000U)
  2182. #define CSL_EVETPCC_ERH_E61_MAX (0x00000001U)
  2183. #define CSL_EVETPCC_ERH_E54_MASK (0x00400000U)
  2184. #define CSL_EVETPCC_ERH_E54_SHIFT (22U)
  2185. #define CSL_EVETPCC_ERH_E54_RESETVAL (0x00000000U)
  2186. #define CSL_EVETPCC_ERH_E54_MAX (0x00000001U)
  2187. #define CSL_EVETPCC_ERH_E55_MASK (0x00800000U)
  2188. #define CSL_EVETPCC_ERH_E55_SHIFT (23U)
  2189. #define CSL_EVETPCC_ERH_E55_RESETVAL (0x00000000U)
  2190. #define CSL_EVETPCC_ERH_E55_MAX (0x00000001U)
  2191. #define CSL_EVETPCC_ERH_E59_MASK (0x08000000U)
  2192. #define CSL_EVETPCC_ERH_E59_SHIFT (27U)
  2193. #define CSL_EVETPCC_ERH_E59_RESETVAL (0x00000000U)
  2194. #define CSL_EVETPCC_ERH_E59_MAX (0x00000001U)
  2195. #define CSL_EVETPCC_ERH_E50_MASK (0x00040000U)
  2196. #define CSL_EVETPCC_ERH_E50_SHIFT (18U)
  2197. #define CSL_EVETPCC_ERH_E50_RESETVAL (0x00000000U)
  2198. #define CSL_EVETPCC_ERH_E50_MAX (0x00000001U)
  2199. #define CSL_EVETPCC_ERH_E52_MASK (0x00100000U)
  2200. #define CSL_EVETPCC_ERH_E52_SHIFT (20U)
  2201. #define CSL_EVETPCC_ERH_E52_RESETVAL (0x00000000U)
  2202. #define CSL_EVETPCC_ERH_E52_MAX (0x00000001U)
  2203. #define CSL_EVETPCC_ERH_E53_MASK (0x00200000U)
  2204. #define CSL_EVETPCC_ERH_E53_SHIFT (21U)
  2205. #define CSL_EVETPCC_ERH_E53_RESETVAL (0x00000000U)
  2206. #define CSL_EVETPCC_ERH_E53_MAX (0x00000001U)
  2207. #define CSL_EVETPCC_ERH_E51_MASK (0x00080000U)
  2208. #define CSL_EVETPCC_ERH_E51_SHIFT (19U)
  2209. #define CSL_EVETPCC_ERH_E51_RESETVAL (0x00000000U)
  2210. #define CSL_EVETPCC_ERH_E51_MAX (0x00000001U)
  2211. #define CSL_EVETPCC_ERH_E36_MASK (0x00000010U)
  2212. #define CSL_EVETPCC_ERH_E36_SHIFT (4U)
  2213. #define CSL_EVETPCC_ERH_E36_RESETVAL (0x00000000U)
  2214. #define CSL_EVETPCC_ERH_E36_MAX (0x00000001U)
  2215. #define CSL_EVETPCC_ERH_E40_MASK (0x00000100U)
  2216. #define CSL_EVETPCC_ERH_E40_SHIFT (8U)
  2217. #define CSL_EVETPCC_ERH_E40_RESETVAL (0x00000000U)
  2218. #define CSL_EVETPCC_ERH_E40_MAX (0x00000001U)
  2219. #define CSL_EVETPCC_ERH_E39_MASK (0x00000080U)
  2220. #define CSL_EVETPCC_ERH_E39_SHIFT (7U)
  2221. #define CSL_EVETPCC_ERH_E39_RESETVAL (0x00000000U)
  2222. #define CSL_EVETPCC_ERH_E39_MAX (0x00000001U)
  2223. #define CSL_EVETPCC_ERH_E38_MASK (0x00000040U)
  2224. #define CSL_EVETPCC_ERH_E38_SHIFT (6U)
  2225. #define CSL_EVETPCC_ERH_E38_RESETVAL (0x00000000U)
  2226. #define CSL_EVETPCC_ERH_E38_MAX (0x00000001U)
  2227. #define CSL_EVETPCC_ERH_E42_MASK (0x00000400U)
  2228. #define CSL_EVETPCC_ERH_E42_SHIFT (10U)
  2229. #define CSL_EVETPCC_ERH_E42_RESETVAL (0x00000000U)
  2230. #define CSL_EVETPCC_ERH_E42_MAX (0x00000001U)
  2231. #define CSL_EVETPCC_ERH_E49_MASK (0x00020000U)
  2232. #define CSL_EVETPCC_ERH_E49_SHIFT (17U)
  2233. #define CSL_EVETPCC_ERH_E49_RESETVAL (0x00000000U)
  2234. #define CSL_EVETPCC_ERH_E49_MAX (0x00000001U)
  2235. #define CSL_EVETPCC_ERH_E41_MASK (0x00000200U)
  2236. #define CSL_EVETPCC_ERH_E41_SHIFT (9U)
  2237. #define CSL_EVETPCC_ERH_E41_RESETVAL (0x00000000U)
  2238. #define CSL_EVETPCC_ERH_E41_MAX (0x00000001U)
  2239. #define CSL_EVETPCC_ERH_E32_MASK (0x00000001U)
  2240. #define CSL_EVETPCC_ERH_E32_SHIFT (0U)
  2241. #define CSL_EVETPCC_ERH_E32_RESETVAL (0x00000000U)
  2242. #define CSL_EVETPCC_ERH_E32_MAX (0x00000001U)
  2243. #define CSL_EVETPCC_ERH_E35_MASK (0x00000008U)
  2244. #define CSL_EVETPCC_ERH_E35_SHIFT (3U)
  2245. #define CSL_EVETPCC_ERH_E35_RESETVAL (0x00000000U)
  2246. #define CSL_EVETPCC_ERH_E35_MAX (0x00000001U)
  2247. #define CSL_EVETPCC_ERH_E43_MASK (0x00000800U)
  2248. #define CSL_EVETPCC_ERH_E43_SHIFT (11U)
  2249. #define CSL_EVETPCC_ERH_E43_RESETVAL (0x00000000U)
  2250. #define CSL_EVETPCC_ERH_E43_MAX (0x00000001U)
  2251. #define CSL_EVETPCC_ERH_E34_MASK (0x00000004U)
  2252. #define CSL_EVETPCC_ERH_E34_SHIFT (2U)
  2253. #define CSL_EVETPCC_ERH_E34_RESETVAL (0x00000000U)
  2254. #define CSL_EVETPCC_ERH_E34_MAX (0x00000001U)
  2255. #define CSL_EVETPCC_ERH_E44_MASK (0x00001000U)
  2256. #define CSL_EVETPCC_ERH_E44_SHIFT (12U)
  2257. #define CSL_EVETPCC_ERH_E44_RESETVAL (0x00000000U)
  2258. #define CSL_EVETPCC_ERH_E44_MAX (0x00000001U)
  2259. #define CSL_EVETPCC_ERH_E37_MASK (0x00000020U)
  2260. #define CSL_EVETPCC_ERH_E37_SHIFT (5U)
  2261. #define CSL_EVETPCC_ERH_E37_RESETVAL (0x00000000U)
  2262. #define CSL_EVETPCC_ERH_E37_MAX (0x00000001U)
  2263. #define CSL_EVETPCC_ERH_E45_MASK (0x00002000U)
  2264. #define CSL_EVETPCC_ERH_E45_SHIFT (13U)
  2265. #define CSL_EVETPCC_ERH_E45_RESETVAL (0x00000000U)
  2266. #define CSL_EVETPCC_ERH_E45_MAX (0x00000001U)
  2267. #define CSL_EVETPCC_ERH_E58_MASK (0x04000000U)
  2268. #define CSL_EVETPCC_ERH_E58_SHIFT (26U)
  2269. #define CSL_EVETPCC_ERH_E58_RESETVAL (0x00000000U)
  2270. #define CSL_EVETPCC_ERH_E58_MAX (0x00000001U)
  2271. #define CSL_EVETPCC_ERH_E62_MASK (0x40000000U)
  2272. #define CSL_EVETPCC_ERH_E62_SHIFT (30U)
  2273. #define CSL_EVETPCC_ERH_E62_RESETVAL (0x00000000U)
  2274. #define CSL_EVETPCC_ERH_E62_MAX (0x00000001U)
  2275. #define CSL_EVETPCC_ERH_E46_MASK (0x00004000U)
  2276. #define CSL_EVETPCC_ERH_E46_SHIFT (14U)
  2277. #define CSL_EVETPCC_ERH_E46_RESETVAL (0x00000000U)
  2278. #define CSL_EVETPCC_ERH_E46_MAX (0x00000001U)
  2279. #define CSL_EVETPCC_ERH_E57_MASK (0x02000000U)
  2280. #define CSL_EVETPCC_ERH_E57_SHIFT (25U)
  2281. #define CSL_EVETPCC_ERH_E57_RESETVAL (0x00000000U)
  2282. #define CSL_EVETPCC_ERH_E57_MAX (0x00000001U)
  2283. #define CSL_EVETPCC_ERH_E63_MASK (0x80000000U)
  2284. #define CSL_EVETPCC_ERH_E63_SHIFT (31U)
  2285. #define CSL_EVETPCC_ERH_E63_RESETVAL (0x00000000U)
  2286. #define CSL_EVETPCC_ERH_E63_MAX (0x00000001U)
  2287. #define CSL_EVETPCC_ERH_E47_MASK (0x00008000U)
  2288. #define CSL_EVETPCC_ERH_E47_SHIFT (15U)
  2289. #define CSL_EVETPCC_ERH_E47_RESETVAL (0x00000000U)
  2290. #define CSL_EVETPCC_ERH_E47_MAX (0x00000001U)
  2291. #define CSL_EVETPCC_ERH_E56_MASK (0x01000000U)
  2292. #define CSL_EVETPCC_ERH_E56_SHIFT (24U)
  2293. #define CSL_EVETPCC_ERH_E56_RESETVAL (0x00000000U)
  2294. #define CSL_EVETPCC_ERH_E56_MAX (0x00000001U)
  2295. #define CSL_EVETPCC_ERH_E48_MASK (0x00010000U)
  2296. #define CSL_EVETPCC_ERH_E48_SHIFT (16U)
  2297. #define CSL_EVETPCC_ERH_E48_RESETVAL (0x00000000U)
  2298. #define CSL_EVETPCC_ERH_E48_MAX (0x00000001U)
  2299. #define CSL_EVETPCC_ERH_E33_MASK (0x00000002U)
  2300. #define CSL_EVETPCC_ERH_E33_SHIFT (1U)
  2301. #define CSL_EVETPCC_ERH_E33_RESETVAL (0x00000000U)
  2302. #define CSL_EVETPCC_ERH_E33_MAX (0x00000001U)
  2303. #define CSL_EVETPCC_ERH_E60_MASK (0x10000000U)
  2304. #define CSL_EVETPCC_ERH_E60_SHIFT (28U)
  2305. #define CSL_EVETPCC_ERH_E60_RESETVAL (0x00000000U)
  2306. #define CSL_EVETPCC_ERH_E60_MAX (0x00000001U)
  2307. #define CSL_EVETPCC_ERH_RESETVAL (0x00000000U)
  2308. /* ECR */
  2309. #define CSL_EVETPCC_ECR_E16_MASK (0x00010000U)
  2310. #define CSL_EVETPCC_ECR_E16_SHIFT (16U)
  2311. #define CSL_EVETPCC_ECR_E16_RESETVAL (0x00000000U)
  2312. #define CSL_EVETPCC_ECR_E16_MAX (0x00000001U)
  2313. #define CSL_EVETPCC_ECR_E10_MASK (0x00000400U)
  2314. #define CSL_EVETPCC_ECR_E10_SHIFT (10U)
  2315. #define CSL_EVETPCC_ECR_E10_RESETVAL (0x00000000U)
  2316. #define CSL_EVETPCC_ECR_E10_MAX (0x00000001U)
  2317. #define CSL_EVETPCC_ECR_E30_MASK (0x40000000U)
  2318. #define CSL_EVETPCC_ECR_E30_SHIFT (30U)
  2319. #define CSL_EVETPCC_ECR_E30_RESETVAL (0x00000000U)
  2320. #define CSL_EVETPCC_ECR_E30_MAX (0x00000001U)
  2321. #define CSL_EVETPCC_ECR_E19_MASK (0x00080000U)
  2322. #define CSL_EVETPCC_ECR_E19_SHIFT (19U)
  2323. #define CSL_EVETPCC_ECR_E19_RESETVAL (0x00000000U)
  2324. #define CSL_EVETPCC_ECR_E19_MAX (0x00000001U)
  2325. #define CSL_EVETPCC_ECR_E29_MASK (0x20000000U)
  2326. #define CSL_EVETPCC_ECR_E29_SHIFT (29U)
  2327. #define CSL_EVETPCC_ECR_E29_RESETVAL (0x00000000U)
  2328. #define CSL_EVETPCC_ECR_E29_MAX (0x00000001U)
  2329. #define CSL_EVETPCC_ECR_E12_MASK (0x00001000U)
  2330. #define CSL_EVETPCC_ECR_E12_SHIFT (12U)
  2331. #define CSL_EVETPCC_ECR_E12_RESETVAL (0x00000000U)
  2332. #define CSL_EVETPCC_ECR_E12_MAX (0x00000001U)
  2333. #define CSL_EVETPCC_ECR_E18_MASK (0x00040000U)
  2334. #define CSL_EVETPCC_ECR_E18_SHIFT (18U)
  2335. #define CSL_EVETPCC_ECR_E18_RESETVAL (0x00000000U)
  2336. #define CSL_EVETPCC_ECR_E18_MAX (0x00000001U)
  2337. #define CSL_EVETPCC_ECR_E11_MASK (0x00000800U)
  2338. #define CSL_EVETPCC_ECR_E11_SHIFT (11U)
  2339. #define CSL_EVETPCC_ECR_E11_RESETVAL (0x00000000U)
  2340. #define CSL_EVETPCC_ECR_E11_MAX (0x00000001U)
  2341. #define CSL_EVETPCC_ECR_E21_MASK (0x00200000U)
  2342. #define CSL_EVETPCC_ECR_E21_SHIFT (21U)
  2343. #define CSL_EVETPCC_ECR_E21_RESETVAL (0x00000000U)
  2344. #define CSL_EVETPCC_ECR_E21_MAX (0x00000001U)
  2345. #define CSL_EVETPCC_ECR_E31_MASK (0x80000000U)
  2346. #define CSL_EVETPCC_ECR_E31_SHIFT (31U)
  2347. #define CSL_EVETPCC_ECR_E31_RESETVAL (0x00000000U)
  2348. #define CSL_EVETPCC_ECR_E31_MAX (0x00000001U)
  2349. #define CSL_EVETPCC_ECR_E14_MASK (0x00004000U)
  2350. #define CSL_EVETPCC_ECR_E14_SHIFT (14U)
  2351. #define CSL_EVETPCC_ECR_E14_RESETVAL (0x00000000U)
  2352. #define CSL_EVETPCC_ECR_E14_MAX (0x00000001U)
  2353. #define CSL_EVETPCC_ECR_E26_MASK (0x04000000U)
  2354. #define CSL_EVETPCC_ECR_E26_SHIFT (26U)
  2355. #define CSL_EVETPCC_ECR_E26_RESETVAL (0x00000000U)
  2356. #define CSL_EVETPCC_ECR_E26_MAX (0x00000001U)
  2357. #define CSL_EVETPCC_ECR_E13_MASK (0x00002000U)
  2358. #define CSL_EVETPCC_ECR_E13_SHIFT (13U)
  2359. #define CSL_EVETPCC_ECR_E13_RESETVAL (0x00000000U)
  2360. #define CSL_EVETPCC_ECR_E13_MAX (0x00000001U)
  2361. #define CSL_EVETPCC_ECR_E25_MASK (0x02000000U)
  2362. #define CSL_EVETPCC_ECR_E25_SHIFT (25U)
  2363. #define CSL_EVETPCC_ECR_E25_RESETVAL (0x00000000U)
  2364. #define CSL_EVETPCC_ECR_E25_MAX (0x00000001U)
  2365. #define CSL_EVETPCC_ECR_E15_MASK (0x00008000U)
  2366. #define CSL_EVETPCC_ECR_E15_SHIFT (15U)
  2367. #define CSL_EVETPCC_ECR_E15_RESETVAL (0x00000000U)
  2368. #define CSL_EVETPCC_ECR_E15_MAX (0x00000001U)
  2369. #define CSL_EVETPCC_ECR_E28_MASK (0x10000000U)
  2370. #define CSL_EVETPCC_ECR_E28_SHIFT (28U)
  2371. #define CSL_EVETPCC_ECR_E28_RESETVAL (0x00000000U)
  2372. #define CSL_EVETPCC_ECR_E28_MAX (0x00000001U)
  2373. #define CSL_EVETPCC_ECR_E17_MASK (0x00020000U)
  2374. #define CSL_EVETPCC_ECR_E17_SHIFT (17U)
  2375. #define CSL_EVETPCC_ECR_E17_RESETVAL (0x00000000U)
  2376. #define CSL_EVETPCC_ECR_E17_MAX (0x00000001U)
  2377. #define CSL_EVETPCC_ECR_E27_MASK (0x08000000U)
  2378. #define CSL_EVETPCC_ECR_E27_SHIFT (27U)
  2379. #define CSL_EVETPCC_ECR_E27_RESETVAL (0x00000000U)
  2380. #define CSL_EVETPCC_ECR_E27_MAX (0x00000001U)
  2381. #define CSL_EVETPCC_ECR_E4_MASK (0x00000010U)
  2382. #define CSL_EVETPCC_ECR_E4_SHIFT (4U)
  2383. #define CSL_EVETPCC_ECR_E4_RESETVAL (0x00000000U)
  2384. #define CSL_EVETPCC_ECR_E4_MAX (0x00000001U)
  2385. #define CSL_EVETPCC_ECR_E24_MASK (0x01000000U)
  2386. #define CSL_EVETPCC_ECR_E24_SHIFT (24U)
  2387. #define CSL_EVETPCC_ECR_E24_RESETVAL (0x00000000U)
  2388. #define CSL_EVETPCC_ECR_E24_MAX (0x00000001U)
  2389. #define CSL_EVETPCC_ECR_E2_MASK (0x00000004U)
  2390. #define CSL_EVETPCC_ECR_E2_SHIFT (2U)
  2391. #define CSL_EVETPCC_ECR_E2_RESETVAL (0x00000000U)
  2392. #define CSL_EVETPCC_ECR_E2_MAX (0x00000001U)
  2393. #define CSL_EVETPCC_ECR_E3_MASK (0x00000008U)
  2394. #define CSL_EVETPCC_ECR_E3_SHIFT (3U)
  2395. #define CSL_EVETPCC_ECR_E3_RESETVAL (0x00000000U)
  2396. #define CSL_EVETPCC_ECR_E3_MAX (0x00000001U)
  2397. #define CSL_EVETPCC_ECR_E0_MASK (0x00000001U)
  2398. #define CSL_EVETPCC_ECR_E0_SHIFT (0U)
  2399. #define CSL_EVETPCC_ECR_E0_RESETVAL (0x00000000U)
  2400. #define CSL_EVETPCC_ECR_E0_MAX (0x00000001U)
  2401. #define CSL_EVETPCC_ECR_E20_MASK (0x00100000U)
  2402. #define CSL_EVETPCC_ECR_E20_SHIFT (20U)
  2403. #define CSL_EVETPCC_ECR_E20_RESETVAL (0x00000000U)
  2404. #define CSL_EVETPCC_ECR_E20_MAX (0x00000001U)
  2405. #define CSL_EVETPCC_ECR_E6_MASK (0x00000040U)
  2406. #define CSL_EVETPCC_ECR_E6_SHIFT (6U)
  2407. #define CSL_EVETPCC_ECR_E6_RESETVAL (0x00000000U)
  2408. #define CSL_EVETPCC_ECR_E6_MAX (0x00000001U)
  2409. #define CSL_EVETPCC_ECR_E1_MASK (0x00000002U)
  2410. #define CSL_EVETPCC_ECR_E1_SHIFT (1U)
  2411. #define CSL_EVETPCC_ECR_E1_RESETVAL (0x00000000U)
  2412. #define CSL_EVETPCC_ECR_E1_MAX (0x00000001U)
  2413. #define CSL_EVETPCC_ECR_E5_MASK (0x00000020U)
  2414. #define CSL_EVETPCC_ECR_E5_SHIFT (5U)
  2415. #define CSL_EVETPCC_ECR_E5_RESETVAL (0x00000000U)
  2416. #define CSL_EVETPCC_ECR_E5_MAX (0x00000001U)
  2417. #define CSL_EVETPCC_ECR_E23_MASK (0x00800000U)
  2418. #define CSL_EVETPCC_ECR_E23_SHIFT (23U)
  2419. #define CSL_EVETPCC_ECR_E23_RESETVAL (0x00000000U)
  2420. #define CSL_EVETPCC_ECR_E23_MAX (0x00000001U)
  2421. #define CSL_EVETPCC_ECR_E8_MASK (0x00000100U)
  2422. #define CSL_EVETPCC_ECR_E8_SHIFT (8U)
  2423. #define CSL_EVETPCC_ECR_E8_RESETVAL (0x00000000U)
  2424. #define CSL_EVETPCC_ECR_E8_MAX (0x00000001U)
  2425. #define CSL_EVETPCC_ECR_E9_MASK (0x00000200U)
  2426. #define CSL_EVETPCC_ECR_E9_SHIFT (9U)
  2427. #define CSL_EVETPCC_ECR_E9_RESETVAL (0x00000000U)
  2428. #define CSL_EVETPCC_ECR_E9_MAX (0x00000001U)
  2429. #define CSL_EVETPCC_ECR_E22_MASK (0x00400000U)
  2430. #define CSL_EVETPCC_ECR_E22_SHIFT (22U)
  2431. #define CSL_EVETPCC_ECR_E22_RESETVAL (0x00000000U)
  2432. #define CSL_EVETPCC_ECR_E22_MAX (0x00000001U)
  2433. #define CSL_EVETPCC_ECR_E7_MASK (0x00000080U)
  2434. #define CSL_EVETPCC_ECR_E7_SHIFT (7U)
  2435. #define CSL_EVETPCC_ECR_E7_RESETVAL (0x00000000U)
  2436. #define CSL_EVETPCC_ECR_E7_MAX (0x00000001U)
  2437. #define CSL_EVETPCC_ECR_RESETVAL (0x00000000U)
  2438. /* ECRH */
  2439. #define CSL_EVETPCC_ECRH_E50_MASK (0x00040000U)
  2440. #define CSL_EVETPCC_ECRH_E50_SHIFT (18U)
  2441. #define CSL_EVETPCC_ECRH_E50_RESETVAL (0x00000000U)
  2442. #define CSL_EVETPCC_ECRH_E50_MAX (0x00000001U)
  2443. #define CSL_EVETPCC_ECRH_E36_MASK (0x00000010U)
  2444. #define CSL_EVETPCC_ECRH_E36_SHIFT (4U)
  2445. #define CSL_EVETPCC_ECRH_E36_RESETVAL (0x00000000U)
  2446. #define CSL_EVETPCC_ECRH_E36_MAX (0x00000001U)
  2447. #define CSL_EVETPCC_ECRH_E60_MASK (0x10000000U)
  2448. #define CSL_EVETPCC_ECRH_E60_SHIFT (28U)
  2449. #define CSL_EVETPCC_ECRH_E60_RESETVAL (0x00000000U)
  2450. #define CSL_EVETPCC_ECRH_E60_MAX (0x00000001U)
  2451. #define CSL_EVETPCC_ECRH_E49_MASK (0x00020000U)
  2452. #define CSL_EVETPCC_ECRH_E49_SHIFT (17U)
  2453. #define CSL_EVETPCC_ECRH_E49_RESETVAL (0x00000000U)
  2454. #define CSL_EVETPCC_ECRH_E49_MAX (0x00000001U)
  2455. #define CSL_EVETPCC_ECRH_E37_MASK (0x00000020U)
  2456. #define CSL_EVETPCC_ECRH_E37_SHIFT (5U)
  2457. #define CSL_EVETPCC_ECRH_E37_RESETVAL (0x00000000U)
  2458. #define CSL_EVETPCC_ECRH_E37_MAX (0x00000001U)
  2459. #define CSL_EVETPCC_ECRH_E48_MASK (0x00010000U)
  2460. #define CSL_EVETPCC_ECRH_E48_SHIFT (16U)
  2461. #define CSL_EVETPCC_ECRH_E48_RESETVAL (0x00000000U)
  2462. #define CSL_EVETPCC_ECRH_E48_MAX (0x00000001U)
  2463. #define CSL_EVETPCC_ECRH_E58_MASK (0x04000000U)
  2464. #define CSL_EVETPCC_ECRH_E58_SHIFT (26U)
  2465. #define CSL_EVETPCC_ECRH_E58_RESETVAL (0x00000000U)
  2466. #define CSL_EVETPCC_ECRH_E58_MAX (0x00000001U)
  2467. #define CSL_EVETPCC_ECRH_E38_MASK (0x00000040U)
  2468. #define CSL_EVETPCC_ECRH_E38_SHIFT (6U)
  2469. #define CSL_EVETPCC_ECRH_E38_RESETVAL (0x00000000U)
  2470. #define CSL_EVETPCC_ECRH_E38_MAX (0x00000001U)
  2471. #define CSL_EVETPCC_ECRH_E63_MASK (0x80000000U)
  2472. #define CSL_EVETPCC_ECRH_E63_SHIFT (31U)
  2473. #define CSL_EVETPCC_ECRH_E63_RESETVAL (0x00000000U)
  2474. #define CSL_EVETPCC_ECRH_E63_MAX (0x00000001U)
  2475. #define CSL_EVETPCC_ECRH_E47_MASK (0x00008000U)
  2476. #define CSL_EVETPCC_ECRH_E47_SHIFT (15U)
  2477. #define CSL_EVETPCC_ECRH_E47_RESETVAL (0x00000000U)
  2478. #define CSL_EVETPCC_ECRH_E47_MAX (0x00000001U)
  2479. #define CSL_EVETPCC_ECRH_E39_MASK (0x00000080U)
  2480. #define CSL_EVETPCC_ECRH_E39_SHIFT (7U)
  2481. #define CSL_EVETPCC_ECRH_E39_RESETVAL (0x00000000U)
  2482. #define CSL_EVETPCC_ECRH_E39_MAX (0x00000001U)
  2483. #define CSL_EVETPCC_ECRH_E32_MASK (0x00000001U)
  2484. #define CSL_EVETPCC_ECRH_E32_SHIFT (0U)
  2485. #define CSL_EVETPCC_ECRH_E32_RESETVAL (0x00000000U)
  2486. #define CSL_EVETPCC_ECRH_E32_MAX (0x00000001U)
  2487. #define CSL_EVETPCC_ECRH_E51_MASK (0x00080000U)
  2488. #define CSL_EVETPCC_ECRH_E51_SHIFT (19U)
  2489. #define CSL_EVETPCC_ECRH_E51_RESETVAL (0x00000000U)
  2490. #define CSL_EVETPCC_ECRH_E51_MAX (0x00000001U)
  2491. #define CSL_EVETPCC_ECRH_E33_MASK (0x00000002U)
  2492. #define CSL_EVETPCC_ECRH_E33_SHIFT (1U)
  2493. #define CSL_EVETPCC_ECRH_E33_RESETVAL (0x00000000U)
  2494. #define CSL_EVETPCC_ECRH_E33_MAX (0x00000001U)
  2495. #define CSL_EVETPCC_ECRH_E34_MASK (0x00000004U)
  2496. #define CSL_EVETPCC_ECRH_E34_SHIFT (2U)
  2497. #define CSL_EVETPCC_ECRH_E34_RESETVAL (0x00000000U)
  2498. #define CSL_EVETPCC_ECRH_E34_MAX (0x00000001U)
  2499. #define CSL_EVETPCC_ECRH_E35_MASK (0x00000008U)
  2500. #define CSL_EVETPCC_ECRH_E35_SHIFT (3U)
  2501. #define CSL_EVETPCC_ECRH_E35_RESETVAL (0x00000000U)
  2502. #define CSL_EVETPCC_ECRH_E35_MAX (0x00000001U)
  2503. #define CSL_EVETPCC_ECRH_E42_MASK (0x00000400U)
  2504. #define CSL_EVETPCC_ECRH_E42_SHIFT (10U)
  2505. #define CSL_EVETPCC_ECRH_E42_RESETVAL (0x00000000U)
  2506. #define CSL_EVETPCC_ECRH_E42_MAX (0x00000001U)
  2507. #define CSL_EVETPCC_ECRH_E52_MASK (0x00100000U)
  2508. #define CSL_EVETPCC_ECRH_E52_SHIFT (20U)
  2509. #define CSL_EVETPCC_ECRH_E52_RESETVAL (0x00000000U)
  2510. #define CSL_EVETPCC_ECRH_E52_MAX (0x00000001U)
  2511. #define CSL_EVETPCC_ECRH_E41_MASK (0x00000200U)
  2512. #define CSL_EVETPCC_ECRH_E41_SHIFT (9U)
  2513. #define CSL_EVETPCC_ECRH_E41_RESETVAL (0x00000000U)
  2514. #define CSL_EVETPCC_ECRH_E41_MAX (0x00000001U)
  2515. #define CSL_EVETPCC_ECRH_E55_MASK (0x00800000U)
  2516. #define CSL_EVETPCC_ECRH_E55_SHIFT (23U)
  2517. #define CSL_EVETPCC_ECRH_E55_RESETVAL (0x00000000U)
  2518. #define CSL_EVETPCC_ECRH_E55_MAX (0x00000001U)
  2519. #define CSL_EVETPCC_ECRH_E53_MASK (0x00200000U)
  2520. #define CSL_EVETPCC_ECRH_E53_SHIFT (21U)
  2521. #define CSL_EVETPCC_ECRH_E53_RESETVAL (0x00000000U)
  2522. #define CSL_EVETPCC_ECRH_E53_MAX (0x00000001U)
  2523. #define CSL_EVETPCC_ECRH_E46_MASK (0x00004000U)
  2524. #define CSL_EVETPCC_ECRH_E46_SHIFT (14U)
  2525. #define CSL_EVETPCC_ECRH_E46_RESETVAL (0x00000000U)
  2526. #define CSL_EVETPCC_ECRH_E46_MAX (0x00000001U)
  2527. #define CSL_EVETPCC_ECRH_E62_MASK (0x40000000U)
  2528. #define CSL_EVETPCC_ECRH_E62_SHIFT (30U)
  2529. #define CSL_EVETPCC_ECRH_E62_RESETVAL (0x00000000U)
  2530. #define CSL_EVETPCC_ECRH_E62_MAX (0x00000001U)
  2531. #define CSL_EVETPCC_ECRH_E40_MASK (0x00000100U)
  2532. #define CSL_EVETPCC_ECRH_E40_SHIFT (8U)
  2533. #define CSL_EVETPCC_ECRH_E40_RESETVAL (0x00000000U)
  2534. #define CSL_EVETPCC_ECRH_E40_MAX (0x00000001U)
  2535. #define CSL_EVETPCC_ECRH_E56_MASK (0x01000000U)
  2536. #define CSL_EVETPCC_ECRH_E56_SHIFT (24U)
  2537. #define CSL_EVETPCC_ECRH_E56_RESETVAL (0x00000000U)
  2538. #define CSL_EVETPCC_ECRH_E56_MAX (0x00000001U)
  2539. #define CSL_EVETPCC_ECRH_E61_MASK (0x20000000U)
  2540. #define CSL_EVETPCC_ECRH_E61_SHIFT (29U)
  2541. #define CSL_EVETPCC_ECRH_E61_RESETVAL (0x00000000U)
  2542. #define CSL_EVETPCC_ECRH_E61_MAX (0x00000001U)
  2543. #define CSL_EVETPCC_ECRH_E45_MASK (0x00002000U)
  2544. #define CSL_EVETPCC_ECRH_E45_SHIFT (13U)
  2545. #define CSL_EVETPCC_ECRH_E45_RESETVAL (0x00000000U)
  2546. #define CSL_EVETPCC_ECRH_E45_MAX (0x00000001U)
  2547. #define CSL_EVETPCC_ECRH_E59_MASK (0x08000000U)
  2548. #define CSL_EVETPCC_ECRH_E59_SHIFT (27U)
  2549. #define CSL_EVETPCC_ECRH_E59_RESETVAL (0x00000000U)
  2550. #define CSL_EVETPCC_ECRH_E59_MAX (0x00000001U)
  2551. #define CSL_EVETPCC_ECRH_E44_MASK (0x00001000U)
  2552. #define CSL_EVETPCC_ECRH_E44_SHIFT (12U)
  2553. #define CSL_EVETPCC_ECRH_E44_RESETVAL (0x00000000U)
  2554. #define CSL_EVETPCC_ECRH_E44_MAX (0x00000001U)
  2555. #define CSL_EVETPCC_ECRH_E54_MASK (0x00400000U)
  2556. #define CSL_EVETPCC_ECRH_E54_SHIFT (22U)
  2557. #define CSL_EVETPCC_ECRH_E54_RESETVAL (0x00000000U)
  2558. #define CSL_EVETPCC_ECRH_E54_MAX (0x00000001U)
  2559. #define CSL_EVETPCC_ECRH_E43_MASK (0x00000800U)
  2560. #define CSL_EVETPCC_ECRH_E43_SHIFT (11U)
  2561. #define CSL_EVETPCC_ECRH_E43_RESETVAL (0x00000000U)
  2562. #define CSL_EVETPCC_ECRH_E43_MAX (0x00000001U)
  2563. #define CSL_EVETPCC_ECRH_E57_MASK (0x02000000U)
  2564. #define CSL_EVETPCC_ECRH_E57_SHIFT (25U)
  2565. #define CSL_EVETPCC_ECRH_E57_RESETVAL (0x00000000U)
  2566. #define CSL_EVETPCC_ECRH_E57_MAX (0x00000001U)
  2567. #define CSL_EVETPCC_ECRH_RESETVAL (0x00000000U)
  2568. /* ESR */
  2569. #define CSL_EVETPCC_ESR_E3_MASK (0x00000008U)
  2570. #define CSL_EVETPCC_ESR_E3_SHIFT (3U)
  2571. #define CSL_EVETPCC_ESR_E3_RESETVAL (0x00000000U)
  2572. #define CSL_EVETPCC_ESR_E3_MAX (0x00000001U)
  2573. #define CSL_EVETPCC_ESR_E6_MASK (0x00000040U)
  2574. #define CSL_EVETPCC_ESR_E6_SHIFT (6U)
  2575. #define CSL_EVETPCC_ESR_E6_RESETVAL (0x00000000U)
  2576. #define CSL_EVETPCC_ESR_E6_MAX (0x00000001U)
  2577. #define CSL_EVETPCC_ESR_E20_MASK (0x00100000U)
  2578. #define CSL_EVETPCC_ESR_E20_SHIFT (20U)
  2579. #define CSL_EVETPCC_ESR_E20_RESETVAL (0x00000000U)
  2580. #define CSL_EVETPCC_ESR_E20_MAX (0x00000001U)
  2581. #define CSL_EVETPCC_ESR_E1_MASK (0x00000002U)
  2582. #define CSL_EVETPCC_ESR_E1_SHIFT (1U)
  2583. #define CSL_EVETPCC_ESR_E1_RESETVAL (0x00000000U)
  2584. #define CSL_EVETPCC_ESR_E1_MAX (0x00000001U)
  2585. #define CSL_EVETPCC_ESR_E4_MASK (0x00000010U)
  2586. #define CSL_EVETPCC_ESR_E4_SHIFT (4U)
  2587. #define CSL_EVETPCC_ESR_E4_RESETVAL (0x00000000U)
  2588. #define CSL_EVETPCC_ESR_E4_MAX (0x00000001U)
  2589. #define CSL_EVETPCC_ESR_E18_MASK (0x00040000U)
  2590. #define CSL_EVETPCC_ESR_E18_SHIFT (18U)
  2591. #define CSL_EVETPCC_ESR_E18_RESETVAL (0x00000000U)
  2592. #define CSL_EVETPCC_ESR_E18_MAX (0x00000001U)
  2593. #define CSL_EVETPCC_ESR_E7_MASK (0x00000080U)
  2594. #define CSL_EVETPCC_ESR_E7_SHIFT (7U)
  2595. #define CSL_EVETPCC_ESR_E7_RESETVAL (0x00000000U)
  2596. #define CSL_EVETPCC_ESR_E7_MAX (0x00000001U)
  2597. #define CSL_EVETPCC_ESR_E11_MASK (0x00000800U)
  2598. #define CSL_EVETPCC_ESR_E11_SHIFT (11U)
  2599. #define CSL_EVETPCC_ESR_E11_RESETVAL (0x00000000U)
  2600. #define CSL_EVETPCC_ESR_E11_MAX (0x00000001U)
  2601. #define CSL_EVETPCC_ESR_E10_MASK (0x00000400U)
  2602. #define CSL_EVETPCC_ESR_E10_SHIFT (10U)
  2603. #define CSL_EVETPCC_ESR_E10_RESETVAL (0x00000000U)
  2604. #define CSL_EVETPCC_ESR_E10_MAX (0x00000001U)
  2605. #define CSL_EVETPCC_ESR_E5_MASK (0x00000020U)
  2606. #define CSL_EVETPCC_ESR_E5_SHIFT (5U)
  2607. #define CSL_EVETPCC_ESR_E5_RESETVAL (0x00000000U)
  2608. #define CSL_EVETPCC_ESR_E5_MAX (0x00000001U)
  2609. #define CSL_EVETPCC_ESR_E8_MASK (0x00000100U)
  2610. #define CSL_EVETPCC_ESR_E8_SHIFT (8U)
  2611. #define CSL_EVETPCC_ESR_E8_RESETVAL (0x00000000U)
  2612. #define CSL_EVETPCC_ESR_E8_MAX (0x00000001U)
  2613. #define CSL_EVETPCC_ESR_E22_MASK (0x00400000U)
  2614. #define CSL_EVETPCC_ESR_E22_SHIFT (22U)
  2615. #define CSL_EVETPCC_ESR_E22_RESETVAL (0x00000000U)
  2616. #define CSL_EVETPCC_ESR_E22_MAX (0x00000001U)
  2617. #define CSL_EVETPCC_ESR_E21_MASK (0x00200000U)
  2618. #define CSL_EVETPCC_ESR_E21_SHIFT (21U)
  2619. #define CSL_EVETPCC_ESR_E21_RESETVAL (0x00000000U)
  2620. #define CSL_EVETPCC_ESR_E21_MAX (0x00000001U)
  2621. #define CSL_EVETPCC_ESR_E23_MASK (0x00800000U)
  2622. #define CSL_EVETPCC_ESR_E23_SHIFT (23U)
  2623. #define CSL_EVETPCC_ESR_E23_RESETVAL (0x00000000U)
  2624. #define CSL_EVETPCC_ESR_E23_MAX (0x00000001U)
  2625. #define CSL_EVETPCC_ESR_E31_MASK (0x80000000U)
  2626. #define CSL_EVETPCC_ESR_E31_SHIFT (31U)
  2627. #define CSL_EVETPCC_ESR_E31_RESETVAL (0x00000000U)
  2628. #define CSL_EVETPCC_ESR_E31_MAX (0x00000001U)
  2629. #define CSL_EVETPCC_ESR_E15_MASK (0x00008000U)
  2630. #define CSL_EVETPCC_ESR_E15_SHIFT (15U)
  2631. #define CSL_EVETPCC_ESR_E15_RESETVAL (0x00000000U)
  2632. #define CSL_EVETPCC_ESR_E15_MAX (0x00000001U)
  2633. #define CSL_EVETPCC_ESR_E26_MASK (0x04000000U)
  2634. #define CSL_EVETPCC_ESR_E26_SHIFT (26U)
  2635. #define CSL_EVETPCC_ESR_E26_RESETVAL (0x00000000U)
  2636. #define CSL_EVETPCC_ESR_E26_MAX (0x00000001U)
  2637. #define CSL_EVETPCC_ESR_E24_MASK (0x01000000U)
  2638. #define CSL_EVETPCC_ESR_E24_SHIFT (24U)
  2639. #define CSL_EVETPCC_ESR_E24_RESETVAL (0x00000000U)
  2640. #define CSL_EVETPCC_ESR_E24_MAX (0x00000001U)
  2641. #define CSL_EVETPCC_ESR_E12_MASK (0x00001000U)
  2642. #define CSL_EVETPCC_ESR_E12_SHIFT (12U)
  2643. #define CSL_EVETPCC_ESR_E12_RESETVAL (0x00000000U)
  2644. #define CSL_EVETPCC_ESR_E12_MAX (0x00000001U)
  2645. #define CSL_EVETPCC_ESR_E13_MASK (0x00002000U)
  2646. #define CSL_EVETPCC_ESR_E13_SHIFT (13U)
  2647. #define CSL_EVETPCC_ESR_E13_RESETVAL (0x00000000U)
  2648. #define CSL_EVETPCC_ESR_E13_MAX (0x00000001U)
  2649. #define CSL_EVETPCC_ESR_E9_MASK (0x00000200U)
  2650. #define CSL_EVETPCC_ESR_E9_SHIFT (9U)
  2651. #define CSL_EVETPCC_ESR_E9_RESETVAL (0x00000000U)
  2652. #define CSL_EVETPCC_ESR_E9_MAX (0x00000001U)
  2653. #define CSL_EVETPCC_ESR_E28_MASK (0x10000000U)
  2654. #define CSL_EVETPCC_ESR_E28_SHIFT (28U)
  2655. #define CSL_EVETPCC_ESR_E28_RESETVAL (0x00000000U)
  2656. #define CSL_EVETPCC_ESR_E28_MAX (0x00000001U)
  2657. #define CSL_EVETPCC_ESR_E25_MASK (0x02000000U)
  2658. #define CSL_EVETPCC_ESR_E25_SHIFT (25U)
  2659. #define CSL_EVETPCC_ESR_E25_RESETVAL (0x00000000U)
  2660. #define CSL_EVETPCC_ESR_E25_MAX (0x00000001U)
  2661. #define CSL_EVETPCC_ESR_E0_MASK (0x00000001U)
  2662. #define CSL_EVETPCC_ESR_E0_SHIFT (0U)
  2663. #define CSL_EVETPCC_ESR_E0_RESETVAL (0x00000000U)
  2664. #define CSL_EVETPCC_ESR_E0_MAX (0x00000001U)
  2665. #define CSL_EVETPCC_ESR_E19_MASK (0x00080000U)
  2666. #define CSL_EVETPCC_ESR_E19_SHIFT (19U)
  2667. #define CSL_EVETPCC_ESR_E19_RESETVAL (0x00000000U)
  2668. #define CSL_EVETPCC_ESR_E19_MAX (0x00000001U)
  2669. #define CSL_EVETPCC_ESR_E16_MASK (0x00010000U)
  2670. #define CSL_EVETPCC_ESR_E16_SHIFT (16U)
  2671. #define CSL_EVETPCC_ESR_E16_RESETVAL (0x00000000U)
  2672. #define CSL_EVETPCC_ESR_E16_MAX (0x00000001U)
  2673. #define CSL_EVETPCC_ESR_E2_MASK (0x00000004U)
  2674. #define CSL_EVETPCC_ESR_E2_SHIFT (2U)
  2675. #define CSL_EVETPCC_ESR_E2_RESETVAL (0x00000000U)
  2676. #define CSL_EVETPCC_ESR_E2_MAX (0x00000001U)
  2677. #define CSL_EVETPCC_ESR_E27_MASK (0x08000000U)
  2678. #define CSL_EVETPCC_ESR_E27_SHIFT (27U)
  2679. #define CSL_EVETPCC_ESR_E27_RESETVAL (0x00000000U)
  2680. #define CSL_EVETPCC_ESR_E27_MAX (0x00000001U)
  2681. #define CSL_EVETPCC_ESR_E17_MASK (0x00020000U)
  2682. #define CSL_EVETPCC_ESR_E17_SHIFT (17U)
  2683. #define CSL_EVETPCC_ESR_E17_RESETVAL (0x00000000U)
  2684. #define CSL_EVETPCC_ESR_E17_MAX (0x00000001U)
  2685. #define CSL_EVETPCC_ESR_E30_MASK (0x40000000U)
  2686. #define CSL_EVETPCC_ESR_E30_SHIFT (30U)
  2687. #define CSL_EVETPCC_ESR_E30_RESETVAL (0x00000000U)
  2688. #define CSL_EVETPCC_ESR_E30_MAX (0x00000001U)
  2689. #define CSL_EVETPCC_ESR_E14_MASK (0x00004000U)
  2690. #define CSL_EVETPCC_ESR_E14_SHIFT (14U)
  2691. #define CSL_EVETPCC_ESR_E14_RESETVAL (0x00000000U)
  2692. #define CSL_EVETPCC_ESR_E14_MAX (0x00000001U)
  2693. #define CSL_EVETPCC_ESR_E29_MASK (0x20000000U)
  2694. #define CSL_EVETPCC_ESR_E29_SHIFT (29U)
  2695. #define CSL_EVETPCC_ESR_E29_RESETVAL (0x00000000U)
  2696. #define CSL_EVETPCC_ESR_E29_MAX (0x00000001U)
  2697. #define CSL_EVETPCC_ESR_RESETVAL (0x00000000U)
  2698. /* ESRH */
  2699. #define CSL_EVETPCC_ESRH_E41_MASK (0x00000200U)
  2700. #define CSL_EVETPCC_ESRH_E41_SHIFT (9U)
  2701. #define CSL_EVETPCC_ESRH_E41_RESETVAL (0x00000000U)
  2702. #define CSL_EVETPCC_ESRH_E41_MAX (0x00000001U)
  2703. #define CSL_EVETPCC_ESRH_E57_MASK (0x02000000U)
  2704. #define CSL_EVETPCC_ESRH_E57_SHIFT (25U)
  2705. #define CSL_EVETPCC_ESRH_E57_RESETVAL (0x00000000U)
  2706. #define CSL_EVETPCC_ESRH_E57_MAX (0x00000001U)
  2707. #define CSL_EVETPCC_ESRH_E46_MASK (0x00004000U)
  2708. #define CSL_EVETPCC_ESRH_E46_SHIFT (14U)
  2709. #define CSL_EVETPCC_ESRH_E46_RESETVAL (0x00000000U)
  2710. #define CSL_EVETPCC_ESRH_E46_MAX (0x00000001U)
  2711. #define CSL_EVETPCC_ESRH_E42_MASK (0x00000400U)
  2712. #define CSL_EVETPCC_ESRH_E42_SHIFT (10U)
  2713. #define CSL_EVETPCC_ESRH_E42_RESETVAL (0x00000000U)
  2714. #define CSL_EVETPCC_ESRH_E42_MAX (0x00000001U)
  2715. #define CSL_EVETPCC_ESRH_E56_MASK (0x01000000U)
  2716. #define CSL_EVETPCC_ESRH_E56_SHIFT (24U)
  2717. #define CSL_EVETPCC_ESRH_E56_RESETVAL (0x00000000U)
  2718. #define CSL_EVETPCC_ESRH_E56_MAX (0x00000001U)
  2719. #define CSL_EVETPCC_ESRH_E33_MASK (0x00000002U)
  2720. #define CSL_EVETPCC_ESRH_E33_SHIFT (1U)
  2721. #define CSL_EVETPCC_ESRH_E33_RESETVAL (0x00000000U)
  2722. #define CSL_EVETPCC_ESRH_E33_MAX (0x00000001U)
  2723. #define CSL_EVETPCC_ESRH_E43_MASK (0x00000800U)
  2724. #define CSL_EVETPCC_ESRH_E43_SHIFT (11U)
  2725. #define CSL_EVETPCC_ESRH_E43_RESETVAL (0x00000000U)
  2726. #define CSL_EVETPCC_ESRH_E43_MAX (0x00000001U)
  2727. #define CSL_EVETPCC_ESRH_E55_MASK (0x00800000U)
  2728. #define CSL_EVETPCC_ESRH_E55_SHIFT (23U)
  2729. #define CSL_EVETPCC_ESRH_E55_RESETVAL (0x00000000U)
  2730. #define CSL_EVETPCC_ESRH_E55_MAX (0x00000001U)
  2731. #define CSL_EVETPCC_ESRH_E32_MASK (0x00000001U)
  2732. #define CSL_EVETPCC_ESRH_E32_SHIFT (0U)
  2733. #define CSL_EVETPCC_ESRH_E32_RESETVAL (0x00000000U)
  2734. #define CSL_EVETPCC_ESRH_E32_MAX (0x00000001U)
  2735. #define CSL_EVETPCC_ESRH_E48_MASK (0x00010000U)
  2736. #define CSL_EVETPCC_ESRH_E48_SHIFT (16U)
  2737. #define CSL_EVETPCC_ESRH_E48_RESETVAL (0x00000000U)
  2738. #define CSL_EVETPCC_ESRH_E48_MAX (0x00000001U)
  2739. #define CSL_EVETPCC_ESRH_E44_MASK (0x00001000U)
  2740. #define CSL_EVETPCC_ESRH_E44_SHIFT (12U)
  2741. #define CSL_EVETPCC_ESRH_E44_RESETVAL (0x00000000U)
  2742. #define CSL_EVETPCC_ESRH_E44_MAX (0x00000001U)
  2743. #define CSL_EVETPCC_ESRH_E45_MASK (0x00002000U)
  2744. #define CSL_EVETPCC_ESRH_E45_SHIFT (13U)
  2745. #define CSL_EVETPCC_ESRH_E45_RESETVAL (0x00000000U)
  2746. #define CSL_EVETPCC_ESRH_E45_MAX (0x00000001U)
  2747. #define CSL_EVETPCC_ESRH_E49_MASK (0x00020000U)
  2748. #define CSL_EVETPCC_ESRH_E49_SHIFT (17U)
  2749. #define CSL_EVETPCC_ESRH_E49_RESETVAL (0x00000000U)
  2750. #define CSL_EVETPCC_ESRH_E49_MAX (0x00000001U)
  2751. #define CSL_EVETPCC_ESRH_E61_MASK (0x20000000U)
  2752. #define CSL_EVETPCC_ESRH_E61_SHIFT (29U)
  2753. #define CSL_EVETPCC_ESRH_E61_RESETVAL (0x00000000U)
  2754. #define CSL_EVETPCC_ESRH_E61_MAX (0x00000001U)
  2755. #define CSL_EVETPCC_ESRH_E52_MASK (0x00100000U)
  2756. #define CSL_EVETPCC_ESRH_E52_SHIFT (20U)
  2757. #define CSL_EVETPCC_ESRH_E52_RESETVAL (0x00000000U)
  2758. #define CSL_EVETPCC_ESRH_E52_MAX (0x00000001U)
  2759. #define CSL_EVETPCC_ESRH_E63_MASK (0x80000000U)
  2760. #define CSL_EVETPCC_ESRH_E63_SHIFT (31U)
  2761. #define CSL_EVETPCC_ESRH_E63_RESETVAL (0x00000000U)
  2762. #define CSL_EVETPCC_ESRH_E63_MAX (0x00000001U)
  2763. #define CSL_EVETPCC_ESRH_E34_MASK (0x00000004U)
  2764. #define CSL_EVETPCC_ESRH_E34_SHIFT (2U)
  2765. #define CSL_EVETPCC_ESRH_E34_RESETVAL (0x00000000U)
  2766. #define CSL_EVETPCC_ESRH_E34_MAX (0x00000001U)
  2767. #define CSL_EVETPCC_ESRH_E47_MASK (0x00008000U)
  2768. #define CSL_EVETPCC_ESRH_E47_SHIFT (15U)
  2769. #define CSL_EVETPCC_ESRH_E47_RESETVAL (0x00000000U)
  2770. #define CSL_EVETPCC_ESRH_E47_MAX (0x00000001U)
  2771. #define CSL_EVETPCC_ESRH_E60_MASK (0x10000000U)
  2772. #define CSL_EVETPCC_ESRH_E60_SHIFT (28U)
  2773. #define CSL_EVETPCC_ESRH_E60_RESETVAL (0x00000000U)
  2774. #define CSL_EVETPCC_ESRH_E60_MAX (0x00000001U)
  2775. #define CSL_EVETPCC_ESRH_E59_MASK (0x08000000U)
  2776. #define CSL_EVETPCC_ESRH_E59_SHIFT (27U)
  2777. #define CSL_EVETPCC_ESRH_E59_RESETVAL (0x00000000U)
  2778. #define CSL_EVETPCC_ESRH_E59_MAX (0x00000001U)
  2779. #define CSL_EVETPCC_ESRH_E50_MASK (0x00040000U)
  2780. #define CSL_EVETPCC_ESRH_E50_SHIFT (18U)
  2781. #define CSL_EVETPCC_ESRH_E50_RESETVAL (0x00000000U)
  2782. #define CSL_EVETPCC_ESRH_E50_MAX (0x00000001U)
  2783. #define CSL_EVETPCC_ESRH_E58_MASK (0x04000000U)
  2784. #define CSL_EVETPCC_ESRH_E58_SHIFT (26U)
  2785. #define CSL_EVETPCC_ESRH_E58_RESETVAL (0x00000000U)
  2786. #define CSL_EVETPCC_ESRH_E58_MAX (0x00000001U)
  2787. #define CSL_EVETPCC_ESRH_E53_MASK (0x00200000U)
  2788. #define CSL_EVETPCC_ESRH_E53_SHIFT (21U)
  2789. #define CSL_EVETPCC_ESRH_E53_RESETVAL (0x00000000U)
  2790. #define CSL_EVETPCC_ESRH_E53_MAX (0x00000001U)
  2791. #define CSL_EVETPCC_ESRH_E35_MASK (0x00000008U)
  2792. #define CSL_EVETPCC_ESRH_E35_SHIFT (3U)
  2793. #define CSL_EVETPCC_ESRH_E35_RESETVAL (0x00000000U)
  2794. #define CSL_EVETPCC_ESRH_E35_MAX (0x00000001U)
  2795. #define CSL_EVETPCC_ESRH_E51_MASK (0x00080000U)
  2796. #define CSL_EVETPCC_ESRH_E51_SHIFT (19U)
  2797. #define CSL_EVETPCC_ESRH_E51_RESETVAL (0x00000000U)
  2798. #define CSL_EVETPCC_ESRH_E51_MAX (0x00000001U)
  2799. #define CSL_EVETPCC_ESRH_E54_MASK (0x00400000U)
  2800. #define CSL_EVETPCC_ESRH_E54_SHIFT (22U)
  2801. #define CSL_EVETPCC_ESRH_E54_RESETVAL (0x00000000U)
  2802. #define CSL_EVETPCC_ESRH_E54_MAX (0x00000001U)
  2803. #define CSL_EVETPCC_ESRH_E36_MASK (0x00000010U)
  2804. #define CSL_EVETPCC_ESRH_E36_SHIFT (4U)
  2805. #define CSL_EVETPCC_ESRH_E36_RESETVAL (0x00000000U)
  2806. #define CSL_EVETPCC_ESRH_E36_MAX (0x00000001U)
  2807. #define CSL_EVETPCC_ESRH_E62_MASK (0x40000000U)
  2808. #define CSL_EVETPCC_ESRH_E62_SHIFT (30U)
  2809. #define CSL_EVETPCC_ESRH_E62_RESETVAL (0x00000000U)
  2810. #define CSL_EVETPCC_ESRH_E62_MAX (0x00000001U)
  2811. #define CSL_EVETPCC_ESRH_E37_MASK (0x00000020U)
  2812. #define CSL_EVETPCC_ESRH_E37_SHIFT (5U)
  2813. #define CSL_EVETPCC_ESRH_E37_RESETVAL (0x00000000U)
  2814. #define CSL_EVETPCC_ESRH_E37_MAX (0x00000001U)
  2815. #define CSL_EVETPCC_ESRH_E38_MASK (0x00000040U)
  2816. #define CSL_EVETPCC_ESRH_E38_SHIFT (6U)
  2817. #define CSL_EVETPCC_ESRH_E38_RESETVAL (0x00000000U)
  2818. #define CSL_EVETPCC_ESRH_E38_MAX (0x00000001U)
  2819. #define CSL_EVETPCC_ESRH_E39_MASK (0x00000080U)
  2820. #define CSL_EVETPCC_ESRH_E39_SHIFT (7U)
  2821. #define CSL_EVETPCC_ESRH_E39_RESETVAL (0x00000000U)
  2822. #define CSL_EVETPCC_ESRH_E39_MAX (0x00000001U)
  2823. #define CSL_EVETPCC_ESRH_E40_MASK (0x00000100U)
  2824. #define CSL_EVETPCC_ESRH_E40_SHIFT (8U)
  2825. #define CSL_EVETPCC_ESRH_E40_RESETVAL (0x00000000U)
  2826. #define CSL_EVETPCC_ESRH_E40_MAX (0x00000001U)
  2827. #define CSL_EVETPCC_ESRH_RESETVAL (0x00000000U)
  2828. /* CER */
  2829. #define CSL_EVETPCC_CER_E6_MASK (0x00000040U)
  2830. #define CSL_EVETPCC_CER_E6_SHIFT (6U)
  2831. #define CSL_EVETPCC_CER_E6_RESETVAL (0x00000000U)
  2832. #define CSL_EVETPCC_CER_E6_MAX (0x00000001U)
  2833. #define CSL_EVETPCC_CER_E25_MASK (0x02000000U)
  2834. #define CSL_EVETPCC_CER_E25_SHIFT (25U)
  2835. #define CSL_EVETPCC_CER_E25_RESETVAL (0x00000000U)
  2836. #define CSL_EVETPCC_CER_E25_MAX (0x00000001U)
  2837. #define CSL_EVETPCC_CER_E18_MASK (0x00040000U)
  2838. #define CSL_EVETPCC_CER_E18_SHIFT (18U)
  2839. #define CSL_EVETPCC_CER_E18_RESETVAL (0x00000000U)
  2840. #define CSL_EVETPCC_CER_E18_MAX (0x00000001U)
  2841. #define CSL_EVETPCC_CER_E7_MASK (0x00000080U)
  2842. #define CSL_EVETPCC_CER_E7_SHIFT (7U)
  2843. #define CSL_EVETPCC_CER_E7_RESETVAL (0x00000000U)
  2844. #define CSL_EVETPCC_CER_E7_MAX (0x00000001U)
  2845. #define CSL_EVETPCC_CER_E24_MASK (0x01000000U)
  2846. #define CSL_EVETPCC_CER_E24_SHIFT (24U)
  2847. #define CSL_EVETPCC_CER_E24_RESETVAL (0x00000000U)
  2848. #define CSL_EVETPCC_CER_E24_MAX (0x00000001U)
  2849. #define CSL_EVETPCC_CER_E31_MASK (0x80000000U)
  2850. #define CSL_EVETPCC_CER_E31_SHIFT (31U)
  2851. #define CSL_EVETPCC_CER_E31_RESETVAL (0x00000000U)
  2852. #define CSL_EVETPCC_CER_E31_MAX (0x00000001U)
  2853. #define CSL_EVETPCC_CER_E8_MASK (0x00000100U)
  2854. #define CSL_EVETPCC_CER_E8_SHIFT (8U)
  2855. #define CSL_EVETPCC_CER_E8_RESETVAL (0x00000000U)
  2856. #define CSL_EVETPCC_CER_E8_MAX (0x00000001U)
  2857. #define CSL_EVETPCC_CER_E26_MASK (0x04000000U)
  2858. #define CSL_EVETPCC_CER_E26_SHIFT (26U)
  2859. #define CSL_EVETPCC_CER_E26_RESETVAL (0x00000000U)
  2860. #define CSL_EVETPCC_CER_E26_MAX (0x00000001U)
  2861. #define CSL_EVETPCC_CER_E29_MASK (0x20000000U)
  2862. #define CSL_EVETPCC_CER_E29_SHIFT (29U)
  2863. #define CSL_EVETPCC_CER_E29_RESETVAL (0x00000000U)
  2864. #define CSL_EVETPCC_CER_E29_MAX (0x00000001U)
  2865. #define CSL_EVETPCC_CER_E9_MASK (0x00000200U)
  2866. #define CSL_EVETPCC_CER_E9_SHIFT (9U)
  2867. #define CSL_EVETPCC_CER_E9_RESETVAL (0x00000000U)
  2868. #define CSL_EVETPCC_CER_E9_MAX (0x00000001U)
  2869. #define CSL_EVETPCC_CER_E30_MASK (0x40000000U)
  2870. #define CSL_EVETPCC_CER_E30_SHIFT (30U)
  2871. #define CSL_EVETPCC_CER_E30_RESETVAL (0x00000000U)
  2872. #define CSL_EVETPCC_CER_E30_MAX (0x00000001U)
  2873. #define CSL_EVETPCC_CER_E10_MASK (0x00000400U)
  2874. #define CSL_EVETPCC_CER_E10_SHIFT (10U)
  2875. #define CSL_EVETPCC_CER_E10_RESETVAL (0x00000000U)
  2876. #define CSL_EVETPCC_CER_E10_MAX (0x00000001U)
  2877. #define CSL_EVETPCC_CER_E28_MASK (0x10000000U)
  2878. #define CSL_EVETPCC_CER_E28_SHIFT (28U)
  2879. #define CSL_EVETPCC_CER_E28_RESETVAL (0x00000000U)
  2880. #define CSL_EVETPCC_CER_E28_MAX (0x00000001U)
  2881. #define CSL_EVETPCC_CER_E11_MASK (0x00000800U)
  2882. #define CSL_EVETPCC_CER_E11_SHIFT (11U)
  2883. #define CSL_EVETPCC_CER_E11_RESETVAL (0x00000000U)
  2884. #define CSL_EVETPCC_CER_E11_MAX (0x00000001U)
  2885. #define CSL_EVETPCC_CER_E27_MASK (0x08000000U)
  2886. #define CSL_EVETPCC_CER_E27_SHIFT (27U)
  2887. #define CSL_EVETPCC_CER_E27_RESETVAL (0x00000000U)
  2888. #define CSL_EVETPCC_CER_E27_MAX (0x00000001U)
  2889. #define CSL_EVETPCC_CER_E0_MASK (0x00000001U)
  2890. #define CSL_EVETPCC_CER_E0_SHIFT (0U)
  2891. #define CSL_EVETPCC_CER_E0_RESETVAL (0x00000000U)
  2892. #define CSL_EVETPCC_CER_E0_MAX (0x00000001U)
  2893. #define CSL_EVETPCC_CER_E12_MASK (0x00001000U)
  2894. #define CSL_EVETPCC_CER_E12_SHIFT (12U)
  2895. #define CSL_EVETPCC_CER_E12_RESETVAL (0x00000000U)
  2896. #define CSL_EVETPCC_CER_E12_MAX (0x00000001U)
  2897. #define CSL_EVETPCC_CER_E1_MASK (0x00000002U)
  2898. #define CSL_EVETPCC_CER_E1_SHIFT (1U)
  2899. #define CSL_EVETPCC_CER_E1_RESETVAL (0x00000000U)
  2900. #define CSL_EVETPCC_CER_E1_MAX (0x00000001U)
  2901. #define CSL_EVETPCC_CER_E13_MASK (0x00002000U)
  2902. #define CSL_EVETPCC_CER_E13_SHIFT (13U)
  2903. #define CSL_EVETPCC_CER_E13_RESETVAL (0x00000000U)
  2904. #define CSL_EVETPCC_CER_E13_MAX (0x00000001U)
  2905. #define CSL_EVETPCC_CER_E19_MASK (0x00080000U)
  2906. #define CSL_EVETPCC_CER_E19_SHIFT (19U)
  2907. #define CSL_EVETPCC_CER_E19_RESETVAL (0x00000000U)
  2908. #define CSL_EVETPCC_CER_E19_MAX (0x00000001U)
  2909. #define CSL_EVETPCC_CER_E2_MASK (0x00000004U)
  2910. #define CSL_EVETPCC_CER_E2_SHIFT (2U)
  2911. #define CSL_EVETPCC_CER_E2_RESETVAL (0x00000000U)
  2912. #define CSL_EVETPCC_CER_E2_MAX (0x00000001U)
  2913. #define CSL_EVETPCC_CER_E14_MASK (0x00004000U)
  2914. #define CSL_EVETPCC_CER_E14_SHIFT (14U)
  2915. #define CSL_EVETPCC_CER_E14_RESETVAL (0x00000000U)
  2916. #define CSL_EVETPCC_CER_E14_MAX (0x00000001U)
  2917. #define CSL_EVETPCC_CER_E3_MASK (0x00000008U)
  2918. #define CSL_EVETPCC_CER_E3_SHIFT (3U)
  2919. #define CSL_EVETPCC_CER_E3_RESETVAL (0x00000000U)
  2920. #define CSL_EVETPCC_CER_E3_MAX (0x00000001U)
  2921. #define CSL_EVETPCC_CER_E15_MASK (0x00008000U)
  2922. #define CSL_EVETPCC_CER_E15_SHIFT (15U)
  2923. #define CSL_EVETPCC_CER_E15_RESETVAL (0x00000000U)
  2924. #define CSL_EVETPCC_CER_E15_MAX (0x00000001U)
  2925. #define CSL_EVETPCC_CER_E21_MASK (0x00200000U)
  2926. #define CSL_EVETPCC_CER_E21_SHIFT (21U)
  2927. #define CSL_EVETPCC_CER_E21_RESETVAL (0x00000000U)
  2928. #define CSL_EVETPCC_CER_E21_MAX (0x00000001U)
  2929. #define CSL_EVETPCC_CER_E20_MASK (0x00100000U)
  2930. #define CSL_EVETPCC_CER_E20_SHIFT (20U)
  2931. #define CSL_EVETPCC_CER_E20_RESETVAL (0x00000000U)
  2932. #define CSL_EVETPCC_CER_E20_MAX (0x00000001U)
  2933. #define CSL_EVETPCC_CER_E4_MASK (0x00000010U)
  2934. #define CSL_EVETPCC_CER_E4_SHIFT (4U)
  2935. #define CSL_EVETPCC_CER_E4_RESETVAL (0x00000000U)
  2936. #define CSL_EVETPCC_CER_E4_MAX (0x00000001U)
  2937. #define CSL_EVETPCC_CER_E23_MASK (0x00800000U)
  2938. #define CSL_EVETPCC_CER_E23_SHIFT (23U)
  2939. #define CSL_EVETPCC_CER_E23_RESETVAL (0x00000000U)
  2940. #define CSL_EVETPCC_CER_E23_MAX (0x00000001U)
  2941. #define CSL_EVETPCC_CER_E16_MASK (0x00010000U)
  2942. #define CSL_EVETPCC_CER_E16_SHIFT (16U)
  2943. #define CSL_EVETPCC_CER_E16_RESETVAL (0x00000000U)
  2944. #define CSL_EVETPCC_CER_E16_MAX (0x00000001U)
  2945. #define CSL_EVETPCC_CER_E5_MASK (0x00000020U)
  2946. #define CSL_EVETPCC_CER_E5_SHIFT (5U)
  2947. #define CSL_EVETPCC_CER_E5_RESETVAL (0x00000000U)
  2948. #define CSL_EVETPCC_CER_E5_MAX (0x00000001U)
  2949. #define CSL_EVETPCC_CER_E22_MASK (0x00400000U)
  2950. #define CSL_EVETPCC_CER_E22_SHIFT (22U)
  2951. #define CSL_EVETPCC_CER_E22_RESETVAL (0x00000000U)
  2952. #define CSL_EVETPCC_CER_E22_MAX (0x00000001U)
  2953. #define CSL_EVETPCC_CER_E17_MASK (0x00020000U)
  2954. #define CSL_EVETPCC_CER_E17_SHIFT (17U)
  2955. #define CSL_EVETPCC_CER_E17_RESETVAL (0x00000000U)
  2956. #define CSL_EVETPCC_CER_E17_MAX (0x00000001U)
  2957. #define CSL_EVETPCC_CER_RESETVAL (0x00000000U)
  2958. /* CERH */
  2959. #define CSL_EVETPCC_CERH_E49_MASK (0x00020000U)
  2960. #define CSL_EVETPCC_CERH_E49_SHIFT (17U)
  2961. #define CSL_EVETPCC_CERH_E49_RESETVAL (0x00000000U)
  2962. #define CSL_EVETPCC_CERH_E49_MAX (0x00000001U)
  2963. #define CSL_EVETPCC_CERH_E38_MASK (0x00000040U)
  2964. #define CSL_EVETPCC_CERH_E38_SHIFT (6U)
  2965. #define CSL_EVETPCC_CERH_E38_RESETVAL (0x00000000U)
  2966. #define CSL_EVETPCC_CERH_E38_MAX (0x00000001U)
  2967. #define CSL_EVETPCC_CERH_E39_MASK (0x00000080U)
  2968. #define CSL_EVETPCC_CERH_E39_SHIFT (7U)
  2969. #define CSL_EVETPCC_CERH_E39_RESETVAL (0x00000000U)
  2970. #define CSL_EVETPCC_CERH_E39_MAX (0x00000001U)
  2971. #define CSL_EVETPCC_CERH_E40_MASK (0x00000100U)
  2972. #define CSL_EVETPCC_CERH_E40_SHIFT (8U)
  2973. #define CSL_EVETPCC_CERH_E40_RESETVAL (0x00000000U)
  2974. #define CSL_EVETPCC_CERH_E40_MAX (0x00000001U)
  2975. #define CSL_EVETPCC_CERH_E63_MASK (0x80000000U)
  2976. #define CSL_EVETPCC_CERH_E63_SHIFT (31U)
  2977. #define CSL_EVETPCC_CERH_E63_RESETVAL (0x00000000U)
  2978. #define CSL_EVETPCC_CERH_E63_MAX (0x00000001U)
  2979. #define CSL_EVETPCC_CERH_E41_MASK (0x00000200U)
  2980. #define CSL_EVETPCC_CERH_E41_SHIFT (9U)
  2981. #define CSL_EVETPCC_CERH_E41_RESETVAL (0x00000000U)
  2982. #define CSL_EVETPCC_CERH_E41_MAX (0x00000001U)
  2983. #define CSL_EVETPCC_CERH_E62_MASK (0x40000000U)
  2984. #define CSL_EVETPCC_CERH_E62_SHIFT (30U)
  2985. #define CSL_EVETPCC_CERH_E62_RESETVAL (0x00000000U)
  2986. #define CSL_EVETPCC_CERH_E62_MAX (0x00000001U)
  2987. #define CSL_EVETPCC_CERH_E61_MASK (0x20000000U)
  2988. #define CSL_EVETPCC_CERH_E61_SHIFT (29U)
  2989. #define CSL_EVETPCC_CERH_E61_RESETVAL (0x00000000U)
  2990. #define CSL_EVETPCC_CERH_E61_MAX (0x00000001U)
  2991. #define CSL_EVETPCC_CERH_E42_MASK (0x00000400U)
  2992. #define CSL_EVETPCC_CERH_E42_SHIFT (10U)
  2993. #define CSL_EVETPCC_CERH_E42_RESETVAL (0x00000000U)
  2994. #define CSL_EVETPCC_CERH_E42_MAX (0x00000001U)
  2995. #define CSL_EVETPCC_CERH_E32_MASK (0x00000001U)
  2996. #define CSL_EVETPCC_CERH_E32_SHIFT (0U)
  2997. #define CSL_EVETPCC_CERH_E32_RESETVAL (0x00000000U)
  2998. #define CSL_EVETPCC_CERH_E32_MAX (0x00000001U)
  2999. #define CSL_EVETPCC_CERH_E57_MASK (0x02000000U)
  3000. #define CSL_EVETPCC_CERH_E57_SHIFT (25U)
  3001. #define CSL_EVETPCC_CERH_E57_RESETVAL (0x00000000U)
  3002. #define CSL_EVETPCC_CERH_E57_MAX (0x00000001U)
  3003. #define CSL_EVETPCC_CERH_E43_MASK (0x00000800U)
  3004. #define CSL_EVETPCC_CERH_E43_SHIFT (11U)
  3005. #define CSL_EVETPCC_CERH_E43_RESETVAL (0x00000000U)
  3006. #define CSL_EVETPCC_CERH_E43_MAX (0x00000001U)
  3007. #define CSL_EVETPCC_CERH_E58_MASK (0x04000000U)
  3008. #define CSL_EVETPCC_CERH_E58_SHIFT (26U)
  3009. #define CSL_EVETPCC_CERH_E58_RESETVAL (0x00000000U)
  3010. #define CSL_EVETPCC_CERH_E58_MAX (0x00000001U)
  3011. #define CSL_EVETPCC_CERH_E44_MASK (0x00001000U)
  3012. #define CSL_EVETPCC_CERH_E44_SHIFT (12U)
  3013. #define CSL_EVETPCC_CERH_E44_RESETVAL (0x00000000U)
  3014. #define CSL_EVETPCC_CERH_E44_MAX (0x00000001U)
  3015. #define CSL_EVETPCC_CERH_E59_MASK (0x08000000U)
  3016. #define CSL_EVETPCC_CERH_E59_SHIFT (27U)
  3017. #define CSL_EVETPCC_CERH_E59_RESETVAL (0x00000000U)
  3018. #define CSL_EVETPCC_CERH_E59_MAX (0x00000001U)
  3019. #define CSL_EVETPCC_CERH_E60_MASK (0x10000000U)
  3020. #define CSL_EVETPCC_CERH_E60_SHIFT (28U)
  3021. #define CSL_EVETPCC_CERH_E60_RESETVAL (0x00000000U)
  3022. #define CSL_EVETPCC_CERH_E60_MAX (0x00000001U)
  3023. #define CSL_EVETPCC_CERH_E45_MASK (0x00002000U)
  3024. #define CSL_EVETPCC_CERH_E45_SHIFT (13U)
  3025. #define CSL_EVETPCC_CERH_E45_RESETVAL (0x00000000U)
  3026. #define CSL_EVETPCC_CERH_E45_MAX (0x00000001U)
  3027. #define CSL_EVETPCC_CERH_E33_MASK (0x00000002U)
  3028. #define CSL_EVETPCC_CERH_E33_SHIFT (1U)
  3029. #define CSL_EVETPCC_CERH_E33_RESETVAL (0x00000000U)
  3030. #define CSL_EVETPCC_CERH_E33_MAX (0x00000001U)
  3031. #define CSL_EVETPCC_CERH_E46_MASK (0x00004000U)
  3032. #define CSL_EVETPCC_CERH_E46_SHIFT (14U)
  3033. #define CSL_EVETPCC_CERH_E46_RESETVAL (0x00000000U)
  3034. #define CSL_EVETPCC_CERH_E46_MAX (0x00000001U)
  3035. #define CSL_EVETPCC_CERH_E34_MASK (0x00000004U)
  3036. #define CSL_EVETPCC_CERH_E34_SHIFT (2U)
  3037. #define CSL_EVETPCC_CERH_E34_RESETVAL (0x00000000U)
  3038. #define CSL_EVETPCC_CERH_E34_MAX (0x00000001U)
  3039. #define CSL_EVETPCC_CERH_E47_MASK (0x00008000U)
  3040. #define CSL_EVETPCC_CERH_E47_SHIFT (15U)
  3041. #define CSL_EVETPCC_CERH_E47_RESETVAL (0x00000000U)
  3042. #define CSL_EVETPCC_CERH_E47_MAX (0x00000001U)
  3043. #define CSL_EVETPCC_CERH_E53_MASK (0x00200000U)
  3044. #define CSL_EVETPCC_CERH_E53_SHIFT (21U)
  3045. #define CSL_EVETPCC_CERH_E53_RESETVAL (0x00000000U)
  3046. #define CSL_EVETPCC_CERH_E53_MAX (0x00000001U)
  3047. #define CSL_EVETPCC_CERH_E54_MASK (0x00400000U)
  3048. #define CSL_EVETPCC_CERH_E54_SHIFT (22U)
  3049. #define CSL_EVETPCC_CERH_E54_RESETVAL (0x00000000U)
  3050. #define CSL_EVETPCC_CERH_E54_MAX (0x00000001U)
  3051. #define CSL_EVETPCC_CERH_E50_MASK (0x00040000U)
  3052. #define CSL_EVETPCC_CERH_E50_SHIFT (18U)
  3053. #define CSL_EVETPCC_CERH_E50_RESETVAL (0x00000000U)
  3054. #define CSL_EVETPCC_CERH_E50_MAX (0x00000001U)
  3055. #define CSL_EVETPCC_CERH_E35_MASK (0x00000008U)
  3056. #define CSL_EVETPCC_CERH_E35_SHIFT (3U)
  3057. #define CSL_EVETPCC_CERH_E35_RESETVAL (0x00000000U)
  3058. #define CSL_EVETPCC_CERH_E35_MAX (0x00000001U)
  3059. #define CSL_EVETPCC_CERH_E48_MASK (0x00010000U)
  3060. #define CSL_EVETPCC_CERH_E48_SHIFT (16U)
  3061. #define CSL_EVETPCC_CERH_E48_RESETVAL (0x00000000U)
  3062. #define CSL_EVETPCC_CERH_E48_MAX (0x00000001U)
  3063. #define CSL_EVETPCC_CERH_E56_MASK (0x01000000U)
  3064. #define CSL_EVETPCC_CERH_E56_SHIFT (24U)
  3065. #define CSL_EVETPCC_CERH_E56_RESETVAL (0x00000000U)
  3066. #define CSL_EVETPCC_CERH_E56_MAX (0x00000001U)
  3067. #define CSL_EVETPCC_CERH_E51_MASK (0x00080000U)
  3068. #define CSL_EVETPCC_CERH_E51_SHIFT (19U)
  3069. #define CSL_EVETPCC_CERH_E51_RESETVAL (0x00000000U)
  3070. #define CSL_EVETPCC_CERH_E51_MAX (0x00000001U)
  3071. #define CSL_EVETPCC_CERH_E36_MASK (0x00000010U)
  3072. #define CSL_EVETPCC_CERH_E36_SHIFT (4U)
  3073. #define CSL_EVETPCC_CERH_E36_RESETVAL (0x00000000U)
  3074. #define CSL_EVETPCC_CERH_E36_MAX (0x00000001U)
  3075. #define CSL_EVETPCC_CERH_E55_MASK (0x00800000U)
  3076. #define CSL_EVETPCC_CERH_E55_SHIFT (23U)
  3077. #define CSL_EVETPCC_CERH_E55_RESETVAL (0x00000000U)
  3078. #define CSL_EVETPCC_CERH_E55_MAX (0x00000001U)
  3079. #define CSL_EVETPCC_CERH_E52_MASK (0x00100000U)
  3080. #define CSL_EVETPCC_CERH_E52_SHIFT (20U)
  3081. #define CSL_EVETPCC_CERH_E52_RESETVAL (0x00000000U)
  3082. #define CSL_EVETPCC_CERH_E52_MAX (0x00000001U)
  3083. #define CSL_EVETPCC_CERH_E37_MASK (0x00000020U)
  3084. #define CSL_EVETPCC_CERH_E37_SHIFT (5U)
  3085. #define CSL_EVETPCC_CERH_E37_RESETVAL (0x00000000U)
  3086. #define CSL_EVETPCC_CERH_E37_MAX (0x00000001U)
  3087. #define CSL_EVETPCC_CERH_RESETVAL (0x00000000U)
  3088. /* EER */
  3089. #define CSL_EVETPCC_EER_E11_MASK (0x00000800U)
  3090. #define CSL_EVETPCC_EER_E11_SHIFT (11U)
  3091. #define CSL_EVETPCC_EER_E11_RESETVAL (0x00000000U)
  3092. #define CSL_EVETPCC_EER_E11_MAX (0x00000001U)
  3093. #define CSL_EVETPCC_EER_E24_MASK (0x01000000U)
  3094. #define CSL_EVETPCC_EER_E24_SHIFT (24U)
  3095. #define CSL_EVETPCC_EER_E24_RESETVAL (0x00000000U)
  3096. #define CSL_EVETPCC_EER_E24_MAX (0x00000001U)
  3097. #define CSL_EVETPCC_EER_E10_MASK (0x00000400U)
  3098. #define CSL_EVETPCC_EER_E10_SHIFT (10U)
  3099. #define CSL_EVETPCC_EER_E10_RESETVAL (0x00000000U)
  3100. #define CSL_EVETPCC_EER_E10_MAX (0x00000001U)
  3101. #define CSL_EVETPCC_EER_E12_MASK (0x00001000U)
  3102. #define CSL_EVETPCC_EER_E12_SHIFT (12U)
  3103. #define CSL_EVETPCC_EER_E12_RESETVAL (0x00000000U)
  3104. #define CSL_EVETPCC_EER_E12_MAX (0x00000001U)
  3105. #define CSL_EVETPCC_EER_E25_MASK (0x02000000U)
  3106. #define CSL_EVETPCC_EER_E25_SHIFT (25U)
  3107. #define CSL_EVETPCC_EER_E25_RESETVAL (0x00000000U)
  3108. #define CSL_EVETPCC_EER_E25_MAX (0x00000001U)
  3109. #define CSL_EVETPCC_EER_E9_MASK (0x00000200U)
  3110. #define CSL_EVETPCC_EER_E9_SHIFT (9U)
  3111. #define CSL_EVETPCC_EER_E9_RESETVAL (0x00000000U)
  3112. #define CSL_EVETPCC_EER_E9_MAX (0x00000001U)
  3113. #define CSL_EVETPCC_EER_E21_MASK (0x00200000U)
  3114. #define CSL_EVETPCC_EER_E21_SHIFT (21U)
  3115. #define CSL_EVETPCC_EER_E21_RESETVAL (0x00000000U)
  3116. #define CSL_EVETPCC_EER_E21_MAX (0x00000001U)
  3117. #define CSL_EVETPCC_EER_E22_MASK (0x00400000U)
  3118. #define CSL_EVETPCC_EER_E22_SHIFT (22U)
  3119. #define CSL_EVETPCC_EER_E22_RESETVAL (0x00000000U)
  3120. #define CSL_EVETPCC_EER_E22_MAX (0x00000001U)
  3121. #define CSL_EVETPCC_EER_E0_MASK (0x00000001U)
  3122. #define CSL_EVETPCC_EER_E0_SHIFT (0U)
  3123. #define CSL_EVETPCC_EER_E0_RESETVAL (0x00000000U)
  3124. #define CSL_EVETPCC_EER_E0_MAX (0x00000001U)
  3125. #define CSL_EVETPCC_EER_E23_MASK (0x00800000U)
  3126. #define CSL_EVETPCC_EER_E23_SHIFT (23U)
  3127. #define CSL_EVETPCC_EER_E23_RESETVAL (0x00000000U)
  3128. #define CSL_EVETPCC_EER_E23_MAX (0x00000001U)
  3129. #define CSL_EVETPCC_EER_E19_MASK (0x00080000U)
  3130. #define CSL_EVETPCC_EER_E19_SHIFT (19U)
  3131. #define CSL_EVETPCC_EER_E19_RESETVAL (0x00000000U)
  3132. #define CSL_EVETPCC_EER_E19_MAX (0x00000001U)
  3133. #define CSL_EVETPCC_EER_E20_MASK (0x00100000U)
  3134. #define CSL_EVETPCC_EER_E20_SHIFT (20U)
  3135. #define CSL_EVETPCC_EER_E20_RESETVAL (0x00000000U)
  3136. #define CSL_EVETPCC_EER_E20_MAX (0x00000001U)
  3137. #define CSL_EVETPCC_EER_E29_MASK (0x20000000U)
  3138. #define CSL_EVETPCC_EER_E29_SHIFT (29U)
  3139. #define CSL_EVETPCC_EER_E29_RESETVAL (0x00000000U)
  3140. #define CSL_EVETPCC_EER_E29_MAX (0x00000001U)
  3141. #define CSL_EVETPCC_EER_E30_MASK (0x40000000U)
  3142. #define CSL_EVETPCC_EER_E30_SHIFT (30U)
  3143. #define CSL_EVETPCC_EER_E30_RESETVAL (0x00000000U)
  3144. #define CSL_EVETPCC_EER_E30_MAX (0x00000001U)
  3145. #define CSL_EVETPCC_EER_E18_MASK (0x00040000U)
  3146. #define CSL_EVETPCC_EER_E18_SHIFT (18U)
  3147. #define CSL_EVETPCC_EER_E18_RESETVAL (0x00000000U)
  3148. #define CSL_EVETPCC_EER_E18_MAX (0x00000001U)
  3149. #define CSL_EVETPCC_EER_E31_MASK (0x80000000U)
  3150. #define CSL_EVETPCC_EER_E31_SHIFT (31U)
  3151. #define CSL_EVETPCC_EER_E31_RESETVAL (0x00000000U)
  3152. #define CSL_EVETPCC_EER_E31_MAX (0x00000001U)
  3153. #define CSL_EVETPCC_EER_E5_MASK (0x00000020U)
  3154. #define CSL_EVETPCC_EER_E5_SHIFT (5U)
  3155. #define CSL_EVETPCC_EER_E5_RESETVAL (0x00000000U)
  3156. #define CSL_EVETPCC_EER_E5_MAX (0x00000001U)
  3157. #define CSL_EVETPCC_EER_E6_MASK (0x00000040U)
  3158. #define CSL_EVETPCC_EER_E6_SHIFT (6U)
  3159. #define CSL_EVETPCC_EER_E6_RESETVAL (0x00000000U)
  3160. #define CSL_EVETPCC_EER_E6_MAX (0x00000001U)
  3161. #define CSL_EVETPCC_EER_E8_MASK (0x00000100U)
  3162. #define CSL_EVETPCC_EER_E8_SHIFT (8U)
  3163. #define CSL_EVETPCC_EER_E8_RESETVAL (0x00000000U)
  3164. #define CSL_EVETPCC_EER_E8_MAX (0x00000001U)
  3165. #define CSL_EVETPCC_EER_E7_MASK (0x00000080U)
  3166. #define CSL_EVETPCC_EER_E7_SHIFT (7U)
  3167. #define CSL_EVETPCC_EER_E7_RESETVAL (0x00000000U)
  3168. #define CSL_EVETPCC_EER_E7_MAX (0x00000001U)
  3169. #define CSL_EVETPCC_EER_E28_MASK (0x10000000U)
  3170. #define CSL_EVETPCC_EER_E28_SHIFT (28U)
  3171. #define CSL_EVETPCC_EER_E28_RESETVAL (0x00000000U)
  3172. #define CSL_EVETPCC_EER_E28_MAX (0x00000001U)
  3173. #define CSL_EVETPCC_EER_E3_MASK (0x00000008U)
  3174. #define CSL_EVETPCC_EER_E3_SHIFT (3U)
  3175. #define CSL_EVETPCC_EER_E3_RESETVAL (0x00000000U)
  3176. #define CSL_EVETPCC_EER_E3_MAX (0x00000001U)
  3177. #define CSL_EVETPCC_EER_E2_MASK (0x00000004U)
  3178. #define CSL_EVETPCC_EER_E2_SHIFT (2U)
  3179. #define CSL_EVETPCC_EER_E2_RESETVAL (0x00000000U)
  3180. #define CSL_EVETPCC_EER_E2_MAX (0x00000001U)
  3181. #define CSL_EVETPCC_EER_E1_MASK (0x00000002U)
  3182. #define CSL_EVETPCC_EER_E1_SHIFT (1U)
  3183. #define CSL_EVETPCC_EER_E1_RESETVAL (0x00000000U)
  3184. #define CSL_EVETPCC_EER_E1_MAX (0x00000001U)
  3185. #define CSL_EVETPCC_EER_E13_MASK (0x00002000U)
  3186. #define CSL_EVETPCC_EER_E13_SHIFT (13U)
  3187. #define CSL_EVETPCC_EER_E13_RESETVAL (0x00000000U)
  3188. #define CSL_EVETPCC_EER_E13_MAX (0x00000001U)
  3189. #define CSL_EVETPCC_EER_E17_MASK (0x00020000U)
  3190. #define CSL_EVETPCC_EER_E17_SHIFT (17U)
  3191. #define CSL_EVETPCC_EER_E17_RESETVAL (0x00000000U)
  3192. #define CSL_EVETPCC_EER_E17_MAX (0x00000001U)
  3193. #define CSL_EVETPCC_EER_E26_MASK (0x04000000U)
  3194. #define CSL_EVETPCC_EER_E26_SHIFT (26U)
  3195. #define CSL_EVETPCC_EER_E26_RESETVAL (0x00000000U)
  3196. #define CSL_EVETPCC_EER_E26_MAX (0x00000001U)
  3197. #define CSL_EVETPCC_EER_E14_MASK (0x00004000U)
  3198. #define CSL_EVETPCC_EER_E14_SHIFT (14U)
  3199. #define CSL_EVETPCC_EER_E14_RESETVAL (0x00000000U)
  3200. #define CSL_EVETPCC_EER_E14_MAX (0x00000001U)
  3201. #define CSL_EVETPCC_EER_E16_MASK (0x00010000U)
  3202. #define CSL_EVETPCC_EER_E16_SHIFT (16U)
  3203. #define CSL_EVETPCC_EER_E16_RESETVAL (0x00000000U)
  3204. #define CSL_EVETPCC_EER_E16_MAX (0x00000001U)
  3205. #define CSL_EVETPCC_EER_E27_MASK (0x08000000U)
  3206. #define CSL_EVETPCC_EER_E27_SHIFT (27U)
  3207. #define CSL_EVETPCC_EER_E27_RESETVAL (0x00000000U)
  3208. #define CSL_EVETPCC_EER_E27_MAX (0x00000001U)
  3209. #define CSL_EVETPCC_EER_E4_MASK (0x00000010U)
  3210. #define CSL_EVETPCC_EER_E4_SHIFT (4U)
  3211. #define CSL_EVETPCC_EER_E4_RESETVAL (0x00000000U)
  3212. #define CSL_EVETPCC_EER_E4_MAX (0x00000001U)
  3213. #define CSL_EVETPCC_EER_E15_MASK (0x00008000U)
  3214. #define CSL_EVETPCC_EER_E15_SHIFT (15U)
  3215. #define CSL_EVETPCC_EER_E15_RESETVAL (0x00000000U)
  3216. #define CSL_EVETPCC_EER_E15_MAX (0x00000001U)
  3217. #define CSL_EVETPCC_EER_RESETVAL (0x00000000U)
  3218. /* EERH */
  3219. #define CSL_EVETPCC_EERH_E47_MASK (0x00008000U)
  3220. #define CSL_EVETPCC_EERH_E47_SHIFT (15U)
  3221. #define CSL_EVETPCC_EERH_E47_RESETVAL (0x00000000U)
  3222. #define CSL_EVETPCC_EERH_E47_MAX (0x00000001U)
  3223. #define CSL_EVETPCC_EERH_E45_MASK (0x00002000U)
  3224. #define CSL_EVETPCC_EERH_E45_SHIFT (13U)
  3225. #define CSL_EVETPCC_EERH_E45_RESETVAL (0x00000000U)
  3226. #define CSL_EVETPCC_EERH_E45_MAX (0x00000001U)
  3227. #define CSL_EVETPCC_EERH_E35_MASK (0x00000008U)
  3228. #define CSL_EVETPCC_EERH_E35_SHIFT (3U)
  3229. #define CSL_EVETPCC_EERH_E35_RESETVAL (0x00000000U)
  3230. #define CSL_EVETPCC_EERH_E35_MAX (0x00000001U)
  3231. #define CSL_EVETPCC_EERH_E56_MASK (0x01000000U)
  3232. #define CSL_EVETPCC_EERH_E56_SHIFT (24U)
  3233. #define CSL_EVETPCC_EERH_E56_RESETVAL (0x00000000U)
  3234. #define CSL_EVETPCC_EERH_E56_MAX (0x00000001U)
  3235. #define CSL_EVETPCC_EERH_E46_MASK (0x00004000U)
  3236. #define CSL_EVETPCC_EERH_E46_SHIFT (14U)
  3237. #define CSL_EVETPCC_EERH_E46_RESETVAL (0x00000000U)
  3238. #define CSL_EVETPCC_EERH_E46_MAX (0x00000001U)
  3239. #define CSL_EVETPCC_EERH_E36_MASK (0x00000010U)
  3240. #define CSL_EVETPCC_EERH_E36_SHIFT (4U)
  3241. #define CSL_EVETPCC_EERH_E36_RESETVAL (0x00000000U)
  3242. #define CSL_EVETPCC_EERH_E36_MAX (0x00000001U)
  3243. #define CSL_EVETPCC_EERH_E55_MASK (0x00800000U)
  3244. #define CSL_EVETPCC_EERH_E55_SHIFT (23U)
  3245. #define CSL_EVETPCC_EERH_E55_RESETVAL (0x00000000U)
  3246. #define CSL_EVETPCC_EERH_E55_MAX (0x00000001U)
  3247. #define CSL_EVETPCC_EERH_E33_MASK (0x00000002U)
  3248. #define CSL_EVETPCC_EERH_E33_SHIFT (1U)
  3249. #define CSL_EVETPCC_EERH_E33_RESETVAL (0x00000000U)
  3250. #define CSL_EVETPCC_EERH_E33_MAX (0x00000001U)
  3251. #define CSL_EVETPCC_EERH_E54_MASK (0x00400000U)
  3252. #define CSL_EVETPCC_EERH_E54_SHIFT (22U)
  3253. #define CSL_EVETPCC_EERH_E54_RESETVAL (0x00000000U)
  3254. #define CSL_EVETPCC_EERH_E54_MAX (0x00000001U)
  3255. #define CSL_EVETPCC_EERH_E43_MASK (0x00000800U)
  3256. #define CSL_EVETPCC_EERH_E43_SHIFT (11U)
  3257. #define CSL_EVETPCC_EERH_E43_RESETVAL (0x00000000U)
  3258. #define CSL_EVETPCC_EERH_E43_MAX (0x00000001U)
  3259. #define CSL_EVETPCC_EERH_E53_MASK (0x00200000U)
  3260. #define CSL_EVETPCC_EERH_E53_SHIFT (21U)
  3261. #define CSL_EVETPCC_EERH_E53_RESETVAL (0x00000000U)
  3262. #define CSL_EVETPCC_EERH_E53_MAX (0x00000001U)
  3263. #define CSL_EVETPCC_EERH_E63_MASK (0x80000000U)
  3264. #define CSL_EVETPCC_EERH_E63_SHIFT (31U)
  3265. #define CSL_EVETPCC_EERH_E63_RESETVAL (0x00000000U)
  3266. #define CSL_EVETPCC_EERH_E63_MAX (0x00000001U)
  3267. #define CSL_EVETPCC_EERH_E34_MASK (0x00000004U)
  3268. #define CSL_EVETPCC_EERH_E34_SHIFT (2U)
  3269. #define CSL_EVETPCC_EERH_E34_RESETVAL (0x00000000U)
  3270. #define CSL_EVETPCC_EERH_E34_MAX (0x00000001U)
  3271. #define CSL_EVETPCC_EERH_E44_MASK (0x00001000U)
  3272. #define CSL_EVETPCC_EERH_E44_SHIFT (12U)
  3273. #define CSL_EVETPCC_EERH_E44_RESETVAL (0x00000000U)
  3274. #define CSL_EVETPCC_EERH_E44_MAX (0x00000001U)
  3275. #define CSL_EVETPCC_EERH_E52_MASK (0x00100000U)
  3276. #define CSL_EVETPCC_EERH_E52_SHIFT (20U)
  3277. #define CSL_EVETPCC_EERH_E52_RESETVAL (0x00000000U)
  3278. #define CSL_EVETPCC_EERH_E52_MAX (0x00000001U)
  3279. #define CSL_EVETPCC_EERH_E41_MASK (0x00000200U)
  3280. #define CSL_EVETPCC_EERH_E41_SHIFT (9U)
  3281. #define CSL_EVETPCC_EERH_E41_RESETVAL (0x00000000U)
  3282. #define CSL_EVETPCC_EERH_E41_MAX (0x00000001U)
  3283. #define CSL_EVETPCC_EERH_E62_MASK (0x40000000U)
  3284. #define CSL_EVETPCC_EERH_E62_SHIFT (30U)
  3285. #define CSL_EVETPCC_EERH_E62_RESETVAL (0x00000000U)
  3286. #define CSL_EVETPCC_EERH_E62_MAX (0x00000001U)
  3287. #define CSL_EVETPCC_EERH_E32_MASK (0x00000001U)
  3288. #define CSL_EVETPCC_EERH_E32_SHIFT (0U)
  3289. #define CSL_EVETPCC_EERH_E32_RESETVAL (0x00000000U)
  3290. #define CSL_EVETPCC_EERH_E32_MAX (0x00000001U)
  3291. #define CSL_EVETPCC_EERH_E51_MASK (0x00080000U)
  3292. #define CSL_EVETPCC_EERH_E51_SHIFT (19U)
  3293. #define CSL_EVETPCC_EERH_E51_RESETVAL (0x00000000U)
  3294. #define CSL_EVETPCC_EERH_E51_MAX (0x00000001U)
  3295. #define CSL_EVETPCC_EERH_E42_MASK (0x00000400U)
  3296. #define CSL_EVETPCC_EERH_E42_SHIFT (10U)
  3297. #define CSL_EVETPCC_EERH_E42_RESETVAL (0x00000000U)
  3298. #define CSL_EVETPCC_EERH_E42_MAX (0x00000001U)
  3299. #define CSL_EVETPCC_EERH_E61_MASK (0x20000000U)
  3300. #define CSL_EVETPCC_EERH_E61_SHIFT (29U)
  3301. #define CSL_EVETPCC_EERH_E61_RESETVAL (0x00000000U)
  3302. #define CSL_EVETPCC_EERH_E61_MAX (0x00000001U)
  3303. #define CSL_EVETPCC_EERH_E50_MASK (0x00040000U)
  3304. #define CSL_EVETPCC_EERH_E50_SHIFT (18U)
  3305. #define CSL_EVETPCC_EERH_E50_RESETVAL (0x00000000U)
  3306. #define CSL_EVETPCC_EERH_E50_MAX (0x00000001U)
  3307. #define CSL_EVETPCC_EERH_E39_MASK (0x00000080U)
  3308. #define CSL_EVETPCC_EERH_E39_SHIFT (7U)
  3309. #define CSL_EVETPCC_EERH_E39_RESETVAL (0x00000000U)
  3310. #define CSL_EVETPCC_EERH_E39_MAX (0x00000001U)
  3311. #define CSL_EVETPCC_EERH_E60_MASK (0x10000000U)
  3312. #define CSL_EVETPCC_EERH_E60_SHIFT (28U)
  3313. #define CSL_EVETPCC_EERH_E60_RESETVAL (0x00000000U)
  3314. #define CSL_EVETPCC_EERH_E60_MAX (0x00000001U)
  3315. #define CSL_EVETPCC_EERH_E49_MASK (0x00020000U)
  3316. #define CSL_EVETPCC_EERH_E49_SHIFT (17U)
  3317. #define CSL_EVETPCC_EERH_E49_RESETVAL (0x00000000U)
  3318. #define CSL_EVETPCC_EERH_E49_MAX (0x00000001U)
  3319. #define CSL_EVETPCC_EERH_E40_MASK (0x00000100U)
  3320. #define CSL_EVETPCC_EERH_E40_SHIFT (8U)
  3321. #define CSL_EVETPCC_EERH_E40_RESETVAL (0x00000000U)
  3322. #define CSL_EVETPCC_EERH_E40_MAX (0x00000001U)
  3323. #define CSL_EVETPCC_EERH_E59_MASK (0x08000000U)
  3324. #define CSL_EVETPCC_EERH_E59_SHIFT (27U)
  3325. #define CSL_EVETPCC_EERH_E59_RESETVAL (0x00000000U)
  3326. #define CSL_EVETPCC_EERH_E59_MAX (0x00000001U)
  3327. #define CSL_EVETPCC_EERH_E48_MASK (0x00010000U)
  3328. #define CSL_EVETPCC_EERH_E48_SHIFT (16U)
  3329. #define CSL_EVETPCC_EERH_E48_RESETVAL (0x00000000U)
  3330. #define CSL_EVETPCC_EERH_E48_MAX (0x00000001U)
  3331. #define CSL_EVETPCC_EERH_E58_MASK (0x04000000U)
  3332. #define CSL_EVETPCC_EERH_E58_SHIFT (26U)
  3333. #define CSL_EVETPCC_EERH_E58_RESETVAL (0x00000000U)
  3334. #define CSL_EVETPCC_EERH_E58_MAX (0x00000001U)
  3335. #define CSL_EVETPCC_EERH_E37_MASK (0x00000020U)
  3336. #define CSL_EVETPCC_EERH_E37_SHIFT (5U)
  3337. #define CSL_EVETPCC_EERH_E37_RESETVAL (0x00000000U)
  3338. #define CSL_EVETPCC_EERH_E37_MAX (0x00000001U)
  3339. #define CSL_EVETPCC_EERH_E57_MASK (0x02000000U)
  3340. #define CSL_EVETPCC_EERH_E57_SHIFT (25U)
  3341. #define CSL_EVETPCC_EERH_E57_RESETVAL (0x00000000U)
  3342. #define CSL_EVETPCC_EERH_E57_MAX (0x00000001U)
  3343. #define CSL_EVETPCC_EERH_E38_MASK (0x00000040U)
  3344. #define CSL_EVETPCC_EERH_E38_SHIFT (6U)
  3345. #define CSL_EVETPCC_EERH_E38_RESETVAL (0x00000000U)
  3346. #define CSL_EVETPCC_EERH_E38_MAX (0x00000001U)
  3347. #define CSL_EVETPCC_EERH_RESETVAL (0x00000000U)
  3348. /* EECR */
  3349. #define CSL_EVETPCC_EECR_E30_MASK (0x40000000U)
  3350. #define CSL_EVETPCC_EECR_E30_SHIFT (30U)
  3351. #define CSL_EVETPCC_EECR_E30_RESETVAL (0x00000000U)
  3352. #define CSL_EVETPCC_EECR_E30_MAX (0x00000001U)
  3353. #define CSL_EVETPCC_EECR_E25_MASK (0x02000000U)
  3354. #define CSL_EVETPCC_EECR_E25_SHIFT (25U)
  3355. #define CSL_EVETPCC_EECR_E25_RESETVAL (0x00000000U)
  3356. #define CSL_EVETPCC_EECR_E25_MAX (0x00000001U)
  3357. #define CSL_EVETPCC_EECR_E14_MASK (0x00004000U)
  3358. #define CSL_EVETPCC_EECR_E14_SHIFT (14U)
  3359. #define CSL_EVETPCC_EECR_E14_RESETVAL (0x00000000U)
  3360. #define CSL_EVETPCC_EECR_E14_MAX (0x00000001U)
  3361. #define CSL_EVETPCC_EECR_E15_MASK (0x00008000U)
  3362. #define CSL_EVETPCC_EECR_E15_SHIFT (15U)
  3363. #define CSL_EVETPCC_EECR_E15_RESETVAL (0x00000000U)
  3364. #define CSL_EVETPCC_EECR_E15_MAX (0x00000001U)
  3365. #define CSL_EVETPCC_EECR_E5_MASK (0x00000020U)
  3366. #define CSL_EVETPCC_EECR_E5_SHIFT (5U)
  3367. #define CSL_EVETPCC_EECR_E5_RESETVAL (0x00000000U)
  3368. #define CSL_EVETPCC_EECR_E5_MAX (0x00000001U)
  3369. #define CSL_EVETPCC_EECR_E31_MASK (0x80000000U)
  3370. #define CSL_EVETPCC_EECR_E31_SHIFT (31U)
  3371. #define CSL_EVETPCC_EECR_E31_RESETVAL (0x00000000U)
  3372. #define CSL_EVETPCC_EECR_E31_MAX (0x00000001U)
  3373. #define CSL_EVETPCC_EECR_E24_MASK (0x01000000U)
  3374. #define CSL_EVETPCC_EECR_E24_SHIFT (24U)
  3375. #define CSL_EVETPCC_EECR_E24_RESETVAL (0x00000000U)
  3376. #define CSL_EVETPCC_EECR_E24_MAX (0x00000001U)
  3377. #define CSL_EVETPCC_EECR_E28_MASK (0x10000000U)
  3378. #define CSL_EVETPCC_EECR_E28_SHIFT (28U)
  3379. #define CSL_EVETPCC_EECR_E28_RESETVAL (0x00000000U)
  3380. #define CSL_EVETPCC_EECR_E28_MAX (0x00000001U)
  3381. #define CSL_EVETPCC_EECR_E6_MASK (0x00000040U)
  3382. #define CSL_EVETPCC_EECR_E6_SHIFT (6U)
  3383. #define CSL_EVETPCC_EECR_E6_RESETVAL (0x00000000U)
  3384. #define CSL_EVETPCC_EECR_E6_MAX (0x00000001U)
  3385. #define CSL_EVETPCC_EECR_E16_MASK (0x00010000U)
  3386. #define CSL_EVETPCC_EECR_E16_SHIFT (16U)
  3387. #define CSL_EVETPCC_EECR_E16_RESETVAL (0x00000000U)
  3388. #define CSL_EVETPCC_EECR_E16_MAX (0x00000001U)
  3389. #define CSL_EVETPCC_EECR_E29_MASK (0x20000000U)
  3390. #define CSL_EVETPCC_EECR_E29_SHIFT (29U)
  3391. #define CSL_EVETPCC_EECR_E29_RESETVAL (0x00000000U)
  3392. #define CSL_EVETPCC_EECR_E29_MAX (0x00000001U)
  3393. #define CSL_EVETPCC_EECR_E26_MASK (0x04000000U)
  3394. #define CSL_EVETPCC_EECR_E26_SHIFT (26U)
  3395. #define CSL_EVETPCC_EECR_E26_RESETVAL (0x00000000U)
  3396. #define CSL_EVETPCC_EECR_E26_MAX (0x00000001U)
  3397. #define CSL_EVETPCC_EECR_E8_MASK (0x00000100U)
  3398. #define CSL_EVETPCC_EECR_E8_SHIFT (8U)
  3399. #define CSL_EVETPCC_EECR_E8_RESETVAL (0x00000000U)
  3400. #define CSL_EVETPCC_EECR_E8_MAX (0x00000001U)
  3401. #define CSL_EVETPCC_EECR_E18_MASK (0x00040000U)
  3402. #define CSL_EVETPCC_EECR_E18_SHIFT (18U)
  3403. #define CSL_EVETPCC_EECR_E18_RESETVAL (0x00000000U)
  3404. #define CSL_EVETPCC_EECR_E18_MAX (0x00000001U)
  3405. #define CSL_EVETPCC_EECR_E7_MASK (0x00000080U)
  3406. #define CSL_EVETPCC_EECR_E7_SHIFT (7U)
  3407. #define CSL_EVETPCC_EECR_E7_RESETVAL (0x00000000U)
  3408. #define CSL_EVETPCC_EECR_E7_MAX (0x00000001U)
  3409. #define CSL_EVETPCC_EECR_E17_MASK (0x00020000U)
  3410. #define CSL_EVETPCC_EECR_E17_SHIFT (17U)
  3411. #define CSL_EVETPCC_EECR_E17_RESETVAL (0x00000000U)
  3412. #define CSL_EVETPCC_EECR_E17_MAX (0x00000001U)
  3413. #define CSL_EVETPCC_EECR_E10_MASK (0x00000400U)
  3414. #define CSL_EVETPCC_EECR_E10_SHIFT (10U)
  3415. #define CSL_EVETPCC_EECR_E10_RESETVAL (0x00000000U)
  3416. #define CSL_EVETPCC_EECR_E10_MAX (0x00000001U)
  3417. #define CSL_EVETPCC_EECR_E20_MASK (0x00100000U)
  3418. #define CSL_EVETPCC_EECR_E20_SHIFT (20U)
  3419. #define CSL_EVETPCC_EECR_E20_RESETVAL (0x00000000U)
  3420. #define CSL_EVETPCC_EECR_E20_MAX (0x00000001U)
  3421. #define CSL_EVETPCC_EECR_E9_MASK (0x00000200U)
  3422. #define CSL_EVETPCC_EECR_E9_SHIFT (9U)
  3423. #define CSL_EVETPCC_EECR_E9_RESETVAL (0x00000000U)
  3424. #define CSL_EVETPCC_EECR_E9_MAX (0x00000001U)
  3425. #define CSL_EVETPCC_EECR_E0_MASK (0x00000001U)
  3426. #define CSL_EVETPCC_EECR_E0_SHIFT (0U)
  3427. #define CSL_EVETPCC_EECR_E0_RESETVAL (0x00000000U)
  3428. #define CSL_EVETPCC_EECR_E0_MAX (0x00000001U)
  3429. #define CSL_EVETPCC_EECR_E19_MASK (0x00080000U)
  3430. #define CSL_EVETPCC_EECR_E19_SHIFT (19U)
  3431. #define CSL_EVETPCC_EECR_E19_RESETVAL (0x00000000U)
  3432. #define CSL_EVETPCC_EECR_E19_MAX (0x00000001U)
  3433. #define CSL_EVETPCC_EECR_E1_MASK (0x00000002U)
  3434. #define CSL_EVETPCC_EECR_E1_SHIFT (1U)
  3435. #define CSL_EVETPCC_EECR_E1_RESETVAL (0x00000000U)
  3436. #define CSL_EVETPCC_EECR_E1_MAX (0x00000001U)
  3437. #define CSL_EVETPCC_EECR_E12_MASK (0x00001000U)
  3438. #define CSL_EVETPCC_EECR_E12_SHIFT (12U)
  3439. #define CSL_EVETPCC_EECR_E12_RESETVAL (0x00000000U)
  3440. #define CSL_EVETPCC_EECR_E12_MAX (0x00000001U)
  3441. #define CSL_EVETPCC_EECR_E22_MASK (0x00400000U)
  3442. #define CSL_EVETPCC_EECR_E22_SHIFT (22U)
  3443. #define CSL_EVETPCC_EECR_E22_RESETVAL (0x00000000U)
  3444. #define CSL_EVETPCC_EECR_E22_MAX (0x00000001U)
  3445. #define CSL_EVETPCC_EECR_E2_MASK (0x00000004U)
  3446. #define CSL_EVETPCC_EECR_E2_SHIFT (2U)
  3447. #define CSL_EVETPCC_EECR_E2_RESETVAL (0x00000000U)
  3448. #define CSL_EVETPCC_EECR_E2_MAX (0x00000001U)
  3449. #define CSL_EVETPCC_EECR_E11_MASK (0x00000800U)
  3450. #define CSL_EVETPCC_EECR_E11_SHIFT (11U)
  3451. #define CSL_EVETPCC_EECR_E11_RESETVAL (0x00000000U)
  3452. #define CSL_EVETPCC_EECR_E11_MAX (0x00000001U)
  3453. #define CSL_EVETPCC_EECR_E21_MASK (0x00200000U)
  3454. #define CSL_EVETPCC_EECR_E21_SHIFT (21U)
  3455. #define CSL_EVETPCC_EECR_E21_RESETVAL (0x00000000U)
  3456. #define CSL_EVETPCC_EECR_E21_MAX (0x00000001U)
  3457. #define CSL_EVETPCC_EECR_E27_MASK (0x08000000U)
  3458. #define CSL_EVETPCC_EECR_E27_SHIFT (27U)
  3459. #define CSL_EVETPCC_EECR_E27_RESETVAL (0x00000000U)
  3460. #define CSL_EVETPCC_EECR_E27_MAX (0x00000001U)
  3461. #define CSL_EVETPCC_EECR_E3_MASK (0x00000008U)
  3462. #define CSL_EVETPCC_EECR_E3_SHIFT (3U)
  3463. #define CSL_EVETPCC_EECR_E3_RESETVAL (0x00000000U)
  3464. #define CSL_EVETPCC_EECR_E3_MAX (0x00000001U)
  3465. #define CSL_EVETPCC_EECR_E23_MASK (0x00800000U)
  3466. #define CSL_EVETPCC_EECR_E23_SHIFT (23U)
  3467. #define CSL_EVETPCC_EECR_E23_RESETVAL (0x00000000U)
  3468. #define CSL_EVETPCC_EECR_E23_MAX (0x00000001U)
  3469. #define CSL_EVETPCC_EECR_E4_MASK (0x00000010U)
  3470. #define CSL_EVETPCC_EECR_E4_SHIFT (4U)
  3471. #define CSL_EVETPCC_EECR_E4_RESETVAL (0x00000000U)
  3472. #define CSL_EVETPCC_EECR_E4_MAX (0x00000001U)
  3473. #define CSL_EVETPCC_EECR_E13_MASK (0x00002000U)
  3474. #define CSL_EVETPCC_EECR_E13_SHIFT (13U)
  3475. #define CSL_EVETPCC_EECR_E13_RESETVAL (0x00000000U)
  3476. #define CSL_EVETPCC_EECR_E13_MAX (0x00000001U)
  3477. #define CSL_EVETPCC_EECR_RESETVAL (0x00000000U)
  3478. /* EECRH */
  3479. #define CSL_EVETPCC_EECRH_E62_MASK (0x40000000U)
  3480. #define CSL_EVETPCC_EECRH_E62_SHIFT (30U)
  3481. #define CSL_EVETPCC_EECRH_E62_RESETVAL (0x00000000U)
  3482. #define CSL_EVETPCC_EECRH_E62_MAX (0x00000001U)
  3483. #define CSL_EVETPCC_EECRH_E37_MASK (0x00000020U)
  3484. #define CSL_EVETPCC_EECRH_E37_SHIFT (5U)
  3485. #define CSL_EVETPCC_EECRH_E37_RESETVAL (0x00000000U)
  3486. #define CSL_EVETPCC_EECRH_E37_MAX (0x00000001U)
  3487. #define CSL_EVETPCC_EECRH_E51_MASK (0x00080000U)
  3488. #define CSL_EVETPCC_EECRH_E51_SHIFT (19U)
  3489. #define CSL_EVETPCC_EECRH_E51_RESETVAL (0x00000000U)
  3490. #define CSL_EVETPCC_EECRH_E51_MAX (0x00000001U)
  3491. #define CSL_EVETPCC_EECRH_E36_MASK (0x00000010U)
  3492. #define CSL_EVETPCC_EECRH_E36_SHIFT (4U)
  3493. #define CSL_EVETPCC_EECRH_E36_RESETVAL (0x00000000U)
  3494. #define CSL_EVETPCC_EECRH_E36_MAX (0x00000001U)
  3495. #define CSL_EVETPCC_EECRH_E50_MASK (0x00040000U)
  3496. #define CSL_EVETPCC_EECRH_E50_SHIFT (18U)
  3497. #define CSL_EVETPCC_EECRH_E50_RESETVAL (0x00000000U)
  3498. #define CSL_EVETPCC_EECRH_E50_MAX (0x00000001U)
  3499. #define CSL_EVETPCC_EECRH_E35_MASK (0x00000008U)
  3500. #define CSL_EVETPCC_EECRH_E35_SHIFT (3U)
  3501. #define CSL_EVETPCC_EECRH_E35_RESETVAL (0x00000000U)
  3502. #define CSL_EVETPCC_EECRH_E35_MAX (0x00000001U)
  3503. #define CSL_EVETPCC_EECRH_E63_MASK (0x80000000U)
  3504. #define CSL_EVETPCC_EECRH_E63_SHIFT (31U)
  3505. #define CSL_EVETPCC_EECRH_E63_RESETVAL (0x00000000U)
  3506. #define CSL_EVETPCC_EECRH_E63_MAX (0x00000001U)
  3507. #define CSL_EVETPCC_EECRH_E54_MASK (0x00400000U)
  3508. #define CSL_EVETPCC_EECRH_E54_SHIFT (22U)
  3509. #define CSL_EVETPCC_EECRH_E54_RESETVAL (0x00000000U)
  3510. #define CSL_EVETPCC_EECRH_E54_MAX (0x00000001U)
  3511. #define CSL_EVETPCC_EECRH_E58_MASK (0x04000000U)
  3512. #define CSL_EVETPCC_EECRH_E58_SHIFT (26U)
  3513. #define CSL_EVETPCC_EECRH_E58_RESETVAL (0x00000000U)
  3514. #define CSL_EVETPCC_EECRH_E58_MAX (0x00000001U)
  3515. #define CSL_EVETPCC_EECRH_E48_MASK (0x00010000U)
  3516. #define CSL_EVETPCC_EECRH_E48_SHIFT (16U)
  3517. #define CSL_EVETPCC_EECRH_E48_RESETVAL (0x00000000U)
  3518. #define CSL_EVETPCC_EECRH_E48_MAX (0x00000001U)
  3519. #define CSL_EVETPCC_EECRH_E59_MASK (0x08000000U)
  3520. #define CSL_EVETPCC_EECRH_E59_SHIFT (27U)
  3521. #define CSL_EVETPCC_EECRH_E59_RESETVAL (0x00000000U)
  3522. #define CSL_EVETPCC_EECRH_E59_MAX (0x00000001U)
  3523. #define CSL_EVETPCC_EECRH_E53_MASK (0x00200000U)
  3524. #define CSL_EVETPCC_EECRH_E53_SHIFT (21U)
  3525. #define CSL_EVETPCC_EECRH_E53_RESETVAL (0x00000000U)
  3526. #define CSL_EVETPCC_EECRH_E53_MAX (0x00000001U)
  3527. #define CSL_EVETPCC_EECRH_E49_MASK (0x00020000U)
  3528. #define CSL_EVETPCC_EECRH_E49_SHIFT (17U)
  3529. #define CSL_EVETPCC_EECRH_E49_RESETVAL (0x00000000U)
  3530. #define CSL_EVETPCC_EECRH_E49_MAX (0x00000001U)
  3531. #define CSL_EVETPCC_EECRH_E60_MASK (0x10000000U)
  3532. #define CSL_EVETPCC_EECRH_E60_SHIFT (28U)
  3533. #define CSL_EVETPCC_EECRH_E60_RESETVAL (0x00000000U)
  3534. #define CSL_EVETPCC_EECRH_E60_MAX (0x00000001U)
  3535. #define CSL_EVETPCC_EECRH_E61_MASK (0x20000000U)
  3536. #define CSL_EVETPCC_EECRH_E61_SHIFT (29U)
  3537. #define CSL_EVETPCC_EECRH_E61_RESETVAL (0x00000000U)
  3538. #define CSL_EVETPCC_EECRH_E61_MAX (0x00000001U)
  3539. #define CSL_EVETPCC_EECRH_E52_MASK (0x00100000U)
  3540. #define CSL_EVETPCC_EECRH_E52_SHIFT (20U)
  3541. #define CSL_EVETPCC_EECRH_E52_RESETVAL (0x00000000U)
  3542. #define CSL_EVETPCC_EECRH_E52_MAX (0x00000001U)
  3543. #define CSL_EVETPCC_EECRH_E44_MASK (0x00001000U)
  3544. #define CSL_EVETPCC_EECRH_E44_SHIFT (12U)
  3545. #define CSL_EVETPCC_EECRH_E44_RESETVAL (0x00000000U)
  3546. #define CSL_EVETPCC_EECRH_E44_MAX (0x00000001U)
  3547. #define CSL_EVETPCC_EECRH_E34_MASK (0x00000004U)
  3548. #define CSL_EVETPCC_EECRH_E34_SHIFT (2U)
  3549. #define CSL_EVETPCC_EECRH_E34_RESETVAL (0x00000000U)
  3550. #define CSL_EVETPCC_EECRH_E34_MAX (0x00000001U)
  3551. #define CSL_EVETPCC_EECRH_E43_MASK (0x00000800U)
  3552. #define CSL_EVETPCC_EECRH_E43_SHIFT (11U)
  3553. #define CSL_EVETPCC_EECRH_E43_RESETVAL (0x00000000U)
  3554. #define CSL_EVETPCC_EECRH_E43_MAX (0x00000001U)
  3555. #define CSL_EVETPCC_EECRH_E33_MASK (0x00000002U)
  3556. #define CSL_EVETPCC_EECRH_E33_SHIFT (1U)
  3557. #define CSL_EVETPCC_EECRH_E33_RESETVAL (0x00000000U)
  3558. #define CSL_EVETPCC_EECRH_E33_MAX (0x00000001U)
  3559. #define CSL_EVETPCC_EECRH_E55_MASK (0x00800000U)
  3560. #define CSL_EVETPCC_EECRH_E55_SHIFT (23U)
  3561. #define CSL_EVETPCC_EECRH_E55_RESETVAL (0x00000000U)
  3562. #define CSL_EVETPCC_EECRH_E55_MAX (0x00000001U)
  3563. #define CSL_EVETPCC_EECRH_E42_MASK (0x00000400U)
  3564. #define CSL_EVETPCC_EECRH_E42_SHIFT (10U)
  3565. #define CSL_EVETPCC_EECRH_E42_RESETVAL (0x00000000U)
  3566. #define CSL_EVETPCC_EECRH_E42_MAX (0x00000001U)
  3567. #define CSL_EVETPCC_EECRH_E56_MASK (0x01000000U)
  3568. #define CSL_EVETPCC_EECRH_E56_SHIFT (24U)
  3569. #define CSL_EVETPCC_EECRH_E56_RESETVAL (0x00000000U)
  3570. #define CSL_EVETPCC_EECRH_E56_MAX (0x00000001U)
  3571. #define CSL_EVETPCC_EECRH_E32_MASK (0x00000001U)
  3572. #define CSL_EVETPCC_EECRH_E32_SHIFT (0U)
  3573. #define CSL_EVETPCC_EECRH_E32_RESETVAL (0x00000000U)
  3574. #define CSL_EVETPCC_EECRH_E32_MAX (0x00000001U)
  3575. #define CSL_EVETPCC_EECRH_E41_MASK (0x00000200U)
  3576. #define CSL_EVETPCC_EECRH_E41_SHIFT (9U)
  3577. #define CSL_EVETPCC_EECRH_E41_RESETVAL (0x00000000U)
  3578. #define CSL_EVETPCC_EECRH_E41_MAX (0x00000001U)
  3579. #define CSL_EVETPCC_EECRH_E57_MASK (0x02000000U)
  3580. #define CSL_EVETPCC_EECRH_E57_SHIFT (25U)
  3581. #define CSL_EVETPCC_EECRH_E57_RESETVAL (0x00000000U)
  3582. #define CSL_EVETPCC_EECRH_E57_MAX (0x00000001U)
  3583. #define CSL_EVETPCC_EECRH_E47_MASK (0x00008000U)
  3584. #define CSL_EVETPCC_EECRH_E47_SHIFT (15U)
  3585. #define CSL_EVETPCC_EECRH_E47_RESETVAL (0x00000000U)
  3586. #define CSL_EVETPCC_EECRH_E47_MAX (0x00000001U)
  3587. #define CSL_EVETPCC_EECRH_E40_MASK (0x00000100U)
  3588. #define CSL_EVETPCC_EECRH_E40_SHIFT (8U)
  3589. #define CSL_EVETPCC_EECRH_E40_RESETVAL (0x00000000U)
  3590. #define CSL_EVETPCC_EECRH_E40_MAX (0x00000001U)
  3591. #define CSL_EVETPCC_EECRH_E46_MASK (0x00004000U)
  3592. #define CSL_EVETPCC_EECRH_E46_SHIFT (14U)
  3593. #define CSL_EVETPCC_EECRH_E46_RESETVAL (0x00000000U)
  3594. #define CSL_EVETPCC_EECRH_E46_MAX (0x00000001U)
  3595. #define CSL_EVETPCC_EECRH_E39_MASK (0x00000080U)
  3596. #define CSL_EVETPCC_EECRH_E39_SHIFT (7U)
  3597. #define CSL_EVETPCC_EECRH_E39_RESETVAL (0x00000000U)
  3598. #define CSL_EVETPCC_EECRH_E39_MAX (0x00000001U)
  3599. #define CSL_EVETPCC_EECRH_E45_MASK (0x00002000U)
  3600. #define CSL_EVETPCC_EECRH_E45_SHIFT (13U)
  3601. #define CSL_EVETPCC_EECRH_E45_RESETVAL (0x00000000U)
  3602. #define CSL_EVETPCC_EECRH_E45_MAX (0x00000001U)
  3603. #define CSL_EVETPCC_EECRH_E38_MASK (0x00000040U)
  3604. #define CSL_EVETPCC_EECRH_E38_SHIFT (6U)
  3605. #define CSL_EVETPCC_EECRH_E38_RESETVAL (0x00000000U)
  3606. #define CSL_EVETPCC_EECRH_E38_MAX (0x00000001U)
  3607. #define CSL_EVETPCC_EECRH_RESETVAL (0x00000000U)
  3608. /* EESR */
  3609. #define CSL_EVETPCC_EESR_E15_MASK (0x00008000U)
  3610. #define CSL_EVETPCC_EESR_E15_SHIFT (15U)
  3611. #define CSL_EVETPCC_EESR_E15_RESETVAL (0x00000000U)
  3612. #define CSL_EVETPCC_EESR_E15_MAX (0x00000001U)
  3613. #define CSL_EVETPCC_EESR_E6_MASK (0x00000040U)
  3614. #define CSL_EVETPCC_EESR_E6_SHIFT (6U)
  3615. #define CSL_EVETPCC_EESR_E6_RESETVAL (0x00000000U)
  3616. #define CSL_EVETPCC_EESR_E6_MAX (0x00000001U)
  3617. #define CSL_EVETPCC_EESR_E16_MASK (0x00010000U)
  3618. #define CSL_EVETPCC_EESR_E16_SHIFT (16U)
  3619. #define CSL_EVETPCC_EESR_E16_RESETVAL (0x00000000U)
  3620. #define CSL_EVETPCC_EESR_E16_MAX (0x00000001U)
  3621. #define CSL_EVETPCC_EESR_E30_MASK (0x40000000U)
  3622. #define CSL_EVETPCC_EESR_E30_SHIFT (30U)
  3623. #define CSL_EVETPCC_EESR_E30_RESETVAL (0x00000000U)
  3624. #define CSL_EVETPCC_EESR_E30_MAX (0x00000001U)
  3625. #define CSL_EVETPCC_EESR_E7_MASK (0x00000080U)
  3626. #define CSL_EVETPCC_EESR_E7_SHIFT (7U)
  3627. #define CSL_EVETPCC_EESR_E7_RESETVAL (0x00000000U)
  3628. #define CSL_EVETPCC_EESR_E7_MAX (0x00000001U)
  3629. #define CSL_EVETPCC_EESR_E4_MASK (0x00000010U)
  3630. #define CSL_EVETPCC_EESR_E4_SHIFT (4U)
  3631. #define CSL_EVETPCC_EESR_E4_RESETVAL (0x00000000U)
  3632. #define CSL_EVETPCC_EESR_E4_MAX (0x00000001U)
  3633. #define CSL_EVETPCC_EESR_E5_MASK (0x00000020U)
  3634. #define CSL_EVETPCC_EESR_E5_SHIFT (5U)
  3635. #define CSL_EVETPCC_EESR_E5_RESETVAL (0x00000000U)
  3636. #define CSL_EVETPCC_EESR_E5_MAX (0x00000001U)
  3637. #define CSL_EVETPCC_EESR_E29_MASK (0x20000000U)
  3638. #define CSL_EVETPCC_EESR_E29_SHIFT (29U)
  3639. #define CSL_EVETPCC_EESR_E29_RESETVAL (0x00000000U)
  3640. #define CSL_EVETPCC_EESR_E29_MAX (0x00000001U)
  3641. #define CSL_EVETPCC_EESR_E0_MASK (0x00000001U)
  3642. #define CSL_EVETPCC_EESR_E0_SHIFT (0U)
  3643. #define CSL_EVETPCC_EESR_E0_RESETVAL (0x00000000U)
  3644. #define CSL_EVETPCC_EESR_E0_MAX (0x00000001U)
  3645. #define CSL_EVETPCC_EESR_E10_MASK (0x00000400U)
  3646. #define CSL_EVETPCC_EESR_E10_SHIFT (10U)
  3647. #define CSL_EVETPCC_EESR_E10_RESETVAL (0x00000000U)
  3648. #define CSL_EVETPCC_EESR_E10_MAX (0x00000001U)
  3649. #define CSL_EVETPCC_EESR_E28_MASK (0x10000000U)
  3650. #define CSL_EVETPCC_EESR_E28_SHIFT (28U)
  3651. #define CSL_EVETPCC_EESR_E28_RESETVAL (0x00000000U)
  3652. #define CSL_EVETPCC_EESR_E28_MAX (0x00000001U)
  3653. #define CSL_EVETPCC_EESR_E27_MASK (0x08000000U)
  3654. #define CSL_EVETPCC_EESR_E27_SHIFT (27U)
  3655. #define CSL_EVETPCC_EESR_E27_RESETVAL (0x00000000U)
  3656. #define CSL_EVETPCC_EESR_E27_MAX (0x00000001U)
  3657. #define CSL_EVETPCC_EESR_E26_MASK (0x04000000U)
  3658. #define CSL_EVETPCC_EESR_E26_SHIFT (26U)
  3659. #define CSL_EVETPCC_EESR_E26_RESETVAL (0x00000000U)
  3660. #define CSL_EVETPCC_EESR_E26_MAX (0x00000001U)
  3661. #define CSL_EVETPCC_EESR_E8_MASK (0x00000100U)
  3662. #define CSL_EVETPCC_EESR_E8_SHIFT (8U)
  3663. #define CSL_EVETPCC_EESR_E8_RESETVAL (0x00000000U)
  3664. #define CSL_EVETPCC_EESR_E8_MAX (0x00000001U)
  3665. #define CSL_EVETPCC_EESR_E9_MASK (0x00000200U)
  3666. #define CSL_EVETPCC_EESR_E9_SHIFT (9U)
  3667. #define CSL_EVETPCC_EESR_E9_RESETVAL (0x00000000U)
  3668. #define CSL_EVETPCC_EESR_E9_MAX (0x00000001U)
  3669. #define CSL_EVETPCC_EESR_E25_MASK (0x02000000U)
  3670. #define CSL_EVETPCC_EESR_E25_SHIFT (25U)
  3671. #define CSL_EVETPCC_EESR_E25_RESETVAL (0x00000000U)
  3672. #define CSL_EVETPCC_EESR_E25_MAX (0x00000001U)
  3673. #define CSL_EVETPCC_EESR_E24_MASK (0x01000000U)
  3674. #define CSL_EVETPCC_EESR_E24_SHIFT (24U)
  3675. #define CSL_EVETPCC_EESR_E24_RESETVAL (0x00000000U)
  3676. #define CSL_EVETPCC_EESR_E24_MAX (0x00000001U)
  3677. #define CSL_EVETPCC_EESR_E11_MASK (0x00000800U)
  3678. #define CSL_EVETPCC_EESR_E11_SHIFT (11U)
  3679. #define CSL_EVETPCC_EESR_E11_RESETVAL (0x00000000U)
  3680. #define CSL_EVETPCC_EESR_E11_MAX (0x00000001U)
  3681. #define CSL_EVETPCC_EESR_E23_MASK (0x00800000U)
  3682. #define CSL_EVETPCC_EESR_E23_SHIFT (23U)
  3683. #define CSL_EVETPCC_EESR_E23_RESETVAL (0x00000000U)
  3684. #define CSL_EVETPCC_EESR_E23_MAX (0x00000001U)
  3685. #define CSL_EVETPCC_EESR_E20_MASK (0x00100000U)
  3686. #define CSL_EVETPCC_EESR_E20_SHIFT (20U)
  3687. #define CSL_EVETPCC_EESR_E20_RESETVAL (0x00000000U)
  3688. #define CSL_EVETPCC_EESR_E20_MAX (0x00000001U)
  3689. #define CSL_EVETPCC_EESR_E22_MASK (0x00400000U)
  3690. #define CSL_EVETPCC_EESR_E22_SHIFT (22U)
  3691. #define CSL_EVETPCC_EESR_E22_RESETVAL (0x00000000U)
  3692. #define CSL_EVETPCC_EESR_E22_MAX (0x00000001U)
  3693. #define CSL_EVETPCC_EESR_E21_MASK (0x00200000U)
  3694. #define CSL_EVETPCC_EESR_E21_SHIFT (21U)
  3695. #define CSL_EVETPCC_EESR_E21_RESETVAL (0x00000000U)
  3696. #define CSL_EVETPCC_EESR_E21_MAX (0x00000001U)
  3697. #define CSL_EVETPCC_EESR_E2_MASK (0x00000004U)
  3698. #define CSL_EVETPCC_EESR_E2_SHIFT (2U)
  3699. #define CSL_EVETPCC_EESR_E2_RESETVAL (0x00000000U)
  3700. #define CSL_EVETPCC_EESR_E2_MAX (0x00000001U)
  3701. #define CSL_EVETPCC_EESR_E18_MASK (0x00040000U)
  3702. #define CSL_EVETPCC_EESR_E18_SHIFT (18U)
  3703. #define CSL_EVETPCC_EESR_E18_RESETVAL (0x00000000U)
  3704. #define CSL_EVETPCC_EESR_E18_MAX (0x00000001U)
  3705. #define CSL_EVETPCC_EESR_E3_MASK (0x00000008U)
  3706. #define CSL_EVETPCC_EESR_E3_SHIFT (3U)
  3707. #define CSL_EVETPCC_EESR_E3_RESETVAL (0x00000000U)
  3708. #define CSL_EVETPCC_EESR_E3_MAX (0x00000001U)
  3709. #define CSL_EVETPCC_EESR_E19_MASK (0x00080000U)
  3710. #define CSL_EVETPCC_EESR_E19_SHIFT (19U)
  3711. #define CSL_EVETPCC_EESR_E19_RESETVAL (0x00000000U)
  3712. #define CSL_EVETPCC_EESR_E19_MAX (0x00000001U)
  3713. #define CSL_EVETPCC_EESR_E31_MASK (0x80000000U)
  3714. #define CSL_EVETPCC_EESR_E31_SHIFT (31U)
  3715. #define CSL_EVETPCC_EESR_E31_RESETVAL (0x00000000U)
  3716. #define CSL_EVETPCC_EESR_E31_MAX (0x00000001U)
  3717. #define CSL_EVETPCC_EESR_E13_MASK (0x00002000U)
  3718. #define CSL_EVETPCC_EESR_E13_SHIFT (13U)
  3719. #define CSL_EVETPCC_EESR_E13_RESETVAL (0x00000000U)
  3720. #define CSL_EVETPCC_EESR_E13_MAX (0x00000001U)
  3721. #define CSL_EVETPCC_EESR_E12_MASK (0x00001000U)
  3722. #define CSL_EVETPCC_EESR_E12_SHIFT (12U)
  3723. #define CSL_EVETPCC_EESR_E12_RESETVAL (0x00000000U)
  3724. #define CSL_EVETPCC_EESR_E12_MAX (0x00000001U)
  3725. #define CSL_EVETPCC_EESR_E14_MASK (0x00004000U)
  3726. #define CSL_EVETPCC_EESR_E14_SHIFT (14U)
  3727. #define CSL_EVETPCC_EESR_E14_RESETVAL (0x00000000U)
  3728. #define CSL_EVETPCC_EESR_E14_MAX (0x00000001U)
  3729. #define CSL_EVETPCC_EESR_E1_MASK (0x00000002U)
  3730. #define CSL_EVETPCC_EESR_E1_SHIFT (1U)
  3731. #define CSL_EVETPCC_EESR_E1_RESETVAL (0x00000000U)
  3732. #define CSL_EVETPCC_EESR_E1_MAX (0x00000001U)
  3733. #define CSL_EVETPCC_EESR_E17_MASK (0x00020000U)
  3734. #define CSL_EVETPCC_EESR_E17_SHIFT (17U)
  3735. #define CSL_EVETPCC_EESR_E17_RESETVAL (0x00000000U)
  3736. #define CSL_EVETPCC_EESR_E17_MAX (0x00000001U)
  3737. #define CSL_EVETPCC_EESR_RESETVAL (0x00000000U)
  3738. /* EESRH */
  3739. #define CSL_EVETPCC_EESRH_E33_MASK (0x00000002U)
  3740. #define CSL_EVETPCC_EESRH_E33_SHIFT (1U)
  3741. #define CSL_EVETPCC_EESRH_E33_RESETVAL (0x00000000U)
  3742. #define CSL_EVETPCC_EESRH_E33_MAX (0x00000001U)
  3743. #define CSL_EVETPCC_EESRH_E35_MASK (0x00000008U)
  3744. #define CSL_EVETPCC_EESRH_E35_SHIFT (3U)
  3745. #define CSL_EVETPCC_EESRH_E35_RESETVAL (0x00000000U)
  3746. #define CSL_EVETPCC_EESRH_E35_MAX (0x00000001U)
  3747. #define CSL_EVETPCC_EESRH_E44_MASK (0x00001000U)
  3748. #define CSL_EVETPCC_EESRH_E44_SHIFT (12U)
  3749. #define CSL_EVETPCC_EESRH_E44_RESETVAL (0x00000000U)
  3750. #define CSL_EVETPCC_EESRH_E44_MAX (0x00000001U)
  3751. #define CSL_EVETPCC_EESRH_E32_MASK (0x00000001U)
  3752. #define CSL_EVETPCC_EESRH_E32_SHIFT (0U)
  3753. #define CSL_EVETPCC_EESRH_E32_RESETVAL (0x00000000U)
  3754. #define CSL_EVETPCC_EESRH_E32_MAX (0x00000001U)
  3755. #define CSL_EVETPCC_EESRH_E43_MASK (0x00000800U)
  3756. #define CSL_EVETPCC_EESRH_E43_SHIFT (11U)
  3757. #define CSL_EVETPCC_EESRH_E43_RESETVAL (0x00000000U)
  3758. #define CSL_EVETPCC_EESRH_E43_MAX (0x00000001U)
  3759. #define CSL_EVETPCC_EESRH_E55_MASK (0x00800000U)
  3760. #define CSL_EVETPCC_EESRH_E55_SHIFT (23U)
  3761. #define CSL_EVETPCC_EESRH_E55_RESETVAL (0x00000000U)
  3762. #define CSL_EVETPCC_EESRH_E55_MAX (0x00000001U)
  3763. #define CSL_EVETPCC_EESRH_E42_MASK (0x00000400U)
  3764. #define CSL_EVETPCC_EESRH_E42_SHIFT (10U)
  3765. #define CSL_EVETPCC_EESRH_E42_RESETVAL (0x00000000U)
  3766. #define CSL_EVETPCC_EESRH_E42_MAX (0x00000001U)
  3767. #define CSL_EVETPCC_EESRH_E54_MASK (0x00400000U)
  3768. #define CSL_EVETPCC_EESRH_E54_SHIFT (22U)
  3769. #define CSL_EVETPCC_EESRH_E54_RESETVAL (0x00000000U)
  3770. #define CSL_EVETPCC_EESRH_E54_MAX (0x00000001U)
  3771. #define CSL_EVETPCC_EESRH_E53_MASK (0x00200000U)
  3772. #define CSL_EVETPCC_EESRH_E53_SHIFT (21U)
  3773. #define CSL_EVETPCC_EESRH_E53_RESETVAL (0x00000000U)
  3774. #define CSL_EVETPCC_EESRH_E53_MAX (0x00000001U)
  3775. #define CSL_EVETPCC_EESRH_E56_MASK (0x01000000U)
  3776. #define CSL_EVETPCC_EESRH_E56_SHIFT (24U)
  3777. #define CSL_EVETPCC_EESRH_E56_RESETVAL (0x00000000U)
  3778. #define CSL_EVETPCC_EESRH_E56_MAX (0x00000001U)
  3779. #define CSL_EVETPCC_EESRH_E41_MASK (0x00000200U)
  3780. #define CSL_EVETPCC_EESRH_E41_SHIFT (9U)
  3781. #define CSL_EVETPCC_EESRH_E41_RESETVAL (0x00000000U)
  3782. #define CSL_EVETPCC_EESRH_E41_MAX (0x00000001U)
  3783. #define CSL_EVETPCC_EESRH_E40_MASK (0x00000100U)
  3784. #define CSL_EVETPCC_EESRH_E40_SHIFT (8U)
  3785. #define CSL_EVETPCC_EESRH_E40_RESETVAL (0x00000000U)
  3786. #define CSL_EVETPCC_EESRH_E40_MAX (0x00000001U)
  3787. #define CSL_EVETPCC_EESRH_E57_MASK (0x02000000U)
  3788. #define CSL_EVETPCC_EESRH_E57_SHIFT (25U)
  3789. #define CSL_EVETPCC_EESRH_E57_RESETVAL (0x00000000U)
  3790. #define CSL_EVETPCC_EESRH_E57_MAX (0x00000001U)
  3791. #define CSL_EVETPCC_EESRH_E52_MASK (0x00100000U)
  3792. #define CSL_EVETPCC_EESRH_E52_SHIFT (20U)
  3793. #define CSL_EVETPCC_EESRH_E52_RESETVAL (0x00000000U)
  3794. #define CSL_EVETPCC_EESRH_E52_MAX (0x00000001U)
  3795. #define CSL_EVETPCC_EESRH_E34_MASK (0x00000004U)
  3796. #define CSL_EVETPCC_EESRH_E34_SHIFT (2U)
  3797. #define CSL_EVETPCC_EESRH_E34_RESETVAL (0x00000000U)
  3798. #define CSL_EVETPCC_EESRH_E34_MAX (0x00000001U)
  3799. #define CSL_EVETPCC_EESRH_E39_MASK (0x00000080U)
  3800. #define CSL_EVETPCC_EESRH_E39_SHIFT (7U)
  3801. #define CSL_EVETPCC_EESRH_E39_RESETVAL (0x00000000U)
  3802. #define CSL_EVETPCC_EESRH_E39_MAX (0x00000001U)
  3803. #define CSL_EVETPCC_EESRH_E58_MASK (0x04000000U)
  3804. #define CSL_EVETPCC_EESRH_E58_SHIFT (26U)
  3805. #define CSL_EVETPCC_EESRH_E58_RESETVAL (0x00000000U)
  3806. #define CSL_EVETPCC_EESRH_E58_MAX (0x00000001U)
  3807. #define CSL_EVETPCC_EESRH_E51_MASK (0x00080000U)
  3808. #define CSL_EVETPCC_EESRH_E51_SHIFT (19U)
  3809. #define CSL_EVETPCC_EESRH_E51_RESETVAL (0x00000000U)
  3810. #define CSL_EVETPCC_EESRH_E51_MAX (0x00000001U)
  3811. #define CSL_EVETPCC_EESRH_E36_MASK (0x00000010U)
  3812. #define CSL_EVETPCC_EESRH_E36_SHIFT (4U)
  3813. #define CSL_EVETPCC_EESRH_E36_RESETVAL (0x00000000U)
  3814. #define CSL_EVETPCC_EESRH_E36_MAX (0x00000001U)
  3815. #define CSL_EVETPCC_EESRH_E38_MASK (0x00000040U)
  3816. #define CSL_EVETPCC_EESRH_E38_SHIFT (6U)
  3817. #define CSL_EVETPCC_EESRH_E38_RESETVAL (0x00000000U)
  3818. #define CSL_EVETPCC_EESRH_E38_MAX (0x00000001U)
  3819. #define CSL_EVETPCC_EESRH_E59_MASK (0x08000000U)
  3820. #define CSL_EVETPCC_EESRH_E59_SHIFT (27U)
  3821. #define CSL_EVETPCC_EESRH_E59_RESETVAL (0x00000000U)
  3822. #define CSL_EVETPCC_EESRH_E59_MAX (0x00000001U)
  3823. #define CSL_EVETPCC_EESRH_E50_MASK (0x00040000U)
  3824. #define CSL_EVETPCC_EESRH_E50_SHIFT (18U)
  3825. #define CSL_EVETPCC_EESRH_E50_RESETVAL (0x00000000U)
  3826. #define CSL_EVETPCC_EESRH_E50_MAX (0x00000001U)
  3827. #define CSL_EVETPCC_EESRH_E37_MASK (0x00000020U)
  3828. #define CSL_EVETPCC_EESRH_E37_SHIFT (5U)
  3829. #define CSL_EVETPCC_EESRH_E37_RESETVAL (0x00000000U)
  3830. #define CSL_EVETPCC_EESRH_E37_MAX (0x00000001U)
  3831. #define CSL_EVETPCC_EESRH_E60_MASK (0x10000000U)
  3832. #define CSL_EVETPCC_EESRH_E60_SHIFT (28U)
  3833. #define CSL_EVETPCC_EESRH_E60_RESETVAL (0x00000000U)
  3834. #define CSL_EVETPCC_EESRH_E60_MAX (0x00000001U)
  3835. #define CSL_EVETPCC_EESRH_E49_MASK (0x00020000U)
  3836. #define CSL_EVETPCC_EESRH_E49_SHIFT (17U)
  3837. #define CSL_EVETPCC_EESRH_E49_RESETVAL (0x00000000U)
  3838. #define CSL_EVETPCC_EESRH_E49_MAX (0x00000001U)
  3839. #define CSL_EVETPCC_EESRH_E61_MASK (0x20000000U)
  3840. #define CSL_EVETPCC_EESRH_E61_SHIFT (29U)
  3841. #define CSL_EVETPCC_EESRH_E61_RESETVAL (0x00000000U)
  3842. #define CSL_EVETPCC_EESRH_E61_MAX (0x00000001U)
  3843. #define CSL_EVETPCC_EESRH_E48_MASK (0x00010000U)
  3844. #define CSL_EVETPCC_EESRH_E48_SHIFT (16U)
  3845. #define CSL_EVETPCC_EESRH_E48_RESETVAL (0x00000000U)
  3846. #define CSL_EVETPCC_EESRH_E48_MAX (0x00000001U)
  3847. #define CSL_EVETPCC_EESRH_E62_MASK (0x40000000U)
  3848. #define CSL_EVETPCC_EESRH_E62_SHIFT (30U)
  3849. #define CSL_EVETPCC_EESRH_E62_RESETVAL (0x00000000U)
  3850. #define CSL_EVETPCC_EESRH_E62_MAX (0x00000001U)
  3851. #define CSL_EVETPCC_EESRH_E47_MASK (0x00008000U)
  3852. #define CSL_EVETPCC_EESRH_E47_SHIFT (15U)
  3853. #define CSL_EVETPCC_EESRH_E47_RESETVAL (0x00000000U)
  3854. #define CSL_EVETPCC_EESRH_E47_MAX (0x00000001U)
  3855. #define CSL_EVETPCC_EESRH_E63_MASK (0x80000000U)
  3856. #define CSL_EVETPCC_EESRH_E63_SHIFT (31U)
  3857. #define CSL_EVETPCC_EESRH_E63_RESETVAL (0x00000000U)
  3858. #define CSL_EVETPCC_EESRH_E63_MAX (0x00000001U)
  3859. #define CSL_EVETPCC_EESRH_E46_MASK (0x00004000U)
  3860. #define CSL_EVETPCC_EESRH_E46_SHIFT (14U)
  3861. #define CSL_EVETPCC_EESRH_E46_RESETVAL (0x00000000U)
  3862. #define CSL_EVETPCC_EESRH_E46_MAX (0x00000001U)
  3863. #define CSL_EVETPCC_EESRH_E45_MASK (0x00002000U)
  3864. #define CSL_EVETPCC_EESRH_E45_SHIFT (13U)
  3865. #define CSL_EVETPCC_EESRH_E45_RESETVAL (0x00000000U)
  3866. #define CSL_EVETPCC_EESRH_E45_MAX (0x00000001U)
  3867. #define CSL_EVETPCC_EESRH_RESETVAL (0x00000000U)
  3868. /* SER */
  3869. #define CSL_EVETPCC_SER_E0_MASK (0x00000001U)
  3870. #define CSL_EVETPCC_SER_E0_SHIFT (0U)
  3871. #define CSL_EVETPCC_SER_E0_RESETVAL (0x00000000U)
  3872. #define CSL_EVETPCC_SER_E0_MAX (0x00000001U)
  3873. #define CSL_EVETPCC_SER_E13_MASK (0x00002000U)
  3874. #define CSL_EVETPCC_SER_E13_SHIFT (13U)
  3875. #define CSL_EVETPCC_SER_E13_RESETVAL (0x00000000U)
  3876. #define CSL_EVETPCC_SER_E13_MAX (0x00000001U)
  3877. #define CSL_EVETPCC_SER_E21_MASK (0x00200000U)
  3878. #define CSL_EVETPCC_SER_E21_SHIFT (21U)
  3879. #define CSL_EVETPCC_SER_E21_RESETVAL (0x00000000U)
  3880. #define CSL_EVETPCC_SER_E21_MAX (0x00000001U)
  3881. #define CSL_EVETPCC_SER_E14_MASK (0x00004000U)
  3882. #define CSL_EVETPCC_SER_E14_SHIFT (14U)
  3883. #define CSL_EVETPCC_SER_E14_RESETVAL (0x00000000U)
  3884. #define CSL_EVETPCC_SER_E14_MAX (0x00000001U)
  3885. #define CSL_EVETPCC_SER_E31_MASK (0x80000000U)
  3886. #define CSL_EVETPCC_SER_E31_SHIFT (31U)
  3887. #define CSL_EVETPCC_SER_E31_RESETVAL (0x00000000U)
  3888. #define CSL_EVETPCC_SER_E31_MAX (0x00000001U)
  3889. #define CSL_EVETPCC_SER_E1_MASK (0x00000002U)
  3890. #define CSL_EVETPCC_SER_E1_SHIFT (1U)
  3891. #define CSL_EVETPCC_SER_E1_RESETVAL (0x00000000U)
  3892. #define CSL_EVETPCC_SER_E1_MAX (0x00000001U)
  3893. #define CSL_EVETPCC_SER_E11_MASK (0x00000800U)
  3894. #define CSL_EVETPCC_SER_E11_SHIFT (11U)
  3895. #define CSL_EVETPCC_SER_E11_RESETVAL (0x00000000U)
  3896. #define CSL_EVETPCC_SER_E11_MAX (0x00000001U)
  3897. #define CSL_EVETPCC_SER_E19_MASK (0x00080000U)
  3898. #define CSL_EVETPCC_SER_E19_SHIFT (19U)
  3899. #define CSL_EVETPCC_SER_E19_RESETVAL (0x00000000U)
  3900. #define CSL_EVETPCC_SER_E19_MAX (0x00000001U)
  3901. #define CSL_EVETPCC_SER_E20_MASK (0x00100000U)
  3902. #define CSL_EVETPCC_SER_E20_SHIFT (20U)
  3903. #define CSL_EVETPCC_SER_E20_RESETVAL (0x00000000U)
  3904. #define CSL_EVETPCC_SER_E20_MAX (0x00000001U)
  3905. #define CSL_EVETPCC_SER_E12_MASK (0x00001000U)
  3906. #define CSL_EVETPCC_SER_E12_SHIFT (12U)
  3907. #define CSL_EVETPCC_SER_E12_RESETVAL (0x00000000U)
  3908. #define CSL_EVETPCC_SER_E12_MAX (0x00000001U)
  3909. #define CSL_EVETPCC_SER_E3_MASK (0x00000008U)
  3910. #define CSL_EVETPCC_SER_E3_SHIFT (3U)
  3911. #define CSL_EVETPCC_SER_E3_RESETVAL (0x00000000U)
  3912. #define CSL_EVETPCC_SER_E3_MAX (0x00000001U)
  3913. #define CSL_EVETPCC_SER_E4_MASK (0x00000010U)
  3914. #define CSL_EVETPCC_SER_E4_SHIFT (4U)
  3915. #define CSL_EVETPCC_SER_E4_RESETVAL (0x00000000U)
  3916. #define CSL_EVETPCC_SER_E4_MAX (0x00000001U)
  3917. #define CSL_EVETPCC_SER_E24_MASK (0x01000000U)
  3918. #define CSL_EVETPCC_SER_E24_SHIFT (24U)
  3919. #define CSL_EVETPCC_SER_E24_RESETVAL (0x00000000U)
  3920. #define CSL_EVETPCC_SER_E24_MAX (0x00000001U)
  3921. #define CSL_EVETPCC_SER_E2_MASK (0x00000004U)
  3922. #define CSL_EVETPCC_SER_E2_SHIFT (2U)
  3923. #define CSL_EVETPCC_SER_E2_RESETVAL (0x00000000U)
  3924. #define CSL_EVETPCC_SER_E2_MAX (0x00000001U)
  3925. #define CSL_EVETPCC_SER_E22_MASK (0x00400000U)
  3926. #define CSL_EVETPCC_SER_E22_SHIFT (22U)
  3927. #define CSL_EVETPCC_SER_E22_RESETVAL (0x00000000U)
  3928. #define CSL_EVETPCC_SER_E22_MAX (0x00000001U)
  3929. #define CSL_EVETPCC_SER_E23_MASK (0x00800000U)
  3930. #define CSL_EVETPCC_SER_E23_SHIFT (23U)
  3931. #define CSL_EVETPCC_SER_E23_RESETVAL (0x00000000U)
  3932. #define CSL_EVETPCC_SER_E23_MAX (0x00000001U)
  3933. #define CSL_EVETPCC_SER_E25_MASK (0x02000000U)
  3934. #define CSL_EVETPCC_SER_E25_SHIFT (25U)
  3935. #define CSL_EVETPCC_SER_E25_RESETVAL (0x00000000U)
  3936. #define CSL_EVETPCC_SER_E25_MAX (0x00000001U)
  3937. #define CSL_EVETPCC_SER_E26_MASK (0x04000000U)
  3938. #define CSL_EVETPCC_SER_E26_SHIFT (26U)
  3939. #define CSL_EVETPCC_SER_E26_RESETVAL (0x00000000U)
  3940. #define CSL_EVETPCC_SER_E26_MAX (0x00000001U)
  3941. #define CSL_EVETPCC_SER_E6_MASK (0x00000040U)
  3942. #define CSL_EVETPCC_SER_E6_SHIFT (6U)
  3943. #define CSL_EVETPCC_SER_E6_RESETVAL (0x00000000U)
  3944. #define CSL_EVETPCC_SER_E6_MAX (0x00000001U)
  3945. #define CSL_EVETPCC_SER_E5_MASK (0x00000020U)
  3946. #define CSL_EVETPCC_SER_E5_SHIFT (5U)
  3947. #define CSL_EVETPCC_SER_E5_RESETVAL (0x00000000U)
  3948. #define CSL_EVETPCC_SER_E5_MAX (0x00000001U)
  3949. #define CSL_EVETPCC_SER_E8_MASK (0x00000100U)
  3950. #define CSL_EVETPCC_SER_E8_SHIFT (8U)
  3951. #define CSL_EVETPCC_SER_E8_RESETVAL (0x00000000U)
  3952. #define CSL_EVETPCC_SER_E8_MAX (0x00000001U)
  3953. #define CSL_EVETPCC_SER_E17_MASK (0x00020000U)
  3954. #define CSL_EVETPCC_SER_E17_SHIFT (17U)
  3955. #define CSL_EVETPCC_SER_E17_RESETVAL (0x00000000U)
  3956. #define CSL_EVETPCC_SER_E17_MAX (0x00000001U)
  3957. #define CSL_EVETPCC_SER_E29_MASK (0x20000000U)
  3958. #define CSL_EVETPCC_SER_E29_SHIFT (29U)
  3959. #define CSL_EVETPCC_SER_E29_RESETVAL (0x00000000U)
  3960. #define CSL_EVETPCC_SER_E29_MAX (0x00000001U)
  3961. #define CSL_EVETPCC_SER_E18_MASK (0x00040000U)
  3962. #define CSL_EVETPCC_SER_E18_SHIFT (18U)
  3963. #define CSL_EVETPCC_SER_E18_RESETVAL (0x00000000U)
  3964. #define CSL_EVETPCC_SER_E18_MAX (0x00000001U)
  3965. #define CSL_EVETPCC_SER_E30_MASK (0x40000000U)
  3966. #define CSL_EVETPCC_SER_E30_SHIFT (30U)
  3967. #define CSL_EVETPCC_SER_E30_RESETVAL (0x00000000U)
  3968. #define CSL_EVETPCC_SER_E30_MAX (0x00000001U)
  3969. #define CSL_EVETPCC_SER_E7_MASK (0x00000080U)
  3970. #define CSL_EVETPCC_SER_E7_SHIFT (7U)
  3971. #define CSL_EVETPCC_SER_E7_RESETVAL (0x00000000U)
  3972. #define CSL_EVETPCC_SER_E7_MAX (0x00000001U)
  3973. #define CSL_EVETPCC_SER_E10_MASK (0x00000400U)
  3974. #define CSL_EVETPCC_SER_E10_SHIFT (10U)
  3975. #define CSL_EVETPCC_SER_E10_RESETVAL (0x00000000U)
  3976. #define CSL_EVETPCC_SER_E10_MAX (0x00000001U)
  3977. #define CSL_EVETPCC_SER_E15_MASK (0x00008000U)
  3978. #define CSL_EVETPCC_SER_E15_SHIFT (15U)
  3979. #define CSL_EVETPCC_SER_E15_RESETVAL (0x00000000U)
  3980. #define CSL_EVETPCC_SER_E15_MAX (0x00000001U)
  3981. #define CSL_EVETPCC_SER_E27_MASK (0x08000000U)
  3982. #define CSL_EVETPCC_SER_E27_SHIFT (27U)
  3983. #define CSL_EVETPCC_SER_E27_RESETVAL (0x00000000U)
  3984. #define CSL_EVETPCC_SER_E27_MAX (0x00000001U)
  3985. #define CSL_EVETPCC_SER_E9_MASK (0x00000200U)
  3986. #define CSL_EVETPCC_SER_E9_SHIFT (9U)
  3987. #define CSL_EVETPCC_SER_E9_RESETVAL (0x00000000U)
  3988. #define CSL_EVETPCC_SER_E9_MAX (0x00000001U)
  3989. #define CSL_EVETPCC_SER_E16_MASK (0x00010000U)
  3990. #define CSL_EVETPCC_SER_E16_SHIFT (16U)
  3991. #define CSL_EVETPCC_SER_E16_RESETVAL (0x00000000U)
  3992. #define CSL_EVETPCC_SER_E16_MAX (0x00000001U)
  3993. #define CSL_EVETPCC_SER_E28_MASK (0x10000000U)
  3994. #define CSL_EVETPCC_SER_E28_SHIFT (28U)
  3995. #define CSL_EVETPCC_SER_E28_RESETVAL (0x00000000U)
  3996. #define CSL_EVETPCC_SER_E28_MAX (0x00000001U)
  3997. #define CSL_EVETPCC_SER_RESETVAL (0x00000000U)
  3998. /* SERH */
  3999. #define CSL_EVETPCC_SERH_E53_MASK (0x00200000U)
  4000. #define CSL_EVETPCC_SERH_E53_SHIFT (21U)
  4001. #define CSL_EVETPCC_SERH_E53_RESETVAL (0x00000000U)
  4002. #define CSL_EVETPCC_SERH_E53_MAX (0x00000001U)
  4003. #define CSL_EVETPCC_SERH_E42_MASK (0x00000400U)
  4004. #define CSL_EVETPCC_SERH_E42_SHIFT (10U)
  4005. #define CSL_EVETPCC_SERH_E42_RESETVAL (0x00000000U)
  4006. #define CSL_EVETPCC_SERH_E42_MAX (0x00000001U)
  4007. #define CSL_EVETPCC_SERH_E52_MASK (0x00100000U)
  4008. #define CSL_EVETPCC_SERH_E52_SHIFT (20U)
  4009. #define CSL_EVETPCC_SERH_E52_RESETVAL (0x00000000U)
  4010. #define CSL_EVETPCC_SERH_E52_MAX (0x00000001U)
  4011. #define CSL_EVETPCC_SERH_E43_MASK (0x00000800U)
  4012. #define CSL_EVETPCC_SERH_E43_SHIFT (11U)
  4013. #define CSL_EVETPCC_SERH_E43_RESETVAL (0x00000000U)
  4014. #define CSL_EVETPCC_SERH_E43_MAX (0x00000001U)
  4015. #define CSL_EVETPCC_SERH_E32_MASK (0x00000001U)
  4016. #define CSL_EVETPCC_SERH_E32_SHIFT (0U)
  4017. #define CSL_EVETPCC_SERH_E32_RESETVAL (0x00000000U)
  4018. #define CSL_EVETPCC_SERH_E32_MAX (0x00000001U)
  4019. #define CSL_EVETPCC_SERH_E44_MASK (0x00001000U)
  4020. #define CSL_EVETPCC_SERH_E44_SHIFT (12U)
  4021. #define CSL_EVETPCC_SERH_E44_RESETVAL (0x00000000U)
  4022. #define CSL_EVETPCC_SERH_E44_MAX (0x00000001U)
  4023. #define CSL_EVETPCC_SERH_E55_MASK (0x00800000U)
  4024. #define CSL_EVETPCC_SERH_E55_SHIFT (23U)
  4025. #define CSL_EVETPCC_SERH_E55_RESETVAL (0x00000000U)
  4026. #define CSL_EVETPCC_SERH_E55_MAX (0x00000001U)
  4027. #define CSL_EVETPCC_SERH_E45_MASK (0x00002000U)
  4028. #define CSL_EVETPCC_SERH_E45_SHIFT (13U)
  4029. #define CSL_EVETPCC_SERH_E45_RESETVAL (0x00000000U)
  4030. #define CSL_EVETPCC_SERH_E45_MAX (0x00000001U)
  4031. #define CSL_EVETPCC_SERH_E54_MASK (0x00400000U)
  4032. #define CSL_EVETPCC_SERH_E54_SHIFT (22U)
  4033. #define CSL_EVETPCC_SERH_E54_RESETVAL (0x00000000U)
  4034. #define CSL_EVETPCC_SERH_E54_MAX (0x00000001U)
  4035. #define CSL_EVETPCC_SERH_E46_MASK (0x00004000U)
  4036. #define CSL_EVETPCC_SERH_E46_SHIFT (14U)
  4037. #define CSL_EVETPCC_SERH_E46_RESETVAL (0x00000000U)
  4038. #define CSL_EVETPCC_SERH_E46_MAX (0x00000001U)
  4039. #define CSL_EVETPCC_SERH_E56_MASK (0x01000000U)
  4040. #define CSL_EVETPCC_SERH_E56_SHIFT (24U)
  4041. #define CSL_EVETPCC_SERH_E56_RESETVAL (0x00000000U)
  4042. #define CSL_EVETPCC_SERH_E56_MAX (0x00000001U)
  4043. #define CSL_EVETPCC_SERH_E58_MASK (0x04000000U)
  4044. #define CSL_EVETPCC_SERH_E58_SHIFT (26U)
  4045. #define CSL_EVETPCC_SERH_E58_RESETVAL (0x00000000U)
  4046. #define CSL_EVETPCC_SERH_E58_MAX (0x00000001U)
  4047. #define CSL_EVETPCC_SERH_E57_MASK (0x02000000U)
  4048. #define CSL_EVETPCC_SERH_E57_SHIFT (25U)
  4049. #define CSL_EVETPCC_SERH_E57_RESETVAL (0x00000000U)
  4050. #define CSL_EVETPCC_SERH_E57_MAX (0x00000001U)
  4051. #define CSL_EVETPCC_SERH_E60_MASK (0x10000000U)
  4052. #define CSL_EVETPCC_SERH_E60_SHIFT (28U)
  4053. #define CSL_EVETPCC_SERH_E60_RESETVAL (0x00000000U)
  4054. #define CSL_EVETPCC_SERH_E60_MAX (0x00000001U)
  4055. #define CSL_EVETPCC_SERH_E59_MASK (0x08000000U)
  4056. #define CSL_EVETPCC_SERH_E59_SHIFT (27U)
  4057. #define CSL_EVETPCC_SERH_E59_RESETVAL (0x00000000U)
  4058. #define CSL_EVETPCC_SERH_E59_MAX (0x00000001U)
  4059. #define CSL_EVETPCC_SERH_E61_MASK (0x20000000U)
  4060. #define CSL_EVETPCC_SERH_E61_SHIFT (29U)
  4061. #define CSL_EVETPCC_SERH_E61_RESETVAL (0x00000000U)
  4062. #define CSL_EVETPCC_SERH_E61_MAX (0x00000001U)
  4063. #define CSL_EVETPCC_SERH_E37_MASK (0x00000020U)
  4064. #define CSL_EVETPCC_SERH_E37_SHIFT (5U)
  4065. #define CSL_EVETPCC_SERH_E37_RESETVAL (0x00000000U)
  4066. #define CSL_EVETPCC_SERH_E37_MAX (0x00000001U)
  4067. #define CSL_EVETPCC_SERH_E47_MASK (0x00008000U)
  4068. #define CSL_EVETPCC_SERH_E47_SHIFT (15U)
  4069. #define CSL_EVETPCC_SERH_E47_RESETVAL (0x00000000U)
  4070. #define CSL_EVETPCC_SERH_E47_MAX (0x00000001U)
  4071. #define CSL_EVETPCC_SERH_E38_MASK (0x00000040U)
  4072. #define CSL_EVETPCC_SERH_E38_SHIFT (6U)
  4073. #define CSL_EVETPCC_SERH_E38_RESETVAL (0x00000000U)
  4074. #define CSL_EVETPCC_SERH_E38_MAX (0x00000001U)
  4075. #define CSL_EVETPCC_SERH_E35_MASK (0x00000008U)
  4076. #define CSL_EVETPCC_SERH_E35_SHIFT (3U)
  4077. #define CSL_EVETPCC_SERH_E35_RESETVAL (0x00000000U)
  4078. #define CSL_EVETPCC_SERH_E35_MAX (0x00000001U)
  4079. #define CSL_EVETPCC_SERH_E48_MASK (0x00010000U)
  4080. #define CSL_EVETPCC_SERH_E48_SHIFT (16U)
  4081. #define CSL_EVETPCC_SERH_E48_RESETVAL (0x00000000U)
  4082. #define CSL_EVETPCC_SERH_E48_MAX (0x00000001U)
  4083. #define CSL_EVETPCC_SERH_E62_MASK (0x40000000U)
  4084. #define CSL_EVETPCC_SERH_E62_SHIFT (30U)
  4085. #define CSL_EVETPCC_SERH_E62_RESETVAL (0x00000000U)
  4086. #define CSL_EVETPCC_SERH_E62_MAX (0x00000001U)
  4087. #define CSL_EVETPCC_SERH_E39_MASK (0x00000080U)
  4088. #define CSL_EVETPCC_SERH_E39_SHIFT (7U)
  4089. #define CSL_EVETPCC_SERH_E39_RESETVAL (0x00000000U)
  4090. #define CSL_EVETPCC_SERH_E39_MAX (0x00000001U)
  4091. #define CSL_EVETPCC_SERH_E63_MASK (0x80000000U)
  4092. #define CSL_EVETPCC_SERH_E63_SHIFT (31U)
  4093. #define CSL_EVETPCC_SERH_E63_RESETVAL (0x00000000U)
  4094. #define CSL_EVETPCC_SERH_E63_MAX (0x00000001U)
  4095. #define CSL_EVETPCC_SERH_E36_MASK (0x00000010U)
  4096. #define CSL_EVETPCC_SERH_E36_SHIFT (4U)
  4097. #define CSL_EVETPCC_SERH_E36_RESETVAL (0x00000000U)
  4098. #define CSL_EVETPCC_SERH_E36_MAX (0x00000001U)
  4099. #define CSL_EVETPCC_SERH_E49_MASK (0x00020000U)
  4100. #define CSL_EVETPCC_SERH_E49_SHIFT (17U)
  4101. #define CSL_EVETPCC_SERH_E49_RESETVAL (0x00000000U)
  4102. #define CSL_EVETPCC_SERH_E49_MAX (0x00000001U)
  4103. #define CSL_EVETPCC_SERH_E40_MASK (0x00000100U)
  4104. #define CSL_EVETPCC_SERH_E40_SHIFT (8U)
  4105. #define CSL_EVETPCC_SERH_E40_RESETVAL (0x00000000U)
  4106. #define CSL_EVETPCC_SERH_E40_MAX (0x00000001U)
  4107. #define CSL_EVETPCC_SERH_E33_MASK (0x00000002U)
  4108. #define CSL_EVETPCC_SERH_E33_SHIFT (1U)
  4109. #define CSL_EVETPCC_SERH_E33_RESETVAL (0x00000000U)
  4110. #define CSL_EVETPCC_SERH_E33_MAX (0x00000001U)
  4111. #define CSL_EVETPCC_SERH_E50_MASK (0x00040000U)
  4112. #define CSL_EVETPCC_SERH_E50_SHIFT (18U)
  4113. #define CSL_EVETPCC_SERH_E50_RESETVAL (0x00000000U)
  4114. #define CSL_EVETPCC_SERH_E50_MAX (0x00000001U)
  4115. #define CSL_EVETPCC_SERH_E41_MASK (0x00000200U)
  4116. #define CSL_EVETPCC_SERH_E41_SHIFT (9U)
  4117. #define CSL_EVETPCC_SERH_E41_RESETVAL (0x00000000U)
  4118. #define CSL_EVETPCC_SERH_E41_MAX (0x00000001U)
  4119. #define CSL_EVETPCC_SERH_E34_MASK (0x00000004U)
  4120. #define CSL_EVETPCC_SERH_E34_SHIFT (2U)
  4121. #define CSL_EVETPCC_SERH_E34_RESETVAL (0x00000000U)
  4122. #define CSL_EVETPCC_SERH_E34_MAX (0x00000001U)
  4123. #define CSL_EVETPCC_SERH_E51_MASK (0x00080000U)
  4124. #define CSL_EVETPCC_SERH_E51_SHIFT (19U)
  4125. #define CSL_EVETPCC_SERH_E51_RESETVAL (0x00000000U)
  4126. #define CSL_EVETPCC_SERH_E51_MAX (0x00000001U)
  4127. #define CSL_EVETPCC_SERH_RESETVAL (0x00000000U)
  4128. /* SECR */
  4129. #define CSL_EVETPCC_SECR_E21_MASK (0x00200000U)
  4130. #define CSL_EVETPCC_SECR_E21_SHIFT (21U)
  4131. #define CSL_EVETPCC_SECR_E21_RESETVAL (0x00000000U)
  4132. #define CSL_EVETPCC_SECR_E21_MAX (0x00000001U)
  4133. #define CSL_EVETPCC_SECR_E29_MASK (0x20000000U)
  4134. #define CSL_EVETPCC_SECR_E29_SHIFT (29U)
  4135. #define CSL_EVETPCC_SECR_E29_RESETVAL (0x00000000U)
  4136. #define CSL_EVETPCC_SECR_E29_MAX (0x00000001U)
  4137. #define CSL_EVETPCC_SECR_E20_MASK (0x00100000U)
  4138. #define CSL_EVETPCC_SECR_E20_SHIFT (20U)
  4139. #define CSL_EVETPCC_SECR_E20_RESETVAL (0x00000000U)
  4140. #define CSL_EVETPCC_SECR_E20_MAX (0x00000001U)
  4141. #define CSL_EVETPCC_SECR_E0_MASK (0x00000001U)
  4142. #define CSL_EVETPCC_SECR_E0_SHIFT (0U)
  4143. #define CSL_EVETPCC_SECR_E0_RESETVAL (0x00000000U)
  4144. #define CSL_EVETPCC_SECR_E0_MAX (0x00000001U)
  4145. #define CSL_EVETPCC_SECR_E10_MASK (0x00000400U)
  4146. #define CSL_EVETPCC_SECR_E10_SHIFT (10U)
  4147. #define CSL_EVETPCC_SECR_E10_RESETVAL (0x00000000U)
  4148. #define CSL_EVETPCC_SECR_E10_MAX (0x00000001U)
  4149. #define CSL_EVETPCC_SECR_E9_MASK (0x00000200U)
  4150. #define CSL_EVETPCC_SECR_E9_SHIFT (9U)
  4151. #define CSL_EVETPCC_SECR_E9_RESETVAL (0x00000000U)
  4152. #define CSL_EVETPCC_SECR_E9_MAX (0x00000001U)
  4153. #define CSL_EVETPCC_SECR_E27_MASK (0x08000000U)
  4154. #define CSL_EVETPCC_SECR_E27_SHIFT (27U)
  4155. #define CSL_EVETPCC_SECR_E27_RESETVAL (0x00000000U)
  4156. #define CSL_EVETPCC_SECR_E27_MAX (0x00000001U)
  4157. #define CSL_EVETPCC_SECR_E2_MASK (0x00000004U)
  4158. #define CSL_EVETPCC_SECR_E2_SHIFT (2U)
  4159. #define CSL_EVETPCC_SECR_E2_RESETVAL (0x00000000U)
  4160. #define CSL_EVETPCC_SECR_E2_MAX (0x00000001U)
  4161. #define CSL_EVETPCC_SECR_E12_MASK (0x00001000U)
  4162. #define CSL_EVETPCC_SECR_E12_SHIFT (12U)
  4163. #define CSL_EVETPCC_SECR_E12_RESETVAL (0x00000000U)
  4164. #define CSL_EVETPCC_SECR_E12_MAX (0x00000001U)
  4165. #define CSL_EVETPCC_SECR_E28_MASK (0x10000000U)
  4166. #define CSL_EVETPCC_SECR_E28_SHIFT (28U)
  4167. #define CSL_EVETPCC_SECR_E28_RESETVAL (0x00000000U)
  4168. #define CSL_EVETPCC_SECR_E28_MAX (0x00000001U)
  4169. #define CSL_EVETPCC_SECR_E1_MASK (0x00000002U)
  4170. #define CSL_EVETPCC_SECR_E1_SHIFT (1U)
  4171. #define CSL_EVETPCC_SECR_E1_RESETVAL (0x00000000U)
  4172. #define CSL_EVETPCC_SECR_E1_MAX (0x00000001U)
  4173. #define CSL_EVETPCC_SECR_E11_MASK (0x00000800U)
  4174. #define CSL_EVETPCC_SECR_E11_SHIFT (11U)
  4175. #define CSL_EVETPCC_SECR_E11_RESETVAL (0x00000000U)
  4176. #define CSL_EVETPCC_SECR_E11_MAX (0x00000001U)
  4177. #define CSL_EVETPCC_SECR_E25_MASK (0x02000000U)
  4178. #define CSL_EVETPCC_SECR_E25_SHIFT (25U)
  4179. #define CSL_EVETPCC_SECR_E25_RESETVAL (0x00000000U)
  4180. #define CSL_EVETPCC_SECR_E25_MAX (0x00000001U)
  4181. #define CSL_EVETPCC_SECR_E4_MASK (0x00000010U)
  4182. #define CSL_EVETPCC_SECR_E4_SHIFT (4U)
  4183. #define CSL_EVETPCC_SECR_E4_RESETVAL (0x00000000U)
  4184. #define CSL_EVETPCC_SECR_E4_MAX (0x00000001U)
  4185. #define CSL_EVETPCC_SECR_E14_MASK (0x00004000U)
  4186. #define CSL_EVETPCC_SECR_E14_SHIFT (14U)
  4187. #define CSL_EVETPCC_SECR_E14_RESETVAL (0x00000000U)
  4188. #define CSL_EVETPCC_SECR_E14_MAX (0x00000001U)
  4189. #define CSL_EVETPCC_SECR_E26_MASK (0x04000000U)
  4190. #define CSL_EVETPCC_SECR_E26_SHIFT (26U)
  4191. #define CSL_EVETPCC_SECR_E26_RESETVAL (0x00000000U)
  4192. #define CSL_EVETPCC_SECR_E26_MAX (0x00000001U)
  4193. #define CSL_EVETPCC_SECR_E3_MASK (0x00000008U)
  4194. #define CSL_EVETPCC_SECR_E3_SHIFT (3U)
  4195. #define CSL_EVETPCC_SECR_E3_RESETVAL (0x00000000U)
  4196. #define CSL_EVETPCC_SECR_E3_MAX (0x00000001U)
  4197. #define CSL_EVETPCC_SECR_E13_MASK (0x00002000U)
  4198. #define CSL_EVETPCC_SECR_E13_SHIFT (13U)
  4199. #define CSL_EVETPCC_SECR_E13_RESETVAL (0x00000000U)
  4200. #define CSL_EVETPCC_SECR_E13_MAX (0x00000001U)
  4201. #define CSL_EVETPCC_SECR_E6_MASK (0x00000040U)
  4202. #define CSL_EVETPCC_SECR_E6_SHIFT (6U)
  4203. #define CSL_EVETPCC_SECR_E6_RESETVAL (0x00000000U)
  4204. #define CSL_EVETPCC_SECR_E6_MAX (0x00000001U)
  4205. #define CSL_EVETPCC_SECR_E16_MASK (0x00010000U)
  4206. #define CSL_EVETPCC_SECR_E16_SHIFT (16U)
  4207. #define CSL_EVETPCC_SECR_E16_RESETVAL (0x00000000U)
  4208. #define CSL_EVETPCC_SECR_E16_MAX (0x00000001U)
  4209. #define CSL_EVETPCC_SECR_E24_MASK (0x01000000U)
  4210. #define CSL_EVETPCC_SECR_E24_SHIFT (24U)
  4211. #define CSL_EVETPCC_SECR_E24_RESETVAL (0x00000000U)
  4212. #define CSL_EVETPCC_SECR_E24_MAX (0x00000001U)
  4213. #define CSL_EVETPCC_SECR_E5_MASK (0x00000020U)
  4214. #define CSL_EVETPCC_SECR_E5_SHIFT (5U)
  4215. #define CSL_EVETPCC_SECR_E5_RESETVAL (0x00000000U)
  4216. #define CSL_EVETPCC_SECR_E5_MAX (0x00000001U)
  4217. #define CSL_EVETPCC_SECR_E15_MASK (0x00008000U)
  4218. #define CSL_EVETPCC_SECR_E15_SHIFT (15U)
  4219. #define CSL_EVETPCC_SECR_E15_RESETVAL (0x00000000U)
  4220. #define CSL_EVETPCC_SECR_E15_MAX (0x00000001U)
  4221. #define CSL_EVETPCC_SECR_E18_MASK (0x00040000U)
  4222. #define CSL_EVETPCC_SECR_E18_SHIFT (18U)
  4223. #define CSL_EVETPCC_SECR_E18_RESETVAL (0x00000000U)
  4224. #define CSL_EVETPCC_SECR_E18_MAX (0x00000001U)
  4225. #define CSL_EVETPCC_SECR_E31_MASK (0x80000000U)
  4226. #define CSL_EVETPCC_SECR_E31_SHIFT (31U)
  4227. #define CSL_EVETPCC_SECR_E31_RESETVAL (0x00000000U)
  4228. #define CSL_EVETPCC_SECR_E31_MAX (0x00000001U)
  4229. #define CSL_EVETPCC_SECR_E8_MASK (0x00000100U)
  4230. #define CSL_EVETPCC_SECR_E8_SHIFT (8U)
  4231. #define CSL_EVETPCC_SECR_E8_RESETVAL (0x00000000U)
  4232. #define CSL_EVETPCC_SECR_E8_MAX (0x00000001U)
  4233. #define CSL_EVETPCC_SECR_E22_MASK (0x00400000U)
  4234. #define CSL_EVETPCC_SECR_E22_SHIFT (22U)
  4235. #define CSL_EVETPCC_SECR_E22_RESETVAL (0x00000000U)
  4236. #define CSL_EVETPCC_SECR_E22_MAX (0x00000001U)
  4237. #define CSL_EVETPCC_SECR_E7_MASK (0x00000080U)
  4238. #define CSL_EVETPCC_SECR_E7_SHIFT (7U)
  4239. #define CSL_EVETPCC_SECR_E7_RESETVAL (0x00000000U)
  4240. #define CSL_EVETPCC_SECR_E7_MAX (0x00000001U)
  4241. #define CSL_EVETPCC_SECR_E19_MASK (0x00080000U)
  4242. #define CSL_EVETPCC_SECR_E19_SHIFT (19U)
  4243. #define CSL_EVETPCC_SECR_E19_RESETVAL (0x00000000U)
  4244. #define CSL_EVETPCC_SECR_E19_MAX (0x00000001U)
  4245. #define CSL_EVETPCC_SECR_E17_MASK (0x00020000U)
  4246. #define CSL_EVETPCC_SECR_E17_SHIFT (17U)
  4247. #define CSL_EVETPCC_SECR_E17_RESETVAL (0x00000000U)
  4248. #define CSL_EVETPCC_SECR_E17_MAX (0x00000001U)
  4249. #define CSL_EVETPCC_SECR_E23_MASK (0x00800000U)
  4250. #define CSL_EVETPCC_SECR_E23_SHIFT (23U)
  4251. #define CSL_EVETPCC_SECR_E23_RESETVAL (0x00000000U)
  4252. #define CSL_EVETPCC_SECR_E23_MAX (0x00000001U)
  4253. #define CSL_EVETPCC_SECR_E30_MASK (0x40000000U)
  4254. #define CSL_EVETPCC_SECR_E30_SHIFT (30U)
  4255. #define CSL_EVETPCC_SECR_E30_RESETVAL (0x00000000U)
  4256. #define CSL_EVETPCC_SECR_E30_MAX (0x00000001U)
  4257. #define CSL_EVETPCC_SECR_RESETVAL (0x00000000U)
  4258. /* SECRH */
  4259. #define CSL_EVETPCC_SECRH_E34_MASK (0x00000004U)
  4260. #define CSL_EVETPCC_SECRH_E34_SHIFT (2U)
  4261. #define CSL_EVETPCC_SECRH_E34_RESETVAL (0x00000000U)
  4262. #define CSL_EVETPCC_SECRH_E34_MAX (0x00000001U)
  4263. #define CSL_EVETPCC_SECRH_E44_MASK (0x00001000U)
  4264. #define CSL_EVETPCC_SECRH_E44_SHIFT (12U)
  4265. #define CSL_EVETPCC_SECRH_E44_RESETVAL (0x00000000U)
  4266. #define CSL_EVETPCC_SECRH_E44_MAX (0x00000001U)
  4267. #define CSL_EVETPCC_SECRH_E54_MASK (0x00400000U)
  4268. #define CSL_EVETPCC_SECRH_E54_SHIFT (22U)
  4269. #define CSL_EVETPCC_SECRH_E54_RESETVAL (0x00000000U)
  4270. #define CSL_EVETPCC_SECRH_E54_MAX (0x00000001U)
  4271. #define CSL_EVETPCC_SECRH_E33_MASK (0x00000002U)
  4272. #define CSL_EVETPCC_SECRH_E33_SHIFT (1U)
  4273. #define CSL_EVETPCC_SECRH_E33_RESETVAL (0x00000000U)
  4274. #define CSL_EVETPCC_SECRH_E33_MAX (0x00000001U)
  4275. #define CSL_EVETPCC_SECRH_E43_MASK (0x00000800U)
  4276. #define CSL_EVETPCC_SECRH_E43_SHIFT (11U)
  4277. #define CSL_EVETPCC_SECRH_E43_RESETVAL (0x00000000U)
  4278. #define CSL_EVETPCC_SECRH_E43_MAX (0x00000001U)
  4279. #define CSL_EVETPCC_SECRH_E53_MASK (0x00200000U)
  4280. #define CSL_EVETPCC_SECRH_E53_SHIFT (21U)
  4281. #define CSL_EVETPCC_SECRH_E53_RESETVAL (0x00000000U)
  4282. #define CSL_EVETPCC_SECRH_E53_MAX (0x00000001U)
  4283. #define CSL_EVETPCC_SECRH_E58_MASK (0x04000000U)
  4284. #define CSL_EVETPCC_SECRH_E58_SHIFT (26U)
  4285. #define CSL_EVETPCC_SECRH_E58_RESETVAL (0x00000000U)
  4286. #define CSL_EVETPCC_SECRH_E58_MAX (0x00000001U)
  4287. #define CSL_EVETPCC_SECRH_E32_MASK (0x00000001U)
  4288. #define CSL_EVETPCC_SECRH_E32_SHIFT (0U)
  4289. #define CSL_EVETPCC_SECRH_E32_RESETVAL (0x00000000U)
  4290. #define CSL_EVETPCC_SECRH_E32_MAX (0x00000001U)
  4291. #define CSL_EVETPCC_SECRH_E63_MASK (0x80000000U)
  4292. #define CSL_EVETPCC_SECRH_E63_SHIFT (31U)
  4293. #define CSL_EVETPCC_SECRH_E63_RESETVAL (0x00000000U)
  4294. #define CSL_EVETPCC_SECRH_E63_MAX (0x00000001U)
  4295. #define CSL_EVETPCC_SECRH_E57_MASK (0x02000000U)
  4296. #define CSL_EVETPCC_SECRH_E57_SHIFT (25U)
  4297. #define CSL_EVETPCC_SECRH_E57_RESETVAL (0x00000000U)
  4298. #define CSL_EVETPCC_SECRH_E57_MAX (0x00000001U)
  4299. #define CSL_EVETPCC_SECRH_E56_MASK (0x01000000U)
  4300. #define CSL_EVETPCC_SECRH_E56_SHIFT (24U)
  4301. #define CSL_EVETPCC_SECRH_E56_RESETVAL (0x00000000U)
  4302. #define CSL_EVETPCC_SECRH_E56_MAX (0x00000001U)
  4303. #define CSL_EVETPCC_SECRH_E55_MASK (0x00800000U)
  4304. #define CSL_EVETPCC_SECRH_E55_SHIFT (23U)
  4305. #define CSL_EVETPCC_SECRH_E55_RESETVAL (0x00000000U)
  4306. #define CSL_EVETPCC_SECRH_E55_MAX (0x00000001U)
  4307. #define CSL_EVETPCC_SECRH_E52_MASK (0x00100000U)
  4308. #define CSL_EVETPCC_SECRH_E52_SHIFT (20U)
  4309. #define CSL_EVETPCC_SECRH_E52_RESETVAL (0x00000000U)
  4310. #define CSL_EVETPCC_SECRH_E52_MAX (0x00000001U)
  4311. #define CSL_EVETPCC_SECRH_E42_MASK (0x00000400U)
  4312. #define CSL_EVETPCC_SECRH_E42_SHIFT (10U)
  4313. #define CSL_EVETPCC_SECRH_E42_RESETVAL (0x00000000U)
  4314. #define CSL_EVETPCC_SECRH_E42_MAX (0x00000001U)
  4315. #define CSL_EVETPCC_SECRH_E51_MASK (0x00080000U)
  4316. #define CSL_EVETPCC_SECRH_E51_SHIFT (19U)
  4317. #define CSL_EVETPCC_SECRH_E51_RESETVAL (0x00000000U)
  4318. #define CSL_EVETPCC_SECRH_E51_MAX (0x00000001U)
  4319. #define CSL_EVETPCC_SECRH_E41_MASK (0x00000200U)
  4320. #define CSL_EVETPCC_SECRH_E41_SHIFT (9U)
  4321. #define CSL_EVETPCC_SECRH_E41_RESETVAL (0x00000000U)
  4322. #define CSL_EVETPCC_SECRH_E41_MAX (0x00000001U)
  4323. #define CSL_EVETPCC_SECRH_E50_MASK (0x00040000U)
  4324. #define CSL_EVETPCC_SECRH_E50_SHIFT (18U)
  4325. #define CSL_EVETPCC_SECRH_E50_RESETVAL (0x00000000U)
  4326. #define CSL_EVETPCC_SECRH_E50_MAX (0x00000001U)
  4327. #define CSL_EVETPCC_SECRH_E40_MASK (0x00000100U)
  4328. #define CSL_EVETPCC_SECRH_E40_SHIFT (8U)
  4329. #define CSL_EVETPCC_SECRH_E40_RESETVAL (0x00000000U)
  4330. #define CSL_EVETPCC_SECRH_E40_MAX (0x00000001U)
  4331. #define CSL_EVETPCC_SECRH_E49_MASK (0x00020000U)
  4332. #define CSL_EVETPCC_SECRH_E49_SHIFT (17U)
  4333. #define CSL_EVETPCC_SECRH_E49_RESETVAL (0x00000000U)
  4334. #define CSL_EVETPCC_SECRH_E49_MAX (0x00000001U)
  4335. #define CSL_EVETPCC_SECRH_E39_MASK (0x00000080U)
  4336. #define CSL_EVETPCC_SECRH_E39_SHIFT (7U)
  4337. #define CSL_EVETPCC_SECRH_E39_RESETVAL (0x00000000U)
  4338. #define CSL_EVETPCC_SECRH_E39_MAX (0x00000001U)
  4339. #define CSL_EVETPCC_SECRH_E48_MASK (0x00010000U)
  4340. #define CSL_EVETPCC_SECRH_E48_SHIFT (16U)
  4341. #define CSL_EVETPCC_SECRH_E48_RESETVAL (0x00000000U)
  4342. #define CSL_EVETPCC_SECRH_E48_MAX (0x00000001U)
  4343. #define CSL_EVETPCC_SECRH_E38_MASK (0x00000040U)
  4344. #define CSL_EVETPCC_SECRH_E38_SHIFT (6U)
  4345. #define CSL_EVETPCC_SECRH_E38_RESETVAL (0x00000000U)
  4346. #define CSL_EVETPCC_SECRH_E38_MAX (0x00000001U)
  4347. #define CSL_EVETPCC_SECRH_E59_MASK (0x08000000U)
  4348. #define CSL_EVETPCC_SECRH_E59_SHIFT (27U)
  4349. #define CSL_EVETPCC_SECRH_E59_RESETVAL (0x00000000U)
  4350. #define CSL_EVETPCC_SECRH_E59_MAX (0x00000001U)
  4351. #define CSL_EVETPCC_SECRH_E47_MASK (0x00008000U)
  4352. #define CSL_EVETPCC_SECRH_E47_SHIFT (15U)
  4353. #define CSL_EVETPCC_SECRH_E47_RESETVAL (0x00000000U)
  4354. #define CSL_EVETPCC_SECRH_E47_MAX (0x00000001U)
  4355. #define CSL_EVETPCC_SECRH_E37_MASK (0x00000020U)
  4356. #define CSL_EVETPCC_SECRH_E37_SHIFT (5U)
  4357. #define CSL_EVETPCC_SECRH_E37_RESETVAL (0x00000000U)
  4358. #define CSL_EVETPCC_SECRH_E37_MAX (0x00000001U)
  4359. #define CSL_EVETPCC_SECRH_E60_MASK (0x10000000U)
  4360. #define CSL_EVETPCC_SECRH_E60_SHIFT (28U)
  4361. #define CSL_EVETPCC_SECRH_E60_RESETVAL (0x00000000U)
  4362. #define CSL_EVETPCC_SECRH_E60_MAX (0x00000001U)
  4363. #define CSL_EVETPCC_SECRH_E36_MASK (0x00000010U)
  4364. #define CSL_EVETPCC_SECRH_E36_SHIFT (4U)
  4365. #define CSL_EVETPCC_SECRH_E36_RESETVAL (0x00000000U)
  4366. #define CSL_EVETPCC_SECRH_E36_MAX (0x00000001U)
  4367. #define CSL_EVETPCC_SECRH_E46_MASK (0x00004000U)
  4368. #define CSL_EVETPCC_SECRH_E46_SHIFT (14U)
  4369. #define CSL_EVETPCC_SECRH_E46_RESETVAL (0x00000000U)
  4370. #define CSL_EVETPCC_SECRH_E46_MAX (0x00000001U)
  4371. #define CSL_EVETPCC_SECRH_E61_MASK (0x20000000U)
  4372. #define CSL_EVETPCC_SECRH_E61_SHIFT (29U)
  4373. #define CSL_EVETPCC_SECRH_E61_RESETVAL (0x00000000U)
  4374. #define CSL_EVETPCC_SECRH_E61_MAX (0x00000001U)
  4375. #define CSL_EVETPCC_SECRH_E35_MASK (0x00000008U)
  4376. #define CSL_EVETPCC_SECRH_E35_SHIFT (3U)
  4377. #define CSL_EVETPCC_SECRH_E35_RESETVAL (0x00000000U)
  4378. #define CSL_EVETPCC_SECRH_E35_MAX (0x00000001U)
  4379. #define CSL_EVETPCC_SECRH_E62_MASK (0x40000000U)
  4380. #define CSL_EVETPCC_SECRH_E62_SHIFT (30U)
  4381. #define CSL_EVETPCC_SECRH_E62_RESETVAL (0x00000000U)
  4382. #define CSL_EVETPCC_SECRH_E62_MAX (0x00000001U)
  4383. #define CSL_EVETPCC_SECRH_E45_MASK (0x00002000U)
  4384. #define CSL_EVETPCC_SECRH_E45_SHIFT (13U)
  4385. #define CSL_EVETPCC_SECRH_E45_RESETVAL (0x00000000U)
  4386. #define CSL_EVETPCC_SECRH_E45_MAX (0x00000001U)
  4387. #define CSL_EVETPCC_SECRH_RESETVAL (0x00000000U)
  4388. /* IER */
  4389. #define CSL_EVETPCC_IER_I15_MASK (0x00008000U)
  4390. #define CSL_EVETPCC_IER_I15_SHIFT (15U)
  4391. #define CSL_EVETPCC_IER_I15_RESETVAL (0x00000000U)
  4392. #define CSL_EVETPCC_IER_I15_MAX (0x00000001U)
  4393. #define CSL_EVETPCC_IER_I30_MASK (0x40000000U)
  4394. #define CSL_EVETPCC_IER_I30_SHIFT (30U)
  4395. #define CSL_EVETPCC_IER_I30_RESETVAL (0x00000000U)
  4396. #define CSL_EVETPCC_IER_I30_MAX (0x00000001U)
  4397. #define CSL_EVETPCC_IER_I14_MASK (0x00004000U)
  4398. #define CSL_EVETPCC_IER_I14_SHIFT (14U)
  4399. #define CSL_EVETPCC_IER_I14_RESETVAL (0x00000000U)
  4400. #define CSL_EVETPCC_IER_I14_MAX (0x00000001U)
  4401. #define CSL_EVETPCC_IER_I29_MASK (0x20000000U)
  4402. #define CSL_EVETPCC_IER_I29_SHIFT (29U)
  4403. #define CSL_EVETPCC_IER_I29_RESETVAL (0x00000000U)
  4404. #define CSL_EVETPCC_IER_I29_MAX (0x00000001U)
  4405. #define CSL_EVETPCC_IER_I7_MASK (0x00000080U)
  4406. #define CSL_EVETPCC_IER_I7_SHIFT (7U)
  4407. #define CSL_EVETPCC_IER_I7_RESETVAL (0x00000000U)
  4408. #define CSL_EVETPCC_IER_I7_MAX (0x00000001U)
  4409. #define CSL_EVETPCC_IER_I28_MASK (0x10000000U)
  4410. #define CSL_EVETPCC_IER_I28_SHIFT (28U)
  4411. #define CSL_EVETPCC_IER_I28_RESETVAL (0x00000000U)
  4412. #define CSL_EVETPCC_IER_I28_MAX (0x00000001U)
  4413. #define CSL_EVETPCC_IER_I17_MASK (0x00020000U)
  4414. #define CSL_EVETPCC_IER_I17_SHIFT (17U)
  4415. #define CSL_EVETPCC_IER_I17_RESETVAL (0x00000000U)
  4416. #define CSL_EVETPCC_IER_I17_MAX (0x00000001U)
  4417. #define CSL_EVETPCC_IER_I16_MASK (0x00010000U)
  4418. #define CSL_EVETPCC_IER_I16_SHIFT (16U)
  4419. #define CSL_EVETPCC_IER_I16_RESETVAL (0x00000000U)
  4420. #define CSL_EVETPCC_IER_I16_MAX (0x00000001U)
  4421. #define CSL_EVETPCC_IER_I27_MASK (0x08000000U)
  4422. #define CSL_EVETPCC_IER_I27_SHIFT (27U)
  4423. #define CSL_EVETPCC_IER_I27_RESETVAL (0x00000000U)
  4424. #define CSL_EVETPCC_IER_I27_MAX (0x00000001U)
  4425. #define CSL_EVETPCC_IER_I0_MASK (0x00000001U)
  4426. #define CSL_EVETPCC_IER_I0_SHIFT (0U)
  4427. #define CSL_EVETPCC_IER_I0_RESETVAL (0x00000000U)
  4428. #define CSL_EVETPCC_IER_I0_MAX (0x00000001U)
  4429. #define CSL_EVETPCC_IER_I1_MASK (0x00000002U)
  4430. #define CSL_EVETPCC_IER_I1_SHIFT (1U)
  4431. #define CSL_EVETPCC_IER_I1_RESETVAL (0x00000000U)
  4432. #define CSL_EVETPCC_IER_I1_MAX (0x00000001U)
  4433. #define CSL_EVETPCC_IER_I13_MASK (0x00002000U)
  4434. #define CSL_EVETPCC_IER_I13_SHIFT (13U)
  4435. #define CSL_EVETPCC_IER_I13_RESETVAL (0x00000000U)
  4436. #define CSL_EVETPCC_IER_I13_MAX (0x00000001U)
  4437. #define CSL_EVETPCC_IER_I2_MASK (0x00000004U)
  4438. #define CSL_EVETPCC_IER_I2_SHIFT (2U)
  4439. #define CSL_EVETPCC_IER_I2_RESETVAL (0x00000000U)
  4440. #define CSL_EVETPCC_IER_I2_MAX (0x00000001U)
  4441. #define CSL_EVETPCC_IER_I31_MASK (0x80000000U)
  4442. #define CSL_EVETPCC_IER_I31_SHIFT (31U)
  4443. #define CSL_EVETPCC_IER_I31_RESETVAL (0x00000000U)
  4444. #define CSL_EVETPCC_IER_I31_MAX (0x00000001U)
  4445. #define CSL_EVETPCC_IER_I22_MASK (0x00400000U)
  4446. #define CSL_EVETPCC_IER_I22_SHIFT (22U)
  4447. #define CSL_EVETPCC_IER_I22_RESETVAL (0x00000000U)
  4448. #define CSL_EVETPCC_IER_I22_MAX (0x00000001U)
  4449. #define CSL_EVETPCC_IER_I3_MASK (0x00000008U)
  4450. #define CSL_EVETPCC_IER_I3_SHIFT (3U)
  4451. #define CSL_EVETPCC_IER_I3_RESETVAL (0x00000000U)
  4452. #define CSL_EVETPCC_IER_I3_MAX (0x00000001U)
  4453. #define CSL_EVETPCC_IER_I26_MASK (0x04000000U)
  4454. #define CSL_EVETPCC_IER_I26_SHIFT (26U)
  4455. #define CSL_EVETPCC_IER_I26_RESETVAL (0x00000000U)
  4456. #define CSL_EVETPCC_IER_I26_MAX (0x00000001U)
  4457. #define CSL_EVETPCC_IER_I5_MASK (0x00000020U)
  4458. #define CSL_EVETPCC_IER_I5_SHIFT (5U)
  4459. #define CSL_EVETPCC_IER_I5_RESETVAL (0x00000000U)
  4460. #define CSL_EVETPCC_IER_I5_MAX (0x00000001U)
  4461. #define CSL_EVETPCC_IER_I19_MASK (0x00080000U)
  4462. #define CSL_EVETPCC_IER_I19_SHIFT (19U)
  4463. #define CSL_EVETPCC_IER_I19_RESETVAL (0x00000000U)
  4464. #define CSL_EVETPCC_IER_I19_MAX (0x00000001U)
  4465. #define CSL_EVETPCC_IER_I8_MASK (0x00000100U)
  4466. #define CSL_EVETPCC_IER_I8_SHIFT (8U)
  4467. #define CSL_EVETPCC_IER_I8_RESETVAL (0x00000000U)
  4468. #define CSL_EVETPCC_IER_I8_MAX (0x00000001U)
  4469. #define CSL_EVETPCC_IER_I25_MASK (0x02000000U)
  4470. #define CSL_EVETPCC_IER_I25_SHIFT (25U)
  4471. #define CSL_EVETPCC_IER_I25_RESETVAL (0x00000000U)
  4472. #define CSL_EVETPCC_IER_I25_MAX (0x00000001U)
  4473. #define CSL_EVETPCC_IER_I4_MASK (0x00000010U)
  4474. #define CSL_EVETPCC_IER_I4_SHIFT (4U)
  4475. #define CSL_EVETPCC_IER_I4_RESETVAL (0x00000000U)
  4476. #define CSL_EVETPCC_IER_I4_MAX (0x00000001U)
  4477. #define CSL_EVETPCC_IER_I18_MASK (0x00040000U)
  4478. #define CSL_EVETPCC_IER_I18_SHIFT (18U)
  4479. #define CSL_EVETPCC_IER_I18_RESETVAL (0x00000000U)
  4480. #define CSL_EVETPCC_IER_I18_MAX (0x00000001U)
  4481. #define CSL_EVETPCC_IER_I9_MASK (0x00000200U)
  4482. #define CSL_EVETPCC_IER_I9_SHIFT (9U)
  4483. #define CSL_EVETPCC_IER_I9_RESETVAL (0x00000000U)
  4484. #define CSL_EVETPCC_IER_I9_MAX (0x00000001U)
  4485. #define CSL_EVETPCC_IER_I21_MASK (0x00200000U)
  4486. #define CSL_EVETPCC_IER_I21_SHIFT (21U)
  4487. #define CSL_EVETPCC_IER_I21_RESETVAL (0x00000000U)
  4488. #define CSL_EVETPCC_IER_I21_MAX (0x00000001U)
  4489. #define CSL_EVETPCC_IER_I24_MASK (0x01000000U)
  4490. #define CSL_EVETPCC_IER_I24_SHIFT (24U)
  4491. #define CSL_EVETPCC_IER_I24_RESETVAL (0x00000000U)
  4492. #define CSL_EVETPCC_IER_I24_MAX (0x00000001U)
  4493. #define CSL_EVETPCC_IER_I10_MASK (0x00000400U)
  4494. #define CSL_EVETPCC_IER_I10_SHIFT (10U)
  4495. #define CSL_EVETPCC_IER_I10_RESETVAL (0x00000000U)
  4496. #define CSL_EVETPCC_IER_I10_MAX (0x00000001U)
  4497. #define CSL_EVETPCC_IER_I12_MASK (0x00001000U)
  4498. #define CSL_EVETPCC_IER_I12_SHIFT (12U)
  4499. #define CSL_EVETPCC_IER_I12_RESETVAL (0x00000000U)
  4500. #define CSL_EVETPCC_IER_I12_MAX (0x00000001U)
  4501. #define CSL_EVETPCC_IER_I23_MASK (0x00800000U)
  4502. #define CSL_EVETPCC_IER_I23_SHIFT (23U)
  4503. #define CSL_EVETPCC_IER_I23_RESETVAL (0x00000000U)
  4504. #define CSL_EVETPCC_IER_I23_MAX (0x00000001U)
  4505. #define CSL_EVETPCC_IER_I20_MASK (0x00100000U)
  4506. #define CSL_EVETPCC_IER_I20_SHIFT (20U)
  4507. #define CSL_EVETPCC_IER_I20_RESETVAL (0x00000000U)
  4508. #define CSL_EVETPCC_IER_I20_MAX (0x00000001U)
  4509. #define CSL_EVETPCC_IER_I6_MASK (0x00000040U)
  4510. #define CSL_EVETPCC_IER_I6_SHIFT (6U)
  4511. #define CSL_EVETPCC_IER_I6_RESETVAL (0x00000000U)
  4512. #define CSL_EVETPCC_IER_I6_MAX (0x00000001U)
  4513. #define CSL_EVETPCC_IER_I11_MASK (0x00000800U)
  4514. #define CSL_EVETPCC_IER_I11_SHIFT (11U)
  4515. #define CSL_EVETPCC_IER_I11_RESETVAL (0x00000000U)
  4516. #define CSL_EVETPCC_IER_I11_MAX (0x00000001U)
  4517. #define CSL_EVETPCC_IER_RESETVAL (0x00000000U)
  4518. /* IERH */
  4519. #define CSL_EVETPCC_IERH_I48_MASK (0x00010000U)
  4520. #define CSL_EVETPCC_IERH_I48_SHIFT (16U)
  4521. #define CSL_EVETPCC_IERH_I48_RESETVAL (0x00000000U)
  4522. #define CSL_EVETPCC_IERH_I48_MAX (0x00000001U)
  4523. #define CSL_EVETPCC_IERH_I35_MASK (0x00000008U)
  4524. #define CSL_EVETPCC_IERH_I35_SHIFT (3U)
  4525. #define CSL_EVETPCC_IERH_I35_RESETVAL (0x00000000U)
  4526. #define CSL_EVETPCC_IERH_I35_MAX (0x00000001U)
  4527. #define CSL_EVETPCC_IERH_I34_MASK (0x00000004U)
  4528. #define CSL_EVETPCC_IERH_I34_SHIFT (2U)
  4529. #define CSL_EVETPCC_IERH_I34_RESETVAL (0x00000000U)
  4530. #define CSL_EVETPCC_IERH_I34_MAX (0x00000001U)
  4531. #define CSL_EVETPCC_IERH_I46_MASK (0x00004000U)
  4532. #define CSL_EVETPCC_IERH_I46_SHIFT (14U)
  4533. #define CSL_EVETPCC_IERH_I46_RESETVAL (0x00000000U)
  4534. #define CSL_EVETPCC_IERH_I46_MAX (0x00000001U)
  4535. #define CSL_EVETPCC_IERH_I59_MASK (0x08000000U)
  4536. #define CSL_EVETPCC_IERH_I59_SHIFT (27U)
  4537. #define CSL_EVETPCC_IERH_I59_RESETVAL (0x00000000U)
  4538. #define CSL_EVETPCC_IERH_I59_MAX (0x00000001U)
  4539. #define CSL_EVETPCC_IERH_I33_MASK (0x00000002U)
  4540. #define CSL_EVETPCC_IERH_I33_SHIFT (1U)
  4541. #define CSL_EVETPCC_IERH_I33_RESETVAL (0x00000000U)
  4542. #define CSL_EVETPCC_IERH_I33_MAX (0x00000001U)
  4543. #define CSL_EVETPCC_IERH_I45_MASK (0x00002000U)
  4544. #define CSL_EVETPCC_IERH_I45_SHIFT (13U)
  4545. #define CSL_EVETPCC_IERH_I45_RESETVAL (0x00000000U)
  4546. #define CSL_EVETPCC_IERH_I45_MAX (0x00000001U)
  4547. #define CSL_EVETPCC_IERH_I60_MASK (0x10000000U)
  4548. #define CSL_EVETPCC_IERH_I60_SHIFT (28U)
  4549. #define CSL_EVETPCC_IERH_I60_RESETVAL (0x00000000U)
  4550. #define CSL_EVETPCC_IERH_I60_MAX (0x00000001U)
  4551. #define CSL_EVETPCC_IERH_I32_MASK (0x00000001U)
  4552. #define CSL_EVETPCC_IERH_I32_SHIFT (0U)
  4553. #define CSL_EVETPCC_IERH_I32_RESETVAL (0x00000000U)
  4554. #define CSL_EVETPCC_IERH_I32_MAX (0x00000001U)
  4555. #define CSL_EVETPCC_IERH_I44_MASK (0x00001000U)
  4556. #define CSL_EVETPCC_IERH_I44_SHIFT (12U)
  4557. #define CSL_EVETPCC_IERH_I44_RESETVAL (0x00000000U)
  4558. #define CSL_EVETPCC_IERH_I44_MAX (0x00000001U)
  4559. #define CSL_EVETPCC_IERH_I61_MASK (0x20000000U)
  4560. #define CSL_EVETPCC_IERH_I61_SHIFT (29U)
  4561. #define CSL_EVETPCC_IERH_I61_RESETVAL (0x00000000U)
  4562. #define CSL_EVETPCC_IERH_I61_MAX (0x00000001U)
  4563. #define CSL_EVETPCC_IERH_I43_MASK (0x00000800U)
  4564. #define CSL_EVETPCC_IERH_I43_SHIFT (11U)
  4565. #define CSL_EVETPCC_IERH_I43_RESETVAL (0x00000000U)
  4566. #define CSL_EVETPCC_IERH_I43_MAX (0x00000001U)
  4567. #define CSL_EVETPCC_IERH_I49_MASK (0x00020000U)
  4568. #define CSL_EVETPCC_IERH_I49_SHIFT (17U)
  4569. #define CSL_EVETPCC_IERH_I49_RESETVAL (0x00000000U)
  4570. #define CSL_EVETPCC_IERH_I49_MAX (0x00000001U)
  4571. #define CSL_EVETPCC_IERH_I62_MASK (0x40000000U)
  4572. #define CSL_EVETPCC_IERH_I62_SHIFT (30U)
  4573. #define CSL_EVETPCC_IERH_I62_RESETVAL (0x00000000U)
  4574. #define CSL_EVETPCC_IERH_I62_MAX (0x00000001U)
  4575. #define CSL_EVETPCC_IERH_I50_MASK (0x00040000U)
  4576. #define CSL_EVETPCC_IERH_I50_SHIFT (18U)
  4577. #define CSL_EVETPCC_IERH_I50_RESETVAL (0x00000000U)
  4578. #define CSL_EVETPCC_IERH_I50_MAX (0x00000001U)
  4579. #define CSL_EVETPCC_IERH_I42_MASK (0x00000400U)
  4580. #define CSL_EVETPCC_IERH_I42_SHIFT (10U)
  4581. #define CSL_EVETPCC_IERH_I42_RESETVAL (0x00000000U)
  4582. #define CSL_EVETPCC_IERH_I42_MAX (0x00000001U)
  4583. #define CSL_EVETPCC_IERH_I63_MASK (0x80000000U)
  4584. #define CSL_EVETPCC_IERH_I63_SHIFT (31U)
  4585. #define CSL_EVETPCC_IERH_I63_RESETVAL (0x00000000U)
  4586. #define CSL_EVETPCC_IERH_I63_MAX (0x00000001U)
  4587. #define CSL_EVETPCC_IERH_I51_MASK (0x00080000U)
  4588. #define CSL_EVETPCC_IERH_I51_SHIFT (19U)
  4589. #define CSL_EVETPCC_IERH_I51_RESETVAL (0x00000000U)
  4590. #define CSL_EVETPCC_IERH_I51_MAX (0x00000001U)
  4591. #define CSL_EVETPCC_IERH_I41_MASK (0x00000200U)
  4592. #define CSL_EVETPCC_IERH_I41_SHIFT (9U)
  4593. #define CSL_EVETPCC_IERH_I41_RESETVAL (0x00000000U)
  4594. #define CSL_EVETPCC_IERH_I41_MAX (0x00000001U)
  4595. #define CSL_EVETPCC_IERH_I52_MASK (0x00100000U)
  4596. #define CSL_EVETPCC_IERH_I52_SHIFT (20U)
  4597. #define CSL_EVETPCC_IERH_I52_RESETVAL (0x00000000U)
  4598. #define CSL_EVETPCC_IERH_I52_MAX (0x00000001U)
  4599. #define CSL_EVETPCC_IERH_I40_MASK (0x00000100U)
  4600. #define CSL_EVETPCC_IERH_I40_SHIFT (8U)
  4601. #define CSL_EVETPCC_IERH_I40_RESETVAL (0x00000000U)
  4602. #define CSL_EVETPCC_IERH_I40_MAX (0x00000001U)
  4603. #define CSL_EVETPCC_IERH_I53_MASK (0x00200000U)
  4604. #define CSL_EVETPCC_IERH_I53_SHIFT (21U)
  4605. #define CSL_EVETPCC_IERH_I53_RESETVAL (0x00000000U)
  4606. #define CSL_EVETPCC_IERH_I53_MAX (0x00000001U)
  4607. #define CSL_EVETPCC_IERH_I39_MASK (0x00000080U)
  4608. #define CSL_EVETPCC_IERH_I39_SHIFT (7U)
  4609. #define CSL_EVETPCC_IERH_I39_RESETVAL (0x00000000U)
  4610. #define CSL_EVETPCC_IERH_I39_MAX (0x00000001U)
  4611. #define CSL_EVETPCC_IERH_I54_MASK (0x00400000U)
  4612. #define CSL_EVETPCC_IERH_I54_SHIFT (22U)
  4613. #define CSL_EVETPCC_IERH_I54_RESETVAL (0x00000000U)
  4614. #define CSL_EVETPCC_IERH_I54_MAX (0x00000001U)
  4615. #define CSL_EVETPCC_IERH_I55_MASK (0x00800000U)
  4616. #define CSL_EVETPCC_IERH_I55_SHIFT (23U)
  4617. #define CSL_EVETPCC_IERH_I55_RESETVAL (0x00000000U)
  4618. #define CSL_EVETPCC_IERH_I55_MAX (0x00000001U)
  4619. #define CSL_EVETPCC_IERH_I56_MASK (0x01000000U)
  4620. #define CSL_EVETPCC_IERH_I56_SHIFT (24U)
  4621. #define CSL_EVETPCC_IERH_I56_RESETVAL (0x00000000U)
  4622. #define CSL_EVETPCC_IERH_I56_MAX (0x00000001U)
  4623. #define CSL_EVETPCC_IERH_I38_MASK (0x00000040U)
  4624. #define CSL_EVETPCC_IERH_I38_SHIFT (6U)
  4625. #define CSL_EVETPCC_IERH_I38_RESETVAL (0x00000000U)
  4626. #define CSL_EVETPCC_IERH_I38_MAX (0x00000001U)
  4627. #define CSL_EVETPCC_IERH_I57_MASK (0x02000000U)
  4628. #define CSL_EVETPCC_IERH_I57_SHIFT (25U)
  4629. #define CSL_EVETPCC_IERH_I57_RESETVAL (0x00000000U)
  4630. #define CSL_EVETPCC_IERH_I57_MAX (0x00000001U)
  4631. #define CSL_EVETPCC_IERH_I58_MASK (0x04000000U)
  4632. #define CSL_EVETPCC_IERH_I58_SHIFT (26U)
  4633. #define CSL_EVETPCC_IERH_I58_RESETVAL (0x00000000U)
  4634. #define CSL_EVETPCC_IERH_I58_MAX (0x00000001U)
  4635. #define CSL_EVETPCC_IERH_I37_MASK (0x00000020U)
  4636. #define CSL_EVETPCC_IERH_I37_SHIFT (5U)
  4637. #define CSL_EVETPCC_IERH_I37_RESETVAL (0x00000000U)
  4638. #define CSL_EVETPCC_IERH_I37_MAX (0x00000001U)
  4639. #define CSL_EVETPCC_IERH_I47_MASK (0x00008000U)
  4640. #define CSL_EVETPCC_IERH_I47_SHIFT (15U)
  4641. #define CSL_EVETPCC_IERH_I47_RESETVAL (0x00000000U)
  4642. #define CSL_EVETPCC_IERH_I47_MAX (0x00000001U)
  4643. #define CSL_EVETPCC_IERH_I36_MASK (0x00000010U)
  4644. #define CSL_EVETPCC_IERH_I36_SHIFT (4U)
  4645. #define CSL_EVETPCC_IERH_I36_RESETVAL (0x00000000U)
  4646. #define CSL_EVETPCC_IERH_I36_MAX (0x00000001U)
  4647. #define CSL_EVETPCC_IERH_RESETVAL (0x00000000U)
  4648. /* IECR */
  4649. #define CSL_EVETPCC_IECR_I27_MASK (0x08000000U)
  4650. #define CSL_EVETPCC_IECR_I27_SHIFT (27U)
  4651. #define CSL_EVETPCC_IECR_I27_RESETVAL (0x00000000U)
  4652. #define CSL_EVETPCC_IECR_I27_MAX (0x00000001U)
  4653. #define CSL_EVETPCC_IECR_I28_MASK (0x10000000U)
  4654. #define CSL_EVETPCC_IECR_I28_SHIFT (28U)
  4655. #define CSL_EVETPCC_IECR_I28_RESETVAL (0x00000000U)
  4656. #define CSL_EVETPCC_IECR_I28_MAX (0x00000001U)
  4657. #define CSL_EVETPCC_IECR_I25_MASK (0x02000000U)
  4658. #define CSL_EVETPCC_IECR_I25_SHIFT (25U)
  4659. #define CSL_EVETPCC_IECR_I25_RESETVAL (0x00000000U)
  4660. #define CSL_EVETPCC_IECR_I25_MAX (0x00000001U)
  4661. #define CSL_EVETPCC_IECR_I16_MASK (0x00010000U)
  4662. #define CSL_EVETPCC_IECR_I16_SHIFT (16U)
  4663. #define CSL_EVETPCC_IECR_I16_RESETVAL (0x00000000U)
  4664. #define CSL_EVETPCC_IECR_I16_MAX (0x00000001U)
  4665. #define CSL_EVETPCC_IECR_I26_MASK (0x04000000U)
  4666. #define CSL_EVETPCC_IECR_I26_SHIFT (26U)
  4667. #define CSL_EVETPCC_IECR_I26_RESETVAL (0x00000000U)
  4668. #define CSL_EVETPCC_IECR_I26_MAX (0x00000001U)
  4669. #define CSL_EVETPCC_IECR_I15_MASK (0x00008000U)
  4670. #define CSL_EVETPCC_IECR_I15_SHIFT (15U)
  4671. #define CSL_EVETPCC_IECR_I15_RESETVAL (0x00000000U)
  4672. #define CSL_EVETPCC_IECR_I15_MAX (0x00000001U)
  4673. #define CSL_EVETPCC_IECR_I14_MASK (0x00004000U)
  4674. #define CSL_EVETPCC_IECR_I14_SHIFT (14U)
  4675. #define CSL_EVETPCC_IECR_I14_RESETVAL (0x00000000U)
  4676. #define CSL_EVETPCC_IECR_I14_MAX (0x00000001U)
  4677. #define CSL_EVETPCC_IECR_I13_MASK (0x00002000U)
  4678. #define CSL_EVETPCC_IECR_I13_SHIFT (13U)
  4679. #define CSL_EVETPCC_IECR_I13_RESETVAL (0x00000000U)
  4680. #define CSL_EVETPCC_IECR_I13_MAX (0x00000001U)
  4681. #define CSL_EVETPCC_IECR_I0_MASK (0x00000001U)
  4682. #define CSL_EVETPCC_IECR_I0_SHIFT (0U)
  4683. #define CSL_EVETPCC_IECR_I0_RESETVAL (0x00000000U)
  4684. #define CSL_EVETPCC_IECR_I0_MAX (0x00000001U)
  4685. #define CSL_EVETPCC_IECR_I22_MASK (0x00400000U)
  4686. #define CSL_EVETPCC_IECR_I22_SHIFT (22U)
  4687. #define CSL_EVETPCC_IECR_I22_RESETVAL (0x00000000U)
  4688. #define CSL_EVETPCC_IECR_I22_MAX (0x00000001U)
  4689. #define CSL_EVETPCC_IECR_I10_MASK (0x00000400U)
  4690. #define CSL_EVETPCC_IECR_I10_SHIFT (10U)
  4691. #define CSL_EVETPCC_IECR_I10_RESETVAL (0x00000000U)
  4692. #define CSL_EVETPCC_IECR_I10_MAX (0x00000001U)
  4693. #define CSL_EVETPCC_IECR_I21_MASK (0x00200000U)
  4694. #define CSL_EVETPCC_IECR_I21_SHIFT (21U)
  4695. #define CSL_EVETPCC_IECR_I21_RESETVAL (0x00000000U)
  4696. #define CSL_EVETPCC_IECR_I21_MAX (0x00000001U)
  4697. #define CSL_EVETPCC_IECR_I9_MASK (0x00000200U)
  4698. #define CSL_EVETPCC_IECR_I9_SHIFT (9U)
  4699. #define CSL_EVETPCC_IECR_I9_RESETVAL (0x00000000U)
  4700. #define CSL_EVETPCC_IECR_I9_MAX (0x00000001U)
  4701. #define CSL_EVETPCC_IECR_I1_MASK (0x00000002U)
  4702. #define CSL_EVETPCC_IECR_I1_SHIFT (1U)
  4703. #define CSL_EVETPCC_IECR_I1_RESETVAL (0x00000000U)
  4704. #define CSL_EVETPCC_IECR_I1_MAX (0x00000001U)
  4705. #define CSL_EVETPCC_IECR_I24_MASK (0x01000000U)
  4706. #define CSL_EVETPCC_IECR_I24_SHIFT (24U)
  4707. #define CSL_EVETPCC_IECR_I24_RESETVAL (0x00000000U)
  4708. #define CSL_EVETPCC_IECR_I24_MAX (0x00000001U)
  4709. #define CSL_EVETPCC_IECR_I3_MASK (0x00000008U)
  4710. #define CSL_EVETPCC_IECR_I3_SHIFT (3U)
  4711. #define CSL_EVETPCC_IECR_I3_RESETVAL (0x00000000U)
  4712. #define CSL_EVETPCC_IECR_I3_MAX (0x00000001U)
  4713. #define CSL_EVETPCC_IECR_I2_MASK (0x00000004U)
  4714. #define CSL_EVETPCC_IECR_I2_SHIFT (2U)
  4715. #define CSL_EVETPCC_IECR_I2_RESETVAL (0x00000000U)
  4716. #define CSL_EVETPCC_IECR_I2_MAX (0x00000001U)
  4717. #define CSL_EVETPCC_IECR_I12_MASK (0x00001000U)
  4718. #define CSL_EVETPCC_IECR_I12_SHIFT (12U)
  4719. #define CSL_EVETPCC_IECR_I12_RESETVAL (0x00000000U)
  4720. #define CSL_EVETPCC_IECR_I12_MAX (0x00000001U)
  4721. #define CSL_EVETPCC_IECR_I23_MASK (0x00800000U)
  4722. #define CSL_EVETPCC_IECR_I23_SHIFT (23U)
  4723. #define CSL_EVETPCC_IECR_I23_RESETVAL (0x00000000U)
  4724. #define CSL_EVETPCC_IECR_I23_MAX (0x00000001U)
  4725. #define CSL_EVETPCC_IECR_I4_MASK (0x00000010U)
  4726. #define CSL_EVETPCC_IECR_I4_SHIFT (4U)
  4727. #define CSL_EVETPCC_IECR_I4_RESETVAL (0x00000000U)
  4728. #define CSL_EVETPCC_IECR_I4_MAX (0x00000001U)
  4729. #define CSL_EVETPCC_IECR_I11_MASK (0x00000800U)
  4730. #define CSL_EVETPCC_IECR_I11_SHIFT (11U)
  4731. #define CSL_EVETPCC_IECR_I11_RESETVAL (0x00000000U)
  4732. #define CSL_EVETPCC_IECR_I11_MAX (0x00000001U)
  4733. #define CSL_EVETPCC_IECR_I6_MASK (0x00000040U)
  4734. #define CSL_EVETPCC_IECR_I6_SHIFT (6U)
  4735. #define CSL_EVETPCC_IECR_I6_RESETVAL (0x00000000U)
  4736. #define CSL_EVETPCC_IECR_I6_MAX (0x00000001U)
  4737. #define CSL_EVETPCC_IECR_I31_MASK (0x80000000U)
  4738. #define CSL_EVETPCC_IECR_I31_SHIFT (31U)
  4739. #define CSL_EVETPCC_IECR_I31_RESETVAL (0x00000000U)
  4740. #define CSL_EVETPCC_IECR_I31_MAX (0x00000001U)
  4741. #define CSL_EVETPCC_IECR_I18_MASK (0x00040000U)
  4742. #define CSL_EVETPCC_IECR_I18_SHIFT (18U)
  4743. #define CSL_EVETPCC_IECR_I18_RESETVAL (0x00000000U)
  4744. #define CSL_EVETPCC_IECR_I18_MAX (0x00000001U)
  4745. #define CSL_EVETPCC_IECR_I17_MASK (0x00020000U)
  4746. #define CSL_EVETPCC_IECR_I17_SHIFT (17U)
  4747. #define CSL_EVETPCC_IECR_I17_RESETVAL (0x00000000U)
  4748. #define CSL_EVETPCC_IECR_I17_MAX (0x00000001U)
  4749. #define CSL_EVETPCC_IECR_I5_MASK (0x00000020U)
  4750. #define CSL_EVETPCC_IECR_I5_SHIFT (5U)
  4751. #define CSL_EVETPCC_IECR_I5_RESETVAL (0x00000000U)
  4752. #define CSL_EVETPCC_IECR_I5_MAX (0x00000001U)
  4753. #define CSL_EVETPCC_IECR_I20_MASK (0x00100000U)
  4754. #define CSL_EVETPCC_IECR_I20_SHIFT (20U)
  4755. #define CSL_EVETPCC_IECR_I20_RESETVAL (0x00000000U)
  4756. #define CSL_EVETPCC_IECR_I20_MAX (0x00000001U)
  4757. #define CSL_EVETPCC_IECR_I29_MASK (0x20000000U)
  4758. #define CSL_EVETPCC_IECR_I29_SHIFT (29U)
  4759. #define CSL_EVETPCC_IECR_I29_RESETVAL (0x00000000U)
  4760. #define CSL_EVETPCC_IECR_I29_MAX (0x00000001U)
  4761. #define CSL_EVETPCC_IECR_I8_MASK (0x00000100U)
  4762. #define CSL_EVETPCC_IECR_I8_SHIFT (8U)
  4763. #define CSL_EVETPCC_IECR_I8_RESETVAL (0x00000000U)
  4764. #define CSL_EVETPCC_IECR_I8_MAX (0x00000001U)
  4765. #define CSL_EVETPCC_IECR_I19_MASK (0x00080000U)
  4766. #define CSL_EVETPCC_IECR_I19_SHIFT (19U)
  4767. #define CSL_EVETPCC_IECR_I19_RESETVAL (0x00000000U)
  4768. #define CSL_EVETPCC_IECR_I19_MAX (0x00000001U)
  4769. #define CSL_EVETPCC_IECR_I30_MASK (0x40000000U)
  4770. #define CSL_EVETPCC_IECR_I30_SHIFT (30U)
  4771. #define CSL_EVETPCC_IECR_I30_RESETVAL (0x00000000U)
  4772. #define CSL_EVETPCC_IECR_I30_MAX (0x00000001U)
  4773. #define CSL_EVETPCC_IECR_I7_MASK (0x00000080U)
  4774. #define CSL_EVETPCC_IECR_I7_SHIFT (7U)
  4775. #define CSL_EVETPCC_IECR_I7_RESETVAL (0x00000000U)
  4776. #define CSL_EVETPCC_IECR_I7_MAX (0x00000001U)
  4777. #define CSL_EVETPCC_IECR_RESETVAL (0x00000000U)
  4778. /* IECRH */
  4779. #define CSL_EVETPCC_IECRH_I35_MASK (0x00000008U)
  4780. #define CSL_EVETPCC_IECRH_I35_SHIFT (3U)
  4781. #define CSL_EVETPCC_IECRH_I35_RESETVAL (0x00000000U)
  4782. #define CSL_EVETPCC_IECRH_I35_MAX (0x00000001U)
  4783. #define CSL_EVETPCC_IECRH_I48_MASK (0x00010000U)
  4784. #define CSL_EVETPCC_IECRH_I48_SHIFT (16U)
  4785. #define CSL_EVETPCC_IECRH_I48_RESETVAL (0x00000000U)
  4786. #define CSL_EVETPCC_IECRH_I48_MAX (0x00000001U)
  4787. #define CSL_EVETPCC_IECRH_I56_MASK (0x01000000U)
  4788. #define CSL_EVETPCC_IECRH_I56_SHIFT (24U)
  4789. #define CSL_EVETPCC_IECRH_I56_RESETVAL (0x00000000U)
  4790. #define CSL_EVETPCC_IECRH_I56_MAX (0x00000001U)
  4791. #define CSL_EVETPCC_IECRH_I34_MASK (0x00000004U)
  4792. #define CSL_EVETPCC_IECRH_I34_SHIFT (2U)
  4793. #define CSL_EVETPCC_IECRH_I34_RESETVAL (0x00000000U)
  4794. #define CSL_EVETPCC_IECRH_I34_MAX (0x00000001U)
  4795. #define CSL_EVETPCC_IECRH_I47_MASK (0x00008000U)
  4796. #define CSL_EVETPCC_IECRH_I47_SHIFT (15U)
  4797. #define CSL_EVETPCC_IECRH_I47_RESETVAL (0x00000000U)
  4798. #define CSL_EVETPCC_IECRH_I47_MAX (0x00000001U)
  4799. #define CSL_EVETPCC_IECRH_I46_MASK (0x00004000U)
  4800. #define CSL_EVETPCC_IECRH_I46_SHIFT (14U)
  4801. #define CSL_EVETPCC_IECRH_I46_RESETVAL (0x00000000U)
  4802. #define CSL_EVETPCC_IECRH_I46_MAX (0x00000001U)
  4803. #define CSL_EVETPCC_IECRH_I55_MASK (0x00800000U)
  4804. #define CSL_EVETPCC_IECRH_I55_SHIFT (23U)
  4805. #define CSL_EVETPCC_IECRH_I55_RESETVAL (0x00000000U)
  4806. #define CSL_EVETPCC_IECRH_I55_MAX (0x00000001U)
  4807. #define CSL_EVETPCC_IECRH_I45_MASK (0x00002000U)
  4808. #define CSL_EVETPCC_IECRH_I45_SHIFT (13U)
  4809. #define CSL_EVETPCC_IECRH_I45_RESETVAL (0x00000000U)
  4810. #define CSL_EVETPCC_IECRH_I45_MAX (0x00000001U)
  4811. #define CSL_EVETPCC_IECRH_I58_MASK (0x04000000U)
  4812. #define CSL_EVETPCC_IECRH_I58_SHIFT (26U)
  4813. #define CSL_EVETPCC_IECRH_I58_RESETVAL (0x00000000U)
  4814. #define CSL_EVETPCC_IECRH_I58_MAX (0x00000001U)
  4815. #define CSL_EVETPCC_IECRH_I32_MASK (0x00000001U)
  4816. #define CSL_EVETPCC_IECRH_I32_SHIFT (0U)
  4817. #define CSL_EVETPCC_IECRH_I32_RESETVAL (0x00000000U)
  4818. #define CSL_EVETPCC_IECRH_I32_MAX (0x00000001U)
  4819. #define CSL_EVETPCC_IECRH_I44_MASK (0x00001000U)
  4820. #define CSL_EVETPCC_IECRH_I44_SHIFT (12U)
  4821. #define CSL_EVETPCC_IECRH_I44_RESETVAL (0x00000000U)
  4822. #define CSL_EVETPCC_IECRH_I44_MAX (0x00000001U)
  4823. #define CSL_EVETPCC_IECRH_I33_MASK (0x00000002U)
  4824. #define CSL_EVETPCC_IECRH_I33_SHIFT (1U)
  4825. #define CSL_EVETPCC_IECRH_I33_RESETVAL (0x00000000U)
  4826. #define CSL_EVETPCC_IECRH_I33_MAX (0x00000001U)
  4827. #define CSL_EVETPCC_IECRH_I57_MASK (0x02000000U)
  4828. #define CSL_EVETPCC_IECRH_I57_SHIFT (25U)
  4829. #define CSL_EVETPCC_IECRH_I57_RESETVAL (0x00000000U)
  4830. #define CSL_EVETPCC_IECRH_I57_MAX (0x00000001U)
  4831. #define CSL_EVETPCC_IECRH_I43_MASK (0x00000800U)
  4832. #define CSL_EVETPCC_IECRH_I43_SHIFT (11U)
  4833. #define CSL_EVETPCC_IECRH_I43_RESETVAL (0x00000000U)
  4834. #define CSL_EVETPCC_IECRH_I43_MAX (0x00000001U)
  4835. #define CSL_EVETPCC_IECRH_I60_MASK (0x10000000U)
  4836. #define CSL_EVETPCC_IECRH_I60_SHIFT (28U)
  4837. #define CSL_EVETPCC_IECRH_I60_RESETVAL (0x00000000U)
  4838. #define CSL_EVETPCC_IECRH_I60_MAX (0x00000001U)
  4839. #define CSL_EVETPCC_IECRH_I42_MASK (0x00000400U)
  4840. #define CSL_EVETPCC_IECRH_I42_SHIFT (10U)
  4841. #define CSL_EVETPCC_IECRH_I42_RESETVAL (0x00000000U)
  4842. #define CSL_EVETPCC_IECRH_I42_MAX (0x00000001U)
  4843. #define CSL_EVETPCC_IECRH_I59_MASK (0x08000000U)
  4844. #define CSL_EVETPCC_IECRH_I59_SHIFT (27U)
  4845. #define CSL_EVETPCC_IECRH_I59_RESETVAL (0x00000000U)
  4846. #define CSL_EVETPCC_IECRH_I59_MAX (0x00000001U)
  4847. #define CSL_EVETPCC_IECRH_I41_MASK (0x00000200U)
  4848. #define CSL_EVETPCC_IECRH_I41_SHIFT (9U)
  4849. #define CSL_EVETPCC_IECRH_I41_RESETVAL (0x00000000U)
  4850. #define CSL_EVETPCC_IECRH_I41_MAX (0x00000001U)
  4851. #define CSL_EVETPCC_IECRH_I62_MASK (0x40000000U)
  4852. #define CSL_EVETPCC_IECRH_I62_SHIFT (30U)
  4853. #define CSL_EVETPCC_IECRH_I62_RESETVAL (0x00000000U)
  4854. #define CSL_EVETPCC_IECRH_I62_MAX (0x00000001U)
  4855. #define CSL_EVETPCC_IECRH_I61_MASK (0x20000000U)
  4856. #define CSL_EVETPCC_IECRH_I61_SHIFT (29U)
  4857. #define CSL_EVETPCC_IECRH_I61_RESETVAL (0x00000000U)
  4858. #define CSL_EVETPCC_IECRH_I61_MAX (0x00000001U)
  4859. #define CSL_EVETPCC_IECRH_I52_MASK (0x00100000U)
  4860. #define CSL_EVETPCC_IECRH_I52_SHIFT (20U)
  4861. #define CSL_EVETPCC_IECRH_I52_RESETVAL (0x00000000U)
  4862. #define CSL_EVETPCC_IECRH_I52_MAX (0x00000001U)
  4863. #define CSL_EVETPCC_IECRH_I38_MASK (0x00000040U)
  4864. #define CSL_EVETPCC_IECRH_I38_SHIFT (6U)
  4865. #define CSL_EVETPCC_IECRH_I38_RESETVAL (0x00000000U)
  4866. #define CSL_EVETPCC_IECRH_I38_MAX (0x00000001U)
  4867. #define CSL_EVETPCC_IECRH_I40_MASK (0x00000100U)
  4868. #define CSL_EVETPCC_IECRH_I40_SHIFT (8U)
  4869. #define CSL_EVETPCC_IECRH_I40_RESETVAL (0x00000000U)
  4870. #define CSL_EVETPCC_IECRH_I40_MAX (0x00000001U)
  4871. #define CSL_EVETPCC_IECRH_I51_MASK (0x00080000U)
  4872. #define CSL_EVETPCC_IECRH_I51_SHIFT (19U)
  4873. #define CSL_EVETPCC_IECRH_I51_RESETVAL (0x00000000U)
  4874. #define CSL_EVETPCC_IECRH_I51_MAX (0x00000001U)
  4875. #define CSL_EVETPCC_IECRH_I50_MASK (0x00040000U)
  4876. #define CSL_EVETPCC_IECRH_I50_SHIFT (18U)
  4877. #define CSL_EVETPCC_IECRH_I50_RESETVAL (0x00000000U)
  4878. #define CSL_EVETPCC_IECRH_I50_MAX (0x00000001U)
  4879. #define CSL_EVETPCC_IECRH_I63_MASK (0x80000000U)
  4880. #define CSL_EVETPCC_IECRH_I63_SHIFT (31U)
  4881. #define CSL_EVETPCC_IECRH_I63_RESETVAL (0x00000000U)
  4882. #define CSL_EVETPCC_IECRH_I63_MAX (0x00000001U)
  4883. #define CSL_EVETPCC_IECRH_I39_MASK (0x00000080U)
  4884. #define CSL_EVETPCC_IECRH_I39_SHIFT (7U)
  4885. #define CSL_EVETPCC_IECRH_I39_RESETVAL (0x00000000U)
  4886. #define CSL_EVETPCC_IECRH_I39_MAX (0x00000001U)
  4887. #define CSL_EVETPCC_IECRH_I54_MASK (0x00400000U)
  4888. #define CSL_EVETPCC_IECRH_I54_SHIFT (22U)
  4889. #define CSL_EVETPCC_IECRH_I54_RESETVAL (0x00000000U)
  4890. #define CSL_EVETPCC_IECRH_I54_MAX (0x00000001U)
  4891. #define CSL_EVETPCC_IECRH_I36_MASK (0x00000010U)
  4892. #define CSL_EVETPCC_IECRH_I36_SHIFT (4U)
  4893. #define CSL_EVETPCC_IECRH_I36_RESETVAL (0x00000000U)
  4894. #define CSL_EVETPCC_IECRH_I36_MAX (0x00000001U)
  4895. #define CSL_EVETPCC_IECRH_I53_MASK (0x00200000U)
  4896. #define CSL_EVETPCC_IECRH_I53_SHIFT (21U)
  4897. #define CSL_EVETPCC_IECRH_I53_RESETVAL (0x00000000U)
  4898. #define CSL_EVETPCC_IECRH_I53_MAX (0x00000001U)
  4899. #define CSL_EVETPCC_IECRH_I49_MASK (0x00020000U)
  4900. #define CSL_EVETPCC_IECRH_I49_SHIFT (17U)
  4901. #define CSL_EVETPCC_IECRH_I49_RESETVAL (0x00000000U)
  4902. #define CSL_EVETPCC_IECRH_I49_MAX (0x00000001U)
  4903. #define CSL_EVETPCC_IECRH_I37_MASK (0x00000020U)
  4904. #define CSL_EVETPCC_IECRH_I37_SHIFT (5U)
  4905. #define CSL_EVETPCC_IECRH_I37_RESETVAL (0x00000000U)
  4906. #define CSL_EVETPCC_IECRH_I37_MAX (0x00000001U)
  4907. #define CSL_EVETPCC_IECRH_RESETVAL (0x00000000U)
  4908. /* IESR */
  4909. #define CSL_EVETPCC_IESR_I22_MASK (0x00400000U)
  4910. #define CSL_EVETPCC_IESR_I22_SHIFT (22U)
  4911. #define CSL_EVETPCC_IESR_I22_RESETVAL (0x00000000U)
  4912. #define CSL_EVETPCC_IESR_I22_MAX (0x00000001U)
  4913. #define CSL_EVETPCC_IESR_I11_MASK (0x00000800U)
  4914. #define CSL_EVETPCC_IESR_I11_SHIFT (11U)
  4915. #define CSL_EVETPCC_IESR_I11_RESETVAL (0x00000000U)
  4916. #define CSL_EVETPCC_IESR_I11_MAX (0x00000001U)
  4917. #define CSL_EVETPCC_IESR_I23_MASK (0x00800000U)
  4918. #define CSL_EVETPCC_IESR_I23_SHIFT (23U)
  4919. #define CSL_EVETPCC_IESR_I23_RESETVAL (0x00000000U)
  4920. #define CSL_EVETPCC_IESR_I23_MAX (0x00000001U)
  4921. #define CSL_EVETPCC_IESR_I0_MASK (0x00000001U)
  4922. #define CSL_EVETPCC_IESR_I0_SHIFT (0U)
  4923. #define CSL_EVETPCC_IESR_I0_RESETVAL (0x00000000U)
  4924. #define CSL_EVETPCC_IESR_I0_MAX (0x00000001U)
  4925. #define CSL_EVETPCC_IESR_I21_MASK (0x00200000U)
  4926. #define CSL_EVETPCC_IESR_I21_SHIFT (21U)
  4927. #define CSL_EVETPCC_IESR_I21_RESETVAL (0x00000000U)
  4928. #define CSL_EVETPCC_IESR_I21_MAX (0x00000001U)
  4929. #define CSL_EVETPCC_IESR_I10_MASK (0x00000400U)
  4930. #define CSL_EVETPCC_IESR_I10_SHIFT (10U)
  4931. #define CSL_EVETPCC_IESR_I10_RESETVAL (0x00000000U)
  4932. #define CSL_EVETPCC_IESR_I10_MAX (0x00000001U)
  4933. #define CSL_EVETPCC_IESR_I31_MASK (0x80000000U)
  4934. #define CSL_EVETPCC_IESR_I31_SHIFT (31U)
  4935. #define CSL_EVETPCC_IESR_I31_RESETVAL (0x00000000U)
  4936. #define CSL_EVETPCC_IESR_I31_MAX (0x00000001U)
  4937. #define CSL_EVETPCC_IESR_I8_MASK (0x00000100U)
  4938. #define CSL_EVETPCC_IESR_I8_SHIFT (8U)
  4939. #define CSL_EVETPCC_IESR_I8_RESETVAL (0x00000000U)
  4940. #define CSL_EVETPCC_IESR_I8_MAX (0x00000001U)
  4941. #define CSL_EVETPCC_IESR_I20_MASK (0x00100000U)
  4942. #define CSL_EVETPCC_IESR_I20_SHIFT (20U)
  4943. #define CSL_EVETPCC_IESR_I20_RESETVAL (0x00000000U)
  4944. #define CSL_EVETPCC_IESR_I20_MAX (0x00000001U)
  4945. #define CSL_EVETPCC_IESR_I9_MASK (0x00000200U)
  4946. #define CSL_EVETPCC_IESR_I9_SHIFT (9U)
  4947. #define CSL_EVETPCC_IESR_I9_RESETVAL (0x00000000U)
  4948. #define CSL_EVETPCC_IESR_I9_MAX (0x00000001U)
  4949. #define CSL_EVETPCC_IESR_I6_MASK (0x00000040U)
  4950. #define CSL_EVETPCC_IESR_I6_SHIFT (6U)
  4951. #define CSL_EVETPCC_IESR_I6_RESETVAL (0x00000000U)
  4952. #define CSL_EVETPCC_IESR_I6_MAX (0x00000001U)
  4953. #define CSL_EVETPCC_IESR_I30_MASK (0x40000000U)
  4954. #define CSL_EVETPCC_IESR_I30_SHIFT (30U)
  4955. #define CSL_EVETPCC_IESR_I30_RESETVAL (0x00000000U)
  4956. #define CSL_EVETPCC_IESR_I30_MAX (0x00000001U)
  4957. #define CSL_EVETPCC_IESR_I17_MASK (0x00020000U)
  4958. #define CSL_EVETPCC_IESR_I17_SHIFT (17U)
  4959. #define CSL_EVETPCC_IESR_I17_RESETVAL (0x00000000U)
  4960. #define CSL_EVETPCC_IESR_I17_MAX (0x00000001U)
  4961. #define CSL_EVETPCC_IESR_I7_MASK (0x00000080U)
  4962. #define CSL_EVETPCC_IESR_I7_SHIFT (7U)
  4963. #define CSL_EVETPCC_IESR_I7_RESETVAL (0x00000000U)
  4964. #define CSL_EVETPCC_IESR_I7_MAX (0x00000001U)
  4965. #define CSL_EVETPCC_IESR_I16_MASK (0x00010000U)
  4966. #define CSL_EVETPCC_IESR_I16_SHIFT (16U)
  4967. #define CSL_EVETPCC_IESR_I16_RESETVAL (0x00000000U)
  4968. #define CSL_EVETPCC_IESR_I16_MAX (0x00000001U)
  4969. #define CSL_EVETPCC_IESR_I28_MASK (0x10000000U)
  4970. #define CSL_EVETPCC_IESR_I28_SHIFT (28U)
  4971. #define CSL_EVETPCC_IESR_I28_RESETVAL (0x00000000U)
  4972. #define CSL_EVETPCC_IESR_I28_MAX (0x00000001U)
  4973. #define CSL_EVETPCC_IESR_I4_MASK (0x00000010U)
  4974. #define CSL_EVETPCC_IESR_I4_SHIFT (4U)
  4975. #define CSL_EVETPCC_IESR_I4_RESETVAL (0x00000000U)
  4976. #define CSL_EVETPCC_IESR_I4_MAX (0x00000001U)
  4977. #define CSL_EVETPCC_IESR_I29_MASK (0x20000000U)
  4978. #define CSL_EVETPCC_IESR_I29_SHIFT (29U)
  4979. #define CSL_EVETPCC_IESR_I29_RESETVAL (0x00000000U)
  4980. #define CSL_EVETPCC_IESR_I29_MAX (0x00000001U)
  4981. #define CSL_EVETPCC_IESR_I19_MASK (0x00080000U)
  4982. #define CSL_EVETPCC_IESR_I19_SHIFT (19U)
  4983. #define CSL_EVETPCC_IESR_I19_RESETVAL (0x00000000U)
  4984. #define CSL_EVETPCC_IESR_I19_MAX (0x00000001U)
  4985. #define CSL_EVETPCC_IESR_I5_MASK (0x00000020U)
  4986. #define CSL_EVETPCC_IESR_I5_SHIFT (5U)
  4987. #define CSL_EVETPCC_IESR_I5_RESETVAL (0x00000000U)
  4988. #define CSL_EVETPCC_IESR_I5_MAX (0x00000001U)
  4989. #define CSL_EVETPCC_IESR_I18_MASK (0x00040000U)
  4990. #define CSL_EVETPCC_IESR_I18_SHIFT (18U)
  4991. #define CSL_EVETPCC_IESR_I18_RESETVAL (0x00000000U)
  4992. #define CSL_EVETPCC_IESR_I18_MAX (0x00000001U)
  4993. #define CSL_EVETPCC_IESR_I26_MASK (0x04000000U)
  4994. #define CSL_EVETPCC_IESR_I26_SHIFT (26U)
  4995. #define CSL_EVETPCC_IESR_I26_RESETVAL (0x00000000U)
  4996. #define CSL_EVETPCC_IESR_I26_MAX (0x00000001U)
  4997. #define CSL_EVETPCC_IESR_I2_MASK (0x00000004U)
  4998. #define CSL_EVETPCC_IESR_I2_SHIFT (2U)
  4999. #define CSL_EVETPCC_IESR_I2_RESETVAL (0x00000000U)
  5000. #define CSL_EVETPCC_IESR_I2_MAX (0x00000001U)
  5001. #define CSL_EVETPCC_IESR_I13_MASK (0x00002000U)
  5002. #define CSL_EVETPCC_IESR_I13_SHIFT (13U)
  5003. #define CSL_EVETPCC_IESR_I13_RESETVAL (0x00000000U)
  5004. #define CSL_EVETPCC_IESR_I13_MAX (0x00000001U)
  5005. #define CSL_EVETPCC_IESR_I3_MASK (0x00000008U)
  5006. #define CSL_EVETPCC_IESR_I3_SHIFT (3U)
  5007. #define CSL_EVETPCC_IESR_I3_RESETVAL (0x00000000U)
  5008. #define CSL_EVETPCC_IESR_I3_MAX (0x00000001U)
  5009. #define CSL_EVETPCC_IESR_I27_MASK (0x08000000U)
  5010. #define CSL_EVETPCC_IESR_I27_SHIFT (27U)
  5011. #define CSL_EVETPCC_IESR_I27_RESETVAL (0x00000000U)
  5012. #define CSL_EVETPCC_IESR_I27_MAX (0x00000001U)
  5013. #define CSL_EVETPCC_IESR_I12_MASK (0x00001000U)
  5014. #define CSL_EVETPCC_IESR_I12_SHIFT (12U)
  5015. #define CSL_EVETPCC_IESR_I12_RESETVAL (0x00000000U)
  5016. #define CSL_EVETPCC_IESR_I12_MAX (0x00000001U)
  5017. #define CSL_EVETPCC_IESR_I24_MASK (0x01000000U)
  5018. #define CSL_EVETPCC_IESR_I24_SHIFT (24U)
  5019. #define CSL_EVETPCC_IESR_I24_RESETVAL (0x00000000U)
  5020. #define CSL_EVETPCC_IESR_I24_MAX (0x00000001U)
  5021. #define CSL_EVETPCC_IESR_I15_MASK (0x00008000U)
  5022. #define CSL_EVETPCC_IESR_I15_SHIFT (15U)
  5023. #define CSL_EVETPCC_IESR_I15_RESETVAL (0x00000000U)
  5024. #define CSL_EVETPCC_IESR_I15_MAX (0x00000001U)
  5025. #define CSL_EVETPCC_IESR_I1_MASK (0x00000002U)
  5026. #define CSL_EVETPCC_IESR_I1_SHIFT (1U)
  5027. #define CSL_EVETPCC_IESR_I1_RESETVAL (0x00000000U)
  5028. #define CSL_EVETPCC_IESR_I1_MAX (0x00000001U)
  5029. #define CSL_EVETPCC_IESR_I25_MASK (0x02000000U)
  5030. #define CSL_EVETPCC_IESR_I25_SHIFT (25U)
  5031. #define CSL_EVETPCC_IESR_I25_RESETVAL (0x00000000U)
  5032. #define CSL_EVETPCC_IESR_I25_MAX (0x00000001U)
  5033. #define CSL_EVETPCC_IESR_I14_MASK (0x00004000U)
  5034. #define CSL_EVETPCC_IESR_I14_SHIFT (14U)
  5035. #define CSL_EVETPCC_IESR_I14_RESETVAL (0x00000000U)
  5036. #define CSL_EVETPCC_IESR_I14_MAX (0x00000001U)
  5037. #define CSL_EVETPCC_IESR_RESETVAL (0x00000000U)
  5038. /* IESRH */
  5039. #define CSL_EVETPCC_IESRH_I52_MASK (0x00100000U)
  5040. #define CSL_EVETPCC_IESRH_I52_SHIFT (20U)
  5041. #define CSL_EVETPCC_IESRH_I52_RESETVAL (0x00000000U)
  5042. #define CSL_EVETPCC_IESRH_I52_MAX (0x00000001U)
  5043. #define CSL_EVETPCC_IESRH_I41_MASK (0x00000200U)
  5044. #define CSL_EVETPCC_IESRH_I41_SHIFT (9U)
  5045. #define CSL_EVETPCC_IESRH_I41_RESETVAL (0x00000000U)
  5046. #define CSL_EVETPCC_IESRH_I41_MAX (0x00000001U)
  5047. #define CSL_EVETPCC_IESRH_I53_MASK (0x00200000U)
  5048. #define CSL_EVETPCC_IESRH_I53_SHIFT (21U)
  5049. #define CSL_EVETPCC_IESRH_I53_RESETVAL (0x00000000U)
  5050. #define CSL_EVETPCC_IESRH_I53_MAX (0x00000001U)
  5051. #define CSL_EVETPCC_IESRH_I42_MASK (0x00000400U)
  5052. #define CSL_EVETPCC_IESRH_I42_SHIFT (10U)
  5053. #define CSL_EVETPCC_IESRH_I42_RESETVAL (0x00000000U)
  5054. #define CSL_EVETPCC_IESRH_I42_MAX (0x00000001U)
  5055. #define CSL_EVETPCC_IESRH_I54_MASK (0x00400000U)
  5056. #define CSL_EVETPCC_IESRH_I54_SHIFT (22U)
  5057. #define CSL_EVETPCC_IESRH_I54_RESETVAL (0x00000000U)
  5058. #define CSL_EVETPCC_IESRH_I54_MAX (0x00000001U)
  5059. #define CSL_EVETPCC_IESRH_I43_MASK (0x00000800U)
  5060. #define CSL_EVETPCC_IESRH_I43_SHIFT (11U)
  5061. #define CSL_EVETPCC_IESRH_I43_RESETVAL (0x00000000U)
  5062. #define CSL_EVETPCC_IESRH_I43_MAX (0x00000001U)
  5063. #define CSL_EVETPCC_IESRH_I55_MASK (0x00800000U)
  5064. #define CSL_EVETPCC_IESRH_I55_SHIFT (23U)
  5065. #define CSL_EVETPCC_IESRH_I55_RESETVAL (0x00000000U)
  5066. #define CSL_EVETPCC_IESRH_I55_MAX (0x00000001U)
  5067. #define CSL_EVETPCC_IESRH_I44_MASK (0x00001000U)
  5068. #define CSL_EVETPCC_IESRH_I44_SHIFT (12U)
  5069. #define CSL_EVETPCC_IESRH_I44_RESETVAL (0x00000000U)
  5070. #define CSL_EVETPCC_IESRH_I44_MAX (0x00000001U)
  5071. #define CSL_EVETPCC_IESRH_I33_MASK (0x00000002U)
  5072. #define CSL_EVETPCC_IESRH_I33_SHIFT (1U)
  5073. #define CSL_EVETPCC_IESRH_I33_RESETVAL (0x00000000U)
  5074. #define CSL_EVETPCC_IESRH_I33_MAX (0x00000001U)
  5075. #define CSL_EVETPCC_IESRH_I56_MASK (0x01000000U)
  5076. #define CSL_EVETPCC_IESRH_I56_SHIFT (24U)
  5077. #define CSL_EVETPCC_IESRH_I56_RESETVAL (0x00000000U)
  5078. #define CSL_EVETPCC_IESRH_I56_MAX (0x00000001U)
  5079. #define CSL_EVETPCC_IESRH_I45_MASK (0x00002000U)
  5080. #define CSL_EVETPCC_IESRH_I45_SHIFT (13U)
  5081. #define CSL_EVETPCC_IESRH_I45_RESETVAL (0x00000000U)
  5082. #define CSL_EVETPCC_IESRH_I45_MAX (0x00000001U)
  5083. #define CSL_EVETPCC_IESRH_I57_MASK (0x02000000U)
  5084. #define CSL_EVETPCC_IESRH_I57_SHIFT (25U)
  5085. #define CSL_EVETPCC_IESRH_I57_RESETVAL (0x00000000U)
  5086. #define CSL_EVETPCC_IESRH_I57_MAX (0x00000001U)
  5087. #define CSL_EVETPCC_IESRH_I32_MASK (0x00000001U)
  5088. #define CSL_EVETPCC_IESRH_I32_SHIFT (0U)
  5089. #define CSL_EVETPCC_IESRH_I32_RESETVAL (0x00000000U)
  5090. #define CSL_EVETPCC_IESRH_I32_MAX (0x00000001U)
  5091. #define CSL_EVETPCC_IESRH_I46_MASK (0x00004000U)
  5092. #define CSL_EVETPCC_IESRH_I46_SHIFT (14U)
  5093. #define CSL_EVETPCC_IESRH_I46_RESETVAL (0x00000000U)
  5094. #define CSL_EVETPCC_IESRH_I46_MAX (0x00000001U)
  5095. #define CSL_EVETPCC_IESRH_I35_MASK (0x00000008U)
  5096. #define CSL_EVETPCC_IESRH_I35_SHIFT (3U)
  5097. #define CSL_EVETPCC_IESRH_I35_RESETVAL (0x00000000U)
  5098. #define CSL_EVETPCC_IESRH_I35_MAX (0x00000001U)
  5099. #define CSL_EVETPCC_IESRH_I58_MASK (0x04000000U)
  5100. #define CSL_EVETPCC_IESRH_I58_SHIFT (26U)
  5101. #define CSL_EVETPCC_IESRH_I58_RESETVAL (0x00000000U)
  5102. #define CSL_EVETPCC_IESRH_I58_MAX (0x00000001U)
  5103. #define CSL_EVETPCC_IESRH_I47_MASK (0x00008000U)
  5104. #define CSL_EVETPCC_IESRH_I47_SHIFT (15U)
  5105. #define CSL_EVETPCC_IESRH_I47_RESETVAL (0x00000000U)
  5106. #define CSL_EVETPCC_IESRH_I47_MAX (0x00000001U)
  5107. #define CSL_EVETPCC_IESRH_I34_MASK (0x00000004U)
  5108. #define CSL_EVETPCC_IESRH_I34_SHIFT (2U)
  5109. #define CSL_EVETPCC_IESRH_I34_RESETVAL (0x00000000U)
  5110. #define CSL_EVETPCC_IESRH_I34_MAX (0x00000001U)
  5111. #define CSL_EVETPCC_IESRH_I59_MASK (0x08000000U)
  5112. #define CSL_EVETPCC_IESRH_I59_SHIFT (27U)
  5113. #define CSL_EVETPCC_IESRH_I59_RESETVAL (0x00000000U)
  5114. #define CSL_EVETPCC_IESRH_I59_MAX (0x00000001U)
  5115. #define CSL_EVETPCC_IESRH_I48_MASK (0x00010000U)
  5116. #define CSL_EVETPCC_IESRH_I48_SHIFT (16U)
  5117. #define CSL_EVETPCC_IESRH_I48_RESETVAL (0x00000000U)
  5118. #define CSL_EVETPCC_IESRH_I48_MAX (0x00000001U)
  5119. #define CSL_EVETPCC_IESRH_I60_MASK (0x10000000U)
  5120. #define CSL_EVETPCC_IESRH_I60_SHIFT (28U)
  5121. #define CSL_EVETPCC_IESRH_I60_RESETVAL (0x00000000U)
  5122. #define CSL_EVETPCC_IESRH_I60_MAX (0x00000001U)
  5123. #define CSL_EVETPCC_IESRH_I37_MASK (0x00000020U)
  5124. #define CSL_EVETPCC_IESRH_I37_SHIFT (5U)
  5125. #define CSL_EVETPCC_IESRH_I37_RESETVAL (0x00000000U)
  5126. #define CSL_EVETPCC_IESRH_I37_MAX (0x00000001U)
  5127. #define CSL_EVETPCC_IESRH_I49_MASK (0x00020000U)
  5128. #define CSL_EVETPCC_IESRH_I49_SHIFT (17U)
  5129. #define CSL_EVETPCC_IESRH_I49_RESETVAL (0x00000000U)
  5130. #define CSL_EVETPCC_IESRH_I49_MAX (0x00000001U)
  5131. #define CSL_EVETPCC_IESRH_I36_MASK (0x00000010U)
  5132. #define CSL_EVETPCC_IESRH_I36_SHIFT (4U)
  5133. #define CSL_EVETPCC_IESRH_I36_RESETVAL (0x00000000U)
  5134. #define CSL_EVETPCC_IESRH_I36_MAX (0x00000001U)
  5135. #define CSL_EVETPCC_IESRH_I50_MASK (0x00040000U)
  5136. #define CSL_EVETPCC_IESRH_I50_SHIFT (18U)
  5137. #define CSL_EVETPCC_IESRH_I50_RESETVAL (0x00000000U)
  5138. #define CSL_EVETPCC_IESRH_I50_MAX (0x00000001U)
  5139. #define CSL_EVETPCC_IESRH_I39_MASK (0x00000080U)
  5140. #define CSL_EVETPCC_IESRH_I39_SHIFT (7U)
  5141. #define CSL_EVETPCC_IESRH_I39_RESETVAL (0x00000000U)
  5142. #define CSL_EVETPCC_IESRH_I39_MAX (0x00000001U)
  5143. #define CSL_EVETPCC_IESRH_I38_MASK (0x00000040U)
  5144. #define CSL_EVETPCC_IESRH_I38_SHIFT (6U)
  5145. #define CSL_EVETPCC_IESRH_I38_RESETVAL (0x00000000U)
  5146. #define CSL_EVETPCC_IESRH_I38_MAX (0x00000001U)
  5147. #define CSL_EVETPCC_IESRH_I63_MASK (0x80000000U)
  5148. #define CSL_EVETPCC_IESRH_I63_SHIFT (31U)
  5149. #define CSL_EVETPCC_IESRH_I63_RESETVAL (0x00000000U)
  5150. #define CSL_EVETPCC_IESRH_I63_MAX (0x00000001U)
  5151. #define CSL_EVETPCC_IESRH_I62_MASK (0x40000000U)
  5152. #define CSL_EVETPCC_IESRH_I62_SHIFT (30U)
  5153. #define CSL_EVETPCC_IESRH_I62_RESETVAL (0x00000000U)
  5154. #define CSL_EVETPCC_IESRH_I62_MAX (0x00000001U)
  5155. #define CSL_EVETPCC_IESRH_I40_MASK (0x00000100U)
  5156. #define CSL_EVETPCC_IESRH_I40_SHIFT (8U)
  5157. #define CSL_EVETPCC_IESRH_I40_RESETVAL (0x00000000U)
  5158. #define CSL_EVETPCC_IESRH_I40_MAX (0x00000001U)
  5159. #define CSL_EVETPCC_IESRH_I61_MASK (0x20000000U)
  5160. #define CSL_EVETPCC_IESRH_I61_SHIFT (29U)
  5161. #define CSL_EVETPCC_IESRH_I61_RESETVAL (0x00000000U)
  5162. #define CSL_EVETPCC_IESRH_I61_MAX (0x00000001U)
  5163. #define CSL_EVETPCC_IESRH_I51_MASK (0x00080000U)
  5164. #define CSL_EVETPCC_IESRH_I51_SHIFT (19U)
  5165. #define CSL_EVETPCC_IESRH_I51_RESETVAL (0x00000000U)
  5166. #define CSL_EVETPCC_IESRH_I51_MAX (0x00000001U)
  5167. #define CSL_EVETPCC_IESRH_RESETVAL (0x00000000U)
  5168. /* IPR */
  5169. #define CSL_EVETPCC_IPR_I15_MASK (0x00008000U)
  5170. #define CSL_EVETPCC_IPR_I15_SHIFT (15U)
  5171. #define CSL_EVETPCC_IPR_I15_RESETVAL (0x00000000U)
  5172. #define CSL_EVETPCC_IPR_I15_MAX (0x00000001U)
  5173. #define CSL_EVETPCC_IPR_I27_MASK (0x08000000U)
  5174. #define CSL_EVETPCC_IPR_I27_SHIFT (27U)
  5175. #define CSL_EVETPCC_IPR_I27_RESETVAL (0x00000000U)
  5176. #define CSL_EVETPCC_IPR_I27_MAX (0x00000001U)
  5177. #define CSL_EVETPCC_IPR_I3_MASK (0x00000008U)
  5178. #define CSL_EVETPCC_IPR_I3_SHIFT (3U)
  5179. #define CSL_EVETPCC_IPR_I3_RESETVAL (0x00000000U)
  5180. #define CSL_EVETPCC_IPR_I3_MAX (0x00000001U)
  5181. #define CSL_EVETPCC_IPR_I14_MASK (0x00004000U)
  5182. #define CSL_EVETPCC_IPR_I14_SHIFT (14U)
  5183. #define CSL_EVETPCC_IPR_I14_RESETVAL (0x00000000U)
  5184. #define CSL_EVETPCC_IPR_I14_MAX (0x00000001U)
  5185. #define CSL_EVETPCC_IPR_I2_MASK (0x00000004U)
  5186. #define CSL_EVETPCC_IPR_I2_SHIFT (2U)
  5187. #define CSL_EVETPCC_IPR_I2_RESETVAL (0x00000000U)
  5188. #define CSL_EVETPCC_IPR_I2_MAX (0x00000001U)
  5189. #define CSL_EVETPCC_IPR_I1_MASK (0x00000002U)
  5190. #define CSL_EVETPCC_IPR_I1_SHIFT (1U)
  5191. #define CSL_EVETPCC_IPR_I1_RESETVAL (0x00000000U)
  5192. #define CSL_EVETPCC_IPR_I1_MAX (0x00000001U)
  5193. #define CSL_EVETPCC_IPR_I13_MASK (0x00002000U)
  5194. #define CSL_EVETPCC_IPR_I13_SHIFT (13U)
  5195. #define CSL_EVETPCC_IPR_I13_RESETVAL (0x00000000U)
  5196. #define CSL_EVETPCC_IPR_I13_MAX (0x00000001U)
  5197. #define CSL_EVETPCC_IPR_I28_MASK (0x10000000U)
  5198. #define CSL_EVETPCC_IPR_I28_SHIFT (28U)
  5199. #define CSL_EVETPCC_IPR_I28_RESETVAL (0x00000000U)
  5200. #define CSL_EVETPCC_IPR_I28_MAX (0x00000001U)
  5201. #define CSL_EVETPCC_IPR_I17_MASK (0x00020000U)
  5202. #define CSL_EVETPCC_IPR_I17_SHIFT (17U)
  5203. #define CSL_EVETPCC_IPR_I17_RESETVAL (0x00000000U)
  5204. #define CSL_EVETPCC_IPR_I17_MAX (0x00000001U)
  5205. #define CSL_EVETPCC_IPR_I0_MASK (0x00000001U)
  5206. #define CSL_EVETPCC_IPR_I0_SHIFT (0U)
  5207. #define CSL_EVETPCC_IPR_I0_RESETVAL (0x00000000U)
  5208. #define CSL_EVETPCC_IPR_I0_MAX (0x00000001U)
  5209. #define CSL_EVETPCC_IPR_I12_MASK (0x00001000U)
  5210. #define CSL_EVETPCC_IPR_I12_SHIFT (12U)
  5211. #define CSL_EVETPCC_IPR_I12_RESETVAL (0x00000000U)
  5212. #define CSL_EVETPCC_IPR_I12_MAX (0x00000001U)
  5213. #define CSL_EVETPCC_IPR_I29_MASK (0x20000000U)
  5214. #define CSL_EVETPCC_IPR_I29_SHIFT (29U)
  5215. #define CSL_EVETPCC_IPR_I29_RESETVAL (0x00000000U)
  5216. #define CSL_EVETPCC_IPR_I29_MAX (0x00000001U)
  5217. #define CSL_EVETPCC_IPR_I6_MASK (0x00000040U)
  5218. #define CSL_EVETPCC_IPR_I6_SHIFT (6U)
  5219. #define CSL_EVETPCC_IPR_I6_RESETVAL (0x00000000U)
  5220. #define CSL_EVETPCC_IPR_I6_MAX (0x00000001U)
  5221. #define CSL_EVETPCC_IPR_I26_MASK (0x04000000U)
  5222. #define CSL_EVETPCC_IPR_I26_SHIFT (26U)
  5223. #define CSL_EVETPCC_IPR_I26_RESETVAL (0x00000000U)
  5224. #define CSL_EVETPCC_IPR_I26_MAX (0x00000001U)
  5225. #define CSL_EVETPCC_IPR_I5_MASK (0x00000020U)
  5226. #define CSL_EVETPCC_IPR_I5_SHIFT (5U)
  5227. #define CSL_EVETPCC_IPR_I5_RESETVAL (0x00000000U)
  5228. #define CSL_EVETPCC_IPR_I5_MAX (0x00000001U)
  5229. #define CSL_EVETPCC_IPR_I4_MASK (0x00000010U)
  5230. #define CSL_EVETPCC_IPR_I4_SHIFT (4U)
  5231. #define CSL_EVETPCC_IPR_I4_RESETVAL (0x00000000U)
  5232. #define CSL_EVETPCC_IPR_I4_MAX (0x00000001U)
  5233. #define CSL_EVETPCC_IPR_I16_MASK (0x00010000U)
  5234. #define CSL_EVETPCC_IPR_I16_SHIFT (16U)
  5235. #define CSL_EVETPCC_IPR_I16_RESETVAL (0x00000000U)
  5236. #define CSL_EVETPCC_IPR_I16_MAX (0x00000001U)
  5237. #define CSL_EVETPCC_IPR_I23_MASK (0x00800000U)
  5238. #define CSL_EVETPCC_IPR_I23_SHIFT (23U)
  5239. #define CSL_EVETPCC_IPR_I23_RESETVAL (0x00000000U)
  5240. #define CSL_EVETPCC_IPR_I23_MAX (0x00000001U)
  5241. #define CSL_EVETPCC_IPR_I7_MASK (0x00000080U)
  5242. #define CSL_EVETPCC_IPR_I7_SHIFT (7U)
  5243. #define CSL_EVETPCC_IPR_I7_RESETVAL (0x00000000U)
  5244. #define CSL_EVETPCC_IPR_I7_MAX (0x00000001U)
  5245. #define CSL_EVETPCC_IPR_I22_MASK (0x00400000U)
  5246. #define CSL_EVETPCC_IPR_I22_SHIFT (22U)
  5247. #define CSL_EVETPCC_IPR_I22_RESETVAL (0x00000000U)
  5248. #define CSL_EVETPCC_IPR_I22_MAX (0x00000001U)
  5249. #define CSL_EVETPCC_IPR_I25_MASK (0x02000000U)
  5250. #define CSL_EVETPCC_IPR_I25_SHIFT (25U)
  5251. #define CSL_EVETPCC_IPR_I25_RESETVAL (0x00000000U)
  5252. #define CSL_EVETPCC_IPR_I25_MAX (0x00000001U)
  5253. #define CSL_EVETPCC_IPR_I24_MASK (0x01000000U)
  5254. #define CSL_EVETPCC_IPR_I24_SHIFT (24U)
  5255. #define CSL_EVETPCC_IPR_I24_RESETVAL (0x00000000U)
  5256. #define CSL_EVETPCC_IPR_I24_MAX (0x00000001U)
  5257. #define CSL_EVETPCC_IPR_I19_MASK (0x00080000U)
  5258. #define CSL_EVETPCC_IPR_I19_SHIFT (19U)
  5259. #define CSL_EVETPCC_IPR_I19_RESETVAL (0x00000000U)
  5260. #define CSL_EVETPCC_IPR_I19_MAX (0x00000001U)
  5261. #define CSL_EVETPCC_IPR_I30_MASK (0x40000000U)
  5262. #define CSL_EVETPCC_IPR_I30_SHIFT (30U)
  5263. #define CSL_EVETPCC_IPR_I30_RESETVAL (0x00000000U)
  5264. #define CSL_EVETPCC_IPR_I30_MAX (0x00000001U)
  5265. #define CSL_EVETPCC_IPR_I11_MASK (0x00000800U)
  5266. #define CSL_EVETPCC_IPR_I11_SHIFT (11U)
  5267. #define CSL_EVETPCC_IPR_I11_RESETVAL (0x00000000U)
  5268. #define CSL_EVETPCC_IPR_I11_MAX (0x00000001U)
  5269. #define CSL_EVETPCC_IPR_I18_MASK (0x00040000U)
  5270. #define CSL_EVETPCC_IPR_I18_SHIFT (18U)
  5271. #define CSL_EVETPCC_IPR_I18_RESETVAL (0x00000000U)
  5272. #define CSL_EVETPCC_IPR_I18_MAX (0x00000001U)
  5273. #define CSL_EVETPCC_IPR_I31_MASK (0x80000000U)
  5274. #define CSL_EVETPCC_IPR_I31_SHIFT (31U)
  5275. #define CSL_EVETPCC_IPR_I31_RESETVAL (0x00000000U)
  5276. #define CSL_EVETPCC_IPR_I31_MAX (0x00000001U)
  5277. #define CSL_EVETPCC_IPR_I10_MASK (0x00000400U)
  5278. #define CSL_EVETPCC_IPR_I10_SHIFT (10U)
  5279. #define CSL_EVETPCC_IPR_I10_RESETVAL (0x00000000U)
  5280. #define CSL_EVETPCC_IPR_I10_MAX (0x00000001U)
  5281. #define CSL_EVETPCC_IPR_I9_MASK (0x00000200U)
  5282. #define CSL_EVETPCC_IPR_I9_SHIFT (9U)
  5283. #define CSL_EVETPCC_IPR_I9_RESETVAL (0x00000000U)
  5284. #define CSL_EVETPCC_IPR_I9_MAX (0x00000001U)
  5285. #define CSL_EVETPCC_IPR_I21_MASK (0x00200000U)
  5286. #define CSL_EVETPCC_IPR_I21_SHIFT (21U)
  5287. #define CSL_EVETPCC_IPR_I21_RESETVAL (0x00000000U)
  5288. #define CSL_EVETPCC_IPR_I21_MAX (0x00000001U)
  5289. #define CSL_EVETPCC_IPR_I8_MASK (0x00000100U)
  5290. #define CSL_EVETPCC_IPR_I8_SHIFT (8U)
  5291. #define CSL_EVETPCC_IPR_I8_RESETVAL (0x00000000U)
  5292. #define CSL_EVETPCC_IPR_I8_MAX (0x00000001U)
  5293. #define CSL_EVETPCC_IPR_I20_MASK (0x00100000U)
  5294. #define CSL_EVETPCC_IPR_I20_SHIFT (20U)
  5295. #define CSL_EVETPCC_IPR_I20_RESETVAL (0x00000000U)
  5296. #define CSL_EVETPCC_IPR_I20_MAX (0x00000001U)
  5297. #define CSL_EVETPCC_IPR_RESETVAL (0x00000000U)
  5298. /* IPRH */
  5299. #define CSL_EVETPCC_IPRH_I53_MASK (0x00200000U)
  5300. #define CSL_EVETPCC_IPRH_I53_SHIFT (21U)
  5301. #define CSL_EVETPCC_IPRH_I53_RESETVAL (0x00000000U)
  5302. #define CSL_EVETPCC_IPRH_I53_MAX (0x00000001U)
  5303. #define CSL_EVETPCC_IPRH_I41_MASK (0x00000200U)
  5304. #define CSL_EVETPCC_IPRH_I41_SHIFT (9U)
  5305. #define CSL_EVETPCC_IPRH_I41_RESETVAL (0x00000000U)
  5306. #define CSL_EVETPCC_IPRH_I41_MAX (0x00000001U)
  5307. #define CSL_EVETPCC_IPRH_I52_MASK (0x00100000U)
  5308. #define CSL_EVETPCC_IPRH_I52_SHIFT (20U)
  5309. #define CSL_EVETPCC_IPRH_I52_RESETVAL (0x00000000U)
  5310. #define CSL_EVETPCC_IPRH_I52_MAX (0x00000001U)
  5311. #define CSL_EVETPCC_IPRH_I40_MASK (0x00000100U)
  5312. #define CSL_EVETPCC_IPRH_I40_SHIFT (8U)
  5313. #define CSL_EVETPCC_IPRH_I40_RESETVAL (0x00000000U)
  5314. #define CSL_EVETPCC_IPRH_I40_MAX (0x00000001U)
  5315. #define CSL_EVETPCC_IPRH_I51_MASK (0x00080000U)
  5316. #define CSL_EVETPCC_IPRH_I51_SHIFT (19U)
  5317. #define CSL_EVETPCC_IPRH_I51_RESETVAL (0x00000000U)
  5318. #define CSL_EVETPCC_IPRH_I51_MAX (0x00000001U)
  5319. #define CSL_EVETPCC_IPRH_I39_MASK (0x00000080U)
  5320. #define CSL_EVETPCC_IPRH_I39_SHIFT (7U)
  5321. #define CSL_EVETPCC_IPRH_I39_RESETVAL (0x00000000U)
  5322. #define CSL_EVETPCC_IPRH_I39_MAX (0x00000001U)
  5323. #define CSL_EVETPCC_IPRH_I32_MASK (0x00000001U)
  5324. #define CSL_EVETPCC_IPRH_I32_SHIFT (0U)
  5325. #define CSL_EVETPCC_IPRH_I32_RESETVAL (0x00000000U)
  5326. #define CSL_EVETPCC_IPRH_I32_MAX (0x00000001U)
  5327. #define CSL_EVETPCC_IPRH_I50_MASK (0x00040000U)
  5328. #define CSL_EVETPCC_IPRH_I50_SHIFT (18U)
  5329. #define CSL_EVETPCC_IPRH_I50_RESETVAL (0x00000000U)
  5330. #define CSL_EVETPCC_IPRH_I50_MAX (0x00000001U)
  5331. #define CSL_EVETPCC_IPRH_I33_MASK (0x00000002U)
  5332. #define CSL_EVETPCC_IPRH_I33_SHIFT (1U)
  5333. #define CSL_EVETPCC_IPRH_I33_RESETVAL (0x00000000U)
  5334. #define CSL_EVETPCC_IPRH_I33_MAX (0x00000001U)
  5335. #define CSL_EVETPCC_IPRH_I34_MASK (0x00000004U)
  5336. #define CSL_EVETPCC_IPRH_I34_SHIFT (2U)
  5337. #define CSL_EVETPCC_IPRH_I34_RESETVAL (0x00000000U)
  5338. #define CSL_EVETPCC_IPRH_I34_MAX (0x00000001U)
  5339. #define CSL_EVETPCC_IPRH_I49_MASK (0x00020000U)
  5340. #define CSL_EVETPCC_IPRH_I49_SHIFT (17U)
  5341. #define CSL_EVETPCC_IPRH_I49_RESETVAL (0x00000000U)
  5342. #define CSL_EVETPCC_IPRH_I49_MAX (0x00000001U)
  5343. #define CSL_EVETPCC_IPRH_I60_MASK (0x10000000U)
  5344. #define CSL_EVETPCC_IPRH_I60_SHIFT (28U)
  5345. #define CSL_EVETPCC_IPRH_I60_RESETVAL (0x00000000U)
  5346. #define CSL_EVETPCC_IPRH_I60_MAX (0x00000001U)
  5347. #define CSL_EVETPCC_IPRH_I47_MASK (0x00008000U)
  5348. #define CSL_EVETPCC_IPRH_I47_SHIFT (15U)
  5349. #define CSL_EVETPCC_IPRH_I47_RESETVAL (0x00000000U)
  5350. #define CSL_EVETPCC_IPRH_I47_MAX (0x00000001U)
  5351. #define CSL_EVETPCC_IPRH_I35_MASK (0x00000008U)
  5352. #define CSL_EVETPCC_IPRH_I35_SHIFT (3U)
  5353. #define CSL_EVETPCC_IPRH_I35_RESETVAL (0x00000000U)
  5354. #define CSL_EVETPCC_IPRH_I35_MAX (0x00000001U)
  5355. #define CSL_EVETPCC_IPRH_I36_MASK (0x00000010U)
  5356. #define CSL_EVETPCC_IPRH_I36_SHIFT (4U)
  5357. #define CSL_EVETPCC_IPRH_I36_RESETVAL (0x00000000U)
  5358. #define CSL_EVETPCC_IPRH_I36_MAX (0x00000001U)
  5359. #define CSL_EVETPCC_IPRH_I59_MASK (0x08000000U)
  5360. #define CSL_EVETPCC_IPRH_I59_SHIFT (27U)
  5361. #define CSL_EVETPCC_IPRH_I59_RESETVAL (0x00000000U)
  5362. #define CSL_EVETPCC_IPRH_I59_MAX (0x00000001U)
  5363. #define CSL_EVETPCC_IPRH_I48_MASK (0x00010000U)
  5364. #define CSL_EVETPCC_IPRH_I48_SHIFT (16U)
  5365. #define CSL_EVETPCC_IPRH_I48_RESETVAL (0x00000000U)
  5366. #define CSL_EVETPCC_IPRH_I48_MAX (0x00000001U)
  5367. #define CSL_EVETPCC_IPRH_I37_MASK (0x00000020U)
  5368. #define CSL_EVETPCC_IPRH_I37_SHIFT (5U)
  5369. #define CSL_EVETPCC_IPRH_I37_RESETVAL (0x00000000U)
  5370. #define CSL_EVETPCC_IPRH_I37_MAX (0x00000001U)
  5371. #define CSL_EVETPCC_IPRH_I61_MASK (0x20000000U)
  5372. #define CSL_EVETPCC_IPRH_I61_SHIFT (29U)
  5373. #define CSL_EVETPCC_IPRH_I61_RESETVAL (0x00000000U)
  5374. #define CSL_EVETPCC_IPRH_I61_MAX (0x00000001U)
  5375. #define CSL_EVETPCC_IPRH_I38_MASK (0x00000040U)
  5376. #define CSL_EVETPCC_IPRH_I38_SHIFT (6U)
  5377. #define CSL_EVETPCC_IPRH_I38_RESETVAL (0x00000000U)
  5378. #define CSL_EVETPCC_IPRH_I38_MAX (0x00000001U)
  5379. #define CSL_EVETPCC_IPRH_I58_MASK (0x04000000U)
  5380. #define CSL_EVETPCC_IPRH_I58_SHIFT (26U)
  5381. #define CSL_EVETPCC_IPRH_I58_RESETVAL (0x00000000U)
  5382. #define CSL_EVETPCC_IPRH_I58_MAX (0x00000001U)
  5383. #define CSL_EVETPCC_IPRH_I46_MASK (0x00004000U)
  5384. #define CSL_EVETPCC_IPRH_I46_SHIFT (14U)
  5385. #define CSL_EVETPCC_IPRH_I46_RESETVAL (0x00000000U)
  5386. #define CSL_EVETPCC_IPRH_I46_MAX (0x00000001U)
  5387. #define CSL_EVETPCC_IPRH_I45_MASK (0x00002000U)
  5388. #define CSL_EVETPCC_IPRH_I45_SHIFT (13U)
  5389. #define CSL_EVETPCC_IPRH_I45_RESETVAL (0x00000000U)
  5390. #define CSL_EVETPCC_IPRH_I45_MAX (0x00000001U)
  5391. #define CSL_EVETPCC_IPRH_I57_MASK (0x02000000U)
  5392. #define CSL_EVETPCC_IPRH_I57_SHIFT (25U)
  5393. #define CSL_EVETPCC_IPRH_I57_RESETVAL (0x00000000U)
  5394. #define CSL_EVETPCC_IPRH_I57_MAX (0x00000001U)
  5395. #define CSL_EVETPCC_IPRH_I44_MASK (0x00001000U)
  5396. #define CSL_EVETPCC_IPRH_I44_SHIFT (12U)
  5397. #define CSL_EVETPCC_IPRH_I44_RESETVAL (0x00000000U)
  5398. #define CSL_EVETPCC_IPRH_I44_MAX (0x00000001U)
  5399. #define CSL_EVETPCC_IPRH_I56_MASK (0x01000000U)
  5400. #define CSL_EVETPCC_IPRH_I56_SHIFT (24U)
  5401. #define CSL_EVETPCC_IPRH_I56_RESETVAL (0x00000000U)
  5402. #define CSL_EVETPCC_IPRH_I56_MAX (0x00000001U)
  5403. #define CSL_EVETPCC_IPRH_I63_MASK (0x80000000U)
  5404. #define CSL_EVETPCC_IPRH_I63_SHIFT (31U)
  5405. #define CSL_EVETPCC_IPRH_I63_RESETVAL (0x00000000U)
  5406. #define CSL_EVETPCC_IPRH_I63_MAX (0x00000001U)
  5407. #define CSL_EVETPCC_IPRH_I43_MASK (0x00000800U)
  5408. #define CSL_EVETPCC_IPRH_I43_SHIFT (11U)
  5409. #define CSL_EVETPCC_IPRH_I43_RESETVAL (0x00000000U)
  5410. #define CSL_EVETPCC_IPRH_I43_MAX (0x00000001U)
  5411. #define CSL_EVETPCC_IPRH_I55_MASK (0x00800000U)
  5412. #define CSL_EVETPCC_IPRH_I55_SHIFT (23U)
  5413. #define CSL_EVETPCC_IPRH_I55_RESETVAL (0x00000000U)
  5414. #define CSL_EVETPCC_IPRH_I55_MAX (0x00000001U)
  5415. #define CSL_EVETPCC_IPRH_I62_MASK (0x40000000U)
  5416. #define CSL_EVETPCC_IPRH_I62_SHIFT (30U)
  5417. #define CSL_EVETPCC_IPRH_I62_RESETVAL (0x00000000U)
  5418. #define CSL_EVETPCC_IPRH_I62_MAX (0x00000001U)
  5419. #define CSL_EVETPCC_IPRH_I42_MASK (0x00000400U)
  5420. #define CSL_EVETPCC_IPRH_I42_SHIFT (10U)
  5421. #define CSL_EVETPCC_IPRH_I42_RESETVAL (0x00000000U)
  5422. #define CSL_EVETPCC_IPRH_I42_MAX (0x00000001U)
  5423. #define CSL_EVETPCC_IPRH_I54_MASK (0x00400000U)
  5424. #define CSL_EVETPCC_IPRH_I54_SHIFT (22U)
  5425. #define CSL_EVETPCC_IPRH_I54_RESETVAL (0x00000000U)
  5426. #define CSL_EVETPCC_IPRH_I54_MAX (0x00000001U)
  5427. #define CSL_EVETPCC_IPRH_RESETVAL (0x00000000U)
  5428. /* ICR */
  5429. #define CSL_EVETPCC_ICR_I17_MASK (0x00020000U)
  5430. #define CSL_EVETPCC_ICR_I17_SHIFT (17U)
  5431. #define CSL_EVETPCC_ICR_I17_RESETVAL (0x00000000U)
  5432. #define CSL_EVETPCC_ICR_I17_MAX (0x00000001U)
  5433. #define CSL_EVETPCC_ICR_I30_MASK (0x40000000U)
  5434. #define CSL_EVETPCC_ICR_I30_SHIFT (30U)
  5435. #define CSL_EVETPCC_ICR_I30_RESETVAL (0x00000000U)
  5436. #define CSL_EVETPCC_ICR_I30_MAX (0x00000001U)
  5437. #define CSL_EVETPCC_ICR_I7_MASK (0x00000080U)
  5438. #define CSL_EVETPCC_ICR_I7_SHIFT (7U)
  5439. #define CSL_EVETPCC_ICR_I7_RESETVAL (0x00000000U)
  5440. #define CSL_EVETPCC_ICR_I7_MAX (0x00000001U)
  5441. #define CSL_EVETPCC_ICR_I19_MASK (0x00080000U)
  5442. #define CSL_EVETPCC_ICR_I19_SHIFT (19U)
  5443. #define CSL_EVETPCC_ICR_I19_RESETVAL (0x00000000U)
  5444. #define CSL_EVETPCC_ICR_I19_MAX (0x00000001U)
  5445. #define CSL_EVETPCC_ICR_I16_MASK (0x00010000U)
  5446. #define CSL_EVETPCC_ICR_I16_SHIFT (16U)
  5447. #define CSL_EVETPCC_ICR_I16_RESETVAL (0x00000000U)
  5448. #define CSL_EVETPCC_ICR_I16_MAX (0x00000001U)
  5449. #define CSL_EVETPCC_ICR_I6_MASK (0x00000040U)
  5450. #define CSL_EVETPCC_ICR_I6_SHIFT (6U)
  5451. #define CSL_EVETPCC_ICR_I6_RESETVAL (0x00000000U)
  5452. #define CSL_EVETPCC_ICR_I6_MAX (0x00000001U)
  5453. #define CSL_EVETPCC_ICR_I31_MASK (0x80000000U)
  5454. #define CSL_EVETPCC_ICR_I31_SHIFT (31U)
  5455. #define CSL_EVETPCC_ICR_I31_RESETVAL (0x00000000U)
  5456. #define CSL_EVETPCC_ICR_I31_MAX (0x00000001U)
  5457. #define CSL_EVETPCC_ICR_I20_MASK (0x00100000U)
  5458. #define CSL_EVETPCC_ICR_I20_SHIFT (20U)
  5459. #define CSL_EVETPCC_ICR_I20_RESETVAL (0x00000000U)
  5460. #define CSL_EVETPCC_ICR_I20_MAX (0x00000001U)
  5461. #define CSL_EVETPCC_ICR_I18_MASK (0x00040000U)
  5462. #define CSL_EVETPCC_ICR_I18_SHIFT (18U)
  5463. #define CSL_EVETPCC_ICR_I18_RESETVAL (0x00000000U)
  5464. #define CSL_EVETPCC_ICR_I18_MAX (0x00000001U)
  5465. #define CSL_EVETPCC_ICR_I21_MASK (0x00200000U)
  5466. #define CSL_EVETPCC_ICR_I21_SHIFT (21U)
  5467. #define CSL_EVETPCC_ICR_I21_RESETVAL (0x00000000U)
  5468. #define CSL_EVETPCC_ICR_I21_MAX (0x00000001U)
  5469. #define CSL_EVETPCC_ICR_I8_MASK (0x00000100U)
  5470. #define CSL_EVETPCC_ICR_I8_SHIFT (8U)
  5471. #define CSL_EVETPCC_ICR_I8_RESETVAL (0x00000000U)
  5472. #define CSL_EVETPCC_ICR_I8_MAX (0x00000001U)
  5473. #define CSL_EVETPCC_ICR_I22_MASK (0x00400000U)
  5474. #define CSL_EVETPCC_ICR_I22_SHIFT (22U)
  5475. #define CSL_EVETPCC_ICR_I22_RESETVAL (0x00000000U)
  5476. #define CSL_EVETPCC_ICR_I22_MAX (0x00000001U)
  5477. #define CSL_EVETPCC_ICR_I13_MASK (0x00002000U)
  5478. #define CSL_EVETPCC_ICR_I13_SHIFT (13U)
  5479. #define CSL_EVETPCC_ICR_I13_RESETVAL (0x00000000U)
  5480. #define CSL_EVETPCC_ICR_I13_MAX (0x00000001U)
  5481. #define CSL_EVETPCC_ICR_I3_MASK (0x00000008U)
  5482. #define CSL_EVETPCC_ICR_I3_SHIFT (3U)
  5483. #define CSL_EVETPCC_ICR_I3_RESETVAL (0x00000000U)
  5484. #define CSL_EVETPCC_ICR_I3_MAX (0x00000001U)
  5485. #define CSL_EVETPCC_ICR_I23_MASK (0x00800000U)
  5486. #define CSL_EVETPCC_ICR_I23_SHIFT (23U)
  5487. #define CSL_EVETPCC_ICR_I23_RESETVAL (0x00000000U)
  5488. #define CSL_EVETPCC_ICR_I23_MAX (0x00000001U)
  5489. #define CSL_EVETPCC_ICR_I12_MASK (0x00001000U)
  5490. #define CSL_EVETPCC_ICR_I12_SHIFT (12U)
  5491. #define CSL_EVETPCC_ICR_I12_RESETVAL (0x00000000U)
  5492. #define CSL_EVETPCC_ICR_I12_MAX (0x00000001U)
  5493. #define CSL_EVETPCC_ICR_I2_MASK (0x00000004U)
  5494. #define CSL_EVETPCC_ICR_I2_SHIFT (2U)
  5495. #define CSL_EVETPCC_ICR_I2_RESETVAL (0x00000000U)
  5496. #define CSL_EVETPCC_ICR_I2_MAX (0x00000001U)
  5497. #define CSL_EVETPCC_ICR_I24_MASK (0x01000000U)
  5498. #define CSL_EVETPCC_ICR_I24_SHIFT (24U)
  5499. #define CSL_EVETPCC_ICR_I24_RESETVAL (0x00000000U)
  5500. #define CSL_EVETPCC_ICR_I24_MAX (0x00000001U)
  5501. #define CSL_EVETPCC_ICR_I15_MASK (0x00008000U)
  5502. #define CSL_EVETPCC_ICR_I15_SHIFT (15U)
  5503. #define CSL_EVETPCC_ICR_I15_RESETVAL (0x00000000U)
  5504. #define CSL_EVETPCC_ICR_I15_MAX (0x00000001U)
  5505. #define CSL_EVETPCC_ICR_I25_MASK (0x02000000U)
  5506. #define CSL_EVETPCC_ICR_I25_SHIFT (25U)
  5507. #define CSL_EVETPCC_ICR_I25_RESETVAL (0x00000000U)
  5508. #define CSL_EVETPCC_ICR_I25_MAX (0x00000001U)
  5509. #define CSL_EVETPCC_ICR_I5_MASK (0x00000020U)
  5510. #define CSL_EVETPCC_ICR_I5_SHIFT (5U)
  5511. #define CSL_EVETPCC_ICR_I5_RESETVAL (0x00000000U)
  5512. #define CSL_EVETPCC_ICR_I5_MAX (0x00000001U)
  5513. #define CSL_EVETPCC_ICR_I14_MASK (0x00004000U)
  5514. #define CSL_EVETPCC_ICR_I14_SHIFT (14U)
  5515. #define CSL_EVETPCC_ICR_I14_RESETVAL (0x00000000U)
  5516. #define CSL_EVETPCC_ICR_I14_MAX (0x00000001U)
  5517. #define CSL_EVETPCC_ICR_I4_MASK (0x00000010U)
  5518. #define CSL_EVETPCC_ICR_I4_SHIFT (4U)
  5519. #define CSL_EVETPCC_ICR_I4_RESETVAL (0x00000000U)
  5520. #define CSL_EVETPCC_ICR_I4_MAX (0x00000001U)
  5521. #define CSL_EVETPCC_ICR_I9_MASK (0x00000200U)
  5522. #define CSL_EVETPCC_ICR_I9_SHIFT (9U)
  5523. #define CSL_EVETPCC_ICR_I9_RESETVAL (0x00000000U)
  5524. #define CSL_EVETPCC_ICR_I9_MAX (0x00000001U)
  5525. #define CSL_EVETPCC_ICR_I27_MASK (0x08000000U)
  5526. #define CSL_EVETPCC_ICR_I27_SHIFT (27U)
  5527. #define CSL_EVETPCC_ICR_I27_RESETVAL (0x00000000U)
  5528. #define CSL_EVETPCC_ICR_I27_MAX (0x00000001U)
  5529. #define CSL_EVETPCC_ICR_I26_MASK (0x04000000U)
  5530. #define CSL_EVETPCC_ICR_I26_SHIFT (26U)
  5531. #define CSL_EVETPCC_ICR_I26_RESETVAL (0x00000000U)
  5532. #define CSL_EVETPCC_ICR_I26_MAX (0x00000001U)
  5533. #define CSL_EVETPCC_ICR_I11_MASK (0x00000800U)
  5534. #define CSL_EVETPCC_ICR_I11_SHIFT (11U)
  5535. #define CSL_EVETPCC_ICR_I11_RESETVAL (0x00000000U)
  5536. #define CSL_EVETPCC_ICR_I11_MAX (0x00000001U)
  5537. #define CSL_EVETPCC_ICR_I1_MASK (0x00000002U)
  5538. #define CSL_EVETPCC_ICR_I1_SHIFT (1U)
  5539. #define CSL_EVETPCC_ICR_I1_RESETVAL (0x00000000U)
  5540. #define CSL_EVETPCC_ICR_I1_MAX (0x00000001U)
  5541. #define CSL_EVETPCC_ICR_I10_MASK (0x00000400U)
  5542. #define CSL_EVETPCC_ICR_I10_SHIFT (10U)
  5543. #define CSL_EVETPCC_ICR_I10_RESETVAL (0x00000000U)
  5544. #define CSL_EVETPCC_ICR_I10_MAX (0x00000001U)
  5545. #define CSL_EVETPCC_ICR_I28_MASK (0x10000000U)
  5546. #define CSL_EVETPCC_ICR_I28_SHIFT (28U)
  5547. #define CSL_EVETPCC_ICR_I28_RESETVAL (0x00000000U)
  5548. #define CSL_EVETPCC_ICR_I28_MAX (0x00000001U)
  5549. #define CSL_EVETPCC_ICR_I0_MASK (0x00000001U)
  5550. #define CSL_EVETPCC_ICR_I0_SHIFT (0U)
  5551. #define CSL_EVETPCC_ICR_I0_RESETVAL (0x00000000U)
  5552. #define CSL_EVETPCC_ICR_I0_MAX (0x00000001U)
  5553. #define CSL_EVETPCC_ICR_I29_MASK (0x20000000U)
  5554. #define CSL_EVETPCC_ICR_I29_SHIFT (29U)
  5555. #define CSL_EVETPCC_ICR_I29_RESETVAL (0x00000000U)
  5556. #define CSL_EVETPCC_ICR_I29_MAX (0x00000001U)
  5557. #define CSL_EVETPCC_ICR_RESETVAL (0x00000000U)
  5558. /* ICRH */
  5559. #define CSL_EVETPCC_ICRH_I37_MASK (0x00000020U)
  5560. #define CSL_EVETPCC_ICRH_I37_SHIFT (5U)
  5561. #define CSL_EVETPCC_ICRH_I37_RESETVAL (0x00000000U)
  5562. #define CSL_EVETPCC_ICRH_I37_MAX (0x00000001U)
  5563. #define CSL_EVETPCC_ICRH_I47_MASK (0x00008000U)
  5564. #define CSL_EVETPCC_ICRH_I47_SHIFT (15U)
  5565. #define CSL_EVETPCC_ICRH_I47_RESETVAL (0x00000000U)
  5566. #define CSL_EVETPCC_ICRH_I47_MAX (0x00000001U)
  5567. #define CSL_EVETPCC_ICRH_I53_MASK (0x00200000U)
  5568. #define CSL_EVETPCC_ICRH_I53_SHIFT (21U)
  5569. #define CSL_EVETPCC_ICRH_I53_RESETVAL (0x00000000U)
  5570. #define CSL_EVETPCC_ICRH_I53_MAX (0x00000001U)
  5571. #define CSL_EVETPCC_ICRH_I36_MASK (0x00000010U)
  5572. #define CSL_EVETPCC_ICRH_I36_SHIFT (4U)
  5573. #define CSL_EVETPCC_ICRH_I36_RESETVAL (0x00000000U)
  5574. #define CSL_EVETPCC_ICRH_I36_MAX (0x00000001U)
  5575. #define CSL_EVETPCC_ICRH_I63_MASK (0x80000000U)
  5576. #define CSL_EVETPCC_ICRH_I63_SHIFT (31U)
  5577. #define CSL_EVETPCC_ICRH_I63_RESETVAL (0x00000000U)
  5578. #define CSL_EVETPCC_ICRH_I63_MAX (0x00000001U)
  5579. #define CSL_EVETPCC_ICRH_I46_MASK (0x00004000U)
  5580. #define CSL_EVETPCC_ICRH_I46_SHIFT (14U)
  5581. #define CSL_EVETPCC_ICRH_I46_RESETVAL (0x00000000U)
  5582. #define CSL_EVETPCC_ICRH_I46_MAX (0x00000001U)
  5583. #define CSL_EVETPCC_ICRH_I39_MASK (0x00000080U)
  5584. #define CSL_EVETPCC_ICRH_I39_SHIFT (7U)
  5585. #define CSL_EVETPCC_ICRH_I39_RESETVAL (0x00000000U)
  5586. #define CSL_EVETPCC_ICRH_I39_MAX (0x00000001U)
  5587. #define CSL_EVETPCC_ICRH_I49_MASK (0x00020000U)
  5588. #define CSL_EVETPCC_ICRH_I49_SHIFT (17U)
  5589. #define CSL_EVETPCC_ICRH_I49_RESETVAL (0x00000000U)
  5590. #define CSL_EVETPCC_ICRH_I49_MAX (0x00000001U)
  5591. #define CSL_EVETPCC_ICRH_I38_MASK (0x00000040U)
  5592. #define CSL_EVETPCC_ICRH_I38_SHIFT (6U)
  5593. #define CSL_EVETPCC_ICRH_I38_RESETVAL (0x00000000U)
  5594. #define CSL_EVETPCC_ICRH_I38_MAX (0x00000001U)
  5595. #define CSL_EVETPCC_ICRH_I48_MASK (0x00010000U)
  5596. #define CSL_EVETPCC_ICRH_I48_SHIFT (16U)
  5597. #define CSL_EVETPCC_ICRH_I48_RESETVAL (0x00000000U)
  5598. #define CSL_EVETPCC_ICRH_I48_MAX (0x00000001U)
  5599. #define CSL_EVETPCC_ICRH_I41_MASK (0x00000200U)
  5600. #define CSL_EVETPCC_ICRH_I41_SHIFT (9U)
  5601. #define CSL_EVETPCC_ICRH_I41_RESETVAL (0x00000000U)
  5602. #define CSL_EVETPCC_ICRH_I41_MAX (0x00000001U)
  5603. #define CSL_EVETPCC_ICRH_I51_MASK (0x00080000U)
  5604. #define CSL_EVETPCC_ICRH_I51_SHIFT (19U)
  5605. #define CSL_EVETPCC_ICRH_I51_RESETVAL (0x00000000U)
  5606. #define CSL_EVETPCC_ICRH_I51_MAX (0x00000001U)
  5607. #define CSL_EVETPCC_ICRH_I40_MASK (0x00000100U)
  5608. #define CSL_EVETPCC_ICRH_I40_SHIFT (8U)
  5609. #define CSL_EVETPCC_ICRH_I40_RESETVAL (0x00000000U)
  5610. #define CSL_EVETPCC_ICRH_I40_MAX (0x00000001U)
  5611. #define CSL_EVETPCC_ICRH_I50_MASK (0x00040000U)
  5612. #define CSL_EVETPCC_ICRH_I50_SHIFT (18U)
  5613. #define CSL_EVETPCC_ICRH_I50_RESETVAL (0x00000000U)
  5614. #define CSL_EVETPCC_ICRH_I50_MAX (0x00000001U)
  5615. #define CSL_EVETPCC_ICRH_I42_MASK (0x00000400U)
  5616. #define CSL_EVETPCC_ICRH_I42_SHIFT (10U)
  5617. #define CSL_EVETPCC_ICRH_I42_RESETVAL (0x00000000U)
  5618. #define CSL_EVETPCC_ICRH_I42_MAX (0x00000001U)
  5619. #define CSL_EVETPCC_ICRH_I62_MASK (0x40000000U)
  5620. #define CSL_EVETPCC_ICRH_I62_SHIFT (30U)
  5621. #define CSL_EVETPCC_ICRH_I62_RESETVAL (0x00000000U)
  5622. #define CSL_EVETPCC_ICRH_I62_MAX (0x00000001U)
  5623. #define CSL_EVETPCC_ICRH_I52_MASK (0x00100000U)
  5624. #define CSL_EVETPCC_ICRH_I52_SHIFT (20U)
  5625. #define CSL_EVETPCC_ICRH_I52_RESETVAL (0x00000000U)
  5626. #define CSL_EVETPCC_ICRH_I52_MAX (0x00000001U)
  5627. #define CSL_EVETPCC_ICRH_I61_MASK (0x20000000U)
  5628. #define CSL_EVETPCC_ICRH_I61_SHIFT (29U)
  5629. #define CSL_EVETPCC_ICRH_I61_RESETVAL (0x00000000U)
  5630. #define CSL_EVETPCC_ICRH_I61_MAX (0x00000001U)
  5631. #define CSL_EVETPCC_ICRH_I32_MASK (0x00000001U)
  5632. #define CSL_EVETPCC_ICRH_I32_SHIFT (0U)
  5633. #define CSL_EVETPCC_ICRH_I32_RESETVAL (0x00000000U)
  5634. #define CSL_EVETPCC_ICRH_I32_MAX (0x00000001U)
  5635. #define CSL_EVETPCC_ICRH_I60_MASK (0x10000000U)
  5636. #define CSL_EVETPCC_ICRH_I60_SHIFT (28U)
  5637. #define CSL_EVETPCC_ICRH_I60_RESETVAL (0x00000000U)
  5638. #define CSL_EVETPCC_ICRH_I60_MAX (0x00000001U)
  5639. #define CSL_EVETPCC_ICRH_I59_MASK (0x08000000U)
  5640. #define CSL_EVETPCC_ICRH_I59_SHIFT (27U)
  5641. #define CSL_EVETPCC_ICRH_I59_RESETVAL (0x00000000U)
  5642. #define CSL_EVETPCC_ICRH_I59_MAX (0x00000001U)
  5643. #define CSL_EVETPCC_ICRH_I58_MASK (0x04000000U)
  5644. #define CSL_EVETPCC_ICRH_I58_SHIFT (26U)
  5645. #define CSL_EVETPCC_ICRH_I58_RESETVAL (0x00000000U)
  5646. #define CSL_EVETPCC_ICRH_I58_MAX (0x00000001U)
  5647. #define CSL_EVETPCC_ICRH_I57_MASK (0x02000000U)
  5648. #define CSL_EVETPCC_ICRH_I57_SHIFT (25U)
  5649. #define CSL_EVETPCC_ICRH_I57_RESETVAL (0x00000000U)
  5650. #define CSL_EVETPCC_ICRH_I57_MAX (0x00000001U)
  5651. #define CSL_EVETPCC_ICRH_I33_MASK (0x00000002U)
  5652. #define CSL_EVETPCC_ICRH_I33_SHIFT (1U)
  5653. #define CSL_EVETPCC_ICRH_I33_RESETVAL (0x00000000U)
  5654. #define CSL_EVETPCC_ICRH_I33_MAX (0x00000001U)
  5655. #define CSL_EVETPCC_ICRH_I43_MASK (0x00000800U)
  5656. #define CSL_EVETPCC_ICRH_I43_SHIFT (11U)
  5657. #define CSL_EVETPCC_ICRH_I43_RESETVAL (0x00000000U)
  5658. #define CSL_EVETPCC_ICRH_I43_MAX (0x00000001U)
  5659. #define CSL_EVETPCC_ICRH_I56_MASK (0x01000000U)
  5660. #define CSL_EVETPCC_ICRH_I56_SHIFT (24U)
  5661. #define CSL_EVETPCC_ICRH_I56_RESETVAL (0x00000000U)
  5662. #define CSL_EVETPCC_ICRH_I56_MAX (0x00000001U)
  5663. #define CSL_EVETPCC_ICRH_I35_MASK (0x00000008U)
  5664. #define CSL_EVETPCC_ICRH_I35_SHIFT (3U)
  5665. #define CSL_EVETPCC_ICRH_I35_RESETVAL (0x00000000U)
  5666. #define CSL_EVETPCC_ICRH_I35_MAX (0x00000001U)
  5667. #define CSL_EVETPCC_ICRH_I55_MASK (0x00800000U)
  5668. #define CSL_EVETPCC_ICRH_I55_SHIFT (23U)
  5669. #define CSL_EVETPCC_ICRH_I55_RESETVAL (0x00000000U)
  5670. #define CSL_EVETPCC_ICRH_I55_MAX (0x00000001U)
  5671. #define CSL_EVETPCC_ICRH_I45_MASK (0x00002000U)
  5672. #define CSL_EVETPCC_ICRH_I45_SHIFT (13U)
  5673. #define CSL_EVETPCC_ICRH_I45_RESETVAL (0x00000000U)
  5674. #define CSL_EVETPCC_ICRH_I45_MAX (0x00000001U)
  5675. #define CSL_EVETPCC_ICRH_I34_MASK (0x00000004U)
  5676. #define CSL_EVETPCC_ICRH_I34_SHIFT (2U)
  5677. #define CSL_EVETPCC_ICRH_I34_RESETVAL (0x00000000U)
  5678. #define CSL_EVETPCC_ICRH_I34_MAX (0x00000001U)
  5679. #define CSL_EVETPCC_ICRH_I54_MASK (0x00400000U)
  5680. #define CSL_EVETPCC_ICRH_I54_SHIFT (22U)
  5681. #define CSL_EVETPCC_ICRH_I54_RESETVAL (0x00000000U)
  5682. #define CSL_EVETPCC_ICRH_I54_MAX (0x00000001U)
  5683. #define CSL_EVETPCC_ICRH_I44_MASK (0x00001000U)
  5684. #define CSL_EVETPCC_ICRH_I44_SHIFT (12U)
  5685. #define CSL_EVETPCC_ICRH_I44_RESETVAL (0x00000000U)
  5686. #define CSL_EVETPCC_ICRH_I44_MAX (0x00000001U)
  5687. #define CSL_EVETPCC_ICRH_RESETVAL (0x00000000U)
  5688. /* IEVAL */
  5689. #define CSL_EVETPCC_IEVAL_SET_MASK (0x00000002U)
  5690. #define CSL_EVETPCC_IEVAL_SET_SHIFT (1U)
  5691. #define CSL_EVETPCC_IEVAL_SET_RESETVAL (0x00000000U)
  5692. #define CSL_EVETPCC_IEVAL_SET_MAX (0x00000001U)
  5693. #define CSL_EVETPCC_IEVAL_EVAL_MASK (0x00000001U)
  5694. #define CSL_EVETPCC_IEVAL_EVAL_SHIFT (0U)
  5695. #define CSL_EVETPCC_IEVAL_EVAL_RESETVAL (0x00000000U)
  5696. #define CSL_EVETPCC_IEVAL_EVAL_MAX (0x00000001U)
  5697. #define CSL_EVETPCC_IEVAL_RESETVAL (0x00000000U)
  5698. /* QER */
  5699. #define CSL_EVETPCC_QER_E7_MASK (0x00000080U)
  5700. #define CSL_EVETPCC_QER_E7_SHIFT (7U)
  5701. #define CSL_EVETPCC_QER_E7_RESETVAL (0x00000000U)
  5702. #define CSL_EVETPCC_QER_E7_MAX (0x00000001U)
  5703. #define CSL_EVETPCC_QER_E6_MASK (0x00000040U)
  5704. #define CSL_EVETPCC_QER_E6_SHIFT (6U)
  5705. #define CSL_EVETPCC_QER_E6_RESETVAL (0x00000000U)
  5706. #define CSL_EVETPCC_QER_E6_MAX (0x00000001U)
  5707. #define CSL_EVETPCC_QER_E5_MASK (0x00000020U)
  5708. #define CSL_EVETPCC_QER_E5_SHIFT (5U)
  5709. #define CSL_EVETPCC_QER_E5_RESETVAL (0x00000000U)
  5710. #define CSL_EVETPCC_QER_E5_MAX (0x00000001U)
  5711. #define CSL_EVETPCC_QER_E3_MASK (0x00000008U)
  5712. #define CSL_EVETPCC_QER_E3_SHIFT (3U)
  5713. #define CSL_EVETPCC_QER_E3_RESETVAL (0x00000000U)
  5714. #define CSL_EVETPCC_QER_E3_MAX (0x00000001U)
  5715. #define CSL_EVETPCC_QER_E4_MASK (0x00000010U)
  5716. #define CSL_EVETPCC_QER_E4_SHIFT (4U)
  5717. #define CSL_EVETPCC_QER_E4_RESETVAL (0x00000000U)
  5718. #define CSL_EVETPCC_QER_E4_MAX (0x00000001U)
  5719. #define CSL_EVETPCC_QER_E1_MASK (0x00000002U)
  5720. #define CSL_EVETPCC_QER_E1_SHIFT (1U)
  5721. #define CSL_EVETPCC_QER_E1_RESETVAL (0x00000000U)
  5722. #define CSL_EVETPCC_QER_E1_MAX (0x00000001U)
  5723. #define CSL_EVETPCC_QER_E2_MASK (0x00000004U)
  5724. #define CSL_EVETPCC_QER_E2_SHIFT (2U)
  5725. #define CSL_EVETPCC_QER_E2_RESETVAL (0x00000000U)
  5726. #define CSL_EVETPCC_QER_E2_MAX (0x00000001U)
  5727. #define CSL_EVETPCC_QER_E0_MASK (0x00000001U)
  5728. #define CSL_EVETPCC_QER_E0_SHIFT (0U)
  5729. #define CSL_EVETPCC_QER_E0_RESETVAL (0x00000000U)
  5730. #define CSL_EVETPCC_QER_E0_MAX (0x00000001U)
  5731. #define CSL_EVETPCC_QER_RESETVAL (0x00000000U)
  5732. /* QEER */
  5733. #define CSL_EVETPCC_QEER_E6_MASK (0x00000040U)
  5734. #define CSL_EVETPCC_QEER_E6_SHIFT (6U)
  5735. #define CSL_EVETPCC_QEER_E6_RESETVAL (0x00000000U)
  5736. #define CSL_EVETPCC_QEER_E6_MAX (0x00000001U)
  5737. #define CSL_EVETPCC_QEER_E5_MASK (0x00000020U)
  5738. #define CSL_EVETPCC_QEER_E5_SHIFT (5U)
  5739. #define CSL_EVETPCC_QEER_E5_RESETVAL (0x00000000U)
  5740. #define CSL_EVETPCC_QEER_E5_MAX (0x00000001U)
  5741. #define CSL_EVETPCC_QEER_E7_MASK (0x00000080U)
  5742. #define CSL_EVETPCC_QEER_E7_SHIFT (7U)
  5743. #define CSL_EVETPCC_QEER_E7_RESETVAL (0x00000000U)
  5744. #define CSL_EVETPCC_QEER_E7_MAX (0x00000001U)
  5745. #define CSL_EVETPCC_QEER_E0_MASK (0x00000001U)
  5746. #define CSL_EVETPCC_QEER_E0_SHIFT (0U)
  5747. #define CSL_EVETPCC_QEER_E0_RESETVAL (0x00000000U)
  5748. #define CSL_EVETPCC_QEER_E0_MAX (0x00000001U)
  5749. #define CSL_EVETPCC_QEER_E2_MASK (0x00000004U)
  5750. #define CSL_EVETPCC_QEER_E2_SHIFT (2U)
  5751. #define CSL_EVETPCC_QEER_E2_RESETVAL (0x00000000U)
  5752. #define CSL_EVETPCC_QEER_E2_MAX (0x00000001U)
  5753. #define CSL_EVETPCC_QEER_E1_MASK (0x00000002U)
  5754. #define CSL_EVETPCC_QEER_E1_SHIFT (1U)
  5755. #define CSL_EVETPCC_QEER_E1_RESETVAL (0x00000000U)
  5756. #define CSL_EVETPCC_QEER_E1_MAX (0x00000001U)
  5757. #define CSL_EVETPCC_QEER_E4_MASK (0x00000010U)
  5758. #define CSL_EVETPCC_QEER_E4_SHIFT (4U)
  5759. #define CSL_EVETPCC_QEER_E4_RESETVAL (0x00000000U)
  5760. #define CSL_EVETPCC_QEER_E4_MAX (0x00000001U)
  5761. #define CSL_EVETPCC_QEER_E3_MASK (0x00000008U)
  5762. #define CSL_EVETPCC_QEER_E3_SHIFT (3U)
  5763. #define CSL_EVETPCC_QEER_E3_RESETVAL (0x00000000U)
  5764. #define CSL_EVETPCC_QEER_E3_MAX (0x00000001U)
  5765. #define CSL_EVETPCC_QEER_RESETVAL (0x00000000U)
  5766. /* QEECR */
  5767. #define CSL_EVETPCC_QEECR_E3_MASK (0x00000008U)
  5768. #define CSL_EVETPCC_QEECR_E3_SHIFT (3U)
  5769. #define CSL_EVETPCC_QEECR_E3_RESETVAL (0x00000000U)
  5770. #define CSL_EVETPCC_QEECR_E3_MAX (0x00000001U)
  5771. #define CSL_EVETPCC_QEECR_E2_MASK (0x00000004U)
  5772. #define CSL_EVETPCC_QEECR_E2_SHIFT (2U)
  5773. #define CSL_EVETPCC_QEECR_E2_RESETVAL (0x00000000U)
  5774. #define CSL_EVETPCC_QEECR_E2_MAX (0x00000001U)
  5775. #define CSL_EVETPCC_QEECR_E1_MASK (0x00000002U)
  5776. #define CSL_EVETPCC_QEECR_E1_SHIFT (1U)
  5777. #define CSL_EVETPCC_QEECR_E1_RESETVAL (0x00000000U)
  5778. #define CSL_EVETPCC_QEECR_E1_MAX (0x00000001U)
  5779. #define CSL_EVETPCC_QEECR_E4_MASK (0x00000010U)
  5780. #define CSL_EVETPCC_QEECR_E4_SHIFT (4U)
  5781. #define CSL_EVETPCC_QEECR_E4_RESETVAL (0x00000000U)
  5782. #define CSL_EVETPCC_QEECR_E4_MAX (0x00000001U)
  5783. #define CSL_EVETPCC_QEECR_E0_MASK (0x00000001U)
  5784. #define CSL_EVETPCC_QEECR_E0_SHIFT (0U)
  5785. #define CSL_EVETPCC_QEECR_E0_RESETVAL (0x00000000U)
  5786. #define CSL_EVETPCC_QEECR_E0_MAX (0x00000001U)
  5787. #define CSL_EVETPCC_QEECR_E6_MASK (0x00000040U)
  5788. #define CSL_EVETPCC_QEECR_E6_SHIFT (6U)
  5789. #define CSL_EVETPCC_QEECR_E6_RESETVAL (0x00000000U)
  5790. #define CSL_EVETPCC_QEECR_E6_MAX (0x00000001U)
  5791. #define CSL_EVETPCC_QEECR_E5_MASK (0x00000020U)
  5792. #define CSL_EVETPCC_QEECR_E5_SHIFT (5U)
  5793. #define CSL_EVETPCC_QEECR_E5_RESETVAL (0x00000000U)
  5794. #define CSL_EVETPCC_QEECR_E5_MAX (0x00000001U)
  5795. #define CSL_EVETPCC_QEECR_E7_MASK (0x00000080U)
  5796. #define CSL_EVETPCC_QEECR_E7_SHIFT (7U)
  5797. #define CSL_EVETPCC_QEECR_E7_RESETVAL (0x00000000U)
  5798. #define CSL_EVETPCC_QEECR_E7_MAX (0x00000001U)
  5799. #define CSL_EVETPCC_QEECR_RESETVAL (0x00000000U)
  5800. /* QEESR */
  5801. #define CSL_EVETPCC_QEESR_E5_MASK (0x00000020U)
  5802. #define CSL_EVETPCC_QEESR_E5_SHIFT (5U)
  5803. #define CSL_EVETPCC_QEESR_E5_RESETVAL (0x00000000U)
  5804. #define CSL_EVETPCC_QEESR_E5_MAX (0x00000001U)
  5805. #define CSL_EVETPCC_QEESR_E3_MASK (0x00000008U)
  5806. #define CSL_EVETPCC_QEESR_E3_SHIFT (3U)
  5807. #define CSL_EVETPCC_QEESR_E3_RESETVAL (0x00000000U)
  5808. #define CSL_EVETPCC_QEESR_E3_MAX (0x00000001U)
  5809. #define CSL_EVETPCC_QEESR_E6_MASK (0x00000040U)
  5810. #define CSL_EVETPCC_QEESR_E6_SHIFT (6U)
  5811. #define CSL_EVETPCC_QEESR_E6_RESETVAL (0x00000000U)
  5812. #define CSL_EVETPCC_QEESR_E6_MAX (0x00000001U)
  5813. #define CSL_EVETPCC_QEESR_E4_MASK (0x00000010U)
  5814. #define CSL_EVETPCC_QEESR_E4_SHIFT (4U)
  5815. #define CSL_EVETPCC_QEESR_E4_RESETVAL (0x00000000U)
  5816. #define CSL_EVETPCC_QEESR_E4_MAX (0x00000001U)
  5817. #define CSL_EVETPCC_QEESR_E1_MASK (0x00000002U)
  5818. #define CSL_EVETPCC_QEESR_E1_SHIFT (1U)
  5819. #define CSL_EVETPCC_QEESR_E1_RESETVAL (0x00000000U)
  5820. #define CSL_EVETPCC_QEESR_E1_MAX (0x00000001U)
  5821. #define CSL_EVETPCC_QEESR_E2_MASK (0x00000004U)
  5822. #define CSL_EVETPCC_QEESR_E2_SHIFT (2U)
  5823. #define CSL_EVETPCC_QEESR_E2_RESETVAL (0x00000000U)
  5824. #define CSL_EVETPCC_QEESR_E2_MAX (0x00000001U)
  5825. #define CSL_EVETPCC_QEESR_E0_MASK (0x00000001U)
  5826. #define CSL_EVETPCC_QEESR_E0_SHIFT (0U)
  5827. #define CSL_EVETPCC_QEESR_E0_RESETVAL (0x00000000U)
  5828. #define CSL_EVETPCC_QEESR_E0_MAX (0x00000001U)
  5829. #define CSL_EVETPCC_QEESR_E7_MASK (0x00000080U)
  5830. #define CSL_EVETPCC_QEESR_E7_SHIFT (7U)
  5831. #define CSL_EVETPCC_QEESR_E7_RESETVAL (0x00000000U)
  5832. #define CSL_EVETPCC_QEESR_E7_MAX (0x00000001U)
  5833. #define CSL_EVETPCC_QEESR_RESETVAL (0x00000000U)
  5834. /* QSER */
  5835. #define CSL_EVETPCC_QSER_E4_MASK (0x00000010U)
  5836. #define CSL_EVETPCC_QSER_E4_SHIFT (4U)
  5837. #define CSL_EVETPCC_QSER_E4_RESETVAL (0x00000000U)
  5838. #define CSL_EVETPCC_QSER_E4_MAX (0x00000001U)
  5839. #define CSL_EVETPCC_QSER_E3_MASK (0x00000008U)
  5840. #define CSL_EVETPCC_QSER_E3_SHIFT (3U)
  5841. #define CSL_EVETPCC_QSER_E3_RESETVAL (0x00000000U)
  5842. #define CSL_EVETPCC_QSER_E3_MAX (0x00000001U)
  5843. #define CSL_EVETPCC_QSER_E2_MASK (0x00000004U)
  5844. #define CSL_EVETPCC_QSER_E2_SHIFT (2U)
  5845. #define CSL_EVETPCC_QSER_E2_RESETVAL (0x00000000U)
  5846. #define CSL_EVETPCC_QSER_E2_MAX (0x00000001U)
  5847. #define CSL_EVETPCC_QSER_E1_MASK (0x00000002U)
  5848. #define CSL_EVETPCC_QSER_E1_SHIFT (1U)
  5849. #define CSL_EVETPCC_QSER_E1_RESETVAL (0x00000000U)
  5850. #define CSL_EVETPCC_QSER_E1_MAX (0x00000001U)
  5851. #define CSL_EVETPCC_QSER_E0_MASK (0x00000001U)
  5852. #define CSL_EVETPCC_QSER_E0_SHIFT (0U)
  5853. #define CSL_EVETPCC_QSER_E0_RESETVAL (0x00000000U)
  5854. #define CSL_EVETPCC_QSER_E0_MAX (0x00000001U)
  5855. #define CSL_EVETPCC_QSER_E7_MASK (0x00000080U)
  5856. #define CSL_EVETPCC_QSER_E7_SHIFT (7U)
  5857. #define CSL_EVETPCC_QSER_E7_RESETVAL (0x00000000U)
  5858. #define CSL_EVETPCC_QSER_E7_MAX (0x00000001U)
  5859. #define CSL_EVETPCC_QSER_E5_MASK (0x00000020U)
  5860. #define CSL_EVETPCC_QSER_E5_SHIFT (5U)
  5861. #define CSL_EVETPCC_QSER_E5_RESETVAL (0x00000000U)
  5862. #define CSL_EVETPCC_QSER_E5_MAX (0x00000001U)
  5863. #define CSL_EVETPCC_QSER_E6_MASK (0x00000040U)
  5864. #define CSL_EVETPCC_QSER_E6_SHIFT (6U)
  5865. #define CSL_EVETPCC_QSER_E6_RESETVAL (0x00000000U)
  5866. #define CSL_EVETPCC_QSER_E6_MAX (0x00000001U)
  5867. #define CSL_EVETPCC_QSER_RESETVAL (0x00000000U)
  5868. /* QSECR */
  5869. #define CSL_EVETPCC_QSECR_E5_MASK (0x00000020U)
  5870. #define CSL_EVETPCC_QSECR_E5_SHIFT (5U)
  5871. #define CSL_EVETPCC_QSECR_E5_RESETVAL (0x00000000U)
  5872. #define CSL_EVETPCC_QSECR_E5_MAX (0x00000001U)
  5873. #define CSL_EVETPCC_QSECR_E6_MASK (0x00000040U)
  5874. #define CSL_EVETPCC_QSECR_E6_SHIFT (6U)
  5875. #define CSL_EVETPCC_QSECR_E6_RESETVAL (0x00000000U)
  5876. #define CSL_EVETPCC_QSECR_E6_MAX (0x00000001U)
  5877. #define CSL_EVETPCC_QSECR_E7_MASK (0x00000080U)
  5878. #define CSL_EVETPCC_QSECR_E7_SHIFT (7U)
  5879. #define CSL_EVETPCC_QSECR_E7_RESETVAL (0x00000000U)
  5880. #define CSL_EVETPCC_QSECR_E7_MAX (0x00000001U)
  5881. #define CSL_EVETPCC_QSECR_E0_MASK (0x00000001U)
  5882. #define CSL_EVETPCC_QSECR_E0_SHIFT (0U)
  5883. #define CSL_EVETPCC_QSECR_E0_RESETVAL (0x00000000U)
  5884. #define CSL_EVETPCC_QSECR_E0_MAX (0x00000001U)
  5885. #define CSL_EVETPCC_QSECR_E2_MASK (0x00000004U)
  5886. #define CSL_EVETPCC_QSECR_E2_SHIFT (2U)
  5887. #define CSL_EVETPCC_QSECR_E2_RESETVAL (0x00000000U)
  5888. #define CSL_EVETPCC_QSECR_E2_MAX (0x00000001U)
  5889. #define CSL_EVETPCC_QSECR_E1_MASK (0x00000002U)
  5890. #define CSL_EVETPCC_QSECR_E1_SHIFT (1U)
  5891. #define CSL_EVETPCC_QSECR_E1_RESETVAL (0x00000000U)
  5892. #define CSL_EVETPCC_QSECR_E1_MAX (0x00000001U)
  5893. #define CSL_EVETPCC_QSECR_E4_MASK (0x00000010U)
  5894. #define CSL_EVETPCC_QSECR_E4_SHIFT (4U)
  5895. #define CSL_EVETPCC_QSECR_E4_RESETVAL (0x00000000U)
  5896. #define CSL_EVETPCC_QSECR_E4_MAX (0x00000001U)
  5897. #define CSL_EVETPCC_QSECR_E3_MASK (0x00000008U)
  5898. #define CSL_EVETPCC_QSECR_E3_SHIFT (3U)
  5899. #define CSL_EVETPCC_QSECR_E3_RESETVAL (0x00000000U)
  5900. #define CSL_EVETPCC_QSECR_E3_MAX (0x00000001U)
  5901. #define CSL_EVETPCC_QSECR_RESETVAL (0x00000000U)
  5902. /* IEVAL_RN */
  5903. #define CSL_EVETPCC_IEVAL_RN_SET_MASK (0x00000002U)
  5904. #define CSL_EVETPCC_IEVAL_RN_SET_SHIFT (1U)
  5905. #define CSL_EVETPCC_IEVAL_RN_SET_RESETVAL (0x00000000U)
  5906. #define CSL_EVETPCC_IEVAL_RN_SET_MAX (0x00000001U)
  5907. #define CSL_EVETPCC_IEVAL_RN_EVAL_MASK (0x00000001U)
  5908. #define CSL_EVETPCC_IEVAL_RN_EVAL_SHIFT (0U)
  5909. #define CSL_EVETPCC_IEVAL_RN_EVAL_RESETVAL (0x00000000U)
  5910. #define CSL_EVETPCC_IEVAL_RN_EVAL_MAX (0x00000001U)
  5911. #define CSL_EVETPCC_IEVAL_RN_RESETVAL (0x00000000U)
  5912. /* IESRH_RN */
  5913. #define CSL_EVETPCC_IESRH_RN_I52_MASK (0x00100000U)
  5914. #define CSL_EVETPCC_IESRH_RN_I52_SHIFT (20U)
  5915. #define CSL_EVETPCC_IESRH_RN_I52_RESETVAL (0x00000000U)
  5916. #define CSL_EVETPCC_IESRH_RN_I52_MAX (0x00000001U)
  5917. #define CSL_EVETPCC_IESRH_RN_I41_MASK (0x00000200U)
  5918. #define CSL_EVETPCC_IESRH_RN_I41_SHIFT (9U)
  5919. #define CSL_EVETPCC_IESRH_RN_I41_RESETVAL (0x00000000U)
  5920. #define CSL_EVETPCC_IESRH_RN_I41_MAX (0x00000001U)
  5921. #define CSL_EVETPCC_IESRH_RN_I53_MASK (0x00200000U)
  5922. #define CSL_EVETPCC_IESRH_RN_I53_SHIFT (21U)
  5923. #define CSL_EVETPCC_IESRH_RN_I53_RESETVAL (0x00000000U)
  5924. #define CSL_EVETPCC_IESRH_RN_I53_MAX (0x00000001U)
  5925. #define CSL_EVETPCC_IESRH_RN_I42_MASK (0x00000400U)
  5926. #define CSL_EVETPCC_IESRH_RN_I42_SHIFT (10U)
  5927. #define CSL_EVETPCC_IESRH_RN_I42_RESETVAL (0x00000000U)
  5928. #define CSL_EVETPCC_IESRH_RN_I42_MAX (0x00000001U)
  5929. #define CSL_EVETPCC_IESRH_RN_I54_MASK (0x00400000U)
  5930. #define CSL_EVETPCC_IESRH_RN_I54_SHIFT (22U)
  5931. #define CSL_EVETPCC_IESRH_RN_I54_RESETVAL (0x00000000U)
  5932. #define CSL_EVETPCC_IESRH_RN_I54_MAX (0x00000001U)
  5933. #define CSL_EVETPCC_IESRH_RN_I43_MASK (0x00000800U)
  5934. #define CSL_EVETPCC_IESRH_RN_I43_SHIFT (11U)
  5935. #define CSL_EVETPCC_IESRH_RN_I43_RESETVAL (0x00000000U)
  5936. #define CSL_EVETPCC_IESRH_RN_I43_MAX (0x00000001U)
  5937. #define CSL_EVETPCC_IESRH_RN_I55_MASK (0x00800000U)
  5938. #define CSL_EVETPCC_IESRH_RN_I55_SHIFT (23U)
  5939. #define CSL_EVETPCC_IESRH_RN_I55_RESETVAL (0x00000000U)
  5940. #define CSL_EVETPCC_IESRH_RN_I55_MAX (0x00000001U)
  5941. #define CSL_EVETPCC_IESRH_RN_I44_MASK (0x00001000U)
  5942. #define CSL_EVETPCC_IESRH_RN_I44_SHIFT (12U)
  5943. #define CSL_EVETPCC_IESRH_RN_I44_RESETVAL (0x00000000U)
  5944. #define CSL_EVETPCC_IESRH_RN_I44_MAX (0x00000001U)
  5945. #define CSL_EVETPCC_IESRH_RN_I33_MASK (0x00000002U)
  5946. #define CSL_EVETPCC_IESRH_RN_I33_SHIFT (1U)
  5947. #define CSL_EVETPCC_IESRH_RN_I33_RESETVAL (0x00000000U)
  5948. #define CSL_EVETPCC_IESRH_RN_I33_MAX (0x00000001U)
  5949. #define CSL_EVETPCC_IESRH_RN_I56_MASK (0x01000000U)
  5950. #define CSL_EVETPCC_IESRH_RN_I56_SHIFT (24U)
  5951. #define CSL_EVETPCC_IESRH_RN_I56_RESETVAL (0x00000000U)
  5952. #define CSL_EVETPCC_IESRH_RN_I56_MAX (0x00000001U)
  5953. #define CSL_EVETPCC_IESRH_RN_I45_MASK (0x00002000U)
  5954. #define CSL_EVETPCC_IESRH_RN_I45_SHIFT (13U)
  5955. #define CSL_EVETPCC_IESRH_RN_I45_RESETVAL (0x00000000U)
  5956. #define CSL_EVETPCC_IESRH_RN_I45_MAX (0x00000001U)
  5957. #define CSL_EVETPCC_IESRH_RN_I57_MASK (0x02000000U)
  5958. #define CSL_EVETPCC_IESRH_RN_I57_SHIFT (25U)
  5959. #define CSL_EVETPCC_IESRH_RN_I57_RESETVAL (0x00000000U)
  5960. #define CSL_EVETPCC_IESRH_RN_I57_MAX (0x00000001U)
  5961. #define CSL_EVETPCC_IESRH_RN_I32_MASK (0x00000001U)
  5962. #define CSL_EVETPCC_IESRH_RN_I32_SHIFT (0U)
  5963. #define CSL_EVETPCC_IESRH_RN_I32_RESETVAL (0x00000000U)
  5964. #define CSL_EVETPCC_IESRH_RN_I32_MAX (0x00000001U)
  5965. #define CSL_EVETPCC_IESRH_RN_I46_MASK (0x00004000U)
  5966. #define CSL_EVETPCC_IESRH_RN_I46_SHIFT (14U)
  5967. #define CSL_EVETPCC_IESRH_RN_I46_RESETVAL (0x00000000U)
  5968. #define CSL_EVETPCC_IESRH_RN_I46_MAX (0x00000001U)
  5969. #define CSL_EVETPCC_IESRH_RN_I35_MASK (0x00000008U)
  5970. #define CSL_EVETPCC_IESRH_RN_I35_SHIFT (3U)
  5971. #define CSL_EVETPCC_IESRH_RN_I35_RESETVAL (0x00000000U)
  5972. #define CSL_EVETPCC_IESRH_RN_I35_MAX (0x00000001U)
  5973. #define CSL_EVETPCC_IESRH_RN_I58_MASK (0x04000000U)
  5974. #define CSL_EVETPCC_IESRH_RN_I58_SHIFT (26U)
  5975. #define CSL_EVETPCC_IESRH_RN_I58_RESETVAL (0x00000000U)
  5976. #define CSL_EVETPCC_IESRH_RN_I58_MAX (0x00000001U)
  5977. #define CSL_EVETPCC_IESRH_RN_I47_MASK (0x00008000U)
  5978. #define CSL_EVETPCC_IESRH_RN_I47_SHIFT (15U)
  5979. #define CSL_EVETPCC_IESRH_RN_I47_RESETVAL (0x00000000U)
  5980. #define CSL_EVETPCC_IESRH_RN_I47_MAX (0x00000001U)
  5981. #define CSL_EVETPCC_IESRH_RN_I34_MASK (0x00000004U)
  5982. #define CSL_EVETPCC_IESRH_RN_I34_SHIFT (2U)
  5983. #define CSL_EVETPCC_IESRH_RN_I34_RESETVAL (0x00000000U)
  5984. #define CSL_EVETPCC_IESRH_RN_I34_MAX (0x00000001U)
  5985. #define CSL_EVETPCC_IESRH_RN_I59_MASK (0x08000000U)
  5986. #define CSL_EVETPCC_IESRH_RN_I59_SHIFT (27U)
  5987. #define CSL_EVETPCC_IESRH_RN_I59_RESETVAL (0x00000000U)
  5988. #define CSL_EVETPCC_IESRH_RN_I59_MAX (0x00000001U)
  5989. #define CSL_EVETPCC_IESRH_RN_I48_MASK (0x00010000U)
  5990. #define CSL_EVETPCC_IESRH_RN_I48_SHIFT (16U)
  5991. #define CSL_EVETPCC_IESRH_RN_I48_RESETVAL (0x00000000U)
  5992. #define CSL_EVETPCC_IESRH_RN_I48_MAX (0x00000001U)
  5993. #define CSL_EVETPCC_IESRH_RN_I60_MASK (0x10000000U)
  5994. #define CSL_EVETPCC_IESRH_RN_I60_SHIFT (28U)
  5995. #define CSL_EVETPCC_IESRH_RN_I60_RESETVAL (0x00000000U)
  5996. #define CSL_EVETPCC_IESRH_RN_I60_MAX (0x00000001U)
  5997. #define CSL_EVETPCC_IESRH_RN_I37_MASK (0x00000020U)
  5998. #define CSL_EVETPCC_IESRH_RN_I37_SHIFT (5U)
  5999. #define CSL_EVETPCC_IESRH_RN_I37_RESETVAL (0x00000000U)
  6000. #define CSL_EVETPCC_IESRH_RN_I37_MAX (0x00000001U)
  6001. #define CSL_EVETPCC_IESRH_RN_I49_MASK (0x00020000U)
  6002. #define CSL_EVETPCC_IESRH_RN_I49_SHIFT (17U)
  6003. #define CSL_EVETPCC_IESRH_RN_I49_RESETVAL (0x00000000U)
  6004. #define CSL_EVETPCC_IESRH_RN_I49_MAX (0x00000001U)
  6005. #define CSL_EVETPCC_IESRH_RN_I36_MASK (0x00000010U)
  6006. #define CSL_EVETPCC_IESRH_RN_I36_SHIFT (4U)
  6007. #define CSL_EVETPCC_IESRH_RN_I36_RESETVAL (0x00000000U)
  6008. #define CSL_EVETPCC_IESRH_RN_I36_MAX (0x00000001U)
  6009. #define CSL_EVETPCC_IESRH_RN_I50_MASK (0x00040000U)
  6010. #define CSL_EVETPCC_IESRH_RN_I50_SHIFT (18U)
  6011. #define CSL_EVETPCC_IESRH_RN_I50_RESETVAL (0x00000000U)
  6012. #define CSL_EVETPCC_IESRH_RN_I50_MAX (0x00000001U)
  6013. #define CSL_EVETPCC_IESRH_RN_I39_MASK (0x00000080U)
  6014. #define CSL_EVETPCC_IESRH_RN_I39_SHIFT (7U)
  6015. #define CSL_EVETPCC_IESRH_RN_I39_RESETVAL (0x00000000U)
  6016. #define CSL_EVETPCC_IESRH_RN_I39_MAX (0x00000001U)
  6017. #define CSL_EVETPCC_IESRH_RN_I38_MASK (0x00000040U)
  6018. #define CSL_EVETPCC_IESRH_RN_I38_SHIFT (6U)
  6019. #define CSL_EVETPCC_IESRH_RN_I38_RESETVAL (0x00000000U)
  6020. #define CSL_EVETPCC_IESRH_RN_I38_MAX (0x00000001U)
  6021. #define CSL_EVETPCC_IESRH_RN_I63_MASK (0x80000000U)
  6022. #define CSL_EVETPCC_IESRH_RN_I63_SHIFT (31U)
  6023. #define CSL_EVETPCC_IESRH_RN_I63_RESETVAL (0x00000000U)
  6024. #define CSL_EVETPCC_IESRH_RN_I63_MAX (0x00000001U)
  6025. #define CSL_EVETPCC_IESRH_RN_I62_MASK (0x40000000U)
  6026. #define CSL_EVETPCC_IESRH_RN_I62_SHIFT (30U)
  6027. #define CSL_EVETPCC_IESRH_RN_I62_RESETVAL (0x00000000U)
  6028. #define CSL_EVETPCC_IESRH_RN_I62_MAX (0x00000001U)
  6029. #define CSL_EVETPCC_IESRH_RN_I40_MASK (0x00000100U)
  6030. #define CSL_EVETPCC_IESRH_RN_I40_SHIFT (8U)
  6031. #define CSL_EVETPCC_IESRH_RN_I40_RESETVAL (0x00000000U)
  6032. #define CSL_EVETPCC_IESRH_RN_I40_MAX (0x00000001U)
  6033. #define CSL_EVETPCC_IESRH_RN_I61_MASK (0x20000000U)
  6034. #define CSL_EVETPCC_IESRH_RN_I61_SHIFT (29U)
  6035. #define CSL_EVETPCC_IESRH_RN_I61_RESETVAL (0x00000000U)
  6036. #define CSL_EVETPCC_IESRH_RN_I61_MAX (0x00000001U)
  6037. #define CSL_EVETPCC_IESRH_RN_I51_MASK (0x00080000U)
  6038. #define CSL_EVETPCC_IESRH_RN_I51_SHIFT (19U)
  6039. #define CSL_EVETPCC_IESRH_RN_I51_RESETVAL (0x00000000U)
  6040. #define CSL_EVETPCC_IESRH_RN_I51_MAX (0x00000001U)
  6041. #define CSL_EVETPCC_IESRH_RN_RESETVAL (0x00000000U)
  6042. /* SER_RN */
  6043. #define CSL_EVETPCC_SER_RN_E0_MASK (0x00000001U)
  6044. #define CSL_EVETPCC_SER_RN_E0_SHIFT (0U)
  6045. #define CSL_EVETPCC_SER_RN_E0_RESETVAL (0x00000000U)
  6046. #define CSL_EVETPCC_SER_RN_E0_MAX (0x00000001U)
  6047. #define CSL_EVETPCC_SER_RN_E13_MASK (0x00002000U)
  6048. #define CSL_EVETPCC_SER_RN_E13_SHIFT (13U)
  6049. #define CSL_EVETPCC_SER_RN_E13_RESETVAL (0x00000000U)
  6050. #define CSL_EVETPCC_SER_RN_E13_MAX (0x00000001U)
  6051. #define CSL_EVETPCC_SER_RN_E21_MASK (0x00200000U)
  6052. #define CSL_EVETPCC_SER_RN_E21_SHIFT (21U)
  6053. #define CSL_EVETPCC_SER_RN_E21_RESETVAL (0x00000000U)
  6054. #define CSL_EVETPCC_SER_RN_E21_MAX (0x00000001U)
  6055. #define CSL_EVETPCC_SER_RN_E14_MASK (0x00004000U)
  6056. #define CSL_EVETPCC_SER_RN_E14_SHIFT (14U)
  6057. #define CSL_EVETPCC_SER_RN_E14_RESETVAL (0x00000000U)
  6058. #define CSL_EVETPCC_SER_RN_E14_MAX (0x00000001U)
  6059. #define CSL_EVETPCC_SER_RN_E31_MASK (0x80000000U)
  6060. #define CSL_EVETPCC_SER_RN_E31_SHIFT (31U)
  6061. #define CSL_EVETPCC_SER_RN_E31_RESETVAL (0x00000000U)
  6062. #define CSL_EVETPCC_SER_RN_E31_MAX (0x00000001U)
  6063. #define CSL_EVETPCC_SER_RN_E1_MASK (0x00000002U)
  6064. #define CSL_EVETPCC_SER_RN_E1_SHIFT (1U)
  6065. #define CSL_EVETPCC_SER_RN_E1_RESETVAL (0x00000000U)
  6066. #define CSL_EVETPCC_SER_RN_E1_MAX (0x00000001U)
  6067. #define CSL_EVETPCC_SER_RN_E11_MASK (0x00000800U)
  6068. #define CSL_EVETPCC_SER_RN_E11_SHIFT (11U)
  6069. #define CSL_EVETPCC_SER_RN_E11_RESETVAL (0x00000000U)
  6070. #define CSL_EVETPCC_SER_RN_E11_MAX (0x00000001U)
  6071. #define CSL_EVETPCC_SER_RN_E19_MASK (0x00080000U)
  6072. #define CSL_EVETPCC_SER_RN_E19_SHIFT (19U)
  6073. #define CSL_EVETPCC_SER_RN_E19_RESETVAL (0x00000000U)
  6074. #define CSL_EVETPCC_SER_RN_E19_MAX (0x00000001U)
  6075. #define CSL_EVETPCC_SER_RN_E20_MASK (0x00100000U)
  6076. #define CSL_EVETPCC_SER_RN_E20_SHIFT (20U)
  6077. #define CSL_EVETPCC_SER_RN_E20_RESETVAL (0x00000000U)
  6078. #define CSL_EVETPCC_SER_RN_E20_MAX (0x00000001U)
  6079. #define CSL_EVETPCC_SER_RN_E12_MASK (0x00001000U)
  6080. #define CSL_EVETPCC_SER_RN_E12_SHIFT (12U)
  6081. #define CSL_EVETPCC_SER_RN_E12_RESETVAL (0x00000000U)
  6082. #define CSL_EVETPCC_SER_RN_E12_MAX (0x00000001U)
  6083. #define CSL_EVETPCC_SER_RN_E3_MASK (0x00000008U)
  6084. #define CSL_EVETPCC_SER_RN_E3_SHIFT (3U)
  6085. #define CSL_EVETPCC_SER_RN_E3_RESETVAL (0x00000000U)
  6086. #define CSL_EVETPCC_SER_RN_E3_MAX (0x00000001U)
  6087. #define CSL_EVETPCC_SER_RN_E4_MASK (0x00000010U)
  6088. #define CSL_EVETPCC_SER_RN_E4_SHIFT (4U)
  6089. #define CSL_EVETPCC_SER_RN_E4_RESETVAL (0x00000000U)
  6090. #define CSL_EVETPCC_SER_RN_E4_MAX (0x00000001U)
  6091. #define CSL_EVETPCC_SER_RN_E24_MASK (0x01000000U)
  6092. #define CSL_EVETPCC_SER_RN_E24_SHIFT (24U)
  6093. #define CSL_EVETPCC_SER_RN_E24_RESETVAL (0x00000000U)
  6094. #define CSL_EVETPCC_SER_RN_E24_MAX (0x00000001U)
  6095. #define CSL_EVETPCC_SER_RN_E2_MASK (0x00000004U)
  6096. #define CSL_EVETPCC_SER_RN_E2_SHIFT (2U)
  6097. #define CSL_EVETPCC_SER_RN_E2_RESETVAL (0x00000000U)
  6098. #define CSL_EVETPCC_SER_RN_E2_MAX (0x00000001U)
  6099. #define CSL_EVETPCC_SER_RN_E22_MASK (0x00400000U)
  6100. #define CSL_EVETPCC_SER_RN_E22_SHIFT (22U)
  6101. #define CSL_EVETPCC_SER_RN_E22_RESETVAL (0x00000000U)
  6102. #define CSL_EVETPCC_SER_RN_E22_MAX (0x00000001U)
  6103. #define CSL_EVETPCC_SER_RN_E23_MASK (0x00800000U)
  6104. #define CSL_EVETPCC_SER_RN_E23_SHIFT (23U)
  6105. #define CSL_EVETPCC_SER_RN_E23_RESETVAL (0x00000000U)
  6106. #define CSL_EVETPCC_SER_RN_E23_MAX (0x00000001U)
  6107. #define CSL_EVETPCC_SER_RN_E25_MASK (0x02000000U)
  6108. #define CSL_EVETPCC_SER_RN_E25_SHIFT (25U)
  6109. #define CSL_EVETPCC_SER_RN_E25_RESETVAL (0x00000000U)
  6110. #define CSL_EVETPCC_SER_RN_E25_MAX (0x00000001U)
  6111. #define CSL_EVETPCC_SER_RN_E26_MASK (0x04000000U)
  6112. #define CSL_EVETPCC_SER_RN_E26_SHIFT (26U)
  6113. #define CSL_EVETPCC_SER_RN_E26_RESETVAL (0x00000000U)
  6114. #define CSL_EVETPCC_SER_RN_E26_MAX (0x00000001U)
  6115. #define CSL_EVETPCC_SER_RN_E6_MASK (0x00000040U)
  6116. #define CSL_EVETPCC_SER_RN_E6_SHIFT (6U)
  6117. #define CSL_EVETPCC_SER_RN_E6_RESETVAL (0x00000000U)
  6118. #define CSL_EVETPCC_SER_RN_E6_MAX (0x00000001U)
  6119. #define CSL_EVETPCC_SER_RN_E5_MASK (0x00000020U)
  6120. #define CSL_EVETPCC_SER_RN_E5_SHIFT (5U)
  6121. #define CSL_EVETPCC_SER_RN_E5_RESETVAL (0x00000000U)
  6122. #define CSL_EVETPCC_SER_RN_E5_MAX (0x00000001U)
  6123. #define CSL_EVETPCC_SER_RN_E8_MASK (0x00000100U)
  6124. #define CSL_EVETPCC_SER_RN_E8_SHIFT (8U)
  6125. #define CSL_EVETPCC_SER_RN_E8_RESETVAL (0x00000000U)
  6126. #define CSL_EVETPCC_SER_RN_E8_MAX (0x00000001U)
  6127. #define CSL_EVETPCC_SER_RN_E17_MASK (0x00020000U)
  6128. #define CSL_EVETPCC_SER_RN_E17_SHIFT (17U)
  6129. #define CSL_EVETPCC_SER_RN_E17_RESETVAL (0x00000000U)
  6130. #define CSL_EVETPCC_SER_RN_E17_MAX (0x00000001U)
  6131. #define CSL_EVETPCC_SER_RN_E29_MASK (0x20000000U)
  6132. #define CSL_EVETPCC_SER_RN_E29_SHIFT (29U)
  6133. #define CSL_EVETPCC_SER_RN_E29_RESETVAL (0x00000000U)
  6134. #define CSL_EVETPCC_SER_RN_E29_MAX (0x00000001U)
  6135. #define CSL_EVETPCC_SER_RN_E18_MASK (0x00040000U)
  6136. #define CSL_EVETPCC_SER_RN_E18_SHIFT (18U)
  6137. #define CSL_EVETPCC_SER_RN_E18_RESETVAL (0x00000000U)
  6138. #define CSL_EVETPCC_SER_RN_E18_MAX (0x00000001U)
  6139. #define CSL_EVETPCC_SER_RN_E30_MASK (0x40000000U)
  6140. #define CSL_EVETPCC_SER_RN_E30_SHIFT (30U)
  6141. #define CSL_EVETPCC_SER_RN_E30_RESETVAL (0x00000000U)
  6142. #define CSL_EVETPCC_SER_RN_E30_MAX (0x00000001U)
  6143. #define CSL_EVETPCC_SER_RN_E7_MASK (0x00000080U)
  6144. #define CSL_EVETPCC_SER_RN_E7_SHIFT (7U)
  6145. #define CSL_EVETPCC_SER_RN_E7_RESETVAL (0x00000000U)
  6146. #define CSL_EVETPCC_SER_RN_E7_MAX (0x00000001U)
  6147. #define CSL_EVETPCC_SER_RN_E10_MASK (0x00000400U)
  6148. #define CSL_EVETPCC_SER_RN_E10_SHIFT (10U)
  6149. #define CSL_EVETPCC_SER_RN_E10_RESETVAL (0x00000000U)
  6150. #define CSL_EVETPCC_SER_RN_E10_MAX (0x00000001U)
  6151. #define CSL_EVETPCC_SER_RN_E15_MASK (0x00008000U)
  6152. #define CSL_EVETPCC_SER_RN_E15_SHIFT (15U)
  6153. #define CSL_EVETPCC_SER_RN_E15_RESETVAL (0x00000000U)
  6154. #define CSL_EVETPCC_SER_RN_E15_MAX (0x00000001U)
  6155. #define CSL_EVETPCC_SER_RN_E27_MASK (0x08000000U)
  6156. #define CSL_EVETPCC_SER_RN_E27_SHIFT (27U)
  6157. #define CSL_EVETPCC_SER_RN_E27_RESETVAL (0x00000000U)
  6158. #define CSL_EVETPCC_SER_RN_E27_MAX (0x00000001U)
  6159. #define CSL_EVETPCC_SER_RN_E9_MASK (0x00000200U)
  6160. #define CSL_EVETPCC_SER_RN_E9_SHIFT (9U)
  6161. #define CSL_EVETPCC_SER_RN_E9_RESETVAL (0x00000000U)
  6162. #define CSL_EVETPCC_SER_RN_E9_MAX (0x00000001U)
  6163. #define CSL_EVETPCC_SER_RN_E16_MASK (0x00010000U)
  6164. #define CSL_EVETPCC_SER_RN_E16_SHIFT (16U)
  6165. #define CSL_EVETPCC_SER_RN_E16_RESETVAL (0x00000000U)
  6166. #define CSL_EVETPCC_SER_RN_E16_MAX (0x00000001U)
  6167. #define CSL_EVETPCC_SER_RN_E28_MASK (0x10000000U)
  6168. #define CSL_EVETPCC_SER_RN_E28_SHIFT (28U)
  6169. #define CSL_EVETPCC_SER_RN_E28_RESETVAL (0x00000000U)
  6170. #define CSL_EVETPCC_SER_RN_E28_MAX (0x00000001U)
  6171. #define CSL_EVETPCC_SER_RN_RESETVAL (0x00000000U)
  6172. /* SERH_RN */
  6173. #define CSL_EVETPCC_SERH_RN_E53_MASK (0x00200000U)
  6174. #define CSL_EVETPCC_SERH_RN_E53_SHIFT (21U)
  6175. #define CSL_EVETPCC_SERH_RN_E53_RESETVAL (0x00000000U)
  6176. #define CSL_EVETPCC_SERH_RN_E53_MAX (0x00000001U)
  6177. #define CSL_EVETPCC_SERH_RN_E42_MASK (0x00000400U)
  6178. #define CSL_EVETPCC_SERH_RN_E42_SHIFT (10U)
  6179. #define CSL_EVETPCC_SERH_RN_E42_RESETVAL (0x00000000U)
  6180. #define CSL_EVETPCC_SERH_RN_E42_MAX (0x00000001U)
  6181. #define CSL_EVETPCC_SERH_RN_E52_MASK (0x00100000U)
  6182. #define CSL_EVETPCC_SERH_RN_E52_SHIFT (20U)
  6183. #define CSL_EVETPCC_SERH_RN_E52_RESETVAL (0x00000000U)
  6184. #define CSL_EVETPCC_SERH_RN_E52_MAX (0x00000001U)
  6185. #define CSL_EVETPCC_SERH_RN_E43_MASK (0x00000800U)
  6186. #define CSL_EVETPCC_SERH_RN_E43_SHIFT (11U)
  6187. #define CSL_EVETPCC_SERH_RN_E43_RESETVAL (0x00000000U)
  6188. #define CSL_EVETPCC_SERH_RN_E43_MAX (0x00000001U)
  6189. #define CSL_EVETPCC_SERH_RN_E32_MASK (0x00000001U)
  6190. #define CSL_EVETPCC_SERH_RN_E32_SHIFT (0U)
  6191. #define CSL_EVETPCC_SERH_RN_E32_RESETVAL (0x00000000U)
  6192. #define CSL_EVETPCC_SERH_RN_E32_MAX (0x00000001U)
  6193. #define CSL_EVETPCC_SERH_RN_E44_MASK (0x00001000U)
  6194. #define CSL_EVETPCC_SERH_RN_E44_SHIFT (12U)
  6195. #define CSL_EVETPCC_SERH_RN_E44_RESETVAL (0x00000000U)
  6196. #define CSL_EVETPCC_SERH_RN_E44_MAX (0x00000001U)
  6197. #define CSL_EVETPCC_SERH_RN_E55_MASK (0x00800000U)
  6198. #define CSL_EVETPCC_SERH_RN_E55_SHIFT (23U)
  6199. #define CSL_EVETPCC_SERH_RN_E55_RESETVAL (0x00000000U)
  6200. #define CSL_EVETPCC_SERH_RN_E55_MAX (0x00000001U)
  6201. #define CSL_EVETPCC_SERH_RN_E45_MASK (0x00002000U)
  6202. #define CSL_EVETPCC_SERH_RN_E45_SHIFT (13U)
  6203. #define CSL_EVETPCC_SERH_RN_E45_RESETVAL (0x00000000U)
  6204. #define CSL_EVETPCC_SERH_RN_E45_MAX (0x00000001U)
  6205. #define CSL_EVETPCC_SERH_RN_E54_MASK (0x00400000U)
  6206. #define CSL_EVETPCC_SERH_RN_E54_SHIFT (22U)
  6207. #define CSL_EVETPCC_SERH_RN_E54_RESETVAL (0x00000000U)
  6208. #define CSL_EVETPCC_SERH_RN_E54_MAX (0x00000001U)
  6209. #define CSL_EVETPCC_SERH_RN_E46_MASK (0x00004000U)
  6210. #define CSL_EVETPCC_SERH_RN_E46_SHIFT (14U)
  6211. #define CSL_EVETPCC_SERH_RN_E46_RESETVAL (0x00000000U)
  6212. #define CSL_EVETPCC_SERH_RN_E46_MAX (0x00000001U)
  6213. #define CSL_EVETPCC_SERH_RN_E56_MASK (0x01000000U)
  6214. #define CSL_EVETPCC_SERH_RN_E56_SHIFT (24U)
  6215. #define CSL_EVETPCC_SERH_RN_E56_RESETVAL (0x00000000U)
  6216. #define CSL_EVETPCC_SERH_RN_E56_MAX (0x00000001U)
  6217. #define CSL_EVETPCC_SERH_RN_E58_MASK (0x04000000U)
  6218. #define CSL_EVETPCC_SERH_RN_E58_SHIFT (26U)
  6219. #define CSL_EVETPCC_SERH_RN_E58_RESETVAL (0x00000000U)
  6220. #define CSL_EVETPCC_SERH_RN_E58_MAX (0x00000001U)
  6221. #define CSL_EVETPCC_SERH_RN_E57_MASK (0x02000000U)
  6222. #define CSL_EVETPCC_SERH_RN_E57_SHIFT (25U)
  6223. #define CSL_EVETPCC_SERH_RN_E57_RESETVAL (0x00000000U)
  6224. #define CSL_EVETPCC_SERH_RN_E57_MAX (0x00000001U)
  6225. #define CSL_EVETPCC_SERH_RN_E60_MASK (0x10000000U)
  6226. #define CSL_EVETPCC_SERH_RN_E60_SHIFT (28U)
  6227. #define CSL_EVETPCC_SERH_RN_E60_RESETVAL (0x00000000U)
  6228. #define CSL_EVETPCC_SERH_RN_E60_MAX (0x00000001U)
  6229. #define CSL_EVETPCC_SERH_RN_E59_MASK (0x08000000U)
  6230. #define CSL_EVETPCC_SERH_RN_E59_SHIFT (27U)
  6231. #define CSL_EVETPCC_SERH_RN_E59_RESETVAL (0x00000000U)
  6232. #define CSL_EVETPCC_SERH_RN_E59_MAX (0x00000001U)
  6233. #define CSL_EVETPCC_SERH_RN_E61_MASK (0x20000000U)
  6234. #define CSL_EVETPCC_SERH_RN_E61_SHIFT (29U)
  6235. #define CSL_EVETPCC_SERH_RN_E61_RESETVAL (0x00000000U)
  6236. #define CSL_EVETPCC_SERH_RN_E61_MAX (0x00000001U)
  6237. #define CSL_EVETPCC_SERH_RN_E37_MASK (0x00000020U)
  6238. #define CSL_EVETPCC_SERH_RN_E37_SHIFT (5U)
  6239. #define CSL_EVETPCC_SERH_RN_E37_RESETVAL (0x00000000U)
  6240. #define CSL_EVETPCC_SERH_RN_E37_MAX (0x00000001U)
  6241. #define CSL_EVETPCC_SERH_RN_E47_MASK (0x00008000U)
  6242. #define CSL_EVETPCC_SERH_RN_E47_SHIFT (15U)
  6243. #define CSL_EVETPCC_SERH_RN_E47_RESETVAL (0x00000000U)
  6244. #define CSL_EVETPCC_SERH_RN_E47_MAX (0x00000001U)
  6245. #define CSL_EVETPCC_SERH_RN_E38_MASK (0x00000040U)
  6246. #define CSL_EVETPCC_SERH_RN_E38_SHIFT (6U)
  6247. #define CSL_EVETPCC_SERH_RN_E38_RESETVAL (0x00000000U)
  6248. #define CSL_EVETPCC_SERH_RN_E38_MAX (0x00000001U)
  6249. #define CSL_EVETPCC_SERH_RN_E35_MASK (0x00000008U)
  6250. #define CSL_EVETPCC_SERH_RN_E35_SHIFT (3U)
  6251. #define CSL_EVETPCC_SERH_RN_E35_RESETVAL (0x00000000U)
  6252. #define CSL_EVETPCC_SERH_RN_E35_MAX (0x00000001U)
  6253. #define CSL_EVETPCC_SERH_RN_E48_MASK (0x00010000U)
  6254. #define CSL_EVETPCC_SERH_RN_E48_SHIFT (16U)
  6255. #define CSL_EVETPCC_SERH_RN_E48_RESETVAL (0x00000000U)
  6256. #define CSL_EVETPCC_SERH_RN_E48_MAX (0x00000001U)
  6257. #define CSL_EVETPCC_SERH_RN_E62_MASK (0x40000000U)
  6258. #define CSL_EVETPCC_SERH_RN_E62_SHIFT (30U)
  6259. #define CSL_EVETPCC_SERH_RN_E62_RESETVAL (0x00000000U)
  6260. #define CSL_EVETPCC_SERH_RN_E62_MAX (0x00000001U)
  6261. #define CSL_EVETPCC_SERH_RN_E39_MASK (0x00000080U)
  6262. #define CSL_EVETPCC_SERH_RN_E39_SHIFT (7U)
  6263. #define CSL_EVETPCC_SERH_RN_E39_RESETVAL (0x00000000U)
  6264. #define CSL_EVETPCC_SERH_RN_E39_MAX (0x00000001U)
  6265. #define CSL_EVETPCC_SERH_RN_E63_MASK (0x80000000U)
  6266. #define CSL_EVETPCC_SERH_RN_E63_SHIFT (31U)
  6267. #define CSL_EVETPCC_SERH_RN_E63_RESETVAL (0x00000000U)
  6268. #define CSL_EVETPCC_SERH_RN_E63_MAX (0x00000001U)
  6269. #define CSL_EVETPCC_SERH_RN_E36_MASK (0x00000010U)
  6270. #define CSL_EVETPCC_SERH_RN_E36_SHIFT (4U)
  6271. #define CSL_EVETPCC_SERH_RN_E36_RESETVAL (0x00000000U)
  6272. #define CSL_EVETPCC_SERH_RN_E36_MAX (0x00000001U)
  6273. #define CSL_EVETPCC_SERH_RN_E49_MASK (0x00020000U)
  6274. #define CSL_EVETPCC_SERH_RN_E49_SHIFT (17U)
  6275. #define CSL_EVETPCC_SERH_RN_E49_RESETVAL (0x00000000U)
  6276. #define CSL_EVETPCC_SERH_RN_E49_MAX (0x00000001U)
  6277. #define CSL_EVETPCC_SERH_RN_E40_MASK (0x00000100U)
  6278. #define CSL_EVETPCC_SERH_RN_E40_SHIFT (8U)
  6279. #define CSL_EVETPCC_SERH_RN_E40_RESETVAL (0x00000000U)
  6280. #define CSL_EVETPCC_SERH_RN_E40_MAX (0x00000001U)
  6281. #define CSL_EVETPCC_SERH_RN_E33_MASK (0x00000002U)
  6282. #define CSL_EVETPCC_SERH_RN_E33_SHIFT (1U)
  6283. #define CSL_EVETPCC_SERH_RN_E33_RESETVAL (0x00000000U)
  6284. #define CSL_EVETPCC_SERH_RN_E33_MAX (0x00000001U)
  6285. #define CSL_EVETPCC_SERH_RN_E50_MASK (0x00040000U)
  6286. #define CSL_EVETPCC_SERH_RN_E50_SHIFT (18U)
  6287. #define CSL_EVETPCC_SERH_RN_E50_RESETVAL (0x00000000U)
  6288. #define CSL_EVETPCC_SERH_RN_E50_MAX (0x00000001U)
  6289. #define CSL_EVETPCC_SERH_RN_E41_MASK (0x00000200U)
  6290. #define CSL_EVETPCC_SERH_RN_E41_SHIFT (9U)
  6291. #define CSL_EVETPCC_SERH_RN_E41_RESETVAL (0x00000000U)
  6292. #define CSL_EVETPCC_SERH_RN_E41_MAX (0x00000001U)
  6293. #define CSL_EVETPCC_SERH_RN_E34_MASK (0x00000004U)
  6294. #define CSL_EVETPCC_SERH_RN_E34_SHIFT (2U)
  6295. #define CSL_EVETPCC_SERH_RN_E34_RESETVAL (0x00000000U)
  6296. #define CSL_EVETPCC_SERH_RN_E34_MAX (0x00000001U)
  6297. #define CSL_EVETPCC_SERH_RN_E51_MASK (0x00080000U)
  6298. #define CSL_EVETPCC_SERH_RN_E51_SHIFT (19U)
  6299. #define CSL_EVETPCC_SERH_RN_E51_RESETVAL (0x00000000U)
  6300. #define CSL_EVETPCC_SERH_RN_E51_MAX (0x00000001U)
  6301. #define CSL_EVETPCC_SERH_RN_RESETVAL (0x00000000U)
  6302. /* ESR_RN */
  6303. #define CSL_EVETPCC_ESR_RN_E3_MASK (0x00000008U)
  6304. #define CSL_EVETPCC_ESR_RN_E3_SHIFT (3U)
  6305. #define CSL_EVETPCC_ESR_RN_E3_RESETVAL (0x00000000U)
  6306. #define CSL_EVETPCC_ESR_RN_E3_MAX (0x00000001U)
  6307. #define CSL_EVETPCC_ESR_RN_E6_MASK (0x00000040U)
  6308. #define CSL_EVETPCC_ESR_RN_E6_SHIFT (6U)
  6309. #define CSL_EVETPCC_ESR_RN_E6_RESETVAL (0x00000000U)
  6310. #define CSL_EVETPCC_ESR_RN_E6_MAX (0x00000001U)
  6311. #define CSL_EVETPCC_ESR_RN_E20_MASK (0x00100000U)
  6312. #define CSL_EVETPCC_ESR_RN_E20_SHIFT (20U)
  6313. #define CSL_EVETPCC_ESR_RN_E20_RESETVAL (0x00000000U)
  6314. #define CSL_EVETPCC_ESR_RN_E20_MAX (0x00000001U)
  6315. #define CSL_EVETPCC_ESR_RN_E1_MASK (0x00000002U)
  6316. #define CSL_EVETPCC_ESR_RN_E1_SHIFT (1U)
  6317. #define CSL_EVETPCC_ESR_RN_E1_RESETVAL (0x00000000U)
  6318. #define CSL_EVETPCC_ESR_RN_E1_MAX (0x00000001U)
  6319. #define CSL_EVETPCC_ESR_RN_E4_MASK (0x00000010U)
  6320. #define CSL_EVETPCC_ESR_RN_E4_SHIFT (4U)
  6321. #define CSL_EVETPCC_ESR_RN_E4_RESETVAL (0x00000000U)
  6322. #define CSL_EVETPCC_ESR_RN_E4_MAX (0x00000001U)
  6323. #define CSL_EVETPCC_ESR_RN_E18_MASK (0x00040000U)
  6324. #define CSL_EVETPCC_ESR_RN_E18_SHIFT (18U)
  6325. #define CSL_EVETPCC_ESR_RN_E18_RESETVAL (0x00000000U)
  6326. #define CSL_EVETPCC_ESR_RN_E18_MAX (0x00000001U)
  6327. #define CSL_EVETPCC_ESR_RN_E7_MASK (0x00000080U)
  6328. #define CSL_EVETPCC_ESR_RN_E7_SHIFT (7U)
  6329. #define CSL_EVETPCC_ESR_RN_E7_RESETVAL (0x00000000U)
  6330. #define CSL_EVETPCC_ESR_RN_E7_MAX (0x00000001U)
  6331. #define CSL_EVETPCC_ESR_RN_E11_MASK (0x00000800U)
  6332. #define CSL_EVETPCC_ESR_RN_E11_SHIFT (11U)
  6333. #define CSL_EVETPCC_ESR_RN_E11_RESETVAL (0x00000000U)
  6334. #define CSL_EVETPCC_ESR_RN_E11_MAX (0x00000001U)
  6335. #define CSL_EVETPCC_ESR_RN_E10_MASK (0x00000400U)
  6336. #define CSL_EVETPCC_ESR_RN_E10_SHIFT (10U)
  6337. #define CSL_EVETPCC_ESR_RN_E10_RESETVAL (0x00000000U)
  6338. #define CSL_EVETPCC_ESR_RN_E10_MAX (0x00000001U)
  6339. #define CSL_EVETPCC_ESR_RN_E5_MASK (0x00000020U)
  6340. #define CSL_EVETPCC_ESR_RN_E5_SHIFT (5U)
  6341. #define CSL_EVETPCC_ESR_RN_E5_RESETVAL (0x00000000U)
  6342. #define CSL_EVETPCC_ESR_RN_E5_MAX (0x00000001U)
  6343. #define CSL_EVETPCC_ESR_RN_E8_MASK (0x00000100U)
  6344. #define CSL_EVETPCC_ESR_RN_E8_SHIFT (8U)
  6345. #define CSL_EVETPCC_ESR_RN_E8_RESETVAL (0x00000000U)
  6346. #define CSL_EVETPCC_ESR_RN_E8_MAX (0x00000001U)
  6347. #define CSL_EVETPCC_ESR_RN_E22_MASK (0x00400000U)
  6348. #define CSL_EVETPCC_ESR_RN_E22_SHIFT (22U)
  6349. #define CSL_EVETPCC_ESR_RN_E22_RESETVAL (0x00000000U)
  6350. #define CSL_EVETPCC_ESR_RN_E22_MAX (0x00000001U)
  6351. #define CSL_EVETPCC_ESR_RN_E21_MASK (0x00200000U)
  6352. #define CSL_EVETPCC_ESR_RN_E21_SHIFT (21U)
  6353. #define CSL_EVETPCC_ESR_RN_E21_RESETVAL (0x00000000U)
  6354. #define CSL_EVETPCC_ESR_RN_E21_MAX (0x00000001U)
  6355. #define CSL_EVETPCC_ESR_RN_E23_MASK (0x00800000U)
  6356. #define CSL_EVETPCC_ESR_RN_E23_SHIFT (23U)
  6357. #define CSL_EVETPCC_ESR_RN_E23_RESETVAL (0x00000000U)
  6358. #define CSL_EVETPCC_ESR_RN_E23_MAX (0x00000001U)
  6359. #define CSL_EVETPCC_ESR_RN_E31_MASK (0x80000000U)
  6360. #define CSL_EVETPCC_ESR_RN_E31_SHIFT (31U)
  6361. #define CSL_EVETPCC_ESR_RN_E31_RESETVAL (0x00000000U)
  6362. #define CSL_EVETPCC_ESR_RN_E31_MAX (0x00000001U)
  6363. #define CSL_EVETPCC_ESR_RN_E15_MASK (0x00008000U)
  6364. #define CSL_EVETPCC_ESR_RN_E15_SHIFT (15U)
  6365. #define CSL_EVETPCC_ESR_RN_E15_RESETVAL (0x00000000U)
  6366. #define CSL_EVETPCC_ESR_RN_E15_MAX (0x00000001U)
  6367. #define CSL_EVETPCC_ESR_RN_E26_MASK (0x04000000U)
  6368. #define CSL_EVETPCC_ESR_RN_E26_SHIFT (26U)
  6369. #define CSL_EVETPCC_ESR_RN_E26_RESETVAL (0x00000000U)
  6370. #define CSL_EVETPCC_ESR_RN_E26_MAX (0x00000001U)
  6371. #define CSL_EVETPCC_ESR_RN_E24_MASK (0x01000000U)
  6372. #define CSL_EVETPCC_ESR_RN_E24_SHIFT (24U)
  6373. #define CSL_EVETPCC_ESR_RN_E24_RESETVAL (0x00000000U)
  6374. #define CSL_EVETPCC_ESR_RN_E24_MAX (0x00000001U)
  6375. #define CSL_EVETPCC_ESR_RN_E12_MASK (0x00001000U)
  6376. #define CSL_EVETPCC_ESR_RN_E12_SHIFT (12U)
  6377. #define CSL_EVETPCC_ESR_RN_E12_RESETVAL (0x00000000U)
  6378. #define CSL_EVETPCC_ESR_RN_E12_MAX (0x00000001U)
  6379. #define CSL_EVETPCC_ESR_RN_E13_MASK (0x00002000U)
  6380. #define CSL_EVETPCC_ESR_RN_E13_SHIFT (13U)
  6381. #define CSL_EVETPCC_ESR_RN_E13_RESETVAL (0x00000000U)
  6382. #define CSL_EVETPCC_ESR_RN_E13_MAX (0x00000001U)
  6383. #define CSL_EVETPCC_ESR_RN_E9_MASK (0x00000200U)
  6384. #define CSL_EVETPCC_ESR_RN_E9_SHIFT (9U)
  6385. #define CSL_EVETPCC_ESR_RN_E9_RESETVAL (0x00000000U)
  6386. #define CSL_EVETPCC_ESR_RN_E9_MAX (0x00000001U)
  6387. #define CSL_EVETPCC_ESR_RN_E28_MASK (0x10000000U)
  6388. #define CSL_EVETPCC_ESR_RN_E28_SHIFT (28U)
  6389. #define CSL_EVETPCC_ESR_RN_E28_RESETVAL (0x00000000U)
  6390. #define CSL_EVETPCC_ESR_RN_E28_MAX (0x00000001U)
  6391. #define CSL_EVETPCC_ESR_RN_E25_MASK (0x02000000U)
  6392. #define CSL_EVETPCC_ESR_RN_E25_SHIFT (25U)
  6393. #define CSL_EVETPCC_ESR_RN_E25_RESETVAL (0x00000000U)
  6394. #define CSL_EVETPCC_ESR_RN_E25_MAX (0x00000001U)
  6395. #define CSL_EVETPCC_ESR_RN_E0_MASK (0x00000001U)
  6396. #define CSL_EVETPCC_ESR_RN_E0_SHIFT (0U)
  6397. #define CSL_EVETPCC_ESR_RN_E0_RESETVAL (0x00000000U)
  6398. #define CSL_EVETPCC_ESR_RN_E0_MAX (0x00000001U)
  6399. #define CSL_EVETPCC_ESR_RN_E19_MASK (0x00080000U)
  6400. #define CSL_EVETPCC_ESR_RN_E19_SHIFT (19U)
  6401. #define CSL_EVETPCC_ESR_RN_E19_RESETVAL (0x00000000U)
  6402. #define CSL_EVETPCC_ESR_RN_E19_MAX (0x00000001U)
  6403. #define CSL_EVETPCC_ESR_RN_E16_MASK (0x00010000U)
  6404. #define CSL_EVETPCC_ESR_RN_E16_SHIFT (16U)
  6405. #define CSL_EVETPCC_ESR_RN_E16_RESETVAL (0x00000000U)
  6406. #define CSL_EVETPCC_ESR_RN_E16_MAX (0x00000001U)
  6407. #define CSL_EVETPCC_ESR_RN_E2_MASK (0x00000004U)
  6408. #define CSL_EVETPCC_ESR_RN_E2_SHIFT (2U)
  6409. #define CSL_EVETPCC_ESR_RN_E2_RESETVAL (0x00000000U)
  6410. #define CSL_EVETPCC_ESR_RN_E2_MAX (0x00000001U)
  6411. #define CSL_EVETPCC_ESR_RN_E27_MASK (0x08000000U)
  6412. #define CSL_EVETPCC_ESR_RN_E27_SHIFT (27U)
  6413. #define CSL_EVETPCC_ESR_RN_E27_RESETVAL (0x00000000U)
  6414. #define CSL_EVETPCC_ESR_RN_E27_MAX (0x00000001U)
  6415. #define CSL_EVETPCC_ESR_RN_E17_MASK (0x00020000U)
  6416. #define CSL_EVETPCC_ESR_RN_E17_SHIFT (17U)
  6417. #define CSL_EVETPCC_ESR_RN_E17_RESETVAL (0x00000000U)
  6418. #define CSL_EVETPCC_ESR_RN_E17_MAX (0x00000001U)
  6419. #define CSL_EVETPCC_ESR_RN_E30_MASK (0x40000000U)
  6420. #define CSL_EVETPCC_ESR_RN_E30_SHIFT (30U)
  6421. #define CSL_EVETPCC_ESR_RN_E30_RESETVAL (0x00000000U)
  6422. #define CSL_EVETPCC_ESR_RN_E30_MAX (0x00000001U)
  6423. #define CSL_EVETPCC_ESR_RN_E14_MASK (0x00004000U)
  6424. #define CSL_EVETPCC_ESR_RN_E14_SHIFT (14U)
  6425. #define CSL_EVETPCC_ESR_RN_E14_RESETVAL (0x00000000U)
  6426. #define CSL_EVETPCC_ESR_RN_E14_MAX (0x00000001U)
  6427. #define CSL_EVETPCC_ESR_RN_E29_MASK (0x20000000U)
  6428. #define CSL_EVETPCC_ESR_RN_E29_SHIFT (29U)
  6429. #define CSL_EVETPCC_ESR_RN_E29_RESETVAL (0x00000000U)
  6430. #define CSL_EVETPCC_ESR_RN_E29_MAX (0x00000001U)
  6431. #define CSL_EVETPCC_ESR_RN_RESETVAL (0x00000000U)
  6432. /* EECR_RN */
  6433. #define CSL_EVETPCC_EECR_RN_E30_MASK (0x40000000U)
  6434. #define CSL_EVETPCC_EECR_RN_E30_SHIFT (30U)
  6435. #define CSL_EVETPCC_EECR_RN_E30_RESETVAL (0x00000000U)
  6436. #define CSL_EVETPCC_EECR_RN_E30_MAX (0x00000001U)
  6437. #define CSL_EVETPCC_EECR_RN_E25_MASK (0x02000000U)
  6438. #define CSL_EVETPCC_EECR_RN_E25_SHIFT (25U)
  6439. #define CSL_EVETPCC_EECR_RN_E25_RESETVAL (0x00000000U)
  6440. #define CSL_EVETPCC_EECR_RN_E25_MAX (0x00000001U)
  6441. #define CSL_EVETPCC_EECR_RN_E14_MASK (0x00004000U)
  6442. #define CSL_EVETPCC_EECR_RN_E14_SHIFT (14U)
  6443. #define CSL_EVETPCC_EECR_RN_E14_RESETVAL (0x00000000U)
  6444. #define CSL_EVETPCC_EECR_RN_E14_MAX (0x00000001U)
  6445. #define CSL_EVETPCC_EECR_RN_E15_MASK (0x00008000U)
  6446. #define CSL_EVETPCC_EECR_RN_E15_SHIFT (15U)
  6447. #define CSL_EVETPCC_EECR_RN_E15_RESETVAL (0x00000000U)
  6448. #define CSL_EVETPCC_EECR_RN_E15_MAX (0x00000001U)
  6449. #define CSL_EVETPCC_EECR_RN_E5_MASK (0x00000020U)
  6450. #define CSL_EVETPCC_EECR_RN_E5_SHIFT (5U)
  6451. #define CSL_EVETPCC_EECR_RN_E5_RESETVAL (0x00000000U)
  6452. #define CSL_EVETPCC_EECR_RN_E5_MAX (0x00000001U)
  6453. #define CSL_EVETPCC_EECR_RN_E31_MASK (0x80000000U)
  6454. #define CSL_EVETPCC_EECR_RN_E31_SHIFT (31U)
  6455. #define CSL_EVETPCC_EECR_RN_E31_RESETVAL (0x00000000U)
  6456. #define CSL_EVETPCC_EECR_RN_E31_MAX (0x00000001U)
  6457. #define CSL_EVETPCC_EECR_RN_E24_MASK (0x01000000U)
  6458. #define CSL_EVETPCC_EECR_RN_E24_SHIFT (24U)
  6459. #define CSL_EVETPCC_EECR_RN_E24_RESETVAL (0x00000000U)
  6460. #define CSL_EVETPCC_EECR_RN_E24_MAX (0x00000001U)
  6461. #define CSL_EVETPCC_EECR_RN_E28_MASK (0x10000000U)
  6462. #define CSL_EVETPCC_EECR_RN_E28_SHIFT (28U)
  6463. #define CSL_EVETPCC_EECR_RN_E28_RESETVAL (0x00000000U)
  6464. #define CSL_EVETPCC_EECR_RN_E28_MAX (0x00000001U)
  6465. #define CSL_EVETPCC_EECR_RN_E6_MASK (0x00000040U)
  6466. #define CSL_EVETPCC_EECR_RN_E6_SHIFT (6U)
  6467. #define CSL_EVETPCC_EECR_RN_E6_RESETVAL (0x00000000U)
  6468. #define CSL_EVETPCC_EECR_RN_E6_MAX (0x00000001U)
  6469. #define CSL_EVETPCC_EECR_RN_E16_MASK (0x00010000U)
  6470. #define CSL_EVETPCC_EECR_RN_E16_SHIFT (16U)
  6471. #define CSL_EVETPCC_EECR_RN_E16_RESETVAL (0x00000000U)
  6472. #define CSL_EVETPCC_EECR_RN_E16_MAX (0x00000001U)
  6473. #define CSL_EVETPCC_EECR_RN_E29_MASK (0x20000000U)
  6474. #define CSL_EVETPCC_EECR_RN_E29_SHIFT (29U)
  6475. #define CSL_EVETPCC_EECR_RN_E29_RESETVAL (0x00000000U)
  6476. #define CSL_EVETPCC_EECR_RN_E29_MAX (0x00000001U)
  6477. #define CSL_EVETPCC_EECR_RN_E26_MASK (0x04000000U)
  6478. #define CSL_EVETPCC_EECR_RN_E26_SHIFT (26U)
  6479. #define CSL_EVETPCC_EECR_RN_E26_RESETVAL (0x00000000U)
  6480. #define CSL_EVETPCC_EECR_RN_E26_MAX (0x00000001U)
  6481. #define CSL_EVETPCC_EECR_RN_E8_MASK (0x00000100U)
  6482. #define CSL_EVETPCC_EECR_RN_E8_SHIFT (8U)
  6483. #define CSL_EVETPCC_EECR_RN_E8_RESETVAL (0x00000000U)
  6484. #define CSL_EVETPCC_EECR_RN_E8_MAX (0x00000001U)
  6485. #define CSL_EVETPCC_EECR_RN_E18_MASK (0x00040000U)
  6486. #define CSL_EVETPCC_EECR_RN_E18_SHIFT (18U)
  6487. #define CSL_EVETPCC_EECR_RN_E18_RESETVAL (0x00000000U)
  6488. #define CSL_EVETPCC_EECR_RN_E18_MAX (0x00000001U)
  6489. #define CSL_EVETPCC_EECR_RN_E7_MASK (0x00000080U)
  6490. #define CSL_EVETPCC_EECR_RN_E7_SHIFT (7U)
  6491. #define CSL_EVETPCC_EECR_RN_E7_RESETVAL (0x00000000U)
  6492. #define CSL_EVETPCC_EECR_RN_E7_MAX (0x00000001U)
  6493. #define CSL_EVETPCC_EECR_RN_E17_MASK (0x00020000U)
  6494. #define CSL_EVETPCC_EECR_RN_E17_SHIFT (17U)
  6495. #define CSL_EVETPCC_EECR_RN_E17_RESETVAL (0x00000000U)
  6496. #define CSL_EVETPCC_EECR_RN_E17_MAX (0x00000001U)
  6497. #define CSL_EVETPCC_EECR_RN_E10_MASK (0x00000400U)
  6498. #define CSL_EVETPCC_EECR_RN_E10_SHIFT (10U)
  6499. #define CSL_EVETPCC_EECR_RN_E10_RESETVAL (0x00000000U)
  6500. #define CSL_EVETPCC_EECR_RN_E10_MAX (0x00000001U)
  6501. #define CSL_EVETPCC_EECR_RN_E20_MASK (0x00100000U)
  6502. #define CSL_EVETPCC_EECR_RN_E20_SHIFT (20U)
  6503. #define CSL_EVETPCC_EECR_RN_E20_RESETVAL (0x00000000U)
  6504. #define CSL_EVETPCC_EECR_RN_E20_MAX (0x00000001U)
  6505. #define CSL_EVETPCC_EECR_RN_E9_MASK (0x00000200U)
  6506. #define CSL_EVETPCC_EECR_RN_E9_SHIFT (9U)
  6507. #define CSL_EVETPCC_EECR_RN_E9_RESETVAL (0x00000000U)
  6508. #define CSL_EVETPCC_EECR_RN_E9_MAX (0x00000001U)
  6509. #define CSL_EVETPCC_EECR_RN_E0_MASK (0x00000001U)
  6510. #define CSL_EVETPCC_EECR_RN_E0_SHIFT (0U)
  6511. #define CSL_EVETPCC_EECR_RN_E0_RESETVAL (0x00000000U)
  6512. #define CSL_EVETPCC_EECR_RN_E0_MAX (0x00000001U)
  6513. #define CSL_EVETPCC_EECR_RN_E19_MASK (0x00080000U)
  6514. #define CSL_EVETPCC_EECR_RN_E19_SHIFT (19U)
  6515. #define CSL_EVETPCC_EECR_RN_E19_RESETVAL (0x00000000U)
  6516. #define CSL_EVETPCC_EECR_RN_E19_MAX (0x00000001U)
  6517. #define CSL_EVETPCC_EECR_RN_E1_MASK (0x00000002U)
  6518. #define CSL_EVETPCC_EECR_RN_E1_SHIFT (1U)
  6519. #define CSL_EVETPCC_EECR_RN_E1_RESETVAL (0x00000000U)
  6520. #define CSL_EVETPCC_EECR_RN_E1_MAX (0x00000001U)
  6521. #define CSL_EVETPCC_EECR_RN_E12_MASK (0x00001000U)
  6522. #define CSL_EVETPCC_EECR_RN_E12_SHIFT (12U)
  6523. #define CSL_EVETPCC_EECR_RN_E12_RESETVAL (0x00000000U)
  6524. #define CSL_EVETPCC_EECR_RN_E12_MAX (0x00000001U)
  6525. #define CSL_EVETPCC_EECR_RN_E22_MASK (0x00400000U)
  6526. #define CSL_EVETPCC_EECR_RN_E22_SHIFT (22U)
  6527. #define CSL_EVETPCC_EECR_RN_E22_RESETVAL (0x00000000U)
  6528. #define CSL_EVETPCC_EECR_RN_E22_MAX (0x00000001U)
  6529. #define CSL_EVETPCC_EECR_RN_E2_MASK (0x00000004U)
  6530. #define CSL_EVETPCC_EECR_RN_E2_SHIFT (2U)
  6531. #define CSL_EVETPCC_EECR_RN_E2_RESETVAL (0x00000000U)
  6532. #define CSL_EVETPCC_EECR_RN_E2_MAX (0x00000001U)
  6533. #define CSL_EVETPCC_EECR_RN_E11_MASK (0x00000800U)
  6534. #define CSL_EVETPCC_EECR_RN_E11_SHIFT (11U)
  6535. #define CSL_EVETPCC_EECR_RN_E11_RESETVAL (0x00000000U)
  6536. #define CSL_EVETPCC_EECR_RN_E11_MAX (0x00000001U)
  6537. #define CSL_EVETPCC_EECR_RN_E21_MASK (0x00200000U)
  6538. #define CSL_EVETPCC_EECR_RN_E21_SHIFT (21U)
  6539. #define CSL_EVETPCC_EECR_RN_E21_RESETVAL (0x00000000U)
  6540. #define CSL_EVETPCC_EECR_RN_E21_MAX (0x00000001U)
  6541. #define CSL_EVETPCC_EECR_RN_E27_MASK (0x08000000U)
  6542. #define CSL_EVETPCC_EECR_RN_E27_SHIFT (27U)
  6543. #define CSL_EVETPCC_EECR_RN_E27_RESETVAL (0x00000000U)
  6544. #define CSL_EVETPCC_EECR_RN_E27_MAX (0x00000001U)
  6545. #define CSL_EVETPCC_EECR_RN_E3_MASK (0x00000008U)
  6546. #define CSL_EVETPCC_EECR_RN_E3_SHIFT (3U)
  6547. #define CSL_EVETPCC_EECR_RN_E3_RESETVAL (0x00000000U)
  6548. #define CSL_EVETPCC_EECR_RN_E3_MAX (0x00000001U)
  6549. #define CSL_EVETPCC_EECR_RN_E23_MASK (0x00800000U)
  6550. #define CSL_EVETPCC_EECR_RN_E23_SHIFT (23U)
  6551. #define CSL_EVETPCC_EECR_RN_E23_RESETVAL (0x00000000U)
  6552. #define CSL_EVETPCC_EECR_RN_E23_MAX (0x00000001U)
  6553. #define CSL_EVETPCC_EECR_RN_E4_MASK (0x00000010U)
  6554. #define CSL_EVETPCC_EECR_RN_E4_SHIFT (4U)
  6555. #define CSL_EVETPCC_EECR_RN_E4_RESETVAL (0x00000000U)
  6556. #define CSL_EVETPCC_EECR_RN_E4_MAX (0x00000001U)
  6557. #define CSL_EVETPCC_EECR_RN_E13_MASK (0x00002000U)
  6558. #define CSL_EVETPCC_EECR_RN_E13_SHIFT (13U)
  6559. #define CSL_EVETPCC_EECR_RN_E13_RESETVAL (0x00000000U)
  6560. #define CSL_EVETPCC_EECR_RN_E13_MAX (0x00000001U)
  6561. #define CSL_EVETPCC_EECR_RN_RESETVAL (0x00000000U)
  6562. /* ER_RN */
  6563. #define CSL_EVETPCC_ER_RN_E22_MASK (0x00400000U)
  6564. #define CSL_EVETPCC_ER_RN_E22_SHIFT (22U)
  6565. #define CSL_EVETPCC_ER_RN_E22_RESETVAL (0x00000000U)
  6566. #define CSL_EVETPCC_ER_RN_E22_MAX (0x00000001U)
  6567. #define CSL_EVETPCC_ER_RN_E2_MASK (0x00000004U)
  6568. #define CSL_EVETPCC_ER_RN_E2_SHIFT (2U)
  6569. #define CSL_EVETPCC_ER_RN_E2_RESETVAL (0x00000000U)
  6570. #define CSL_EVETPCC_ER_RN_E2_MAX (0x00000001U)
  6571. #define CSL_EVETPCC_ER_RN_E19_MASK (0x00080000U)
  6572. #define CSL_EVETPCC_ER_RN_E19_SHIFT (19U)
  6573. #define CSL_EVETPCC_ER_RN_E19_RESETVAL (0x00000000U)
  6574. #define CSL_EVETPCC_ER_RN_E19_MAX (0x00000001U)
  6575. #define CSL_EVETPCC_ER_RN_E5_MASK (0x00000020U)
  6576. #define CSL_EVETPCC_ER_RN_E5_SHIFT (5U)
  6577. #define CSL_EVETPCC_ER_RN_E5_RESETVAL (0x00000000U)
  6578. #define CSL_EVETPCC_ER_RN_E5_MAX (0x00000001U)
  6579. #define CSL_EVETPCC_ER_RN_E29_MASK (0x20000000U)
  6580. #define CSL_EVETPCC_ER_RN_E29_SHIFT (29U)
  6581. #define CSL_EVETPCC_ER_RN_E29_RESETVAL (0x00000000U)
  6582. #define CSL_EVETPCC_ER_RN_E29_MAX (0x00000001U)
  6583. #define CSL_EVETPCC_ER_RN_E18_MASK (0x00040000U)
  6584. #define CSL_EVETPCC_ER_RN_E18_SHIFT (18U)
  6585. #define CSL_EVETPCC_ER_RN_E18_RESETVAL (0x00000000U)
  6586. #define CSL_EVETPCC_ER_RN_E18_MAX (0x00000001U)
  6587. #define CSL_EVETPCC_ER_RN_E6_MASK (0x00000040U)
  6588. #define CSL_EVETPCC_ER_RN_E6_SHIFT (6U)
  6589. #define CSL_EVETPCC_ER_RN_E6_RESETVAL (0x00000000U)
  6590. #define CSL_EVETPCC_ER_RN_E6_MAX (0x00000001U)
  6591. #define CSL_EVETPCC_ER_RN_E21_MASK (0x00200000U)
  6592. #define CSL_EVETPCC_ER_RN_E21_SHIFT (21U)
  6593. #define CSL_EVETPCC_ER_RN_E21_RESETVAL (0x00000000U)
  6594. #define CSL_EVETPCC_ER_RN_E21_MAX (0x00000001U)
  6595. #define CSL_EVETPCC_ER_RN_E3_MASK (0x00000008U)
  6596. #define CSL_EVETPCC_ER_RN_E3_SHIFT (3U)
  6597. #define CSL_EVETPCC_ER_RN_E3_RESETVAL (0x00000000U)
  6598. #define CSL_EVETPCC_ER_RN_E3_MAX (0x00000001U)
  6599. #define CSL_EVETPCC_ER_RN_E31_MASK (0x80000000U)
  6600. #define CSL_EVETPCC_ER_RN_E31_SHIFT (31U)
  6601. #define CSL_EVETPCC_ER_RN_E31_RESETVAL (0x00000000U)
  6602. #define CSL_EVETPCC_ER_RN_E31_MAX (0x00000001U)
  6603. #define CSL_EVETPCC_ER_RN_E20_MASK (0x00100000U)
  6604. #define CSL_EVETPCC_ER_RN_E20_SHIFT (20U)
  6605. #define CSL_EVETPCC_ER_RN_E20_RESETVAL (0x00000000U)
  6606. #define CSL_EVETPCC_ER_RN_E20_MAX (0x00000001U)
  6607. #define CSL_EVETPCC_ER_RN_E4_MASK (0x00000010U)
  6608. #define CSL_EVETPCC_ER_RN_E4_SHIFT (4U)
  6609. #define CSL_EVETPCC_ER_RN_E4_RESETVAL (0x00000000U)
  6610. #define CSL_EVETPCC_ER_RN_E4_MAX (0x00000001U)
  6611. #define CSL_EVETPCC_ER_RN_E9_MASK (0x00000200U)
  6612. #define CSL_EVETPCC_ER_RN_E9_SHIFT (9U)
  6613. #define CSL_EVETPCC_ER_RN_E9_RESETVAL (0x00000000U)
  6614. #define CSL_EVETPCC_ER_RN_E9_MAX (0x00000001U)
  6615. #define CSL_EVETPCC_ER_RN_E28_MASK (0x10000000U)
  6616. #define CSL_EVETPCC_ER_RN_E28_SHIFT (28U)
  6617. #define CSL_EVETPCC_ER_RN_E28_RESETVAL (0x00000000U)
  6618. #define CSL_EVETPCC_ER_RN_E28_MAX (0x00000001U)
  6619. #define CSL_EVETPCC_ER_RN_E14_MASK (0x00004000U)
  6620. #define CSL_EVETPCC_ER_RN_E14_SHIFT (14U)
  6621. #define CSL_EVETPCC_ER_RN_E14_RESETVAL (0x00000000U)
  6622. #define CSL_EVETPCC_ER_RN_E14_MAX (0x00000001U)
  6623. #define CSL_EVETPCC_ER_RN_E10_MASK (0x00000400U)
  6624. #define CSL_EVETPCC_ER_RN_E10_SHIFT (10U)
  6625. #define CSL_EVETPCC_ER_RN_E10_RESETVAL (0x00000000U)
  6626. #define CSL_EVETPCC_ER_RN_E10_MAX (0x00000001U)
  6627. #define CSL_EVETPCC_ER_RN_E27_MASK (0x08000000U)
  6628. #define CSL_EVETPCC_ER_RN_E27_SHIFT (27U)
  6629. #define CSL_EVETPCC_ER_RN_E27_RESETVAL (0x00000000U)
  6630. #define CSL_EVETPCC_ER_RN_E27_MAX (0x00000001U)
  6631. #define CSL_EVETPCC_ER_RN_E7_MASK (0x00000080U)
  6632. #define CSL_EVETPCC_ER_RN_E7_SHIFT (7U)
  6633. #define CSL_EVETPCC_ER_RN_E7_RESETVAL (0x00000000U)
  6634. #define CSL_EVETPCC_ER_RN_E7_MAX (0x00000001U)
  6635. #define CSL_EVETPCC_ER_RN_E17_MASK (0x00020000U)
  6636. #define CSL_EVETPCC_ER_RN_E17_SHIFT (17U)
  6637. #define CSL_EVETPCC_ER_RN_E17_RESETVAL (0x00000000U)
  6638. #define CSL_EVETPCC_ER_RN_E17_MAX (0x00000001U)
  6639. #define CSL_EVETPCC_ER_RN_E8_MASK (0x00000100U)
  6640. #define CSL_EVETPCC_ER_RN_E8_SHIFT (8U)
  6641. #define CSL_EVETPCC_ER_RN_E8_RESETVAL (0x00000000U)
  6642. #define CSL_EVETPCC_ER_RN_E8_MAX (0x00000001U)
  6643. #define CSL_EVETPCC_ER_RN_E16_MASK (0x00010000U)
  6644. #define CSL_EVETPCC_ER_RN_E16_SHIFT (16U)
  6645. #define CSL_EVETPCC_ER_RN_E16_RESETVAL (0x00000000U)
  6646. #define CSL_EVETPCC_ER_RN_E16_MAX (0x00000001U)
  6647. #define CSL_EVETPCC_ER_RN_E30_MASK (0x40000000U)
  6648. #define CSL_EVETPCC_ER_RN_E30_SHIFT (30U)
  6649. #define CSL_EVETPCC_ER_RN_E30_RESETVAL (0x00000000U)
  6650. #define CSL_EVETPCC_ER_RN_E30_MAX (0x00000001U)
  6651. #define CSL_EVETPCC_ER_RN_E24_MASK (0x01000000U)
  6652. #define CSL_EVETPCC_ER_RN_E24_SHIFT (24U)
  6653. #define CSL_EVETPCC_ER_RN_E24_RESETVAL (0x00000000U)
  6654. #define CSL_EVETPCC_ER_RN_E24_MAX (0x00000001U)
  6655. #define CSL_EVETPCC_ER_RN_E23_MASK (0x00800000U)
  6656. #define CSL_EVETPCC_ER_RN_E23_SHIFT (23U)
  6657. #define CSL_EVETPCC_ER_RN_E23_RESETVAL (0x00000000U)
  6658. #define CSL_EVETPCC_ER_RN_E23_MAX (0x00000001U)
  6659. #define CSL_EVETPCC_ER_RN_E0_MASK (0x00000001U)
  6660. #define CSL_EVETPCC_ER_RN_E0_SHIFT (0U)
  6661. #define CSL_EVETPCC_ER_RN_E0_RESETVAL (0x00000000U)
  6662. #define CSL_EVETPCC_ER_RN_E0_MAX (0x00000001U)
  6663. #define CSL_EVETPCC_ER_RN_E13_MASK (0x00002000U)
  6664. #define CSL_EVETPCC_ER_RN_E13_SHIFT (13U)
  6665. #define CSL_EVETPCC_ER_RN_E13_RESETVAL (0x00000000U)
  6666. #define CSL_EVETPCC_ER_RN_E13_MAX (0x00000001U)
  6667. #define CSL_EVETPCC_ER_RN_E11_MASK (0x00000800U)
  6668. #define CSL_EVETPCC_ER_RN_E11_SHIFT (11U)
  6669. #define CSL_EVETPCC_ER_RN_E11_RESETVAL (0x00000000U)
  6670. #define CSL_EVETPCC_ER_RN_E11_MAX (0x00000001U)
  6671. #define CSL_EVETPCC_ER_RN_E26_MASK (0x04000000U)
  6672. #define CSL_EVETPCC_ER_RN_E26_SHIFT (26U)
  6673. #define CSL_EVETPCC_ER_RN_E26_RESETVAL (0x00000000U)
  6674. #define CSL_EVETPCC_ER_RN_E26_MAX (0x00000001U)
  6675. #define CSL_EVETPCC_ER_RN_E1_MASK (0x00000002U)
  6676. #define CSL_EVETPCC_ER_RN_E1_SHIFT (1U)
  6677. #define CSL_EVETPCC_ER_RN_E1_RESETVAL (0x00000000U)
  6678. #define CSL_EVETPCC_ER_RN_E1_MAX (0x00000001U)
  6679. #define CSL_EVETPCC_ER_RN_E12_MASK (0x00001000U)
  6680. #define CSL_EVETPCC_ER_RN_E12_SHIFT (12U)
  6681. #define CSL_EVETPCC_ER_RN_E12_RESETVAL (0x00000000U)
  6682. #define CSL_EVETPCC_ER_RN_E12_MAX (0x00000001U)
  6683. #define CSL_EVETPCC_ER_RN_E25_MASK (0x02000000U)
  6684. #define CSL_EVETPCC_ER_RN_E25_SHIFT (25U)
  6685. #define CSL_EVETPCC_ER_RN_E25_RESETVAL (0x00000000U)
  6686. #define CSL_EVETPCC_ER_RN_E25_MAX (0x00000001U)
  6687. #define CSL_EVETPCC_ER_RN_E15_MASK (0x00008000U)
  6688. #define CSL_EVETPCC_ER_RN_E15_SHIFT (15U)
  6689. #define CSL_EVETPCC_ER_RN_E15_RESETVAL (0x00000000U)
  6690. #define CSL_EVETPCC_ER_RN_E15_MAX (0x00000001U)
  6691. #define CSL_EVETPCC_ER_RN_RESETVAL (0x00000000U)
  6692. /* ICRH_RN */
  6693. #define CSL_EVETPCC_ICRH_RN_I37_MASK (0x00000020U)
  6694. #define CSL_EVETPCC_ICRH_RN_I37_SHIFT (5U)
  6695. #define CSL_EVETPCC_ICRH_RN_I37_RESETVAL (0x00000000U)
  6696. #define CSL_EVETPCC_ICRH_RN_I37_MAX (0x00000001U)
  6697. #define CSL_EVETPCC_ICRH_RN_I47_MASK (0x00008000U)
  6698. #define CSL_EVETPCC_ICRH_RN_I47_SHIFT (15U)
  6699. #define CSL_EVETPCC_ICRH_RN_I47_RESETVAL (0x00000000U)
  6700. #define CSL_EVETPCC_ICRH_RN_I47_MAX (0x00000001U)
  6701. #define CSL_EVETPCC_ICRH_RN_I53_MASK (0x00200000U)
  6702. #define CSL_EVETPCC_ICRH_RN_I53_SHIFT (21U)
  6703. #define CSL_EVETPCC_ICRH_RN_I53_RESETVAL (0x00000000U)
  6704. #define CSL_EVETPCC_ICRH_RN_I53_MAX (0x00000001U)
  6705. #define CSL_EVETPCC_ICRH_RN_I36_MASK (0x00000010U)
  6706. #define CSL_EVETPCC_ICRH_RN_I36_SHIFT (4U)
  6707. #define CSL_EVETPCC_ICRH_RN_I36_RESETVAL (0x00000000U)
  6708. #define CSL_EVETPCC_ICRH_RN_I36_MAX (0x00000001U)
  6709. #define CSL_EVETPCC_ICRH_RN_I63_MASK (0x80000000U)
  6710. #define CSL_EVETPCC_ICRH_RN_I63_SHIFT (31U)
  6711. #define CSL_EVETPCC_ICRH_RN_I63_RESETVAL (0x00000000U)
  6712. #define CSL_EVETPCC_ICRH_RN_I63_MAX (0x00000001U)
  6713. #define CSL_EVETPCC_ICRH_RN_I46_MASK (0x00004000U)
  6714. #define CSL_EVETPCC_ICRH_RN_I46_SHIFT (14U)
  6715. #define CSL_EVETPCC_ICRH_RN_I46_RESETVAL (0x00000000U)
  6716. #define CSL_EVETPCC_ICRH_RN_I46_MAX (0x00000001U)
  6717. #define CSL_EVETPCC_ICRH_RN_I39_MASK (0x00000080U)
  6718. #define CSL_EVETPCC_ICRH_RN_I39_SHIFT (7U)
  6719. #define CSL_EVETPCC_ICRH_RN_I39_RESETVAL (0x00000000U)
  6720. #define CSL_EVETPCC_ICRH_RN_I39_MAX (0x00000001U)
  6721. #define CSL_EVETPCC_ICRH_RN_I49_MASK (0x00020000U)
  6722. #define CSL_EVETPCC_ICRH_RN_I49_SHIFT (17U)
  6723. #define CSL_EVETPCC_ICRH_RN_I49_RESETVAL (0x00000000U)
  6724. #define CSL_EVETPCC_ICRH_RN_I49_MAX (0x00000001U)
  6725. #define CSL_EVETPCC_ICRH_RN_I38_MASK (0x00000040U)
  6726. #define CSL_EVETPCC_ICRH_RN_I38_SHIFT (6U)
  6727. #define CSL_EVETPCC_ICRH_RN_I38_RESETVAL (0x00000000U)
  6728. #define CSL_EVETPCC_ICRH_RN_I38_MAX (0x00000001U)
  6729. #define CSL_EVETPCC_ICRH_RN_I48_MASK (0x00010000U)
  6730. #define CSL_EVETPCC_ICRH_RN_I48_SHIFT (16U)
  6731. #define CSL_EVETPCC_ICRH_RN_I48_RESETVAL (0x00000000U)
  6732. #define CSL_EVETPCC_ICRH_RN_I48_MAX (0x00000001U)
  6733. #define CSL_EVETPCC_ICRH_RN_I41_MASK (0x00000200U)
  6734. #define CSL_EVETPCC_ICRH_RN_I41_SHIFT (9U)
  6735. #define CSL_EVETPCC_ICRH_RN_I41_RESETVAL (0x00000000U)
  6736. #define CSL_EVETPCC_ICRH_RN_I41_MAX (0x00000001U)
  6737. #define CSL_EVETPCC_ICRH_RN_I51_MASK (0x00080000U)
  6738. #define CSL_EVETPCC_ICRH_RN_I51_SHIFT (19U)
  6739. #define CSL_EVETPCC_ICRH_RN_I51_RESETVAL (0x00000000U)
  6740. #define CSL_EVETPCC_ICRH_RN_I51_MAX (0x00000001U)
  6741. #define CSL_EVETPCC_ICRH_RN_I40_MASK (0x00000100U)
  6742. #define CSL_EVETPCC_ICRH_RN_I40_SHIFT (8U)
  6743. #define CSL_EVETPCC_ICRH_RN_I40_RESETVAL (0x00000000U)
  6744. #define CSL_EVETPCC_ICRH_RN_I40_MAX (0x00000001U)
  6745. #define CSL_EVETPCC_ICRH_RN_I50_MASK (0x00040000U)
  6746. #define CSL_EVETPCC_ICRH_RN_I50_SHIFT (18U)
  6747. #define CSL_EVETPCC_ICRH_RN_I50_RESETVAL (0x00000000U)
  6748. #define CSL_EVETPCC_ICRH_RN_I50_MAX (0x00000001U)
  6749. #define CSL_EVETPCC_ICRH_RN_I42_MASK (0x00000400U)
  6750. #define CSL_EVETPCC_ICRH_RN_I42_SHIFT (10U)
  6751. #define CSL_EVETPCC_ICRH_RN_I42_RESETVAL (0x00000000U)
  6752. #define CSL_EVETPCC_ICRH_RN_I42_MAX (0x00000001U)
  6753. #define CSL_EVETPCC_ICRH_RN_I62_MASK (0x40000000U)
  6754. #define CSL_EVETPCC_ICRH_RN_I62_SHIFT (30U)
  6755. #define CSL_EVETPCC_ICRH_RN_I62_RESETVAL (0x00000000U)
  6756. #define CSL_EVETPCC_ICRH_RN_I62_MAX (0x00000001U)
  6757. #define CSL_EVETPCC_ICRH_RN_I52_MASK (0x00100000U)
  6758. #define CSL_EVETPCC_ICRH_RN_I52_SHIFT (20U)
  6759. #define CSL_EVETPCC_ICRH_RN_I52_RESETVAL (0x00000000U)
  6760. #define CSL_EVETPCC_ICRH_RN_I52_MAX (0x00000001U)
  6761. #define CSL_EVETPCC_ICRH_RN_I61_MASK (0x20000000U)
  6762. #define CSL_EVETPCC_ICRH_RN_I61_SHIFT (29U)
  6763. #define CSL_EVETPCC_ICRH_RN_I61_RESETVAL (0x00000000U)
  6764. #define CSL_EVETPCC_ICRH_RN_I61_MAX (0x00000001U)
  6765. #define CSL_EVETPCC_ICRH_RN_I32_MASK (0x00000001U)
  6766. #define CSL_EVETPCC_ICRH_RN_I32_SHIFT (0U)
  6767. #define CSL_EVETPCC_ICRH_RN_I32_RESETVAL (0x00000000U)
  6768. #define CSL_EVETPCC_ICRH_RN_I32_MAX (0x00000001U)
  6769. #define CSL_EVETPCC_ICRH_RN_I60_MASK (0x10000000U)
  6770. #define CSL_EVETPCC_ICRH_RN_I60_SHIFT (28U)
  6771. #define CSL_EVETPCC_ICRH_RN_I60_RESETVAL (0x00000000U)
  6772. #define CSL_EVETPCC_ICRH_RN_I60_MAX (0x00000001U)
  6773. #define CSL_EVETPCC_ICRH_RN_I59_MASK (0x08000000U)
  6774. #define CSL_EVETPCC_ICRH_RN_I59_SHIFT (27U)
  6775. #define CSL_EVETPCC_ICRH_RN_I59_RESETVAL (0x00000000U)
  6776. #define CSL_EVETPCC_ICRH_RN_I59_MAX (0x00000001U)
  6777. #define CSL_EVETPCC_ICRH_RN_I58_MASK (0x04000000U)
  6778. #define CSL_EVETPCC_ICRH_RN_I58_SHIFT (26U)
  6779. #define CSL_EVETPCC_ICRH_RN_I58_RESETVAL (0x00000000U)
  6780. #define CSL_EVETPCC_ICRH_RN_I58_MAX (0x00000001U)
  6781. #define CSL_EVETPCC_ICRH_RN_I57_MASK (0x02000000U)
  6782. #define CSL_EVETPCC_ICRH_RN_I57_SHIFT (25U)
  6783. #define CSL_EVETPCC_ICRH_RN_I57_RESETVAL (0x00000000U)
  6784. #define CSL_EVETPCC_ICRH_RN_I57_MAX (0x00000001U)
  6785. #define CSL_EVETPCC_ICRH_RN_I33_MASK (0x00000002U)
  6786. #define CSL_EVETPCC_ICRH_RN_I33_SHIFT (1U)
  6787. #define CSL_EVETPCC_ICRH_RN_I33_RESETVAL (0x00000000U)
  6788. #define CSL_EVETPCC_ICRH_RN_I33_MAX (0x00000001U)
  6789. #define CSL_EVETPCC_ICRH_RN_I43_MASK (0x00000800U)
  6790. #define CSL_EVETPCC_ICRH_RN_I43_SHIFT (11U)
  6791. #define CSL_EVETPCC_ICRH_RN_I43_RESETVAL (0x00000000U)
  6792. #define CSL_EVETPCC_ICRH_RN_I43_MAX (0x00000001U)
  6793. #define CSL_EVETPCC_ICRH_RN_I56_MASK (0x01000000U)
  6794. #define CSL_EVETPCC_ICRH_RN_I56_SHIFT (24U)
  6795. #define CSL_EVETPCC_ICRH_RN_I56_RESETVAL (0x00000000U)
  6796. #define CSL_EVETPCC_ICRH_RN_I56_MAX (0x00000001U)
  6797. #define CSL_EVETPCC_ICRH_RN_I35_MASK (0x00000008U)
  6798. #define CSL_EVETPCC_ICRH_RN_I35_SHIFT (3U)
  6799. #define CSL_EVETPCC_ICRH_RN_I35_RESETVAL (0x00000000U)
  6800. #define CSL_EVETPCC_ICRH_RN_I35_MAX (0x00000001U)
  6801. #define CSL_EVETPCC_ICRH_RN_I55_MASK (0x00800000U)
  6802. #define CSL_EVETPCC_ICRH_RN_I55_SHIFT (23U)
  6803. #define CSL_EVETPCC_ICRH_RN_I55_RESETVAL (0x00000000U)
  6804. #define CSL_EVETPCC_ICRH_RN_I55_MAX (0x00000001U)
  6805. #define CSL_EVETPCC_ICRH_RN_I45_MASK (0x00002000U)
  6806. #define CSL_EVETPCC_ICRH_RN_I45_SHIFT (13U)
  6807. #define CSL_EVETPCC_ICRH_RN_I45_RESETVAL (0x00000000U)
  6808. #define CSL_EVETPCC_ICRH_RN_I45_MAX (0x00000001U)
  6809. #define CSL_EVETPCC_ICRH_RN_I34_MASK (0x00000004U)
  6810. #define CSL_EVETPCC_ICRH_RN_I34_SHIFT (2U)
  6811. #define CSL_EVETPCC_ICRH_RN_I34_RESETVAL (0x00000000U)
  6812. #define CSL_EVETPCC_ICRH_RN_I34_MAX (0x00000001U)
  6813. #define CSL_EVETPCC_ICRH_RN_I54_MASK (0x00400000U)
  6814. #define CSL_EVETPCC_ICRH_RN_I54_SHIFT (22U)
  6815. #define CSL_EVETPCC_ICRH_RN_I54_RESETVAL (0x00000000U)
  6816. #define CSL_EVETPCC_ICRH_RN_I54_MAX (0x00000001U)
  6817. #define CSL_EVETPCC_ICRH_RN_I44_MASK (0x00001000U)
  6818. #define CSL_EVETPCC_ICRH_RN_I44_SHIFT (12U)
  6819. #define CSL_EVETPCC_ICRH_RN_I44_RESETVAL (0x00000000U)
  6820. #define CSL_EVETPCC_ICRH_RN_I44_MAX (0x00000001U)
  6821. #define CSL_EVETPCC_ICRH_RN_RESETVAL (0x00000000U)
  6822. /* EECRH_RN */
  6823. #define CSL_EVETPCC_EECRH_RN_E62_MASK (0x40000000U)
  6824. #define CSL_EVETPCC_EECRH_RN_E62_SHIFT (30U)
  6825. #define CSL_EVETPCC_EECRH_RN_E62_RESETVAL (0x00000000U)
  6826. #define CSL_EVETPCC_EECRH_RN_E62_MAX (0x00000001U)
  6827. #define CSL_EVETPCC_EECRH_RN_E37_MASK (0x00000020U)
  6828. #define CSL_EVETPCC_EECRH_RN_E37_SHIFT (5U)
  6829. #define CSL_EVETPCC_EECRH_RN_E37_RESETVAL (0x00000000U)
  6830. #define CSL_EVETPCC_EECRH_RN_E37_MAX (0x00000001U)
  6831. #define CSL_EVETPCC_EECRH_RN_E51_MASK (0x00080000U)
  6832. #define CSL_EVETPCC_EECRH_RN_E51_SHIFT (19U)
  6833. #define CSL_EVETPCC_EECRH_RN_E51_RESETVAL (0x00000000U)
  6834. #define CSL_EVETPCC_EECRH_RN_E51_MAX (0x00000001U)
  6835. #define CSL_EVETPCC_EECRH_RN_E36_MASK (0x00000010U)
  6836. #define CSL_EVETPCC_EECRH_RN_E36_SHIFT (4U)
  6837. #define CSL_EVETPCC_EECRH_RN_E36_RESETVAL (0x00000000U)
  6838. #define CSL_EVETPCC_EECRH_RN_E36_MAX (0x00000001U)
  6839. #define CSL_EVETPCC_EECRH_RN_E50_MASK (0x00040000U)
  6840. #define CSL_EVETPCC_EECRH_RN_E50_SHIFT (18U)
  6841. #define CSL_EVETPCC_EECRH_RN_E50_RESETVAL (0x00000000U)
  6842. #define CSL_EVETPCC_EECRH_RN_E50_MAX (0x00000001U)
  6843. #define CSL_EVETPCC_EECRH_RN_E35_MASK (0x00000008U)
  6844. #define CSL_EVETPCC_EECRH_RN_E35_SHIFT (3U)
  6845. #define CSL_EVETPCC_EECRH_RN_E35_RESETVAL (0x00000000U)
  6846. #define CSL_EVETPCC_EECRH_RN_E35_MAX (0x00000001U)
  6847. #define CSL_EVETPCC_EECRH_RN_E63_MASK (0x80000000U)
  6848. #define CSL_EVETPCC_EECRH_RN_E63_SHIFT (31U)
  6849. #define CSL_EVETPCC_EECRH_RN_E63_RESETVAL (0x00000000U)
  6850. #define CSL_EVETPCC_EECRH_RN_E63_MAX (0x00000001U)
  6851. #define CSL_EVETPCC_EECRH_RN_E54_MASK (0x00400000U)
  6852. #define CSL_EVETPCC_EECRH_RN_E54_SHIFT (22U)
  6853. #define CSL_EVETPCC_EECRH_RN_E54_RESETVAL (0x00000000U)
  6854. #define CSL_EVETPCC_EECRH_RN_E54_MAX (0x00000001U)
  6855. #define CSL_EVETPCC_EECRH_RN_E58_MASK (0x04000000U)
  6856. #define CSL_EVETPCC_EECRH_RN_E58_SHIFT (26U)
  6857. #define CSL_EVETPCC_EECRH_RN_E58_RESETVAL (0x00000000U)
  6858. #define CSL_EVETPCC_EECRH_RN_E58_MAX (0x00000001U)
  6859. #define CSL_EVETPCC_EECRH_RN_E48_MASK (0x00010000U)
  6860. #define CSL_EVETPCC_EECRH_RN_E48_SHIFT (16U)
  6861. #define CSL_EVETPCC_EECRH_RN_E48_RESETVAL (0x00000000U)
  6862. #define CSL_EVETPCC_EECRH_RN_E48_MAX (0x00000001U)
  6863. #define CSL_EVETPCC_EECRH_RN_E59_MASK (0x08000000U)
  6864. #define CSL_EVETPCC_EECRH_RN_E59_SHIFT (27U)
  6865. #define CSL_EVETPCC_EECRH_RN_E59_RESETVAL (0x00000000U)
  6866. #define CSL_EVETPCC_EECRH_RN_E59_MAX (0x00000001U)
  6867. #define CSL_EVETPCC_EECRH_RN_E53_MASK (0x00200000U)
  6868. #define CSL_EVETPCC_EECRH_RN_E53_SHIFT (21U)
  6869. #define CSL_EVETPCC_EECRH_RN_E53_RESETVAL (0x00000000U)
  6870. #define CSL_EVETPCC_EECRH_RN_E53_MAX (0x00000001U)
  6871. #define CSL_EVETPCC_EECRH_RN_E49_MASK (0x00020000U)
  6872. #define CSL_EVETPCC_EECRH_RN_E49_SHIFT (17U)
  6873. #define CSL_EVETPCC_EECRH_RN_E49_RESETVAL (0x00000000U)
  6874. #define CSL_EVETPCC_EECRH_RN_E49_MAX (0x00000001U)
  6875. #define CSL_EVETPCC_EECRH_RN_E60_MASK (0x10000000U)
  6876. #define CSL_EVETPCC_EECRH_RN_E60_SHIFT (28U)
  6877. #define CSL_EVETPCC_EECRH_RN_E60_RESETVAL (0x00000000U)
  6878. #define CSL_EVETPCC_EECRH_RN_E60_MAX (0x00000001U)
  6879. #define CSL_EVETPCC_EECRH_RN_E61_MASK (0x20000000U)
  6880. #define CSL_EVETPCC_EECRH_RN_E61_SHIFT (29U)
  6881. #define CSL_EVETPCC_EECRH_RN_E61_RESETVAL (0x00000000U)
  6882. #define CSL_EVETPCC_EECRH_RN_E61_MAX (0x00000001U)
  6883. #define CSL_EVETPCC_EECRH_RN_E52_MASK (0x00100000U)
  6884. #define CSL_EVETPCC_EECRH_RN_E52_SHIFT (20U)
  6885. #define CSL_EVETPCC_EECRH_RN_E52_RESETVAL (0x00000000U)
  6886. #define CSL_EVETPCC_EECRH_RN_E52_MAX (0x00000001U)
  6887. #define CSL_EVETPCC_EECRH_RN_E44_MASK (0x00001000U)
  6888. #define CSL_EVETPCC_EECRH_RN_E44_SHIFT (12U)
  6889. #define CSL_EVETPCC_EECRH_RN_E44_RESETVAL (0x00000000U)
  6890. #define CSL_EVETPCC_EECRH_RN_E44_MAX (0x00000001U)
  6891. #define CSL_EVETPCC_EECRH_RN_E34_MASK (0x00000004U)
  6892. #define CSL_EVETPCC_EECRH_RN_E34_SHIFT (2U)
  6893. #define CSL_EVETPCC_EECRH_RN_E34_RESETVAL (0x00000000U)
  6894. #define CSL_EVETPCC_EECRH_RN_E34_MAX (0x00000001U)
  6895. #define CSL_EVETPCC_EECRH_RN_E43_MASK (0x00000800U)
  6896. #define CSL_EVETPCC_EECRH_RN_E43_SHIFT (11U)
  6897. #define CSL_EVETPCC_EECRH_RN_E43_RESETVAL (0x00000000U)
  6898. #define CSL_EVETPCC_EECRH_RN_E43_MAX (0x00000001U)
  6899. #define CSL_EVETPCC_EECRH_RN_E33_MASK (0x00000002U)
  6900. #define CSL_EVETPCC_EECRH_RN_E33_SHIFT (1U)
  6901. #define CSL_EVETPCC_EECRH_RN_E33_RESETVAL (0x00000000U)
  6902. #define CSL_EVETPCC_EECRH_RN_E33_MAX (0x00000001U)
  6903. #define CSL_EVETPCC_EECRH_RN_E55_MASK (0x00800000U)
  6904. #define CSL_EVETPCC_EECRH_RN_E55_SHIFT (23U)
  6905. #define CSL_EVETPCC_EECRH_RN_E55_RESETVAL (0x00000000U)
  6906. #define CSL_EVETPCC_EECRH_RN_E55_MAX (0x00000001U)
  6907. #define CSL_EVETPCC_EECRH_RN_E42_MASK (0x00000400U)
  6908. #define CSL_EVETPCC_EECRH_RN_E42_SHIFT (10U)
  6909. #define CSL_EVETPCC_EECRH_RN_E42_RESETVAL (0x00000000U)
  6910. #define CSL_EVETPCC_EECRH_RN_E42_MAX (0x00000001U)
  6911. #define CSL_EVETPCC_EECRH_RN_E56_MASK (0x01000000U)
  6912. #define CSL_EVETPCC_EECRH_RN_E56_SHIFT (24U)
  6913. #define CSL_EVETPCC_EECRH_RN_E56_RESETVAL (0x00000000U)
  6914. #define CSL_EVETPCC_EECRH_RN_E56_MAX (0x00000001U)
  6915. #define CSL_EVETPCC_EECRH_RN_E32_MASK (0x00000001U)
  6916. #define CSL_EVETPCC_EECRH_RN_E32_SHIFT (0U)
  6917. #define CSL_EVETPCC_EECRH_RN_E32_RESETVAL (0x00000000U)
  6918. #define CSL_EVETPCC_EECRH_RN_E32_MAX (0x00000001U)
  6919. #define CSL_EVETPCC_EECRH_RN_E41_MASK (0x00000200U)
  6920. #define CSL_EVETPCC_EECRH_RN_E41_SHIFT (9U)
  6921. #define CSL_EVETPCC_EECRH_RN_E41_RESETVAL (0x00000000U)
  6922. #define CSL_EVETPCC_EECRH_RN_E41_MAX (0x00000001U)
  6923. #define CSL_EVETPCC_EECRH_RN_E57_MASK (0x02000000U)
  6924. #define CSL_EVETPCC_EECRH_RN_E57_SHIFT (25U)
  6925. #define CSL_EVETPCC_EECRH_RN_E57_RESETVAL (0x00000000U)
  6926. #define CSL_EVETPCC_EECRH_RN_E57_MAX (0x00000001U)
  6927. #define CSL_EVETPCC_EECRH_RN_E47_MASK (0x00008000U)
  6928. #define CSL_EVETPCC_EECRH_RN_E47_SHIFT (15U)
  6929. #define CSL_EVETPCC_EECRH_RN_E47_RESETVAL (0x00000000U)
  6930. #define CSL_EVETPCC_EECRH_RN_E47_MAX (0x00000001U)
  6931. #define CSL_EVETPCC_EECRH_RN_E40_MASK (0x00000100U)
  6932. #define CSL_EVETPCC_EECRH_RN_E40_SHIFT (8U)
  6933. #define CSL_EVETPCC_EECRH_RN_E40_RESETVAL (0x00000000U)
  6934. #define CSL_EVETPCC_EECRH_RN_E40_MAX (0x00000001U)
  6935. #define CSL_EVETPCC_EECRH_RN_E46_MASK (0x00004000U)
  6936. #define CSL_EVETPCC_EECRH_RN_E46_SHIFT (14U)
  6937. #define CSL_EVETPCC_EECRH_RN_E46_RESETVAL (0x00000000U)
  6938. #define CSL_EVETPCC_EECRH_RN_E46_MAX (0x00000001U)
  6939. #define CSL_EVETPCC_EECRH_RN_E39_MASK (0x00000080U)
  6940. #define CSL_EVETPCC_EECRH_RN_E39_SHIFT (7U)
  6941. #define CSL_EVETPCC_EECRH_RN_E39_RESETVAL (0x00000000U)
  6942. #define CSL_EVETPCC_EECRH_RN_E39_MAX (0x00000001U)
  6943. #define CSL_EVETPCC_EECRH_RN_E45_MASK (0x00002000U)
  6944. #define CSL_EVETPCC_EECRH_RN_E45_SHIFT (13U)
  6945. #define CSL_EVETPCC_EECRH_RN_E45_RESETVAL (0x00000000U)
  6946. #define CSL_EVETPCC_EECRH_RN_E45_MAX (0x00000001U)
  6947. #define CSL_EVETPCC_EECRH_RN_E38_MASK (0x00000040U)
  6948. #define CSL_EVETPCC_EECRH_RN_E38_SHIFT (6U)
  6949. #define CSL_EVETPCC_EECRH_RN_E38_RESETVAL (0x00000000U)
  6950. #define CSL_EVETPCC_EECRH_RN_E38_MAX (0x00000001U)
  6951. #define CSL_EVETPCC_EECRH_RN_RESETVAL (0x00000000U)
  6952. /* IESR_RN */
  6953. #define CSL_EVETPCC_IESR_RN_I22_MASK (0x00400000U)
  6954. #define CSL_EVETPCC_IESR_RN_I22_SHIFT (22U)
  6955. #define CSL_EVETPCC_IESR_RN_I22_RESETVAL (0x00000000U)
  6956. #define CSL_EVETPCC_IESR_RN_I22_MAX (0x00000001U)
  6957. #define CSL_EVETPCC_IESR_RN_I11_MASK (0x00000800U)
  6958. #define CSL_EVETPCC_IESR_RN_I11_SHIFT (11U)
  6959. #define CSL_EVETPCC_IESR_RN_I11_RESETVAL (0x00000000U)
  6960. #define CSL_EVETPCC_IESR_RN_I11_MAX (0x00000001U)
  6961. #define CSL_EVETPCC_IESR_RN_I23_MASK (0x00800000U)
  6962. #define CSL_EVETPCC_IESR_RN_I23_SHIFT (23U)
  6963. #define CSL_EVETPCC_IESR_RN_I23_RESETVAL (0x00000000U)
  6964. #define CSL_EVETPCC_IESR_RN_I23_MAX (0x00000001U)
  6965. #define CSL_EVETPCC_IESR_RN_I0_MASK (0x00000001U)
  6966. #define CSL_EVETPCC_IESR_RN_I0_SHIFT (0U)
  6967. #define CSL_EVETPCC_IESR_RN_I0_RESETVAL (0x00000000U)
  6968. #define CSL_EVETPCC_IESR_RN_I0_MAX (0x00000001U)
  6969. #define CSL_EVETPCC_IESR_RN_I21_MASK (0x00200000U)
  6970. #define CSL_EVETPCC_IESR_RN_I21_SHIFT (21U)
  6971. #define CSL_EVETPCC_IESR_RN_I21_RESETVAL (0x00000000U)
  6972. #define CSL_EVETPCC_IESR_RN_I21_MAX (0x00000001U)
  6973. #define CSL_EVETPCC_IESR_RN_I10_MASK (0x00000400U)
  6974. #define CSL_EVETPCC_IESR_RN_I10_SHIFT (10U)
  6975. #define CSL_EVETPCC_IESR_RN_I10_RESETVAL (0x00000000U)
  6976. #define CSL_EVETPCC_IESR_RN_I10_MAX (0x00000001U)
  6977. #define CSL_EVETPCC_IESR_RN_I31_MASK (0x80000000U)
  6978. #define CSL_EVETPCC_IESR_RN_I31_SHIFT (31U)
  6979. #define CSL_EVETPCC_IESR_RN_I31_RESETVAL (0x00000000U)
  6980. #define CSL_EVETPCC_IESR_RN_I31_MAX (0x00000001U)
  6981. #define CSL_EVETPCC_IESR_RN_I8_MASK (0x00000100U)
  6982. #define CSL_EVETPCC_IESR_RN_I8_SHIFT (8U)
  6983. #define CSL_EVETPCC_IESR_RN_I8_RESETVAL (0x00000000U)
  6984. #define CSL_EVETPCC_IESR_RN_I8_MAX (0x00000001U)
  6985. #define CSL_EVETPCC_IESR_RN_I20_MASK (0x00100000U)
  6986. #define CSL_EVETPCC_IESR_RN_I20_SHIFT (20U)
  6987. #define CSL_EVETPCC_IESR_RN_I20_RESETVAL (0x00000000U)
  6988. #define CSL_EVETPCC_IESR_RN_I20_MAX (0x00000001U)
  6989. #define CSL_EVETPCC_IESR_RN_I9_MASK (0x00000200U)
  6990. #define CSL_EVETPCC_IESR_RN_I9_SHIFT (9U)
  6991. #define CSL_EVETPCC_IESR_RN_I9_RESETVAL (0x00000000U)
  6992. #define CSL_EVETPCC_IESR_RN_I9_MAX (0x00000001U)
  6993. #define CSL_EVETPCC_IESR_RN_I6_MASK (0x00000040U)
  6994. #define CSL_EVETPCC_IESR_RN_I6_SHIFT (6U)
  6995. #define CSL_EVETPCC_IESR_RN_I6_RESETVAL (0x00000000U)
  6996. #define CSL_EVETPCC_IESR_RN_I6_MAX (0x00000001U)
  6997. #define CSL_EVETPCC_IESR_RN_I30_MASK (0x40000000U)
  6998. #define CSL_EVETPCC_IESR_RN_I30_SHIFT (30U)
  6999. #define CSL_EVETPCC_IESR_RN_I30_RESETVAL (0x00000000U)
  7000. #define CSL_EVETPCC_IESR_RN_I30_MAX (0x00000001U)
  7001. #define CSL_EVETPCC_IESR_RN_I17_MASK (0x00020000U)
  7002. #define CSL_EVETPCC_IESR_RN_I17_SHIFT (17U)
  7003. #define CSL_EVETPCC_IESR_RN_I17_RESETVAL (0x00000000U)
  7004. #define CSL_EVETPCC_IESR_RN_I17_MAX (0x00000001U)
  7005. #define CSL_EVETPCC_IESR_RN_I7_MASK (0x00000080U)
  7006. #define CSL_EVETPCC_IESR_RN_I7_SHIFT (7U)
  7007. #define CSL_EVETPCC_IESR_RN_I7_RESETVAL (0x00000000U)
  7008. #define CSL_EVETPCC_IESR_RN_I7_MAX (0x00000001U)
  7009. #define CSL_EVETPCC_IESR_RN_I16_MASK (0x00010000U)
  7010. #define CSL_EVETPCC_IESR_RN_I16_SHIFT (16U)
  7011. #define CSL_EVETPCC_IESR_RN_I16_RESETVAL (0x00000000U)
  7012. #define CSL_EVETPCC_IESR_RN_I16_MAX (0x00000001U)
  7013. #define CSL_EVETPCC_IESR_RN_I28_MASK (0x10000000U)
  7014. #define CSL_EVETPCC_IESR_RN_I28_SHIFT (28U)
  7015. #define CSL_EVETPCC_IESR_RN_I28_RESETVAL (0x00000000U)
  7016. #define CSL_EVETPCC_IESR_RN_I28_MAX (0x00000001U)
  7017. #define CSL_EVETPCC_IESR_RN_I4_MASK (0x00000010U)
  7018. #define CSL_EVETPCC_IESR_RN_I4_SHIFT (4U)
  7019. #define CSL_EVETPCC_IESR_RN_I4_RESETVAL (0x00000000U)
  7020. #define CSL_EVETPCC_IESR_RN_I4_MAX (0x00000001U)
  7021. #define CSL_EVETPCC_IESR_RN_I29_MASK (0x20000000U)
  7022. #define CSL_EVETPCC_IESR_RN_I29_SHIFT (29U)
  7023. #define CSL_EVETPCC_IESR_RN_I29_RESETVAL (0x00000000U)
  7024. #define CSL_EVETPCC_IESR_RN_I29_MAX (0x00000001U)
  7025. #define CSL_EVETPCC_IESR_RN_I19_MASK (0x00080000U)
  7026. #define CSL_EVETPCC_IESR_RN_I19_SHIFT (19U)
  7027. #define CSL_EVETPCC_IESR_RN_I19_RESETVAL (0x00000000U)
  7028. #define CSL_EVETPCC_IESR_RN_I19_MAX (0x00000001U)
  7029. #define CSL_EVETPCC_IESR_RN_I5_MASK (0x00000020U)
  7030. #define CSL_EVETPCC_IESR_RN_I5_SHIFT (5U)
  7031. #define CSL_EVETPCC_IESR_RN_I5_RESETVAL (0x00000000U)
  7032. #define CSL_EVETPCC_IESR_RN_I5_MAX (0x00000001U)
  7033. #define CSL_EVETPCC_IESR_RN_I18_MASK (0x00040000U)
  7034. #define CSL_EVETPCC_IESR_RN_I18_SHIFT (18U)
  7035. #define CSL_EVETPCC_IESR_RN_I18_RESETVAL (0x00000000U)
  7036. #define CSL_EVETPCC_IESR_RN_I18_MAX (0x00000001U)
  7037. #define CSL_EVETPCC_IESR_RN_I26_MASK (0x04000000U)
  7038. #define CSL_EVETPCC_IESR_RN_I26_SHIFT (26U)
  7039. #define CSL_EVETPCC_IESR_RN_I26_RESETVAL (0x00000000U)
  7040. #define CSL_EVETPCC_IESR_RN_I26_MAX (0x00000001U)
  7041. #define CSL_EVETPCC_IESR_RN_I2_MASK (0x00000004U)
  7042. #define CSL_EVETPCC_IESR_RN_I2_SHIFT (2U)
  7043. #define CSL_EVETPCC_IESR_RN_I2_RESETVAL (0x00000000U)
  7044. #define CSL_EVETPCC_IESR_RN_I2_MAX (0x00000001U)
  7045. #define CSL_EVETPCC_IESR_RN_I13_MASK (0x00002000U)
  7046. #define CSL_EVETPCC_IESR_RN_I13_SHIFT (13U)
  7047. #define CSL_EVETPCC_IESR_RN_I13_RESETVAL (0x00000000U)
  7048. #define CSL_EVETPCC_IESR_RN_I13_MAX (0x00000001U)
  7049. #define CSL_EVETPCC_IESR_RN_I3_MASK (0x00000008U)
  7050. #define CSL_EVETPCC_IESR_RN_I3_SHIFT (3U)
  7051. #define CSL_EVETPCC_IESR_RN_I3_RESETVAL (0x00000000U)
  7052. #define CSL_EVETPCC_IESR_RN_I3_MAX (0x00000001U)
  7053. #define CSL_EVETPCC_IESR_RN_I27_MASK (0x08000000U)
  7054. #define CSL_EVETPCC_IESR_RN_I27_SHIFT (27U)
  7055. #define CSL_EVETPCC_IESR_RN_I27_RESETVAL (0x00000000U)
  7056. #define CSL_EVETPCC_IESR_RN_I27_MAX (0x00000001U)
  7057. #define CSL_EVETPCC_IESR_RN_I12_MASK (0x00001000U)
  7058. #define CSL_EVETPCC_IESR_RN_I12_SHIFT (12U)
  7059. #define CSL_EVETPCC_IESR_RN_I12_RESETVAL (0x00000000U)
  7060. #define CSL_EVETPCC_IESR_RN_I12_MAX (0x00000001U)
  7061. #define CSL_EVETPCC_IESR_RN_I24_MASK (0x01000000U)
  7062. #define CSL_EVETPCC_IESR_RN_I24_SHIFT (24U)
  7063. #define CSL_EVETPCC_IESR_RN_I24_RESETVAL (0x00000000U)
  7064. #define CSL_EVETPCC_IESR_RN_I24_MAX (0x00000001U)
  7065. #define CSL_EVETPCC_IESR_RN_I15_MASK (0x00008000U)
  7066. #define CSL_EVETPCC_IESR_RN_I15_SHIFT (15U)
  7067. #define CSL_EVETPCC_IESR_RN_I15_RESETVAL (0x00000000U)
  7068. #define CSL_EVETPCC_IESR_RN_I15_MAX (0x00000001U)
  7069. #define CSL_EVETPCC_IESR_RN_I1_MASK (0x00000002U)
  7070. #define CSL_EVETPCC_IESR_RN_I1_SHIFT (1U)
  7071. #define CSL_EVETPCC_IESR_RN_I1_RESETVAL (0x00000000U)
  7072. #define CSL_EVETPCC_IESR_RN_I1_MAX (0x00000001U)
  7073. #define CSL_EVETPCC_IESR_RN_I25_MASK (0x02000000U)
  7074. #define CSL_EVETPCC_IESR_RN_I25_SHIFT (25U)
  7075. #define CSL_EVETPCC_IESR_RN_I25_RESETVAL (0x00000000U)
  7076. #define CSL_EVETPCC_IESR_RN_I25_MAX (0x00000001U)
  7077. #define CSL_EVETPCC_IESR_RN_I14_MASK (0x00004000U)
  7078. #define CSL_EVETPCC_IESR_RN_I14_SHIFT (14U)
  7079. #define CSL_EVETPCC_IESR_RN_I14_RESETVAL (0x00000000U)
  7080. #define CSL_EVETPCC_IESR_RN_I14_MAX (0x00000001U)
  7081. #define CSL_EVETPCC_IESR_RN_RESETVAL (0x00000000U)
  7082. /* SECR_RN */
  7083. #define CSL_EVETPCC_SECR_RN_E21_MASK (0x00200000U)
  7084. #define CSL_EVETPCC_SECR_RN_E21_SHIFT (21U)
  7085. #define CSL_EVETPCC_SECR_RN_E21_RESETVAL (0x00000000U)
  7086. #define CSL_EVETPCC_SECR_RN_E21_MAX (0x00000001U)
  7087. #define CSL_EVETPCC_SECR_RN_E29_MASK (0x20000000U)
  7088. #define CSL_EVETPCC_SECR_RN_E29_SHIFT (29U)
  7089. #define CSL_EVETPCC_SECR_RN_E29_RESETVAL (0x00000000U)
  7090. #define CSL_EVETPCC_SECR_RN_E29_MAX (0x00000001U)
  7091. #define CSL_EVETPCC_SECR_RN_E20_MASK (0x00100000U)
  7092. #define CSL_EVETPCC_SECR_RN_E20_SHIFT (20U)
  7093. #define CSL_EVETPCC_SECR_RN_E20_RESETVAL (0x00000000U)
  7094. #define CSL_EVETPCC_SECR_RN_E20_MAX (0x00000001U)
  7095. #define CSL_EVETPCC_SECR_RN_E0_MASK (0x00000001U)
  7096. #define CSL_EVETPCC_SECR_RN_E0_SHIFT (0U)
  7097. #define CSL_EVETPCC_SECR_RN_E0_RESETVAL (0x00000000U)
  7098. #define CSL_EVETPCC_SECR_RN_E0_MAX (0x00000001U)
  7099. #define CSL_EVETPCC_SECR_RN_E10_MASK (0x00000400U)
  7100. #define CSL_EVETPCC_SECR_RN_E10_SHIFT (10U)
  7101. #define CSL_EVETPCC_SECR_RN_E10_RESETVAL (0x00000000U)
  7102. #define CSL_EVETPCC_SECR_RN_E10_MAX (0x00000001U)
  7103. #define CSL_EVETPCC_SECR_RN_E9_MASK (0x00000200U)
  7104. #define CSL_EVETPCC_SECR_RN_E9_SHIFT (9U)
  7105. #define CSL_EVETPCC_SECR_RN_E9_RESETVAL (0x00000000U)
  7106. #define CSL_EVETPCC_SECR_RN_E9_MAX (0x00000001U)
  7107. #define CSL_EVETPCC_SECR_RN_E27_MASK (0x08000000U)
  7108. #define CSL_EVETPCC_SECR_RN_E27_SHIFT (27U)
  7109. #define CSL_EVETPCC_SECR_RN_E27_RESETVAL (0x00000000U)
  7110. #define CSL_EVETPCC_SECR_RN_E27_MAX (0x00000001U)
  7111. #define CSL_EVETPCC_SECR_RN_E2_MASK (0x00000004U)
  7112. #define CSL_EVETPCC_SECR_RN_E2_SHIFT (2U)
  7113. #define CSL_EVETPCC_SECR_RN_E2_RESETVAL (0x00000000U)
  7114. #define CSL_EVETPCC_SECR_RN_E2_MAX (0x00000001U)
  7115. #define CSL_EVETPCC_SECR_RN_E12_MASK (0x00001000U)
  7116. #define CSL_EVETPCC_SECR_RN_E12_SHIFT (12U)
  7117. #define CSL_EVETPCC_SECR_RN_E12_RESETVAL (0x00000000U)
  7118. #define CSL_EVETPCC_SECR_RN_E12_MAX (0x00000001U)
  7119. #define CSL_EVETPCC_SECR_RN_E28_MASK (0x10000000U)
  7120. #define CSL_EVETPCC_SECR_RN_E28_SHIFT (28U)
  7121. #define CSL_EVETPCC_SECR_RN_E28_RESETVAL (0x00000000U)
  7122. #define CSL_EVETPCC_SECR_RN_E28_MAX (0x00000001U)
  7123. #define CSL_EVETPCC_SECR_RN_E1_MASK (0x00000002U)
  7124. #define CSL_EVETPCC_SECR_RN_E1_SHIFT (1U)
  7125. #define CSL_EVETPCC_SECR_RN_E1_RESETVAL (0x00000000U)
  7126. #define CSL_EVETPCC_SECR_RN_E1_MAX (0x00000001U)
  7127. #define CSL_EVETPCC_SECR_RN_E11_MASK (0x00000800U)
  7128. #define CSL_EVETPCC_SECR_RN_E11_SHIFT (11U)
  7129. #define CSL_EVETPCC_SECR_RN_E11_RESETVAL (0x00000000U)
  7130. #define CSL_EVETPCC_SECR_RN_E11_MAX (0x00000001U)
  7131. #define CSL_EVETPCC_SECR_RN_E25_MASK (0x02000000U)
  7132. #define CSL_EVETPCC_SECR_RN_E25_SHIFT (25U)
  7133. #define CSL_EVETPCC_SECR_RN_E25_RESETVAL (0x00000000U)
  7134. #define CSL_EVETPCC_SECR_RN_E25_MAX (0x00000001U)
  7135. #define CSL_EVETPCC_SECR_RN_E4_MASK (0x00000010U)
  7136. #define CSL_EVETPCC_SECR_RN_E4_SHIFT (4U)
  7137. #define CSL_EVETPCC_SECR_RN_E4_RESETVAL (0x00000000U)
  7138. #define CSL_EVETPCC_SECR_RN_E4_MAX (0x00000001U)
  7139. #define CSL_EVETPCC_SECR_RN_E14_MASK (0x00004000U)
  7140. #define CSL_EVETPCC_SECR_RN_E14_SHIFT (14U)
  7141. #define CSL_EVETPCC_SECR_RN_E14_RESETVAL (0x00000000U)
  7142. #define CSL_EVETPCC_SECR_RN_E14_MAX (0x00000001U)
  7143. #define CSL_EVETPCC_SECR_RN_E26_MASK (0x04000000U)
  7144. #define CSL_EVETPCC_SECR_RN_E26_SHIFT (26U)
  7145. #define CSL_EVETPCC_SECR_RN_E26_RESETVAL (0x00000000U)
  7146. #define CSL_EVETPCC_SECR_RN_E26_MAX (0x00000001U)
  7147. #define CSL_EVETPCC_SECR_RN_E3_MASK (0x00000008U)
  7148. #define CSL_EVETPCC_SECR_RN_E3_SHIFT (3U)
  7149. #define CSL_EVETPCC_SECR_RN_E3_RESETVAL (0x00000000U)
  7150. #define CSL_EVETPCC_SECR_RN_E3_MAX (0x00000001U)
  7151. #define CSL_EVETPCC_SECR_RN_E13_MASK (0x00002000U)
  7152. #define CSL_EVETPCC_SECR_RN_E13_SHIFT (13U)
  7153. #define CSL_EVETPCC_SECR_RN_E13_RESETVAL (0x00000000U)
  7154. #define CSL_EVETPCC_SECR_RN_E13_MAX (0x00000001U)
  7155. #define CSL_EVETPCC_SECR_RN_E6_MASK (0x00000040U)
  7156. #define CSL_EVETPCC_SECR_RN_E6_SHIFT (6U)
  7157. #define CSL_EVETPCC_SECR_RN_E6_RESETVAL (0x00000000U)
  7158. #define CSL_EVETPCC_SECR_RN_E6_MAX (0x00000001U)
  7159. #define CSL_EVETPCC_SECR_RN_E16_MASK (0x00010000U)
  7160. #define CSL_EVETPCC_SECR_RN_E16_SHIFT (16U)
  7161. #define CSL_EVETPCC_SECR_RN_E16_RESETVAL (0x00000000U)
  7162. #define CSL_EVETPCC_SECR_RN_E16_MAX (0x00000001U)
  7163. #define CSL_EVETPCC_SECR_RN_E24_MASK (0x01000000U)
  7164. #define CSL_EVETPCC_SECR_RN_E24_SHIFT (24U)
  7165. #define CSL_EVETPCC_SECR_RN_E24_RESETVAL (0x00000000U)
  7166. #define CSL_EVETPCC_SECR_RN_E24_MAX (0x00000001U)
  7167. #define CSL_EVETPCC_SECR_RN_E5_MASK (0x00000020U)
  7168. #define CSL_EVETPCC_SECR_RN_E5_SHIFT (5U)
  7169. #define CSL_EVETPCC_SECR_RN_E5_RESETVAL (0x00000000U)
  7170. #define CSL_EVETPCC_SECR_RN_E5_MAX (0x00000001U)
  7171. #define CSL_EVETPCC_SECR_RN_E15_MASK (0x00008000U)
  7172. #define CSL_EVETPCC_SECR_RN_E15_SHIFT (15U)
  7173. #define CSL_EVETPCC_SECR_RN_E15_RESETVAL (0x00000000U)
  7174. #define CSL_EVETPCC_SECR_RN_E15_MAX (0x00000001U)
  7175. #define CSL_EVETPCC_SECR_RN_E18_MASK (0x00040000U)
  7176. #define CSL_EVETPCC_SECR_RN_E18_SHIFT (18U)
  7177. #define CSL_EVETPCC_SECR_RN_E18_RESETVAL (0x00000000U)
  7178. #define CSL_EVETPCC_SECR_RN_E18_MAX (0x00000001U)
  7179. #define CSL_EVETPCC_SECR_RN_E31_MASK (0x80000000U)
  7180. #define CSL_EVETPCC_SECR_RN_E31_SHIFT (31U)
  7181. #define CSL_EVETPCC_SECR_RN_E31_RESETVAL (0x00000000U)
  7182. #define CSL_EVETPCC_SECR_RN_E31_MAX (0x00000001U)
  7183. #define CSL_EVETPCC_SECR_RN_E8_MASK (0x00000100U)
  7184. #define CSL_EVETPCC_SECR_RN_E8_SHIFT (8U)
  7185. #define CSL_EVETPCC_SECR_RN_E8_RESETVAL (0x00000000U)
  7186. #define CSL_EVETPCC_SECR_RN_E8_MAX (0x00000001U)
  7187. #define CSL_EVETPCC_SECR_RN_E22_MASK (0x00400000U)
  7188. #define CSL_EVETPCC_SECR_RN_E22_SHIFT (22U)
  7189. #define CSL_EVETPCC_SECR_RN_E22_RESETVAL (0x00000000U)
  7190. #define CSL_EVETPCC_SECR_RN_E22_MAX (0x00000001U)
  7191. #define CSL_EVETPCC_SECR_RN_E7_MASK (0x00000080U)
  7192. #define CSL_EVETPCC_SECR_RN_E7_SHIFT (7U)
  7193. #define CSL_EVETPCC_SECR_RN_E7_RESETVAL (0x00000000U)
  7194. #define CSL_EVETPCC_SECR_RN_E7_MAX (0x00000001U)
  7195. #define CSL_EVETPCC_SECR_RN_E19_MASK (0x00080000U)
  7196. #define CSL_EVETPCC_SECR_RN_E19_SHIFT (19U)
  7197. #define CSL_EVETPCC_SECR_RN_E19_RESETVAL (0x00000000U)
  7198. #define CSL_EVETPCC_SECR_RN_E19_MAX (0x00000001U)
  7199. #define CSL_EVETPCC_SECR_RN_E17_MASK (0x00020000U)
  7200. #define CSL_EVETPCC_SECR_RN_E17_SHIFT (17U)
  7201. #define CSL_EVETPCC_SECR_RN_E17_RESETVAL (0x00000000U)
  7202. #define CSL_EVETPCC_SECR_RN_E17_MAX (0x00000001U)
  7203. #define CSL_EVETPCC_SECR_RN_E23_MASK (0x00800000U)
  7204. #define CSL_EVETPCC_SECR_RN_E23_SHIFT (23U)
  7205. #define CSL_EVETPCC_SECR_RN_E23_RESETVAL (0x00000000U)
  7206. #define CSL_EVETPCC_SECR_RN_E23_MAX (0x00000001U)
  7207. #define CSL_EVETPCC_SECR_RN_E30_MASK (0x40000000U)
  7208. #define CSL_EVETPCC_SECR_RN_E30_SHIFT (30U)
  7209. #define CSL_EVETPCC_SECR_RN_E30_RESETVAL (0x00000000U)
  7210. #define CSL_EVETPCC_SECR_RN_E30_MAX (0x00000001U)
  7211. #define CSL_EVETPCC_SECR_RN_RESETVAL (0x00000000U)
  7212. /* EESR_RN */
  7213. #define CSL_EVETPCC_EESR_RN_E15_MASK (0x00008000U)
  7214. #define CSL_EVETPCC_EESR_RN_E15_SHIFT (15U)
  7215. #define CSL_EVETPCC_EESR_RN_E15_RESETVAL (0x00000000U)
  7216. #define CSL_EVETPCC_EESR_RN_E15_MAX (0x00000001U)
  7217. #define CSL_EVETPCC_EESR_RN_E6_MASK (0x00000040U)
  7218. #define CSL_EVETPCC_EESR_RN_E6_SHIFT (6U)
  7219. #define CSL_EVETPCC_EESR_RN_E6_RESETVAL (0x00000000U)
  7220. #define CSL_EVETPCC_EESR_RN_E6_MAX (0x00000001U)
  7221. #define CSL_EVETPCC_EESR_RN_E16_MASK (0x00010000U)
  7222. #define CSL_EVETPCC_EESR_RN_E16_SHIFT (16U)
  7223. #define CSL_EVETPCC_EESR_RN_E16_RESETVAL (0x00000000U)
  7224. #define CSL_EVETPCC_EESR_RN_E16_MAX (0x00000001U)
  7225. #define CSL_EVETPCC_EESR_RN_E30_MASK (0x40000000U)
  7226. #define CSL_EVETPCC_EESR_RN_E30_SHIFT (30U)
  7227. #define CSL_EVETPCC_EESR_RN_E30_RESETVAL (0x00000000U)
  7228. #define CSL_EVETPCC_EESR_RN_E30_MAX (0x00000001U)
  7229. #define CSL_EVETPCC_EESR_RN_E7_MASK (0x00000080U)
  7230. #define CSL_EVETPCC_EESR_RN_E7_SHIFT (7U)
  7231. #define CSL_EVETPCC_EESR_RN_E7_RESETVAL (0x00000000U)
  7232. #define CSL_EVETPCC_EESR_RN_E7_MAX (0x00000001U)
  7233. #define CSL_EVETPCC_EESR_RN_E4_MASK (0x00000010U)
  7234. #define CSL_EVETPCC_EESR_RN_E4_SHIFT (4U)
  7235. #define CSL_EVETPCC_EESR_RN_E4_RESETVAL (0x00000000U)
  7236. #define CSL_EVETPCC_EESR_RN_E4_MAX (0x00000001U)
  7237. #define CSL_EVETPCC_EESR_RN_E5_MASK (0x00000020U)
  7238. #define CSL_EVETPCC_EESR_RN_E5_SHIFT (5U)
  7239. #define CSL_EVETPCC_EESR_RN_E5_RESETVAL (0x00000000U)
  7240. #define CSL_EVETPCC_EESR_RN_E5_MAX (0x00000001U)
  7241. #define CSL_EVETPCC_EESR_RN_E29_MASK (0x20000000U)
  7242. #define CSL_EVETPCC_EESR_RN_E29_SHIFT (29U)
  7243. #define CSL_EVETPCC_EESR_RN_E29_RESETVAL (0x00000000U)
  7244. #define CSL_EVETPCC_EESR_RN_E29_MAX (0x00000001U)
  7245. #define CSL_EVETPCC_EESR_RN_E0_MASK (0x00000001U)
  7246. #define CSL_EVETPCC_EESR_RN_E0_SHIFT (0U)
  7247. #define CSL_EVETPCC_EESR_RN_E0_RESETVAL (0x00000000U)
  7248. #define CSL_EVETPCC_EESR_RN_E0_MAX (0x00000001U)
  7249. #define CSL_EVETPCC_EESR_RN_E10_MASK (0x00000400U)
  7250. #define CSL_EVETPCC_EESR_RN_E10_SHIFT (10U)
  7251. #define CSL_EVETPCC_EESR_RN_E10_RESETVAL (0x00000000U)
  7252. #define CSL_EVETPCC_EESR_RN_E10_MAX (0x00000001U)
  7253. #define CSL_EVETPCC_EESR_RN_E28_MASK (0x10000000U)
  7254. #define CSL_EVETPCC_EESR_RN_E28_SHIFT (28U)
  7255. #define CSL_EVETPCC_EESR_RN_E28_RESETVAL (0x00000000U)
  7256. #define CSL_EVETPCC_EESR_RN_E28_MAX (0x00000001U)
  7257. #define CSL_EVETPCC_EESR_RN_E27_MASK (0x08000000U)
  7258. #define CSL_EVETPCC_EESR_RN_E27_SHIFT (27U)
  7259. #define CSL_EVETPCC_EESR_RN_E27_RESETVAL (0x00000000U)
  7260. #define CSL_EVETPCC_EESR_RN_E27_MAX (0x00000001U)
  7261. #define CSL_EVETPCC_EESR_RN_E26_MASK (0x04000000U)
  7262. #define CSL_EVETPCC_EESR_RN_E26_SHIFT (26U)
  7263. #define CSL_EVETPCC_EESR_RN_E26_RESETVAL (0x00000000U)
  7264. #define CSL_EVETPCC_EESR_RN_E26_MAX (0x00000001U)
  7265. #define CSL_EVETPCC_EESR_RN_E8_MASK (0x00000100U)
  7266. #define CSL_EVETPCC_EESR_RN_E8_SHIFT (8U)
  7267. #define CSL_EVETPCC_EESR_RN_E8_RESETVAL (0x00000000U)
  7268. #define CSL_EVETPCC_EESR_RN_E8_MAX (0x00000001U)
  7269. #define CSL_EVETPCC_EESR_RN_E9_MASK (0x00000200U)
  7270. #define CSL_EVETPCC_EESR_RN_E9_SHIFT (9U)
  7271. #define CSL_EVETPCC_EESR_RN_E9_RESETVAL (0x00000000U)
  7272. #define CSL_EVETPCC_EESR_RN_E9_MAX (0x00000001U)
  7273. #define CSL_EVETPCC_EESR_RN_E25_MASK (0x02000000U)
  7274. #define CSL_EVETPCC_EESR_RN_E25_SHIFT (25U)
  7275. #define CSL_EVETPCC_EESR_RN_E25_RESETVAL (0x00000000U)
  7276. #define CSL_EVETPCC_EESR_RN_E25_MAX (0x00000001U)
  7277. #define CSL_EVETPCC_EESR_RN_E24_MASK (0x01000000U)
  7278. #define CSL_EVETPCC_EESR_RN_E24_SHIFT (24U)
  7279. #define CSL_EVETPCC_EESR_RN_E24_RESETVAL (0x00000000U)
  7280. #define CSL_EVETPCC_EESR_RN_E24_MAX (0x00000001U)
  7281. #define CSL_EVETPCC_EESR_RN_E11_MASK (0x00000800U)
  7282. #define CSL_EVETPCC_EESR_RN_E11_SHIFT (11U)
  7283. #define CSL_EVETPCC_EESR_RN_E11_RESETVAL (0x00000000U)
  7284. #define CSL_EVETPCC_EESR_RN_E11_MAX (0x00000001U)
  7285. #define CSL_EVETPCC_EESR_RN_E23_MASK (0x00800000U)
  7286. #define CSL_EVETPCC_EESR_RN_E23_SHIFT (23U)
  7287. #define CSL_EVETPCC_EESR_RN_E23_RESETVAL (0x00000000U)
  7288. #define CSL_EVETPCC_EESR_RN_E23_MAX (0x00000001U)
  7289. #define CSL_EVETPCC_EESR_RN_E20_MASK (0x00100000U)
  7290. #define CSL_EVETPCC_EESR_RN_E20_SHIFT (20U)
  7291. #define CSL_EVETPCC_EESR_RN_E20_RESETVAL (0x00000000U)
  7292. #define CSL_EVETPCC_EESR_RN_E20_MAX (0x00000001U)
  7293. #define CSL_EVETPCC_EESR_RN_E22_MASK (0x00400000U)
  7294. #define CSL_EVETPCC_EESR_RN_E22_SHIFT (22U)
  7295. #define CSL_EVETPCC_EESR_RN_E22_RESETVAL (0x00000000U)
  7296. #define CSL_EVETPCC_EESR_RN_E22_MAX (0x00000001U)
  7297. #define CSL_EVETPCC_EESR_RN_E21_MASK (0x00200000U)
  7298. #define CSL_EVETPCC_EESR_RN_E21_SHIFT (21U)
  7299. #define CSL_EVETPCC_EESR_RN_E21_RESETVAL (0x00000000U)
  7300. #define CSL_EVETPCC_EESR_RN_E21_MAX (0x00000001U)
  7301. #define CSL_EVETPCC_EESR_RN_E2_MASK (0x00000004U)
  7302. #define CSL_EVETPCC_EESR_RN_E2_SHIFT (2U)
  7303. #define CSL_EVETPCC_EESR_RN_E2_RESETVAL (0x00000000U)
  7304. #define CSL_EVETPCC_EESR_RN_E2_MAX (0x00000001U)
  7305. #define CSL_EVETPCC_EESR_RN_E18_MASK (0x00040000U)
  7306. #define CSL_EVETPCC_EESR_RN_E18_SHIFT (18U)
  7307. #define CSL_EVETPCC_EESR_RN_E18_RESETVAL (0x00000000U)
  7308. #define CSL_EVETPCC_EESR_RN_E18_MAX (0x00000001U)
  7309. #define CSL_EVETPCC_EESR_RN_E3_MASK (0x00000008U)
  7310. #define CSL_EVETPCC_EESR_RN_E3_SHIFT (3U)
  7311. #define CSL_EVETPCC_EESR_RN_E3_RESETVAL (0x00000000U)
  7312. #define CSL_EVETPCC_EESR_RN_E3_MAX (0x00000001U)
  7313. #define CSL_EVETPCC_EESR_RN_E19_MASK (0x00080000U)
  7314. #define CSL_EVETPCC_EESR_RN_E19_SHIFT (19U)
  7315. #define CSL_EVETPCC_EESR_RN_E19_RESETVAL (0x00000000U)
  7316. #define CSL_EVETPCC_EESR_RN_E19_MAX (0x00000001U)
  7317. #define CSL_EVETPCC_EESR_RN_E31_MASK (0x80000000U)
  7318. #define CSL_EVETPCC_EESR_RN_E31_SHIFT (31U)
  7319. #define CSL_EVETPCC_EESR_RN_E31_RESETVAL (0x00000000U)
  7320. #define CSL_EVETPCC_EESR_RN_E31_MAX (0x00000001U)
  7321. #define CSL_EVETPCC_EESR_RN_E13_MASK (0x00002000U)
  7322. #define CSL_EVETPCC_EESR_RN_E13_SHIFT (13U)
  7323. #define CSL_EVETPCC_EESR_RN_E13_RESETVAL (0x00000000U)
  7324. #define CSL_EVETPCC_EESR_RN_E13_MAX (0x00000001U)
  7325. #define CSL_EVETPCC_EESR_RN_E12_MASK (0x00001000U)
  7326. #define CSL_EVETPCC_EESR_RN_E12_SHIFT (12U)
  7327. #define CSL_EVETPCC_EESR_RN_E12_RESETVAL (0x00000000U)
  7328. #define CSL_EVETPCC_EESR_RN_E12_MAX (0x00000001U)
  7329. #define CSL_EVETPCC_EESR_RN_E14_MASK (0x00004000U)
  7330. #define CSL_EVETPCC_EESR_RN_E14_SHIFT (14U)
  7331. #define CSL_EVETPCC_EESR_RN_E14_RESETVAL (0x00000000U)
  7332. #define CSL_EVETPCC_EESR_RN_E14_MAX (0x00000001U)
  7333. #define CSL_EVETPCC_EESR_RN_E1_MASK (0x00000002U)
  7334. #define CSL_EVETPCC_EESR_RN_E1_SHIFT (1U)
  7335. #define CSL_EVETPCC_EESR_RN_E1_RESETVAL (0x00000000U)
  7336. #define CSL_EVETPCC_EESR_RN_E1_MAX (0x00000001U)
  7337. #define CSL_EVETPCC_EESR_RN_E17_MASK (0x00020000U)
  7338. #define CSL_EVETPCC_EESR_RN_E17_SHIFT (17U)
  7339. #define CSL_EVETPCC_EESR_RN_E17_RESETVAL (0x00000000U)
  7340. #define CSL_EVETPCC_EESR_RN_E17_MAX (0x00000001U)
  7341. #define CSL_EVETPCC_EESR_RN_RESETVAL (0x00000000U)
  7342. /* QER_RN */
  7343. #define CSL_EVETPCC_QER_RN_E7_MASK (0x00000080U)
  7344. #define CSL_EVETPCC_QER_RN_E7_SHIFT (7U)
  7345. #define CSL_EVETPCC_QER_RN_E7_RESETVAL (0x00000000U)
  7346. #define CSL_EVETPCC_QER_RN_E7_MAX (0x00000001U)
  7347. #define CSL_EVETPCC_QER_RN_E6_MASK (0x00000040U)
  7348. #define CSL_EVETPCC_QER_RN_E6_SHIFT (6U)
  7349. #define CSL_EVETPCC_QER_RN_E6_RESETVAL (0x00000000U)
  7350. #define CSL_EVETPCC_QER_RN_E6_MAX (0x00000001U)
  7351. #define CSL_EVETPCC_QER_RN_E5_MASK (0x00000020U)
  7352. #define CSL_EVETPCC_QER_RN_E5_SHIFT (5U)
  7353. #define CSL_EVETPCC_QER_RN_E5_RESETVAL (0x00000000U)
  7354. #define CSL_EVETPCC_QER_RN_E5_MAX (0x00000001U)
  7355. #define CSL_EVETPCC_QER_RN_E3_MASK (0x00000008U)
  7356. #define CSL_EVETPCC_QER_RN_E3_SHIFT (3U)
  7357. #define CSL_EVETPCC_QER_RN_E3_RESETVAL (0x00000000U)
  7358. #define CSL_EVETPCC_QER_RN_E3_MAX (0x00000001U)
  7359. #define CSL_EVETPCC_QER_RN_E4_MASK (0x00000010U)
  7360. #define CSL_EVETPCC_QER_RN_E4_SHIFT (4U)
  7361. #define CSL_EVETPCC_QER_RN_E4_RESETVAL (0x00000000U)
  7362. #define CSL_EVETPCC_QER_RN_E4_MAX (0x00000001U)
  7363. #define CSL_EVETPCC_QER_RN_E1_MASK (0x00000002U)
  7364. #define CSL_EVETPCC_QER_RN_E1_SHIFT (1U)
  7365. #define CSL_EVETPCC_QER_RN_E1_RESETVAL (0x00000000U)
  7366. #define CSL_EVETPCC_QER_RN_E1_MAX (0x00000001U)
  7367. #define CSL_EVETPCC_QER_RN_E2_MASK (0x00000004U)
  7368. #define CSL_EVETPCC_QER_RN_E2_SHIFT (2U)
  7369. #define CSL_EVETPCC_QER_RN_E2_RESETVAL (0x00000000U)
  7370. #define CSL_EVETPCC_QER_RN_E2_MAX (0x00000001U)
  7371. #define CSL_EVETPCC_QER_RN_E0_MASK (0x00000001U)
  7372. #define CSL_EVETPCC_QER_RN_E0_SHIFT (0U)
  7373. #define CSL_EVETPCC_QER_RN_E0_RESETVAL (0x00000000U)
  7374. #define CSL_EVETPCC_QER_RN_E0_MAX (0x00000001U)
  7375. #define CSL_EVETPCC_QER_RN_RESETVAL (0x00000000U)
  7376. /* SECRH_RN */
  7377. #define CSL_EVETPCC_SECRH_RN_E34_MASK (0x00000004U)
  7378. #define CSL_EVETPCC_SECRH_RN_E34_SHIFT (2U)
  7379. #define CSL_EVETPCC_SECRH_RN_E34_RESETVAL (0x00000000U)
  7380. #define CSL_EVETPCC_SECRH_RN_E34_MAX (0x00000001U)
  7381. #define CSL_EVETPCC_SECRH_RN_E44_MASK (0x00001000U)
  7382. #define CSL_EVETPCC_SECRH_RN_E44_SHIFT (12U)
  7383. #define CSL_EVETPCC_SECRH_RN_E44_RESETVAL (0x00000000U)
  7384. #define CSL_EVETPCC_SECRH_RN_E44_MAX (0x00000001U)
  7385. #define CSL_EVETPCC_SECRH_RN_E54_MASK (0x00400000U)
  7386. #define CSL_EVETPCC_SECRH_RN_E54_SHIFT (22U)
  7387. #define CSL_EVETPCC_SECRH_RN_E54_RESETVAL (0x00000000U)
  7388. #define CSL_EVETPCC_SECRH_RN_E54_MAX (0x00000001U)
  7389. #define CSL_EVETPCC_SECRH_RN_E33_MASK (0x00000002U)
  7390. #define CSL_EVETPCC_SECRH_RN_E33_SHIFT (1U)
  7391. #define CSL_EVETPCC_SECRH_RN_E33_RESETVAL (0x00000000U)
  7392. #define CSL_EVETPCC_SECRH_RN_E33_MAX (0x00000001U)
  7393. #define CSL_EVETPCC_SECRH_RN_E43_MASK (0x00000800U)
  7394. #define CSL_EVETPCC_SECRH_RN_E43_SHIFT (11U)
  7395. #define CSL_EVETPCC_SECRH_RN_E43_RESETVAL (0x00000000U)
  7396. #define CSL_EVETPCC_SECRH_RN_E43_MAX (0x00000001U)
  7397. #define CSL_EVETPCC_SECRH_RN_E53_MASK (0x00200000U)
  7398. #define CSL_EVETPCC_SECRH_RN_E53_SHIFT (21U)
  7399. #define CSL_EVETPCC_SECRH_RN_E53_RESETVAL (0x00000000U)
  7400. #define CSL_EVETPCC_SECRH_RN_E53_MAX (0x00000001U)
  7401. #define CSL_EVETPCC_SECRH_RN_E58_MASK (0x04000000U)
  7402. #define CSL_EVETPCC_SECRH_RN_E58_SHIFT (26U)
  7403. #define CSL_EVETPCC_SECRH_RN_E58_RESETVAL (0x00000000U)
  7404. #define CSL_EVETPCC_SECRH_RN_E58_MAX (0x00000001U)
  7405. #define CSL_EVETPCC_SECRH_RN_E32_MASK (0x00000001U)
  7406. #define CSL_EVETPCC_SECRH_RN_E32_SHIFT (0U)
  7407. #define CSL_EVETPCC_SECRH_RN_E32_RESETVAL (0x00000000U)
  7408. #define CSL_EVETPCC_SECRH_RN_E32_MAX (0x00000001U)
  7409. #define CSL_EVETPCC_SECRH_RN_E63_MASK (0x80000000U)
  7410. #define CSL_EVETPCC_SECRH_RN_E63_SHIFT (31U)
  7411. #define CSL_EVETPCC_SECRH_RN_E63_RESETVAL (0x00000000U)
  7412. #define CSL_EVETPCC_SECRH_RN_E63_MAX (0x00000001U)
  7413. #define CSL_EVETPCC_SECRH_RN_E57_MASK (0x02000000U)
  7414. #define CSL_EVETPCC_SECRH_RN_E57_SHIFT (25U)
  7415. #define CSL_EVETPCC_SECRH_RN_E57_RESETVAL (0x00000000U)
  7416. #define CSL_EVETPCC_SECRH_RN_E57_MAX (0x00000001U)
  7417. #define CSL_EVETPCC_SECRH_RN_E56_MASK (0x01000000U)
  7418. #define CSL_EVETPCC_SECRH_RN_E56_SHIFT (24U)
  7419. #define CSL_EVETPCC_SECRH_RN_E56_RESETVAL (0x00000000U)
  7420. #define CSL_EVETPCC_SECRH_RN_E56_MAX (0x00000001U)
  7421. #define CSL_EVETPCC_SECRH_RN_E55_MASK (0x00800000U)
  7422. #define CSL_EVETPCC_SECRH_RN_E55_SHIFT (23U)
  7423. #define CSL_EVETPCC_SECRH_RN_E55_RESETVAL (0x00000000U)
  7424. #define CSL_EVETPCC_SECRH_RN_E55_MAX (0x00000001U)
  7425. #define CSL_EVETPCC_SECRH_RN_E52_MASK (0x00100000U)
  7426. #define CSL_EVETPCC_SECRH_RN_E52_SHIFT (20U)
  7427. #define CSL_EVETPCC_SECRH_RN_E52_RESETVAL (0x00000000U)
  7428. #define CSL_EVETPCC_SECRH_RN_E52_MAX (0x00000001U)
  7429. #define CSL_EVETPCC_SECRH_RN_E42_MASK (0x00000400U)
  7430. #define CSL_EVETPCC_SECRH_RN_E42_SHIFT (10U)
  7431. #define CSL_EVETPCC_SECRH_RN_E42_RESETVAL (0x00000000U)
  7432. #define CSL_EVETPCC_SECRH_RN_E42_MAX (0x00000001U)
  7433. #define CSL_EVETPCC_SECRH_RN_E51_MASK (0x00080000U)
  7434. #define CSL_EVETPCC_SECRH_RN_E51_SHIFT (19U)
  7435. #define CSL_EVETPCC_SECRH_RN_E51_RESETVAL (0x00000000U)
  7436. #define CSL_EVETPCC_SECRH_RN_E51_MAX (0x00000001U)
  7437. #define CSL_EVETPCC_SECRH_RN_E41_MASK (0x00000200U)
  7438. #define CSL_EVETPCC_SECRH_RN_E41_SHIFT (9U)
  7439. #define CSL_EVETPCC_SECRH_RN_E41_RESETVAL (0x00000000U)
  7440. #define CSL_EVETPCC_SECRH_RN_E41_MAX (0x00000001U)
  7441. #define CSL_EVETPCC_SECRH_RN_E50_MASK (0x00040000U)
  7442. #define CSL_EVETPCC_SECRH_RN_E50_SHIFT (18U)
  7443. #define CSL_EVETPCC_SECRH_RN_E50_RESETVAL (0x00000000U)
  7444. #define CSL_EVETPCC_SECRH_RN_E50_MAX (0x00000001U)
  7445. #define CSL_EVETPCC_SECRH_RN_E40_MASK (0x00000100U)
  7446. #define CSL_EVETPCC_SECRH_RN_E40_SHIFT (8U)
  7447. #define CSL_EVETPCC_SECRH_RN_E40_RESETVAL (0x00000000U)
  7448. #define CSL_EVETPCC_SECRH_RN_E40_MAX (0x00000001U)
  7449. #define CSL_EVETPCC_SECRH_RN_E49_MASK (0x00020000U)
  7450. #define CSL_EVETPCC_SECRH_RN_E49_SHIFT (17U)
  7451. #define CSL_EVETPCC_SECRH_RN_E49_RESETVAL (0x00000000U)
  7452. #define CSL_EVETPCC_SECRH_RN_E49_MAX (0x00000001U)
  7453. #define CSL_EVETPCC_SECRH_RN_E39_MASK (0x00000080U)
  7454. #define CSL_EVETPCC_SECRH_RN_E39_SHIFT (7U)
  7455. #define CSL_EVETPCC_SECRH_RN_E39_RESETVAL (0x00000000U)
  7456. #define CSL_EVETPCC_SECRH_RN_E39_MAX (0x00000001U)
  7457. #define CSL_EVETPCC_SECRH_RN_E48_MASK (0x00010000U)
  7458. #define CSL_EVETPCC_SECRH_RN_E48_SHIFT (16U)
  7459. #define CSL_EVETPCC_SECRH_RN_E48_RESETVAL (0x00000000U)
  7460. #define CSL_EVETPCC_SECRH_RN_E48_MAX (0x00000001U)
  7461. #define CSL_EVETPCC_SECRH_RN_E38_MASK (0x00000040U)
  7462. #define CSL_EVETPCC_SECRH_RN_E38_SHIFT (6U)
  7463. #define CSL_EVETPCC_SECRH_RN_E38_RESETVAL (0x00000000U)
  7464. #define CSL_EVETPCC_SECRH_RN_E38_MAX (0x00000001U)
  7465. #define CSL_EVETPCC_SECRH_RN_E59_MASK (0x08000000U)
  7466. #define CSL_EVETPCC_SECRH_RN_E59_SHIFT (27U)
  7467. #define CSL_EVETPCC_SECRH_RN_E59_RESETVAL (0x00000000U)
  7468. #define CSL_EVETPCC_SECRH_RN_E59_MAX (0x00000001U)
  7469. #define CSL_EVETPCC_SECRH_RN_E47_MASK (0x00008000U)
  7470. #define CSL_EVETPCC_SECRH_RN_E47_SHIFT (15U)
  7471. #define CSL_EVETPCC_SECRH_RN_E47_RESETVAL (0x00000000U)
  7472. #define CSL_EVETPCC_SECRH_RN_E47_MAX (0x00000001U)
  7473. #define CSL_EVETPCC_SECRH_RN_E37_MASK (0x00000020U)
  7474. #define CSL_EVETPCC_SECRH_RN_E37_SHIFT (5U)
  7475. #define CSL_EVETPCC_SECRH_RN_E37_RESETVAL (0x00000000U)
  7476. #define CSL_EVETPCC_SECRH_RN_E37_MAX (0x00000001U)
  7477. #define CSL_EVETPCC_SECRH_RN_E60_MASK (0x10000000U)
  7478. #define CSL_EVETPCC_SECRH_RN_E60_SHIFT (28U)
  7479. #define CSL_EVETPCC_SECRH_RN_E60_RESETVAL (0x00000000U)
  7480. #define CSL_EVETPCC_SECRH_RN_E60_MAX (0x00000001U)
  7481. #define CSL_EVETPCC_SECRH_RN_E36_MASK (0x00000010U)
  7482. #define CSL_EVETPCC_SECRH_RN_E36_SHIFT (4U)
  7483. #define CSL_EVETPCC_SECRH_RN_E36_RESETVAL (0x00000000U)
  7484. #define CSL_EVETPCC_SECRH_RN_E36_MAX (0x00000001U)
  7485. #define CSL_EVETPCC_SECRH_RN_E46_MASK (0x00004000U)
  7486. #define CSL_EVETPCC_SECRH_RN_E46_SHIFT (14U)
  7487. #define CSL_EVETPCC_SECRH_RN_E46_RESETVAL (0x00000000U)
  7488. #define CSL_EVETPCC_SECRH_RN_E46_MAX (0x00000001U)
  7489. #define CSL_EVETPCC_SECRH_RN_E61_MASK (0x20000000U)
  7490. #define CSL_EVETPCC_SECRH_RN_E61_SHIFT (29U)
  7491. #define CSL_EVETPCC_SECRH_RN_E61_RESETVAL (0x00000000U)
  7492. #define CSL_EVETPCC_SECRH_RN_E61_MAX (0x00000001U)
  7493. #define CSL_EVETPCC_SECRH_RN_E35_MASK (0x00000008U)
  7494. #define CSL_EVETPCC_SECRH_RN_E35_SHIFT (3U)
  7495. #define CSL_EVETPCC_SECRH_RN_E35_RESETVAL (0x00000000U)
  7496. #define CSL_EVETPCC_SECRH_RN_E35_MAX (0x00000001U)
  7497. #define CSL_EVETPCC_SECRH_RN_E62_MASK (0x40000000U)
  7498. #define CSL_EVETPCC_SECRH_RN_E62_SHIFT (30U)
  7499. #define CSL_EVETPCC_SECRH_RN_E62_RESETVAL (0x00000000U)
  7500. #define CSL_EVETPCC_SECRH_RN_E62_MAX (0x00000001U)
  7501. #define CSL_EVETPCC_SECRH_RN_E45_MASK (0x00002000U)
  7502. #define CSL_EVETPCC_SECRH_RN_E45_SHIFT (13U)
  7503. #define CSL_EVETPCC_SECRH_RN_E45_RESETVAL (0x00000000U)
  7504. #define CSL_EVETPCC_SECRH_RN_E45_MAX (0x00000001U)
  7505. #define CSL_EVETPCC_SECRH_RN_RESETVAL (0x00000000U)
  7506. /* EESRH_RN */
  7507. #define CSL_EVETPCC_EESRH_RN_E33_MASK (0x00000002U)
  7508. #define CSL_EVETPCC_EESRH_RN_E33_SHIFT (1U)
  7509. #define CSL_EVETPCC_EESRH_RN_E33_RESETVAL (0x00000000U)
  7510. #define CSL_EVETPCC_EESRH_RN_E33_MAX (0x00000001U)
  7511. #define CSL_EVETPCC_EESRH_RN_E35_MASK (0x00000008U)
  7512. #define CSL_EVETPCC_EESRH_RN_E35_SHIFT (3U)
  7513. #define CSL_EVETPCC_EESRH_RN_E35_RESETVAL (0x00000000U)
  7514. #define CSL_EVETPCC_EESRH_RN_E35_MAX (0x00000001U)
  7515. #define CSL_EVETPCC_EESRH_RN_E44_MASK (0x00001000U)
  7516. #define CSL_EVETPCC_EESRH_RN_E44_SHIFT (12U)
  7517. #define CSL_EVETPCC_EESRH_RN_E44_RESETVAL (0x00000000U)
  7518. #define CSL_EVETPCC_EESRH_RN_E44_MAX (0x00000001U)
  7519. #define CSL_EVETPCC_EESRH_RN_E32_MASK (0x00000001U)
  7520. #define CSL_EVETPCC_EESRH_RN_E32_SHIFT (0U)
  7521. #define CSL_EVETPCC_EESRH_RN_E32_RESETVAL (0x00000000U)
  7522. #define CSL_EVETPCC_EESRH_RN_E32_MAX (0x00000001U)
  7523. #define CSL_EVETPCC_EESRH_RN_E43_MASK (0x00000800U)
  7524. #define CSL_EVETPCC_EESRH_RN_E43_SHIFT (11U)
  7525. #define CSL_EVETPCC_EESRH_RN_E43_RESETVAL (0x00000000U)
  7526. #define CSL_EVETPCC_EESRH_RN_E43_MAX (0x00000001U)
  7527. #define CSL_EVETPCC_EESRH_RN_E55_MASK (0x00800000U)
  7528. #define CSL_EVETPCC_EESRH_RN_E55_SHIFT (23U)
  7529. #define CSL_EVETPCC_EESRH_RN_E55_RESETVAL (0x00000000U)
  7530. #define CSL_EVETPCC_EESRH_RN_E55_MAX (0x00000001U)
  7531. #define CSL_EVETPCC_EESRH_RN_E42_MASK (0x00000400U)
  7532. #define CSL_EVETPCC_EESRH_RN_E42_SHIFT (10U)
  7533. #define CSL_EVETPCC_EESRH_RN_E42_RESETVAL (0x00000000U)
  7534. #define CSL_EVETPCC_EESRH_RN_E42_MAX (0x00000001U)
  7535. #define CSL_EVETPCC_EESRH_RN_E54_MASK (0x00400000U)
  7536. #define CSL_EVETPCC_EESRH_RN_E54_SHIFT (22U)
  7537. #define CSL_EVETPCC_EESRH_RN_E54_RESETVAL (0x00000000U)
  7538. #define CSL_EVETPCC_EESRH_RN_E54_MAX (0x00000001U)
  7539. #define CSL_EVETPCC_EESRH_RN_E53_MASK (0x00200000U)
  7540. #define CSL_EVETPCC_EESRH_RN_E53_SHIFT (21U)
  7541. #define CSL_EVETPCC_EESRH_RN_E53_RESETVAL (0x00000000U)
  7542. #define CSL_EVETPCC_EESRH_RN_E53_MAX (0x00000001U)
  7543. #define CSL_EVETPCC_EESRH_RN_E56_MASK (0x01000000U)
  7544. #define CSL_EVETPCC_EESRH_RN_E56_SHIFT (24U)
  7545. #define CSL_EVETPCC_EESRH_RN_E56_RESETVAL (0x00000000U)
  7546. #define CSL_EVETPCC_EESRH_RN_E56_MAX (0x00000001U)
  7547. #define CSL_EVETPCC_EESRH_RN_E41_MASK (0x00000200U)
  7548. #define CSL_EVETPCC_EESRH_RN_E41_SHIFT (9U)
  7549. #define CSL_EVETPCC_EESRH_RN_E41_RESETVAL (0x00000000U)
  7550. #define CSL_EVETPCC_EESRH_RN_E41_MAX (0x00000001U)
  7551. #define CSL_EVETPCC_EESRH_RN_E40_MASK (0x00000100U)
  7552. #define CSL_EVETPCC_EESRH_RN_E40_SHIFT (8U)
  7553. #define CSL_EVETPCC_EESRH_RN_E40_RESETVAL (0x00000000U)
  7554. #define CSL_EVETPCC_EESRH_RN_E40_MAX (0x00000001U)
  7555. #define CSL_EVETPCC_EESRH_RN_E57_MASK (0x02000000U)
  7556. #define CSL_EVETPCC_EESRH_RN_E57_SHIFT (25U)
  7557. #define CSL_EVETPCC_EESRH_RN_E57_RESETVAL (0x00000000U)
  7558. #define CSL_EVETPCC_EESRH_RN_E57_MAX (0x00000001U)
  7559. #define CSL_EVETPCC_EESRH_RN_E52_MASK (0x00100000U)
  7560. #define CSL_EVETPCC_EESRH_RN_E52_SHIFT (20U)
  7561. #define CSL_EVETPCC_EESRH_RN_E52_RESETVAL (0x00000000U)
  7562. #define CSL_EVETPCC_EESRH_RN_E52_MAX (0x00000001U)
  7563. #define CSL_EVETPCC_EESRH_RN_E34_MASK (0x00000004U)
  7564. #define CSL_EVETPCC_EESRH_RN_E34_SHIFT (2U)
  7565. #define CSL_EVETPCC_EESRH_RN_E34_RESETVAL (0x00000000U)
  7566. #define CSL_EVETPCC_EESRH_RN_E34_MAX (0x00000001U)
  7567. #define CSL_EVETPCC_EESRH_RN_E39_MASK (0x00000080U)
  7568. #define CSL_EVETPCC_EESRH_RN_E39_SHIFT (7U)
  7569. #define CSL_EVETPCC_EESRH_RN_E39_RESETVAL (0x00000000U)
  7570. #define CSL_EVETPCC_EESRH_RN_E39_MAX (0x00000001U)
  7571. #define CSL_EVETPCC_EESRH_RN_E58_MASK (0x04000000U)
  7572. #define CSL_EVETPCC_EESRH_RN_E58_SHIFT (26U)
  7573. #define CSL_EVETPCC_EESRH_RN_E58_RESETVAL (0x00000000U)
  7574. #define CSL_EVETPCC_EESRH_RN_E58_MAX (0x00000001U)
  7575. #define CSL_EVETPCC_EESRH_RN_E51_MASK (0x00080000U)
  7576. #define CSL_EVETPCC_EESRH_RN_E51_SHIFT (19U)
  7577. #define CSL_EVETPCC_EESRH_RN_E51_RESETVAL (0x00000000U)
  7578. #define CSL_EVETPCC_EESRH_RN_E51_MAX (0x00000001U)
  7579. #define CSL_EVETPCC_EESRH_RN_E36_MASK (0x00000010U)
  7580. #define CSL_EVETPCC_EESRH_RN_E36_SHIFT (4U)
  7581. #define CSL_EVETPCC_EESRH_RN_E36_RESETVAL (0x00000000U)
  7582. #define CSL_EVETPCC_EESRH_RN_E36_MAX (0x00000001U)
  7583. #define CSL_EVETPCC_EESRH_RN_E38_MASK (0x00000040U)
  7584. #define CSL_EVETPCC_EESRH_RN_E38_SHIFT (6U)
  7585. #define CSL_EVETPCC_EESRH_RN_E38_RESETVAL (0x00000000U)
  7586. #define CSL_EVETPCC_EESRH_RN_E38_MAX (0x00000001U)
  7587. #define CSL_EVETPCC_EESRH_RN_E59_MASK (0x08000000U)
  7588. #define CSL_EVETPCC_EESRH_RN_E59_SHIFT (27U)
  7589. #define CSL_EVETPCC_EESRH_RN_E59_RESETVAL (0x00000000U)
  7590. #define CSL_EVETPCC_EESRH_RN_E59_MAX (0x00000001U)
  7591. #define CSL_EVETPCC_EESRH_RN_E50_MASK (0x00040000U)
  7592. #define CSL_EVETPCC_EESRH_RN_E50_SHIFT (18U)
  7593. #define CSL_EVETPCC_EESRH_RN_E50_RESETVAL (0x00000000U)
  7594. #define CSL_EVETPCC_EESRH_RN_E50_MAX (0x00000001U)
  7595. #define CSL_EVETPCC_EESRH_RN_E37_MASK (0x00000020U)
  7596. #define CSL_EVETPCC_EESRH_RN_E37_SHIFT (5U)
  7597. #define CSL_EVETPCC_EESRH_RN_E37_RESETVAL (0x00000000U)
  7598. #define CSL_EVETPCC_EESRH_RN_E37_MAX (0x00000001U)
  7599. #define CSL_EVETPCC_EESRH_RN_E60_MASK (0x10000000U)
  7600. #define CSL_EVETPCC_EESRH_RN_E60_SHIFT (28U)
  7601. #define CSL_EVETPCC_EESRH_RN_E60_RESETVAL (0x00000000U)
  7602. #define CSL_EVETPCC_EESRH_RN_E60_MAX (0x00000001U)
  7603. #define CSL_EVETPCC_EESRH_RN_E49_MASK (0x00020000U)
  7604. #define CSL_EVETPCC_EESRH_RN_E49_SHIFT (17U)
  7605. #define CSL_EVETPCC_EESRH_RN_E49_RESETVAL (0x00000000U)
  7606. #define CSL_EVETPCC_EESRH_RN_E49_MAX (0x00000001U)
  7607. #define CSL_EVETPCC_EESRH_RN_E61_MASK (0x20000000U)
  7608. #define CSL_EVETPCC_EESRH_RN_E61_SHIFT (29U)
  7609. #define CSL_EVETPCC_EESRH_RN_E61_RESETVAL (0x00000000U)
  7610. #define CSL_EVETPCC_EESRH_RN_E61_MAX (0x00000001U)
  7611. #define CSL_EVETPCC_EESRH_RN_E48_MASK (0x00010000U)
  7612. #define CSL_EVETPCC_EESRH_RN_E48_SHIFT (16U)
  7613. #define CSL_EVETPCC_EESRH_RN_E48_RESETVAL (0x00000000U)
  7614. #define CSL_EVETPCC_EESRH_RN_E48_MAX (0x00000001U)
  7615. #define CSL_EVETPCC_EESRH_RN_E62_MASK (0x40000000U)
  7616. #define CSL_EVETPCC_EESRH_RN_E62_SHIFT (30U)
  7617. #define CSL_EVETPCC_EESRH_RN_E62_RESETVAL (0x00000000U)
  7618. #define CSL_EVETPCC_EESRH_RN_E62_MAX (0x00000001U)
  7619. #define CSL_EVETPCC_EESRH_RN_E47_MASK (0x00008000U)
  7620. #define CSL_EVETPCC_EESRH_RN_E47_SHIFT (15U)
  7621. #define CSL_EVETPCC_EESRH_RN_E47_RESETVAL (0x00000000U)
  7622. #define CSL_EVETPCC_EESRH_RN_E47_MAX (0x00000001U)
  7623. #define CSL_EVETPCC_EESRH_RN_E63_MASK (0x80000000U)
  7624. #define CSL_EVETPCC_EESRH_RN_E63_SHIFT (31U)
  7625. #define CSL_EVETPCC_EESRH_RN_E63_RESETVAL (0x00000000U)
  7626. #define CSL_EVETPCC_EESRH_RN_E63_MAX (0x00000001U)
  7627. #define CSL_EVETPCC_EESRH_RN_E46_MASK (0x00004000U)
  7628. #define CSL_EVETPCC_EESRH_RN_E46_SHIFT (14U)
  7629. #define CSL_EVETPCC_EESRH_RN_E46_RESETVAL (0x00000000U)
  7630. #define CSL_EVETPCC_EESRH_RN_E46_MAX (0x00000001U)
  7631. #define CSL_EVETPCC_EESRH_RN_E45_MASK (0x00002000U)
  7632. #define CSL_EVETPCC_EESRH_RN_E45_SHIFT (13U)
  7633. #define CSL_EVETPCC_EESRH_RN_E45_RESETVAL (0x00000000U)
  7634. #define CSL_EVETPCC_EESRH_RN_E45_MAX (0x00000001U)
  7635. #define CSL_EVETPCC_EESRH_RN_RESETVAL (0x00000000U)
  7636. /* IER_RN */
  7637. #define CSL_EVETPCC_IER_RN_I15_MASK (0x00008000U)
  7638. #define CSL_EVETPCC_IER_RN_I15_SHIFT (15U)
  7639. #define CSL_EVETPCC_IER_RN_I15_RESETVAL (0x00000000U)
  7640. #define CSL_EVETPCC_IER_RN_I15_MAX (0x00000001U)
  7641. #define CSL_EVETPCC_IER_RN_I30_MASK (0x40000000U)
  7642. #define CSL_EVETPCC_IER_RN_I30_SHIFT (30U)
  7643. #define CSL_EVETPCC_IER_RN_I30_RESETVAL (0x00000000U)
  7644. #define CSL_EVETPCC_IER_RN_I30_MAX (0x00000001U)
  7645. #define CSL_EVETPCC_IER_RN_I14_MASK (0x00004000U)
  7646. #define CSL_EVETPCC_IER_RN_I14_SHIFT (14U)
  7647. #define CSL_EVETPCC_IER_RN_I14_RESETVAL (0x00000000U)
  7648. #define CSL_EVETPCC_IER_RN_I14_MAX (0x00000001U)
  7649. #define CSL_EVETPCC_IER_RN_I29_MASK (0x20000000U)
  7650. #define CSL_EVETPCC_IER_RN_I29_SHIFT (29U)
  7651. #define CSL_EVETPCC_IER_RN_I29_RESETVAL (0x00000000U)
  7652. #define CSL_EVETPCC_IER_RN_I29_MAX (0x00000001U)
  7653. #define CSL_EVETPCC_IER_RN_I7_MASK (0x00000080U)
  7654. #define CSL_EVETPCC_IER_RN_I7_SHIFT (7U)
  7655. #define CSL_EVETPCC_IER_RN_I7_RESETVAL (0x00000000U)
  7656. #define CSL_EVETPCC_IER_RN_I7_MAX (0x00000001U)
  7657. #define CSL_EVETPCC_IER_RN_I28_MASK (0x10000000U)
  7658. #define CSL_EVETPCC_IER_RN_I28_SHIFT (28U)
  7659. #define CSL_EVETPCC_IER_RN_I28_RESETVAL (0x00000000U)
  7660. #define CSL_EVETPCC_IER_RN_I28_MAX (0x00000001U)
  7661. #define CSL_EVETPCC_IER_RN_I17_MASK (0x00020000U)
  7662. #define CSL_EVETPCC_IER_RN_I17_SHIFT (17U)
  7663. #define CSL_EVETPCC_IER_RN_I17_RESETVAL (0x00000000U)
  7664. #define CSL_EVETPCC_IER_RN_I17_MAX (0x00000001U)
  7665. #define CSL_EVETPCC_IER_RN_I16_MASK (0x00010000U)
  7666. #define CSL_EVETPCC_IER_RN_I16_SHIFT (16U)
  7667. #define CSL_EVETPCC_IER_RN_I16_RESETVAL (0x00000000U)
  7668. #define CSL_EVETPCC_IER_RN_I16_MAX (0x00000001U)
  7669. #define CSL_EVETPCC_IER_RN_I27_MASK (0x08000000U)
  7670. #define CSL_EVETPCC_IER_RN_I27_SHIFT (27U)
  7671. #define CSL_EVETPCC_IER_RN_I27_RESETVAL (0x00000000U)
  7672. #define CSL_EVETPCC_IER_RN_I27_MAX (0x00000001U)
  7673. #define CSL_EVETPCC_IER_RN_I0_MASK (0x00000001U)
  7674. #define CSL_EVETPCC_IER_RN_I0_SHIFT (0U)
  7675. #define CSL_EVETPCC_IER_RN_I0_RESETVAL (0x00000000U)
  7676. #define CSL_EVETPCC_IER_RN_I0_MAX (0x00000001U)
  7677. #define CSL_EVETPCC_IER_RN_I1_MASK (0x00000002U)
  7678. #define CSL_EVETPCC_IER_RN_I1_SHIFT (1U)
  7679. #define CSL_EVETPCC_IER_RN_I1_RESETVAL (0x00000000U)
  7680. #define CSL_EVETPCC_IER_RN_I1_MAX (0x00000001U)
  7681. #define CSL_EVETPCC_IER_RN_I13_MASK (0x00002000U)
  7682. #define CSL_EVETPCC_IER_RN_I13_SHIFT (13U)
  7683. #define CSL_EVETPCC_IER_RN_I13_RESETVAL (0x00000000U)
  7684. #define CSL_EVETPCC_IER_RN_I13_MAX (0x00000001U)
  7685. #define CSL_EVETPCC_IER_RN_I2_MASK (0x00000004U)
  7686. #define CSL_EVETPCC_IER_RN_I2_SHIFT (2U)
  7687. #define CSL_EVETPCC_IER_RN_I2_RESETVAL (0x00000000U)
  7688. #define CSL_EVETPCC_IER_RN_I2_MAX (0x00000001U)
  7689. #define CSL_EVETPCC_IER_RN_I31_MASK (0x80000000U)
  7690. #define CSL_EVETPCC_IER_RN_I31_SHIFT (31U)
  7691. #define CSL_EVETPCC_IER_RN_I31_RESETVAL (0x00000000U)
  7692. #define CSL_EVETPCC_IER_RN_I31_MAX (0x00000001U)
  7693. #define CSL_EVETPCC_IER_RN_I22_MASK (0x00400000U)
  7694. #define CSL_EVETPCC_IER_RN_I22_SHIFT (22U)
  7695. #define CSL_EVETPCC_IER_RN_I22_RESETVAL (0x00000000U)
  7696. #define CSL_EVETPCC_IER_RN_I22_MAX (0x00000001U)
  7697. #define CSL_EVETPCC_IER_RN_I3_MASK (0x00000008U)
  7698. #define CSL_EVETPCC_IER_RN_I3_SHIFT (3U)
  7699. #define CSL_EVETPCC_IER_RN_I3_RESETVAL (0x00000000U)
  7700. #define CSL_EVETPCC_IER_RN_I3_MAX (0x00000001U)
  7701. #define CSL_EVETPCC_IER_RN_I26_MASK (0x04000000U)
  7702. #define CSL_EVETPCC_IER_RN_I26_SHIFT (26U)
  7703. #define CSL_EVETPCC_IER_RN_I26_RESETVAL (0x00000000U)
  7704. #define CSL_EVETPCC_IER_RN_I26_MAX (0x00000001U)
  7705. #define CSL_EVETPCC_IER_RN_I5_MASK (0x00000020U)
  7706. #define CSL_EVETPCC_IER_RN_I5_SHIFT (5U)
  7707. #define CSL_EVETPCC_IER_RN_I5_RESETVAL (0x00000000U)
  7708. #define CSL_EVETPCC_IER_RN_I5_MAX (0x00000001U)
  7709. #define CSL_EVETPCC_IER_RN_I19_MASK (0x00080000U)
  7710. #define CSL_EVETPCC_IER_RN_I19_SHIFT (19U)
  7711. #define CSL_EVETPCC_IER_RN_I19_RESETVAL (0x00000000U)
  7712. #define CSL_EVETPCC_IER_RN_I19_MAX (0x00000001U)
  7713. #define CSL_EVETPCC_IER_RN_I8_MASK (0x00000100U)
  7714. #define CSL_EVETPCC_IER_RN_I8_SHIFT (8U)
  7715. #define CSL_EVETPCC_IER_RN_I8_RESETVAL (0x00000000U)
  7716. #define CSL_EVETPCC_IER_RN_I8_MAX (0x00000001U)
  7717. #define CSL_EVETPCC_IER_RN_I25_MASK (0x02000000U)
  7718. #define CSL_EVETPCC_IER_RN_I25_SHIFT (25U)
  7719. #define CSL_EVETPCC_IER_RN_I25_RESETVAL (0x00000000U)
  7720. #define CSL_EVETPCC_IER_RN_I25_MAX (0x00000001U)
  7721. #define CSL_EVETPCC_IER_RN_I4_MASK (0x00000010U)
  7722. #define CSL_EVETPCC_IER_RN_I4_SHIFT (4U)
  7723. #define CSL_EVETPCC_IER_RN_I4_RESETVAL (0x00000000U)
  7724. #define CSL_EVETPCC_IER_RN_I4_MAX (0x00000001U)
  7725. #define CSL_EVETPCC_IER_RN_I18_MASK (0x00040000U)
  7726. #define CSL_EVETPCC_IER_RN_I18_SHIFT (18U)
  7727. #define CSL_EVETPCC_IER_RN_I18_RESETVAL (0x00000000U)
  7728. #define CSL_EVETPCC_IER_RN_I18_MAX (0x00000001U)
  7729. #define CSL_EVETPCC_IER_RN_I9_MASK (0x00000200U)
  7730. #define CSL_EVETPCC_IER_RN_I9_SHIFT (9U)
  7731. #define CSL_EVETPCC_IER_RN_I9_RESETVAL (0x00000000U)
  7732. #define CSL_EVETPCC_IER_RN_I9_MAX (0x00000001U)
  7733. #define CSL_EVETPCC_IER_RN_I21_MASK (0x00200000U)
  7734. #define CSL_EVETPCC_IER_RN_I21_SHIFT (21U)
  7735. #define CSL_EVETPCC_IER_RN_I21_RESETVAL (0x00000000U)
  7736. #define CSL_EVETPCC_IER_RN_I21_MAX (0x00000001U)
  7737. #define CSL_EVETPCC_IER_RN_I24_MASK (0x01000000U)
  7738. #define CSL_EVETPCC_IER_RN_I24_SHIFT (24U)
  7739. #define CSL_EVETPCC_IER_RN_I24_RESETVAL (0x00000000U)
  7740. #define CSL_EVETPCC_IER_RN_I24_MAX (0x00000001U)
  7741. #define CSL_EVETPCC_IER_RN_I10_MASK (0x00000400U)
  7742. #define CSL_EVETPCC_IER_RN_I10_SHIFT (10U)
  7743. #define CSL_EVETPCC_IER_RN_I10_RESETVAL (0x00000000U)
  7744. #define CSL_EVETPCC_IER_RN_I10_MAX (0x00000001U)
  7745. #define CSL_EVETPCC_IER_RN_I12_MASK (0x00001000U)
  7746. #define CSL_EVETPCC_IER_RN_I12_SHIFT (12U)
  7747. #define CSL_EVETPCC_IER_RN_I12_RESETVAL (0x00000000U)
  7748. #define CSL_EVETPCC_IER_RN_I12_MAX (0x00000001U)
  7749. #define CSL_EVETPCC_IER_RN_I23_MASK (0x00800000U)
  7750. #define CSL_EVETPCC_IER_RN_I23_SHIFT (23U)
  7751. #define CSL_EVETPCC_IER_RN_I23_RESETVAL (0x00000000U)
  7752. #define CSL_EVETPCC_IER_RN_I23_MAX (0x00000001U)
  7753. #define CSL_EVETPCC_IER_RN_I20_MASK (0x00100000U)
  7754. #define CSL_EVETPCC_IER_RN_I20_SHIFT (20U)
  7755. #define CSL_EVETPCC_IER_RN_I20_RESETVAL (0x00000000U)
  7756. #define CSL_EVETPCC_IER_RN_I20_MAX (0x00000001U)
  7757. #define CSL_EVETPCC_IER_RN_I6_MASK (0x00000040U)
  7758. #define CSL_EVETPCC_IER_RN_I6_SHIFT (6U)
  7759. #define CSL_EVETPCC_IER_RN_I6_RESETVAL (0x00000000U)
  7760. #define CSL_EVETPCC_IER_RN_I6_MAX (0x00000001U)
  7761. #define CSL_EVETPCC_IER_RN_I11_MASK (0x00000800U)
  7762. #define CSL_EVETPCC_IER_RN_I11_SHIFT (11U)
  7763. #define CSL_EVETPCC_IER_RN_I11_RESETVAL (0x00000000U)
  7764. #define CSL_EVETPCC_IER_RN_I11_MAX (0x00000001U)
  7765. #define CSL_EVETPCC_IER_RN_RESETVAL (0x00000000U)
  7766. /* QEECR_RN */
  7767. #define CSL_EVETPCC_QEECR_RN_E3_MASK (0x00000008U)
  7768. #define CSL_EVETPCC_QEECR_RN_E3_SHIFT (3U)
  7769. #define CSL_EVETPCC_QEECR_RN_E3_RESETVAL (0x00000000U)
  7770. #define CSL_EVETPCC_QEECR_RN_E3_MAX (0x00000001U)
  7771. #define CSL_EVETPCC_QEECR_RN_E2_MASK (0x00000004U)
  7772. #define CSL_EVETPCC_QEECR_RN_E2_SHIFT (2U)
  7773. #define CSL_EVETPCC_QEECR_RN_E2_RESETVAL (0x00000000U)
  7774. #define CSL_EVETPCC_QEECR_RN_E2_MAX (0x00000001U)
  7775. #define CSL_EVETPCC_QEECR_RN_E1_MASK (0x00000002U)
  7776. #define CSL_EVETPCC_QEECR_RN_E1_SHIFT (1U)
  7777. #define CSL_EVETPCC_QEECR_RN_E1_RESETVAL (0x00000000U)
  7778. #define CSL_EVETPCC_QEECR_RN_E1_MAX (0x00000001U)
  7779. #define CSL_EVETPCC_QEECR_RN_E4_MASK (0x00000010U)
  7780. #define CSL_EVETPCC_QEECR_RN_E4_SHIFT (4U)
  7781. #define CSL_EVETPCC_QEECR_RN_E4_RESETVAL (0x00000000U)
  7782. #define CSL_EVETPCC_QEECR_RN_E4_MAX (0x00000001U)
  7783. #define CSL_EVETPCC_QEECR_RN_E0_MASK (0x00000001U)
  7784. #define CSL_EVETPCC_QEECR_RN_E0_SHIFT (0U)
  7785. #define CSL_EVETPCC_QEECR_RN_E0_RESETVAL (0x00000000U)
  7786. #define CSL_EVETPCC_QEECR_RN_E0_MAX (0x00000001U)
  7787. #define CSL_EVETPCC_QEECR_RN_E6_MASK (0x00000040U)
  7788. #define CSL_EVETPCC_QEECR_RN_E6_SHIFT (6U)
  7789. #define CSL_EVETPCC_QEECR_RN_E6_RESETVAL (0x00000000U)
  7790. #define CSL_EVETPCC_QEECR_RN_E6_MAX (0x00000001U)
  7791. #define CSL_EVETPCC_QEECR_RN_E5_MASK (0x00000020U)
  7792. #define CSL_EVETPCC_QEECR_RN_E5_SHIFT (5U)
  7793. #define CSL_EVETPCC_QEECR_RN_E5_RESETVAL (0x00000000U)
  7794. #define CSL_EVETPCC_QEECR_RN_E5_MAX (0x00000001U)
  7795. #define CSL_EVETPCC_QEECR_RN_E7_MASK (0x00000080U)
  7796. #define CSL_EVETPCC_QEECR_RN_E7_SHIFT (7U)
  7797. #define CSL_EVETPCC_QEECR_RN_E7_RESETVAL (0x00000000U)
  7798. #define CSL_EVETPCC_QEECR_RN_E7_MAX (0x00000001U)
  7799. #define CSL_EVETPCC_QEECR_RN_RESETVAL (0x00000000U)
  7800. /* EER_RN */
  7801. #define CSL_EVETPCC_EER_RN_E11_MASK (0x00000800U)
  7802. #define CSL_EVETPCC_EER_RN_E11_SHIFT (11U)
  7803. #define CSL_EVETPCC_EER_RN_E11_RESETVAL (0x00000000U)
  7804. #define CSL_EVETPCC_EER_RN_E11_MAX (0x00000001U)
  7805. #define CSL_EVETPCC_EER_RN_E24_MASK (0x01000000U)
  7806. #define CSL_EVETPCC_EER_RN_E24_SHIFT (24U)
  7807. #define CSL_EVETPCC_EER_RN_E24_RESETVAL (0x00000000U)
  7808. #define CSL_EVETPCC_EER_RN_E24_MAX (0x00000001U)
  7809. #define CSL_EVETPCC_EER_RN_E10_MASK (0x00000400U)
  7810. #define CSL_EVETPCC_EER_RN_E10_SHIFT (10U)
  7811. #define CSL_EVETPCC_EER_RN_E10_RESETVAL (0x00000000U)
  7812. #define CSL_EVETPCC_EER_RN_E10_MAX (0x00000001U)
  7813. #define CSL_EVETPCC_EER_RN_E12_MASK (0x00001000U)
  7814. #define CSL_EVETPCC_EER_RN_E12_SHIFT (12U)
  7815. #define CSL_EVETPCC_EER_RN_E12_RESETVAL (0x00000000U)
  7816. #define CSL_EVETPCC_EER_RN_E12_MAX (0x00000001U)
  7817. #define CSL_EVETPCC_EER_RN_E25_MASK (0x02000000U)
  7818. #define CSL_EVETPCC_EER_RN_E25_SHIFT (25U)
  7819. #define CSL_EVETPCC_EER_RN_E25_RESETVAL (0x00000000U)
  7820. #define CSL_EVETPCC_EER_RN_E25_MAX (0x00000001U)
  7821. #define CSL_EVETPCC_EER_RN_E9_MASK (0x00000200U)
  7822. #define CSL_EVETPCC_EER_RN_E9_SHIFT (9U)
  7823. #define CSL_EVETPCC_EER_RN_E9_RESETVAL (0x00000000U)
  7824. #define CSL_EVETPCC_EER_RN_E9_MAX (0x00000001U)
  7825. #define CSL_EVETPCC_EER_RN_E21_MASK (0x00200000U)
  7826. #define CSL_EVETPCC_EER_RN_E21_SHIFT (21U)
  7827. #define CSL_EVETPCC_EER_RN_E21_RESETVAL (0x00000000U)
  7828. #define CSL_EVETPCC_EER_RN_E21_MAX (0x00000001U)
  7829. #define CSL_EVETPCC_EER_RN_E22_MASK (0x00400000U)
  7830. #define CSL_EVETPCC_EER_RN_E22_SHIFT (22U)
  7831. #define CSL_EVETPCC_EER_RN_E22_RESETVAL (0x00000000U)
  7832. #define CSL_EVETPCC_EER_RN_E22_MAX (0x00000001U)
  7833. #define CSL_EVETPCC_EER_RN_E0_MASK (0x00000001U)
  7834. #define CSL_EVETPCC_EER_RN_E0_SHIFT (0U)
  7835. #define CSL_EVETPCC_EER_RN_E0_RESETVAL (0x00000000U)
  7836. #define CSL_EVETPCC_EER_RN_E0_MAX (0x00000001U)
  7837. #define CSL_EVETPCC_EER_RN_E23_MASK (0x00800000U)
  7838. #define CSL_EVETPCC_EER_RN_E23_SHIFT (23U)
  7839. #define CSL_EVETPCC_EER_RN_E23_RESETVAL (0x00000000U)
  7840. #define CSL_EVETPCC_EER_RN_E23_MAX (0x00000001U)
  7841. #define CSL_EVETPCC_EER_RN_E19_MASK (0x00080000U)
  7842. #define CSL_EVETPCC_EER_RN_E19_SHIFT (19U)
  7843. #define CSL_EVETPCC_EER_RN_E19_RESETVAL (0x00000000U)
  7844. #define CSL_EVETPCC_EER_RN_E19_MAX (0x00000001U)
  7845. #define CSL_EVETPCC_EER_RN_E20_MASK (0x00100000U)
  7846. #define CSL_EVETPCC_EER_RN_E20_SHIFT (20U)
  7847. #define CSL_EVETPCC_EER_RN_E20_RESETVAL (0x00000000U)
  7848. #define CSL_EVETPCC_EER_RN_E20_MAX (0x00000001U)
  7849. #define CSL_EVETPCC_EER_RN_E29_MASK (0x20000000U)
  7850. #define CSL_EVETPCC_EER_RN_E29_SHIFT (29U)
  7851. #define CSL_EVETPCC_EER_RN_E29_RESETVAL (0x00000000U)
  7852. #define CSL_EVETPCC_EER_RN_E29_MAX (0x00000001U)
  7853. #define CSL_EVETPCC_EER_RN_E30_MASK (0x40000000U)
  7854. #define CSL_EVETPCC_EER_RN_E30_SHIFT (30U)
  7855. #define CSL_EVETPCC_EER_RN_E30_RESETVAL (0x00000000U)
  7856. #define CSL_EVETPCC_EER_RN_E30_MAX (0x00000001U)
  7857. #define CSL_EVETPCC_EER_RN_E18_MASK (0x00040000U)
  7858. #define CSL_EVETPCC_EER_RN_E18_SHIFT (18U)
  7859. #define CSL_EVETPCC_EER_RN_E18_RESETVAL (0x00000000U)
  7860. #define CSL_EVETPCC_EER_RN_E18_MAX (0x00000001U)
  7861. #define CSL_EVETPCC_EER_RN_E31_MASK (0x80000000U)
  7862. #define CSL_EVETPCC_EER_RN_E31_SHIFT (31U)
  7863. #define CSL_EVETPCC_EER_RN_E31_RESETVAL (0x00000000U)
  7864. #define CSL_EVETPCC_EER_RN_E31_MAX (0x00000001U)
  7865. #define CSL_EVETPCC_EER_RN_E5_MASK (0x00000020U)
  7866. #define CSL_EVETPCC_EER_RN_E5_SHIFT (5U)
  7867. #define CSL_EVETPCC_EER_RN_E5_RESETVAL (0x00000000U)
  7868. #define CSL_EVETPCC_EER_RN_E5_MAX (0x00000001U)
  7869. #define CSL_EVETPCC_EER_RN_E6_MASK (0x00000040U)
  7870. #define CSL_EVETPCC_EER_RN_E6_SHIFT (6U)
  7871. #define CSL_EVETPCC_EER_RN_E6_RESETVAL (0x00000000U)
  7872. #define CSL_EVETPCC_EER_RN_E6_MAX (0x00000001U)
  7873. #define CSL_EVETPCC_EER_RN_E8_MASK (0x00000100U)
  7874. #define CSL_EVETPCC_EER_RN_E8_SHIFT (8U)
  7875. #define CSL_EVETPCC_EER_RN_E8_RESETVAL (0x00000000U)
  7876. #define CSL_EVETPCC_EER_RN_E8_MAX (0x00000001U)
  7877. #define CSL_EVETPCC_EER_RN_E7_MASK (0x00000080U)
  7878. #define CSL_EVETPCC_EER_RN_E7_SHIFT (7U)
  7879. #define CSL_EVETPCC_EER_RN_E7_RESETVAL (0x00000000U)
  7880. #define CSL_EVETPCC_EER_RN_E7_MAX (0x00000001U)
  7881. #define CSL_EVETPCC_EER_RN_E28_MASK (0x10000000U)
  7882. #define CSL_EVETPCC_EER_RN_E28_SHIFT (28U)
  7883. #define CSL_EVETPCC_EER_RN_E28_RESETVAL (0x00000000U)
  7884. #define CSL_EVETPCC_EER_RN_E28_MAX (0x00000001U)
  7885. #define CSL_EVETPCC_EER_RN_E3_MASK (0x00000008U)
  7886. #define CSL_EVETPCC_EER_RN_E3_SHIFT (3U)
  7887. #define CSL_EVETPCC_EER_RN_E3_RESETVAL (0x00000000U)
  7888. #define CSL_EVETPCC_EER_RN_E3_MAX (0x00000001U)
  7889. #define CSL_EVETPCC_EER_RN_E2_MASK (0x00000004U)
  7890. #define CSL_EVETPCC_EER_RN_E2_SHIFT (2U)
  7891. #define CSL_EVETPCC_EER_RN_E2_RESETVAL (0x00000000U)
  7892. #define CSL_EVETPCC_EER_RN_E2_MAX (0x00000001U)
  7893. #define CSL_EVETPCC_EER_RN_E1_MASK (0x00000002U)
  7894. #define CSL_EVETPCC_EER_RN_E1_SHIFT (1U)
  7895. #define CSL_EVETPCC_EER_RN_E1_RESETVAL (0x00000000U)
  7896. #define CSL_EVETPCC_EER_RN_E1_MAX (0x00000001U)
  7897. #define CSL_EVETPCC_EER_RN_E13_MASK (0x00002000U)
  7898. #define CSL_EVETPCC_EER_RN_E13_SHIFT (13U)
  7899. #define CSL_EVETPCC_EER_RN_E13_RESETVAL (0x00000000U)
  7900. #define CSL_EVETPCC_EER_RN_E13_MAX (0x00000001U)
  7901. #define CSL_EVETPCC_EER_RN_E17_MASK (0x00020000U)
  7902. #define CSL_EVETPCC_EER_RN_E17_SHIFT (17U)
  7903. #define CSL_EVETPCC_EER_RN_E17_RESETVAL (0x00000000U)
  7904. #define CSL_EVETPCC_EER_RN_E17_MAX (0x00000001U)
  7905. #define CSL_EVETPCC_EER_RN_E26_MASK (0x04000000U)
  7906. #define CSL_EVETPCC_EER_RN_E26_SHIFT (26U)
  7907. #define CSL_EVETPCC_EER_RN_E26_RESETVAL (0x00000000U)
  7908. #define CSL_EVETPCC_EER_RN_E26_MAX (0x00000001U)
  7909. #define CSL_EVETPCC_EER_RN_E14_MASK (0x00004000U)
  7910. #define CSL_EVETPCC_EER_RN_E14_SHIFT (14U)
  7911. #define CSL_EVETPCC_EER_RN_E14_RESETVAL (0x00000000U)
  7912. #define CSL_EVETPCC_EER_RN_E14_MAX (0x00000001U)
  7913. #define CSL_EVETPCC_EER_RN_E16_MASK (0x00010000U)
  7914. #define CSL_EVETPCC_EER_RN_E16_SHIFT (16U)
  7915. #define CSL_EVETPCC_EER_RN_E16_RESETVAL (0x00000000U)
  7916. #define CSL_EVETPCC_EER_RN_E16_MAX (0x00000001U)
  7917. #define CSL_EVETPCC_EER_RN_E27_MASK (0x08000000U)
  7918. #define CSL_EVETPCC_EER_RN_E27_SHIFT (27U)
  7919. #define CSL_EVETPCC_EER_RN_E27_RESETVAL (0x00000000U)
  7920. #define CSL_EVETPCC_EER_RN_E27_MAX (0x00000001U)
  7921. #define CSL_EVETPCC_EER_RN_E4_MASK (0x00000010U)
  7922. #define CSL_EVETPCC_EER_RN_E4_SHIFT (4U)
  7923. #define CSL_EVETPCC_EER_RN_E4_RESETVAL (0x00000000U)
  7924. #define CSL_EVETPCC_EER_RN_E4_MAX (0x00000001U)
  7925. #define CSL_EVETPCC_EER_RN_E15_MASK (0x00008000U)
  7926. #define CSL_EVETPCC_EER_RN_E15_SHIFT (15U)
  7927. #define CSL_EVETPCC_EER_RN_E15_RESETVAL (0x00000000U)
  7928. #define CSL_EVETPCC_EER_RN_E15_MAX (0x00000001U)
  7929. #define CSL_EVETPCC_EER_RN_RESETVAL (0x00000000U)
  7930. /* CERH_RN */
  7931. #define CSL_EVETPCC_CERH_RN_E49_MASK (0x00020000U)
  7932. #define CSL_EVETPCC_CERH_RN_E49_SHIFT (17U)
  7933. #define CSL_EVETPCC_CERH_RN_E49_RESETVAL (0x00000000U)
  7934. #define CSL_EVETPCC_CERH_RN_E49_MAX (0x00000001U)
  7935. #define CSL_EVETPCC_CERH_RN_E38_MASK (0x00000040U)
  7936. #define CSL_EVETPCC_CERH_RN_E38_SHIFT (6U)
  7937. #define CSL_EVETPCC_CERH_RN_E38_RESETVAL (0x00000000U)
  7938. #define CSL_EVETPCC_CERH_RN_E38_MAX (0x00000001U)
  7939. #define CSL_EVETPCC_CERH_RN_E39_MASK (0x00000080U)
  7940. #define CSL_EVETPCC_CERH_RN_E39_SHIFT (7U)
  7941. #define CSL_EVETPCC_CERH_RN_E39_RESETVAL (0x00000000U)
  7942. #define CSL_EVETPCC_CERH_RN_E39_MAX (0x00000001U)
  7943. #define CSL_EVETPCC_CERH_RN_E40_MASK (0x00000100U)
  7944. #define CSL_EVETPCC_CERH_RN_E40_SHIFT (8U)
  7945. #define CSL_EVETPCC_CERH_RN_E40_RESETVAL (0x00000000U)
  7946. #define CSL_EVETPCC_CERH_RN_E40_MAX (0x00000001U)
  7947. #define CSL_EVETPCC_CERH_RN_E63_MASK (0x80000000U)
  7948. #define CSL_EVETPCC_CERH_RN_E63_SHIFT (31U)
  7949. #define CSL_EVETPCC_CERH_RN_E63_RESETVAL (0x00000000U)
  7950. #define CSL_EVETPCC_CERH_RN_E63_MAX (0x00000001U)
  7951. #define CSL_EVETPCC_CERH_RN_E41_MASK (0x00000200U)
  7952. #define CSL_EVETPCC_CERH_RN_E41_SHIFT (9U)
  7953. #define CSL_EVETPCC_CERH_RN_E41_RESETVAL (0x00000000U)
  7954. #define CSL_EVETPCC_CERH_RN_E41_MAX (0x00000001U)
  7955. #define CSL_EVETPCC_CERH_RN_E62_MASK (0x40000000U)
  7956. #define CSL_EVETPCC_CERH_RN_E62_SHIFT (30U)
  7957. #define CSL_EVETPCC_CERH_RN_E62_RESETVAL (0x00000000U)
  7958. #define CSL_EVETPCC_CERH_RN_E62_MAX (0x00000001U)
  7959. #define CSL_EVETPCC_CERH_RN_E61_MASK (0x20000000U)
  7960. #define CSL_EVETPCC_CERH_RN_E61_SHIFT (29U)
  7961. #define CSL_EVETPCC_CERH_RN_E61_RESETVAL (0x00000000U)
  7962. #define CSL_EVETPCC_CERH_RN_E61_MAX (0x00000001U)
  7963. #define CSL_EVETPCC_CERH_RN_E42_MASK (0x00000400U)
  7964. #define CSL_EVETPCC_CERH_RN_E42_SHIFT (10U)
  7965. #define CSL_EVETPCC_CERH_RN_E42_RESETVAL (0x00000000U)
  7966. #define CSL_EVETPCC_CERH_RN_E42_MAX (0x00000001U)
  7967. #define CSL_EVETPCC_CERH_RN_E32_MASK (0x00000001U)
  7968. #define CSL_EVETPCC_CERH_RN_E32_SHIFT (0U)
  7969. #define CSL_EVETPCC_CERH_RN_E32_RESETVAL (0x00000000U)
  7970. #define CSL_EVETPCC_CERH_RN_E32_MAX (0x00000001U)
  7971. #define CSL_EVETPCC_CERH_RN_E57_MASK (0x02000000U)
  7972. #define CSL_EVETPCC_CERH_RN_E57_SHIFT (25U)
  7973. #define CSL_EVETPCC_CERH_RN_E57_RESETVAL (0x00000000U)
  7974. #define CSL_EVETPCC_CERH_RN_E57_MAX (0x00000001U)
  7975. #define CSL_EVETPCC_CERH_RN_E43_MASK (0x00000800U)
  7976. #define CSL_EVETPCC_CERH_RN_E43_SHIFT (11U)
  7977. #define CSL_EVETPCC_CERH_RN_E43_RESETVAL (0x00000000U)
  7978. #define CSL_EVETPCC_CERH_RN_E43_MAX (0x00000001U)
  7979. #define CSL_EVETPCC_CERH_RN_E58_MASK (0x04000000U)
  7980. #define CSL_EVETPCC_CERH_RN_E58_SHIFT (26U)
  7981. #define CSL_EVETPCC_CERH_RN_E58_RESETVAL (0x00000000U)
  7982. #define CSL_EVETPCC_CERH_RN_E58_MAX (0x00000001U)
  7983. #define CSL_EVETPCC_CERH_RN_E44_MASK (0x00001000U)
  7984. #define CSL_EVETPCC_CERH_RN_E44_SHIFT (12U)
  7985. #define CSL_EVETPCC_CERH_RN_E44_RESETVAL (0x00000000U)
  7986. #define CSL_EVETPCC_CERH_RN_E44_MAX (0x00000001U)
  7987. #define CSL_EVETPCC_CERH_RN_E59_MASK (0x08000000U)
  7988. #define CSL_EVETPCC_CERH_RN_E59_SHIFT (27U)
  7989. #define CSL_EVETPCC_CERH_RN_E59_RESETVAL (0x00000000U)
  7990. #define CSL_EVETPCC_CERH_RN_E59_MAX (0x00000001U)
  7991. #define CSL_EVETPCC_CERH_RN_E60_MASK (0x10000000U)
  7992. #define CSL_EVETPCC_CERH_RN_E60_SHIFT (28U)
  7993. #define CSL_EVETPCC_CERH_RN_E60_RESETVAL (0x00000000U)
  7994. #define CSL_EVETPCC_CERH_RN_E60_MAX (0x00000001U)
  7995. #define CSL_EVETPCC_CERH_RN_E45_MASK (0x00002000U)
  7996. #define CSL_EVETPCC_CERH_RN_E45_SHIFT (13U)
  7997. #define CSL_EVETPCC_CERH_RN_E45_RESETVAL (0x00000000U)
  7998. #define CSL_EVETPCC_CERH_RN_E45_MAX (0x00000001U)
  7999. #define CSL_EVETPCC_CERH_RN_E33_MASK (0x00000002U)
  8000. #define CSL_EVETPCC_CERH_RN_E33_SHIFT (1U)
  8001. #define CSL_EVETPCC_CERH_RN_E33_RESETVAL (0x00000000U)
  8002. #define CSL_EVETPCC_CERH_RN_E33_MAX (0x00000001U)
  8003. #define CSL_EVETPCC_CERH_RN_E46_MASK (0x00004000U)
  8004. #define CSL_EVETPCC_CERH_RN_E46_SHIFT (14U)
  8005. #define CSL_EVETPCC_CERH_RN_E46_RESETVAL (0x00000000U)
  8006. #define CSL_EVETPCC_CERH_RN_E46_MAX (0x00000001U)
  8007. #define CSL_EVETPCC_CERH_RN_E34_MASK (0x00000004U)
  8008. #define CSL_EVETPCC_CERH_RN_E34_SHIFT (2U)
  8009. #define CSL_EVETPCC_CERH_RN_E34_RESETVAL (0x00000000U)
  8010. #define CSL_EVETPCC_CERH_RN_E34_MAX (0x00000001U)
  8011. #define CSL_EVETPCC_CERH_RN_E47_MASK (0x00008000U)
  8012. #define CSL_EVETPCC_CERH_RN_E47_SHIFT (15U)
  8013. #define CSL_EVETPCC_CERH_RN_E47_RESETVAL (0x00000000U)
  8014. #define CSL_EVETPCC_CERH_RN_E47_MAX (0x00000001U)
  8015. #define CSL_EVETPCC_CERH_RN_E53_MASK (0x00200000U)
  8016. #define CSL_EVETPCC_CERH_RN_E53_SHIFT (21U)
  8017. #define CSL_EVETPCC_CERH_RN_E53_RESETVAL (0x00000000U)
  8018. #define CSL_EVETPCC_CERH_RN_E53_MAX (0x00000001U)
  8019. #define CSL_EVETPCC_CERH_RN_E54_MASK (0x00400000U)
  8020. #define CSL_EVETPCC_CERH_RN_E54_SHIFT (22U)
  8021. #define CSL_EVETPCC_CERH_RN_E54_RESETVAL (0x00000000U)
  8022. #define CSL_EVETPCC_CERH_RN_E54_MAX (0x00000001U)
  8023. #define CSL_EVETPCC_CERH_RN_E50_MASK (0x00040000U)
  8024. #define CSL_EVETPCC_CERH_RN_E50_SHIFT (18U)
  8025. #define CSL_EVETPCC_CERH_RN_E50_RESETVAL (0x00000000U)
  8026. #define CSL_EVETPCC_CERH_RN_E50_MAX (0x00000001U)
  8027. #define CSL_EVETPCC_CERH_RN_E35_MASK (0x00000008U)
  8028. #define CSL_EVETPCC_CERH_RN_E35_SHIFT (3U)
  8029. #define CSL_EVETPCC_CERH_RN_E35_RESETVAL (0x00000000U)
  8030. #define CSL_EVETPCC_CERH_RN_E35_MAX (0x00000001U)
  8031. #define CSL_EVETPCC_CERH_RN_E48_MASK (0x00010000U)
  8032. #define CSL_EVETPCC_CERH_RN_E48_SHIFT (16U)
  8033. #define CSL_EVETPCC_CERH_RN_E48_RESETVAL (0x00000000U)
  8034. #define CSL_EVETPCC_CERH_RN_E48_MAX (0x00000001U)
  8035. #define CSL_EVETPCC_CERH_RN_E56_MASK (0x01000000U)
  8036. #define CSL_EVETPCC_CERH_RN_E56_SHIFT (24U)
  8037. #define CSL_EVETPCC_CERH_RN_E56_RESETVAL (0x00000000U)
  8038. #define CSL_EVETPCC_CERH_RN_E56_MAX (0x00000001U)
  8039. #define CSL_EVETPCC_CERH_RN_E51_MASK (0x00080000U)
  8040. #define CSL_EVETPCC_CERH_RN_E51_SHIFT (19U)
  8041. #define CSL_EVETPCC_CERH_RN_E51_RESETVAL (0x00000000U)
  8042. #define CSL_EVETPCC_CERH_RN_E51_MAX (0x00000001U)
  8043. #define CSL_EVETPCC_CERH_RN_E36_MASK (0x00000010U)
  8044. #define CSL_EVETPCC_CERH_RN_E36_SHIFT (4U)
  8045. #define CSL_EVETPCC_CERH_RN_E36_RESETVAL (0x00000000U)
  8046. #define CSL_EVETPCC_CERH_RN_E36_MAX (0x00000001U)
  8047. #define CSL_EVETPCC_CERH_RN_E55_MASK (0x00800000U)
  8048. #define CSL_EVETPCC_CERH_RN_E55_SHIFT (23U)
  8049. #define CSL_EVETPCC_CERH_RN_E55_RESETVAL (0x00000000U)
  8050. #define CSL_EVETPCC_CERH_RN_E55_MAX (0x00000001U)
  8051. #define CSL_EVETPCC_CERH_RN_E52_MASK (0x00100000U)
  8052. #define CSL_EVETPCC_CERH_RN_E52_SHIFT (20U)
  8053. #define CSL_EVETPCC_CERH_RN_E52_RESETVAL (0x00000000U)
  8054. #define CSL_EVETPCC_CERH_RN_E52_MAX (0x00000001U)
  8055. #define CSL_EVETPCC_CERH_RN_E37_MASK (0x00000020U)
  8056. #define CSL_EVETPCC_CERH_RN_E37_SHIFT (5U)
  8057. #define CSL_EVETPCC_CERH_RN_E37_RESETVAL (0x00000000U)
  8058. #define CSL_EVETPCC_CERH_RN_E37_MAX (0x00000001U)
  8059. #define CSL_EVETPCC_CERH_RN_RESETVAL (0x00000000U)
  8060. /* QEER_RN */
  8061. #define CSL_EVETPCC_QEER_RN_E6_MASK (0x00000040U)
  8062. #define CSL_EVETPCC_QEER_RN_E6_SHIFT (6U)
  8063. #define CSL_EVETPCC_QEER_RN_E6_RESETVAL (0x00000000U)
  8064. #define CSL_EVETPCC_QEER_RN_E6_MAX (0x00000001U)
  8065. #define CSL_EVETPCC_QEER_RN_E5_MASK (0x00000020U)
  8066. #define CSL_EVETPCC_QEER_RN_E5_SHIFT (5U)
  8067. #define CSL_EVETPCC_QEER_RN_E5_RESETVAL (0x00000000U)
  8068. #define CSL_EVETPCC_QEER_RN_E5_MAX (0x00000001U)
  8069. #define CSL_EVETPCC_QEER_RN_E7_MASK (0x00000080U)
  8070. #define CSL_EVETPCC_QEER_RN_E7_SHIFT (7U)
  8071. #define CSL_EVETPCC_QEER_RN_E7_RESETVAL (0x00000000U)
  8072. #define CSL_EVETPCC_QEER_RN_E7_MAX (0x00000001U)
  8073. #define CSL_EVETPCC_QEER_RN_E0_MASK (0x00000001U)
  8074. #define CSL_EVETPCC_QEER_RN_E0_SHIFT (0U)
  8075. #define CSL_EVETPCC_QEER_RN_E0_RESETVAL (0x00000000U)
  8076. #define CSL_EVETPCC_QEER_RN_E0_MAX (0x00000001U)
  8077. #define CSL_EVETPCC_QEER_RN_E2_MASK (0x00000004U)
  8078. #define CSL_EVETPCC_QEER_RN_E2_SHIFT (2U)
  8079. #define CSL_EVETPCC_QEER_RN_E2_RESETVAL (0x00000000U)
  8080. #define CSL_EVETPCC_QEER_RN_E2_MAX (0x00000001U)
  8081. #define CSL_EVETPCC_QEER_RN_E1_MASK (0x00000002U)
  8082. #define CSL_EVETPCC_QEER_RN_E1_SHIFT (1U)
  8083. #define CSL_EVETPCC_QEER_RN_E1_RESETVAL (0x00000000U)
  8084. #define CSL_EVETPCC_QEER_RN_E1_MAX (0x00000001U)
  8085. #define CSL_EVETPCC_QEER_RN_E4_MASK (0x00000010U)
  8086. #define CSL_EVETPCC_QEER_RN_E4_SHIFT (4U)
  8087. #define CSL_EVETPCC_QEER_RN_E4_RESETVAL (0x00000000U)
  8088. #define CSL_EVETPCC_QEER_RN_E4_MAX (0x00000001U)
  8089. #define CSL_EVETPCC_QEER_RN_E3_MASK (0x00000008U)
  8090. #define CSL_EVETPCC_QEER_RN_E3_SHIFT (3U)
  8091. #define CSL_EVETPCC_QEER_RN_E3_RESETVAL (0x00000000U)
  8092. #define CSL_EVETPCC_QEER_RN_E3_MAX (0x00000001U)
  8093. #define CSL_EVETPCC_QEER_RN_RESETVAL (0x00000000U)
  8094. /* QSECR_RN */
  8095. #define CSL_EVETPCC_QSECR_RN_E5_MASK (0x00000020U)
  8096. #define CSL_EVETPCC_QSECR_RN_E5_SHIFT (5U)
  8097. #define CSL_EVETPCC_QSECR_RN_E5_RESETVAL (0x00000000U)
  8098. #define CSL_EVETPCC_QSECR_RN_E5_MAX (0x00000001U)
  8099. #define CSL_EVETPCC_QSECR_RN_E6_MASK (0x00000040U)
  8100. #define CSL_EVETPCC_QSECR_RN_E6_SHIFT (6U)
  8101. #define CSL_EVETPCC_QSECR_RN_E6_RESETVAL (0x00000000U)
  8102. #define CSL_EVETPCC_QSECR_RN_E6_MAX (0x00000001U)
  8103. #define CSL_EVETPCC_QSECR_RN_E7_MASK (0x00000080U)
  8104. #define CSL_EVETPCC_QSECR_RN_E7_SHIFT (7U)
  8105. #define CSL_EVETPCC_QSECR_RN_E7_RESETVAL (0x00000000U)
  8106. #define CSL_EVETPCC_QSECR_RN_E7_MAX (0x00000001U)
  8107. #define CSL_EVETPCC_QSECR_RN_E0_MASK (0x00000001U)
  8108. #define CSL_EVETPCC_QSECR_RN_E0_SHIFT (0U)
  8109. #define CSL_EVETPCC_QSECR_RN_E0_RESETVAL (0x00000000U)
  8110. #define CSL_EVETPCC_QSECR_RN_E0_MAX (0x00000001U)
  8111. #define CSL_EVETPCC_QSECR_RN_E2_MASK (0x00000004U)
  8112. #define CSL_EVETPCC_QSECR_RN_E2_SHIFT (2U)
  8113. #define CSL_EVETPCC_QSECR_RN_E2_RESETVAL (0x00000000U)
  8114. #define CSL_EVETPCC_QSECR_RN_E2_MAX (0x00000001U)
  8115. #define CSL_EVETPCC_QSECR_RN_E1_MASK (0x00000002U)
  8116. #define CSL_EVETPCC_QSECR_RN_E1_SHIFT (1U)
  8117. #define CSL_EVETPCC_QSECR_RN_E1_RESETVAL (0x00000000U)
  8118. #define CSL_EVETPCC_QSECR_RN_E1_MAX (0x00000001U)
  8119. #define CSL_EVETPCC_QSECR_RN_E4_MASK (0x00000010U)
  8120. #define CSL_EVETPCC_QSECR_RN_E4_SHIFT (4U)
  8121. #define CSL_EVETPCC_QSECR_RN_E4_RESETVAL (0x00000000U)
  8122. #define CSL_EVETPCC_QSECR_RN_E4_MAX (0x00000001U)
  8123. #define CSL_EVETPCC_QSECR_RN_E3_MASK (0x00000008U)
  8124. #define CSL_EVETPCC_QSECR_RN_E3_SHIFT (3U)
  8125. #define CSL_EVETPCC_QSECR_RN_E3_RESETVAL (0x00000000U)
  8126. #define CSL_EVETPCC_QSECR_RN_E3_MAX (0x00000001U)
  8127. #define CSL_EVETPCC_QSECR_RN_RESETVAL (0x00000000U)
  8128. /* ECRH_RN */
  8129. #define CSL_EVETPCC_ECRH_RN_E50_MASK (0x00040000U)
  8130. #define CSL_EVETPCC_ECRH_RN_E50_SHIFT (18U)
  8131. #define CSL_EVETPCC_ECRH_RN_E50_RESETVAL (0x00000000U)
  8132. #define CSL_EVETPCC_ECRH_RN_E50_MAX (0x00000001U)
  8133. #define CSL_EVETPCC_ECRH_RN_E36_MASK (0x00000010U)
  8134. #define CSL_EVETPCC_ECRH_RN_E36_SHIFT (4U)
  8135. #define CSL_EVETPCC_ECRH_RN_E36_RESETVAL (0x00000000U)
  8136. #define CSL_EVETPCC_ECRH_RN_E36_MAX (0x00000001U)
  8137. #define CSL_EVETPCC_ECRH_RN_E60_MASK (0x10000000U)
  8138. #define CSL_EVETPCC_ECRH_RN_E60_SHIFT (28U)
  8139. #define CSL_EVETPCC_ECRH_RN_E60_RESETVAL (0x00000000U)
  8140. #define CSL_EVETPCC_ECRH_RN_E60_MAX (0x00000001U)
  8141. #define CSL_EVETPCC_ECRH_RN_E49_MASK (0x00020000U)
  8142. #define CSL_EVETPCC_ECRH_RN_E49_SHIFT (17U)
  8143. #define CSL_EVETPCC_ECRH_RN_E49_RESETVAL (0x00000000U)
  8144. #define CSL_EVETPCC_ECRH_RN_E49_MAX (0x00000001U)
  8145. #define CSL_EVETPCC_ECRH_RN_E37_MASK (0x00000020U)
  8146. #define CSL_EVETPCC_ECRH_RN_E37_SHIFT (5U)
  8147. #define CSL_EVETPCC_ECRH_RN_E37_RESETVAL (0x00000000U)
  8148. #define CSL_EVETPCC_ECRH_RN_E37_MAX (0x00000001U)
  8149. #define CSL_EVETPCC_ECRH_RN_E48_MASK (0x00010000U)
  8150. #define CSL_EVETPCC_ECRH_RN_E48_SHIFT (16U)
  8151. #define CSL_EVETPCC_ECRH_RN_E48_RESETVAL (0x00000000U)
  8152. #define CSL_EVETPCC_ECRH_RN_E48_MAX (0x00000001U)
  8153. #define CSL_EVETPCC_ECRH_RN_E58_MASK (0x04000000U)
  8154. #define CSL_EVETPCC_ECRH_RN_E58_SHIFT (26U)
  8155. #define CSL_EVETPCC_ECRH_RN_E58_RESETVAL (0x00000000U)
  8156. #define CSL_EVETPCC_ECRH_RN_E58_MAX (0x00000001U)
  8157. #define CSL_EVETPCC_ECRH_RN_E38_MASK (0x00000040U)
  8158. #define CSL_EVETPCC_ECRH_RN_E38_SHIFT (6U)
  8159. #define CSL_EVETPCC_ECRH_RN_E38_RESETVAL (0x00000000U)
  8160. #define CSL_EVETPCC_ECRH_RN_E38_MAX (0x00000001U)
  8161. #define CSL_EVETPCC_ECRH_RN_E63_MASK (0x80000000U)
  8162. #define CSL_EVETPCC_ECRH_RN_E63_SHIFT (31U)
  8163. #define CSL_EVETPCC_ECRH_RN_E63_RESETVAL (0x00000000U)
  8164. #define CSL_EVETPCC_ECRH_RN_E63_MAX (0x00000001U)
  8165. #define CSL_EVETPCC_ECRH_RN_E47_MASK (0x00008000U)
  8166. #define CSL_EVETPCC_ECRH_RN_E47_SHIFT (15U)
  8167. #define CSL_EVETPCC_ECRH_RN_E47_RESETVAL (0x00000000U)
  8168. #define CSL_EVETPCC_ECRH_RN_E47_MAX (0x00000001U)
  8169. #define CSL_EVETPCC_ECRH_RN_E39_MASK (0x00000080U)
  8170. #define CSL_EVETPCC_ECRH_RN_E39_SHIFT (7U)
  8171. #define CSL_EVETPCC_ECRH_RN_E39_RESETVAL (0x00000000U)
  8172. #define CSL_EVETPCC_ECRH_RN_E39_MAX (0x00000001U)
  8173. #define CSL_EVETPCC_ECRH_RN_E32_MASK (0x00000001U)
  8174. #define CSL_EVETPCC_ECRH_RN_E32_SHIFT (0U)
  8175. #define CSL_EVETPCC_ECRH_RN_E32_RESETVAL (0x00000000U)
  8176. #define CSL_EVETPCC_ECRH_RN_E32_MAX (0x00000001U)
  8177. #define CSL_EVETPCC_ECRH_RN_E51_MASK (0x00080000U)
  8178. #define CSL_EVETPCC_ECRH_RN_E51_SHIFT (19U)
  8179. #define CSL_EVETPCC_ECRH_RN_E51_RESETVAL (0x00000000U)
  8180. #define CSL_EVETPCC_ECRH_RN_E51_MAX (0x00000001U)
  8181. #define CSL_EVETPCC_ECRH_RN_E33_MASK (0x00000002U)
  8182. #define CSL_EVETPCC_ECRH_RN_E33_SHIFT (1U)
  8183. #define CSL_EVETPCC_ECRH_RN_E33_RESETVAL (0x00000000U)
  8184. #define CSL_EVETPCC_ECRH_RN_E33_MAX (0x00000001U)
  8185. #define CSL_EVETPCC_ECRH_RN_E34_MASK (0x00000004U)
  8186. #define CSL_EVETPCC_ECRH_RN_E34_SHIFT (2U)
  8187. #define CSL_EVETPCC_ECRH_RN_E34_RESETVAL (0x00000000U)
  8188. #define CSL_EVETPCC_ECRH_RN_E34_MAX (0x00000001U)
  8189. #define CSL_EVETPCC_ECRH_RN_E35_MASK (0x00000008U)
  8190. #define CSL_EVETPCC_ECRH_RN_E35_SHIFT (3U)
  8191. #define CSL_EVETPCC_ECRH_RN_E35_RESETVAL (0x00000000U)
  8192. #define CSL_EVETPCC_ECRH_RN_E35_MAX (0x00000001U)
  8193. #define CSL_EVETPCC_ECRH_RN_E42_MASK (0x00000400U)
  8194. #define CSL_EVETPCC_ECRH_RN_E42_SHIFT (10U)
  8195. #define CSL_EVETPCC_ECRH_RN_E42_RESETVAL (0x00000000U)
  8196. #define CSL_EVETPCC_ECRH_RN_E42_MAX (0x00000001U)
  8197. #define CSL_EVETPCC_ECRH_RN_E52_MASK (0x00100000U)
  8198. #define CSL_EVETPCC_ECRH_RN_E52_SHIFT (20U)
  8199. #define CSL_EVETPCC_ECRH_RN_E52_RESETVAL (0x00000000U)
  8200. #define CSL_EVETPCC_ECRH_RN_E52_MAX (0x00000001U)
  8201. #define CSL_EVETPCC_ECRH_RN_E41_MASK (0x00000200U)
  8202. #define CSL_EVETPCC_ECRH_RN_E41_SHIFT (9U)
  8203. #define CSL_EVETPCC_ECRH_RN_E41_RESETVAL (0x00000000U)
  8204. #define CSL_EVETPCC_ECRH_RN_E41_MAX (0x00000001U)
  8205. #define CSL_EVETPCC_ECRH_RN_E55_MASK (0x00800000U)
  8206. #define CSL_EVETPCC_ECRH_RN_E55_SHIFT (23U)
  8207. #define CSL_EVETPCC_ECRH_RN_E55_RESETVAL (0x00000000U)
  8208. #define CSL_EVETPCC_ECRH_RN_E55_MAX (0x00000001U)
  8209. #define CSL_EVETPCC_ECRH_RN_E53_MASK (0x00200000U)
  8210. #define CSL_EVETPCC_ECRH_RN_E53_SHIFT (21U)
  8211. #define CSL_EVETPCC_ECRH_RN_E53_RESETVAL (0x00000000U)
  8212. #define CSL_EVETPCC_ECRH_RN_E53_MAX (0x00000001U)
  8213. #define CSL_EVETPCC_ECRH_RN_E46_MASK (0x00004000U)
  8214. #define CSL_EVETPCC_ECRH_RN_E46_SHIFT (14U)
  8215. #define CSL_EVETPCC_ECRH_RN_E46_RESETVAL (0x00000000U)
  8216. #define CSL_EVETPCC_ECRH_RN_E46_MAX (0x00000001U)
  8217. #define CSL_EVETPCC_ECRH_RN_E62_MASK (0x40000000U)
  8218. #define CSL_EVETPCC_ECRH_RN_E62_SHIFT (30U)
  8219. #define CSL_EVETPCC_ECRH_RN_E62_RESETVAL (0x00000000U)
  8220. #define CSL_EVETPCC_ECRH_RN_E62_MAX (0x00000001U)
  8221. #define CSL_EVETPCC_ECRH_RN_E40_MASK (0x00000100U)
  8222. #define CSL_EVETPCC_ECRH_RN_E40_SHIFT (8U)
  8223. #define CSL_EVETPCC_ECRH_RN_E40_RESETVAL (0x00000000U)
  8224. #define CSL_EVETPCC_ECRH_RN_E40_MAX (0x00000001U)
  8225. #define CSL_EVETPCC_ECRH_RN_E56_MASK (0x01000000U)
  8226. #define CSL_EVETPCC_ECRH_RN_E56_SHIFT (24U)
  8227. #define CSL_EVETPCC_ECRH_RN_E56_RESETVAL (0x00000000U)
  8228. #define CSL_EVETPCC_ECRH_RN_E56_MAX (0x00000001U)
  8229. #define CSL_EVETPCC_ECRH_RN_E61_MASK (0x20000000U)
  8230. #define CSL_EVETPCC_ECRH_RN_E61_SHIFT (29U)
  8231. #define CSL_EVETPCC_ECRH_RN_E61_RESETVAL (0x00000000U)
  8232. #define CSL_EVETPCC_ECRH_RN_E61_MAX (0x00000001U)
  8233. #define CSL_EVETPCC_ECRH_RN_E45_MASK (0x00002000U)
  8234. #define CSL_EVETPCC_ECRH_RN_E45_SHIFT (13U)
  8235. #define CSL_EVETPCC_ECRH_RN_E45_RESETVAL (0x00000000U)
  8236. #define CSL_EVETPCC_ECRH_RN_E45_MAX (0x00000001U)
  8237. #define CSL_EVETPCC_ECRH_RN_E59_MASK (0x08000000U)
  8238. #define CSL_EVETPCC_ECRH_RN_E59_SHIFT (27U)
  8239. #define CSL_EVETPCC_ECRH_RN_E59_RESETVAL (0x00000000U)
  8240. #define CSL_EVETPCC_ECRH_RN_E59_MAX (0x00000001U)
  8241. #define CSL_EVETPCC_ECRH_RN_E44_MASK (0x00001000U)
  8242. #define CSL_EVETPCC_ECRH_RN_E44_SHIFT (12U)
  8243. #define CSL_EVETPCC_ECRH_RN_E44_RESETVAL (0x00000000U)
  8244. #define CSL_EVETPCC_ECRH_RN_E44_MAX (0x00000001U)
  8245. #define CSL_EVETPCC_ECRH_RN_E54_MASK (0x00400000U)
  8246. #define CSL_EVETPCC_ECRH_RN_E54_SHIFT (22U)
  8247. #define CSL_EVETPCC_ECRH_RN_E54_RESETVAL (0x00000000U)
  8248. #define CSL_EVETPCC_ECRH_RN_E54_MAX (0x00000001U)
  8249. #define CSL_EVETPCC_ECRH_RN_E43_MASK (0x00000800U)
  8250. #define CSL_EVETPCC_ECRH_RN_E43_SHIFT (11U)
  8251. #define CSL_EVETPCC_ECRH_RN_E43_RESETVAL (0x00000000U)
  8252. #define CSL_EVETPCC_ECRH_RN_E43_MAX (0x00000001U)
  8253. #define CSL_EVETPCC_ECRH_RN_E57_MASK (0x02000000U)
  8254. #define CSL_EVETPCC_ECRH_RN_E57_SHIFT (25U)
  8255. #define CSL_EVETPCC_ECRH_RN_E57_RESETVAL (0x00000000U)
  8256. #define CSL_EVETPCC_ECRH_RN_E57_MAX (0x00000001U)
  8257. #define CSL_EVETPCC_ECRH_RN_RESETVAL (0x00000000U)
  8258. /* ICR_RN */
  8259. #define CSL_EVETPCC_ICR_RN_I17_MASK (0x00020000U)
  8260. #define CSL_EVETPCC_ICR_RN_I17_SHIFT (17U)
  8261. #define CSL_EVETPCC_ICR_RN_I17_RESETVAL (0x00000000U)
  8262. #define CSL_EVETPCC_ICR_RN_I17_MAX (0x00000001U)
  8263. #define CSL_EVETPCC_ICR_RN_I30_MASK (0x40000000U)
  8264. #define CSL_EVETPCC_ICR_RN_I30_SHIFT (30U)
  8265. #define CSL_EVETPCC_ICR_RN_I30_RESETVAL (0x00000000U)
  8266. #define CSL_EVETPCC_ICR_RN_I30_MAX (0x00000001U)
  8267. #define CSL_EVETPCC_ICR_RN_I7_MASK (0x00000080U)
  8268. #define CSL_EVETPCC_ICR_RN_I7_SHIFT (7U)
  8269. #define CSL_EVETPCC_ICR_RN_I7_RESETVAL (0x00000000U)
  8270. #define CSL_EVETPCC_ICR_RN_I7_MAX (0x00000001U)
  8271. #define CSL_EVETPCC_ICR_RN_I19_MASK (0x00080000U)
  8272. #define CSL_EVETPCC_ICR_RN_I19_SHIFT (19U)
  8273. #define CSL_EVETPCC_ICR_RN_I19_RESETVAL (0x00000000U)
  8274. #define CSL_EVETPCC_ICR_RN_I19_MAX (0x00000001U)
  8275. #define CSL_EVETPCC_ICR_RN_I16_MASK (0x00010000U)
  8276. #define CSL_EVETPCC_ICR_RN_I16_SHIFT (16U)
  8277. #define CSL_EVETPCC_ICR_RN_I16_RESETVAL (0x00000000U)
  8278. #define CSL_EVETPCC_ICR_RN_I16_MAX (0x00000001U)
  8279. #define CSL_EVETPCC_ICR_RN_I6_MASK (0x00000040U)
  8280. #define CSL_EVETPCC_ICR_RN_I6_SHIFT (6U)
  8281. #define CSL_EVETPCC_ICR_RN_I6_RESETVAL (0x00000000U)
  8282. #define CSL_EVETPCC_ICR_RN_I6_MAX (0x00000001U)
  8283. #define CSL_EVETPCC_ICR_RN_I31_MASK (0x80000000U)
  8284. #define CSL_EVETPCC_ICR_RN_I31_SHIFT (31U)
  8285. #define CSL_EVETPCC_ICR_RN_I31_RESETVAL (0x00000000U)
  8286. #define CSL_EVETPCC_ICR_RN_I31_MAX (0x00000001U)
  8287. #define CSL_EVETPCC_ICR_RN_I20_MASK (0x00100000U)
  8288. #define CSL_EVETPCC_ICR_RN_I20_SHIFT (20U)
  8289. #define CSL_EVETPCC_ICR_RN_I20_RESETVAL (0x00000000U)
  8290. #define CSL_EVETPCC_ICR_RN_I20_MAX (0x00000001U)
  8291. #define CSL_EVETPCC_ICR_RN_I18_MASK (0x00040000U)
  8292. #define CSL_EVETPCC_ICR_RN_I18_SHIFT (18U)
  8293. #define CSL_EVETPCC_ICR_RN_I18_RESETVAL (0x00000000U)
  8294. #define CSL_EVETPCC_ICR_RN_I18_MAX (0x00000001U)
  8295. #define CSL_EVETPCC_ICR_RN_I21_MASK (0x00200000U)
  8296. #define CSL_EVETPCC_ICR_RN_I21_SHIFT (21U)
  8297. #define CSL_EVETPCC_ICR_RN_I21_RESETVAL (0x00000000U)
  8298. #define CSL_EVETPCC_ICR_RN_I21_MAX (0x00000001U)
  8299. #define CSL_EVETPCC_ICR_RN_I8_MASK (0x00000100U)
  8300. #define CSL_EVETPCC_ICR_RN_I8_SHIFT (8U)
  8301. #define CSL_EVETPCC_ICR_RN_I8_RESETVAL (0x00000000U)
  8302. #define CSL_EVETPCC_ICR_RN_I8_MAX (0x00000001U)
  8303. #define CSL_EVETPCC_ICR_RN_I22_MASK (0x00400000U)
  8304. #define CSL_EVETPCC_ICR_RN_I22_SHIFT (22U)
  8305. #define CSL_EVETPCC_ICR_RN_I22_RESETVAL (0x00000000U)
  8306. #define CSL_EVETPCC_ICR_RN_I22_MAX (0x00000001U)
  8307. #define CSL_EVETPCC_ICR_RN_I13_MASK (0x00002000U)
  8308. #define CSL_EVETPCC_ICR_RN_I13_SHIFT (13U)
  8309. #define CSL_EVETPCC_ICR_RN_I13_RESETVAL (0x00000000U)
  8310. #define CSL_EVETPCC_ICR_RN_I13_MAX (0x00000001U)
  8311. #define CSL_EVETPCC_ICR_RN_I3_MASK (0x00000008U)
  8312. #define CSL_EVETPCC_ICR_RN_I3_SHIFT (3U)
  8313. #define CSL_EVETPCC_ICR_RN_I3_RESETVAL (0x00000000U)
  8314. #define CSL_EVETPCC_ICR_RN_I3_MAX (0x00000001U)
  8315. #define CSL_EVETPCC_ICR_RN_I23_MASK (0x00800000U)
  8316. #define CSL_EVETPCC_ICR_RN_I23_SHIFT (23U)
  8317. #define CSL_EVETPCC_ICR_RN_I23_RESETVAL (0x00000000U)
  8318. #define CSL_EVETPCC_ICR_RN_I23_MAX (0x00000001U)
  8319. #define CSL_EVETPCC_ICR_RN_I12_MASK (0x00001000U)
  8320. #define CSL_EVETPCC_ICR_RN_I12_SHIFT (12U)
  8321. #define CSL_EVETPCC_ICR_RN_I12_RESETVAL (0x00000000U)
  8322. #define CSL_EVETPCC_ICR_RN_I12_MAX (0x00000001U)
  8323. #define CSL_EVETPCC_ICR_RN_I2_MASK (0x00000004U)
  8324. #define CSL_EVETPCC_ICR_RN_I2_SHIFT (2U)
  8325. #define CSL_EVETPCC_ICR_RN_I2_RESETVAL (0x00000000U)
  8326. #define CSL_EVETPCC_ICR_RN_I2_MAX (0x00000001U)
  8327. #define CSL_EVETPCC_ICR_RN_I24_MASK (0x01000000U)
  8328. #define CSL_EVETPCC_ICR_RN_I24_SHIFT (24U)
  8329. #define CSL_EVETPCC_ICR_RN_I24_RESETVAL (0x00000000U)
  8330. #define CSL_EVETPCC_ICR_RN_I24_MAX (0x00000001U)
  8331. #define CSL_EVETPCC_ICR_RN_I15_MASK (0x00008000U)
  8332. #define CSL_EVETPCC_ICR_RN_I15_SHIFT (15U)
  8333. #define CSL_EVETPCC_ICR_RN_I15_RESETVAL (0x00000000U)
  8334. #define CSL_EVETPCC_ICR_RN_I15_MAX (0x00000001U)
  8335. #define CSL_EVETPCC_ICR_RN_I25_MASK (0x02000000U)
  8336. #define CSL_EVETPCC_ICR_RN_I25_SHIFT (25U)
  8337. #define CSL_EVETPCC_ICR_RN_I25_RESETVAL (0x00000000U)
  8338. #define CSL_EVETPCC_ICR_RN_I25_MAX (0x00000001U)
  8339. #define CSL_EVETPCC_ICR_RN_I5_MASK (0x00000020U)
  8340. #define CSL_EVETPCC_ICR_RN_I5_SHIFT (5U)
  8341. #define CSL_EVETPCC_ICR_RN_I5_RESETVAL (0x00000000U)
  8342. #define CSL_EVETPCC_ICR_RN_I5_MAX (0x00000001U)
  8343. #define CSL_EVETPCC_ICR_RN_I14_MASK (0x00004000U)
  8344. #define CSL_EVETPCC_ICR_RN_I14_SHIFT (14U)
  8345. #define CSL_EVETPCC_ICR_RN_I14_RESETVAL (0x00000000U)
  8346. #define CSL_EVETPCC_ICR_RN_I14_MAX (0x00000001U)
  8347. #define CSL_EVETPCC_ICR_RN_I4_MASK (0x00000010U)
  8348. #define CSL_EVETPCC_ICR_RN_I4_SHIFT (4U)
  8349. #define CSL_EVETPCC_ICR_RN_I4_RESETVAL (0x00000000U)
  8350. #define CSL_EVETPCC_ICR_RN_I4_MAX (0x00000001U)
  8351. #define CSL_EVETPCC_ICR_RN_I9_MASK (0x00000200U)
  8352. #define CSL_EVETPCC_ICR_RN_I9_SHIFT (9U)
  8353. #define CSL_EVETPCC_ICR_RN_I9_RESETVAL (0x00000000U)
  8354. #define CSL_EVETPCC_ICR_RN_I9_MAX (0x00000001U)
  8355. #define CSL_EVETPCC_ICR_RN_I27_MASK (0x08000000U)
  8356. #define CSL_EVETPCC_ICR_RN_I27_SHIFT (27U)
  8357. #define CSL_EVETPCC_ICR_RN_I27_RESETVAL (0x00000000U)
  8358. #define CSL_EVETPCC_ICR_RN_I27_MAX (0x00000001U)
  8359. #define CSL_EVETPCC_ICR_RN_I26_MASK (0x04000000U)
  8360. #define CSL_EVETPCC_ICR_RN_I26_SHIFT (26U)
  8361. #define CSL_EVETPCC_ICR_RN_I26_RESETVAL (0x00000000U)
  8362. #define CSL_EVETPCC_ICR_RN_I26_MAX (0x00000001U)
  8363. #define CSL_EVETPCC_ICR_RN_I11_MASK (0x00000800U)
  8364. #define CSL_EVETPCC_ICR_RN_I11_SHIFT (11U)
  8365. #define CSL_EVETPCC_ICR_RN_I11_RESETVAL (0x00000000U)
  8366. #define CSL_EVETPCC_ICR_RN_I11_MAX (0x00000001U)
  8367. #define CSL_EVETPCC_ICR_RN_I1_MASK (0x00000002U)
  8368. #define CSL_EVETPCC_ICR_RN_I1_SHIFT (1U)
  8369. #define CSL_EVETPCC_ICR_RN_I1_RESETVAL (0x00000000U)
  8370. #define CSL_EVETPCC_ICR_RN_I1_MAX (0x00000001U)
  8371. #define CSL_EVETPCC_ICR_RN_I10_MASK (0x00000400U)
  8372. #define CSL_EVETPCC_ICR_RN_I10_SHIFT (10U)
  8373. #define CSL_EVETPCC_ICR_RN_I10_RESETVAL (0x00000000U)
  8374. #define CSL_EVETPCC_ICR_RN_I10_MAX (0x00000001U)
  8375. #define CSL_EVETPCC_ICR_RN_I28_MASK (0x10000000U)
  8376. #define CSL_EVETPCC_ICR_RN_I28_SHIFT (28U)
  8377. #define CSL_EVETPCC_ICR_RN_I28_RESETVAL (0x00000000U)
  8378. #define CSL_EVETPCC_ICR_RN_I28_MAX (0x00000001U)
  8379. #define CSL_EVETPCC_ICR_RN_I0_MASK (0x00000001U)
  8380. #define CSL_EVETPCC_ICR_RN_I0_SHIFT (0U)
  8381. #define CSL_EVETPCC_ICR_RN_I0_RESETVAL (0x00000000U)
  8382. #define CSL_EVETPCC_ICR_RN_I0_MAX (0x00000001U)
  8383. #define CSL_EVETPCC_ICR_RN_I29_MASK (0x20000000U)
  8384. #define CSL_EVETPCC_ICR_RN_I29_SHIFT (29U)
  8385. #define CSL_EVETPCC_ICR_RN_I29_RESETVAL (0x00000000U)
  8386. #define CSL_EVETPCC_ICR_RN_I29_MAX (0x00000001U)
  8387. #define CSL_EVETPCC_ICR_RN_RESETVAL (0x00000000U)
  8388. /* IPRH_RN */
  8389. #define CSL_EVETPCC_IPRH_RN_I53_MASK (0x00200000U)
  8390. #define CSL_EVETPCC_IPRH_RN_I53_SHIFT (21U)
  8391. #define CSL_EVETPCC_IPRH_RN_I53_RESETVAL (0x00000000U)
  8392. #define CSL_EVETPCC_IPRH_RN_I53_MAX (0x00000001U)
  8393. #define CSL_EVETPCC_IPRH_RN_I41_MASK (0x00000200U)
  8394. #define CSL_EVETPCC_IPRH_RN_I41_SHIFT (9U)
  8395. #define CSL_EVETPCC_IPRH_RN_I41_RESETVAL (0x00000000U)
  8396. #define CSL_EVETPCC_IPRH_RN_I41_MAX (0x00000001U)
  8397. #define CSL_EVETPCC_IPRH_RN_I52_MASK (0x00100000U)
  8398. #define CSL_EVETPCC_IPRH_RN_I52_SHIFT (20U)
  8399. #define CSL_EVETPCC_IPRH_RN_I52_RESETVAL (0x00000000U)
  8400. #define CSL_EVETPCC_IPRH_RN_I52_MAX (0x00000001U)
  8401. #define CSL_EVETPCC_IPRH_RN_I40_MASK (0x00000100U)
  8402. #define CSL_EVETPCC_IPRH_RN_I40_SHIFT (8U)
  8403. #define CSL_EVETPCC_IPRH_RN_I40_RESETVAL (0x00000000U)
  8404. #define CSL_EVETPCC_IPRH_RN_I40_MAX (0x00000001U)
  8405. #define CSL_EVETPCC_IPRH_RN_I51_MASK (0x00080000U)
  8406. #define CSL_EVETPCC_IPRH_RN_I51_SHIFT (19U)
  8407. #define CSL_EVETPCC_IPRH_RN_I51_RESETVAL (0x00000000U)
  8408. #define CSL_EVETPCC_IPRH_RN_I51_MAX (0x00000001U)
  8409. #define CSL_EVETPCC_IPRH_RN_I39_MASK (0x00000080U)
  8410. #define CSL_EVETPCC_IPRH_RN_I39_SHIFT (7U)
  8411. #define CSL_EVETPCC_IPRH_RN_I39_RESETVAL (0x00000000U)
  8412. #define CSL_EVETPCC_IPRH_RN_I39_MAX (0x00000001U)
  8413. #define CSL_EVETPCC_IPRH_RN_I32_MASK (0x00000001U)
  8414. #define CSL_EVETPCC_IPRH_RN_I32_SHIFT (0U)
  8415. #define CSL_EVETPCC_IPRH_RN_I32_RESETVAL (0x00000000U)
  8416. #define CSL_EVETPCC_IPRH_RN_I32_MAX (0x00000001U)
  8417. #define CSL_EVETPCC_IPRH_RN_I50_MASK (0x00040000U)
  8418. #define CSL_EVETPCC_IPRH_RN_I50_SHIFT (18U)
  8419. #define CSL_EVETPCC_IPRH_RN_I50_RESETVAL (0x00000000U)
  8420. #define CSL_EVETPCC_IPRH_RN_I50_MAX (0x00000001U)
  8421. #define CSL_EVETPCC_IPRH_RN_I33_MASK (0x00000002U)
  8422. #define CSL_EVETPCC_IPRH_RN_I33_SHIFT (1U)
  8423. #define CSL_EVETPCC_IPRH_RN_I33_RESETVAL (0x00000000U)
  8424. #define CSL_EVETPCC_IPRH_RN_I33_MAX (0x00000001U)
  8425. #define CSL_EVETPCC_IPRH_RN_I34_MASK (0x00000004U)
  8426. #define CSL_EVETPCC_IPRH_RN_I34_SHIFT (2U)
  8427. #define CSL_EVETPCC_IPRH_RN_I34_RESETVAL (0x00000000U)
  8428. #define CSL_EVETPCC_IPRH_RN_I34_MAX (0x00000001U)
  8429. #define CSL_EVETPCC_IPRH_RN_I49_MASK (0x00020000U)
  8430. #define CSL_EVETPCC_IPRH_RN_I49_SHIFT (17U)
  8431. #define CSL_EVETPCC_IPRH_RN_I49_RESETVAL (0x00000000U)
  8432. #define CSL_EVETPCC_IPRH_RN_I49_MAX (0x00000001U)
  8433. #define CSL_EVETPCC_IPRH_RN_I60_MASK (0x10000000U)
  8434. #define CSL_EVETPCC_IPRH_RN_I60_SHIFT (28U)
  8435. #define CSL_EVETPCC_IPRH_RN_I60_RESETVAL (0x00000000U)
  8436. #define CSL_EVETPCC_IPRH_RN_I60_MAX (0x00000001U)
  8437. #define CSL_EVETPCC_IPRH_RN_I47_MASK (0x00008000U)
  8438. #define CSL_EVETPCC_IPRH_RN_I47_SHIFT (15U)
  8439. #define CSL_EVETPCC_IPRH_RN_I47_RESETVAL (0x00000000U)
  8440. #define CSL_EVETPCC_IPRH_RN_I47_MAX (0x00000001U)
  8441. #define CSL_EVETPCC_IPRH_RN_I35_MASK (0x00000008U)
  8442. #define CSL_EVETPCC_IPRH_RN_I35_SHIFT (3U)
  8443. #define CSL_EVETPCC_IPRH_RN_I35_RESETVAL (0x00000000U)
  8444. #define CSL_EVETPCC_IPRH_RN_I35_MAX (0x00000001U)
  8445. #define CSL_EVETPCC_IPRH_RN_I36_MASK (0x00000010U)
  8446. #define CSL_EVETPCC_IPRH_RN_I36_SHIFT (4U)
  8447. #define CSL_EVETPCC_IPRH_RN_I36_RESETVAL (0x00000000U)
  8448. #define CSL_EVETPCC_IPRH_RN_I36_MAX (0x00000001U)
  8449. #define CSL_EVETPCC_IPRH_RN_I59_MASK (0x08000000U)
  8450. #define CSL_EVETPCC_IPRH_RN_I59_SHIFT (27U)
  8451. #define CSL_EVETPCC_IPRH_RN_I59_RESETVAL (0x00000000U)
  8452. #define CSL_EVETPCC_IPRH_RN_I59_MAX (0x00000001U)
  8453. #define CSL_EVETPCC_IPRH_RN_I48_MASK (0x00010000U)
  8454. #define CSL_EVETPCC_IPRH_RN_I48_SHIFT (16U)
  8455. #define CSL_EVETPCC_IPRH_RN_I48_RESETVAL (0x00000000U)
  8456. #define CSL_EVETPCC_IPRH_RN_I48_MAX (0x00000001U)
  8457. #define CSL_EVETPCC_IPRH_RN_I37_MASK (0x00000020U)
  8458. #define CSL_EVETPCC_IPRH_RN_I37_SHIFT (5U)
  8459. #define CSL_EVETPCC_IPRH_RN_I37_RESETVAL (0x00000000U)
  8460. #define CSL_EVETPCC_IPRH_RN_I37_MAX (0x00000001U)
  8461. #define CSL_EVETPCC_IPRH_RN_I61_MASK (0x20000000U)
  8462. #define CSL_EVETPCC_IPRH_RN_I61_SHIFT (29U)
  8463. #define CSL_EVETPCC_IPRH_RN_I61_RESETVAL (0x00000000U)
  8464. #define CSL_EVETPCC_IPRH_RN_I61_MAX (0x00000001U)
  8465. #define CSL_EVETPCC_IPRH_RN_I38_MASK (0x00000040U)
  8466. #define CSL_EVETPCC_IPRH_RN_I38_SHIFT (6U)
  8467. #define CSL_EVETPCC_IPRH_RN_I38_RESETVAL (0x00000000U)
  8468. #define CSL_EVETPCC_IPRH_RN_I38_MAX (0x00000001U)
  8469. #define CSL_EVETPCC_IPRH_RN_I58_MASK (0x04000000U)
  8470. #define CSL_EVETPCC_IPRH_RN_I58_SHIFT (26U)
  8471. #define CSL_EVETPCC_IPRH_RN_I58_RESETVAL (0x00000000U)
  8472. #define CSL_EVETPCC_IPRH_RN_I58_MAX (0x00000001U)
  8473. #define CSL_EVETPCC_IPRH_RN_I46_MASK (0x00004000U)
  8474. #define CSL_EVETPCC_IPRH_RN_I46_SHIFT (14U)
  8475. #define CSL_EVETPCC_IPRH_RN_I46_RESETVAL (0x00000000U)
  8476. #define CSL_EVETPCC_IPRH_RN_I46_MAX (0x00000001U)
  8477. #define CSL_EVETPCC_IPRH_RN_I45_MASK (0x00002000U)
  8478. #define CSL_EVETPCC_IPRH_RN_I45_SHIFT (13U)
  8479. #define CSL_EVETPCC_IPRH_RN_I45_RESETVAL (0x00000000U)
  8480. #define CSL_EVETPCC_IPRH_RN_I45_MAX (0x00000001U)
  8481. #define CSL_EVETPCC_IPRH_RN_I57_MASK (0x02000000U)
  8482. #define CSL_EVETPCC_IPRH_RN_I57_SHIFT (25U)
  8483. #define CSL_EVETPCC_IPRH_RN_I57_RESETVAL (0x00000000U)
  8484. #define CSL_EVETPCC_IPRH_RN_I57_MAX (0x00000001U)
  8485. #define CSL_EVETPCC_IPRH_RN_I44_MASK (0x00001000U)
  8486. #define CSL_EVETPCC_IPRH_RN_I44_SHIFT (12U)
  8487. #define CSL_EVETPCC_IPRH_RN_I44_RESETVAL (0x00000000U)
  8488. #define CSL_EVETPCC_IPRH_RN_I44_MAX (0x00000001U)
  8489. #define CSL_EVETPCC_IPRH_RN_I56_MASK (0x01000000U)
  8490. #define CSL_EVETPCC_IPRH_RN_I56_SHIFT (24U)
  8491. #define CSL_EVETPCC_IPRH_RN_I56_RESETVAL (0x00000000U)
  8492. #define CSL_EVETPCC_IPRH_RN_I56_MAX (0x00000001U)
  8493. #define CSL_EVETPCC_IPRH_RN_I63_MASK (0x80000000U)
  8494. #define CSL_EVETPCC_IPRH_RN_I63_SHIFT (31U)
  8495. #define CSL_EVETPCC_IPRH_RN_I63_RESETVAL (0x00000000U)
  8496. #define CSL_EVETPCC_IPRH_RN_I63_MAX (0x00000001U)
  8497. #define CSL_EVETPCC_IPRH_RN_I43_MASK (0x00000800U)
  8498. #define CSL_EVETPCC_IPRH_RN_I43_SHIFT (11U)
  8499. #define CSL_EVETPCC_IPRH_RN_I43_RESETVAL (0x00000000U)
  8500. #define CSL_EVETPCC_IPRH_RN_I43_MAX (0x00000001U)
  8501. #define CSL_EVETPCC_IPRH_RN_I55_MASK (0x00800000U)
  8502. #define CSL_EVETPCC_IPRH_RN_I55_SHIFT (23U)
  8503. #define CSL_EVETPCC_IPRH_RN_I55_RESETVAL (0x00000000U)
  8504. #define CSL_EVETPCC_IPRH_RN_I55_MAX (0x00000001U)
  8505. #define CSL_EVETPCC_IPRH_RN_I62_MASK (0x40000000U)
  8506. #define CSL_EVETPCC_IPRH_RN_I62_SHIFT (30U)
  8507. #define CSL_EVETPCC_IPRH_RN_I62_RESETVAL (0x00000000U)
  8508. #define CSL_EVETPCC_IPRH_RN_I62_MAX (0x00000001U)
  8509. #define CSL_EVETPCC_IPRH_RN_I42_MASK (0x00000400U)
  8510. #define CSL_EVETPCC_IPRH_RN_I42_SHIFT (10U)
  8511. #define CSL_EVETPCC_IPRH_RN_I42_RESETVAL (0x00000000U)
  8512. #define CSL_EVETPCC_IPRH_RN_I42_MAX (0x00000001U)
  8513. #define CSL_EVETPCC_IPRH_RN_I54_MASK (0x00400000U)
  8514. #define CSL_EVETPCC_IPRH_RN_I54_SHIFT (22U)
  8515. #define CSL_EVETPCC_IPRH_RN_I54_RESETVAL (0x00000000U)
  8516. #define CSL_EVETPCC_IPRH_RN_I54_MAX (0x00000001U)
  8517. #define CSL_EVETPCC_IPRH_RN_RESETVAL (0x00000000U)
  8518. /* CER_RN */
  8519. #define CSL_EVETPCC_CER_RN_E6_MASK (0x00000040U)
  8520. #define CSL_EVETPCC_CER_RN_E6_SHIFT (6U)
  8521. #define CSL_EVETPCC_CER_RN_E6_RESETVAL (0x00000000U)
  8522. #define CSL_EVETPCC_CER_RN_E6_MAX (0x00000001U)
  8523. #define CSL_EVETPCC_CER_RN_E25_MASK (0x02000000U)
  8524. #define CSL_EVETPCC_CER_RN_E25_SHIFT (25U)
  8525. #define CSL_EVETPCC_CER_RN_E25_RESETVAL (0x00000000U)
  8526. #define CSL_EVETPCC_CER_RN_E25_MAX (0x00000001U)
  8527. #define CSL_EVETPCC_CER_RN_E18_MASK (0x00040000U)
  8528. #define CSL_EVETPCC_CER_RN_E18_SHIFT (18U)
  8529. #define CSL_EVETPCC_CER_RN_E18_RESETVAL (0x00000000U)
  8530. #define CSL_EVETPCC_CER_RN_E18_MAX (0x00000001U)
  8531. #define CSL_EVETPCC_CER_RN_E7_MASK (0x00000080U)
  8532. #define CSL_EVETPCC_CER_RN_E7_SHIFT (7U)
  8533. #define CSL_EVETPCC_CER_RN_E7_RESETVAL (0x00000000U)
  8534. #define CSL_EVETPCC_CER_RN_E7_MAX (0x00000001U)
  8535. #define CSL_EVETPCC_CER_RN_E24_MASK (0x01000000U)
  8536. #define CSL_EVETPCC_CER_RN_E24_SHIFT (24U)
  8537. #define CSL_EVETPCC_CER_RN_E24_RESETVAL (0x00000000U)
  8538. #define CSL_EVETPCC_CER_RN_E24_MAX (0x00000001U)
  8539. #define CSL_EVETPCC_CER_RN_E31_MASK (0x80000000U)
  8540. #define CSL_EVETPCC_CER_RN_E31_SHIFT (31U)
  8541. #define CSL_EVETPCC_CER_RN_E31_RESETVAL (0x00000000U)
  8542. #define CSL_EVETPCC_CER_RN_E31_MAX (0x00000001U)
  8543. #define CSL_EVETPCC_CER_RN_E8_MASK (0x00000100U)
  8544. #define CSL_EVETPCC_CER_RN_E8_SHIFT (8U)
  8545. #define CSL_EVETPCC_CER_RN_E8_RESETVAL (0x00000000U)
  8546. #define CSL_EVETPCC_CER_RN_E8_MAX (0x00000001U)
  8547. #define CSL_EVETPCC_CER_RN_E26_MASK (0x04000000U)
  8548. #define CSL_EVETPCC_CER_RN_E26_SHIFT (26U)
  8549. #define CSL_EVETPCC_CER_RN_E26_RESETVAL (0x00000000U)
  8550. #define CSL_EVETPCC_CER_RN_E26_MAX (0x00000001U)
  8551. #define CSL_EVETPCC_CER_RN_E29_MASK (0x20000000U)
  8552. #define CSL_EVETPCC_CER_RN_E29_SHIFT (29U)
  8553. #define CSL_EVETPCC_CER_RN_E29_RESETVAL (0x00000000U)
  8554. #define CSL_EVETPCC_CER_RN_E29_MAX (0x00000001U)
  8555. #define CSL_EVETPCC_CER_RN_E9_MASK (0x00000200U)
  8556. #define CSL_EVETPCC_CER_RN_E9_SHIFT (9U)
  8557. #define CSL_EVETPCC_CER_RN_E9_RESETVAL (0x00000000U)
  8558. #define CSL_EVETPCC_CER_RN_E9_MAX (0x00000001U)
  8559. #define CSL_EVETPCC_CER_RN_E30_MASK (0x40000000U)
  8560. #define CSL_EVETPCC_CER_RN_E30_SHIFT (30U)
  8561. #define CSL_EVETPCC_CER_RN_E30_RESETVAL (0x00000000U)
  8562. #define CSL_EVETPCC_CER_RN_E30_MAX (0x00000001U)
  8563. #define CSL_EVETPCC_CER_RN_E10_MASK (0x00000400U)
  8564. #define CSL_EVETPCC_CER_RN_E10_SHIFT (10U)
  8565. #define CSL_EVETPCC_CER_RN_E10_RESETVAL (0x00000000U)
  8566. #define CSL_EVETPCC_CER_RN_E10_MAX (0x00000001U)
  8567. #define CSL_EVETPCC_CER_RN_E28_MASK (0x10000000U)
  8568. #define CSL_EVETPCC_CER_RN_E28_SHIFT (28U)
  8569. #define CSL_EVETPCC_CER_RN_E28_RESETVAL (0x00000000U)
  8570. #define CSL_EVETPCC_CER_RN_E28_MAX (0x00000001U)
  8571. #define CSL_EVETPCC_CER_RN_E11_MASK (0x00000800U)
  8572. #define CSL_EVETPCC_CER_RN_E11_SHIFT (11U)
  8573. #define CSL_EVETPCC_CER_RN_E11_RESETVAL (0x00000000U)
  8574. #define CSL_EVETPCC_CER_RN_E11_MAX (0x00000001U)
  8575. #define CSL_EVETPCC_CER_RN_E27_MASK (0x08000000U)
  8576. #define CSL_EVETPCC_CER_RN_E27_SHIFT (27U)
  8577. #define CSL_EVETPCC_CER_RN_E27_RESETVAL (0x00000000U)
  8578. #define CSL_EVETPCC_CER_RN_E27_MAX (0x00000001U)
  8579. #define CSL_EVETPCC_CER_RN_E0_MASK (0x00000001U)
  8580. #define CSL_EVETPCC_CER_RN_E0_SHIFT (0U)
  8581. #define CSL_EVETPCC_CER_RN_E0_RESETVAL (0x00000000U)
  8582. #define CSL_EVETPCC_CER_RN_E0_MAX (0x00000001U)
  8583. #define CSL_EVETPCC_CER_RN_E12_MASK (0x00001000U)
  8584. #define CSL_EVETPCC_CER_RN_E12_SHIFT (12U)
  8585. #define CSL_EVETPCC_CER_RN_E12_RESETVAL (0x00000000U)
  8586. #define CSL_EVETPCC_CER_RN_E12_MAX (0x00000001U)
  8587. #define CSL_EVETPCC_CER_RN_E1_MASK (0x00000002U)
  8588. #define CSL_EVETPCC_CER_RN_E1_SHIFT (1U)
  8589. #define CSL_EVETPCC_CER_RN_E1_RESETVAL (0x00000000U)
  8590. #define CSL_EVETPCC_CER_RN_E1_MAX (0x00000001U)
  8591. #define CSL_EVETPCC_CER_RN_E13_MASK (0x00002000U)
  8592. #define CSL_EVETPCC_CER_RN_E13_SHIFT (13U)
  8593. #define CSL_EVETPCC_CER_RN_E13_RESETVAL (0x00000000U)
  8594. #define CSL_EVETPCC_CER_RN_E13_MAX (0x00000001U)
  8595. #define CSL_EVETPCC_CER_RN_E19_MASK (0x00080000U)
  8596. #define CSL_EVETPCC_CER_RN_E19_SHIFT (19U)
  8597. #define CSL_EVETPCC_CER_RN_E19_RESETVAL (0x00000000U)
  8598. #define CSL_EVETPCC_CER_RN_E19_MAX (0x00000001U)
  8599. #define CSL_EVETPCC_CER_RN_E2_MASK (0x00000004U)
  8600. #define CSL_EVETPCC_CER_RN_E2_SHIFT (2U)
  8601. #define CSL_EVETPCC_CER_RN_E2_RESETVAL (0x00000000U)
  8602. #define CSL_EVETPCC_CER_RN_E2_MAX (0x00000001U)
  8603. #define CSL_EVETPCC_CER_RN_E14_MASK (0x00004000U)
  8604. #define CSL_EVETPCC_CER_RN_E14_SHIFT (14U)
  8605. #define CSL_EVETPCC_CER_RN_E14_RESETVAL (0x00000000U)
  8606. #define CSL_EVETPCC_CER_RN_E14_MAX (0x00000001U)
  8607. #define CSL_EVETPCC_CER_RN_E3_MASK (0x00000008U)
  8608. #define CSL_EVETPCC_CER_RN_E3_SHIFT (3U)
  8609. #define CSL_EVETPCC_CER_RN_E3_RESETVAL (0x00000000U)
  8610. #define CSL_EVETPCC_CER_RN_E3_MAX (0x00000001U)
  8611. #define CSL_EVETPCC_CER_RN_E15_MASK (0x00008000U)
  8612. #define CSL_EVETPCC_CER_RN_E15_SHIFT (15U)
  8613. #define CSL_EVETPCC_CER_RN_E15_RESETVAL (0x00000000U)
  8614. #define CSL_EVETPCC_CER_RN_E15_MAX (0x00000001U)
  8615. #define CSL_EVETPCC_CER_RN_E21_MASK (0x00200000U)
  8616. #define CSL_EVETPCC_CER_RN_E21_SHIFT (21U)
  8617. #define CSL_EVETPCC_CER_RN_E21_RESETVAL (0x00000000U)
  8618. #define CSL_EVETPCC_CER_RN_E21_MAX (0x00000001U)
  8619. #define CSL_EVETPCC_CER_RN_E20_MASK (0x00100000U)
  8620. #define CSL_EVETPCC_CER_RN_E20_SHIFT (20U)
  8621. #define CSL_EVETPCC_CER_RN_E20_RESETVAL (0x00000000U)
  8622. #define CSL_EVETPCC_CER_RN_E20_MAX (0x00000001U)
  8623. #define CSL_EVETPCC_CER_RN_E4_MASK (0x00000010U)
  8624. #define CSL_EVETPCC_CER_RN_E4_SHIFT (4U)
  8625. #define CSL_EVETPCC_CER_RN_E4_RESETVAL (0x00000000U)
  8626. #define CSL_EVETPCC_CER_RN_E4_MAX (0x00000001U)
  8627. #define CSL_EVETPCC_CER_RN_E23_MASK (0x00800000U)
  8628. #define CSL_EVETPCC_CER_RN_E23_SHIFT (23U)
  8629. #define CSL_EVETPCC_CER_RN_E23_RESETVAL (0x00000000U)
  8630. #define CSL_EVETPCC_CER_RN_E23_MAX (0x00000001U)
  8631. #define CSL_EVETPCC_CER_RN_E16_MASK (0x00010000U)
  8632. #define CSL_EVETPCC_CER_RN_E16_SHIFT (16U)
  8633. #define CSL_EVETPCC_CER_RN_E16_RESETVAL (0x00000000U)
  8634. #define CSL_EVETPCC_CER_RN_E16_MAX (0x00000001U)
  8635. #define CSL_EVETPCC_CER_RN_E5_MASK (0x00000020U)
  8636. #define CSL_EVETPCC_CER_RN_E5_SHIFT (5U)
  8637. #define CSL_EVETPCC_CER_RN_E5_RESETVAL (0x00000000U)
  8638. #define CSL_EVETPCC_CER_RN_E5_MAX (0x00000001U)
  8639. #define CSL_EVETPCC_CER_RN_E22_MASK (0x00400000U)
  8640. #define CSL_EVETPCC_CER_RN_E22_SHIFT (22U)
  8641. #define CSL_EVETPCC_CER_RN_E22_RESETVAL (0x00000000U)
  8642. #define CSL_EVETPCC_CER_RN_E22_MAX (0x00000001U)
  8643. #define CSL_EVETPCC_CER_RN_E17_MASK (0x00020000U)
  8644. #define CSL_EVETPCC_CER_RN_E17_SHIFT (17U)
  8645. #define CSL_EVETPCC_CER_RN_E17_RESETVAL (0x00000000U)
  8646. #define CSL_EVETPCC_CER_RN_E17_MAX (0x00000001U)
  8647. #define CSL_EVETPCC_CER_RN_RESETVAL (0x00000000U)
  8648. /* IECRH_RN */
  8649. #define CSL_EVETPCC_IECRH_RN_I35_MASK (0x00000008U)
  8650. #define CSL_EVETPCC_IECRH_RN_I35_SHIFT (3U)
  8651. #define CSL_EVETPCC_IECRH_RN_I35_RESETVAL (0x00000000U)
  8652. #define CSL_EVETPCC_IECRH_RN_I35_MAX (0x00000001U)
  8653. #define CSL_EVETPCC_IECRH_RN_I48_MASK (0x00010000U)
  8654. #define CSL_EVETPCC_IECRH_RN_I48_SHIFT (16U)
  8655. #define CSL_EVETPCC_IECRH_RN_I48_RESETVAL (0x00000000U)
  8656. #define CSL_EVETPCC_IECRH_RN_I48_MAX (0x00000001U)
  8657. #define CSL_EVETPCC_IECRH_RN_I56_MASK (0x01000000U)
  8658. #define CSL_EVETPCC_IECRH_RN_I56_SHIFT (24U)
  8659. #define CSL_EVETPCC_IECRH_RN_I56_RESETVAL (0x00000000U)
  8660. #define CSL_EVETPCC_IECRH_RN_I56_MAX (0x00000001U)
  8661. #define CSL_EVETPCC_IECRH_RN_I34_MASK (0x00000004U)
  8662. #define CSL_EVETPCC_IECRH_RN_I34_SHIFT (2U)
  8663. #define CSL_EVETPCC_IECRH_RN_I34_RESETVAL (0x00000000U)
  8664. #define CSL_EVETPCC_IECRH_RN_I34_MAX (0x00000001U)
  8665. #define CSL_EVETPCC_IECRH_RN_I47_MASK (0x00008000U)
  8666. #define CSL_EVETPCC_IECRH_RN_I47_SHIFT (15U)
  8667. #define CSL_EVETPCC_IECRH_RN_I47_RESETVAL (0x00000000U)
  8668. #define CSL_EVETPCC_IECRH_RN_I47_MAX (0x00000001U)
  8669. #define CSL_EVETPCC_IECRH_RN_I46_MASK (0x00004000U)
  8670. #define CSL_EVETPCC_IECRH_RN_I46_SHIFT (14U)
  8671. #define CSL_EVETPCC_IECRH_RN_I46_RESETVAL (0x00000000U)
  8672. #define CSL_EVETPCC_IECRH_RN_I46_MAX (0x00000001U)
  8673. #define CSL_EVETPCC_IECRH_RN_I55_MASK (0x00800000U)
  8674. #define CSL_EVETPCC_IECRH_RN_I55_SHIFT (23U)
  8675. #define CSL_EVETPCC_IECRH_RN_I55_RESETVAL (0x00000000U)
  8676. #define CSL_EVETPCC_IECRH_RN_I55_MAX (0x00000001U)
  8677. #define CSL_EVETPCC_IECRH_RN_I45_MASK (0x00002000U)
  8678. #define CSL_EVETPCC_IECRH_RN_I45_SHIFT (13U)
  8679. #define CSL_EVETPCC_IECRH_RN_I45_RESETVAL (0x00000000U)
  8680. #define CSL_EVETPCC_IECRH_RN_I45_MAX (0x00000001U)
  8681. #define CSL_EVETPCC_IECRH_RN_I58_MASK (0x04000000U)
  8682. #define CSL_EVETPCC_IECRH_RN_I58_SHIFT (26U)
  8683. #define CSL_EVETPCC_IECRH_RN_I58_RESETVAL (0x00000000U)
  8684. #define CSL_EVETPCC_IECRH_RN_I58_MAX (0x00000001U)
  8685. #define CSL_EVETPCC_IECRH_RN_I32_MASK (0x00000001U)
  8686. #define CSL_EVETPCC_IECRH_RN_I32_SHIFT (0U)
  8687. #define CSL_EVETPCC_IECRH_RN_I32_RESETVAL (0x00000000U)
  8688. #define CSL_EVETPCC_IECRH_RN_I32_MAX (0x00000001U)
  8689. #define CSL_EVETPCC_IECRH_RN_I44_MASK (0x00001000U)
  8690. #define CSL_EVETPCC_IECRH_RN_I44_SHIFT (12U)
  8691. #define CSL_EVETPCC_IECRH_RN_I44_RESETVAL (0x00000000U)
  8692. #define CSL_EVETPCC_IECRH_RN_I44_MAX (0x00000001U)
  8693. #define CSL_EVETPCC_IECRH_RN_I33_MASK (0x00000002U)
  8694. #define CSL_EVETPCC_IECRH_RN_I33_SHIFT (1U)
  8695. #define CSL_EVETPCC_IECRH_RN_I33_RESETVAL (0x00000000U)
  8696. #define CSL_EVETPCC_IECRH_RN_I33_MAX (0x00000001U)
  8697. #define CSL_EVETPCC_IECRH_RN_I57_MASK (0x02000000U)
  8698. #define CSL_EVETPCC_IECRH_RN_I57_SHIFT (25U)
  8699. #define CSL_EVETPCC_IECRH_RN_I57_RESETVAL (0x00000000U)
  8700. #define CSL_EVETPCC_IECRH_RN_I57_MAX (0x00000001U)
  8701. #define CSL_EVETPCC_IECRH_RN_I43_MASK (0x00000800U)
  8702. #define CSL_EVETPCC_IECRH_RN_I43_SHIFT (11U)
  8703. #define CSL_EVETPCC_IECRH_RN_I43_RESETVAL (0x00000000U)
  8704. #define CSL_EVETPCC_IECRH_RN_I43_MAX (0x00000001U)
  8705. #define CSL_EVETPCC_IECRH_RN_I60_MASK (0x10000000U)
  8706. #define CSL_EVETPCC_IECRH_RN_I60_SHIFT (28U)
  8707. #define CSL_EVETPCC_IECRH_RN_I60_RESETVAL (0x00000000U)
  8708. #define CSL_EVETPCC_IECRH_RN_I60_MAX (0x00000001U)
  8709. #define CSL_EVETPCC_IECRH_RN_I42_MASK (0x00000400U)
  8710. #define CSL_EVETPCC_IECRH_RN_I42_SHIFT (10U)
  8711. #define CSL_EVETPCC_IECRH_RN_I42_RESETVAL (0x00000000U)
  8712. #define CSL_EVETPCC_IECRH_RN_I42_MAX (0x00000001U)
  8713. #define CSL_EVETPCC_IECRH_RN_I59_MASK (0x08000000U)
  8714. #define CSL_EVETPCC_IECRH_RN_I59_SHIFT (27U)
  8715. #define CSL_EVETPCC_IECRH_RN_I59_RESETVAL (0x00000000U)
  8716. #define CSL_EVETPCC_IECRH_RN_I59_MAX (0x00000001U)
  8717. #define CSL_EVETPCC_IECRH_RN_I41_MASK (0x00000200U)
  8718. #define CSL_EVETPCC_IECRH_RN_I41_SHIFT (9U)
  8719. #define CSL_EVETPCC_IECRH_RN_I41_RESETVAL (0x00000000U)
  8720. #define CSL_EVETPCC_IECRH_RN_I41_MAX (0x00000001U)
  8721. #define CSL_EVETPCC_IECRH_RN_I62_MASK (0x40000000U)
  8722. #define CSL_EVETPCC_IECRH_RN_I62_SHIFT (30U)
  8723. #define CSL_EVETPCC_IECRH_RN_I62_RESETVAL (0x00000000U)
  8724. #define CSL_EVETPCC_IECRH_RN_I62_MAX (0x00000001U)
  8725. #define CSL_EVETPCC_IECRH_RN_I61_MASK (0x20000000U)
  8726. #define CSL_EVETPCC_IECRH_RN_I61_SHIFT (29U)
  8727. #define CSL_EVETPCC_IECRH_RN_I61_RESETVAL (0x00000000U)
  8728. #define CSL_EVETPCC_IECRH_RN_I61_MAX (0x00000001U)
  8729. #define CSL_EVETPCC_IECRH_RN_I52_MASK (0x00100000U)
  8730. #define CSL_EVETPCC_IECRH_RN_I52_SHIFT (20U)
  8731. #define CSL_EVETPCC_IECRH_RN_I52_RESETVAL (0x00000000U)
  8732. #define CSL_EVETPCC_IECRH_RN_I52_MAX (0x00000001U)
  8733. #define CSL_EVETPCC_IECRH_RN_I38_MASK (0x00000040U)
  8734. #define CSL_EVETPCC_IECRH_RN_I38_SHIFT (6U)
  8735. #define CSL_EVETPCC_IECRH_RN_I38_RESETVAL (0x00000000U)
  8736. #define CSL_EVETPCC_IECRH_RN_I38_MAX (0x00000001U)
  8737. #define CSL_EVETPCC_IECRH_RN_I40_MASK (0x00000100U)
  8738. #define CSL_EVETPCC_IECRH_RN_I40_SHIFT (8U)
  8739. #define CSL_EVETPCC_IECRH_RN_I40_RESETVAL (0x00000000U)
  8740. #define CSL_EVETPCC_IECRH_RN_I40_MAX (0x00000001U)
  8741. #define CSL_EVETPCC_IECRH_RN_I51_MASK (0x00080000U)
  8742. #define CSL_EVETPCC_IECRH_RN_I51_SHIFT (19U)
  8743. #define CSL_EVETPCC_IECRH_RN_I51_RESETVAL (0x00000000U)
  8744. #define CSL_EVETPCC_IECRH_RN_I51_MAX (0x00000001U)
  8745. #define CSL_EVETPCC_IECRH_RN_I50_MASK (0x00040000U)
  8746. #define CSL_EVETPCC_IECRH_RN_I50_SHIFT (18U)
  8747. #define CSL_EVETPCC_IECRH_RN_I50_RESETVAL (0x00000000U)
  8748. #define CSL_EVETPCC_IECRH_RN_I50_MAX (0x00000001U)
  8749. #define CSL_EVETPCC_IECRH_RN_I63_MASK (0x80000000U)
  8750. #define CSL_EVETPCC_IECRH_RN_I63_SHIFT (31U)
  8751. #define CSL_EVETPCC_IECRH_RN_I63_RESETVAL (0x00000000U)
  8752. #define CSL_EVETPCC_IECRH_RN_I63_MAX (0x00000001U)
  8753. #define CSL_EVETPCC_IECRH_RN_I39_MASK (0x00000080U)
  8754. #define CSL_EVETPCC_IECRH_RN_I39_SHIFT (7U)
  8755. #define CSL_EVETPCC_IECRH_RN_I39_RESETVAL (0x00000000U)
  8756. #define CSL_EVETPCC_IECRH_RN_I39_MAX (0x00000001U)
  8757. #define CSL_EVETPCC_IECRH_RN_I54_MASK (0x00400000U)
  8758. #define CSL_EVETPCC_IECRH_RN_I54_SHIFT (22U)
  8759. #define CSL_EVETPCC_IECRH_RN_I54_RESETVAL (0x00000000U)
  8760. #define CSL_EVETPCC_IECRH_RN_I54_MAX (0x00000001U)
  8761. #define CSL_EVETPCC_IECRH_RN_I36_MASK (0x00000010U)
  8762. #define CSL_EVETPCC_IECRH_RN_I36_SHIFT (4U)
  8763. #define CSL_EVETPCC_IECRH_RN_I36_RESETVAL (0x00000000U)
  8764. #define CSL_EVETPCC_IECRH_RN_I36_MAX (0x00000001U)
  8765. #define CSL_EVETPCC_IECRH_RN_I53_MASK (0x00200000U)
  8766. #define CSL_EVETPCC_IECRH_RN_I53_SHIFT (21U)
  8767. #define CSL_EVETPCC_IECRH_RN_I53_RESETVAL (0x00000000U)
  8768. #define CSL_EVETPCC_IECRH_RN_I53_MAX (0x00000001U)
  8769. #define CSL_EVETPCC_IECRH_RN_I49_MASK (0x00020000U)
  8770. #define CSL_EVETPCC_IECRH_RN_I49_SHIFT (17U)
  8771. #define CSL_EVETPCC_IECRH_RN_I49_RESETVAL (0x00000000U)
  8772. #define CSL_EVETPCC_IECRH_RN_I49_MAX (0x00000001U)
  8773. #define CSL_EVETPCC_IECRH_RN_I37_MASK (0x00000020U)
  8774. #define CSL_EVETPCC_IECRH_RN_I37_SHIFT (5U)
  8775. #define CSL_EVETPCC_IECRH_RN_I37_RESETVAL (0x00000000U)
  8776. #define CSL_EVETPCC_IECRH_RN_I37_MAX (0x00000001U)
  8777. #define CSL_EVETPCC_IECRH_RN_RESETVAL (0x00000000U)
  8778. /* IECR_RN */
  8779. #define CSL_EVETPCC_IECR_RN_I27_MASK (0x08000000U)
  8780. #define CSL_EVETPCC_IECR_RN_I27_SHIFT (27U)
  8781. #define CSL_EVETPCC_IECR_RN_I27_RESETVAL (0x00000000U)
  8782. #define CSL_EVETPCC_IECR_RN_I27_MAX (0x00000001U)
  8783. #define CSL_EVETPCC_IECR_RN_I28_MASK (0x10000000U)
  8784. #define CSL_EVETPCC_IECR_RN_I28_SHIFT (28U)
  8785. #define CSL_EVETPCC_IECR_RN_I28_RESETVAL (0x00000000U)
  8786. #define CSL_EVETPCC_IECR_RN_I28_MAX (0x00000001U)
  8787. #define CSL_EVETPCC_IECR_RN_I25_MASK (0x02000000U)
  8788. #define CSL_EVETPCC_IECR_RN_I25_SHIFT (25U)
  8789. #define CSL_EVETPCC_IECR_RN_I25_RESETVAL (0x00000000U)
  8790. #define CSL_EVETPCC_IECR_RN_I25_MAX (0x00000001U)
  8791. #define CSL_EVETPCC_IECR_RN_I16_MASK (0x00010000U)
  8792. #define CSL_EVETPCC_IECR_RN_I16_SHIFT (16U)
  8793. #define CSL_EVETPCC_IECR_RN_I16_RESETVAL (0x00000000U)
  8794. #define CSL_EVETPCC_IECR_RN_I16_MAX (0x00000001U)
  8795. #define CSL_EVETPCC_IECR_RN_I26_MASK (0x04000000U)
  8796. #define CSL_EVETPCC_IECR_RN_I26_SHIFT (26U)
  8797. #define CSL_EVETPCC_IECR_RN_I26_RESETVAL (0x00000000U)
  8798. #define CSL_EVETPCC_IECR_RN_I26_MAX (0x00000001U)
  8799. #define CSL_EVETPCC_IECR_RN_I15_MASK (0x00008000U)
  8800. #define CSL_EVETPCC_IECR_RN_I15_SHIFT (15U)
  8801. #define CSL_EVETPCC_IECR_RN_I15_RESETVAL (0x00000000U)
  8802. #define CSL_EVETPCC_IECR_RN_I15_MAX (0x00000001U)
  8803. #define CSL_EVETPCC_IECR_RN_I14_MASK (0x00004000U)
  8804. #define CSL_EVETPCC_IECR_RN_I14_SHIFT (14U)
  8805. #define CSL_EVETPCC_IECR_RN_I14_RESETVAL (0x00000000U)
  8806. #define CSL_EVETPCC_IECR_RN_I14_MAX (0x00000001U)
  8807. #define CSL_EVETPCC_IECR_RN_I13_MASK (0x00002000U)
  8808. #define CSL_EVETPCC_IECR_RN_I13_SHIFT (13U)
  8809. #define CSL_EVETPCC_IECR_RN_I13_RESETVAL (0x00000000U)
  8810. #define CSL_EVETPCC_IECR_RN_I13_MAX (0x00000001U)
  8811. #define CSL_EVETPCC_IECR_RN_I0_MASK (0x00000001U)
  8812. #define CSL_EVETPCC_IECR_RN_I0_SHIFT (0U)
  8813. #define CSL_EVETPCC_IECR_RN_I0_RESETVAL (0x00000000U)
  8814. #define CSL_EVETPCC_IECR_RN_I0_MAX (0x00000001U)
  8815. #define CSL_EVETPCC_IECR_RN_I22_MASK (0x00400000U)
  8816. #define CSL_EVETPCC_IECR_RN_I22_SHIFT (22U)
  8817. #define CSL_EVETPCC_IECR_RN_I22_RESETVAL (0x00000000U)
  8818. #define CSL_EVETPCC_IECR_RN_I22_MAX (0x00000001U)
  8819. #define CSL_EVETPCC_IECR_RN_I10_MASK (0x00000400U)
  8820. #define CSL_EVETPCC_IECR_RN_I10_SHIFT (10U)
  8821. #define CSL_EVETPCC_IECR_RN_I10_RESETVAL (0x00000000U)
  8822. #define CSL_EVETPCC_IECR_RN_I10_MAX (0x00000001U)
  8823. #define CSL_EVETPCC_IECR_RN_I21_MASK (0x00200000U)
  8824. #define CSL_EVETPCC_IECR_RN_I21_SHIFT (21U)
  8825. #define CSL_EVETPCC_IECR_RN_I21_RESETVAL (0x00000000U)
  8826. #define CSL_EVETPCC_IECR_RN_I21_MAX (0x00000001U)
  8827. #define CSL_EVETPCC_IECR_RN_I9_MASK (0x00000200U)
  8828. #define CSL_EVETPCC_IECR_RN_I9_SHIFT (9U)
  8829. #define CSL_EVETPCC_IECR_RN_I9_RESETVAL (0x00000000U)
  8830. #define CSL_EVETPCC_IECR_RN_I9_MAX (0x00000001U)
  8831. #define CSL_EVETPCC_IECR_RN_I1_MASK (0x00000002U)
  8832. #define CSL_EVETPCC_IECR_RN_I1_SHIFT (1U)
  8833. #define CSL_EVETPCC_IECR_RN_I1_RESETVAL (0x00000000U)
  8834. #define CSL_EVETPCC_IECR_RN_I1_MAX (0x00000001U)
  8835. #define CSL_EVETPCC_IECR_RN_I24_MASK (0x01000000U)
  8836. #define CSL_EVETPCC_IECR_RN_I24_SHIFT (24U)
  8837. #define CSL_EVETPCC_IECR_RN_I24_RESETVAL (0x00000000U)
  8838. #define CSL_EVETPCC_IECR_RN_I24_MAX (0x00000001U)
  8839. #define CSL_EVETPCC_IECR_RN_I3_MASK (0x00000008U)
  8840. #define CSL_EVETPCC_IECR_RN_I3_SHIFT (3U)
  8841. #define CSL_EVETPCC_IECR_RN_I3_RESETVAL (0x00000000U)
  8842. #define CSL_EVETPCC_IECR_RN_I3_MAX (0x00000001U)
  8843. #define CSL_EVETPCC_IECR_RN_I2_MASK (0x00000004U)
  8844. #define CSL_EVETPCC_IECR_RN_I2_SHIFT (2U)
  8845. #define CSL_EVETPCC_IECR_RN_I2_RESETVAL (0x00000000U)
  8846. #define CSL_EVETPCC_IECR_RN_I2_MAX (0x00000001U)
  8847. #define CSL_EVETPCC_IECR_RN_I12_MASK (0x00001000U)
  8848. #define CSL_EVETPCC_IECR_RN_I12_SHIFT (12U)
  8849. #define CSL_EVETPCC_IECR_RN_I12_RESETVAL (0x00000000U)
  8850. #define CSL_EVETPCC_IECR_RN_I12_MAX (0x00000001U)
  8851. #define CSL_EVETPCC_IECR_RN_I23_MASK (0x00800000U)
  8852. #define CSL_EVETPCC_IECR_RN_I23_SHIFT (23U)
  8853. #define CSL_EVETPCC_IECR_RN_I23_RESETVAL (0x00000000U)
  8854. #define CSL_EVETPCC_IECR_RN_I23_MAX (0x00000001U)
  8855. #define CSL_EVETPCC_IECR_RN_I4_MASK (0x00000010U)
  8856. #define CSL_EVETPCC_IECR_RN_I4_SHIFT (4U)
  8857. #define CSL_EVETPCC_IECR_RN_I4_RESETVAL (0x00000000U)
  8858. #define CSL_EVETPCC_IECR_RN_I4_MAX (0x00000001U)
  8859. #define CSL_EVETPCC_IECR_RN_I11_MASK (0x00000800U)
  8860. #define CSL_EVETPCC_IECR_RN_I11_SHIFT (11U)
  8861. #define CSL_EVETPCC_IECR_RN_I11_RESETVAL (0x00000000U)
  8862. #define CSL_EVETPCC_IECR_RN_I11_MAX (0x00000001U)
  8863. #define CSL_EVETPCC_IECR_RN_I6_MASK (0x00000040U)
  8864. #define CSL_EVETPCC_IECR_RN_I6_SHIFT (6U)
  8865. #define CSL_EVETPCC_IECR_RN_I6_RESETVAL (0x00000000U)
  8866. #define CSL_EVETPCC_IECR_RN_I6_MAX (0x00000001U)
  8867. #define CSL_EVETPCC_IECR_RN_I31_MASK (0x80000000U)
  8868. #define CSL_EVETPCC_IECR_RN_I31_SHIFT (31U)
  8869. #define CSL_EVETPCC_IECR_RN_I31_RESETVAL (0x00000000U)
  8870. #define CSL_EVETPCC_IECR_RN_I31_MAX (0x00000001U)
  8871. #define CSL_EVETPCC_IECR_RN_I18_MASK (0x00040000U)
  8872. #define CSL_EVETPCC_IECR_RN_I18_SHIFT (18U)
  8873. #define CSL_EVETPCC_IECR_RN_I18_RESETVAL (0x00000000U)
  8874. #define CSL_EVETPCC_IECR_RN_I18_MAX (0x00000001U)
  8875. #define CSL_EVETPCC_IECR_RN_I17_MASK (0x00020000U)
  8876. #define CSL_EVETPCC_IECR_RN_I17_SHIFT (17U)
  8877. #define CSL_EVETPCC_IECR_RN_I17_RESETVAL (0x00000000U)
  8878. #define CSL_EVETPCC_IECR_RN_I17_MAX (0x00000001U)
  8879. #define CSL_EVETPCC_IECR_RN_I5_MASK (0x00000020U)
  8880. #define CSL_EVETPCC_IECR_RN_I5_SHIFT (5U)
  8881. #define CSL_EVETPCC_IECR_RN_I5_RESETVAL (0x00000000U)
  8882. #define CSL_EVETPCC_IECR_RN_I5_MAX (0x00000001U)
  8883. #define CSL_EVETPCC_IECR_RN_I20_MASK (0x00100000U)
  8884. #define CSL_EVETPCC_IECR_RN_I20_SHIFT (20U)
  8885. #define CSL_EVETPCC_IECR_RN_I20_RESETVAL (0x00000000U)
  8886. #define CSL_EVETPCC_IECR_RN_I20_MAX (0x00000001U)
  8887. #define CSL_EVETPCC_IECR_RN_I29_MASK (0x20000000U)
  8888. #define CSL_EVETPCC_IECR_RN_I29_SHIFT (29U)
  8889. #define CSL_EVETPCC_IECR_RN_I29_RESETVAL (0x00000000U)
  8890. #define CSL_EVETPCC_IECR_RN_I29_MAX (0x00000001U)
  8891. #define CSL_EVETPCC_IECR_RN_I8_MASK (0x00000100U)
  8892. #define CSL_EVETPCC_IECR_RN_I8_SHIFT (8U)
  8893. #define CSL_EVETPCC_IECR_RN_I8_RESETVAL (0x00000000U)
  8894. #define CSL_EVETPCC_IECR_RN_I8_MAX (0x00000001U)
  8895. #define CSL_EVETPCC_IECR_RN_I19_MASK (0x00080000U)
  8896. #define CSL_EVETPCC_IECR_RN_I19_SHIFT (19U)
  8897. #define CSL_EVETPCC_IECR_RN_I19_RESETVAL (0x00000000U)
  8898. #define CSL_EVETPCC_IECR_RN_I19_MAX (0x00000001U)
  8899. #define CSL_EVETPCC_IECR_RN_I30_MASK (0x40000000U)
  8900. #define CSL_EVETPCC_IECR_RN_I30_SHIFT (30U)
  8901. #define CSL_EVETPCC_IECR_RN_I30_RESETVAL (0x00000000U)
  8902. #define CSL_EVETPCC_IECR_RN_I30_MAX (0x00000001U)
  8903. #define CSL_EVETPCC_IECR_RN_I7_MASK (0x00000080U)
  8904. #define CSL_EVETPCC_IECR_RN_I7_SHIFT (7U)
  8905. #define CSL_EVETPCC_IECR_RN_I7_RESETVAL (0x00000000U)
  8906. #define CSL_EVETPCC_IECR_RN_I7_MAX (0x00000001U)
  8907. #define CSL_EVETPCC_IECR_RN_RESETVAL (0x00000000U)
  8908. /* QSER_RN */
  8909. #define CSL_EVETPCC_QSER_RN_E4_MASK (0x00000010U)
  8910. #define CSL_EVETPCC_QSER_RN_E4_SHIFT (4U)
  8911. #define CSL_EVETPCC_QSER_RN_E4_RESETVAL (0x00000000U)
  8912. #define CSL_EVETPCC_QSER_RN_E4_MAX (0x00000001U)
  8913. #define CSL_EVETPCC_QSER_RN_E3_MASK (0x00000008U)
  8914. #define CSL_EVETPCC_QSER_RN_E3_SHIFT (3U)
  8915. #define CSL_EVETPCC_QSER_RN_E3_RESETVAL (0x00000000U)
  8916. #define CSL_EVETPCC_QSER_RN_E3_MAX (0x00000001U)
  8917. #define CSL_EVETPCC_QSER_RN_E2_MASK (0x00000004U)
  8918. #define CSL_EVETPCC_QSER_RN_E2_SHIFT (2U)
  8919. #define CSL_EVETPCC_QSER_RN_E2_RESETVAL (0x00000000U)
  8920. #define CSL_EVETPCC_QSER_RN_E2_MAX (0x00000001U)
  8921. #define CSL_EVETPCC_QSER_RN_E1_MASK (0x00000002U)
  8922. #define CSL_EVETPCC_QSER_RN_E1_SHIFT (1U)
  8923. #define CSL_EVETPCC_QSER_RN_E1_RESETVAL (0x00000000U)
  8924. #define CSL_EVETPCC_QSER_RN_E1_MAX (0x00000001U)
  8925. #define CSL_EVETPCC_QSER_RN_E0_MASK (0x00000001U)
  8926. #define CSL_EVETPCC_QSER_RN_E0_SHIFT (0U)
  8927. #define CSL_EVETPCC_QSER_RN_E0_RESETVAL (0x00000000U)
  8928. #define CSL_EVETPCC_QSER_RN_E0_MAX (0x00000001U)
  8929. #define CSL_EVETPCC_QSER_RN_E7_MASK (0x00000080U)
  8930. #define CSL_EVETPCC_QSER_RN_E7_SHIFT (7U)
  8931. #define CSL_EVETPCC_QSER_RN_E7_RESETVAL (0x00000000U)
  8932. #define CSL_EVETPCC_QSER_RN_E7_MAX (0x00000001U)
  8933. #define CSL_EVETPCC_QSER_RN_E5_MASK (0x00000020U)
  8934. #define CSL_EVETPCC_QSER_RN_E5_SHIFT (5U)
  8935. #define CSL_EVETPCC_QSER_RN_E5_RESETVAL (0x00000000U)
  8936. #define CSL_EVETPCC_QSER_RN_E5_MAX (0x00000001U)
  8937. #define CSL_EVETPCC_QSER_RN_E6_MASK (0x00000040U)
  8938. #define CSL_EVETPCC_QSER_RN_E6_SHIFT (6U)
  8939. #define CSL_EVETPCC_QSER_RN_E6_RESETVAL (0x00000000U)
  8940. #define CSL_EVETPCC_QSER_RN_E6_MAX (0x00000001U)
  8941. #define CSL_EVETPCC_QSER_RN_RESETVAL (0x00000000U)
  8942. /* IERH_RN */
  8943. #define CSL_EVETPCC_IERH_RN_I48_MASK (0x00010000U)
  8944. #define CSL_EVETPCC_IERH_RN_I48_SHIFT (16U)
  8945. #define CSL_EVETPCC_IERH_RN_I48_RESETVAL (0x00000000U)
  8946. #define CSL_EVETPCC_IERH_RN_I48_MAX (0x00000001U)
  8947. #define CSL_EVETPCC_IERH_RN_I35_MASK (0x00000008U)
  8948. #define CSL_EVETPCC_IERH_RN_I35_SHIFT (3U)
  8949. #define CSL_EVETPCC_IERH_RN_I35_RESETVAL (0x00000000U)
  8950. #define CSL_EVETPCC_IERH_RN_I35_MAX (0x00000001U)
  8951. #define CSL_EVETPCC_IERH_RN_I34_MASK (0x00000004U)
  8952. #define CSL_EVETPCC_IERH_RN_I34_SHIFT (2U)
  8953. #define CSL_EVETPCC_IERH_RN_I34_RESETVAL (0x00000000U)
  8954. #define CSL_EVETPCC_IERH_RN_I34_MAX (0x00000001U)
  8955. #define CSL_EVETPCC_IERH_RN_I46_MASK (0x00004000U)
  8956. #define CSL_EVETPCC_IERH_RN_I46_SHIFT (14U)
  8957. #define CSL_EVETPCC_IERH_RN_I46_RESETVAL (0x00000000U)
  8958. #define CSL_EVETPCC_IERH_RN_I46_MAX (0x00000001U)
  8959. #define CSL_EVETPCC_IERH_RN_I59_MASK (0x08000000U)
  8960. #define CSL_EVETPCC_IERH_RN_I59_SHIFT (27U)
  8961. #define CSL_EVETPCC_IERH_RN_I59_RESETVAL (0x00000000U)
  8962. #define CSL_EVETPCC_IERH_RN_I59_MAX (0x00000001U)
  8963. #define CSL_EVETPCC_IERH_RN_I33_MASK (0x00000002U)
  8964. #define CSL_EVETPCC_IERH_RN_I33_SHIFT (1U)
  8965. #define CSL_EVETPCC_IERH_RN_I33_RESETVAL (0x00000000U)
  8966. #define CSL_EVETPCC_IERH_RN_I33_MAX (0x00000001U)
  8967. #define CSL_EVETPCC_IERH_RN_I45_MASK (0x00002000U)
  8968. #define CSL_EVETPCC_IERH_RN_I45_SHIFT (13U)
  8969. #define CSL_EVETPCC_IERH_RN_I45_RESETVAL (0x00000000U)
  8970. #define CSL_EVETPCC_IERH_RN_I45_MAX (0x00000001U)
  8971. #define CSL_EVETPCC_IERH_RN_I60_MASK (0x10000000U)
  8972. #define CSL_EVETPCC_IERH_RN_I60_SHIFT (28U)
  8973. #define CSL_EVETPCC_IERH_RN_I60_RESETVAL (0x00000000U)
  8974. #define CSL_EVETPCC_IERH_RN_I60_MAX (0x00000001U)
  8975. #define CSL_EVETPCC_IERH_RN_I32_MASK (0x00000001U)
  8976. #define CSL_EVETPCC_IERH_RN_I32_SHIFT (0U)
  8977. #define CSL_EVETPCC_IERH_RN_I32_RESETVAL (0x00000000U)
  8978. #define CSL_EVETPCC_IERH_RN_I32_MAX (0x00000001U)
  8979. #define CSL_EVETPCC_IERH_RN_I44_MASK (0x00001000U)
  8980. #define CSL_EVETPCC_IERH_RN_I44_SHIFT (12U)
  8981. #define CSL_EVETPCC_IERH_RN_I44_RESETVAL (0x00000000U)
  8982. #define CSL_EVETPCC_IERH_RN_I44_MAX (0x00000001U)
  8983. #define CSL_EVETPCC_IERH_RN_I61_MASK (0x20000000U)
  8984. #define CSL_EVETPCC_IERH_RN_I61_SHIFT (29U)
  8985. #define CSL_EVETPCC_IERH_RN_I61_RESETVAL (0x00000000U)
  8986. #define CSL_EVETPCC_IERH_RN_I61_MAX (0x00000001U)
  8987. #define CSL_EVETPCC_IERH_RN_I43_MASK (0x00000800U)
  8988. #define CSL_EVETPCC_IERH_RN_I43_SHIFT (11U)
  8989. #define CSL_EVETPCC_IERH_RN_I43_RESETVAL (0x00000000U)
  8990. #define CSL_EVETPCC_IERH_RN_I43_MAX (0x00000001U)
  8991. #define CSL_EVETPCC_IERH_RN_I49_MASK (0x00020000U)
  8992. #define CSL_EVETPCC_IERH_RN_I49_SHIFT (17U)
  8993. #define CSL_EVETPCC_IERH_RN_I49_RESETVAL (0x00000000U)
  8994. #define CSL_EVETPCC_IERH_RN_I49_MAX (0x00000001U)
  8995. #define CSL_EVETPCC_IERH_RN_I62_MASK (0x40000000U)
  8996. #define CSL_EVETPCC_IERH_RN_I62_SHIFT (30U)
  8997. #define CSL_EVETPCC_IERH_RN_I62_RESETVAL (0x00000000U)
  8998. #define CSL_EVETPCC_IERH_RN_I62_MAX (0x00000001U)
  8999. #define CSL_EVETPCC_IERH_RN_I50_MASK (0x00040000U)
  9000. #define CSL_EVETPCC_IERH_RN_I50_SHIFT (18U)
  9001. #define CSL_EVETPCC_IERH_RN_I50_RESETVAL (0x00000000U)
  9002. #define CSL_EVETPCC_IERH_RN_I50_MAX (0x00000001U)
  9003. #define CSL_EVETPCC_IERH_RN_I42_MASK (0x00000400U)
  9004. #define CSL_EVETPCC_IERH_RN_I42_SHIFT (10U)
  9005. #define CSL_EVETPCC_IERH_RN_I42_RESETVAL (0x00000000U)
  9006. #define CSL_EVETPCC_IERH_RN_I42_MAX (0x00000001U)
  9007. #define CSL_EVETPCC_IERH_RN_I63_MASK (0x80000000U)
  9008. #define CSL_EVETPCC_IERH_RN_I63_SHIFT (31U)
  9009. #define CSL_EVETPCC_IERH_RN_I63_RESETVAL (0x00000000U)
  9010. #define CSL_EVETPCC_IERH_RN_I63_MAX (0x00000001U)
  9011. #define CSL_EVETPCC_IERH_RN_I51_MASK (0x00080000U)
  9012. #define CSL_EVETPCC_IERH_RN_I51_SHIFT (19U)
  9013. #define CSL_EVETPCC_IERH_RN_I51_RESETVAL (0x00000000U)
  9014. #define CSL_EVETPCC_IERH_RN_I51_MAX (0x00000001U)
  9015. #define CSL_EVETPCC_IERH_RN_I41_MASK (0x00000200U)
  9016. #define CSL_EVETPCC_IERH_RN_I41_SHIFT (9U)
  9017. #define CSL_EVETPCC_IERH_RN_I41_RESETVAL (0x00000000U)
  9018. #define CSL_EVETPCC_IERH_RN_I41_MAX (0x00000001U)
  9019. #define CSL_EVETPCC_IERH_RN_I52_MASK (0x00100000U)
  9020. #define CSL_EVETPCC_IERH_RN_I52_SHIFT (20U)
  9021. #define CSL_EVETPCC_IERH_RN_I52_RESETVAL (0x00000000U)
  9022. #define CSL_EVETPCC_IERH_RN_I52_MAX (0x00000001U)
  9023. #define CSL_EVETPCC_IERH_RN_I40_MASK (0x00000100U)
  9024. #define CSL_EVETPCC_IERH_RN_I40_SHIFT (8U)
  9025. #define CSL_EVETPCC_IERH_RN_I40_RESETVAL (0x00000000U)
  9026. #define CSL_EVETPCC_IERH_RN_I40_MAX (0x00000001U)
  9027. #define CSL_EVETPCC_IERH_RN_I53_MASK (0x00200000U)
  9028. #define CSL_EVETPCC_IERH_RN_I53_SHIFT (21U)
  9029. #define CSL_EVETPCC_IERH_RN_I53_RESETVAL (0x00000000U)
  9030. #define CSL_EVETPCC_IERH_RN_I53_MAX (0x00000001U)
  9031. #define CSL_EVETPCC_IERH_RN_I39_MASK (0x00000080U)
  9032. #define CSL_EVETPCC_IERH_RN_I39_SHIFT (7U)
  9033. #define CSL_EVETPCC_IERH_RN_I39_RESETVAL (0x00000000U)
  9034. #define CSL_EVETPCC_IERH_RN_I39_MAX (0x00000001U)
  9035. #define CSL_EVETPCC_IERH_RN_I54_MASK (0x00400000U)
  9036. #define CSL_EVETPCC_IERH_RN_I54_SHIFT (22U)
  9037. #define CSL_EVETPCC_IERH_RN_I54_RESETVAL (0x00000000U)
  9038. #define CSL_EVETPCC_IERH_RN_I54_MAX (0x00000001U)
  9039. #define CSL_EVETPCC_IERH_RN_I55_MASK (0x00800000U)
  9040. #define CSL_EVETPCC_IERH_RN_I55_SHIFT (23U)
  9041. #define CSL_EVETPCC_IERH_RN_I55_RESETVAL (0x00000000U)
  9042. #define CSL_EVETPCC_IERH_RN_I55_MAX (0x00000001U)
  9043. #define CSL_EVETPCC_IERH_RN_I56_MASK (0x01000000U)
  9044. #define CSL_EVETPCC_IERH_RN_I56_SHIFT (24U)
  9045. #define CSL_EVETPCC_IERH_RN_I56_RESETVAL (0x00000000U)
  9046. #define CSL_EVETPCC_IERH_RN_I56_MAX (0x00000001U)
  9047. #define CSL_EVETPCC_IERH_RN_I38_MASK (0x00000040U)
  9048. #define CSL_EVETPCC_IERH_RN_I38_SHIFT (6U)
  9049. #define CSL_EVETPCC_IERH_RN_I38_RESETVAL (0x00000000U)
  9050. #define CSL_EVETPCC_IERH_RN_I38_MAX (0x00000001U)
  9051. #define CSL_EVETPCC_IERH_RN_I57_MASK (0x02000000U)
  9052. #define CSL_EVETPCC_IERH_RN_I57_SHIFT (25U)
  9053. #define CSL_EVETPCC_IERH_RN_I57_RESETVAL (0x00000000U)
  9054. #define CSL_EVETPCC_IERH_RN_I57_MAX (0x00000001U)
  9055. #define CSL_EVETPCC_IERH_RN_I58_MASK (0x04000000U)
  9056. #define CSL_EVETPCC_IERH_RN_I58_SHIFT (26U)
  9057. #define CSL_EVETPCC_IERH_RN_I58_RESETVAL (0x00000000U)
  9058. #define CSL_EVETPCC_IERH_RN_I58_MAX (0x00000001U)
  9059. #define CSL_EVETPCC_IERH_RN_I37_MASK (0x00000020U)
  9060. #define CSL_EVETPCC_IERH_RN_I37_SHIFT (5U)
  9061. #define CSL_EVETPCC_IERH_RN_I37_RESETVAL (0x00000000U)
  9062. #define CSL_EVETPCC_IERH_RN_I37_MAX (0x00000001U)
  9063. #define CSL_EVETPCC_IERH_RN_I47_MASK (0x00008000U)
  9064. #define CSL_EVETPCC_IERH_RN_I47_SHIFT (15U)
  9065. #define CSL_EVETPCC_IERH_RN_I47_RESETVAL (0x00000000U)
  9066. #define CSL_EVETPCC_IERH_RN_I47_MAX (0x00000001U)
  9067. #define CSL_EVETPCC_IERH_RN_I36_MASK (0x00000010U)
  9068. #define CSL_EVETPCC_IERH_RN_I36_SHIFT (4U)
  9069. #define CSL_EVETPCC_IERH_RN_I36_RESETVAL (0x00000000U)
  9070. #define CSL_EVETPCC_IERH_RN_I36_MAX (0x00000001U)
  9071. #define CSL_EVETPCC_IERH_RN_RESETVAL (0x00000000U)
  9072. /* ECR_RN */
  9073. #define CSL_EVETPCC_ECR_RN_E16_MASK (0x00010000U)
  9074. #define CSL_EVETPCC_ECR_RN_E16_SHIFT (16U)
  9075. #define CSL_EVETPCC_ECR_RN_E16_RESETVAL (0x00000000U)
  9076. #define CSL_EVETPCC_ECR_RN_E16_MAX (0x00000001U)
  9077. #define CSL_EVETPCC_ECR_RN_E10_MASK (0x00000400U)
  9078. #define CSL_EVETPCC_ECR_RN_E10_SHIFT (10U)
  9079. #define CSL_EVETPCC_ECR_RN_E10_RESETVAL (0x00000000U)
  9080. #define CSL_EVETPCC_ECR_RN_E10_MAX (0x00000001U)
  9081. #define CSL_EVETPCC_ECR_RN_E30_MASK (0x40000000U)
  9082. #define CSL_EVETPCC_ECR_RN_E30_SHIFT (30U)
  9083. #define CSL_EVETPCC_ECR_RN_E30_RESETVAL (0x00000000U)
  9084. #define CSL_EVETPCC_ECR_RN_E30_MAX (0x00000001U)
  9085. #define CSL_EVETPCC_ECR_RN_E19_MASK (0x00080000U)
  9086. #define CSL_EVETPCC_ECR_RN_E19_SHIFT (19U)
  9087. #define CSL_EVETPCC_ECR_RN_E19_RESETVAL (0x00000000U)
  9088. #define CSL_EVETPCC_ECR_RN_E19_MAX (0x00000001U)
  9089. #define CSL_EVETPCC_ECR_RN_E29_MASK (0x20000000U)
  9090. #define CSL_EVETPCC_ECR_RN_E29_SHIFT (29U)
  9091. #define CSL_EVETPCC_ECR_RN_E29_RESETVAL (0x00000000U)
  9092. #define CSL_EVETPCC_ECR_RN_E29_MAX (0x00000001U)
  9093. #define CSL_EVETPCC_ECR_RN_E12_MASK (0x00001000U)
  9094. #define CSL_EVETPCC_ECR_RN_E12_SHIFT (12U)
  9095. #define CSL_EVETPCC_ECR_RN_E12_RESETVAL (0x00000000U)
  9096. #define CSL_EVETPCC_ECR_RN_E12_MAX (0x00000001U)
  9097. #define CSL_EVETPCC_ECR_RN_E18_MASK (0x00040000U)
  9098. #define CSL_EVETPCC_ECR_RN_E18_SHIFT (18U)
  9099. #define CSL_EVETPCC_ECR_RN_E18_RESETVAL (0x00000000U)
  9100. #define CSL_EVETPCC_ECR_RN_E18_MAX (0x00000001U)
  9101. #define CSL_EVETPCC_ECR_RN_E11_MASK (0x00000800U)
  9102. #define CSL_EVETPCC_ECR_RN_E11_SHIFT (11U)
  9103. #define CSL_EVETPCC_ECR_RN_E11_RESETVAL (0x00000000U)
  9104. #define CSL_EVETPCC_ECR_RN_E11_MAX (0x00000001U)
  9105. #define CSL_EVETPCC_ECR_RN_E21_MASK (0x00200000U)
  9106. #define CSL_EVETPCC_ECR_RN_E21_SHIFT (21U)
  9107. #define CSL_EVETPCC_ECR_RN_E21_RESETVAL (0x00000000U)
  9108. #define CSL_EVETPCC_ECR_RN_E21_MAX (0x00000001U)
  9109. #define CSL_EVETPCC_ECR_RN_E31_MASK (0x80000000U)
  9110. #define CSL_EVETPCC_ECR_RN_E31_SHIFT (31U)
  9111. #define CSL_EVETPCC_ECR_RN_E31_RESETVAL (0x00000000U)
  9112. #define CSL_EVETPCC_ECR_RN_E31_MAX (0x00000001U)
  9113. #define CSL_EVETPCC_ECR_RN_E14_MASK (0x00004000U)
  9114. #define CSL_EVETPCC_ECR_RN_E14_SHIFT (14U)
  9115. #define CSL_EVETPCC_ECR_RN_E14_RESETVAL (0x00000000U)
  9116. #define CSL_EVETPCC_ECR_RN_E14_MAX (0x00000001U)
  9117. #define CSL_EVETPCC_ECR_RN_E26_MASK (0x04000000U)
  9118. #define CSL_EVETPCC_ECR_RN_E26_SHIFT (26U)
  9119. #define CSL_EVETPCC_ECR_RN_E26_RESETVAL (0x00000000U)
  9120. #define CSL_EVETPCC_ECR_RN_E26_MAX (0x00000001U)
  9121. #define CSL_EVETPCC_ECR_RN_E13_MASK (0x00002000U)
  9122. #define CSL_EVETPCC_ECR_RN_E13_SHIFT (13U)
  9123. #define CSL_EVETPCC_ECR_RN_E13_RESETVAL (0x00000000U)
  9124. #define CSL_EVETPCC_ECR_RN_E13_MAX (0x00000001U)
  9125. #define CSL_EVETPCC_ECR_RN_E25_MASK (0x02000000U)
  9126. #define CSL_EVETPCC_ECR_RN_E25_SHIFT (25U)
  9127. #define CSL_EVETPCC_ECR_RN_E25_RESETVAL (0x00000000U)
  9128. #define CSL_EVETPCC_ECR_RN_E25_MAX (0x00000001U)
  9129. #define CSL_EVETPCC_ECR_RN_E15_MASK (0x00008000U)
  9130. #define CSL_EVETPCC_ECR_RN_E15_SHIFT (15U)
  9131. #define CSL_EVETPCC_ECR_RN_E15_RESETVAL (0x00000000U)
  9132. #define CSL_EVETPCC_ECR_RN_E15_MAX (0x00000001U)
  9133. #define CSL_EVETPCC_ECR_RN_E28_MASK (0x10000000U)
  9134. #define CSL_EVETPCC_ECR_RN_E28_SHIFT (28U)
  9135. #define CSL_EVETPCC_ECR_RN_E28_RESETVAL (0x00000000U)
  9136. #define CSL_EVETPCC_ECR_RN_E28_MAX (0x00000001U)
  9137. #define CSL_EVETPCC_ECR_RN_E17_MASK (0x00020000U)
  9138. #define CSL_EVETPCC_ECR_RN_E17_SHIFT (17U)
  9139. #define CSL_EVETPCC_ECR_RN_E17_RESETVAL (0x00000000U)
  9140. #define CSL_EVETPCC_ECR_RN_E17_MAX (0x00000001U)
  9141. #define CSL_EVETPCC_ECR_RN_E27_MASK (0x08000000U)
  9142. #define CSL_EVETPCC_ECR_RN_E27_SHIFT (27U)
  9143. #define CSL_EVETPCC_ECR_RN_E27_RESETVAL (0x00000000U)
  9144. #define CSL_EVETPCC_ECR_RN_E27_MAX (0x00000001U)
  9145. #define CSL_EVETPCC_ECR_RN_E4_MASK (0x00000010U)
  9146. #define CSL_EVETPCC_ECR_RN_E4_SHIFT (4U)
  9147. #define CSL_EVETPCC_ECR_RN_E4_RESETVAL (0x00000000U)
  9148. #define CSL_EVETPCC_ECR_RN_E4_MAX (0x00000001U)
  9149. #define CSL_EVETPCC_ECR_RN_E24_MASK (0x01000000U)
  9150. #define CSL_EVETPCC_ECR_RN_E24_SHIFT (24U)
  9151. #define CSL_EVETPCC_ECR_RN_E24_RESETVAL (0x00000000U)
  9152. #define CSL_EVETPCC_ECR_RN_E24_MAX (0x00000001U)
  9153. #define CSL_EVETPCC_ECR_RN_E2_MASK (0x00000004U)
  9154. #define CSL_EVETPCC_ECR_RN_E2_SHIFT (2U)
  9155. #define CSL_EVETPCC_ECR_RN_E2_RESETVAL (0x00000000U)
  9156. #define CSL_EVETPCC_ECR_RN_E2_MAX (0x00000001U)
  9157. #define CSL_EVETPCC_ECR_RN_E3_MASK (0x00000008U)
  9158. #define CSL_EVETPCC_ECR_RN_E3_SHIFT (3U)
  9159. #define CSL_EVETPCC_ECR_RN_E3_RESETVAL (0x00000000U)
  9160. #define CSL_EVETPCC_ECR_RN_E3_MAX (0x00000001U)
  9161. #define CSL_EVETPCC_ECR_RN_E0_MASK (0x00000001U)
  9162. #define CSL_EVETPCC_ECR_RN_E0_SHIFT (0U)
  9163. #define CSL_EVETPCC_ECR_RN_E0_RESETVAL (0x00000000U)
  9164. #define CSL_EVETPCC_ECR_RN_E0_MAX (0x00000001U)
  9165. #define CSL_EVETPCC_ECR_RN_E20_MASK (0x00100000U)
  9166. #define CSL_EVETPCC_ECR_RN_E20_SHIFT (20U)
  9167. #define CSL_EVETPCC_ECR_RN_E20_RESETVAL (0x00000000U)
  9168. #define CSL_EVETPCC_ECR_RN_E20_MAX (0x00000001U)
  9169. #define CSL_EVETPCC_ECR_RN_E6_MASK (0x00000040U)
  9170. #define CSL_EVETPCC_ECR_RN_E6_SHIFT (6U)
  9171. #define CSL_EVETPCC_ECR_RN_E6_RESETVAL (0x00000000U)
  9172. #define CSL_EVETPCC_ECR_RN_E6_MAX (0x00000001U)
  9173. #define CSL_EVETPCC_ECR_RN_E1_MASK (0x00000002U)
  9174. #define CSL_EVETPCC_ECR_RN_E1_SHIFT (1U)
  9175. #define CSL_EVETPCC_ECR_RN_E1_RESETVAL (0x00000000U)
  9176. #define CSL_EVETPCC_ECR_RN_E1_MAX (0x00000001U)
  9177. #define CSL_EVETPCC_ECR_RN_E5_MASK (0x00000020U)
  9178. #define CSL_EVETPCC_ECR_RN_E5_SHIFT (5U)
  9179. #define CSL_EVETPCC_ECR_RN_E5_RESETVAL (0x00000000U)
  9180. #define CSL_EVETPCC_ECR_RN_E5_MAX (0x00000001U)
  9181. #define CSL_EVETPCC_ECR_RN_E23_MASK (0x00800000U)
  9182. #define CSL_EVETPCC_ECR_RN_E23_SHIFT (23U)
  9183. #define CSL_EVETPCC_ECR_RN_E23_RESETVAL (0x00000000U)
  9184. #define CSL_EVETPCC_ECR_RN_E23_MAX (0x00000001U)
  9185. #define CSL_EVETPCC_ECR_RN_E8_MASK (0x00000100U)
  9186. #define CSL_EVETPCC_ECR_RN_E8_SHIFT (8U)
  9187. #define CSL_EVETPCC_ECR_RN_E8_RESETVAL (0x00000000U)
  9188. #define CSL_EVETPCC_ECR_RN_E8_MAX (0x00000001U)
  9189. #define CSL_EVETPCC_ECR_RN_E9_MASK (0x00000200U)
  9190. #define CSL_EVETPCC_ECR_RN_E9_SHIFT (9U)
  9191. #define CSL_EVETPCC_ECR_RN_E9_RESETVAL (0x00000000U)
  9192. #define CSL_EVETPCC_ECR_RN_E9_MAX (0x00000001U)
  9193. #define CSL_EVETPCC_ECR_RN_E22_MASK (0x00400000U)
  9194. #define CSL_EVETPCC_ECR_RN_E22_SHIFT (22U)
  9195. #define CSL_EVETPCC_ECR_RN_E22_RESETVAL (0x00000000U)
  9196. #define CSL_EVETPCC_ECR_RN_E22_MAX (0x00000001U)
  9197. #define CSL_EVETPCC_ECR_RN_E7_MASK (0x00000080U)
  9198. #define CSL_EVETPCC_ECR_RN_E7_SHIFT (7U)
  9199. #define CSL_EVETPCC_ECR_RN_E7_RESETVAL (0x00000000U)
  9200. #define CSL_EVETPCC_ECR_RN_E7_MAX (0x00000001U)
  9201. #define CSL_EVETPCC_ECR_RN_RESETVAL (0x00000000U)
  9202. /* EERH_RN */
  9203. #define CSL_EVETPCC_EERH_RN_E47_MASK (0x00008000U)
  9204. #define CSL_EVETPCC_EERH_RN_E47_SHIFT (15U)
  9205. #define CSL_EVETPCC_EERH_RN_E47_RESETVAL (0x00000000U)
  9206. #define CSL_EVETPCC_EERH_RN_E47_MAX (0x00000001U)
  9207. #define CSL_EVETPCC_EERH_RN_E45_MASK (0x00002000U)
  9208. #define CSL_EVETPCC_EERH_RN_E45_SHIFT (13U)
  9209. #define CSL_EVETPCC_EERH_RN_E45_RESETVAL (0x00000000U)
  9210. #define CSL_EVETPCC_EERH_RN_E45_MAX (0x00000001U)
  9211. #define CSL_EVETPCC_EERH_RN_E35_MASK (0x00000008U)
  9212. #define CSL_EVETPCC_EERH_RN_E35_SHIFT (3U)
  9213. #define CSL_EVETPCC_EERH_RN_E35_RESETVAL (0x00000000U)
  9214. #define CSL_EVETPCC_EERH_RN_E35_MAX (0x00000001U)
  9215. #define CSL_EVETPCC_EERH_RN_E56_MASK (0x01000000U)
  9216. #define CSL_EVETPCC_EERH_RN_E56_SHIFT (24U)
  9217. #define CSL_EVETPCC_EERH_RN_E56_RESETVAL (0x00000000U)
  9218. #define CSL_EVETPCC_EERH_RN_E56_MAX (0x00000001U)
  9219. #define CSL_EVETPCC_EERH_RN_E46_MASK (0x00004000U)
  9220. #define CSL_EVETPCC_EERH_RN_E46_SHIFT (14U)
  9221. #define CSL_EVETPCC_EERH_RN_E46_RESETVAL (0x00000000U)
  9222. #define CSL_EVETPCC_EERH_RN_E46_MAX (0x00000001U)
  9223. #define CSL_EVETPCC_EERH_RN_E36_MASK (0x00000010U)
  9224. #define CSL_EVETPCC_EERH_RN_E36_SHIFT (4U)
  9225. #define CSL_EVETPCC_EERH_RN_E36_RESETVAL (0x00000000U)
  9226. #define CSL_EVETPCC_EERH_RN_E36_MAX (0x00000001U)
  9227. #define CSL_EVETPCC_EERH_RN_E55_MASK (0x00800000U)
  9228. #define CSL_EVETPCC_EERH_RN_E55_SHIFT (23U)
  9229. #define CSL_EVETPCC_EERH_RN_E55_RESETVAL (0x00000000U)
  9230. #define CSL_EVETPCC_EERH_RN_E55_MAX (0x00000001U)
  9231. #define CSL_EVETPCC_EERH_RN_E33_MASK (0x00000002U)
  9232. #define CSL_EVETPCC_EERH_RN_E33_SHIFT (1U)
  9233. #define CSL_EVETPCC_EERH_RN_E33_RESETVAL (0x00000000U)
  9234. #define CSL_EVETPCC_EERH_RN_E33_MAX (0x00000001U)
  9235. #define CSL_EVETPCC_EERH_RN_E54_MASK (0x00400000U)
  9236. #define CSL_EVETPCC_EERH_RN_E54_SHIFT (22U)
  9237. #define CSL_EVETPCC_EERH_RN_E54_RESETVAL (0x00000000U)
  9238. #define CSL_EVETPCC_EERH_RN_E54_MAX (0x00000001U)
  9239. #define CSL_EVETPCC_EERH_RN_E43_MASK (0x00000800U)
  9240. #define CSL_EVETPCC_EERH_RN_E43_SHIFT (11U)
  9241. #define CSL_EVETPCC_EERH_RN_E43_RESETVAL (0x00000000U)
  9242. #define CSL_EVETPCC_EERH_RN_E43_MAX (0x00000001U)
  9243. #define CSL_EVETPCC_EERH_RN_E53_MASK (0x00200000U)
  9244. #define CSL_EVETPCC_EERH_RN_E53_SHIFT (21U)
  9245. #define CSL_EVETPCC_EERH_RN_E53_RESETVAL (0x00000000U)
  9246. #define CSL_EVETPCC_EERH_RN_E53_MAX (0x00000001U)
  9247. #define CSL_EVETPCC_EERH_RN_E63_MASK (0x80000000U)
  9248. #define CSL_EVETPCC_EERH_RN_E63_SHIFT (31U)
  9249. #define CSL_EVETPCC_EERH_RN_E63_RESETVAL (0x00000000U)
  9250. #define CSL_EVETPCC_EERH_RN_E63_MAX (0x00000001U)
  9251. #define CSL_EVETPCC_EERH_RN_E34_MASK (0x00000004U)
  9252. #define CSL_EVETPCC_EERH_RN_E34_SHIFT (2U)
  9253. #define CSL_EVETPCC_EERH_RN_E34_RESETVAL (0x00000000U)
  9254. #define CSL_EVETPCC_EERH_RN_E34_MAX (0x00000001U)
  9255. #define CSL_EVETPCC_EERH_RN_E44_MASK (0x00001000U)
  9256. #define CSL_EVETPCC_EERH_RN_E44_SHIFT (12U)
  9257. #define CSL_EVETPCC_EERH_RN_E44_RESETVAL (0x00000000U)
  9258. #define CSL_EVETPCC_EERH_RN_E44_MAX (0x00000001U)
  9259. #define CSL_EVETPCC_EERH_RN_E52_MASK (0x00100000U)
  9260. #define CSL_EVETPCC_EERH_RN_E52_SHIFT (20U)
  9261. #define CSL_EVETPCC_EERH_RN_E52_RESETVAL (0x00000000U)
  9262. #define CSL_EVETPCC_EERH_RN_E52_MAX (0x00000001U)
  9263. #define CSL_EVETPCC_EERH_RN_E41_MASK (0x00000200U)
  9264. #define CSL_EVETPCC_EERH_RN_E41_SHIFT (9U)
  9265. #define CSL_EVETPCC_EERH_RN_E41_RESETVAL (0x00000000U)
  9266. #define CSL_EVETPCC_EERH_RN_E41_MAX (0x00000001U)
  9267. #define CSL_EVETPCC_EERH_RN_E62_MASK (0x40000000U)
  9268. #define CSL_EVETPCC_EERH_RN_E62_SHIFT (30U)
  9269. #define CSL_EVETPCC_EERH_RN_E62_RESETVAL (0x00000000U)
  9270. #define CSL_EVETPCC_EERH_RN_E62_MAX (0x00000001U)
  9271. #define CSL_EVETPCC_EERH_RN_E32_MASK (0x00000001U)
  9272. #define CSL_EVETPCC_EERH_RN_E32_SHIFT (0U)
  9273. #define CSL_EVETPCC_EERH_RN_E32_RESETVAL (0x00000000U)
  9274. #define CSL_EVETPCC_EERH_RN_E32_MAX (0x00000001U)
  9275. #define CSL_EVETPCC_EERH_RN_E51_MASK (0x00080000U)
  9276. #define CSL_EVETPCC_EERH_RN_E51_SHIFT (19U)
  9277. #define CSL_EVETPCC_EERH_RN_E51_RESETVAL (0x00000000U)
  9278. #define CSL_EVETPCC_EERH_RN_E51_MAX (0x00000001U)
  9279. #define CSL_EVETPCC_EERH_RN_E42_MASK (0x00000400U)
  9280. #define CSL_EVETPCC_EERH_RN_E42_SHIFT (10U)
  9281. #define CSL_EVETPCC_EERH_RN_E42_RESETVAL (0x00000000U)
  9282. #define CSL_EVETPCC_EERH_RN_E42_MAX (0x00000001U)
  9283. #define CSL_EVETPCC_EERH_RN_E61_MASK (0x20000000U)
  9284. #define CSL_EVETPCC_EERH_RN_E61_SHIFT (29U)
  9285. #define CSL_EVETPCC_EERH_RN_E61_RESETVAL (0x00000000U)
  9286. #define CSL_EVETPCC_EERH_RN_E61_MAX (0x00000001U)
  9287. #define CSL_EVETPCC_EERH_RN_E50_MASK (0x00040000U)
  9288. #define CSL_EVETPCC_EERH_RN_E50_SHIFT (18U)
  9289. #define CSL_EVETPCC_EERH_RN_E50_RESETVAL (0x00000000U)
  9290. #define CSL_EVETPCC_EERH_RN_E50_MAX (0x00000001U)
  9291. #define CSL_EVETPCC_EERH_RN_E39_MASK (0x00000080U)
  9292. #define CSL_EVETPCC_EERH_RN_E39_SHIFT (7U)
  9293. #define CSL_EVETPCC_EERH_RN_E39_RESETVAL (0x00000000U)
  9294. #define CSL_EVETPCC_EERH_RN_E39_MAX (0x00000001U)
  9295. #define CSL_EVETPCC_EERH_RN_E60_MASK (0x10000000U)
  9296. #define CSL_EVETPCC_EERH_RN_E60_SHIFT (28U)
  9297. #define CSL_EVETPCC_EERH_RN_E60_RESETVAL (0x00000000U)
  9298. #define CSL_EVETPCC_EERH_RN_E60_MAX (0x00000001U)
  9299. #define CSL_EVETPCC_EERH_RN_E49_MASK (0x00020000U)
  9300. #define CSL_EVETPCC_EERH_RN_E49_SHIFT (17U)
  9301. #define CSL_EVETPCC_EERH_RN_E49_RESETVAL (0x00000000U)
  9302. #define CSL_EVETPCC_EERH_RN_E49_MAX (0x00000001U)
  9303. #define CSL_EVETPCC_EERH_RN_E40_MASK (0x00000100U)
  9304. #define CSL_EVETPCC_EERH_RN_E40_SHIFT (8U)
  9305. #define CSL_EVETPCC_EERH_RN_E40_RESETVAL (0x00000000U)
  9306. #define CSL_EVETPCC_EERH_RN_E40_MAX (0x00000001U)
  9307. #define CSL_EVETPCC_EERH_RN_E59_MASK (0x08000000U)
  9308. #define CSL_EVETPCC_EERH_RN_E59_SHIFT (27U)
  9309. #define CSL_EVETPCC_EERH_RN_E59_RESETVAL (0x00000000U)
  9310. #define CSL_EVETPCC_EERH_RN_E59_MAX (0x00000001U)
  9311. #define CSL_EVETPCC_EERH_RN_E48_MASK (0x00010000U)
  9312. #define CSL_EVETPCC_EERH_RN_E48_SHIFT (16U)
  9313. #define CSL_EVETPCC_EERH_RN_E48_RESETVAL (0x00000000U)
  9314. #define CSL_EVETPCC_EERH_RN_E48_MAX (0x00000001U)
  9315. #define CSL_EVETPCC_EERH_RN_E58_MASK (0x04000000U)
  9316. #define CSL_EVETPCC_EERH_RN_E58_SHIFT (26U)
  9317. #define CSL_EVETPCC_EERH_RN_E58_RESETVAL (0x00000000U)
  9318. #define CSL_EVETPCC_EERH_RN_E58_MAX (0x00000001U)
  9319. #define CSL_EVETPCC_EERH_RN_E37_MASK (0x00000020U)
  9320. #define CSL_EVETPCC_EERH_RN_E37_SHIFT (5U)
  9321. #define CSL_EVETPCC_EERH_RN_E37_RESETVAL (0x00000000U)
  9322. #define CSL_EVETPCC_EERH_RN_E37_MAX (0x00000001U)
  9323. #define CSL_EVETPCC_EERH_RN_E57_MASK (0x02000000U)
  9324. #define CSL_EVETPCC_EERH_RN_E57_SHIFT (25U)
  9325. #define CSL_EVETPCC_EERH_RN_E57_RESETVAL (0x00000000U)
  9326. #define CSL_EVETPCC_EERH_RN_E57_MAX (0x00000001U)
  9327. #define CSL_EVETPCC_EERH_RN_E38_MASK (0x00000040U)
  9328. #define CSL_EVETPCC_EERH_RN_E38_SHIFT (6U)
  9329. #define CSL_EVETPCC_EERH_RN_E38_RESETVAL (0x00000000U)
  9330. #define CSL_EVETPCC_EERH_RN_E38_MAX (0x00000001U)
  9331. #define CSL_EVETPCC_EERH_RN_RESETVAL (0x00000000U)
  9332. /* IPR_RN */
  9333. #define CSL_EVETPCC_IPR_RN_I15_MASK (0x00008000U)
  9334. #define CSL_EVETPCC_IPR_RN_I15_SHIFT (15U)
  9335. #define CSL_EVETPCC_IPR_RN_I15_RESETVAL (0x00000000U)
  9336. #define CSL_EVETPCC_IPR_RN_I15_MAX (0x00000001U)
  9337. #define CSL_EVETPCC_IPR_RN_I27_MASK (0x08000000U)
  9338. #define CSL_EVETPCC_IPR_RN_I27_SHIFT (27U)
  9339. #define CSL_EVETPCC_IPR_RN_I27_RESETVAL (0x00000000U)
  9340. #define CSL_EVETPCC_IPR_RN_I27_MAX (0x00000001U)
  9341. #define CSL_EVETPCC_IPR_RN_I3_MASK (0x00000008U)
  9342. #define CSL_EVETPCC_IPR_RN_I3_SHIFT (3U)
  9343. #define CSL_EVETPCC_IPR_RN_I3_RESETVAL (0x00000000U)
  9344. #define CSL_EVETPCC_IPR_RN_I3_MAX (0x00000001U)
  9345. #define CSL_EVETPCC_IPR_RN_I14_MASK (0x00004000U)
  9346. #define CSL_EVETPCC_IPR_RN_I14_SHIFT (14U)
  9347. #define CSL_EVETPCC_IPR_RN_I14_RESETVAL (0x00000000U)
  9348. #define CSL_EVETPCC_IPR_RN_I14_MAX (0x00000001U)
  9349. #define CSL_EVETPCC_IPR_RN_I2_MASK (0x00000004U)
  9350. #define CSL_EVETPCC_IPR_RN_I2_SHIFT (2U)
  9351. #define CSL_EVETPCC_IPR_RN_I2_RESETVAL (0x00000000U)
  9352. #define CSL_EVETPCC_IPR_RN_I2_MAX (0x00000001U)
  9353. #define CSL_EVETPCC_IPR_RN_I1_MASK (0x00000002U)
  9354. #define CSL_EVETPCC_IPR_RN_I1_SHIFT (1U)
  9355. #define CSL_EVETPCC_IPR_RN_I1_RESETVAL (0x00000000U)
  9356. #define CSL_EVETPCC_IPR_RN_I1_MAX (0x00000001U)
  9357. #define CSL_EVETPCC_IPR_RN_I13_MASK (0x00002000U)
  9358. #define CSL_EVETPCC_IPR_RN_I13_SHIFT (13U)
  9359. #define CSL_EVETPCC_IPR_RN_I13_RESETVAL (0x00000000U)
  9360. #define CSL_EVETPCC_IPR_RN_I13_MAX (0x00000001U)
  9361. #define CSL_EVETPCC_IPR_RN_I28_MASK (0x10000000U)
  9362. #define CSL_EVETPCC_IPR_RN_I28_SHIFT (28U)
  9363. #define CSL_EVETPCC_IPR_RN_I28_RESETVAL (0x00000000U)
  9364. #define CSL_EVETPCC_IPR_RN_I28_MAX (0x00000001U)
  9365. #define CSL_EVETPCC_IPR_RN_I17_MASK (0x00020000U)
  9366. #define CSL_EVETPCC_IPR_RN_I17_SHIFT (17U)
  9367. #define CSL_EVETPCC_IPR_RN_I17_RESETVAL (0x00000000U)
  9368. #define CSL_EVETPCC_IPR_RN_I17_MAX (0x00000001U)
  9369. #define CSL_EVETPCC_IPR_RN_I0_MASK (0x00000001U)
  9370. #define CSL_EVETPCC_IPR_RN_I0_SHIFT (0U)
  9371. #define CSL_EVETPCC_IPR_RN_I0_RESETVAL (0x00000000U)
  9372. #define CSL_EVETPCC_IPR_RN_I0_MAX (0x00000001U)
  9373. #define CSL_EVETPCC_IPR_RN_I12_MASK (0x00001000U)
  9374. #define CSL_EVETPCC_IPR_RN_I12_SHIFT (12U)
  9375. #define CSL_EVETPCC_IPR_RN_I12_RESETVAL (0x00000000U)
  9376. #define CSL_EVETPCC_IPR_RN_I12_MAX (0x00000001U)
  9377. #define CSL_EVETPCC_IPR_RN_I29_MASK (0x20000000U)
  9378. #define CSL_EVETPCC_IPR_RN_I29_SHIFT (29U)
  9379. #define CSL_EVETPCC_IPR_RN_I29_RESETVAL (0x00000000U)
  9380. #define CSL_EVETPCC_IPR_RN_I29_MAX (0x00000001U)
  9381. #define CSL_EVETPCC_IPR_RN_I6_MASK (0x00000040U)
  9382. #define CSL_EVETPCC_IPR_RN_I6_SHIFT (6U)
  9383. #define CSL_EVETPCC_IPR_RN_I6_RESETVAL (0x00000000U)
  9384. #define CSL_EVETPCC_IPR_RN_I6_MAX (0x00000001U)
  9385. #define CSL_EVETPCC_IPR_RN_I26_MASK (0x04000000U)
  9386. #define CSL_EVETPCC_IPR_RN_I26_SHIFT (26U)
  9387. #define CSL_EVETPCC_IPR_RN_I26_RESETVAL (0x00000000U)
  9388. #define CSL_EVETPCC_IPR_RN_I26_MAX (0x00000001U)
  9389. #define CSL_EVETPCC_IPR_RN_I5_MASK (0x00000020U)
  9390. #define CSL_EVETPCC_IPR_RN_I5_SHIFT (5U)
  9391. #define CSL_EVETPCC_IPR_RN_I5_RESETVAL (0x00000000U)
  9392. #define CSL_EVETPCC_IPR_RN_I5_MAX (0x00000001U)
  9393. #define CSL_EVETPCC_IPR_RN_I4_MASK (0x00000010U)
  9394. #define CSL_EVETPCC_IPR_RN_I4_SHIFT (4U)
  9395. #define CSL_EVETPCC_IPR_RN_I4_RESETVAL (0x00000000U)
  9396. #define CSL_EVETPCC_IPR_RN_I4_MAX (0x00000001U)
  9397. #define CSL_EVETPCC_IPR_RN_I16_MASK (0x00010000U)
  9398. #define CSL_EVETPCC_IPR_RN_I16_SHIFT (16U)
  9399. #define CSL_EVETPCC_IPR_RN_I16_RESETVAL (0x00000000U)
  9400. #define CSL_EVETPCC_IPR_RN_I16_MAX (0x00000001U)
  9401. #define CSL_EVETPCC_IPR_RN_I23_MASK (0x00800000U)
  9402. #define CSL_EVETPCC_IPR_RN_I23_SHIFT (23U)
  9403. #define CSL_EVETPCC_IPR_RN_I23_RESETVAL (0x00000000U)
  9404. #define CSL_EVETPCC_IPR_RN_I23_MAX (0x00000001U)
  9405. #define CSL_EVETPCC_IPR_RN_I7_MASK (0x00000080U)
  9406. #define CSL_EVETPCC_IPR_RN_I7_SHIFT (7U)
  9407. #define CSL_EVETPCC_IPR_RN_I7_RESETVAL (0x00000000U)
  9408. #define CSL_EVETPCC_IPR_RN_I7_MAX (0x00000001U)
  9409. #define CSL_EVETPCC_IPR_RN_I22_MASK (0x00400000U)
  9410. #define CSL_EVETPCC_IPR_RN_I22_SHIFT (22U)
  9411. #define CSL_EVETPCC_IPR_RN_I22_RESETVAL (0x00000000U)
  9412. #define CSL_EVETPCC_IPR_RN_I22_MAX (0x00000001U)
  9413. #define CSL_EVETPCC_IPR_RN_I25_MASK (0x02000000U)
  9414. #define CSL_EVETPCC_IPR_RN_I25_SHIFT (25U)
  9415. #define CSL_EVETPCC_IPR_RN_I25_RESETVAL (0x00000000U)
  9416. #define CSL_EVETPCC_IPR_RN_I25_MAX (0x00000001U)
  9417. #define CSL_EVETPCC_IPR_RN_I24_MASK (0x01000000U)
  9418. #define CSL_EVETPCC_IPR_RN_I24_SHIFT (24U)
  9419. #define CSL_EVETPCC_IPR_RN_I24_RESETVAL (0x00000000U)
  9420. #define CSL_EVETPCC_IPR_RN_I24_MAX (0x00000001U)
  9421. #define CSL_EVETPCC_IPR_RN_I19_MASK (0x00080000U)
  9422. #define CSL_EVETPCC_IPR_RN_I19_SHIFT (19U)
  9423. #define CSL_EVETPCC_IPR_RN_I19_RESETVAL (0x00000000U)
  9424. #define CSL_EVETPCC_IPR_RN_I19_MAX (0x00000001U)
  9425. #define CSL_EVETPCC_IPR_RN_I30_MASK (0x40000000U)
  9426. #define CSL_EVETPCC_IPR_RN_I30_SHIFT (30U)
  9427. #define CSL_EVETPCC_IPR_RN_I30_RESETVAL (0x00000000U)
  9428. #define CSL_EVETPCC_IPR_RN_I30_MAX (0x00000001U)
  9429. #define CSL_EVETPCC_IPR_RN_I11_MASK (0x00000800U)
  9430. #define CSL_EVETPCC_IPR_RN_I11_SHIFT (11U)
  9431. #define CSL_EVETPCC_IPR_RN_I11_RESETVAL (0x00000000U)
  9432. #define CSL_EVETPCC_IPR_RN_I11_MAX (0x00000001U)
  9433. #define CSL_EVETPCC_IPR_RN_I18_MASK (0x00040000U)
  9434. #define CSL_EVETPCC_IPR_RN_I18_SHIFT (18U)
  9435. #define CSL_EVETPCC_IPR_RN_I18_RESETVAL (0x00000000U)
  9436. #define CSL_EVETPCC_IPR_RN_I18_MAX (0x00000001U)
  9437. #define CSL_EVETPCC_IPR_RN_I31_MASK (0x80000000U)
  9438. #define CSL_EVETPCC_IPR_RN_I31_SHIFT (31U)
  9439. #define CSL_EVETPCC_IPR_RN_I31_RESETVAL (0x00000000U)
  9440. #define CSL_EVETPCC_IPR_RN_I31_MAX (0x00000001U)
  9441. #define CSL_EVETPCC_IPR_RN_I10_MASK (0x00000400U)
  9442. #define CSL_EVETPCC_IPR_RN_I10_SHIFT (10U)
  9443. #define CSL_EVETPCC_IPR_RN_I10_RESETVAL (0x00000000U)
  9444. #define CSL_EVETPCC_IPR_RN_I10_MAX (0x00000001U)
  9445. #define CSL_EVETPCC_IPR_RN_I9_MASK (0x00000200U)
  9446. #define CSL_EVETPCC_IPR_RN_I9_SHIFT (9U)
  9447. #define CSL_EVETPCC_IPR_RN_I9_RESETVAL (0x00000000U)
  9448. #define CSL_EVETPCC_IPR_RN_I9_MAX (0x00000001U)
  9449. #define CSL_EVETPCC_IPR_RN_I21_MASK (0x00200000U)
  9450. #define CSL_EVETPCC_IPR_RN_I21_SHIFT (21U)
  9451. #define CSL_EVETPCC_IPR_RN_I21_RESETVAL (0x00000000U)
  9452. #define CSL_EVETPCC_IPR_RN_I21_MAX (0x00000001U)
  9453. #define CSL_EVETPCC_IPR_RN_I8_MASK (0x00000100U)
  9454. #define CSL_EVETPCC_IPR_RN_I8_SHIFT (8U)
  9455. #define CSL_EVETPCC_IPR_RN_I8_RESETVAL (0x00000000U)
  9456. #define CSL_EVETPCC_IPR_RN_I8_MAX (0x00000001U)
  9457. #define CSL_EVETPCC_IPR_RN_I20_MASK (0x00100000U)
  9458. #define CSL_EVETPCC_IPR_RN_I20_SHIFT (20U)
  9459. #define CSL_EVETPCC_IPR_RN_I20_RESETVAL (0x00000000U)
  9460. #define CSL_EVETPCC_IPR_RN_I20_MAX (0x00000001U)
  9461. #define CSL_EVETPCC_IPR_RN_RESETVAL (0x00000000U)
  9462. /* ESRH_RN */
  9463. #define CSL_EVETPCC_ESRH_RN_E41_MASK (0x00000200U)
  9464. #define CSL_EVETPCC_ESRH_RN_E41_SHIFT (9U)
  9465. #define CSL_EVETPCC_ESRH_RN_E41_RESETVAL (0x00000000U)
  9466. #define CSL_EVETPCC_ESRH_RN_E41_MAX (0x00000001U)
  9467. #define CSL_EVETPCC_ESRH_RN_E57_MASK (0x02000000U)
  9468. #define CSL_EVETPCC_ESRH_RN_E57_SHIFT (25U)
  9469. #define CSL_EVETPCC_ESRH_RN_E57_RESETVAL (0x00000000U)
  9470. #define CSL_EVETPCC_ESRH_RN_E57_MAX (0x00000001U)
  9471. #define CSL_EVETPCC_ESRH_RN_E46_MASK (0x00004000U)
  9472. #define CSL_EVETPCC_ESRH_RN_E46_SHIFT (14U)
  9473. #define CSL_EVETPCC_ESRH_RN_E46_RESETVAL (0x00000000U)
  9474. #define CSL_EVETPCC_ESRH_RN_E46_MAX (0x00000001U)
  9475. #define CSL_EVETPCC_ESRH_RN_E42_MASK (0x00000400U)
  9476. #define CSL_EVETPCC_ESRH_RN_E42_SHIFT (10U)
  9477. #define CSL_EVETPCC_ESRH_RN_E42_RESETVAL (0x00000000U)
  9478. #define CSL_EVETPCC_ESRH_RN_E42_MAX (0x00000001U)
  9479. #define CSL_EVETPCC_ESRH_RN_E56_MASK (0x01000000U)
  9480. #define CSL_EVETPCC_ESRH_RN_E56_SHIFT (24U)
  9481. #define CSL_EVETPCC_ESRH_RN_E56_RESETVAL (0x00000000U)
  9482. #define CSL_EVETPCC_ESRH_RN_E56_MAX (0x00000001U)
  9483. #define CSL_EVETPCC_ESRH_RN_E33_MASK (0x00000002U)
  9484. #define CSL_EVETPCC_ESRH_RN_E33_SHIFT (1U)
  9485. #define CSL_EVETPCC_ESRH_RN_E33_RESETVAL (0x00000000U)
  9486. #define CSL_EVETPCC_ESRH_RN_E33_MAX (0x00000001U)
  9487. #define CSL_EVETPCC_ESRH_RN_E43_MASK (0x00000800U)
  9488. #define CSL_EVETPCC_ESRH_RN_E43_SHIFT (11U)
  9489. #define CSL_EVETPCC_ESRH_RN_E43_RESETVAL (0x00000000U)
  9490. #define CSL_EVETPCC_ESRH_RN_E43_MAX (0x00000001U)
  9491. #define CSL_EVETPCC_ESRH_RN_E55_MASK (0x00800000U)
  9492. #define CSL_EVETPCC_ESRH_RN_E55_SHIFT (23U)
  9493. #define CSL_EVETPCC_ESRH_RN_E55_RESETVAL (0x00000000U)
  9494. #define CSL_EVETPCC_ESRH_RN_E55_MAX (0x00000001U)
  9495. #define CSL_EVETPCC_ESRH_RN_E32_MASK (0x00000001U)
  9496. #define CSL_EVETPCC_ESRH_RN_E32_SHIFT (0U)
  9497. #define CSL_EVETPCC_ESRH_RN_E32_RESETVAL (0x00000000U)
  9498. #define CSL_EVETPCC_ESRH_RN_E32_MAX (0x00000001U)
  9499. #define CSL_EVETPCC_ESRH_RN_E48_MASK (0x00010000U)
  9500. #define CSL_EVETPCC_ESRH_RN_E48_SHIFT (16U)
  9501. #define CSL_EVETPCC_ESRH_RN_E48_RESETVAL (0x00000000U)
  9502. #define CSL_EVETPCC_ESRH_RN_E48_MAX (0x00000001U)
  9503. #define CSL_EVETPCC_ESRH_RN_E44_MASK (0x00001000U)
  9504. #define CSL_EVETPCC_ESRH_RN_E44_SHIFT (12U)
  9505. #define CSL_EVETPCC_ESRH_RN_E44_RESETVAL (0x00000000U)
  9506. #define CSL_EVETPCC_ESRH_RN_E44_MAX (0x00000001U)
  9507. #define CSL_EVETPCC_ESRH_RN_E45_MASK (0x00002000U)
  9508. #define CSL_EVETPCC_ESRH_RN_E45_SHIFT (13U)
  9509. #define CSL_EVETPCC_ESRH_RN_E45_RESETVAL (0x00000000U)
  9510. #define CSL_EVETPCC_ESRH_RN_E45_MAX (0x00000001U)
  9511. #define CSL_EVETPCC_ESRH_RN_E49_MASK (0x00020000U)
  9512. #define CSL_EVETPCC_ESRH_RN_E49_SHIFT (17U)
  9513. #define CSL_EVETPCC_ESRH_RN_E49_RESETVAL (0x00000000U)
  9514. #define CSL_EVETPCC_ESRH_RN_E49_MAX (0x00000001U)
  9515. #define CSL_EVETPCC_ESRH_RN_E61_MASK (0x20000000U)
  9516. #define CSL_EVETPCC_ESRH_RN_E61_SHIFT (29U)
  9517. #define CSL_EVETPCC_ESRH_RN_E61_RESETVAL (0x00000000U)
  9518. #define CSL_EVETPCC_ESRH_RN_E61_MAX (0x00000001U)
  9519. #define CSL_EVETPCC_ESRH_RN_E52_MASK (0x00100000U)
  9520. #define CSL_EVETPCC_ESRH_RN_E52_SHIFT (20U)
  9521. #define CSL_EVETPCC_ESRH_RN_E52_RESETVAL (0x00000000U)
  9522. #define CSL_EVETPCC_ESRH_RN_E52_MAX (0x00000001U)
  9523. #define CSL_EVETPCC_ESRH_RN_E63_MASK (0x80000000U)
  9524. #define CSL_EVETPCC_ESRH_RN_E63_SHIFT (31U)
  9525. #define CSL_EVETPCC_ESRH_RN_E63_RESETVAL (0x00000000U)
  9526. #define CSL_EVETPCC_ESRH_RN_E63_MAX (0x00000001U)
  9527. #define CSL_EVETPCC_ESRH_RN_E34_MASK (0x00000004U)
  9528. #define CSL_EVETPCC_ESRH_RN_E34_SHIFT (2U)
  9529. #define CSL_EVETPCC_ESRH_RN_E34_RESETVAL (0x00000000U)
  9530. #define CSL_EVETPCC_ESRH_RN_E34_MAX (0x00000001U)
  9531. #define CSL_EVETPCC_ESRH_RN_E47_MASK (0x00008000U)
  9532. #define CSL_EVETPCC_ESRH_RN_E47_SHIFT (15U)
  9533. #define CSL_EVETPCC_ESRH_RN_E47_RESETVAL (0x00000000U)
  9534. #define CSL_EVETPCC_ESRH_RN_E47_MAX (0x00000001U)
  9535. #define CSL_EVETPCC_ESRH_RN_E60_MASK (0x10000000U)
  9536. #define CSL_EVETPCC_ESRH_RN_E60_SHIFT (28U)
  9537. #define CSL_EVETPCC_ESRH_RN_E60_RESETVAL (0x00000000U)
  9538. #define CSL_EVETPCC_ESRH_RN_E60_MAX (0x00000001U)
  9539. #define CSL_EVETPCC_ESRH_RN_E59_MASK (0x08000000U)
  9540. #define CSL_EVETPCC_ESRH_RN_E59_SHIFT (27U)
  9541. #define CSL_EVETPCC_ESRH_RN_E59_RESETVAL (0x00000000U)
  9542. #define CSL_EVETPCC_ESRH_RN_E59_MAX (0x00000001U)
  9543. #define CSL_EVETPCC_ESRH_RN_E50_MASK (0x00040000U)
  9544. #define CSL_EVETPCC_ESRH_RN_E50_SHIFT (18U)
  9545. #define CSL_EVETPCC_ESRH_RN_E50_RESETVAL (0x00000000U)
  9546. #define CSL_EVETPCC_ESRH_RN_E50_MAX (0x00000001U)
  9547. #define CSL_EVETPCC_ESRH_RN_E58_MASK (0x04000000U)
  9548. #define CSL_EVETPCC_ESRH_RN_E58_SHIFT (26U)
  9549. #define CSL_EVETPCC_ESRH_RN_E58_RESETVAL (0x00000000U)
  9550. #define CSL_EVETPCC_ESRH_RN_E58_MAX (0x00000001U)
  9551. #define CSL_EVETPCC_ESRH_RN_E53_MASK (0x00200000U)
  9552. #define CSL_EVETPCC_ESRH_RN_E53_SHIFT (21U)
  9553. #define CSL_EVETPCC_ESRH_RN_E53_RESETVAL (0x00000000U)
  9554. #define CSL_EVETPCC_ESRH_RN_E53_MAX (0x00000001U)
  9555. #define CSL_EVETPCC_ESRH_RN_E35_MASK (0x00000008U)
  9556. #define CSL_EVETPCC_ESRH_RN_E35_SHIFT (3U)
  9557. #define CSL_EVETPCC_ESRH_RN_E35_RESETVAL (0x00000000U)
  9558. #define CSL_EVETPCC_ESRH_RN_E35_MAX (0x00000001U)
  9559. #define CSL_EVETPCC_ESRH_RN_E51_MASK (0x00080000U)
  9560. #define CSL_EVETPCC_ESRH_RN_E51_SHIFT (19U)
  9561. #define CSL_EVETPCC_ESRH_RN_E51_RESETVAL (0x00000000U)
  9562. #define CSL_EVETPCC_ESRH_RN_E51_MAX (0x00000001U)
  9563. #define CSL_EVETPCC_ESRH_RN_E54_MASK (0x00400000U)
  9564. #define CSL_EVETPCC_ESRH_RN_E54_SHIFT (22U)
  9565. #define CSL_EVETPCC_ESRH_RN_E54_RESETVAL (0x00000000U)
  9566. #define CSL_EVETPCC_ESRH_RN_E54_MAX (0x00000001U)
  9567. #define CSL_EVETPCC_ESRH_RN_E36_MASK (0x00000010U)
  9568. #define CSL_EVETPCC_ESRH_RN_E36_SHIFT (4U)
  9569. #define CSL_EVETPCC_ESRH_RN_E36_RESETVAL (0x00000000U)
  9570. #define CSL_EVETPCC_ESRH_RN_E36_MAX (0x00000001U)
  9571. #define CSL_EVETPCC_ESRH_RN_E62_MASK (0x40000000U)
  9572. #define CSL_EVETPCC_ESRH_RN_E62_SHIFT (30U)
  9573. #define CSL_EVETPCC_ESRH_RN_E62_RESETVAL (0x00000000U)
  9574. #define CSL_EVETPCC_ESRH_RN_E62_MAX (0x00000001U)
  9575. #define CSL_EVETPCC_ESRH_RN_E37_MASK (0x00000020U)
  9576. #define CSL_EVETPCC_ESRH_RN_E37_SHIFT (5U)
  9577. #define CSL_EVETPCC_ESRH_RN_E37_RESETVAL (0x00000000U)
  9578. #define CSL_EVETPCC_ESRH_RN_E37_MAX (0x00000001U)
  9579. #define CSL_EVETPCC_ESRH_RN_E38_MASK (0x00000040U)
  9580. #define CSL_EVETPCC_ESRH_RN_E38_SHIFT (6U)
  9581. #define CSL_EVETPCC_ESRH_RN_E38_RESETVAL (0x00000000U)
  9582. #define CSL_EVETPCC_ESRH_RN_E38_MAX (0x00000001U)
  9583. #define CSL_EVETPCC_ESRH_RN_E39_MASK (0x00000080U)
  9584. #define CSL_EVETPCC_ESRH_RN_E39_SHIFT (7U)
  9585. #define CSL_EVETPCC_ESRH_RN_E39_RESETVAL (0x00000000U)
  9586. #define CSL_EVETPCC_ESRH_RN_E39_MAX (0x00000001U)
  9587. #define CSL_EVETPCC_ESRH_RN_E40_MASK (0x00000100U)
  9588. #define CSL_EVETPCC_ESRH_RN_E40_SHIFT (8U)
  9589. #define CSL_EVETPCC_ESRH_RN_E40_RESETVAL (0x00000000U)
  9590. #define CSL_EVETPCC_ESRH_RN_E40_MAX (0x00000001U)
  9591. #define CSL_EVETPCC_ESRH_RN_RESETVAL (0x00000000U)
  9592. /* QEESR_RN */
  9593. #define CSL_EVETPCC_QEESR_RN_E5_MASK (0x00000020U)
  9594. #define CSL_EVETPCC_QEESR_RN_E5_SHIFT (5U)
  9595. #define CSL_EVETPCC_QEESR_RN_E5_RESETVAL (0x00000000U)
  9596. #define CSL_EVETPCC_QEESR_RN_E5_MAX (0x00000001U)
  9597. #define CSL_EVETPCC_QEESR_RN_E3_MASK (0x00000008U)
  9598. #define CSL_EVETPCC_QEESR_RN_E3_SHIFT (3U)
  9599. #define CSL_EVETPCC_QEESR_RN_E3_RESETVAL (0x00000000U)
  9600. #define CSL_EVETPCC_QEESR_RN_E3_MAX (0x00000001U)
  9601. #define CSL_EVETPCC_QEESR_RN_E6_MASK (0x00000040U)
  9602. #define CSL_EVETPCC_QEESR_RN_E6_SHIFT (6U)
  9603. #define CSL_EVETPCC_QEESR_RN_E6_RESETVAL (0x00000000U)
  9604. #define CSL_EVETPCC_QEESR_RN_E6_MAX (0x00000001U)
  9605. #define CSL_EVETPCC_QEESR_RN_E4_MASK (0x00000010U)
  9606. #define CSL_EVETPCC_QEESR_RN_E4_SHIFT (4U)
  9607. #define CSL_EVETPCC_QEESR_RN_E4_RESETVAL (0x00000000U)
  9608. #define CSL_EVETPCC_QEESR_RN_E4_MAX (0x00000001U)
  9609. #define CSL_EVETPCC_QEESR_RN_E1_MASK (0x00000002U)
  9610. #define CSL_EVETPCC_QEESR_RN_E1_SHIFT (1U)
  9611. #define CSL_EVETPCC_QEESR_RN_E1_RESETVAL (0x00000000U)
  9612. #define CSL_EVETPCC_QEESR_RN_E1_MAX (0x00000001U)
  9613. #define CSL_EVETPCC_QEESR_RN_E2_MASK (0x00000004U)
  9614. #define CSL_EVETPCC_QEESR_RN_E2_SHIFT (2U)
  9615. #define CSL_EVETPCC_QEESR_RN_E2_RESETVAL (0x00000000U)
  9616. #define CSL_EVETPCC_QEESR_RN_E2_MAX (0x00000001U)
  9617. #define CSL_EVETPCC_QEESR_RN_E0_MASK (0x00000001U)
  9618. #define CSL_EVETPCC_QEESR_RN_E0_SHIFT (0U)
  9619. #define CSL_EVETPCC_QEESR_RN_E0_RESETVAL (0x00000000U)
  9620. #define CSL_EVETPCC_QEESR_RN_E0_MAX (0x00000001U)
  9621. #define CSL_EVETPCC_QEESR_RN_E7_MASK (0x00000080U)
  9622. #define CSL_EVETPCC_QEESR_RN_E7_SHIFT (7U)
  9623. #define CSL_EVETPCC_QEESR_RN_E7_RESETVAL (0x00000000U)
  9624. #define CSL_EVETPCC_QEESR_RN_E7_MAX (0x00000001U)
  9625. #define CSL_EVETPCC_QEESR_RN_RESETVAL (0x00000000U)
  9626. /* ERH_RN */
  9627. #define CSL_EVETPCC_ERH_RN_E61_MASK (0x20000000U)
  9628. #define CSL_EVETPCC_ERH_RN_E61_SHIFT (29U)
  9629. #define CSL_EVETPCC_ERH_RN_E61_RESETVAL (0x00000000U)
  9630. #define CSL_EVETPCC_ERH_RN_E61_MAX (0x00000001U)
  9631. #define CSL_EVETPCC_ERH_RN_E54_MASK (0x00400000U)
  9632. #define CSL_EVETPCC_ERH_RN_E54_SHIFT (22U)
  9633. #define CSL_EVETPCC_ERH_RN_E54_RESETVAL (0x00000000U)
  9634. #define CSL_EVETPCC_ERH_RN_E54_MAX (0x00000001U)
  9635. #define CSL_EVETPCC_ERH_RN_E55_MASK (0x00800000U)
  9636. #define CSL_EVETPCC_ERH_RN_E55_SHIFT (23U)
  9637. #define CSL_EVETPCC_ERH_RN_E55_RESETVAL (0x00000000U)
  9638. #define CSL_EVETPCC_ERH_RN_E55_MAX (0x00000001U)
  9639. #define CSL_EVETPCC_ERH_RN_E59_MASK (0x08000000U)
  9640. #define CSL_EVETPCC_ERH_RN_E59_SHIFT (27U)
  9641. #define CSL_EVETPCC_ERH_RN_E59_RESETVAL (0x00000000U)
  9642. #define CSL_EVETPCC_ERH_RN_E59_MAX (0x00000001U)
  9643. #define CSL_EVETPCC_ERH_RN_E50_MASK (0x00040000U)
  9644. #define CSL_EVETPCC_ERH_RN_E50_SHIFT (18U)
  9645. #define CSL_EVETPCC_ERH_RN_E50_RESETVAL (0x00000000U)
  9646. #define CSL_EVETPCC_ERH_RN_E50_MAX (0x00000001U)
  9647. #define CSL_EVETPCC_ERH_RN_E52_MASK (0x00100000U)
  9648. #define CSL_EVETPCC_ERH_RN_E52_SHIFT (20U)
  9649. #define CSL_EVETPCC_ERH_RN_E52_RESETVAL (0x00000000U)
  9650. #define CSL_EVETPCC_ERH_RN_E52_MAX (0x00000001U)
  9651. #define CSL_EVETPCC_ERH_RN_E53_MASK (0x00200000U)
  9652. #define CSL_EVETPCC_ERH_RN_E53_SHIFT (21U)
  9653. #define CSL_EVETPCC_ERH_RN_E53_RESETVAL (0x00000000U)
  9654. #define CSL_EVETPCC_ERH_RN_E53_MAX (0x00000001U)
  9655. #define CSL_EVETPCC_ERH_RN_E51_MASK (0x00080000U)
  9656. #define CSL_EVETPCC_ERH_RN_E51_SHIFT (19U)
  9657. #define CSL_EVETPCC_ERH_RN_E51_RESETVAL (0x00000000U)
  9658. #define CSL_EVETPCC_ERH_RN_E51_MAX (0x00000001U)
  9659. #define CSL_EVETPCC_ERH_RN_E36_MASK (0x00000010U)
  9660. #define CSL_EVETPCC_ERH_RN_E36_SHIFT (4U)
  9661. #define CSL_EVETPCC_ERH_RN_E36_RESETVAL (0x00000000U)
  9662. #define CSL_EVETPCC_ERH_RN_E36_MAX (0x00000001U)
  9663. #define CSL_EVETPCC_ERH_RN_E40_MASK (0x00000100U)
  9664. #define CSL_EVETPCC_ERH_RN_E40_SHIFT (8U)
  9665. #define CSL_EVETPCC_ERH_RN_E40_RESETVAL (0x00000000U)
  9666. #define CSL_EVETPCC_ERH_RN_E40_MAX (0x00000001U)
  9667. #define CSL_EVETPCC_ERH_RN_E39_MASK (0x00000080U)
  9668. #define CSL_EVETPCC_ERH_RN_E39_SHIFT (7U)
  9669. #define CSL_EVETPCC_ERH_RN_E39_RESETVAL (0x00000000U)
  9670. #define CSL_EVETPCC_ERH_RN_E39_MAX (0x00000001U)
  9671. #define CSL_EVETPCC_ERH_RN_E38_MASK (0x00000040U)
  9672. #define CSL_EVETPCC_ERH_RN_E38_SHIFT (6U)
  9673. #define CSL_EVETPCC_ERH_RN_E38_RESETVAL (0x00000000U)
  9674. #define CSL_EVETPCC_ERH_RN_E38_MAX (0x00000001U)
  9675. #define CSL_EVETPCC_ERH_RN_E42_MASK (0x00000400U)
  9676. #define CSL_EVETPCC_ERH_RN_E42_SHIFT (10U)
  9677. #define CSL_EVETPCC_ERH_RN_E42_RESETVAL (0x00000000U)
  9678. #define CSL_EVETPCC_ERH_RN_E42_MAX (0x00000001U)
  9679. #define CSL_EVETPCC_ERH_RN_E49_MASK (0x00020000U)
  9680. #define CSL_EVETPCC_ERH_RN_E49_SHIFT (17U)
  9681. #define CSL_EVETPCC_ERH_RN_E49_RESETVAL (0x00000000U)
  9682. #define CSL_EVETPCC_ERH_RN_E49_MAX (0x00000001U)
  9683. #define CSL_EVETPCC_ERH_RN_E41_MASK (0x00000200U)
  9684. #define CSL_EVETPCC_ERH_RN_E41_SHIFT (9U)
  9685. #define CSL_EVETPCC_ERH_RN_E41_RESETVAL (0x00000000U)
  9686. #define CSL_EVETPCC_ERH_RN_E41_MAX (0x00000001U)
  9687. #define CSL_EVETPCC_ERH_RN_E32_MASK (0x00000001U)
  9688. #define CSL_EVETPCC_ERH_RN_E32_SHIFT (0U)
  9689. #define CSL_EVETPCC_ERH_RN_E32_RESETVAL (0x00000000U)
  9690. #define CSL_EVETPCC_ERH_RN_E32_MAX (0x00000001U)
  9691. #define CSL_EVETPCC_ERH_RN_E35_MASK (0x00000008U)
  9692. #define CSL_EVETPCC_ERH_RN_E35_SHIFT (3U)
  9693. #define CSL_EVETPCC_ERH_RN_E35_RESETVAL (0x00000000U)
  9694. #define CSL_EVETPCC_ERH_RN_E35_MAX (0x00000001U)
  9695. #define CSL_EVETPCC_ERH_RN_E43_MASK (0x00000800U)
  9696. #define CSL_EVETPCC_ERH_RN_E43_SHIFT (11U)
  9697. #define CSL_EVETPCC_ERH_RN_E43_RESETVAL (0x00000000U)
  9698. #define CSL_EVETPCC_ERH_RN_E43_MAX (0x00000001U)
  9699. #define CSL_EVETPCC_ERH_RN_E34_MASK (0x00000004U)
  9700. #define CSL_EVETPCC_ERH_RN_E34_SHIFT (2U)
  9701. #define CSL_EVETPCC_ERH_RN_E34_RESETVAL (0x00000000U)
  9702. #define CSL_EVETPCC_ERH_RN_E34_MAX (0x00000001U)
  9703. #define CSL_EVETPCC_ERH_RN_E44_MASK (0x00001000U)
  9704. #define CSL_EVETPCC_ERH_RN_E44_SHIFT (12U)
  9705. #define CSL_EVETPCC_ERH_RN_E44_RESETVAL (0x00000000U)
  9706. #define CSL_EVETPCC_ERH_RN_E44_MAX (0x00000001U)
  9707. #define CSL_EVETPCC_ERH_RN_E37_MASK (0x00000020U)
  9708. #define CSL_EVETPCC_ERH_RN_E37_SHIFT (5U)
  9709. #define CSL_EVETPCC_ERH_RN_E37_RESETVAL (0x00000000U)
  9710. #define CSL_EVETPCC_ERH_RN_E37_MAX (0x00000001U)
  9711. #define CSL_EVETPCC_ERH_RN_E45_MASK (0x00002000U)
  9712. #define CSL_EVETPCC_ERH_RN_E45_SHIFT (13U)
  9713. #define CSL_EVETPCC_ERH_RN_E45_RESETVAL (0x00000000U)
  9714. #define CSL_EVETPCC_ERH_RN_E45_MAX (0x00000001U)
  9715. #define CSL_EVETPCC_ERH_RN_E58_MASK (0x04000000U)
  9716. #define CSL_EVETPCC_ERH_RN_E58_SHIFT (26U)
  9717. #define CSL_EVETPCC_ERH_RN_E58_RESETVAL (0x00000000U)
  9718. #define CSL_EVETPCC_ERH_RN_E58_MAX (0x00000001U)
  9719. #define CSL_EVETPCC_ERH_RN_E62_MASK (0x40000000U)
  9720. #define CSL_EVETPCC_ERH_RN_E62_SHIFT (30U)
  9721. #define CSL_EVETPCC_ERH_RN_E62_RESETVAL (0x00000000U)
  9722. #define CSL_EVETPCC_ERH_RN_E62_MAX (0x00000001U)
  9723. #define CSL_EVETPCC_ERH_RN_E46_MASK (0x00004000U)
  9724. #define CSL_EVETPCC_ERH_RN_E46_SHIFT (14U)
  9725. #define CSL_EVETPCC_ERH_RN_E46_RESETVAL (0x00000000U)
  9726. #define CSL_EVETPCC_ERH_RN_E46_MAX (0x00000001U)
  9727. #define CSL_EVETPCC_ERH_RN_E57_MASK (0x02000000U)
  9728. #define CSL_EVETPCC_ERH_RN_E57_SHIFT (25U)
  9729. #define CSL_EVETPCC_ERH_RN_E57_RESETVAL (0x00000000U)
  9730. #define CSL_EVETPCC_ERH_RN_E57_MAX (0x00000001U)
  9731. #define CSL_EVETPCC_ERH_RN_E63_MASK (0x80000000U)
  9732. #define CSL_EVETPCC_ERH_RN_E63_SHIFT (31U)
  9733. #define CSL_EVETPCC_ERH_RN_E63_RESETVAL (0x00000000U)
  9734. #define CSL_EVETPCC_ERH_RN_E63_MAX (0x00000001U)
  9735. #define CSL_EVETPCC_ERH_RN_E47_MASK (0x00008000U)
  9736. #define CSL_EVETPCC_ERH_RN_E47_SHIFT (15U)
  9737. #define CSL_EVETPCC_ERH_RN_E47_RESETVAL (0x00000000U)
  9738. #define CSL_EVETPCC_ERH_RN_E47_MAX (0x00000001U)
  9739. #define CSL_EVETPCC_ERH_RN_E56_MASK (0x01000000U)
  9740. #define CSL_EVETPCC_ERH_RN_E56_SHIFT (24U)
  9741. #define CSL_EVETPCC_ERH_RN_E56_RESETVAL (0x00000000U)
  9742. #define CSL_EVETPCC_ERH_RN_E56_MAX (0x00000001U)
  9743. #define CSL_EVETPCC_ERH_RN_E48_MASK (0x00010000U)
  9744. #define CSL_EVETPCC_ERH_RN_E48_SHIFT (16U)
  9745. #define CSL_EVETPCC_ERH_RN_E48_RESETVAL (0x00000000U)
  9746. #define CSL_EVETPCC_ERH_RN_E48_MAX (0x00000001U)
  9747. #define CSL_EVETPCC_ERH_RN_E33_MASK (0x00000002U)
  9748. #define CSL_EVETPCC_ERH_RN_E33_SHIFT (1U)
  9749. #define CSL_EVETPCC_ERH_RN_E33_RESETVAL (0x00000000U)
  9750. #define CSL_EVETPCC_ERH_RN_E33_MAX (0x00000001U)
  9751. #define CSL_EVETPCC_ERH_RN_E60_MASK (0x10000000U)
  9752. #define CSL_EVETPCC_ERH_RN_E60_SHIFT (28U)
  9753. #define CSL_EVETPCC_ERH_RN_E60_RESETVAL (0x00000000U)
  9754. #define CSL_EVETPCC_ERH_RN_E60_MAX (0x00000001U)
  9755. #define CSL_EVETPCC_ERH_RN_RESETVAL (0x00000000U)
  9756. /* OPT */
  9757. #define CSL_EVETPCC_OPT_PRIV_MASK (0x80000000U)
  9758. #define CSL_EVETPCC_OPT_PRIV_SHIFT (31U)
  9759. #define CSL_EVETPCC_OPT_PRIV_RESETVAL (0x00000000U)
  9760. #define CSL_EVETPCC_OPT_PRIV_MAX (0x00000001U)
  9761. #define CSL_EVETPCC_OPT_SECURE_MASK (0x40000000U)
  9762. #define CSL_EVETPCC_OPT_SECURE_SHIFT (30U)
  9763. #define CSL_EVETPCC_OPT_SECURE_RESETVAL (0x00000000U)
  9764. #define CSL_EVETPCC_OPT_SECURE_MAX (0x00000001U)
  9765. #define CSL_EVETPCC_OPT_PRIVID_MASK (0x0F000000U)
  9766. #define CSL_EVETPCC_OPT_PRIVID_SHIFT (24U)
  9767. #define CSL_EVETPCC_OPT_PRIVID_RESETVAL (0x00000000U)
  9768. #define CSL_EVETPCC_OPT_PRIVID_MAX (0x0000000fU)
  9769. #define CSL_EVETPCC_OPT_ITCCHEN_MASK (0x00800000U)
  9770. #define CSL_EVETPCC_OPT_ITCCHEN_SHIFT (23U)
  9771. #define CSL_EVETPCC_OPT_ITCCHEN_RESETVAL (0x00000000U)
  9772. #define CSL_EVETPCC_OPT_ITCCHEN_MAX (0x00000001U)
  9773. #define CSL_EVETPCC_OPT_TCCHEN_MASK (0x00400000U)
  9774. #define CSL_EVETPCC_OPT_TCCHEN_SHIFT (22U)
  9775. #define CSL_EVETPCC_OPT_TCCHEN_RESETVAL (0x00000000U)
  9776. #define CSL_EVETPCC_OPT_TCCHEN_MAX (0x00000001U)
  9777. #define CSL_EVETPCC_OPT_ITCINTEN_MASK (0x00200000U)
  9778. #define CSL_EVETPCC_OPT_ITCINTEN_SHIFT (21U)
  9779. #define CSL_EVETPCC_OPT_ITCINTEN_RESETVAL (0x00000000U)
  9780. #define CSL_EVETPCC_OPT_ITCINTEN_MAX (0x00000001U)
  9781. #define CSL_EVETPCC_OPT_TCINTEN_MASK (0x00100000U)
  9782. #define CSL_EVETPCC_OPT_TCINTEN_SHIFT (20U)
  9783. #define CSL_EVETPCC_OPT_TCINTEN_RESETVAL (0x00000000U)
  9784. #define CSL_EVETPCC_OPT_TCINTEN_MAX (0x00000001U)
  9785. #define CSL_EVETPCC_OPT_WIMODE_MASK (0x00080000U)
  9786. #define CSL_EVETPCC_OPT_WIMODE_SHIFT (19U)
  9787. #define CSL_EVETPCC_OPT_WIMODE_RESETVAL (0x00000000U)
  9788. #define CSL_EVETPCC_OPT_WIMODE_MAX (0x00000001U)
  9789. #define CSL_EVETPCC_OPT_TCC_MASK (0x0003F000U)
  9790. #define CSL_EVETPCC_OPT_TCC_SHIFT (12U)
  9791. #define CSL_EVETPCC_OPT_TCC_RESETVAL (0x00000000U)
  9792. #define CSL_EVETPCC_OPT_TCC_MAX (0x0000003fU)
  9793. #define CSL_EVETPCC_OPT_TCCMODE_MASK (0x00000800U)
  9794. #define CSL_EVETPCC_OPT_TCCMODE_SHIFT (11U)
  9795. #define CSL_EVETPCC_OPT_TCCMODE_RESETVAL (0x00000000U)
  9796. #define CSL_EVETPCC_OPT_TCCMODE_MAX (0x00000001U)
  9797. #define CSL_EVETPCC_OPT_FWID_MASK (0x00000700U)
  9798. #define CSL_EVETPCC_OPT_FWID_SHIFT (8U)
  9799. #define CSL_EVETPCC_OPT_FWID_RESETVAL (0x00000000U)
  9800. #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH256BIT (0x00000005U)
  9801. #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH128BIT (0x00000004U)
  9802. #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH64BIT (0x00000003U)
  9803. #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH32BIT (0x00000002U)
  9804. #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH16BIT (0x00000001U)
  9805. #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH8BIT (0x00000000U)
  9806. #define CSL_EVETPCC_OPT_STATIC_MASK (0x00000008U)
  9807. #define CSL_EVETPCC_OPT_STATIC_SHIFT (3U)
  9808. #define CSL_EVETPCC_OPT_STATIC_RESETVAL (0x00000000U)
  9809. #define CSL_EVETPCC_OPT_STATIC_MAX (0x00000001U)
  9810. #define CSL_EVETPCC_OPT_SYNCDIM_MASK (0x00000004U)
  9811. #define CSL_EVETPCC_OPT_SYNCDIM_SHIFT (2U)
  9812. #define CSL_EVETPCC_OPT_SYNCDIM_RESETVAL (0x00000000U)
  9813. #define CSL_EVETPCC_OPT_SYNCDIM_MAX (0x00000001U)
  9814. #define CSL_EVETPCC_OPT_DAM_MASK (0x00000002U)
  9815. #define CSL_EVETPCC_OPT_DAM_SHIFT (1U)
  9816. #define CSL_EVETPCC_OPT_DAM_RESETVAL (0x00000000U)
  9817. #define CSL_EVETPCC_OPT_DAM_MAX (0x00000001U)
  9818. #define CSL_EVETPCC_OPT_SAM_MASK (0x00000001U)
  9819. #define CSL_EVETPCC_OPT_SAM_SHIFT (0U)
  9820. #define CSL_EVETPCC_OPT_SAM_RESETVAL (0x00000000U)
  9821. #define CSL_EVETPCC_OPT_SAM_MAX (0x00000001U)
  9822. #define CSL_EVETPCC_OPT_RESETVAL (0x00000000U)
  9823. /* SRC */
  9824. #define CSL_EVETPCC_SRC_SRC_MASK (0xFFFFFFFFU)
  9825. #define CSL_EVETPCC_SRC_SRC_SHIFT (0U)
  9826. #define CSL_EVETPCC_SRC_SRC_RESETVAL (0x00000000U)
  9827. #define CSL_EVETPCC_SRC_SRC_MAX (0xffffffffU)
  9828. #define CSL_EVETPCC_SRC_RESETVAL (0x00000000U)
  9829. /* ABCNT */
  9830. #define CSL_EVETPCC_ABCNT_ACNT_MASK (0x0000FFFFU)
  9831. #define CSL_EVETPCC_ABCNT_ACNT_SHIFT (0U)
  9832. #define CSL_EVETPCC_ABCNT_ACNT_RESETVAL (0x00000000U)
  9833. #define CSL_EVETPCC_ABCNT_ACNT_MAX (0x0000ffffU)
  9834. #define CSL_EVETPCC_ABCNT_BCNT_MASK (0xFFFF0000U)
  9835. #define CSL_EVETPCC_ABCNT_BCNT_SHIFT (16U)
  9836. #define CSL_EVETPCC_ABCNT_BCNT_RESETVAL (0x00000000U)
  9837. #define CSL_EVETPCC_ABCNT_BCNT_MAX (0x0000ffffU)
  9838. #define CSL_EVETPCC_ABCNT_RESETVAL (0x00000000U)
  9839. /* BIDX */
  9840. #define CSL_EVETPCC_BIDX_SBIDX_MASK (0x0000FFFFU)
  9841. #define CSL_EVETPCC_BIDX_SBIDX_SHIFT (0U)
  9842. #define CSL_EVETPCC_BIDX_SBIDX_RESETVAL (0x00000000U)
  9843. #define CSL_EVETPCC_BIDX_SBIDX_MAX (0x0000ffffU)
  9844. #define CSL_EVETPCC_BIDX_DBIDX_MASK (0xFFFF0000U)
  9845. #define CSL_EVETPCC_BIDX_DBIDX_SHIFT (16U)
  9846. #define CSL_EVETPCC_BIDX_DBIDX_RESETVAL (0x00000000U)
  9847. #define CSL_EVETPCC_BIDX_DBIDX_MAX (0x0000ffffU)
  9848. #define CSL_EVETPCC_BIDX_RESETVAL (0x00000000U)
  9849. /* LNK */
  9850. #define CSL_EVETPCC_LNK_BCNTRLD_MASK (0xFFFF0000U)
  9851. #define CSL_EVETPCC_LNK_BCNTRLD_SHIFT (16U)
  9852. #define CSL_EVETPCC_LNK_BCNTRLD_RESETVAL (0x00000000U)
  9853. #define CSL_EVETPCC_LNK_BCNTRLD_MAX (0x0000ffffU)
  9854. #define CSL_EVETPCC_LNK_LINK_MASK (0x0000FFFFU)
  9855. #define CSL_EVETPCC_LNK_LINK_SHIFT (0U)
  9856. #define CSL_EVETPCC_LNK_LINK_RESETVAL (0x00000000U)
  9857. #define CSL_EVETPCC_LNK_LINK_MAX (0x0000ffffU)
  9858. #define CSL_EVETPCC_LNK_RESETVAL (0x00000000U)
  9859. /* CIDX */
  9860. #define CSL_EVETPCC_CIDX_SCIDX_MASK (0x0000FFFFU)
  9861. #define CSL_EVETPCC_CIDX_SCIDX_SHIFT (0U)
  9862. #define CSL_EVETPCC_CIDX_SCIDX_RESETVAL (0x00000000U)
  9863. #define CSL_EVETPCC_CIDX_SCIDX_MAX (0x0000ffffU)
  9864. #define CSL_EVETPCC_CIDX_DCIDX_MASK (0xFFFF0000U)
  9865. #define CSL_EVETPCC_CIDX_DCIDX_SHIFT (16U)
  9866. #define CSL_EVETPCC_CIDX_DCIDX_RESETVAL (0x00000000U)
  9867. #define CSL_EVETPCC_CIDX_DCIDX_MAX (0x0000ffffU)
  9868. #define CSL_EVETPCC_CIDX_RESETVAL (0x00000000U)
  9869. /* CCNT */
  9870. #define CSL_EVETPCC_CCNT_CCNT_MASK (0x0000FFFFU)
  9871. #define CSL_EVETPCC_CCNT_CCNT_SHIFT (0U)
  9872. #define CSL_EVETPCC_CCNT_CCNT_RESETVAL (0x00000000U)
  9873. #define CSL_EVETPCC_CCNT_CCNT_MAX (0x0000ffffU)
  9874. #define CSL_EVETPCC_CCNT_RESETVAL (0x00000000U)
  9875. /* DST */
  9876. #define CSL_EVETPCC_DST_DST_MASK (0xFFFFFFFFU)
  9877. #define CSL_EVETPCC_DST_DST_SHIFT (0U)
  9878. #define CSL_EVETPCC_DST_DST_RESETVAL (0x00000000U)
  9879. #define CSL_EVETPCC_DST_DST_MAX (0xffffffffU)
  9880. #define CSL_EVETPCC_DST_RESETVAL (0x00000000U)
  9881. #ifdef __cplusplus
  9882. }
  9883. #endif
  9884. #endif