Test/linux-devkit/sysroots/armv7ahf-neon-linux-gnueabi/usr/include/ti/csl/cslr_dfe_dpda.h

/*
 * cslr_dfe_dpda.h
 *
 * This file contains the macros for Register Chip Support Library (CSL) which 
 * can be used for operations on the respective underlying hardware/peripheral
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

/* The file is auto generated at 11:02:54 08/16/13 (Rev 1.71)*/

#ifndef CSLR_DFE_DPDA_H__
#define CSLR_DFE_DPDA_H__

#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/

typedef struct
{
    volatile Uint32 ie_register;
    volatile Uint32 q_register;
} CSL_DFE_DPDA_DPDA_SCALAR_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_000_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_001_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_002_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_003_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_004_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_005_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_006_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_007_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_008_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_009_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_010_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_011_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_012_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_013_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_014_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_015_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_016_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_017_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_018_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_019_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_020_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_021_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_022_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_023_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_024_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_025_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_026_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_027_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_028_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_029_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_030_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_031_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_032_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_033_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_034_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_035_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_036_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_037_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_038_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_039_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_040_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_041_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_042_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_043_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_044_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_045_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_046_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_047_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_048_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_049_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_050_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_051_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_052_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_053_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_054_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_055_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_056_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_057_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_058_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_059_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_060_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_061_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_062_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_063_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_064_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_065_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_066_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_067_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_068_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_069_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_070_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_071_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_072_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_073_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_074_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_075_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_076_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_077_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_078_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_079_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_080_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_081_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_082_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_083_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_084_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_085_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_086_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_087_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_088_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_089_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_090_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_091_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_092_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_093_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_094_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_095_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_096_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_097_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_098_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_099_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_100_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_101_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_102_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_103_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_104_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_105_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_106_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_107_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_108_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_109_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_110_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_111_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_112_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_113_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_114_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_115_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_116_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_117_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_118_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_119_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_120_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_121_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_122_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_123_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_124_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_125_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_126_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_127_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_128_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_129_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_130_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_131_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_132_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_133_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_134_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_135_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_136_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_137_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_138_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_139_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_140_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_141_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_142_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_143_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_144_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_145_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_146_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_147_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_148_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_149_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_150_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_151_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_152_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_153_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_154_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_155_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_156_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_157_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_158_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_159_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_160_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_161_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_162_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_163_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_164_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_165_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_166_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_167_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_168_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_169_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_170_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_171_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_172_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_173_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_174_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_175_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_176_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_177_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_178_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_179_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_180_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_181_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_182_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_183_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_184_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_185_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_186_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_187_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_188_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_189_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_190_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_191_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_192_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_193_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_194_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_195_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_196_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_197_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_198_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_199_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_200_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_201_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_202_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_203_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_204_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_205_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_206_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_207_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_208_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_209_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_210_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_211_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_212_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_213_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_214_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_215_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_216_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_217_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_218_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_219_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_220_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_221_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_222_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_223_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_224_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_225_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_226_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_227_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_228_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_229_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_230_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_231_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_232_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_233_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_234_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_235_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_236_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_237_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_238_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_239_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_240_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_241_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_242_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_243_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_244_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_245_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_246_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_247_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_248_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_249_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_250_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_251_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_252_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_253_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_254_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_255_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_256_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_257_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_258_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_259_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_260_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_261_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_262_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_263_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_264_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_265_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_266_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_267_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_268_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_269_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_270_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_271_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_272_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_273_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_274_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_275_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_276_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_277_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_278_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_279_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_280_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_281_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_282_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_283_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_284_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_285_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_286_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_287_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_288_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_289_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_290_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_291_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_292_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_293_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_294_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_295_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_296_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_297_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_298_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_299_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_300_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_301_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_302_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_303_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_304_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_305_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_306_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_307_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_308_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_309_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_310_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_311_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_312_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_313_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_314_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_315_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_316_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_317_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_318_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_319_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_320_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_321_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_322_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_323_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_324_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_325_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_326_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_327_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_328_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_329_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_330_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_331_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_332_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_333_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_334_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_335_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_336_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_337_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_338_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_339_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_340_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_341_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_342_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_343_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_344_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_345_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_346_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_347_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_348_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_349_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_350_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_351_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_352_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_353_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_354_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_355_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_356_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_357_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_358_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_359_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_360_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_361_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_362_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_363_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_364_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_365_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_366_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_367_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_368_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_369_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_370_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_371_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_372_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_373_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_374_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_375_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_376_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_377_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_378_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_379_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_380_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_381_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_382_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_383_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_384_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_385_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_386_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_387_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_388_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_389_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_390_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_391_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_392_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_393_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_394_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_395_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_396_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_397_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_398_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_399_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_400_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_401_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_402_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_403_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_404_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_405_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_406_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_407_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_408_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_409_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_410_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_411_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_412_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_413_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_414_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_415_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_416_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_417_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_418_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_419_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_420_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_421_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_422_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_423_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_424_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_425_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_426_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_427_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_428_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_429_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_430_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_431_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_432_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_433_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_434_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_435_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_436_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_437_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_438_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_439_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_440_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_441_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_442_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_443_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_444_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_445_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_446_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_447_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_448_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_449_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_450_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_451_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_452_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_453_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_454_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_455_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_456_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_457_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_458_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_459_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_460_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_461_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_462_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_463_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_464_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_465_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_466_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_467_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_468_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_469_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_470_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_471_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_472_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_473_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_474_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_475_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_476_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_477_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_478_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_479_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_480_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_481_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_482_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_483_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_484_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_485_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_486_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_487_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_488_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_489_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_490_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_491_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_492_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_493_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_494_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_495_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_496_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_497_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_498_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_499_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_500_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_501_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_502_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_503_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_504_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_505_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_506_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_507_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_508_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_509_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_510_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_511_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_512_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_513_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_514_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_515_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_516_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_517_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_518_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_519_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_520_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_521_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_522_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_523_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_524_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_525_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_526_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_527_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_528_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_529_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_530_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_531_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_532_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_533_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_534_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_535_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_536_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_537_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_538_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_539_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_540_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_541_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_542_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_543_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_544_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_545_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_546_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_547_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_548_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_549_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_550_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_551_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_552_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_553_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_554_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_555_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_556_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_557_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_558_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_559_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_560_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_561_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_562_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_563_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_564_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_565_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_566_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_567_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_568_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_569_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_570_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_571_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_572_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_573_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_574_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_575_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_576_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_577_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_578_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_579_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_580_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_581_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_582_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_583_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_584_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_585_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_586_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_587_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_588_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_589_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_590_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_591_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_592_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_593_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_594_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_595_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_596_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_597_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_598_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_599_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_600_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_601_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_602_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_603_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_604_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_605_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_606_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_607_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_608_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_609_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_610_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_611_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_612_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_613_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_614_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_615_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_616_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_617_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_618_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_619_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_620_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_621_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_622_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_623_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_624_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_625_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_626_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_627_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_628_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_629_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_630_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_631_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_632_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_633_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_634_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_635_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_636_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_637_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_638_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_639_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_640_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_641_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_642_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_643_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_644_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_645_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_646_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_647_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_648_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_649_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_650_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_651_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_652_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_653_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_654_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_655_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_656_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_657_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_658_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_659_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_660_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_661_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_662_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_663_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_664_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_665_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_666_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_667_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_668_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_669_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_670_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_671_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_672_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_673_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_674_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_675_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_676_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_677_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_678_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_679_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_680_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_681_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_682_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_683_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_684_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_685_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_686_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_687_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_688_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_689_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_690_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_691_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_692_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_693_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_694_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_695_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_696_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_697_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_698_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_699_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_700_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_701_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_702_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_703_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_704_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_705_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_706_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_707_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_708_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_709_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_710_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_711_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_712_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_713_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_714_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_715_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_716_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_717_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_718_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_719_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_720_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_721_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_722_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_723_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_724_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_725_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_726_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_727_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_728_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_729_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_730_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_731_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_732_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_733_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_734_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_735_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_736_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_737_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_738_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_739_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_740_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_741_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_742_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_743_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_744_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_745_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_746_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_747_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_748_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_749_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_750_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_751_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_752_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_753_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_754_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_755_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_756_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_757_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_758_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_759_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_760_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_761_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_762_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_763_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_764_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_765_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_766_REGS;

typedef struct
{
    volatile Uint32 ie;
    volatile Uint32 q;
} CSL_DFE_DPDA_DPDA_PREG_767_REGS;

typedef struct 
{
    /* Addr: h(0), d(0) */
    volatile Uint32 rsvd0[1];
    /* Addr: h(4), d(4) */
    volatile Uint32 mask;
    /* Addr: h(8), d(8) */
    volatile Uint32 status;
    /* Addr: h(C), d(12) */
    volatile Uint32 force;
    /* Addr: h(10), d(16) */
    volatile Uint32 rsvd1[28];
    /* Addr: h(80), d(128) */
    volatile Uint32 inits;
    /* Addr: h(84), d(132) */
    volatile Uint32 jacob_static;
    /* Addr: h(88), d(136) */
    volatile Uint32 main_control;
    /* Addr: h(8C), d(140) */
    volatile Uint32 interrupt_params;
    /* Addr: h(90), d(144) */
    volatile Uint32 interrupt_main_and_req;
    /* Addr: h(94), d(148) */
    volatile Uint32 exponents;
    /* Addr: h(98), d(152) */
    volatile Uint32 testbus_control;
    /* Addr: h(9C), d(156) */
    volatile Uint32 debug_breakpoint;
    /* Addr: h(A0), d(160) */
    volatile Uint32 debug_sets;
    /* Addr: h(A4), d(164) */
    volatile Uint32 rsvd2[7];
    /* Addr: h(C0), d(192) */
    volatile Uint32 cr0_0;
    /* Addr: h(C4), d(196) */
    volatile Uint32 cr0_1;
    /* Addr: h(C8), d(200) */
    volatile Uint32 cr1_0;
    /* Addr: h(CC), d(204) */
    volatile Uint32 cr1_1;
    /* Addr: h(D0), d(208) */
    volatile Uint32 cr2_0;
    /* Addr: h(D4), d(212) */
    volatile Uint32 cr2_1;
    /* Addr: h(D8), d(216) */
    volatile Uint32 cr3;
    /* Addr: h(DC), d(220) */
    volatile Uint32 cr4_0;
    /* Addr: h(E0), d(224) */
    volatile Uint32 cr4_1;
    /* Addr: h(E4), d(228) */
    volatile Uint32 cr5_0;
    /* Addr: h(E8), d(232) */
    volatile Uint32 cr5_1;
    /* Addr: h(EC), d(236) */
    volatile Uint32 jacob_op_0;
    /* Addr: h(F0), d(240) */
    volatile Uint32 jacob_op_1;
    /* Addr: h(F4), d(244) */
    volatile Uint32 simd_op_0;
    /* Addr: h(F8), d(248) */
    volatile Uint32 simd_op_1;
    /* Addr: h(FC), d(252) */
    volatile Uint32 lutfill_op;
    /* Addr: h(100), d(256) */
    volatile Uint32 ig_counters;
    /* Addr: h(104), d(260) */
    volatile Uint32 time_reg;
    /* Addr: h(108), d(264) */
    volatile Uint32 lutfill_main;
    /* Addr: h(10C), d(268) */
    volatile Uint32 lutfill_0;
    /* Addr: h(110), d(272) */
    volatile Uint32 lutfill_1;
    /* Addr: h(114), d(276) */
    volatile Uint32 lutfill_2;
    /* Addr: h(118), d(280) */
    volatile Uint32 cfp_broadcast_i_e;
    /* Addr: h(11C), d(284) */
    volatile Uint32 cfp_broadcast_q;
    /* Addr: h(120), d(288) */
    volatile Uint32 jg_master_i_e;
    /* Addr: h(124), d(292) */
    volatile Uint32 jg_master_q;
    /* Addr: h(128), d(296) */
    volatile Uint32 jg_column0_i_e;
    /* Addr: h(12C), d(300) */
    volatile Uint32 jg_column0_q;
    /* Addr: h(130), d(304) */
    volatile Uint32 jg_column1_i_e;
    /* Addr: h(134), d(308) */
    volatile Uint32 jg_column1_q;
    /* Addr: h(138), d(312) */
    volatile Uint32 jg_column2_i_e;
    /* Addr: h(13C), d(316) */
    volatile Uint32 jg_column2_q;
    /* Addr: h(140), d(320) */
    volatile Uint32 jg_column3_i_e;
    /* Addr: h(144), d(324) */
    volatile Uint32 jg_column3_q;
    /* Addr: h(148), d(328) */
    volatile Uint32 jg_column4_i_e;
    /* Addr: h(14C), d(332) */
    volatile Uint32 jg_column4_q;
    /* Addr: h(150), d(336) */
    volatile Uint32 jg_column5_i_e;
    /* Addr: h(154), d(340) */
    volatile Uint32 jg_column5_q;
    /* Addr: h(158), d(344) */
    volatile Uint32 jg_column6_i_e;
    /* Addr: h(15C), d(348) */
    volatile Uint32 jg_column6_q;
    /* Addr: h(160), d(352) */
    volatile Uint32 jg_column7_i_e;
    /* Addr: h(164), d(356) */
    volatile Uint32 jg_column7_q;
    /* Addr: h(168), d(360) */
    volatile Uint32 se_scalar_i_e;
    /* Addr: h(16C), d(364) */
    volatile Uint32 se_scalar_q;
    /* Addr: h(170), d(368) */
    volatile Uint32 se_lutfill_cfp0_i_e;
    /* Addr: h(174), d(372) */
    volatile Uint32 se_lutfill_cfp0_q;
    /* Addr: h(178), d(376) */
    volatile Uint32 se_lutfill_cfp1_i_e;
    /* Addr: h(17C), d(380) */
    volatile Uint32 se_lutfill_cfp1_q;
    /* Addr: h(180), d(384) */
    volatile Uint32 se_lutfill_cfp2_i_e;
    /* Addr: h(184), d(388) */
    volatile Uint32 se_lutfill_cfp2_q;
    /* Addr: h(188), d(392) */
    volatile Uint32 sc_mult_i_e;
    /* Addr: h(18C), d(396) */
    volatile Uint32 sc_mult_q;
    /* Addr: h(190), d(400) */
    volatile Uint32 sc_accum_i_e;
    /* Addr: h(194), d(404) */
    volatile Uint32 sc_accum_q;
    /* Addr: h(198), d(408) */
    volatile Uint32 sc_mag_i_e;
    /* Addr: h(19C), d(412) */
    volatile Uint32 dbg_addr_0;
    /* Addr: h(1A0), d(416) */
    volatile Uint32 dbg_addr_1;
    /* Addr: h(1A4), d(420) */
    volatile Uint32 rsvd3[23];
    /* Addr: h(200), d(512) */
    volatile CSL_DFE_DPDA_DPDA_SCALAR_REGS dpda_scalar[64];
    /* Addr: h(400), d(1024) */
    volatile Uint32 dpda_ig_regfile[55];
    /* Addr: h(4DC), d(1244) */
    volatile Uint32 dpda_ig_regfile_preg_radd;
    /* Addr: h(4E0), d(1248) */
    volatile Uint32 dpda_ig_regfile_preg_wadd;
    /* Addr: h(4E4), d(1252) */
    volatile Uint32 rsvd4[1];
    /* Addr: h(4E8), d(1256) */
    volatile Uint32 dpda_ig_regfile_dsp_status1;
    /* Addr: h(4EC), d(1260) */
    volatile Uint32 dpda_ig_regfile_immediate;
    /* Addr: h(4F0), d(1264) */
    volatile Uint32 dpda_ig_regfile_cb_status;
    /* Addr: h(4F4), d(1268) */
    volatile Uint32 dpda_ig_regfile_mask_adap;
    /* Addr: h(4F8), d(1272) */
    volatile Uint32 dpda_ig_regfile_dsp_param1;
    /* Addr: h(4FC), d(1276) */
    volatile Uint32 dpda_ig_regfile_dsp_param2;
    /* Addr: h(500), d(1280) */
    volatile Uint32 rsvd5[192];
    /* Addr: h(800), d(2048) */
    volatile Uint32 dpda_into_dpd4_ram0[256];
    /* Addr: h(C00), d(3072) */
    volatile Uint32 dpda_into_dpd4_ram1[256];
    /* Addr: h(1000), d(4096) */
    volatile Uint32 dpda_into_dpd4_ram2[256];
    /* Addr: h(1400), d(5120) */
    volatile Uint32 dpda_stack[64];
    /* Addr: h(1500), d(5376) */
    volatile Uint32 rsvd6[2752];
    /* Addr: h(4000), d(16384) */
    volatile Uint32 dpda_lut_master[2560];
    /* Addr: h(6800), d(26624) */
    volatile Uint32 rsvd7[1536];
    /* Addr: h(8000), d(32768) */
    volatile Uint32 dpda_lut_0[1024];
    /* Addr: h(9000), d(36864) */
    volatile Uint32 dpda_lut_1[1024];
    /* Addr: h(A000), d(40960) */
    volatile Uint32 dpda_lut_2[1024];
    /* Addr: h(B000), d(45056) */
    volatile Uint32 dpda_lut_3[1024];
    /* Addr: h(C000), d(49152) */
    volatile Uint32 dpda_lut_4[1024];
    /* Addr: h(D000), d(53248) */
    volatile Uint32 dpda_lut_5[1024];
    /* Addr: h(E000), d(57344) */
    volatile Uint32 dpda_lut_6[1024];
    /* Addr: h(F000), d(61440) */
    volatile Uint32 dpda_lut_7[1024];
    /* Addr: h(10000), d(65536) */
    volatile Uint32 dpda_iram[8192];
    /* Addr: h(18000), d(98304) */
    volatile Uint32 rsvd8[40960];
    /* Addr: h(40000), d(262144) */
    volatile CSL_DFE_DPDA_DPDA_PREG_000_REGS dpda_preg_000[24];
    /* Addr: h(400C0), d(262336) */
    volatile Uint32 rsvd9[16];
    /* Addr: h(40100), d(262400) */
    volatile CSL_DFE_DPDA_DPDA_PREG_001_REGS dpda_preg_001[24];
    /* Addr: h(401C0), d(262592) */
    volatile Uint32 rsvd10[16];
    /* Addr: h(40200), d(262656) */
    volatile CSL_DFE_DPDA_DPDA_PREG_002_REGS dpda_preg_002[24];
    /* Addr: h(402C0), d(262848) */
    volatile Uint32 rsvd11[16];
    /* Addr: h(40300), d(262912) */
    volatile CSL_DFE_DPDA_DPDA_PREG_003_REGS dpda_preg_003[24];
    /* Addr: h(403C0), d(263104) */
    volatile Uint32 rsvd12[16];
    /* Addr: h(40400), d(263168) */
    volatile CSL_DFE_DPDA_DPDA_PREG_004_REGS dpda_preg_004[24];
    /* Addr: h(404C0), d(263360) */
    volatile Uint32 rsvd13[16];
    /* Addr: h(40500), d(263424) */
    volatile CSL_DFE_DPDA_DPDA_PREG_005_REGS dpda_preg_005[24];
    /* Addr: h(405C0), d(263616) */
    volatile Uint32 rsvd14[16];
    /* Addr: h(40600), d(263680) */
    volatile CSL_DFE_DPDA_DPDA_PREG_006_REGS dpda_preg_006[24];
    /* Addr: h(406C0), d(263872) */
    volatile Uint32 rsvd15[16];
    /* Addr: h(40700), d(263936) */
    volatile CSL_DFE_DPDA_DPDA_PREG_007_REGS dpda_preg_007[24];
    /* Addr: h(407C0), d(264128) */
    volatile Uint32 rsvd16[16];
    /* Addr: h(40800), d(264192) */
    volatile CSL_DFE_DPDA_DPDA_PREG_008_REGS dpda_preg_008[24];
    /* Addr: h(408C0), d(264384) */
    volatile Uint32 rsvd17[16];
    /* Addr: h(40900), d(264448) */
    volatile CSL_DFE_DPDA_DPDA_PREG_009_REGS dpda_preg_009[24];
    /* Addr: h(409C0), d(264640) */
    volatile Uint32 rsvd18[16];
    /* Addr: h(40A00), d(264704) */
    volatile CSL_DFE_DPDA_DPDA_PREG_010_REGS dpda_preg_010[24];
    /* Addr: h(40AC0), d(264896) */
    volatile Uint32 rsvd19[16];
    /* Addr: h(40B00), d(264960) */
    volatile CSL_DFE_DPDA_DPDA_PREG_011_REGS dpda_preg_011[24];
    /* Addr: h(40BC0), d(265152) */
    volatile Uint32 rsvd20[16];
    /* Addr: h(40C00), d(265216) */
    volatile CSL_DFE_DPDA_DPDA_PREG_012_REGS dpda_preg_012[24];
    /* Addr: h(40CC0), d(265408) */
    volatile Uint32 rsvd21[16];
    /* Addr: h(40D00), d(265472) */
    volatile CSL_DFE_DPDA_DPDA_PREG_013_REGS dpda_preg_013[24];
    /* Addr: h(40DC0), d(265664) */
    volatile Uint32 rsvd22[16];
    /* Addr: h(40E00), d(265728) */
    volatile CSL_DFE_DPDA_DPDA_PREG_014_REGS dpda_preg_014[24];
    /* Addr: h(40EC0), d(265920) */
    volatile Uint32 rsvd23[16];
    /* Addr: h(40F00), d(265984) */
    volatile CSL_DFE_DPDA_DPDA_PREG_015_REGS dpda_preg_015[24];
    /* Addr: h(40FC0), d(266176) */
    volatile Uint32 rsvd24[16];
    /* Addr: h(41000), d(266240) */
    volatile CSL_DFE_DPDA_DPDA_PREG_016_REGS dpda_preg_016[24];
    /* Addr: h(410C0), d(266432) */
    volatile Uint32 rsvd25[16];
    /* Addr: h(41100), d(266496) */
    volatile CSL_DFE_DPDA_DPDA_PREG_017_REGS dpda_preg_017[24];
    /* Addr: h(411C0), d(266688) */
    volatile Uint32 rsvd26[16];
    /* Addr: h(41200), d(266752) */
    volatile CSL_DFE_DPDA_DPDA_PREG_018_REGS dpda_preg_018[24];
    /* Addr: h(412C0), d(266944) */
    volatile Uint32 rsvd27[16];
    /* Addr: h(41300), d(267008) */
    volatile CSL_DFE_DPDA_DPDA_PREG_019_REGS dpda_preg_019[24];
    /* Addr: h(413C0), d(267200) */
    volatile Uint32 rsvd28[16];
    /* Addr: h(41400), d(267264) */
    volatile CSL_DFE_DPDA_DPDA_PREG_020_REGS dpda_preg_020[24];
    /* Addr: h(414C0), d(267456) */
    volatile Uint32 rsvd29[16];
    /* Addr: h(41500), d(267520) */
    volatile CSL_DFE_DPDA_DPDA_PREG_021_REGS dpda_preg_021[24];
    /* Addr: h(415C0), d(267712) */
    volatile Uint32 rsvd30[16];
    /* Addr: h(41600), d(267776) */
    volatile CSL_DFE_DPDA_DPDA_PREG_022_REGS dpda_preg_022[24];
    /* Addr: h(416C0), d(267968) */
    volatile Uint32 rsvd31[16];
    /* Addr: h(41700), d(268032) */
    volatile CSL_DFE_DPDA_DPDA_PREG_023_REGS dpda_preg_023[24];
    /* Addr: h(417C0), d(268224) */
    volatile Uint32 rsvd32[16];
    /* Addr: h(41800), d(268288) */
    volatile CSL_DFE_DPDA_DPDA_PREG_024_REGS dpda_preg_024[24];
    /* Addr: h(418C0), d(268480) */
    volatile Uint32 rsvd33[16];
    /* Addr: h(41900), d(268544) */
    volatile CSL_DFE_DPDA_DPDA_PREG_025_REGS dpda_preg_025[24];
    /* Addr: h(419C0), d(268736) */
    volatile Uint32 rsvd34[16];
    /* Addr: h(41A00), d(268800) */
    volatile CSL_DFE_DPDA_DPDA_PREG_026_REGS dpda_preg_026[24];
    /* Addr: h(41AC0), d(268992) */
    volatile Uint32 rsvd35[16];
    /* Addr: h(41B00), d(269056) */
    volatile CSL_DFE_DPDA_DPDA_PREG_027_REGS dpda_preg_027[24];
    /* Addr: h(41BC0), d(269248) */
    volatile Uint32 rsvd36[16];
    /* Addr: h(41C00), d(269312) */
    volatile CSL_DFE_DPDA_DPDA_PREG_028_REGS dpda_preg_028[24];
    /* Addr: h(41CC0), d(269504) */
    volatile Uint32 rsvd37[16];
    /* Addr: h(41D00), d(269568) */
    volatile CSL_DFE_DPDA_DPDA_PREG_029_REGS dpda_preg_029[24];
    /* Addr: h(41DC0), d(269760) */
    volatile Uint32 rsvd38[16];
    /* Addr: h(41E00), d(269824) */
    volatile CSL_DFE_DPDA_DPDA_PREG_030_REGS dpda_preg_030[24];
    /* Addr: h(41EC0), d(270016) */
    volatile Uint32 rsvd39[16];
    /* Addr: h(41F00), d(270080) */
    volatile CSL_DFE_DPDA_DPDA_PREG_031_REGS dpda_preg_031[24];
    /* Addr: h(41FC0), d(270272) */
    volatile Uint32 rsvd40[16];
    /* Addr: h(42000), d(270336) */
    volatile CSL_DFE_DPDA_DPDA_PREG_032_REGS dpda_preg_032[24];
    /* Addr: h(420C0), d(270528) */
    volatile Uint32 rsvd41[16];
    /* Addr: h(42100), d(270592) */
    volatile CSL_DFE_DPDA_DPDA_PREG_033_REGS dpda_preg_033[24];
    /* Addr: h(421C0), d(270784) */
    volatile Uint32 rsvd42[16];
    /* Addr: h(42200), d(270848) */
    volatile CSL_DFE_DPDA_DPDA_PREG_034_REGS dpda_preg_034[24];
    /* Addr: h(422C0), d(271040) */
    volatile Uint32 rsvd43[16];
    /* Addr: h(42300), d(271104) */
    volatile CSL_DFE_DPDA_DPDA_PREG_035_REGS dpda_preg_035[24];
    /* Addr: h(423C0), d(271296) */
    volatile Uint32 rsvd44[16];
    /* Addr: h(42400), d(271360) */
    volatile CSL_DFE_DPDA_DPDA_PREG_036_REGS dpda_preg_036[24];
    /* Addr: h(424C0), d(271552) */
    volatile Uint32 rsvd45[16];
    /* Addr: h(42500), d(271616) */
    volatile CSL_DFE_DPDA_DPDA_PREG_037_REGS dpda_preg_037[24];
    /* Addr: h(425C0), d(271808) */
    volatile Uint32 rsvd46[16];
    /* Addr: h(42600), d(271872) */
    volatile CSL_DFE_DPDA_DPDA_PREG_038_REGS dpda_preg_038[24];
    /* Addr: h(426C0), d(272064) */
    volatile Uint32 rsvd47[16];
    /* Addr: h(42700), d(272128) */
    volatile CSL_DFE_DPDA_DPDA_PREG_039_REGS dpda_preg_039[24];
    /* Addr: h(427C0), d(272320) */
    volatile Uint32 rsvd48[16];
    /* Addr: h(42800), d(272384) */
    volatile CSL_DFE_DPDA_DPDA_PREG_040_REGS dpda_preg_040[24];
    /* Addr: h(428C0), d(272576) */
    volatile Uint32 rsvd49[16];
    /* Addr: h(42900), d(272640) */
    volatile CSL_DFE_DPDA_DPDA_PREG_041_REGS dpda_preg_041[24];
    /* Addr: h(429C0), d(272832) */
    volatile Uint32 rsvd50[16];
    /* Addr: h(42A00), d(272896) */
    volatile CSL_DFE_DPDA_DPDA_PREG_042_REGS dpda_preg_042[24];
    /* Addr: h(42AC0), d(273088) */
    volatile Uint32 rsvd51[16];
    /* Addr: h(42B00), d(273152) */
    volatile CSL_DFE_DPDA_DPDA_PREG_043_REGS dpda_preg_043[24];
    /* Addr: h(42BC0), d(273344) */
    volatile Uint32 rsvd52[16];
    /* Addr: h(42C00), d(273408) */
    volatile CSL_DFE_DPDA_DPDA_PREG_044_REGS dpda_preg_044[24];
    /* Addr: h(42CC0), d(273600) */
    volatile Uint32 rsvd53[16];
    /* Addr: h(42D00), d(273664) */
    volatile CSL_DFE_DPDA_DPDA_PREG_045_REGS dpda_preg_045[24];
    /* Addr: h(42DC0), d(273856) */
    volatile Uint32 rsvd54[16];
    /* Addr: h(42E00), d(273920) */
    volatile CSL_DFE_DPDA_DPDA_PREG_046_REGS dpda_preg_046[24];
    /* Addr: h(42EC0), d(274112) */
    volatile Uint32 rsvd55[16];
    /* Addr: h(42F00), d(274176) */
    volatile CSL_DFE_DPDA_DPDA_PREG_047_REGS dpda_preg_047[24];
    /* Addr: h(42FC0), d(274368) */
    volatile Uint32 rsvd56[16];
    /* Addr: h(43000), d(274432) */
    volatile CSL_DFE_DPDA_DPDA_PREG_048_REGS dpda_preg_048[24];
    /* Addr: h(430C0), d(274624) */
    volatile Uint32 rsvd57[16];
    /* Addr: h(43100), d(274688) */
    volatile CSL_DFE_DPDA_DPDA_PREG_049_REGS dpda_preg_049[24];
    /* Addr: h(431C0), d(274880) */
    volatile Uint32 rsvd58[16];
    /* Addr: h(43200), d(274944) */
    volatile CSL_DFE_DPDA_DPDA_PREG_050_REGS dpda_preg_050[24];
    /* Addr: h(432C0), d(275136) */
    volatile Uint32 rsvd59[16];
    /* Addr: h(43300), d(275200) */
    volatile CSL_DFE_DPDA_DPDA_PREG_051_REGS dpda_preg_051[24];
    /* Addr: h(433C0), d(275392) */
    volatile Uint32 rsvd60[16];
    /* Addr: h(43400), d(275456) */
    volatile CSL_DFE_DPDA_DPDA_PREG_052_REGS dpda_preg_052[24];
    /* Addr: h(434C0), d(275648) */
    volatile Uint32 rsvd61[16];
    /* Addr: h(43500), d(275712) */
    volatile CSL_DFE_DPDA_DPDA_PREG_053_REGS dpda_preg_053[24];
    /* Addr: h(435C0), d(275904) */
    volatile Uint32 rsvd62[16];
    /* Addr: h(43600), d(275968) */
    volatile CSL_DFE_DPDA_DPDA_PREG_054_REGS dpda_preg_054[24];
    /* Addr: h(436C0), d(276160) */
    volatile Uint32 rsvd63[16];
    /* Addr: h(43700), d(276224) */
    volatile CSL_DFE_DPDA_DPDA_PREG_055_REGS dpda_preg_055[24];
    /* Addr: h(437C0), d(276416) */
    volatile Uint32 rsvd64[16];
    /* Addr: h(43800), d(276480) */
    volatile CSL_DFE_DPDA_DPDA_PREG_056_REGS dpda_preg_056[24];
    /* Addr: h(438C0), d(276672) */
    volatile Uint32 rsvd65[16];
    /* Addr: h(43900), d(276736) */
    volatile CSL_DFE_DPDA_DPDA_PREG_057_REGS dpda_preg_057[24];
    /* Addr: h(439C0), d(276928) */
    volatile Uint32 rsvd66[16];
    /* Addr: h(43A00), d(276992) */
    volatile CSL_DFE_DPDA_DPDA_PREG_058_REGS dpda_preg_058[24];
    /* Addr: h(43AC0), d(277184) */
    volatile Uint32 rsvd67[16];
    /* Addr: h(43B00), d(277248) */
    volatile CSL_DFE_DPDA_DPDA_PREG_059_REGS dpda_preg_059[24];
    /* Addr: h(43BC0), d(277440) */
    volatile Uint32 rsvd68[16];
    /* Addr: h(43C00), d(277504) */
    volatile CSL_DFE_DPDA_DPDA_PREG_060_REGS dpda_preg_060[24];
    /* Addr: h(43CC0), d(277696) */
    volatile Uint32 rsvd69[16];
    /* Addr: h(43D00), d(277760) */
    volatile CSL_DFE_DPDA_DPDA_PREG_061_REGS dpda_preg_061[24];
    /* Addr: h(43DC0), d(277952) */
    volatile Uint32 rsvd70[16];
    /* Addr: h(43E00), d(278016) */
    volatile CSL_DFE_DPDA_DPDA_PREG_062_REGS dpda_preg_062[24];
    /* Addr: h(43EC0), d(278208) */
    volatile Uint32 rsvd71[16];
    /* Addr: h(43F00), d(278272) */
    volatile CSL_DFE_DPDA_DPDA_PREG_063_REGS dpda_preg_063[24];
    /* Addr: h(43FC0), d(278464) */
    volatile Uint32 rsvd72[16];
    /* Addr: h(44000), d(278528) */
    volatile CSL_DFE_DPDA_DPDA_PREG_064_REGS dpda_preg_064[24];
    /* Addr: h(440C0), d(278720) */
    volatile Uint32 rsvd73[16];
    /* Addr: h(44100), d(278784) */
    volatile CSL_DFE_DPDA_DPDA_PREG_065_REGS dpda_preg_065[24];
    /* Addr: h(441C0), d(278976) */
    volatile Uint32 rsvd74[16];
    /* Addr: h(44200), d(279040) */
    volatile CSL_DFE_DPDA_DPDA_PREG_066_REGS dpda_preg_066[24];
    /* Addr: h(442C0), d(279232) */
    volatile Uint32 rsvd75[16];
    /* Addr: h(44300), d(279296) */
    volatile CSL_DFE_DPDA_DPDA_PREG_067_REGS dpda_preg_067[24];
    /* Addr: h(443C0), d(279488) */
    volatile Uint32 rsvd76[16];
    /* Addr: h(44400), d(279552) */
    volatile CSL_DFE_DPDA_DPDA_PREG_068_REGS dpda_preg_068[24];
    /* Addr: h(444C0), d(279744) */
    volatile Uint32 rsvd77[16];
    /* Addr: h(44500), d(279808) */
    volatile CSL_DFE_DPDA_DPDA_PREG_069_REGS dpda_preg_069[24];
    /* Addr: h(445C0), d(280000) */
    volatile Uint32 rsvd78[16];
    /* Addr: h(44600), d(280064) */
    volatile CSL_DFE_DPDA_DPDA_PREG_070_REGS dpda_preg_070[24];
    /* Addr: h(446C0), d(280256) */
    volatile Uint32 rsvd79[16];
    /* Addr: h(44700), d(280320) */
    volatile CSL_DFE_DPDA_DPDA_PREG_071_REGS dpda_preg_071[24];
    /* Addr: h(447C0), d(280512) */
    volatile Uint32 rsvd80[16];
    /* Addr: h(44800), d(280576) */
    volatile CSL_DFE_DPDA_DPDA_PREG_072_REGS dpda_preg_072[24];
    /* Addr: h(448C0), d(280768) */
    volatile Uint32 rsvd81[16];
    /* Addr: h(44900), d(280832) */
    volatile CSL_DFE_DPDA_DPDA_PREG_073_REGS dpda_preg_073[24];
    /* Addr: h(449C0), d(281024) */
    volatile Uint32 rsvd82[16];
    /* Addr: h(44A00), d(281088) */
    volatile CSL_DFE_DPDA_DPDA_PREG_074_REGS dpda_preg_074[24];
    /* Addr: h(44AC0), d(281280) */
    volatile Uint32 rsvd83[16];
    /* Addr: h(44B00), d(281344) */
    volatile CSL_DFE_DPDA_DPDA_PREG_075_REGS dpda_preg_075[24];
    /* Addr: h(44BC0), d(281536) */
    volatile Uint32 rsvd84[16];
    /* Addr: h(44C00), d(281600) */
    volatile CSL_DFE_DPDA_DPDA_PREG_076_REGS dpda_preg_076[24];
    /* Addr: h(44CC0), d(281792) */
    volatile Uint32 rsvd85[16];
    /* Addr: h(44D00), d(281856) */
    volatile CSL_DFE_DPDA_DPDA_PREG_077_REGS dpda_preg_077[24];
    /* Addr: h(44DC0), d(282048) */
    volatile Uint32 rsvd86[16];
    /* Addr: h(44E00), d(282112) */
    volatile CSL_DFE_DPDA_DPDA_PREG_078_REGS dpda_preg_078[24];
    /* Addr: h(44EC0), d(282304) */
    volatile Uint32 rsvd87[16];
    /* Addr: h(44F00), d(282368) */
    volatile CSL_DFE_DPDA_DPDA_PREG_079_REGS dpda_preg_079[24];
    /* Addr: h(44FC0), d(282560) */
    volatile Uint32 rsvd88[16];
    /* Addr: h(45000), d(282624) */
    volatile CSL_DFE_DPDA_DPDA_PREG_080_REGS dpda_preg_080[24];
    /* Addr: h(450C0), d(282816) */
    volatile Uint32 rsvd89[16];
    /* Addr: h(45100), d(282880) */
    volatile CSL_DFE_DPDA_DPDA_PREG_081_REGS dpda_preg_081[24];
    /* Addr: h(451C0), d(283072) */
    volatile Uint32 rsvd90[16];
    /* Addr: h(45200), d(283136) */
    volatile CSL_DFE_DPDA_DPDA_PREG_082_REGS dpda_preg_082[24];
    /* Addr: h(452C0), d(283328) */
    volatile Uint32 rsvd91[16];
    /* Addr: h(45300), d(283392) */
    volatile CSL_DFE_DPDA_DPDA_PREG_083_REGS dpda_preg_083[24];
    /* Addr: h(453C0), d(283584) */
    volatile Uint32 rsvd92[16];
    /* Addr: h(45400), d(283648) */
    volatile CSL_DFE_DPDA_DPDA_PREG_084_REGS dpda_preg_084[24];
    /* Addr: h(454C0), d(283840) */
    volatile Uint32 rsvd93[16];
    /* Addr: h(45500), d(283904) */
    volatile CSL_DFE_DPDA_DPDA_PREG_085_REGS dpda_preg_085[24];
    /* Addr: h(455C0), d(284096) */
    volatile Uint32 rsvd94[16];
    /* Addr: h(45600), d(284160) */
    volatile CSL_DFE_DPDA_DPDA_PREG_086_REGS dpda_preg_086[24];
    /* Addr: h(456C0), d(284352) */
    volatile Uint32 rsvd95[16];
    /* Addr: h(45700), d(284416) */
    volatile CSL_DFE_DPDA_DPDA_PREG_087_REGS dpda_preg_087[24];
    /* Addr: h(457C0), d(284608) */
    volatile Uint32 rsvd96[16];
    /* Addr: h(45800), d(284672) */
    volatile CSL_DFE_DPDA_DPDA_PREG_088_REGS dpda_preg_088[24];
    /* Addr: h(458C0), d(284864) */
    volatile Uint32 rsvd97[16];
    /* Addr: h(45900), d(284928) */
    volatile CSL_DFE_DPDA_DPDA_PREG_089_REGS dpda_preg_089[24];
    /* Addr: h(459C0), d(285120) */
    volatile Uint32 rsvd98[16];
    /* Addr: h(45A00), d(285184) */
    volatile CSL_DFE_DPDA_DPDA_PREG_090_REGS dpda_preg_090[24];
    /* Addr: h(45AC0), d(285376) */
    volatile Uint32 rsvd99[16];
    /* Addr: h(45B00), d(285440) */
    volatile CSL_DFE_DPDA_DPDA_PREG_091_REGS dpda_preg_091[24];
    /* Addr: h(45BC0), d(285632) */
    volatile Uint32 rsvd100[16];
    /* Addr: h(45C00), d(285696) */
    volatile CSL_DFE_DPDA_DPDA_PREG_092_REGS dpda_preg_092[24];
    /* Addr: h(45CC0), d(285888) */
    volatile Uint32 rsvd101[16];
    /* Addr: h(45D00), d(285952) */
    volatile CSL_DFE_DPDA_DPDA_PREG_093_REGS dpda_preg_093[24];
    /* Addr: h(45DC0), d(286144) */
    volatile Uint32 rsvd102[16];
    /* Addr: h(45E00), d(286208) */
    volatile CSL_DFE_DPDA_DPDA_PREG_094_REGS dpda_preg_094[24];
    /* Addr: h(45EC0), d(286400) */
    volatile Uint32 rsvd103[16];
    /* Addr: h(45F00), d(286464) */
    volatile CSL_DFE_DPDA_DPDA_PREG_095_REGS dpda_preg_095[24];
    /* Addr: h(45FC0), d(286656) */
    volatile Uint32 rsvd104[16];
    /* Addr: h(46000), d(286720) */
    volatile CSL_DFE_DPDA_DPDA_PREG_096_REGS dpda_preg_096[24];
    /* Addr: h(460C0), d(286912) */
    volatile Uint32 rsvd105[16];
    /* Addr: h(46100), d(286976) */
    volatile CSL_DFE_DPDA_DPDA_PREG_097_REGS dpda_preg_097[24];
    /* Addr: h(461C0), d(287168) */
    volatile Uint32 rsvd106[16];
    /* Addr: h(46200), d(287232) */
    volatile CSL_DFE_DPDA_DPDA_PREG_098_REGS dpda_preg_098[24];
    /* Addr: h(462C0), d(287424) */
    volatile Uint32 rsvd107[16];
    /* Addr: h(46300), d(287488) */
    volatile CSL_DFE_DPDA_DPDA_PREG_099_REGS dpda_preg_099[24];
    /* Addr: h(463C0), d(287680) */
    volatile Uint32 rsvd108[16];
    /* Addr: h(46400), d(287744) */
    volatile CSL_DFE_DPDA_DPDA_PREG_100_REGS dpda_preg_100[24];
    /* Addr: h(464C0), d(287936) */
    volatile Uint32 rsvd109[16];
    /* Addr: h(46500), d(288000) */
    volatile CSL_DFE_DPDA_DPDA_PREG_101_REGS dpda_preg_101[24];
    /* Addr: h(465C0), d(288192) */
    volatile Uint32 rsvd110[16];
    /* Addr: h(46600), d(288256) */
    volatile CSL_DFE_DPDA_DPDA_PREG_102_REGS dpda_preg_102[24];
    /* Addr: h(466C0), d(288448) */
    volatile Uint32 rsvd111[16];
    /* Addr: h(46700), d(288512) */
    volatile CSL_DFE_DPDA_DPDA_PREG_103_REGS dpda_preg_103[24];
    /* Addr: h(467C0), d(288704) */
    volatile Uint32 rsvd112[16];
    /* Addr: h(46800), d(288768) */
    volatile CSL_DFE_DPDA_DPDA_PREG_104_REGS dpda_preg_104[24];
    /* Addr: h(468C0), d(288960) */
    volatile Uint32 rsvd113[16];
    /* Addr: h(46900), d(289024) */
    volatile CSL_DFE_DPDA_DPDA_PREG_105_REGS dpda_preg_105[24];
    /* Addr: h(469C0), d(289216) */
    volatile Uint32 rsvd114[16];
    /* Addr: h(46A00), d(289280) */
    volatile CSL_DFE_DPDA_DPDA_PREG_106_REGS dpda_preg_106[24];
    /* Addr: h(46AC0), d(289472) */
    volatile Uint32 rsvd115[16];
    /* Addr: h(46B00), d(289536) */
    volatile CSL_DFE_DPDA_DPDA_PREG_107_REGS dpda_preg_107[24];
    /* Addr: h(46BC0), d(289728) */
    volatile Uint32 rsvd116[16];
    /* Addr: h(46C00), d(289792) */
    volatile CSL_DFE_DPDA_DPDA_PREG_108_REGS dpda_preg_108[24];
    /* Addr: h(46CC0), d(289984) */
    volatile Uint32 rsvd117[16];
    /* Addr: h(46D00), d(290048) */
    volatile CSL_DFE_DPDA_DPDA_PREG_109_REGS dpda_preg_109[24];
    /* Addr: h(46DC0), d(290240) */
    volatile Uint32 rsvd118[16];
    /* Addr: h(46E00), d(290304) */
    volatile CSL_DFE_DPDA_DPDA_PREG_110_REGS dpda_preg_110[24];
    /* Addr: h(46EC0), d(290496) */
    volatile Uint32 rsvd119[16];
    /* Addr: h(46F00), d(290560) */
    volatile CSL_DFE_DPDA_DPDA_PREG_111_REGS dpda_preg_111[24];
    /* Addr: h(46FC0), d(290752) */
    volatile Uint32 rsvd120[16];
    /* Addr: h(47000), d(290816) */
    volatile CSL_DFE_DPDA_DPDA_PREG_112_REGS dpda_preg_112[24];
    /* Addr: h(470C0), d(291008) */
    volatile Uint32 rsvd121[16];
    /* Addr: h(47100), d(291072) */
    volatile CSL_DFE_DPDA_DPDA_PREG_113_REGS dpda_preg_113[24];
    /* Addr: h(471C0), d(291264) */
    volatile Uint32 rsvd122[16];
    /* Addr: h(47200), d(291328) */
    volatile CSL_DFE_DPDA_DPDA_PREG_114_REGS dpda_preg_114[24];
    /* Addr: h(472C0), d(291520) */
    volatile Uint32 rsvd123[16];
    /* Addr: h(47300), d(291584) */
    volatile CSL_DFE_DPDA_DPDA_PREG_115_REGS dpda_preg_115[24];
    /* Addr: h(473C0), d(291776) */
    volatile Uint32 rsvd124[16];
    /* Addr: h(47400), d(291840) */
    volatile CSL_DFE_DPDA_DPDA_PREG_116_REGS dpda_preg_116[24];
    /* Addr: h(474C0), d(292032) */
    volatile Uint32 rsvd125[16];
    /* Addr: h(47500), d(292096) */
    volatile CSL_DFE_DPDA_DPDA_PREG_117_REGS dpda_preg_117[24];
    /* Addr: h(475C0), d(292288) */
    volatile Uint32 rsvd126[16];
    /* Addr: h(47600), d(292352) */
    volatile CSL_DFE_DPDA_DPDA_PREG_118_REGS dpda_preg_118[24];
    /* Addr: h(476C0), d(292544) */
    volatile Uint32 rsvd127[16];
    /* Addr: h(47700), d(292608) */
    volatile CSL_DFE_DPDA_DPDA_PREG_119_REGS dpda_preg_119[24];
    /* Addr: h(477C0), d(292800) */
    volatile Uint32 rsvd128[16];
    /* Addr: h(47800), d(292864) */
    volatile CSL_DFE_DPDA_DPDA_PREG_120_REGS dpda_preg_120[24];
    /* Addr: h(478C0), d(293056) */
    volatile Uint32 rsvd129[16];
    /* Addr: h(47900), d(293120) */
    volatile CSL_DFE_DPDA_DPDA_PREG_121_REGS dpda_preg_121[24];
    /* Addr: h(479C0), d(293312) */
    volatile Uint32 rsvd130[16];
    /* Addr: h(47A00), d(293376) */
    volatile CSL_DFE_DPDA_DPDA_PREG_122_REGS dpda_preg_122[24];
    /* Addr: h(47AC0), d(293568) */
    volatile Uint32 rsvd131[16];
    /* Addr: h(47B00), d(293632) */
    volatile CSL_DFE_DPDA_DPDA_PREG_123_REGS dpda_preg_123[24];
    /* Addr: h(47BC0), d(293824) */
    volatile Uint32 rsvd132[16];
    /* Addr: h(47C00), d(293888) */
    volatile CSL_DFE_DPDA_DPDA_PREG_124_REGS dpda_preg_124[24];
    /* Addr: h(47CC0), d(294080) */
    volatile Uint32 rsvd133[16];
    /* Addr: h(47D00), d(294144) */
    volatile CSL_DFE_DPDA_DPDA_PREG_125_REGS dpda_preg_125[24];
    /* Addr: h(47DC0), d(294336) */
    volatile Uint32 rsvd134[16];
    /* Addr: h(47E00), d(294400) */
    volatile CSL_DFE_DPDA_DPDA_PREG_126_REGS dpda_preg_126[24];
    /* Addr: h(47EC0), d(294592) */
    volatile Uint32 rsvd135[16];
    /* Addr: h(47F00), d(294656) */
    volatile CSL_DFE_DPDA_DPDA_PREG_127_REGS dpda_preg_127[24];
    /* Addr: h(47FC0), d(294848) */
    volatile Uint32 rsvd136[16];
    /* Addr: h(48000), d(294912) */
    volatile CSL_DFE_DPDA_DPDA_PREG_128_REGS dpda_preg_128[24];
    /* Addr: h(480C0), d(295104) */
    volatile Uint32 rsvd137[16];
    /* Addr: h(48100), d(295168) */
    volatile CSL_DFE_DPDA_DPDA_PREG_129_REGS dpda_preg_129[24];
    /* Addr: h(481C0), d(295360) */
    volatile Uint32 rsvd138[16];
    /* Addr: h(48200), d(295424) */
    volatile CSL_DFE_DPDA_DPDA_PREG_130_REGS dpda_preg_130[24];
    /* Addr: h(482C0), d(295616) */
    volatile Uint32 rsvd139[16];
    /* Addr: h(48300), d(295680) */
    volatile CSL_DFE_DPDA_DPDA_PREG_131_REGS dpda_preg_131[24];
    /* Addr: h(483C0), d(295872) */
    volatile Uint32 rsvd140[16];
    /* Addr: h(48400), d(295936) */
    volatile CSL_DFE_DPDA_DPDA_PREG_132_REGS dpda_preg_132[24];
    /* Addr: h(484C0), d(296128) */
    volatile Uint32 rsvd141[16];
    /* Addr: h(48500), d(296192) */
    volatile CSL_DFE_DPDA_DPDA_PREG_133_REGS dpda_preg_133[24];
    /* Addr: h(485C0), d(296384) */
    volatile Uint32 rsvd142[16];
    /* Addr: h(48600), d(296448) */
    volatile CSL_DFE_DPDA_DPDA_PREG_134_REGS dpda_preg_134[24];
    /* Addr: h(486C0), d(296640) */
    volatile Uint32 rsvd143[16];
    /* Addr: h(48700), d(296704) */
    volatile CSL_DFE_DPDA_DPDA_PREG_135_REGS dpda_preg_135[24];
    /* Addr: h(487C0), d(296896) */
    volatile Uint32 rsvd144[16];
    /* Addr: h(48800), d(296960) */
    volatile CSL_DFE_DPDA_DPDA_PREG_136_REGS dpda_preg_136[24];
    /* Addr: h(488C0), d(297152) */
    volatile Uint32 rsvd145[16];
    /* Addr: h(48900), d(297216) */
    volatile CSL_DFE_DPDA_DPDA_PREG_137_REGS dpda_preg_137[24];
    /* Addr: h(489C0), d(297408) */
    volatile Uint32 rsvd146[16];
    /* Addr: h(48A00), d(297472) */
    volatile CSL_DFE_DPDA_DPDA_PREG_138_REGS dpda_preg_138[24];
    /* Addr: h(48AC0), d(297664) */
    volatile Uint32 rsvd147[16];
    /* Addr: h(48B00), d(297728) */
    volatile CSL_DFE_DPDA_DPDA_PREG_139_REGS dpda_preg_139[24];
    /* Addr: h(48BC0), d(297920) */
    volatile Uint32 rsvd148[16];
    /* Addr: h(48C00), d(297984) */
    volatile CSL_DFE_DPDA_DPDA_PREG_140_REGS dpda_preg_140[24];
    /* Addr: h(48CC0), d(298176) */
    volatile Uint32 rsvd149[16];
    /* Addr: h(48D00), d(298240) */
    volatile CSL_DFE_DPDA_DPDA_PREG_141_REGS dpda_preg_141[24];
    /* Addr: h(48DC0), d(298432) */
    volatile Uint32 rsvd150[16];
    /* Addr: h(48E00), d(298496) */
    volatile CSL_DFE_DPDA_DPDA_PREG_142_REGS dpda_preg_142[24];
    /* Addr: h(48EC0), d(298688) */
    volatile Uint32 rsvd151[16];
    /* Addr: h(48F00), d(298752) */
    volatile CSL_DFE_DPDA_DPDA_PREG_143_REGS dpda_preg_143[24];
    /* Addr: h(48FC0), d(298944) */
    volatile Uint32 rsvd152[16];
    /* Addr: h(49000), d(299008) */
    volatile CSL_DFE_DPDA_DPDA_PREG_144_REGS dpda_preg_144[24];
    /* Addr: h(490C0), d(299200) */
    volatile Uint32 rsvd153[16];
    /* Addr: h(49100), d(299264) */
    volatile CSL_DFE_DPDA_DPDA_PREG_145_REGS dpda_preg_145[24];
    /* Addr: h(491C0), d(299456) */
    volatile Uint32 rsvd154[16];
    /* Addr: h(49200), d(299520) */
    volatile CSL_DFE_DPDA_DPDA_PREG_146_REGS dpda_preg_146[24];
    /* Addr: h(492C0), d(299712) */
    volatile Uint32 rsvd155[16];
    /* Addr: h(49300), d(299776) */
    volatile CSL_DFE_DPDA_DPDA_PREG_147_REGS dpda_preg_147[24];
    /* Addr: h(493C0), d(299968) */
    volatile Uint32 rsvd156[16];
    /* Addr: h(49400), d(300032) */
    volatile CSL_DFE_DPDA_DPDA_PREG_148_REGS dpda_preg_148[24];
    /* Addr: h(494C0), d(300224) */
    volatile Uint32 rsvd157[16];
    /* Addr: h(49500), d(300288) */
    volatile CSL_DFE_DPDA_DPDA_PREG_149_REGS dpda_preg_149[24];
    /* Addr: h(495C0), d(300480) */
    volatile Uint32 rsvd158[16];
    /* Addr: h(49600), d(300544) */
    volatile CSL_DFE_DPDA_DPDA_PREG_150_REGS dpda_preg_150[24];
    /* Addr: h(496C0), d(300736) */
    volatile Uint32 rsvd159[16];
    /* Addr: h(49700), d(300800) */
    volatile CSL_DFE_DPDA_DPDA_PREG_151_REGS dpda_preg_151[24];
    /* Addr: h(497C0), d(300992) */
    volatile Uint32 rsvd160[16];
    /* Addr: h(49800), d(301056) */
    volatile CSL_DFE_DPDA_DPDA_PREG_152_REGS dpda_preg_152[24];
    /* Addr: h(498C0), d(301248) */
    volatile Uint32 rsvd161[16];
    /* Addr: h(49900), d(301312) */
    volatile CSL_DFE_DPDA_DPDA_PREG_153_REGS dpda_preg_153[24];
    /* Addr: h(499C0), d(301504) */
    volatile Uint32 rsvd162[16];
    /* Addr: h(49A00), d(301568) */
    volatile CSL_DFE_DPDA_DPDA_PREG_154_REGS dpda_preg_154[24];
    /* Addr: h(49AC0), d(301760) */
    volatile Uint32 rsvd163[16];
    /* Addr: h(49B00), d(301824) */
    volatile CSL_DFE_DPDA_DPDA_PREG_155_REGS dpda_preg_155[24];
    /* Addr: h(49BC0), d(302016) */
    volatile Uint32 rsvd164[16];
    /* Addr: h(49C00), d(302080) */
    volatile CSL_DFE_DPDA_DPDA_PREG_156_REGS dpda_preg_156[24];
    /* Addr: h(49CC0), d(302272) */
    volatile Uint32 rsvd165[16];
    /* Addr: h(49D00), d(302336) */
    volatile CSL_DFE_DPDA_DPDA_PREG_157_REGS dpda_preg_157[24];
    /* Addr: h(49DC0), d(302528) */
    volatile Uint32 rsvd166[16];
    /* Addr: h(49E00), d(302592) */
    volatile CSL_DFE_DPDA_DPDA_PREG_158_REGS dpda_preg_158[24];
    /* Addr: h(49EC0), d(302784) */
    volatile Uint32 rsvd167[16];
    /* Addr: h(49F00), d(302848) */
    volatile CSL_DFE_DPDA_DPDA_PREG_159_REGS dpda_preg_159[24];
    /* Addr: h(49FC0), d(303040) */
    volatile Uint32 rsvd168[16];
    /* Addr: h(4A000), d(303104) */
    volatile CSL_DFE_DPDA_DPDA_PREG_160_REGS dpda_preg_160[24];
    /* Addr: h(4A0C0), d(303296) */
    volatile Uint32 rsvd169[16];
    /* Addr: h(4A100), d(303360) */
    volatile CSL_DFE_DPDA_DPDA_PREG_161_REGS dpda_preg_161[24];
    /* Addr: h(4A1C0), d(303552) */
    volatile Uint32 rsvd170[16];
    /* Addr: h(4A200), d(303616) */
    volatile CSL_DFE_DPDA_DPDA_PREG_162_REGS dpda_preg_162[24];
    /* Addr: h(4A2C0), d(303808) */
    volatile Uint32 rsvd171[16];
    /* Addr: h(4A300), d(303872) */
    volatile CSL_DFE_DPDA_DPDA_PREG_163_REGS dpda_preg_163[24];
    /* Addr: h(4A3C0), d(304064) */
    volatile Uint32 rsvd172[16];
    /* Addr: h(4A400), d(304128) */
    volatile CSL_DFE_DPDA_DPDA_PREG_164_REGS dpda_preg_164[24];
    /* Addr: h(4A4C0), d(304320) */
    volatile Uint32 rsvd173[16];
    /* Addr: h(4A500), d(304384) */
    volatile CSL_DFE_DPDA_DPDA_PREG_165_REGS dpda_preg_165[24];
    /* Addr: h(4A5C0), d(304576) */
    volatile Uint32 rsvd174[16];
    /* Addr: h(4A600), d(304640) */
    volatile CSL_DFE_DPDA_DPDA_PREG_166_REGS dpda_preg_166[24];
    /* Addr: h(4A6C0), d(304832) */
    volatile Uint32 rsvd175[16];
    /* Addr: h(4A700), d(304896) */
    volatile CSL_DFE_DPDA_DPDA_PREG_167_REGS dpda_preg_167[24];
    /* Addr: h(4A7C0), d(305088) */
    volatile Uint32 rsvd176[16];
    /* Addr: h(4A800), d(305152) */
    volatile CSL_DFE_DPDA_DPDA_PREG_168_REGS dpda_preg_168[24];
    /* Addr: h(4A8C0), d(305344) */
    volatile Uint32 rsvd177[16];
    /* Addr: h(4A900), d(305408) */
    volatile CSL_DFE_DPDA_DPDA_PREG_169_REGS dpda_preg_169[24];
    /* Addr: h(4A9C0), d(305600) */
    volatile Uint32 rsvd178[16];
    /* Addr: h(4AA00), d(305664) */
    volatile CSL_DFE_DPDA_DPDA_PREG_170_REGS dpda_preg_170[24];
    /* Addr: h(4AAC0), d(305856) */
    volatile Uint32 rsvd179[16];
    /* Addr: h(4AB00), d(305920) */
    volatile CSL_DFE_DPDA_DPDA_PREG_171_REGS dpda_preg_171[24];
    /* Addr: h(4ABC0), d(306112) */
    volatile Uint32 rsvd180[16];
    /* Addr: h(4AC00), d(306176) */
    volatile CSL_DFE_DPDA_DPDA_PREG_172_REGS dpda_preg_172[24];
    /* Addr: h(4ACC0), d(306368) */
    volatile Uint32 rsvd181[16];
    /* Addr: h(4AD00), d(306432) */
    volatile CSL_DFE_DPDA_DPDA_PREG_173_REGS dpda_preg_173[24];
    /* Addr: h(4ADC0), d(306624) */
    volatile Uint32 rsvd182[16];
    /* Addr: h(4AE00), d(306688) */
    volatile CSL_DFE_DPDA_DPDA_PREG_174_REGS dpda_preg_174[24];
    /* Addr: h(4AEC0), d(306880) */
    volatile Uint32 rsvd183[16];
    /* Addr: h(4AF00), d(306944) */
    volatile CSL_DFE_DPDA_DPDA_PREG_175_REGS dpda_preg_175[24];
    /* Addr: h(4AFC0), d(307136) */
    volatile Uint32 rsvd184[16];
    /* Addr: h(4B000), d(307200) */
    volatile CSL_DFE_DPDA_DPDA_PREG_176_REGS dpda_preg_176[24];
    /* Addr: h(4B0C0), d(307392) */
    volatile Uint32 rsvd185[16];
    /* Addr: h(4B100), d(307456) */
    volatile CSL_DFE_DPDA_DPDA_PREG_177_REGS dpda_preg_177[24];
    /* Addr: h(4B1C0), d(307648) */
    volatile Uint32 rsvd186[16];
    /* Addr: h(4B200), d(307712) */
    volatile CSL_DFE_DPDA_DPDA_PREG_178_REGS dpda_preg_178[24];
    /* Addr: h(4B2C0), d(307904) */
    volatile Uint32 rsvd187[16];
    /* Addr: h(4B300), d(307968) */
    volatile CSL_DFE_DPDA_DPDA_PREG_179_REGS dpda_preg_179[24];
    /* Addr: h(4B3C0), d(308160) */
    volatile Uint32 rsvd188[16];
    /* Addr: h(4B400), d(308224) */
    volatile CSL_DFE_DPDA_DPDA_PREG_180_REGS dpda_preg_180[24];
    /* Addr: h(4B4C0), d(308416) */
    volatile Uint32 rsvd189[16];
    /* Addr: h(4B500), d(308480) */
    volatile CSL_DFE_DPDA_DPDA_PREG_181_REGS dpda_preg_181[24];
    /* Addr: h(4B5C0), d(308672) */
    volatile Uint32 rsvd190[16];
    /* Addr: h(4B600), d(308736) */
    volatile CSL_DFE_DPDA_DPDA_PREG_182_REGS dpda_preg_182[24];
    /* Addr: h(4B6C0), d(308928) */
    volatile Uint32 rsvd191[16];
    /* Addr: h(4B700), d(308992) */
    volatile CSL_DFE_DPDA_DPDA_PREG_183_REGS dpda_preg_183[24];
    /* Addr: h(4B7C0), d(309184) */
    volatile Uint32 rsvd192[16];
    /* Addr: h(4B800), d(309248) */
    volatile CSL_DFE_DPDA_DPDA_PREG_184_REGS dpda_preg_184[24];
    /* Addr: h(4B8C0), d(309440) */
    volatile Uint32 rsvd193[16];
    /* Addr: h(4B900), d(309504) */
    volatile CSL_DFE_DPDA_DPDA_PREG_185_REGS dpda_preg_185[24];
    /* Addr: h(4B9C0), d(309696) */
    volatile Uint32 rsvd194[16];
    /* Addr: h(4BA00), d(309760) */
    volatile CSL_DFE_DPDA_DPDA_PREG_186_REGS dpda_preg_186[24];
    /* Addr: h(4BAC0), d(309952) */
    volatile Uint32 rsvd195[16];
    /* Addr: h(4BB00), d(310016) */
    volatile CSL_DFE_DPDA_DPDA_PREG_187_REGS dpda_preg_187[24];
    /* Addr: h(4BBC0), d(310208) */
    volatile Uint32 rsvd196[16];
    /* Addr: h(4BC00), d(310272) */
    volatile CSL_DFE_DPDA_DPDA_PREG_188_REGS dpda_preg_188[24];
    /* Addr: h(4BCC0), d(310464) */
    volatile Uint32 rsvd197[16];
    /* Addr: h(4BD00), d(310528) */
    volatile CSL_DFE_DPDA_DPDA_PREG_189_REGS dpda_preg_189[24];
    /* Addr: h(4BDC0), d(310720) */
    volatile Uint32 rsvd198[16];
    /* Addr: h(4BE00), d(310784) */
    volatile CSL_DFE_DPDA_DPDA_PREG_190_REGS dpda_preg_190[24];
    /* Addr: h(4BEC0), d(310976) */
    volatile Uint32 rsvd199[16];
    /* Addr: h(4BF00), d(311040) */
    volatile CSL_DFE_DPDA_DPDA_PREG_191_REGS dpda_preg_191[24];
    /* Addr: h(4BFC0), d(311232) */
    volatile Uint32 rsvd200[16];
    /* Addr: h(4C000), d(311296) */
    volatile CSL_DFE_DPDA_DPDA_PREG_192_REGS dpda_preg_192[24];
    /* Addr: h(4C0C0), d(311488) */
    volatile Uint32 rsvd201[16];
    /* Addr: h(4C100), d(311552) */
    volatile CSL_DFE_DPDA_DPDA_PREG_193_REGS dpda_preg_193[24];
    /* Addr: h(4C1C0), d(311744) */
    volatile Uint32 rsvd202[16];
    /* Addr: h(4C200), d(311808) */
    volatile CSL_DFE_DPDA_DPDA_PREG_194_REGS dpda_preg_194[24];
    /* Addr: h(4C2C0), d(312000) */
    volatile Uint32 rsvd203[16];
    /* Addr: h(4C300), d(312064) */
    volatile CSL_DFE_DPDA_DPDA_PREG_195_REGS dpda_preg_195[24];
    /* Addr: h(4C3C0), d(312256) */
    volatile Uint32 rsvd204[16];
    /* Addr: h(4C400), d(312320) */
    volatile CSL_DFE_DPDA_DPDA_PREG_196_REGS dpda_preg_196[24];
    /* Addr: h(4C4C0), d(312512) */
    volatile Uint32 rsvd205[16];
    /* Addr: h(4C500), d(312576) */
    volatile CSL_DFE_DPDA_DPDA_PREG_197_REGS dpda_preg_197[24];
    /* Addr: h(4C5C0), d(312768) */
    volatile Uint32 rsvd206[16];
    /* Addr: h(4C600), d(312832) */
    volatile CSL_DFE_DPDA_DPDA_PREG_198_REGS dpda_preg_198[24];
    /* Addr: h(4C6C0), d(313024) */
    volatile Uint32 rsvd207[16];
    /* Addr: h(4C700), d(313088) */
    volatile CSL_DFE_DPDA_DPDA_PREG_199_REGS dpda_preg_199[24];
    /* Addr: h(4C7C0), d(313280) */
    volatile Uint32 rsvd208[16];
    /* Addr: h(4C800), d(313344) */
    volatile CSL_DFE_DPDA_DPDA_PREG_200_REGS dpda_preg_200[24];
    /* Addr: h(4C8C0), d(313536) */
    volatile Uint32 rsvd209[16];
    /* Addr: h(4C900), d(313600) */
    volatile CSL_DFE_DPDA_DPDA_PREG_201_REGS dpda_preg_201[24];
    /* Addr: h(4C9C0), d(313792) */
    volatile Uint32 rsvd210[16];
    /* Addr: h(4CA00), d(313856) */
    volatile CSL_DFE_DPDA_DPDA_PREG_202_REGS dpda_preg_202[24];
    /* Addr: h(4CAC0), d(314048) */
    volatile Uint32 rsvd211[16];
    /* Addr: h(4CB00), d(314112) */
    volatile CSL_DFE_DPDA_DPDA_PREG_203_REGS dpda_preg_203[24];
    /* Addr: h(4CBC0), d(314304) */
    volatile Uint32 rsvd212[16];
    /* Addr: h(4CC00), d(314368) */
    volatile CSL_DFE_DPDA_DPDA_PREG_204_REGS dpda_preg_204[24];
    /* Addr: h(4CCC0), d(314560) */
    volatile Uint32 rsvd213[16];
    /* Addr: h(4CD00), d(314624) */
    volatile CSL_DFE_DPDA_DPDA_PREG_205_REGS dpda_preg_205[24];
    /* Addr: h(4CDC0), d(314816) */
    volatile Uint32 rsvd214[16];
    /* Addr: h(4CE00), d(314880) */
    volatile CSL_DFE_DPDA_DPDA_PREG_206_REGS dpda_preg_206[24];
    /* Addr: h(4CEC0), d(315072) */
    volatile Uint32 rsvd215[16];
    /* Addr: h(4CF00), d(315136) */
    volatile CSL_DFE_DPDA_DPDA_PREG_207_REGS dpda_preg_207[24];
    /* Addr: h(4CFC0), d(315328) */
    volatile Uint32 rsvd216[16];
    /* Addr: h(4D000), d(315392) */
    volatile CSL_DFE_DPDA_DPDA_PREG_208_REGS dpda_preg_208[24];
    /* Addr: h(4D0C0), d(315584) */
    volatile Uint32 rsvd217[16];
    /* Addr: h(4D100), d(315648) */
    volatile CSL_DFE_DPDA_DPDA_PREG_209_REGS dpda_preg_209[24];
    /* Addr: h(4D1C0), d(315840) */
    volatile Uint32 rsvd218[16];
    /* Addr: h(4D200), d(315904) */
    volatile CSL_DFE_DPDA_DPDA_PREG_210_REGS dpda_preg_210[24];
    /* Addr: h(4D2C0), d(316096) */
    volatile Uint32 rsvd219[16];
    /* Addr: h(4D300), d(316160) */
    volatile CSL_DFE_DPDA_DPDA_PREG_211_REGS dpda_preg_211[24];
    /* Addr: h(4D3C0), d(316352) */
    volatile Uint32 rsvd220[16];
    /* Addr: h(4D400), d(316416) */
    volatile CSL_DFE_DPDA_DPDA_PREG_212_REGS dpda_preg_212[24];
    /* Addr: h(4D4C0), d(316608) */
    volatile Uint32 rsvd221[16];
    /* Addr: h(4D500), d(316672) */
    volatile CSL_DFE_DPDA_DPDA_PREG_213_REGS dpda_preg_213[24];
    /* Addr: h(4D5C0), d(316864) */
    volatile Uint32 rsvd222[16];
    /* Addr: h(4D600), d(316928) */
    volatile CSL_DFE_DPDA_DPDA_PREG_214_REGS dpda_preg_214[24];
    /* Addr: h(4D6C0), d(317120) */
    volatile Uint32 rsvd223[16];
    /* Addr: h(4D700), d(317184) */
    volatile CSL_DFE_DPDA_DPDA_PREG_215_REGS dpda_preg_215[24];
    /* Addr: h(4D7C0), d(317376) */
    volatile Uint32 rsvd224[16];
    /* Addr: h(4D800), d(317440) */
    volatile CSL_DFE_DPDA_DPDA_PREG_216_REGS dpda_preg_216[24];
    /* Addr: h(4D8C0), d(317632) */
    volatile Uint32 rsvd225[16];
    /* Addr: h(4D900), d(317696) */
    volatile CSL_DFE_DPDA_DPDA_PREG_217_REGS dpda_preg_217[24];
    /* Addr: h(4D9C0), d(317888) */
    volatile Uint32 rsvd226[16];
    /* Addr: h(4DA00), d(317952) */
    volatile CSL_DFE_DPDA_DPDA_PREG_218_REGS dpda_preg_218[24];
    /* Addr: h(4DAC0), d(318144) */
    volatile Uint32 rsvd227[16];
    /* Addr: h(4DB00), d(318208) */
    volatile CSL_DFE_DPDA_DPDA_PREG_219_REGS dpda_preg_219[24];
    /* Addr: h(4DBC0), d(318400) */
    volatile Uint32 rsvd228[16];
    /* Addr: h(4DC00), d(318464) */
    volatile CSL_DFE_DPDA_DPDA_PREG_220_REGS dpda_preg_220[24];
    /* Addr: h(4DCC0), d(318656) */
    volatile Uint32 rsvd229[16];
    /* Addr: h(4DD00), d(318720) */
    volatile CSL_DFE_DPDA_DPDA_PREG_221_REGS dpda_preg_221[24];
    /* Addr: h(4DDC0), d(318912) */
    volatile Uint32 rsvd230[16];
    /* Addr: h(4DE00), d(318976) */
    volatile CSL_DFE_DPDA_DPDA_PREG_222_REGS dpda_preg_222[24];
    /* Addr: h(4DEC0), d(319168) */
    volatile Uint32 rsvd231[16];
    /* Addr: h(4DF00), d(319232) */
    volatile CSL_DFE_DPDA_DPDA_PREG_223_REGS dpda_preg_223[24];
    /* Addr: h(4DFC0), d(319424) */
    volatile Uint32 rsvd232[16];
    /* Addr: h(4E000), d(319488) */
    volatile CSL_DFE_DPDA_DPDA_PREG_224_REGS dpda_preg_224[24];
    /* Addr: h(4E0C0), d(319680) */
    volatile Uint32 rsvd233[16];
    /* Addr: h(4E100), d(319744) */
    volatile CSL_DFE_DPDA_DPDA_PREG_225_REGS dpda_preg_225[24];
    /* Addr: h(4E1C0), d(319936) */
    volatile Uint32 rsvd234[16];
    /* Addr: h(4E200), d(320000) */
    volatile CSL_DFE_DPDA_DPDA_PREG_226_REGS dpda_preg_226[24];
    /* Addr: h(4E2C0), d(320192) */
    volatile Uint32 rsvd235[16];
    /* Addr: h(4E300), d(320256) */
    volatile CSL_DFE_DPDA_DPDA_PREG_227_REGS dpda_preg_227[24];
    /* Addr: h(4E3C0), d(320448) */
    volatile Uint32 rsvd236[16];
    /* Addr: h(4E400), d(320512) */
    volatile CSL_DFE_DPDA_DPDA_PREG_228_REGS dpda_preg_228[24];
    /* Addr: h(4E4C0), d(320704) */
    volatile Uint32 rsvd237[16];
    /* Addr: h(4E500), d(320768) */
    volatile CSL_DFE_DPDA_DPDA_PREG_229_REGS dpda_preg_229[24];
    /* Addr: h(4E5C0), d(320960) */
    volatile Uint32 rsvd238[16];
    /* Addr: h(4E600), d(321024) */
    volatile CSL_DFE_DPDA_DPDA_PREG_230_REGS dpda_preg_230[24];
    /* Addr: h(4E6C0), d(321216) */
    volatile Uint32 rsvd239[16];
    /* Addr: h(4E700), d(321280) */
    volatile CSL_DFE_DPDA_DPDA_PREG_231_REGS dpda_preg_231[24];
    /* Addr: h(4E7C0), d(321472) */
    volatile Uint32 rsvd240[16];
    /* Addr: h(4E800), d(321536) */
    volatile CSL_DFE_DPDA_DPDA_PREG_232_REGS dpda_preg_232[24];
    /* Addr: h(4E8C0), d(321728) */
    volatile Uint32 rsvd241[16];
    /* Addr: h(4E900), d(321792) */
    volatile CSL_DFE_DPDA_DPDA_PREG_233_REGS dpda_preg_233[24];
    /* Addr: h(4E9C0), d(321984) */
    volatile Uint32 rsvd242[16];
    /* Addr: h(4EA00), d(322048) */
    volatile CSL_DFE_DPDA_DPDA_PREG_234_REGS dpda_preg_234[24];
    /* Addr: h(4EAC0), d(322240) */
    volatile Uint32 rsvd243[16];
    /* Addr: h(4EB00), d(322304) */
    volatile CSL_DFE_DPDA_DPDA_PREG_235_REGS dpda_preg_235[24];
    /* Addr: h(4EBC0), d(322496) */
    volatile Uint32 rsvd244[16];
    /* Addr: h(4EC00), d(322560) */
    volatile CSL_DFE_DPDA_DPDA_PREG_236_REGS dpda_preg_236[24];
    /* Addr: h(4ECC0), d(322752) */
    volatile Uint32 rsvd245[16];
    /* Addr: h(4ED00), d(322816) */
    volatile CSL_DFE_DPDA_DPDA_PREG_237_REGS dpda_preg_237[24];
    /* Addr: h(4EDC0), d(323008) */
    volatile Uint32 rsvd246[16];
    /* Addr: h(4EE00), d(323072) */
    volatile CSL_DFE_DPDA_DPDA_PREG_238_REGS dpda_preg_238[24];
    /* Addr: h(4EEC0), d(323264) */
    volatile Uint32 rsvd247[16];
    /* Addr: h(4EF00), d(323328) */
    volatile CSL_DFE_DPDA_DPDA_PREG_239_REGS dpda_preg_239[24];
    /* Addr: h(4EFC0), d(323520) */
    volatile Uint32 rsvd248[16];
    /* Addr: h(4F000), d(323584) */
    volatile CSL_DFE_DPDA_DPDA_PREG_240_REGS dpda_preg_240[24];
    /* Addr: h(4F0C0), d(323776) */
    volatile Uint32 rsvd249[16];
    /* Addr: h(4F100), d(323840) */
    volatile CSL_DFE_DPDA_DPDA_PREG_241_REGS dpda_preg_241[24];
    /* Addr: h(4F1C0), d(324032) */
    volatile Uint32 rsvd250[16];
    /* Addr: h(4F200), d(324096) */
    volatile CSL_DFE_DPDA_DPDA_PREG_242_REGS dpda_preg_242[24];
    /* Addr: h(4F2C0), d(324288) */
    volatile Uint32 rsvd251[16];
    /* Addr: h(4F300), d(324352) */
    volatile CSL_DFE_DPDA_DPDA_PREG_243_REGS dpda_preg_243[24];
    /* Addr: h(4F3C0), d(324544) */
    volatile Uint32 rsvd252[16];
    /* Addr: h(4F400), d(324608) */
    volatile CSL_DFE_DPDA_DPDA_PREG_244_REGS dpda_preg_244[24];
    /* Addr: h(4F4C0), d(324800) */
    volatile Uint32 rsvd253[16];
    /* Addr: h(4F500), d(324864) */
    volatile CSL_DFE_DPDA_DPDA_PREG_245_REGS dpda_preg_245[24];
    /* Addr: h(4F5C0), d(325056) */
    volatile Uint32 rsvd254[16];
    /* Addr: h(4F600), d(325120) */
    volatile CSL_DFE_DPDA_DPDA_PREG_246_REGS dpda_preg_246[24];
    /* Addr: h(4F6C0), d(325312) */
    volatile Uint32 rsvd255[16];
    /* Addr: h(4F700), d(325376) */
    volatile CSL_DFE_DPDA_DPDA_PREG_247_REGS dpda_preg_247[24];
    /* Addr: h(4F7C0), d(325568) */
    volatile Uint32 rsvd256[16];
    /* Addr: h(4F800), d(325632) */
    volatile CSL_DFE_DPDA_DPDA_PREG_248_REGS dpda_preg_248[24];
    /* Addr: h(4F8C0), d(325824) */
    volatile Uint32 rsvd257[16];
    /* Addr: h(4F900), d(325888) */
    volatile CSL_DFE_DPDA_DPDA_PREG_249_REGS dpda_preg_249[24];
    /* Addr: h(4F9C0), d(326080) */
    volatile Uint32 rsvd258[16];
    /* Addr: h(4FA00), d(326144) */
    volatile CSL_DFE_DPDA_DPDA_PREG_250_REGS dpda_preg_250[24];
    /* Addr: h(4FAC0), d(326336) */
    volatile Uint32 rsvd259[16];
    /* Addr: h(4FB00), d(326400) */
    volatile CSL_DFE_DPDA_DPDA_PREG_251_REGS dpda_preg_251[24];
    /* Addr: h(4FBC0), d(326592) */
    volatile Uint32 rsvd260[16];
    /* Addr: h(4FC00), d(326656) */
    volatile CSL_DFE_DPDA_DPDA_PREG_252_REGS dpda_preg_252[24];
    /* Addr: h(4FCC0), d(326848) */
    volatile Uint32 rsvd261[16];
    /* Addr: h(4FD00), d(326912) */
    volatile CSL_DFE_DPDA_DPDA_PREG_253_REGS dpda_preg_253[24];
    /* Addr: h(4FDC0), d(327104) */
    volatile Uint32 rsvd262[16];
    /* Addr: h(4FE00), d(327168) */
    volatile CSL_DFE_DPDA_DPDA_PREG_254_REGS dpda_preg_254[24];
    /* Addr: h(4FEC0), d(327360) */
    volatile Uint32 rsvd263[16];
    /* Addr: h(4FF00), d(327424) */
    volatile CSL_DFE_DPDA_DPDA_PREG_255_REGS dpda_preg_255[24];
    /* Addr: h(4FFC0), d(327616) */
    volatile Uint32 rsvd264[16];
    /* Addr: h(50000), d(327680) */
    volatile CSL_DFE_DPDA_DPDA_PREG_256_REGS dpda_preg_256[24];
    /* Addr: h(500C0), d(327872) */
    volatile Uint32 rsvd265[16];
    /* Addr: h(50100), d(327936) */
    volatile CSL_DFE_DPDA_DPDA_PREG_257_REGS dpda_preg_257[24];
    /* Addr: h(501C0), d(328128) */
    volatile Uint32 rsvd266[16];
    /* Addr: h(50200), d(328192) */
    volatile CSL_DFE_DPDA_DPDA_PREG_258_REGS dpda_preg_258[24];
    /* Addr: h(502C0), d(328384) */
    volatile Uint32 rsvd267[16];
    /* Addr: h(50300), d(328448) */
    volatile CSL_DFE_DPDA_DPDA_PREG_259_REGS dpda_preg_259[24];
    /* Addr: h(503C0), d(328640) */
    volatile Uint32 rsvd268[16];
    /* Addr: h(50400), d(328704) */
    volatile CSL_DFE_DPDA_DPDA_PREG_260_REGS dpda_preg_260[24];
    /* Addr: h(504C0), d(328896) */
    volatile Uint32 rsvd269[16];
    /* Addr: h(50500), d(328960) */
    volatile CSL_DFE_DPDA_DPDA_PREG_261_REGS dpda_preg_261[24];
    /* Addr: h(505C0), d(329152) */
    volatile Uint32 rsvd270[16];
    /* Addr: h(50600), d(329216) */
    volatile CSL_DFE_DPDA_DPDA_PREG_262_REGS dpda_preg_262[24];
    /* Addr: h(506C0), d(329408) */
    volatile Uint32 rsvd271[16];
    /* Addr: h(50700), d(329472) */
    volatile CSL_DFE_DPDA_DPDA_PREG_263_REGS dpda_preg_263[24];
    /* Addr: h(507C0), d(329664) */
    volatile Uint32 rsvd272[16];
    /* Addr: h(50800), d(329728) */
    volatile CSL_DFE_DPDA_DPDA_PREG_264_REGS dpda_preg_264[24];
    /* Addr: h(508C0), d(329920) */
    volatile Uint32 rsvd273[16];
    /* Addr: h(50900), d(329984) */
    volatile CSL_DFE_DPDA_DPDA_PREG_265_REGS dpda_preg_265[24];
    /* Addr: h(509C0), d(330176) */
    volatile Uint32 rsvd274[16];
    /* Addr: h(50A00), d(330240) */
    volatile CSL_DFE_DPDA_DPDA_PREG_266_REGS dpda_preg_266[24];
    /* Addr: h(50AC0), d(330432) */
    volatile Uint32 rsvd275[16];
    /* Addr: h(50B00), d(330496) */
    volatile CSL_DFE_DPDA_DPDA_PREG_267_REGS dpda_preg_267[24];
    /* Addr: h(50BC0), d(330688) */
    volatile Uint32 rsvd276[16];
    /* Addr: h(50C00), d(330752) */
    volatile CSL_DFE_DPDA_DPDA_PREG_268_REGS dpda_preg_268[24];
    /* Addr: h(50CC0), d(330944) */
    volatile Uint32 rsvd277[16];
    /* Addr: h(50D00), d(331008) */
    volatile CSL_DFE_DPDA_DPDA_PREG_269_REGS dpda_preg_269[24];
    /* Addr: h(50DC0), d(331200) */
    volatile Uint32 rsvd278[16];
    /* Addr: h(50E00), d(331264) */
    volatile CSL_DFE_DPDA_DPDA_PREG_270_REGS dpda_preg_270[24];
    /* Addr: h(50EC0), d(331456) */
    volatile Uint32 rsvd279[16];
    /* Addr: h(50F00), d(331520) */
    volatile CSL_DFE_DPDA_DPDA_PREG_271_REGS dpda_preg_271[24];
    /* Addr: h(50FC0), d(331712) */
    volatile Uint32 rsvd280[16];
    /* Addr: h(51000), d(331776) */
    volatile CSL_DFE_DPDA_DPDA_PREG_272_REGS dpda_preg_272[24];
    /* Addr: h(510C0), d(331968) */
    volatile Uint32 rsvd281[16];
    /* Addr: h(51100), d(332032) */
    volatile CSL_DFE_DPDA_DPDA_PREG_273_REGS dpda_preg_273[24];
    /* Addr: h(511C0), d(332224) */
    volatile Uint32 rsvd282[16];
    /* Addr: h(51200), d(332288) */
    volatile CSL_DFE_DPDA_DPDA_PREG_274_REGS dpda_preg_274[24];
    /* Addr: h(512C0), d(332480) */
    volatile Uint32 rsvd283[16];
    /* Addr: h(51300), d(332544) */
    volatile CSL_DFE_DPDA_DPDA_PREG_275_REGS dpda_preg_275[24];
    /* Addr: h(513C0), d(332736) */
    volatile Uint32 rsvd284[16];
    /* Addr: h(51400), d(332800) */
    volatile CSL_DFE_DPDA_DPDA_PREG_276_REGS dpda_preg_276[24];
    /* Addr: h(514C0), d(332992) */
    volatile Uint32 rsvd285[16];
    /* Addr: h(51500), d(333056) */
    volatile CSL_DFE_DPDA_DPDA_PREG_277_REGS dpda_preg_277[24];
    /* Addr: h(515C0), d(333248) */
    volatile Uint32 rsvd286[16];
    /* Addr: h(51600), d(333312) */
    volatile CSL_DFE_DPDA_DPDA_PREG_278_REGS dpda_preg_278[24];
    /* Addr: h(516C0), d(333504) */
    volatile Uint32 rsvd287[16];
    /* Addr: h(51700), d(333568) */
    volatile CSL_DFE_DPDA_DPDA_PREG_279_REGS dpda_preg_279[24];
    /* Addr: h(517C0), d(333760) */
    volatile Uint32 rsvd288[16];
    /* Addr: h(51800), d(333824) */
    volatile CSL_DFE_DPDA_DPDA_PREG_280_REGS dpda_preg_280[24];
    /* Addr: h(518C0), d(334016) */
    volatile Uint32 rsvd289[16];
    /* Addr: h(51900), d(334080) */
    volatile CSL_DFE_DPDA_DPDA_PREG_281_REGS dpda_preg_281[24];
    /* Addr: h(519C0), d(334272) */
    volatile Uint32 rsvd290[16];
    /* Addr: h(51A00), d(334336) */
    volatile CSL_DFE_DPDA_DPDA_PREG_282_REGS dpda_preg_282[24];
    /* Addr: h(51AC0), d(334528) */
    volatile Uint32 rsvd291[16];
    /* Addr: h(51B00), d(334592) */
    volatile CSL_DFE_DPDA_DPDA_PREG_283_REGS dpda_preg_283[24];
    /* Addr: h(51BC0), d(334784) */
    volatile Uint32 rsvd292[16];
    /* Addr: h(51C00), d(334848) */
    volatile CSL_DFE_DPDA_DPDA_PREG_284_REGS dpda_preg_284[24];
    /* Addr: h(51CC0), d(335040) */
    volatile Uint32 rsvd293[16];
    /* Addr: h(51D00), d(335104) */
    volatile CSL_DFE_DPDA_DPDA_PREG_285_REGS dpda_preg_285[24];
    /* Addr: h(51DC0), d(335296) */
    volatile Uint32 rsvd294[16];
    /* Addr: h(51E00), d(335360) */
    volatile CSL_DFE_DPDA_DPDA_PREG_286_REGS dpda_preg_286[24];
    /* Addr: h(51EC0), d(335552) */
    volatile Uint32 rsvd295[16];
    /* Addr: h(51F00), d(335616) */
    volatile CSL_DFE_DPDA_DPDA_PREG_287_REGS dpda_preg_287[24];
    /* Addr: h(51FC0), d(335808) */
    volatile Uint32 rsvd296[16];
    /* Addr: h(52000), d(335872) */
    volatile CSL_DFE_DPDA_DPDA_PREG_288_REGS dpda_preg_288[24];
    /* Addr: h(520C0), d(336064) */
    volatile Uint32 rsvd297[16];
    /* Addr: h(52100), d(336128) */
    volatile CSL_DFE_DPDA_DPDA_PREG_289_REGS dpda_preg_289[24];
    /* Addr: h(521C0), d(336320) */
    volatile Uint32 rsvd298[16];
    /* Addr: h(52200), d(336384) */
    volatile CSL_DFE_DPDA_DPDA_PREG_290_REGS dpda_preg_290[24];
    /* Addr: h(522C0), d(336576) */
    volatile Uint32 rsvd299[16];
    /* Addr: h(52300), d(336640) */
    volatile CSL_DFE_DPDA_DPDA_PREG_291_REGS dpda_preg_291[24];
    /* Addr: h(523C0), d(336832) */
    volatile Uint32 rsvd300[16];
    /* Addr: h(52400), d(336896) */
    volatile CSL_DFE_DPDA_DPDA_PREG_292_REGS dpda_preg_292[24];
    /* Addr: h(524C0), d(337088) */
    volatile Uint32 rsvd301[16];
    /* Addr: h(52500), d(337152) */
    volatile CSL_DFE_DPDA_DPDA_PREG_293_REGS dpda_preg_293[24];
    /* Addr: h(525C0), d(337344) */
    volatile Uint32 rsvd302[16];
    /* Addr: h(52600), d(337408) */
    volatile CSL_DFE_DPDA_DPDA_PREG_294_REGS dpda_preg_294[24];
    /* Addr: h(526C0), d(337600) */
    volatile Uint32 rsvd303[16];
    /* Addr: h(52700), d(337664) */
    volatile CSL_DFE_DPDA_DPDA_PREG_295_REGS dpda_preg_295[24];
    /* Addr: h(527C0), d(337856) */
    volatile Uint32 rsvd304[16];
    /* Addr: h(52800), d(337920) */
    volatile CSL_DFE_DPDA_DPDA_PREG_296_REGS dpda_preg_296[24];
    /* Addr: h(528C0), d(338112) */
    volatile Uint32 rsvd305[16];
    /* Addr: h(52900), d(338176) */
    volatile CSL_DFE_DPDA_DPDA_PREG_297_REGS dpda_preg_297[24];
    /* Addr: h(529C0), d(338368) */
    volatile Uint32 rsvd306[16];
    /* Addr: h(52A00), d(338432) */
    volatile CSL_DFE_DPDA_DPDA_PREG_298_REGS dpda_preg_298[24];
    /* Addr: h(52AC0), d(338624) */
    volatile Uint32 rsvd307[16];
    /* Addr: h(52B00), d(338688) */
    volatile CSL_DFE_DPDA_DPDA_PREG_299_REGS dpda_preg_299[24];
    /* Addr: h(52BC0), d(338880) */
    volatile Uint32 rsvd308[16];
    /* Addr: h(52C00), d(338944) */
    volatile CSL_DFE_DPDA_DPDA_PREG_300_REGS dpda_preg_300[24];
    /* Addr: h(52CC0), d(339136) */
    volatile Uint32 rsvd309[16];
    /* Addr: h(52D00), d(339200) */
    volatile CSL_DFE_DPDA_DPDA_PREG_301_REGS dpda_preg_301[24];
    /* Addr: h(52DC0), d(339392) */
    volatile Uint32 rsvd310[16];
    /* Addr: h(52E00), d(339456) */
    volatile CSL_DFE_DPDA_DPDA_PREG_302_REGS dpda_preg_302[24];
    /* Addr: h(52EC0), d(339648) */
    volatile Uint32 rsvd311[16];
    /* Addr: h(52F00), d(339712) */
    volatile CSL_DFE_DPDA_DPDA_PREG_303_REGS dpda_preg_303[24];
    /* Addr: h(52FC0), d(339904) */
    volatile Uint32 rsvd312[16];
    /* Addr: h(53000), d(339968) */
    volatile CSL_DFE_DPDA_DPDA_PREG_304_REGS dpda_preg_304[24];
    /* Addr: h(530C0), d(340160) */
    volatile Uint32 rsvd313[16];
    /* Addr: h(53100), d(340224) */
    volatile CSL_DFE_DPDA_DPDA_PREG_305_REGS dpda_preg_305[24];
    /* Addr: h(531C0), d(340416) */
    volatile Uint32 rsvd314[16];
    /* Addr: h(53200), d(340480) */
    volatile CSL_DFE_DPDA_DPDA_PREG_306_REGS dpda_preg_306[24];
    /* Addr: h(532C0), d(340672) */
    volatile Uint32 rsvd315[16];
    /* Addr: h(53300), d(340736) */
    volatile CSL_DFE_DPDA_DPDA_PREG_307_REGS dpda_preg_307[24];
    /* Addr: h(533C0), d(340928) */
    volatile Uint32 rsvd316[16];
    /* Addr: h(53400), d(340992) */
    volatile CSL_DFE_DPDA_DPDA_PREG_308_REGS dpda_preg_308[24];
    /* Addr: h(534C0), d(341184) */
    volatile Uint32 rsvd317[16];
    /* Addr: h(53500), d(341248) */
    volatile CSL_DFE_DPDA_DPDA_PREG_309_REGS dpda_preg_309[24];
    /* Addr: h(535C0), d(341440) */
    volatile Uint32 rsvd318[16];
    /* Addr: h(53600), d(341504) */
    volatile CSL_DFE_DPDA_DPDA_PREG_310_REGS dpda_preg_310[24];
    /* Addr: h(536C0), d(341696) */
    volatile Uint32 rsvd319[16];
    /* Addr: h(53700), d(341760) */
    volatile CSL_DFE_DPDA_DPDA_PREG_311_REGS dpda_preg_311[24];
    /* Addr: h(537C0), d(341952) */
    volatile Uint32 rsvd320[16];
    /* Addr: h(53800), d(342016) */
    volatile CSL_DFE_DPDA_DPDA_PREG_312_REGS dpda_preg_312[24];
    /* Addr: h(538C0), d(342208) */
    volatile Uint32 rsvd321[16];
    /* Addr: h(53900), d(342272) */
    volatile CSL_DFE_DPDA_DPDA_PREG_313_REGS dpda_preg_313[24];
    /* Addr: h(539C0), d(342464) */
    volatile Uint32 rsvd322[16];
    /* Addr: h(53A00), d(342528) */
    volatile CSL_DFE_DPDA_DPDA_PREG_314_REGS dpda_preg_314[24];
    /* Addr: h(53AC0), d(342720) */
    volatile Uint32 rsvd323[16];
    /* Addr: h(53B00), d(342784) */
    volatile CSL_DFE_DPDA_DPDA_PREG_315_REGS dpda_preg_315[24];
    /* Addr: h(53BC0), d(342976) */
    volatile Uint32 rsvd324[16];
    /* Addr: h(53C00), d(343040) */
    volatile CSL_DFE_DPDA_DPDA_PREG_316_REGS dpda_preg_316[24];
    /* Addr: h(53CC0), d(343232) */
    volatile Uint32 rsvd325[16];
    /* Addr: h(53D00), d(343296) */
    volatile CSL_DFE_DPDA_DPDA_PREG_317_REGS dpda_preg_317[24];
    /* Addr: h(53DC0), d(343488) */
    volatile Uint32 rsvd326[16];
    /* Addr: h(53E00), d(343552) */
    volatile CSL_DFE_DPDA_DPDA_PREG_318_REGS dpda_preg_318[24];
    /* Addr: h(53EC0), d(343744) */
    volatile Uint32 rsvd327[16];
    /* Addr: h(53F00), d(343808) */
    volatile CSL_DFE_DPDA_DPDA_PREG_319_REGS dpda_preg_319[24];
    /* Addr: h(53FC0), d(344000) */
    volatile Uint32 rsvd328[16];
    /* Addr: h(54000), d(344064) */
    volatile CSL_DFE_DPDA_DPDA_PREG_320_REGS dpda_preg_320[24];
    /* Addr: h(540C0), d(344256) */
    volatile Uint32 rsvd329[16];
    /* Addr: h(54100), d(344320) */
    volatile CSL_DFE_DPDA_DPDA_PREG_321_REGS dpda_preg_321[24];
    /* Addr: h(541C0), d(344512) */
    volatile Uint32 rsvd330[16];
    /* Addr: h(54200), d(344576) */
    volatile CSL_DFE_DPDA_DPDA_PREG_322_REGS dpda_preg_322[24];
    /* Addr: h(542C0), d(344768) */
    volatile Uint32 rsvd331[16];
    /* Addr: h(54300), d(344832) */
    volatile CSL_DFE_DPDA_DPDA_PREG_323_REGS dpda_preg_323[24];
    /* Addr: h(543C0), d(345024) */
    volatile Uint32 rsvd332[16];
    /* Addr: h(54400), d(345088) */
    volatile CSL_DFE_DPDA_DPDA_PREG_324_REGS dpda_preg_324[24];
    /* Addr: h(544C0), d(345280) */
    volatile Uint32 rsvd333[16];
    /* Addr: h(54500), d(345344) */
    volatile CSL_DFE_DPDA_DPDA_PREG_325_REGS dpda_preg_325[24];
    /* Addr: h(545C0), d(345536) */
    volatile Uint32 rsvd334[16];
    /* Addr: h(54600), d(345600) */
    volatile CSL_DFE_DPDA_DPDA_PREG_326_REGS dpda_preg_326[24];
    /* Addr: h(546C0), d(345792) */
    volatile Uint32 rsvd335[16];
    /* Addr: h(54700), d(345856) */
    volatile CSL_DFE_DPDA_DPDA_PREG_327_REGS dpda_preg_327[24];
    /* Addr: h(547C0), d(346048) */
    volatile Uint32 rsvd336[16];
    /* Addr: h(54800), d(346112) */
    volatile CSL_DFE_DPDA_DPDA_PREG_328_REGS dpda_preg_328[24];
    /* Addr: h(548C0), d(346304) */
    volatile Uint32 rsvd337[16];
    /* Addr: h(54900), d(346368) */
    volatile CSL_DFE_DPDA_DPDA_PREG_329_REGS dpda_preg_329[24];
    /* Addr: h(549C0), d(346560) */
    volatile Uint32 rsvd338[16];
    /* Addr: h(54A00), d(346624) */
    volatile CSL_DFE_DPDA_DPDA_PREG_330_REGS dpda_preg_330[24];
    /* Addr: h(54AC0), d(346816) */
    volatile Uint32 rsvd339[16];
    /* Addr: h(54B00), d(346880) */
    volatile CSL_DFE_DPDA_DPDA_PREG_331_REGS dpda_preg_331[24];
    /* Addr: h(54BC0), d(347072) */
    volatile Uint32 rsvd340[16];
    /* Addr: h(54C00), d(347136) */
    volatile CSL_DFE_DPDA_DPDA_PREG_332_REGS dpda_preg_332[24];
    /* Addr: h(54CC0), d(347328) */
    volatile Uint32 rsvd341[16];
    /* Addr: h(54D00), d(347392) */
    volatile CSL_DFE_DPDA_DPDA_PREG_333_REGS dpda_preg_333[24];
    /* Addr: h(54DC0), d(347584) */
    volatile Uint32 rsvd342[16];
    /* Addr: h(54E00), d(347648) */
    volatile CSL_DFE_DPDA_DPDA_PREG_334_REGS dpda_preg_334[24];
    /* Addr: h(54EC0), d(347840) */
    volatile Uint32 rsvd343[16];
    /* Addr: h(54F00), d(347904) */
    volatile CSL_DFE_DPDA_DPDA_PREG_335_REGS dpda_preg_335[24];
    /* Addr: h(54FC0), d(348096) */
    volatile Uint32 rsvd344[16];
    /* Addr: h(55000), d(348160) */
    volatile CSL_DFE_DPDA_DPDA_PREG_336_REGS dpda_preg_336[24];
    /* Addr: h(550C0), d(348352) */
    volatile Uint32 rsvd345[16];
    /* Addr: h(55100), d(348416) */
    volatile CSL_DFE_DPDA_DPDA_PREG_337_REGS dpda_preg_337[24];
    /* Addr: h(551C0), d(348608) */
    volatile Uint32 rsvd346[16];
    /* Addr: h(55200), d(348672) */
    volatile CSL_DFE_DPDA_DPDA_PREG_338_REGS dpda_preg_338[24];
    /* Addr: h(552C0), d(348864) */
    volatile Uint32 rsvd347[16];
    /* Addr: h(55300), d(348928) */
    volatile CSL_DFE_DPDA_DPDA_PREG_339_REGS dpda_preg_339[24];
    /* Addr: h(553C0), d(349120) */
    volatile Uint32 rsvd348[16];
    /* Addr: h(55400), d(349184) */
    volatile CSL_DFE_DPDA_DPDA_PREG_340_REGS dpda_preg_340[24];
    /* Addr: h(554C0), d(349376) */
    volatile Uint32 rsvd349[16];
    /* Addr: h(55500), d(349440) */
    volatile CSL_DFE_DPDA_DPDA_PREG_341_REGS dpda_preg_341[24];
    /* Addr: h(555C0), d(349632) */
    volatile Uint32 rsvd350[16];
    /* Addr: h(55600), d(349696) */
    volatile CSL_DFE_DPDA_DPDA_PREG_342_REGS dpda_preg_342[24];
    /* Addr: h(556C0), d(349888) */
    volatile Uint32 rsvd351[16];
    /* Addr: h(55700), d(349952) */
    volatile CSL_DFE_DPDA_DPDA_PREG_343_REGS dpda_preg_343[24];
    /* Addr: h(557C0), d(350144) */
    volatile Uint32 rsvd352[16];
    /* Addr: h(55800), d(350208) */
    volatile CSL_DFE_DPDA_DPDA_PREG_344_REGS dpda_preg_344[24];
    /* Addr: h(558C0), d(350400) */
    volatile Uint32 rsvd353[16];
    /* Addr: h(55900), d(350464) */
    volatile CSL_DFE_DPDA_DPDA_PREG_345_REGS dpda_preg_345[24];
    /* Addr: h(559C0), d(350656) */
    volatile Uint32 rsvd354[16];
    /* Addr: h(55A00), d(350720) */
    volatile CSL_DFE_DPDA_DPDA_PREG_346_REGS dpda_preg_346[24];
    /* Addr: h(55AC0), d(350912) */
    volatile Uint32 rsvd355[16];
    /* Addr: h(55B00), d(350976) */
    volatile CSL_DFE_DPDA_DPDA_PREG_347_REGS dpda_preg_347[24];
    /* Addr: h(55BC0), d(351168) */
    volatile Uint32 rsvd356[16];
    /* Addr: h(55C00), d(351232) */
    volatile CSL_DFE_DPDA_DPDA_PREG_348_REGS dpda_preg_348[24];
    /* Addr: h(55CC0), d(351424) */
    volatile Uint32 rsvd357[16];
    /* Addr: h(55D00), d(351488) */
    volatile CSL_DFE_DPDA_DPDA_PREG_349_REGS dpda_preg_349[24];
    /* Addr: h(55DC0), d(351680) */
    volatile Uint32 rsvd358[16];
    /* Addr: h(55E00), d(351744) */
    volatile CSL_DFE_DPDA_DPDA_PREG_350_REGS dpda_preg_350[24];
    /* Addr: h(55EC0), d(351936) */
    volatile Uint32 rsvd359[16];
    /* Addr: h(55F00), d(352000) */
    volatile CSL_DFE_DPDA_DPDA_PREG_351_REGS dpda_preg_351[24];
    /* Addr: h(55FC0), d(352192) */
    volatile Uint32 rsvd360[16];
    /* Addr: h(56000), d(352256) */
    volatile CSL_DFE_DPDA_DPDA_PREG_352_REGS dpda_preg_352[24];
    /* Addr: h(560C0), d(352448) */
    volatile Uint32 rsvd361[16];
    /* Addr: h(56100), d(352512) */
    volatile CSL_DFE_DPDA_DPDA_PREG_353_REGS dpda_preg_353[24];
    /* Addr: h(561C0), d(352704) */
    volatile Uint32 rsvd362[16];
    /* Addr: h(56200), d(352768) */
    volatile CSL_DFE_DPDA_DPDA_PREG_354_REGS dpda_preg_354[24];
    /* Addr: h(562C0), d(352960) */
    volatile Uint32 rsvd363[16];
    /* Addr: h(56300), d(353024) */
    volatile CSL_DFE_DPDA_DPDA_PREG_355_REGS dpda_preg_355[24];
    /* Addr: h(563C0), d(353216) */
    volatile Uint32 rsvd364[16];
    /* Addr: h(56400), d(353280) */
    volatile CSL_DFE_DPDA_DPDA_PREG_356_REGS dpda_preg_356[24];
    /* Addr: h(564C0), d(353472) */
    volatile Uint32 rsvd365[16];
    /* Addr: h(56500), d(353536) */
    volatile CSL_DFE_DPDA_DPDA_PREG_357_REGS dpda_preg_357[24];
    /* Addr: h(565C0), d(353728) */
    volatile Uint32 rsvd366[16];
    /* Addr: h(56600), d(353792) */
    volatile CSL_DFE_DPDA_DPDA_PREG_358_REGS dpda_preg_358[24];
    /* Addr: h(566C0), d(353984) */
    volatile Uint32 rsvd367[16];
    /* Addr: h(56700), d(354048) */
    volatile CSL_DFE_DPDA_DPDA_PREG_359_REGS dpda_preg_359[24];
    /* Addr: h(567C0), d(354240) */
    volatile Uint32 rsvd368[16];
    /* Addr: h(56800), d(354304) */
    volatile CSL_DFE_DPDA_DPDA_PREG_360_REGS dpda_preg_360[24];
    /* Addr: h(568C0), d(354496) */
    volatile Uint32 rsvd369[16];
    /* Addr: h(56900), d(354560) */
    volatile CSL_DFE_DPDA_DPDA_PREG_361_REGS dpda_preg_361[24];
    /* Addr: h(569C0), d(354752) */
    volatile Uint32 rsvd370[16];
    /* Addr: h(56A00), d(354816) */
    volatile CSL_DFE_DPDA_DPDA_PREG_362_REGS dpda_preg_362[24];
    /* Addr: h(56AC0), d(355008) */
    volatile Uint32 rsvd371[16];
    /* Addr: h(56B00), d(355072) */
    volatile CSL_DFE_DPDA_DPDA_PREG_363_REGS dpda_preg_363[24];
    /* Addr: h(56BC0), d(355264) */
    volatile Uint32 rsvd372[16];
    /* Addr: h(56C00), d(355328) */
    volatile CSL_DFE_DPDA_DPDA_PREG_364_REGS dpda_preg_364[24];
    /* Addr: h(56CC0), d(355520) */
    volatile Uint32 rsvd373[16];
    /* Addr: h(56D00), d(355584) */
    volatile CSL_DFE_DPDA_DPDA_PREG_365_REGS dpda_preg_365[24];
    /* Addr: h(56DC0), d(355776) */
    volatile Uint32 rsvd374[16];
    /* Addr: h(56E00), d(355840) */
    volatile CSL_DFE_DPDA_DPDA_PREG_366_REGS dpda_preg_366[24];
    /* Addr: h(56EC0), d(356032) */
    volatile Uint32 rsvd375[16];
    /* Addr: h(56F00), d(356096) */
    volatile CSL_DFE_DPDA_DPDA_PREG_367_REGS dpda_preg_367[24];
    /* Addr: h(56FC0), d(356288) */
    volatile Uint32 rsvd376[16];
    /* Addr: h(57000), d(356352) */
    volatile CSL_DFE_DPDA_DPDA_PREG_368_REGS dpda_preg_368[24];
    /* Addr: h(570C0), d(356544) */
    volatile Uint32 rsvd377[16];
    /* Addr: h(57100), d(356608) */
    volatile CSL_DFE_DPDA_DPDA_PREG_369_REGS dpda_preg_369[24];
    /* Addr: h(571C0), d(356800) */
    volatile Uint32 rsvd378[16];
    /* Addr: h(57200), d(356864) */
    volatile CSL_DFE_DPDA_DPDA_PREG_370_REGS dpda_preg_370[24];
    /* Addr: h(572C0), d(357056) */
    volatile Uint32 rsvd379[16];
    /* Addr: h(57300), d(357120) */
    volatile CSL_DFE_DPDA_DPDA_PREG_371_REGS dpda_preg_371[24];
    /* Addr: h(573C0), d(357312) */
    volatile Uint32 rsvd380[16];
    /* Addr: h(57400), d(357376) */
    volatile CSL_DFE_DPDA_DPDA_PREG_372_REGS dpda_preg_372[24];
    /* Addr: h(574C0), d(357568) */
    volatile Uint32 rsvd381[16];
    /* Addr: h(57500), d(357632) */
    volatile CSL_DFE_DPDA_DPDA_PREG_373_REGS dpda_preg_373[24];
    /* Addr: h(575C0), d(357824) */
    volatile Uint32 rsvd382[16];
    /* Addr: h(57600), d(357888) */
    volatile CSL_DFE_DPDA_DPDA_PREG_374_REGS dpda_preg_374[24];
    /* Addr: h(576C0), d(358080) */
    volatile Uint32 rsvd383[16];
    /* Addr: h(57700), d(358144) */
    volatile CSL_DFE_DPDA_DPDA_PREG_375_REGS dpda_preg_375[24];
    /* Addr: h(577C0), d(358336) */
    volatile Uint32 rsvd384[16];
    /* Addr: h(57800), d(358400) */
    volatile CSL_DFE_DPDA_DPDA_PREG_376_REGS dpda_preg_376[24];
    /* Addr: h(578C0), d(358592) */
    volatile Uint32 rsvd385[16];
    /* Addr: h(57900), d(358656) */
    volatile CSL_DFE_DPDA_DPDA_PREG_377_REGS dpda_preg_377[24];
    /* Addr: h(579C0), d(358848) */
    volatile Uint32 rsvd386[16];
    /* Addr: h(57A00), d(358912) */
    volatile CSL_DFE_DPDA_DPDA_PREG_378_REGS dpda_preg_378[24];
    /* Addr: h(57AC0), d(359104) */
    volatile Uint32 rsvd387[16];
    /* Addr: h(57B00), d(359168) */
    volatile CSL_DFE_DPDA_DPDA_PREG_379_REGS dpda_preg_379[24];
    /* Addr: h(57BC0), d(359360) */
    volatile Uint32 rsvd388[16];
    /* Addr: h(57C00), d(359424) */
    volatile CSL_DFE_DPDA_DPDA_PREG_380_REGS dpda_preg_380[24];
    /* Addr: h(57CC0), d(359616) */
    volatile Uint32 rsvd389[16];
    /* Addr: h(57D00), d(359680) */
    volatile CSL_DFE_DPDA_DPDA_PREG_381_REGS dpda_preg_381[24];
    /* Addr: h(57DC0), d(359872) */
    volatile Uint32 rsvd390[16];
    /* Addr: h(57E00), d(359936) */
    volatile CSL_DFE_DPDA_DPDA_PREG_382_REGS dpda_preg_382[24];
    /* Addr: h(57EC0), d(360128) */
    volatile Uint32 rsvd391[16];
    /* Addr: h(57F00), d(360192) */
    volatile CSL_DFE_DPDA_DPDA_PREG_383_REGS dpda_preg_383[24];
    /* Addr: h(57FC0), d(360384) */
    volatile Uint32 rsvd392[16];
    /* Addr: h(58000), d(360448) */
    volatile CSL_DFE_DPDA_DPDA_PREG_384_REGS dpda_preg_384[24];
    /* Addr: h(580C0), d(360640) */
    volatile Uint32 rsvd393[16];
    /* Addr: h(58100), d(360704) */
    volatile CSL_DFE_DPDA_DPDA_PREG_385_REGS dpda_preg_385[24];
    /* Addr: h(581C0), d(360896) */
    volatile Uint32 rsvd394[16];
    /* Addr: h(58200), d(360960) */
    volatile CSL_DFE_DPDA_DPDA_PREG_386_REGS dpda_preg_386[24];
    /* Addr: h(582C0), d(361152) */
    volatile Uint32 rsvd395[16];
    /* Addr: h(58300), d(361216) */
    volatile CSL_DFE_DPDA_DPDA_PREG_387_REGS dpda_preg_387[24];
    /* Addr: h(583C0), d(361408) */
    volatile Uint32 rsvd396[16];
    /* Addr: h(58400), d(361472) */
    volatile CSL_DFE_DPDA_DPDA_PREG_388_REGS dpda_preg_388[24];
    /* Addr: h(584C0), d(361664) */
    volatile Uint32 rsvd397[16];
    /* Addr: h(58500), d(361728) */
    volatile CSL_DFE_DPDA_DPDA_PREG_389_REGS dpda_preg_389[24];
    /* Addr: h(585C0), d(361920) */
    volatile Uint32 rsvd398[16];
    /* Addr: h(58600), d(361984) */
    volatile CSL_DFE_DPDA_DPDA_PREG_390_REGS dpda_preg_390[24];
    /* Addr: h(586C0), d(362176) */
    volatile Uint32 rsvd399[16];
    /* Addr: h(58700), d(362240) */
    volatile CSL_DFE_DPDA_DPDA_PREG_391_REGS dpda_preg_391[24];
    /* Addr: h(587C0), d(362432) */
    volatile Uint32 rsvd400[16];
    /* Addr: h(58800), d(362496) */
    volatile CSL_DFE_DPDA_DPDA_PREG_392_REGS dpda_preg_392[24];
    /* Addr: h(588C0), d(362688) */
    volatile Uint32 rsvd401[16];
    /* Addr: h(58900), d(362752) */
    volatile CSL_DFE_DPDA_DPDA_PREG_393_REGS dpda_preg_393[24];
    /* Addr: h(589C0), d(362944) */
    volatile Uint32 rsvd402[16];
    /* Addr: h(58A00), d(363008) */
    volatile CSL_DFE_DPDA_DPDA_PREG_394_REGS dpda_preg_394[24];
    /* Addr: h(58AC0), d(363200) */
    volatile Uint32 rsvd403[16];
    /* Addr: h(58B00), d(363264) */
    volatile CSL_DFE_DPDA_DPDA_PREG_395_REGS dpda_preg_395[24];
    /* Addr: h(58BC0), d(363456) */
    volatile Uint32 rsvd404[16];
    /* Addr: h(58C00), d(363520) */
    volatile CSL_DFE_DPDA_DPDA_PREG_396_REGS dpda_preg_396[24];
    /* Addr: h(58CC0), d(363712) */
    volatile Uint32 rsvd405[16];
    /* Addr: h(58D00), d(363776) */
    volatile CSL_DFE_DPDA_DPDA_PREG_397_REGS dpda_preg_397[24];
    /* Addr: h(58DC0), d(363968) */
    volatile Uint32 rsvd406[16];
    /* Addr: h(58E00), d(364032) */
    volatile CSL_DFE_DPDA_DPDA_PREG_398_REGS dpda_preg_398[24];
    /* Addr: h(58EC0), d(364224) */
    volatile Uint32 rsvd407[16];
    /* Addr: h(58F00), d(364288) */
    volatile CSL_DFE_DPDA_DPDA_PREG_399_REGS dpda_preg_399[24];
    /* Addr: h(58FC0), d(364480) */
    volatile Uint32 rsvd408[16];
    /* Addr: h(59000), d(364544) */
    volatile CSL_DFE_DPDA_DPDA_PREG_400_REGS dpda_preg_400[24];
    /* Addr: h(590C0), d(364736) */
    volatile Uint32 rsvd409[16];
    /* Addr: h(59100), d(364800) */
    volatile CSL_DFE_DPDA_DPDA_PREG_401_REGS dpda_preg_401[24];
    /* Addr: h(591C0), d(364992) */
    volatile Uint32 rsvd410[16];
    /* Addr: h(59200), d(365056) */
    volatile CSL_DFE_DPDA_DPDA_PREG_402_REGS dpda_preg_402[24];
    /* Addr: h(592C0), d(365248) */
    volatile Uint32 rsvd411[16];
    /* Addr: h(59300), d(365312) */
    volatile CSL_DFE_DPDA_DPDA_PREG_403_REGS dpda_preg_403[24];
    /* Addr: h(593C0), d(365504) */
    volatile Uint32 rsvd412[16];
    /* Addr: h(59400), d(365568) */
    volatile CSL_DFE_DPDA_DPDA_PREG_404_REGS dpda_preg_404[24];
    /* Addr: h(594C0), d(365760) */
    volatile Uint32 rsvd413[16];
    /* Addr: h(59500), d(365824) */
    volatile CSL_DFE_DPDA_DPDA_PREG_405_REGS dpda_preg_405[24];
    /* Addr: h(595C0), d(366016) */
    volatile Uint32 rsvd414[16];
    /* Addr: h(59600), d(366080) */
    volatile CSL_DFE_DPDA_DPDA_PREG_406_REGS dpda_preg_406[24];
    /* Addr: h(596C0), d(366272) */
    volatile Uint32 rsvd415[16];
    /* Addr: h(59700), d(366336) */
    volatile CSL_DFE_DPDA_DPDA_PREG_407_REGS dpda_preg_407[24];
    /* Addr: h(597C0), d(366528) */
    volatile Uint32 rsvd416[16];
    /* Addr: h(59800), d(366592) */
    volatile CSL_DFE_DPDA_DPDA_PREG_408_REGS dpda_preg_408[24];
    /* Addr: h(598C0), d(366784) */
    volatile Uint32 rsvd417[16];
    /* Addr: h(59900), d(366848) */
    volatile CSL_DFE_DPDA_DPDA_PREG_409_REGS dpda_preg_409[24];
    /* Addr: h(599C0), d(367040) */
    volatile Uint32 rsvd418[16];
    /* Addr: h(59A00), d(367104) */
    volatile CSL_DFE_DPDA_DPDA_PREG_410_REGS dpda_preg_410[24];
    /* Addr: h(59AC0), d(367296) */
    volatile Uint32 rsvd419[16];
    /* Addr: h(59B00), d(367360) */
    volatile CSL_DFE_DPDA_DPDA_PREG_411_REGS dpda_preg_411[24];
    /* Addr: h(59BC0), d(367552) */
    volatile Uint32 rsvd420[16];
    /* Addr: h(59C00), d(367616) */
    volatile CSL_DFE_DPDA_DPDA_PREG_412_REGS dpda_preg_412[24];
    /* Addr: h(59CC0), d(367808) */
    volatile Uint32 rsvd421[16];
    /* Addr: h(59D00), d(367872) */
    volatile CSL_DFE_DPDA_DPDA_PREG_413_REGS dpda_preg_413[24];
    /* Addr: h(59DC0), d(368064) */
    volatile Uint32 rsvd422[16];
    /* Addr: h(59E00), d(368128) */
    volatile CSL_DFE_DPDA_DPDA_PREG_414_REGS dpda_preg_414[24];
    /* Addr: h(59EC0), d(368320) */
    volatile Uint32 rsvd423[16];
    /* Addr: h(59F00), d(368384) */
    volatile CSL_DFE_DPDA_DPDA_PREG_415_REGS dpda_preg_415[24];
    /* Addr: h(59FC0), d(368576) */
    volatile Uint32 rsvd424[16];
    /* Addr: h(5A000), d(368640) */
    volatile CSL_DFE_DPDA_DPDA_PREG_416_REGS dpda_preg_416[24];
    /* Addr: h(5A0C0), d(368832) */
    volatile Uint32 rsvd425[16];
    /* Addr: h(5A100), d(368896) */
    volatile CSL_DFE_DPDA_DPDA_PREG_417_REGS dpda_preg_417[24];
    /* Addr: h(5A1C0), d(369088) */
    volatile Uint32 rsvd426[16];
    /* Addr: h(5A200), d(369152) */
    volatile CSL_DFE_DPDA_DPDA_PREG_418_REGS dpda_preg_418[24];
    /* Addr: h(5A2C0), d(369344) */
    volatile Uint32 rsvd427[16];
    /* Addr: h(5A300), d(369408) */
    volatile CSL_DFE_DPDA_DPDA_PREG_419_REGS dpda_preg_419[24];
    /* Addr: h(5A3C0), d(369600) */
    volatile Uint32 rsvd428[16];
    /* Addr: h(5A400), d(369664) */
    volatile CSL_DFE_DPDA_DPDA_PREG_420_REGS dpda_preg_420[24];
    /* Addr: h(5A4C0), d(369856) */
    volatile Uint32 rsvd429[16];
    /* Addr: h(5A500), d(369920) */
    volatile CSL_DFE_DPDA_DPDA_PREG_421_REGS dpda_preg_421[24];
    /* Addr: h(5A5C0), d(370112) */
    volatile Uint32 rsvd430[16];
    /* Addr: h(5A600), d(370176) */
    volatile CSL_DFE_DPDA_DPDA_PREG_422_REGS dpda_preg_422[24];
    /* Addr: h(5A6C0), d(370368) */
    volatile Uint32 rsvd431[16];
    /* Addr: h(5A700), d(370432) */
    volatile CSL_DFE_DPDA_DPDA_PREG_423_REGS dpda_preg_423[24];
    /* Addr: h(5A7C0), d(370624) */
    volatile Uint32 rsvd432[16];
    /* Addr: h(5A800), d(370688) */
    volatile CSL_DFE_DPDA_DPDA_PREG_424_REGS dpda_preg_424[24];
    /* Addr: h(5A8C0), d(370880) */
    volatile Uint32 rsvd433[16];
    /* Addr: h(5A900), d(370944) */
    volatile CSL_DFE_DPDA_DPDA_PREG_425_REGS dpda_preg_425[24];
    /* Addr: h(5A9C0), d(371136) */
    volatile Uint32 rsvd434[16];
    /* Addr: h(5AA00), d(371200) */
    volatile CSL_DFE_DPDA_DPDA_PREG_426_REGS dpda_preg_426[24];
    /* Addr: h(5AAC0), d(371392) */
    volatile Uint32 rsvd435[16];
    /* Addr: h(5AB00), d(371456) */
    volatile CSL_DFE_DPDA_DPDA_PREG_427_REGS dpda_preg_427[24];
    /* Addr: h(5ABC0), d(371648) */
    volatile Uint32 rsvd436[16];
    /* Addr: h(5AC00), d(371712) */
    volatile CSL_DFE_DPDA_DPDA_PREG_428_REGS dpda_preg_428[24];
    /* Addr: h(5ACC0), d(371904) */
    volatile Uint32 rsvd437[16];
    /* Addr: h(5AD00), d(371968) */
    volatile CSL_DFE_DPDA_DPDA_PREG_429_REGS dpda_preg_429[24];
    /* Addr: h(5ADC0), d(372160) */
    volatile Uint32 rsvd438[16];
    /* Addr: h(5AE00), d(372224) */
    volatile CSL_DFE_DPDA_DPDA_PREG_430_REGS dpda_preg_430[24];
    /* Addr: h(5AEC0), d(372416) */
    volatile Uint32 rsvd439[16];
    /* Addr: h(5AF00), d(372480) */
    volatile CSL_DFE_DPDA_DPDA_PREG_431_REGS dpda_preg_431[24];
    /* Addr: h(5AFC0), d(372672) */
    volatile Uint32 rsvd440[16];
    /* Addr: h(5B000), d(372736) */
    volatile CSL_DFE_DPDA_DPDA_PREG_432_REGS dpda_preg_432[24];
    /* Addr: h(5B0C0), d(372928) */
    volatile Uint32 rsvd441[16];
    /* Addr: h(5B100), d(372992) */
    volatile CSL_DFE_DPDA_DPDA_PREG_433_REGS dpda_preg_433[24];
    /* Addr: h(5B1C0), d(373184) */
    volatile Uint32 rsvd442[16];
    /* Addr: h(5B200), d(373248) */
    volatile CSL_DFE_DPDA_DPDA_PREG_434_REGS dpda_preg_434[24];
    /* Addr: h(5B2C0), d(373440) */
    volatile Uint32 rsvd443[16];
    /* Addr: h(5B300), d(373504) */
    volatile CSL_DFE_DPDA_DPDA_PREG_435_REGS dpda_preg_435[24];
    /* Addr: h(5B3C0), d(373696) */
    volatile Uint32 rsvd444[16];
    /* Addr: h(5B400), d(373760) */
    volatile CSL_DFE_DPDA_DPDA_PREG_436_REGS dpda_preg_436[24];
    /* Addr: h(5B4C0), d(373952) */
    volatile Uint32 rsvd445[16];
    /* Addr: h(5B500), d(374016) */
    volatile CSL_DFE_DPDA_DPDA_PREG_437_REGS dpda_preg_437[24];
    /* Addr: h(5B5C0), d(374208) */
    volatile Uint32 rsvd446[16];
    /* Addr: h(5B600), d(374272) */
    volatile CSL_DFE_DPDA_DPDA_PREG_438_REGS dpda_preg_438[24];
    /* Addr: h(5B6C0), d(374464) */
    volatile Uint32 rsvd447[16];
    /* Addr: h(5B700), d(374528) */
    volatile CSL_DFE_DPDA_DPDA_PREG_439_REGS dpda_preg_439[24];
    /* Addr: h(5B7C0), d(374720) */
    volatile Uint32 rsvd448[16];
    /* Addr: h(5B800), d(374784) */
    volatile CSL_DFE_DPDA_DPDA_PREG_440_REGS dpda_preg_440[24];
    /* Addr: h(5B8C0), d(374976) */
    volatile Uint32 rsvd449[16];
    /* Addr: h(5B900), d(375040) */
    volatile CSL_DFE_DPDA_DPDA_PREG_441_REGS dpda_preg_441[24];
    /* Addr: h(5B9C0), d(375232) */
    volatile Uint32 rsvd450[16];
    /* Addr: h(5BA00), d(375296) */
    volatile CSL_DFE_DPDA_DPDA_PREG_442_REGS dpda_preg_442[24];
    /* Addr: h(5BAC0), d(375488) */
    volatile Uint32 rsvd451[16];
    /* Addr: h(5BB00), d(375552) */
    volatile CSL_DFE_DPDA_DPDA_PREG_443_REGS dpda_preg_443[24];
    /* Addr: h(5BBC0), d(375744) */
    volatile Uint32 rsvd452[16];
    /* Addr: h(5BC00), d(375808) */
    volatile CSL_DFE_DPDA_DPDA_PREG_444_REGS dpda_preg_444[24];
    /* Addr: h(5BCC0), d(376000) */
    volatile Uint32 rsvd453[16];
    /* Addr: h(5BD00), d(376064) */
    volatile CSL_DFE_DPDA_DPDA_PREG_445_REGS dpda_preg_445[24];
    /* Addr: h(5BDC0), d(376256) */
    volatile Uint32 rsvd454[16];
    /* Addr: h(5BE00), d(376320) */
    volatile CSL_DFE_DPDA_DPDA_PREG_446_REGS dpda_preg_446[24];
    /* Addr: h(5BEC0), d(376512) */
    volatile Uint32 rsvd455[16];
    /* Addr: h(5BF00), d(376576) */
    volatile CSL_DFE_DPDA_DPDA_PREG_447_REGS dpda_preg_447[24];
    /* Addr: h(5BFC0), d(376768) */
    volatile Uint32 rsvd456[16];
    /* Addr: h(5C000), d(376832) */
    volatile CSL_DFE_DPDA_DPDA_PREG_448_REGS dpda_preg_448[24];
    /* Addr: h(5C0C0), d(377024) */
    volatile Uint32 rsvd457[16];
    /* Addr: h(5C100), d(377088) */
    volatile CSL_DFE_DPDA_DPDA_PREG_449_REGS dpda_preg_449[24];
    /* Addr: h(5C1C0), d(377280) */
    volatile Uint32 rsvd458[16];
    /* Addr: h(5C200), d(377344) */
    volatile CSL_DFE_DPDA_DPDA_PREG_450_REGS dpda_preg_450[24];
    /* Addr: h(5C2C0), d(377536) */
    volatile Uint32 rsvd459[16];
    /* Addr: h(5C300), d(377600) */
    volatile CSL_DFE_DPDA_DPDA_PREG_451_REGS dpda_preg_451[24];
    /* Addr: h(5C3C0), d(377792) */
    volatile Uint32 rsvd460[16];
    /* Addr: h(5C400), d(377856) */
    volatile CSL_DFE_DPDA_DPDA_PREG_452_REGS dpda_preg_452[24];
    /* Addr: h(5C4C0), d(378048) */
    volatile Uint32 rsvd461[16];
    /* Addr: h(5C500), d(378112) */
    volatile CSL_DFE_DPDA_DPDA_PREG_453_REGS dpda_preg_453[24];
    /* Addr: h(5C5C0), d(378304) */
    volatile Uint32 rsvd462[16];
    /* Addr: h(5C600), d(378368) */
    volatile CSL_DFE_DPDA_DPDA_PREG_454_REGS dpda_preg_454[24];
    /* Addr: h(5C6C0), d(378560) */
    volatile Uint32 rsvd463[16];
    /* Addr: h(5C700), d(378624) */
    volatile CSL_DFE_DPDA_DPDA_PREG_455_REGS dpda_preg_455[24];
    /* Addr: h(5C7C0), d(378816) */
    volatile Uint32 rsvd464[16];
    /* Addr: h(5C800), d(378880) */
    volatile CSL_DFE_DPDA_DPDA_PREG_456_REGS dpda_preg_456[24];
    /* Addr: h(5C8C0), d(379072) */
    volatile Uint32 rsvd465[16];
    /* Addr: h(5C900), d(379136) */
    volatile CSL_DFE_DPDA_DPDA_PREG_457_REGS dpda_preg_457[24];
    /* Addr: h(5C9C0), d(379328) */
    volatile Uint32 rsvd466[16];
    /* Addr: h(5CA00), d(379392) */
    volatile CSL_DFE_DPDA_DPDA_PREG_458_REGS dpda_preg_458[24];
    /* Addr: h(5CAC0), d(379584) */
    volatile Uint32 rsvd467[16];
    /* Addr: h(5CB00), d(379648) */
    volatile CSL_DFE_DPDA_DPDA_PREG_459_REGS dpda_preg_459[24];
    /* Addr: h(5CBC0), d(379840) */
    volatile Uint32 rsvd468[16];
    /* Addr: h(5CC00), d(379904) */
    volatile CSL_DFE_DPDA_DPDA_PREG_460_REGS dpda_preg_460[24];
    /* Addr: h(5CCC0), d(380096) */
    volatile Uint32 rsvd469[16];
    /* Addr: h(5CD00), d(380160) */
    volatile CSL_DFE_DPDA_DPDA_PREG_461_REGS dpda_preg_461[24];
    /* Addr: h(5CDC0), d(380352) */
    volatile Uint32 rsvd470[16];
    /* Addr: h(5CE00), d(380416) */
    volatile CSL_DFE_DPDA_DPDA_PREG_462_REGS dpda_preg_462[24];
    /* Addr: h(5CEC0), d(380608) */
    volatile Uint32 rsvd471[16];
    /* Addr: h(5CF00), d(380672) */
    volatile CSL_DFE_DPDA_DPDA_PREG_463_REGS dpda_preg_463[24];
    /* Addr: h(5CFC0), d(380864) */
    volatile Uint32 rsvd472[16];
    /* Addr: h(5D000), d(380928) */
    volatile CSL_DFE_DPDA_DPDA_PREG_464_REGS dpda_preg_464[24];
    /* Addr: h(5D0C0), d(381120) */
    volatile Uint32 rsvd473[16];
    /* Addr: h(5D100), d(381184) */
    volatile CSL_DFE_DPDA_DPDA_PREG_465_REGS dpda_preg_465[24];
    /* Addr: h(5D1C0), d(381376) */
    volatile Uint32 rsvd474[16];
    /* Addr: h(5D200), d(381440) */
    volatile CSL_DFE_DPDA_DPDA_PREG_466_REGS dpda_preg_466[24];
    /* Addr: h(5D2C0), d(381632) */
    volatile Uint32 rsvd475[16];
    /* Addr: h(5D300), d(381696) */
    volatile CSL_DFE_DPDA_DPDA_PREG_467_REGS dpda_preg_467[24];
    /* Addr: h(5D3C0), d(381888) */
    volatile Uint32 rsvd476[16];
    /* Addr: h(5D400), d(381952) */
    volatile CSL_DFE_DPDA_DPDA_PREG_468_REGS dpda_preg_468[24];
    /* Addr: h(5D4C0), d(382144) */
    volatile Uint32 rsvd477[16];
    /* Addr: h(5D500), d(382208) */
    volatile CSL_DFE_DPDA_DPDA_PREG_469_REGS dpda_preg_469[24];
    /* Addr: h(5D5C0), d(382400) */
    volatile Uint32 rsvd478[16];
    /* Addr: h(5D600), d(382464) */
    volatile CSL_DFE_DPDA_DPDA_PREG_470_REGS dpda_preg_470[24];
    /* Addr: h(5D6C0), d(382656) */
    volatile Uint32 rsvd479[16];
    /* Addr: h(5D700), d(382720) */
    volatile CSL_DFE_DPDA_DPDA_PREG_471_REGS dpda_preg_471[24];
    /* Addr: h(5D7C0), d(382912) */
    volatile Uint32 rsvd480[16];
    /* Addr: h(5D800), d(382976) */
    volatile CSL_DFE_DPDA_DPDA_PREG_472_REGS dpda_preg_472[24];
    /* Addr: h(5D8C0), d(383168) */
    volatile Uint32 rsvd481[16];
    /* Addr: h(5D900), d(383232) */
    volatile CSL_DFE_DPDA_DPDA_PREG_473_REGS dpda_preg_473[24];
    /* Addr: h(5D9C0), d(383424) */
    volatile Uint32 rsvd482[16];
    /* Addr: h(5DA00), d(383488) */
    volatile CSL_DFE_DPDA_DPDA_PREG_474_REGS dpda_preg_474[24];
    /* Addr: h(5DAC0), d(383680) */
    volatile Uint32 rsvd483[16];
    /* Addr: h(5DB00), d(383744) */
    volatile CSL_DFE_DPDA_DPDA_PREG_475_REGS dpda_preg_475[24];
    /* Addr: h(5DBC0), d(383936) */
    volatile Uint32 rsvd484[16];
    /* Addr: h(5DC00), d(384000) */
    volatile CSL_DFE_DPDA_DPDA_PREG_476_REGS dpda_preg_476[24];
    /* Addr: h(5DCC0), d(384192) */
    volatile Uint32 rsvd485[16];
    /* Addr: h(5DD00), d(384256) */
    volatile CSL_DFE_DPDA_DPDA_PREG_477_REGS dpda_preg_477[24];
    /* Addr: h(5DDC0), d(384448) */
    volatile Uint32 rsvd486[16];
    /* Addr: h(5DE00), d(384512) */
    volatile CSL_DFE_DPDA_DPDA_PREG_478_REGS dpda_preg_478[24];
    /* Addr: h(5DEC0), d(384704) */
    volatile Uint32 rsvd487[16];
    /* Addr: h(5DF00), d(384768) */
    volatile CSL_DFE_DPDA_DPDA_PREG_479_REGS dpda_preg_479[24];
    /* Addr: h(5DFC0), d(384960) */
    volatile Uint32 rsvd488[16];
    /* Addr: h(5E000), d(385024) */
    volatile CSL_DFE_DPDA_DPDA_PREG_480_REGS dpda_preg_480[24];
    /* Addr: h(5E0C0), d(385216) */
    volatile Uint32 rsvd489[16];
    /* Addr: h(5E100), d(385280) */
    volatile CSL_DFE_DPDA_DPDA_PREG_481_REGS dpda_preg_481[24];
    /* Addr: h(5E1C0), d(385472) */
    volatile Uint32 rsvd490[16];
    /* Addr: h(5E200), d(385536) */
    volatile CSL_DFE_DPDA_DPDA_PREG_482_REGS dpda_preg_482[24];
    /* Addr: h(5E2C0), d(385728) */
    volatile Uint32 rsvd491[16];
    /* Addr: h(5E300), d(385792) */
    volatile CSL_DFE_DPDA_DPDA_PREG_483_REGS dpda_preg_483[24];
    /* Addr: h(5E3C0), d(385984) */
    volatile Uint32 rsvd492[16];
    /* Addr: h(5E400), d(386048) */
    volatile CSL_DFE_DPDA_DPDA_PREG_484_REGS dpda_preg_484[24];
    /* Addr: h(5E4C0), d(386240) */
    volatile Uint32 rsvd493[16];
    /* Addr: h(5E500), d(386304) */
    volatile CSL_DFE_DPDA_DPDA_PREG_485_REGS dpda_preg_485[24];
    /* Addr: h(5E5C0), d(386496) */
    volatile Uint32 rsvd494[16];
    /* Addr: h(5E600), d(386560) */
    volatile CSL_DFE_DPDA_DPDA_PREG_486_REGS dpda_preg_486[24];
    /* Addr: h(5E6C0), d(386752) */
    volatile Uint32 rsvd495[16];
    /* Addr: h(5E700), d(386816) */
    volatile CSL_DFE_DPDA_DPDA_PREG_487_REGS dpda_preg_487[24];
    /* Addr: h(5E7C0), d(387008) */
    volatile Uint32 rsvd496[16];
    /* Addr: h(5E800), d(387072) */
    volatile CSL_DFE_DPDA_DPDA_PREG_488_REGS dpda_preg_488[24];
    /* Addr: h(5E8C0), d(387264) */
    volatile Uint32 rsvd497[16];
    /* Addr: h(5E900), d(387328) */
    volatile CSL_DFE_DPDA_DPDA_PREG_489_REGS dpda_preg_489[24];
    /* Addr: h(5E9C0), d(387520) */
    volatile Uint32 rsvd498[16];
    /* Addr: h(5EA00), d(387584) */
    volatile CSL_DFE_DPDA_DPDA_PREG_490_REGS dpda_preg_490[24];
    /* Addr: h(5EAC0), d(387776) */
    volatile Uint32 rsvd499[16];
    /* Addr: h(5EB00), d(387840) */
    volatile CSL_DFE_DPDA_DPDA_PREG_491_REGS dpda_preg_491[24];
    /* Addr: h(5EBC0), d(388032) */
    volatile Uint32 rsvd500[16];
    /* Addr: h(5EC00), d(388096) */
    volatile CSL_DFE_DPDA_DPDA_PREG_492_REGS dpda_preg_492[24];
    /* Addr: h(5ECC0), d(388288) */
    volatile Uint32 rsvd501[16];
    /* Addr: h(5ED00), d(388352) */
    volatile CSL_DFE_DPDA_DPDA_PREG_493_REGS dpda_preg_493[24];
    /* Addr: h(5EDC0), d(388544) */
    volatile Uint32 rsvd502[16];
    /* Addr: h(5EE00), d(388608) */
    volatile CSL_DFE_DPDA_DPDA_PREG_494_REGS dpda_preg_494[24];
    /* Addr: h(5EEC0), d(388800) */
    volatile Uint32 rsvd503[16];
    /* Addr: h(5EF00), d(388864) */
    volatile CSL_DFE_DPDA_DPDA_PREG_495_REGS dpda_preg_495[24];
    /* Addr: h(5EFC0), d(389056) */
    volatile Uint32 rsvd504[16];
    /* Addr: h(5F000), d(389120) */
    volatile CSL_DFE_DPDA_DPDA_PREG_496_REGS dpda_preg_496[24];
    /* Addr: h(5F0C0), d(389312) */
    volatile Uint32 rsvd505[16];
    /* Addr: h(5F100), d(389376) */
    volatile CSL_DFE_DPDA_DPDA_PREG_497_REGS dpda_preg_497[24];
    /* Addr: h(5F1C0), d(389568) */
    volatile Uint32 rsvd506[16];
    /* Addr: h(5F200), d(389632) */
    volatile CSL_DFE_DPDA_DPDA_PREG_498_REGS dpda_preg_498[24];
    /* Addr: h(5F2C0), d(389824) */
    volatile Uint32 rsvd507[16];
    /* Addr: h(5F300), d(389888) */
    volatile CSL_DFE_DPDA_DPDA_PREG_499_REGS dpda_preg_499[24];
    /* Addr: h(5F3C0), d(390080) */
    volatile Uint32 rsvd508[16];
    /* Addr: h(5F400), d(390144) */
    volatile CSL_DFE_DPDA_DPDA_PREG_500_REGS dpda_preg_500[24];
    /* Addr: h(5F4C0), d(390336) */
    volatile Uint32 rsvd509[16];
    /* Addr: h(5F500), d(390400) */
    volatile CSL_DFE_DPDA_DPDA_PREG_501_REGS dpda_preg_501[24];
    /* Addr: h(5F5C0), d(390592) */
    volatile Uint32 rsvd510[16];
    /* Addr: h(5F600), d(390656) */
    volatile CSL_DFE_DPDA_DPDA_PREG_502_REGS dpda_preg_502[24];
    /* Addr: h(5F6C0), d(390848) */
    volatile Uint32 rsvd511[16];
    /* Addr: h(5F700), d(390912) */
    volatile CSL_DFE_DPDA_DPDA_PREG_503_REGS dpda_preg_503[24];
    /* Addr: h(5F7C0), d(391104) */
    volatile Uint32 rsvd512[16];
    /* Addr: h(5F800), d(391168) */
    volatile CSL_DFE_DPDA_DPDA_PREG_504_REGS dpda_preg_504[24];
    /* Addr: h(5F8C0), d(391360) */
    volatile Uint32 rsvd513[16];
    /* Addr: h(5F900), d(391424) */
    volatile CSL_DFE_DPDA_DPDA_PREG_505_REGS dpda_preg_505[24];
    /* Addr: h(5F9C0), d(391616) */
    volatile Uint32 rsvd514[16];
    /* Addr: h(5FA00), d(391680) */
    volatile CSL_DFE_DPDA_DPDA_PREG_506_REGS dpda_preg_506[24];
    /* Addr: h(5FAC0), d(391872) */
    volatile Uint32 rsvd515[16];
    /* Addr: h(5FB00), d(391936) */
    volatile CSL_DFE_DPDA_DPDA_PREG_507_REGS dpda_preg_507[24];
    /* Addr: h(5FBC0), d(392128) */
    volatile Uint32 rsvd516[16];
    /* Addr: h(5FC00), d(392192) */
    volatile CSL_DFE_DPDA_DPDA_PREG_508_REGS dpda_preg_508[24];
    /* Addr: h(5FCC0), d(392384) */
    volatile Uint32 rsvd517[16];
    /* Addr: h(5FD00), d(392448) */
    volatile CSL_DFE_DPDA_DPDA_PREG_509_REGS dpda_preg_509[24];
    /* Addr: h(5FDC0), d(392640) */
    volatile Uint32 rsvd518[16];
    /* Addr: h(5FE00), d(392704) */
    volatile CSL_DFE_DPDA_DPDA_PREG_510_REGS dpda_preg_510[24];
    /* Addr: h(5FEC0), d(392896) */
    volatile Uint32 rsvd519[16];
    /* Addr: h(5FF00), d(392960) */
    volatile CSL_DFE_DPDA_DPDA_PREG_511_REGS dpda_preg_511[24];
    /* Addr: h(5FFC0), d(393152) */
    volatile Uint32 rsvd520[16];
    /* Addr: h(60000), d(393216) */
    volatile CSL_DFE_DPDA_DPDA_PREG_512_REGS dpda_preg_512[24];
    /* Addr: h(600C0), d(393408) */
    volatile Uint32 rsvd521[16];
    /* Addr: h(60100), d(393472) */
    volatile CSL_DFE_DPDA_DPDA_PREG_513_REGS dpda_preg_513[24];
    /* Addr: h(601C0), d(393664) */
    volatile Uint32 rsvd522[16];
    /* Addr: h(60200), d(393728) */
    volatile CSL_DFE_DPDA_DPDA_PREG_514_REGS dpda_preg_514[24];
    /* Addr: h(602C0), d(393920) */
    volatile Uint32 rsvd523[16];
    /* Addr: h(60300), d(393984) */
    volatile CSL_DFE_DPDA_DPDA_PREG_515_REGS dpda_preg_515[24];
    /* Addr: h(603C0), d(394176) */
    volatile Uint32 rsvd524[16];
    /* Addr: h(60400), d(394240) */
    volatile CSL_DFE_DPDA_DPDA_PREG_516_REGS dpda_preg_516[24];
    /* Addr: h(604C0), d(394432) */
    volatile Uint32 rsvd525[16];
    /* Addr: h(60500), d(394496) */
    volatile CSL_DFE_DPDA_DPDA_PREG_517_REGS dpda_preg_517[24];
    /* Addr: h(605C0), d(394688) */
    volatile Uint32 rsvd526[16];
    /* Addr: h(60600), d(394752) */
    volatile CSL_DFE_DPDA_DPDA_PREG_518_REGS dpda_preg_518[24];
    /* Addr: h(606C0), d(394944) */
    volatile Uint32 rsvd527[16];
    /* Addr: h(60700), d(395008) */
    volatile CSL_DFE_DPDA_DPDA_PREG_519_REGS dpda_preg_519[24];
    /* Addr: h(607C0), d(395200) */
    volatile Uint32 rsvd528[16];
    /* Addr: h(60800), d(395264) */
    volatile CSL_DFE_DPDA_DPDA_PREG_520_REGS dpda_preg_520[24];
    /* Addr: h(608C0), d(395456) */
    volatile Uint32 rsvd529[16];
    /* Addr: h(60900), d(395520) */
    volatile CSL_DFE_DPDA_DPDA_PREG_521_REGS dpda_preg_521[24];
    /* Addr: h(609C0), d(395712) */
    volatile Uint32 rsvd530[16];
    /* Addr: h(60A00), d(395776) */
    volatile CSL_DFE_DPDA_DPDA_PREG_522_REGS dpda_preg_522[24];
    /* Addr: h(60AC0), d(395968) */
    volatile Uint32 rsvd531[16];
    /* Addr: h(60B00), d(396032) */
    volatile CSL_DFE_DPDA_DPDA_PREG_523_REGS dpda_preg_523[24];
    /* Addr: h(60BC0), d(396224) */
    volatile Uint32 rsvd532[16];
    /* Addr: h(60C00), d(396288) */
    volatile CSL_DFE_DPDA_DPDA_PREG_524_REGS dpda_preg_524[24];
    /* Addr: h(60CC0), d(396480) */
    volatile Uint32 rsvd533[16];
    /* Addr: h(60D00), d(396544) */
    volatile CSL_DFE_DPDA_DPDA_PREG_525_REGS dpda_preg_525[24];
    /* Addr: h(60DC0), d(396736) */
    volatile Uint32 rsvd534[16];
    /* Addr: h(60E00), d(396800) */
    volatile CSL_DFE_DPDA_DPDA_PREG_526_REGS dpda_preg_526[24];
    /* Addr: h(60EC0), d(396992) */
    volatile Uint32 rsvd535[16];
    /* Addr: h(60F00), d(397056) */
    volatile CSL_DFE_DPDA_DPDA_PREG_527_REGS dpda_preg_527[24];
    /* Addr: h(60FC0), d(397248) */
    volatile Uint32 rsvd536[16];
    /* Addr: h(61000), d(397312) */
    volatile CSL_DFE_DPDA_DPDA_PREG_528_REGS dpda_preg_528[24];
    /* Addr: h(610C0), d(397504) */
    volatile Uint32 rsvd537[16];
    /* Addr: h(61100), d(397568) */
    volatile CSL_DFE_DPDA_DPDA_PREG_529_REGS dpda_preg_529[24];
    /* Addr: h(611C0), d(397760) */
    volatile Uint32 rsvd538[16];
    /* Addr: h(61200), d(397824) */
    volatile CSL_DFE_DPDA_DPDA_PREG_530_REGS dpda_preg_530[24];
    /* Addr: h(612C0), d(398016) */
    volatile Uint32 rsvd539[16];
    /* Addr: h(61300), d(398080) */
    volatile CSL_DFE_DPDA_DPDA_PREG_531_REGS dpda_preg_531[24];
    /* Addr: h(613C0), d(398272) */
    volatile Uint32 rsvd540[16];
    /* Addr: h(61400), d(398336) */
    volatile CSL_DFE_DPDA_DPDA_PREG_532_REGS dpda_preg_532[24];
    /* Addr: h(614C0), d(398528) */
    volatile Uint32 rsvd541[16];
    /* Addr: h(61500), d(398592) */
    volatile CSL_DFE_DPDA_DPDA_PREG_533_REGS dpda_preg_533[24];
    /* Addr: h(615C0), d(398784) */
    volatile Uint32 rsvd542[16];
    /* Addr: h(61600), d(398848) */
    volatile CSL_DFE_DPDA_DPDA_PREG_534_REGS dpda_preg_534[24];
    /* Addr: h(616C0), d(399040) */
    volatile Uint32 rsvd543[16];
    /* Addr: h(61700), d(399104) */
    volatile CSL_DFE_DPDA_DPDA_PREG_535_REGS dpda_preg_535[24];
    /* Addr: h(617C0), d(399296) */
    volatile Uint32 rsvd544[16];
    /* Addr: h(61800), d(399360) */
    volatile CSL_DFE_DPDA_DPDA_PREG_536_REGS dpda_preg_536[24];
    /* Addr: h(618C0), d(399552) */
    volatile Uint32 rsvd545[16];
    /* Addr: h(61900), d(399616) */
    volatile CSL_DFE_DPDA_DPDA_PREG_537_REGS dpda_preg_537[24];
    /* Addr: h(619C0), d(399808) */
    volatile Uint32 rsvd546[16];
    /* Addr: h(61A00), d(399872) */
    volatile CSL_DFE_DPDA_DPDA_PREG_538_REGS dpda_preg_538[24];
    /* Addr: h(61AC0), d(400064) */
    volatile Uint32 rsvd547[16];
    /* Addr: h(61B00), d(400128) */
    volatile CSL_DFE_DPDA_DPDA_PREG_539_REGS dpda_preg_539[24];
    /* Addr: h(61BC0), d(400320) */
    volatile Uint32 rsvd548[16];
    /* Addr: h(61C00), d(400384) */
    volatile CSL_DFE_DPDA_DPDA_PREG_540_REGS dpda_preg_540[24];
    /* Addr: h(61CC0), d(400576) */
    volatile Uint32 rsvd549[16];
    /* Addr: h(61D00), d(400640) */
    volatile CSL_DFE_DPDA_DPDA_PREG_541_REGS dpda_preg_541[24];
    /* Addr: h(61DC0), d(400832) */
    volatile Uint32 rsvd550[16];
    /* Addr: h(61E00), d(400896) */
    volatile CSL_DFE_DPDA_DPDA_PREG_542_REGS dpda_preg_542[24];
    /* Addr: h(61EC0), d(401088) */
    volatile Uint32 rsvd551[16];
    /* Addr: h(61F00), d(401152) */
    volatile CSL_DFE_DPDA_DPDA_PREG_543_REGS dpda_preg_543[24];
    /* Addr: h(61FC0), d(401344) */
    volatile Uint32 rsvd552[16];
    /* Addr: h(62000), d(401408) */
    volatile CSL_DFE_DPDA_DPDA_PREG_544_REGS dpda_preg_544[24];
    /* Addr: h(620C0), d(401600) */
    volatile Uint32 rsvd553[16];
    /* Addr: h(62100), d(401664) */
    volatile CSL_DFE_DPDA_DPDA_PREG_545_REGS dpda_preg_545[24];
    /* Addr: h(621C0), d(401856) */
    volatile Uint32 rsvd554[16];
    /* Addr: h(62200), d(401920) */
    volatile CSL_DFE_DPDA_DPDA_PREG_546_REGS dpda_preg_546[24];
    /* Addr: h(622C0), d(402112) */
    volatile Uint32 rsvd555[16];
    /* Addr: h(62300), d(402176) */
    volatile CSL_DFE_DPDA_DPDA_PREG_547_REGS dpda_preg_547[24];
    /* Addr: h(623C0), d(402368) */
    volatile Uint32 rsvd556[16];
    /* Addr: h(62400), d(402432) */
    volatile CSL_DFE_DPDA_DPDA_PREG_548_REGS dpda_preg_548[24];
    /* Addr: h(624C0), d(402624) */
    volatile Uint32 rsvd557[16];
    /* Addr: h(62500), d(402688) */
    volatile CSL_DFE_DPDA_DPDA_PREG_549_REGS dpda_preg_549[24];
    /* Addr: h(625C0), d(402880) */
    volatile Uint32 rsvd558[16];
    /* Addr: h(62600), d(402944) */
    volatile CSL_DFE_DPDA_DPDA_PREG_550_REGS dpda_preg_550[24];
    /* Addr: h(626C0), d(403136) */
    volatile Uint32 rsvd559[16];
    /* Addr: h(62700), d(403200) */
    volatile CSL_DFE_DPDA_DPDA_PREG_551_REGS dpda_preg_551[24];
    /* Addr: h(627C0), d(403392) */
    volatile Uint32 rsvd560[16];
    /* Addr: h(62800), d(403456) */
    volatile CSL_DFE_DPDA_DPDA_PREG_552_REGS dpda_preg_552[24];
    /* Addr: h(628C0), d(403648) */
    volatile Uint32 rsvd561[16];
    /* Addr: h(62900), d(403712) */
    volatile CSL_DFE_DPDA_DPDA_PREG_553_REGS dpda_preg_553[24];
    /* Addr: h(629C0), d(403904) */
    volatile Uint32 rsvd562[16];
    /* Addr: h(62A00), d(403968) */
    volatile CSL_DFE_DPDA_DPDA_PREG_554_REGS dpda_preg_554[24];
    /* Addr: h(62AC0), d(404160) */
    volatile Uint32 rsvd563[16];
    /* Addr: h(62B00), d(404224) */
    volatile CSL_DFE_DPDA_DPDA_PREG_555_REGS dpda_preg_555[24];
    /* Addr: h(62BC0), d(404416) */
    volatile Uint32 rsvd564[16];
    /* Addr: h(62C00), d(404480) */
    volatile CSL_DFE_DPDA_DPDA_PREG_556_REGS dpda_preg_556[24];
    /* Addr: h(62CC0), d(404672) */
    volatile Uint32 rsvd565[16];
    /* Addr: h(62D00), d(404736) */
    volatile CSL_DFE_DPDA_DPDA_PREG_557_REGS dpda_preg_557[24];
    /* Addr: h(62DC0), d(404928) */
    volatile Uint32 rsvd566[16];
    /* Addr: h(62E00), d(404992) */
    volatile CSL_DFE_DPDA_DPDA_PREG_558_REGS dpda_preg_558[24];
    /* Addr: h(62EC0), d(405184) */
    volatile Uint32 rsvd567[16];
    /* Addr: h(62F00), d(405248) */
    volatile CSL_DFE_DPDA_DPDA_PREG_559_REGS dpda_preg_559[24];
    /* Addr: h(62FC0), d(405440) */
    volatile Uint32 rsvd568[16];
    /* Addr: h(63000), d(405504) */
    volatile CSL_DFE_DPDA_DPDA_PREG_560_REGS dpda_preg_560[24];
    /* Addr: h(630C0), d(405696) */
    volatile Uint32 rsvd569[16];
    /* Addr: h(63100), d(405760) */
    volatile CSL_DFE_DPDA_DPDA_PREG_561_REGS dpda_preg_561[24];
    /* Addr: h(631C0), d(405952) */
    volatile Uint32 rsvd570[16];
    /* Addr: h(63200), d(406016) */
    volatile CSL_DFE_DPDA_DPDA_PREG_562_REGS dpda_preg_562[24];
    /* Addr: h(632C0), d(406208) */
    volatile Uint32 rsvd571[16];
    /* Addr: h(63300), d(406272) */
    volatile CSL_DFE_DPDA_DPDA_PREG_563_REGS dpda_preg_563[24];
    /* Addr: h(633C0), d(406464) */
    volatile Uint32 rsvd572[16];
    /* Addr: h(63400), d(406528) */
    volatile CSL_DFE_DPDA_DPDA_PREG_564_REGS dpda_preg_564[24];
    /* Addr: h(634C0), d(406720) */
    volatile Uint32 rsvd573[16];
    /* Addr: h(63500), d(406784) */
    volatile CSL_DFE_DPDA_DPDA_PREG_565_REGS dpda_preg_565[24];
    /* Addr: h(635C0), d(406976) */
    volatile Uint32 rsvd574[16];
    /* Addr: h(63600), d(407040) */
    volatile CSL_DFE_DPDA_DPDA_PREG_566_REGS dpda_preg_566[24];
    /* Addr: h(636C0), d(407232) */
    volatile Uint32 rsvd575[16];
    /* Addr: h(63700), d(407296) */
    volatile CSL_DFE_DPDA_DPDA_PREG_567_REGS dpda_preg_567[24];
    /* Addr: h(637C0), d(407488) */
    volatile Uint32 rsvd576[16];
    /* Addr: h(63800), d(407552) */
    volatile CSL_DFE_DPDA_DPDA_PREG_568_REGS dpda_preg_568[24];
    /* Addr: h(638C0), d(407744) */
    volatile Uint32 rsvd577[16];
    /* Addr: h(63900), d(407808) */
    volatile CSL_DFE_DPDA_DPDA_PREG_569_REGS dpda_preg_569[24];
    /* Addr: h(639C0), d(408000) */
    volatile Uint32 rsvd578[16];
    /* Addr: h(63A00), d(408064) */
    volatile CSL_DFE_DPDA_DPDA_PREG_570_REGS dpda_preg_570[24];
    /* Addr: h(63AC0), d(408256) */
    volatile Uint32 rsvd579[16];
    /* Addr: h(63B00), d(408320) */
    volatile CSL_DFE_DPDA_DPDA_PREG_571_REGS dpda_preg_571[24];
    /* Addr: h(63BC0), d(408512) */
    volatile Uint32 rsvd580[16];
    /* Addr: h(63C00), d(408576) */
    volatile CSL_DFE_DPDA_DPDA_PREG_572_REGS dpda_preg_572[24];
    /* Addr: h(63CC0), d(408768) */
    volatile Uint32 rsvd581[16];
    /* Addr: h(63D00), d(408832) */
    volatile CSL_DFE_DPDA_DPDA_PREG_573_REGS dpda_preg_573[24];
    /* Addr: h(63DC0), d(409024) */
    volatile Uint32 rsvd582[16];
    /* Addr: h(63E00), d(409088) */
    volatile CSL_DFE_DPDA_DPDA_PREG_574_REGS dpda_preg_574[24];
    /* Addr: h(63EC0), d(409280) */
    volatile Uint32 rsvd583[16];
    /* Addr: h(63F00), d(409344) */
    volatile CSL_DFE_DPDA_DPDA_PREG_575_REGS dpda_preg_575[24];
    /* Addr: h(63FC0), d(409536) */
    volatile Uint32 rsvd584[16];
    /* Addr: h(64000), d(409600) */
    volatile CSL_DFE_DPDA_DPDA_PREG_576_REGS dpda_preg_576[24];
    /* Addr: h(640C0), d(409792) */
    volatile Uint32 rsvd585[16];
    /* Addr: h(64100), d(409856) */
    volatile CSL_DFE_DPDA_DPDA_PREG_577_REGS dpda_preg_577[24];
    /* Addr: h(641C0), d(410048) */
    volatile Uint32 rsvd586[16];
    /* Addr: h(64200), d(410112) */
    volatile CSL_DFE_DPDA_DPDA_PREG_578_REGS dpda_preg_578[24];
    /* Addr: h(642C0), d(410304) */
    volatile Uint32 rsvd587[16];
    /* Addr: h(64300), d(410368) */
    volatile CSL_DFE_DPDA_DPDA_PREG_579_REGS dpda_preg_579[24];
    /* Addr: h(643C0), d(410560) */
    volatile Uint32 rsvd588[16];
    /* Addr: h(64400), d(410624) */
    volatile CSL_DFE_DPDA_DPDA_PREG_580_REGS dpda_preg_580[24];
    /* Addr: h(644C0), d(410816) */
    volatile Uint32 rsvd589[16];
    /* Addr: h(64500), d(410880) */
    volatile CSL_DFE_DPDA_DPDA_PREG_581_REGS dpda_preg_581[24];
    /* Addr: h(645C0), d(411072) */
    volatile Uint32 rsvd590[16];
    /* Addr: h(64600), d(411136) */
    volatile CSL_DFE_DPDA_DPDA_PREG_582_REGS dpda_preg_582[24];
    /* Addr: h(646C0), d(411328) */
    volatile Uint32 rsvd591[16];
    /* Addr: h(64700), d(411392) */
    volatile CSL_DFE_DPDA_DPDA_PREG_583_REGS dpda_preg_583[24];
    /* Addr: h(647C0), d(411584) */
    volatile Uint32 rsvd592[16];
    /* Addr: h(64800), d(411648) */
    volatile CSL_DFE_DPDA_DPDA_PREG_584_REGS dpda_preg_584[24];
    /* Addr: h(648C0), d(411840) */
    volatile Uint32 rsvd593[16];
    /* Addr: h(64900), d(411904) */
    volatile CSL_DFE_DPDA_DPDA_PREG_585_REGS dpda_preg_585[24];
    /* Addr: h(649C0), d(412096) */
    volatile Uint32 rsvd594[16];
    /* Addr: h(64A00), d(412160) */
    volatile CSL_DFE_DPDA_DPDA_PREG_586_REGS dpda_preg_586[24];
    /* Addr: h(64AC0), d(412352) */
    volatile Uint32 rsvd595[16];
    /* Addr: h(64B00), d(412416) */
    volatile CSL_DFE_DPDA_DPDA_PREG_587_REGS dpda_preg_587[24];
    /* Addr: h(64BC0), d(412608) */
    volatile Uint32 rsvd596[16];
    /* Addr: h(64C00), d(412672) */
    volatile CSL_DFE_DPDA_DPDA_PREG_588_REGS dpda_preg_588[24];
    /* Addr: h(64CC0), d(412864) */
    volatile Uint32 rsvd597[16];
    /* Addr: h(64D00), d(412928) */
    volatile CSL_DFE_DPDA_DPDA_PREG_589_REGS dpda_preg_589[24];
    /* Addr: h(64DC0), d(413120) */
    volatile Uint32 rsvd598[16];
    /* Addr: h(64E00), d(413184) */
    volatile CSL_DFE_DPDA_DPDA_PREG_590_REGS dpda_preg_590[24];
    /* Addr: h(64EC0), d(413376) */
    volatile Uint32 rsvd599[16];
    /* Addr: h(64F00), d(413440) */
    volatile CSL_DFE_DPDA_DPDA_PREG_591_REGS dpda_preg_591[24];
    /* Addr: h(64FC0), d(413632) */
    volatile Uint32 rsvd600[16];
    /* Addr: h(65000), d(413696) */
    volatile CSL_DFE_DPDA_DPDA_PREG_592_REGS dpda_preg_592[24];
    /* Addr: h(650C0), d(413888) */
    volatile Uint32 rsvd601[16];
    /* Addr: h(65100), d(413952) */
    volatile CSL_DFE_DPDA_DPDA_PREG_593_REGS dpda_preg_593[24];
    /* Addr: h(651C0), d(414144) */
    volatile Uint32 rsvd602[16];
    /* Addr: h(65200), d(414208) */
    volatile CSL_DFE_DPDA_DPDA_PREG_594_REGS dpda_preg_594[24];
    /* Addr: h(652C0), d(414400) */
    volatile Uint32 rsvd603[16];
    /* Addr: h(65300), d(414464) */
    volatile CSL_DFE_DPDA_DPDA_PREG_595_REGS dpda_preg_595[24];
    /* Addr: h(653C0), d(414656) */
    volatile Uint32 rsvd604[16];
    /* Addr: h(65400), d(414720) */
    volatile CSL_DFE_DPDA_DPDA_PREG_596_REGS dpda_preg_596[24];
    /* Addr: h(654C0), d(414912) */
    volatile Uint32 rsvd605[16];
    /* Addr: h(65500), d(414976) */
    volatile CSL_DFE_DPDA_DPDA_PREG_597_REGS dpda_preg_597[24];
    /* Addr: h(655C0), d(415168) */
    volatile Uint32 rsvd606[16];
    /* Addr: h(65600), d(415232) */
    volatile CSL_DFE_DPDA_DPDA_PREG_598_REGS dpda_preg_598[24];
    /* Addr: h(656C0), d(415424) */
    volatile Uint32 rsvd607[16];
    /* Addr: h(65700), d(415488) */
    volatile CSL_DFE_DPDA_DPDA_PREG_599_REGS dpda_preg_599[24];
    /* Addr: h(657C0), d(415680) */
    volatile Uint32 rsvd608[16];
    /* Addr: h(65800), d(415744) */
    volatile CSL_DFE_DPDA_DPDA_PREG_600_REGS dpda_preg_600[24];
    /* Addr: h(658C0), d(415936) */
    volatile Uint32 rsvd609[16];
    /* Addr: h(65900), d(416000) */
    volatile CSL_DFE_DPDA_DPDA_PREG_601_REGS dpda_preg_601[24];
    /* Addr: h(659C0), d(416192) */
    volatile Uint32 rsvd610[16];
    /* Addr: h(65A00), d(416256) */
    volatile CSL_DFE_DPDA_DPDA_PREG_602_REGS dpda_preg_602[24];
    /* Addr: h(65AC0), d(416448) */
    volatile Uint32 rsvd611[16];
    /* Addr: h(65B00), d(416512) */
    volatile CSL_DFE_DPDA_DPDA_PREG_603_REGS dpda_preg_603[24];
    /* Addr: h(65BC0), d(416704) */
    volatile Uint32 rsvd612[16];
    /* Addr: h(65C00), d(416768) */
    volatile CSL_DFE_DPDA_DPDA_PREG_604_REGS dpda_preg_604[24];
    /* Addr: h(65CC0), d(416960) */
    volatile Uint32 rsvd613[16];
    /* Addr: h(65D00), d(417024) */
    volatile CSL_DFE_DPDA_DPDA_PREG_605_REGS dpda_preg_605[24];
    /* Addr: h(65DC0), d(417216) */
    volatile Uint32 rsvd614[16];
    /* Addr: h(65E00), d(417280) */
    volatile CSL_DFE_DPDA_DPDA_PREG_606_REGS dpda_preg_606[24];
    /* Addr: h(65EC0), d(417472) */
    volatile Uint32 rsvd615[16];
    /* Addr: h(65F00), d(417536) */
    volatile CSL_DFE_DPDA_DPDA_PREG_607_REGS dpda_preg_607[24];
    /* Addr: h(65FC0), d(417728) */
    volatile Uint32 rsvd616[16];
    /* Addr: h(66000), d(417792) */
    volatile CSL_DFE_DPDA_DPDA_PREG_608_REGS dpda_preg_608[24];
    /* Addr: h(660C0), d(417984) */
    volatile Uint32 rsvd617[16];
    /* Addr: h(66100), d(418048) */
    volatile CSL_DFE_DPDA_DPDA_PREG_609_REGS dpda_preg_609[24];
    /* Addr: h(661C0), d(418240) */
    volatile Uint32 rsvd618[16];
    /* Addr: h(66200), d(418304) */
    volatile CSL_DFE_DPDA_DPDA_PREG_610_REGS dpda_preg_610[24];
    /* Addr: h(662C0), d(418496) */
    volatile Uint32 rsvd619[16];
    /* Addr: h(66300), d(418560) */
    volatile CSL_DFE_DPDA_DPDA_PREG_611_REGS dpda_preg_611[24];
    /* Addr: h(663C0), d(418752) */
    volatile Uint32 rsvd620[16];
    /* Addr: h(66400), d(418816) */
    volatile CSL_DFE_DPDA_DPDA_PREG_612_REGS dpda_preg_612[24];
    /* Addr: h(664C0), d(419008) */
    volatile Uint32 rsvd621[16];
    /* Addr: h(66500), d(419072) */
    volatile CSL_DFE_DPDA_DPDA_PREG_613_REGS dpda_preg_613[24];
    /* Addr: h(665C0), d(419264) */
    volatile Uint32 rsvd622[16];
    /* Addr: h(66600), d(419328) */
    volatile CSL_DFE_DPDA_DPDA_PREG_614_REGS dpda_preg_614[24];
    /* Addr: h(666C0), d(419520) */
    volatile Uint32 rsvd623[16];
    /* Addr: h(66700), d(419584) */
    volatile CSL_DFE_DPDA_DPDA_PREG_615_REGS dpda_preg_615[24];
    /* Addr: h(667C0), d(419776) */
    volatile Uint32 rsvd624[16];
    /* Addr: h(66800), d(419840) */
    volatile CSL_DFE_DPDA_DPDA_PREG_616_REGS dpda_preg_616[24];
    /* Addr: h(668C0), d(420032) */
    volatile Uint32 rsvd625[16];
    /* Addr: h(66900), d(420096) */
    volatile CSL_DFE_DPDA_DPDA_PREG_617_REGS dpda_preg_617[24];
    /* Addr: h(669C0), d(420288) */
    volatile Uint32 rsvd626[16];
    /* Addr: h(66A00), d(420352) */
    volatile CSL_DFE_DPDA_DPDA_PREG_618_REGS dpda_preg_618[24];
    /* Addr: h(66AC0), d(420544) */
    volatile Uint32 rsvd627[16];
    /* Addr: h(66B00), d(420608) */
    volatile CSL_DFE_DPDA_DPDA_PREG_619_REGS dpda_preg_619[24];
    /* Addr: h(66BC0), d(420800) */
    volatile Uint32 rsvd628[16];
    /* Addr: h(66C00), d(420864) */
    volatile CSL_DFE_DPDA_DPDA_PREG_620_REGS dpda_preg_620[24];
    /* Addr: h(66CC0), d(421056) */
    volatile Uint32 rsvd629[16];
    /* Addr: h(66D00), d(421120) */
    volatile CSL_DFE_DPDA_DPDA_PREG_621_REGS dpda_preg_621[24];
    /* Addr: h(66DC0), d(421312) */
    volatile Uint32 rsvd630[16];
    /* Addr: h(66E00), d(421376) */
    volatile CSL_DFE_DPDA_DPDA_PREG_622_REGS dpda_preg_622[24];
    /* Addr: h(66EC0), d(421568) */
    volatile Uint32 rsvd631[16];
    /* Addr: h(66F00), d(421632) */
    volatile CSL_DFE_DPDA_DPDA_PREG_623_REGS dpda_preg_623[24];
    /* Addr: h(66FC0), d(421824) */
    volatile Uint32 rsvd632[16];
    /* Addr: h(67000), d(421888) */
    volatile CSL_DFE_DPDA_DPDA_PREG_624_REGS dpda_preg_624[24];
    /* Addr: h(670C0), d(422080) */
    volatile Uint32 rsvd633[16];
    /* Addr: h(67100), d(422144) */
    volatile CSL_DFE_DPDA_DPDA_PREG_625_REGS dpda_preg_625[24];
    /* Addr: h(671C0), d(422336) */
    volatile Uint32 rsvd634[16];
    /* Addr: h(67200), d(422400) */
    volatile CSL_DFE_DPDA_DPDA_PREG_626_REGS dpda_preg_626[24];
    /* Addr: h(672C0), d(422592) */
    volatile Uint32 rsvd635[16];
    /* Addr: h(67300), d(422656) */
    volatile CSL_DFE_DPDA_DPDA_PREG_627_REGS dpda_preg_627[24];
    /* Addr: h(673C0), d(422848) */
    volatile Uint32 rsvd636[16];
    /* Addr: h(67400), d(422912) */
    volatile CSL_DFE_DPDA_DPDA_PREG_628_REGS dpda_preg_628[24];
    /* Addr: h(674C0), d(423104) */
    volatile Uint32 rsvd637[16];
    /* Addr: h(67500), d(423168) */
    volatile CSL_DFE_DPDA_DPDA_PREG_629_REGS dpda_preg_629[24];
    /* Addr: h(675C0), d(423360) */
    volatile Uint32 rsvd638[16];
    /* Addr: h(67600), d(423424) */
    volatile CSL_DFE_DPDA_DPDA_PREG_630_REGS dpda_preg_630[24];
    /* Addr: h(676C0), d(423616) */
    volatile Uint32 rsvd639[16];
    /* Addr: h(67700), d(423680) */
    volatile CSL_DFE_DPDA_DPDA_PREG_631_REGS dpda_preg_631[24];
    /* Addr: h(677C0), d(423872) */
    volatile Uint32 rsvd640[16];
    /* Addr: h(67800), d(423936) */
    volatile CSL_DFE_DPDA_DPDA_PREG_632_REGS dpda_preg_632[24];
    /* Addr: h(678C0), d(424128) */
    volatile Uint32 rsvd641[16];
    /* Addr: h(67900), d(424192) */
    volatile CSL_DFE_DPDA_DPDA_PREG_633_REGS dpda_preg_633[24];
    /* Addr: h(679C0), d(424384) */
    volatile Uint32 rsvd642[16];
    /* Addr: h(67A00), d(424448) */
    volatile CSL_DFE_DPDA_DPDA_PREG_634_REGS dpda_preg_634[24];
    /* Addr: h(67AC0), d(424640) */
    volatile Uint32 rsvd643[16];
    /* Addr: h(67B00), d(424704) */
    volatile CSL_DFE_DPDA_DPDA_PREG_635_REGS dpda_preg_635[24];
    /* Addr: h(67BC0), d(424896) */
    volatile Uint32 rsvd644[16];
    /* Addr: h(67C00), d(424960) */
    volatile CSL_DFE_DPDA_DPDA_PREG_636_REGS dpda_preg_636[24];
    /* Addr: h(67CC0), d(425152) */
    volatile Uint32 rsvd645[16];
    /* Addr: h(67D00), d(425216) */
    volatile CSL_DFE_DPDA_DPDA_PREG_637_REGS dpda_preg_637[24];
    /* Addr: h(67DC0), d(425408) */
    volatile Uint32 rsvd646[16];
    /* Addr: h(67E00), d(425472) */
    volatile CSL_DFE_DPDA_DPDA_PREG_638_REGS dpda_preg_638[24];
    /* Addr: h(67EC0), d(425664) */
    volatile Uint32 rsvd647[16];
    /* Addr: h(67F00), d(425728) */
    volatile CSL_DFE_DPDA_DPDA_PREG_639_REGS dpda_preg_639[24];
    /* Addr: h(67FC0), d(425920) */
    volatile Uint32 rsvd648[16];
    /* Addr: h(68000), d(425984) */
    volatile CSL_DFE_DPDA_DPDA_PREG_640_REGS dpda_preg_640[24];
    /* Addr: h(680C0), d(426176) */
    volatile Uint32 rsvd649[16];
    /* Addr: h(68100), d(426240) */
    volatile CSL_DFE_DPDA_DPDA_PREG_641_REGS dpda_preg_641[24];
    /* Addr: h(681C0), d(426432) */
    volatile Uint32 rsvd650[16];
    /* Addr: h(68200), d(426496) */
    volatile CSL_DFE_DPDA_DPDA_PREG_642_REGS dpda_preg_642[24];
    /* Addr: h(682C0), d(426688) */
    volatile Uint32 rsvd651[16];
    /* Addr: h(68300), d(426752) */
    volatile CSL_DFE_DPDA_DPDA_PREG_643_REGS dpda_preg_643[24];
    /* Addr: h(683C0), d(426944) */
    volatile Uint32 rsvd652[16];
    /* Addr: h(68400), d(427008) */
    volatile CSL_DFE_DPDA_DPDA_PREG_644_REGS dpda_preg_644[24];
    /* Addr: h(684C0), d(427200) */
    volatile Uint32 rsvd653[16];
    /* Addr: h(68500), d(427264) */
    volatile CSL_DFE_DPDA_DPDA_PREG_645_REGS dpda_preg_645[24];
    /* Addr: h(685C0), d(427456) */
    volatile Uint32 rsvd654[16];
    /* Addr: h(68600), d(427520) */
    volatile CSL_DFE_DPDA_DPDA_PREG_646_REGS dpda_preg_646[24];
    /* Addr: h(686C0), d(427712) */
    volatile Uint32 rsvd655[16];
    /* Addr: h(68700), d(427776) */
    volatile CSL_DFE_DPDA_DPDA_PREG_647_REGS dpda_preg_647[24];
    /* Addr: h(687C0), d(427968) */
    volatile Uint32 rsvd656[16];
    /* Addr: h(68800), d(428032) */
    volatile CSL_DFE_DPDA_DPDA_PREG_648_REGS dpda_preg_648[24];
    /* Addr: h(688C0), d(428224) */
    volatile Uint32 rsvd657[16];
    /* Addr: h(68900), d(428288) */
    volatile CSL_DFE_DPDA_DPDA_PREG_649_REGS dpda_preg_649[24];
    /* Addr: h(689C0), d(428480) */
    volatile Uint32 rsvd658[16];
    /* Addr: h(68A00), d(428544) */
    volatile CSL_DFE_DPDA_DPDA_PREG_650_REGS dpda_preg_650[24];
    /* Addr: h(68AC0), d(428736) */
    volatile Uint32 rsvd659[16];
    /* Addr: h(68B00), d(428800) */
    volatile CSL_DFE_DPDA_DPDA_PREG_651_REGS dpda_preg_651[24];
    /* Addr: h(68BC0), d(428992) */
    volatile Uint32 rsvd660[16];
    /* Addr: h(68C00), d(429056) */
    volatile CSL_DFE_DPDA_DPDA_PREG_652_REGS dpda_preg_652[24];
    /* Addr: h(68CC0), d(429248) */
    volatile Uint32 rsvd661[16];
    /* Addr: h(68D00), d(429312) */
    volatile CSL_DFE_DPDA_DPDA_PREG_653_REGS dpda_preg_653[24];
    /* Addr: h(68DC0), d(429504) */
    volatile Uint32 rsvd662[16];
    /* Addr: h(68E00), d(429568) */
    volatile CSL_DFE_DPDA_DPDA_PREG_654_REGS dpda_preg_654[24];
    /* Addr: h(68EC0), d(429760) */
    volatile Uint32 rsvd663[16];
    /* Addr: h(68F00), d(429824) */
    volatile CSL_DFE_DPDA_DPDA_PREG_655_REGS dpda_preg_655[24];
    /* Addr: h(68FC0), d(430016) */
    volatile Uint32 rsvd664[16];
    /* Addr: h(69000), d(430080) */
    volatile CSL_DFE_DPDA_DPDA_PREG_656_REGS dpda_preg_656[24];
    /* Addr: h(690C0), d(430272) */
    volatile Uint32 rsvd665[16];
    /* Addr: h(69100), d(430336) */
    volatile CSL_DFE_DPDA_DPDA_PREG_657_REGS dpda_preg_657[24];
    /* Addr: h(691C0), d(430528) */
    volatile Uint32 rsvd666[16];
    /* Addr: h(69200), d(430592) */
    volatile CSL_DFE_DPDA_DPDA_PREG_658_REGS dpda_preg_658[24];
    /* Addr: h(692C0), d(430784) */
    volatile Uint32 rsvd667[16];
    /* Addr: h(69300), d(430848) */
    volatile CSL_DFE_DPDA_DPDA_PREG_659_REGS dpda_preg_659[24];
    /* Addr: h(693C0), d(431040) */
    volatile Uint32 rsvd668[16];
    /* Addr: h(69400), d(431104) */
    volatile CSL_DFE_DPDA_DPDA_PREG_660_REGS dpda_preg_660[24];
    /* Addr: h(694C0), d(431296) */
    volatile Uint32 rsvd669[16];
    /* Addr: h(69500), d(431360) */
    volatile CSL_DFE_DPDA_DPDA_PREG_661_REGS dpda_preg_661[24];
    /* Addr: h(695C0), d(431552) */
    volatile Uint32 rsvd670[16];
    /* Addr: h(69600), d(431616) */
    volatile CSL_DFE_DPDA_DPDA_PREG_662_REGS dpda_preg_662[24];
    /* Addr: h(696C0), d(431808) */
    volatile Uint32 rsvd671[16];
    /* Addr: h(69700), d(431872) */
    volatile CSL_DFE_DPDA_DPDA_PREG_663_REGS dpda_preg_663[24];
    /* Addr: h(697C0), d(432064) */
    volatile Uint32 rsvd672[16];
    /* Addr: h(69800), d(432128) */
    volatile CSL_DFE_DPDA_DPDA_PREG_664_REGS dpda_preg_664[24];
    /* Addr: h(698C0), d(432320) */
    volatile Uint32 rsvd673[16];
    /* Addr: h(69900), d(432384) */
    volatile CSL_DFE_DPDA_DPDA_PREG_665_REGS dpda_preg_665[24];
    /* Addr: h(699C0), d(432576) */
    volatile Uint32 rsvd674[16];
    /* Addr: h(69A00), d(432640) */
    volatile CSL_DFE_DPDA_DPDA_PREG_666_REGS dpda_preg_666[24];
    /* Addr: h(69AC0), d(432832) */
    volatile Uint32 rsvd675[16];
    /* Addr: h(69B00), d(432896) */
    volatile CSL_DFE_DPDA_DPDA_PREG_667_REGS dpda_preg_667[24];
    /* Addr: h(69BC0), d(433088) */
    volatile Uint32 rsvd676[16];
    /* Addr: h(69C00), d(433152) */
    volatile CSL_DFE_DPDA_DPDA_PREG_668_REGS dpda_preg_668[24];
    /* Addr: h(69CC0), d(433344) */
    volatile Uint32 rsvd677[16];
    /* Addr: h(69D00), d(433408) */
    volatile CSL_DFE_DPDA_DPDA_PREG_669_REGS dpda_preg_669[24];
    /* Addr: h(69DC0), d(433600) */
    volatile Uint32 rsvd678[16];
    /* Addr: h(69E00), d(433664) */
    volatile CSL_DFE_DPDA_DPDA_PREG_670_REGS dpda_preg_670[24];
    /* Addr: h(69EC0), d(433856) */
    volatile Uint32 rsvd679[16];
    /* Addr: h(69F00), d(433920) */
    volatile CSL_DFE_DPDA_DPDA_PREG_671_REGS dpda_preg_671[24];
    /* Addr: h(69FC0), d(434112) */
    volatile Uint32 rsvd680[16];
    /* Addr: h(6A000), d(434176) */
    volatile CSL_DFE_DPDA_DPDA_PREG_672_REGS dpda_preg_672[24];
    /* Addr: h(6A0C0), d(434368) */
    volatile Uint32 rsvd681[16];
    /* Addr: h(6A100), d(434432) */
    volatile CSL_DFE_DPDA_DPDA_PREG_673_REGS dpda_preg_673[24];
    /* Addr: h(6A1C0), d(434624) */
    volatile Uint32 rsvd682[16];
    /* Addr: h(6A200), d(434688) */
    volatile CSL_DFE_DPDA_DPDA_PREG_674_REGS dpda_preg_674[24];
    /* Addr: h(6A2C0), d(434880) */
    volatile Uint32 rsvd683[16];
    /* Addr: h(6A300), d(434944) */
    volatile CSL_DFE_DPDA_DPDA_PREG_675_REGS dpda_preg_675[24];
    /* Addr: h(6A3C0), d(435136) */
    volatile Uint32 rsvd684[16];
    /* Addr: h(6A400), d(435200) */
    volatile CSL_DFE_DPDA_DPDA_PREG_676_REGS dpda_preg_676[24];
    /* Addr: h(6A4C0), d(435392) */
    volatile Uint32 rsvd685[16];
    /* Addr: h(6A500), d(435456) */
    volatile CSL_DFE_DPDA_DPDA_PREG_677_REGS dpda_preg_677[24];
    /* Addr: h(6A5C0), d(435648) */
    volatile Uint32 rsvd686[16];
    /* Addr: h(6A600), d(435712) */
    volatile CSL_DFE_DPDA_DPDA_PREG_678_REGS dpda_preg_678[24];
    /* Addr: h(6A6C0), d(435904) */
    volatile Uint32 rsvd687[16];
    /* Addr: h(6A700), d(435968) */
    volatile CSL_DFE_DPDA_DPDA_PREG_679_REGS dpda_preg_679[24];
    /* Addr: h(6A7C0), d(436160) */
    volatile Uint32 rsvd688[16];
    /* Addr: h(6A800), d(436224) */
    volatile CSL_DFE_DPDA_DPDA_PREG_680_REGS dpda_preg_680[24];
    /* Addr: h(6A8C0), d(436416) */
    volatile Uint32 rsvd689[16];
    /* Addr: h(6A900), d(436480) */
    volatile CSL_DFE_DPDA_DPDA_PREG_681_REGS dpda_preg_681[24];
    /* Addr: h(6A9C0), d(436672) */
    volatile Uint32 rsvd690[16];
    /* Addr: h(6AA00), d(436736) */
    volatile CSL_DFE_DPDA_DPDA_PREG_682_REGS dpda_preg_682[24];
    /* Addr: h(6AAC0), d(436928) */
    volatile Uint32 rsvd691[16];
    /* Addr: h(6AB00), d(436992) */
    volatile CSL_DFE_DPDA_DPDA_PREG_683_REGS dpda_preg_683[24];
    /* Addr: h(6ABC0), d(437184) */
    volatile Uint32 rsvd692[16];
    /* Addr: h(6AC00), d(437248) */
    volatile CSL_DFE_DPDA_DPDA_PREG_684_REGS dpda_preg_684[24];
    /* Addr: h(6ACC0), d(437440) */
    volatile Uint32 rsvd693[16];
    /* Addr: h(6AD00), d(437504) */
    volatile CSL_DFE_DPDA_DPDA_PREG_685_REGS dpda_preg_685[24];
    /* Addr: h(6ADC0), d(437696) */
    volatile Uint32 rsvd694[16];
    /* Addr: h(6AE00), d(437760) */
    volatile CSL_DFE_DPDA_DPDA_PREG_686_REGS dpda_preg_686[24];
    /* Addr: h(6AEC0), d(437952) */
    volatile Uint32 rsvd695[16];
    /* Addr: h(6AF00), d(438016) */
    volatile CSL_DFE_DPDA_DPDA_PREG_687_REGS dpda_preg_687[24];
    /* Addr: h(6AFC0), d(438208) */
    volatile Uint32 rsvd696[16];
    /* Addr: h(6B000), d(438272) */
    volatile CSL_DFE_DPDA_DPDA_PREG_688_REGS dpda_preg_688[24];
    /* Addr: h(6B0C0), d(438464) */
    volatile Uint32 rsvd697[16];
    /* Addr: h(6B100), d(438528) */
    volatile CSL_DFE_DPDA_DPDA_PREG_689_REGS dpda_preg_689[24];
    /* Addr: h(6B1C0), d(438720) */
    volatile Uint32 rsvd698[16];
    /* Addr: h(6B200), d(438784) */
    volatile CSL_DFE_DPDA_DPDA_PREG_690_REGS dpda_preg_690[24];
    /* Addr: h(6B2C0), d(438976) */
    volatile Uint32 rsvd699[16];
    /* Addr: h(6B300), d(439040) */
    volatile CSL_DFE_DPDA_DPDA_PREG_691_REGS dpda_preg_691[24];
    /* Addr: h(6B3C0), d(439232) */
    volatile Uint32 rsvd700[16];
    /* Addr: h(6B400), d(439296) */
    volatile CSL_DFE_DPDA_DPDA_PREG_692_REGS dpda_preg_692[24];
    /* Addr: h(6B4C0), d(439488) */
    volatile Uint32 rsvd701[16];
    /* Addr: h(6B500), d(439552) */
    volatile CSL_DFE_DPDA_DPDA_PREG_693_REGS dpda_preg_693[24];
    /* Addr: h(6B5C0), d(439744) */
    volatile Uint32 rsvd702[16];
    /* Addr: h(6B600), d(439808) */
    volatile CSL_DFE_DPDA_DPDA_PREG_694_REGS dpda_preg_694[24];
    /* Addr: h(6B6C0), d(440000) */
    volatile Uint32 rsvd703[16];
    /* Addr: h(6B700), d(440064) */
    volatile CSL_DFE_DPDA_DPDA_PREG_695_REGS dpda_preg_695[24];
    /* Addr: h(6B7C0), d(440256) */
    volatile Uint32 rsvd704[16];
    /* Addr: h(6B800), d(440320) */
    volatile CSL_DFE_DPDA_DPDA_PREG_696_REGS dpda_preg_696[24];
    /* Addr: h(6B8C0), d(440512) */
    volatile Uint32 rsvd705[16];
    /* Addr: h(6B900), d(440576) */
    volatile CSL_DFE_DPDA_DPDA_PREG_697_REGS dpda_preg_697[24];
    /* Addr: h(6B9C0), d(440768) */
    volatile Uint32 rsvd706[16];
    /* Addr: h(6BA00), d(440832) */
    volatile CSL_DFE_DPDA_DPDA_PREG_698_REGS dpda_preg_698[24];
    /* Addr: h(6BAC0), d(441024) */
    volatile Uint32 rsvd707[16];
    /* Addr: h(6BB00), d(441088) */
    volatile CSL_DFE_DPDA_DPDA_PREG_699_REGS dpda_preg_699[24];
    /* Addr: h(6BBC0), d(441280) */
    volatile Uint32 rsvd708[16];
    /* Addr: h(6BC00), d(441344) */
    volatile CSL_DFE_DPDA_DPDA_PREG_700_REGS dpda_preg_700[24];
    /* Addr: h(6BCC0), d(441536) */
    volatile Uint32 rsvd709[16];
    /* Addr: h(6BD00), d(441600) */
    volatile CSL_DFE_DPDA_DPDA_PREG_701_REGS dpda_preg_701[24];
    /* Addr: h(6BDC0), d(441792) */
    volatile Uint32 rsvd710[16];
    /* Addr: h(6BE00), d(441856) */
    volatile CSL_DFE_DPDA_DPDA_PREG_702_REGS dpda_preg_702[24];
    /* Addr: h(6BEC0), d(442048) */
    volatile Uint32 rsvd711[16];
    /* Addr: h(6BF00), d(442112) */
    volatile CSL_DFE_DPDA_DPDA_PREG_703_REGS dpda_preg_703[24];
    /* Addr: h(6BFC0), d(442304) */
    volatile Uint32 rsvd712[16];
    /* Addr: h(6C000), d(442368) */
    volatile CSL_DFE_DPDA_DPDA_PREG_704_REGS dpda_preg_704[24];
    /* Addr: h(6C0C0), d(442560) */
    volatile Uint32 rsvd713[16];
    /* Addr: h(6C100), d(442624) */
    volatile CSL_DFE_DPDA_DPDA_PREG_705_REGS dpda_preg_705[24];
    /* Addr: h(6C1C0), d(442816) */
    volatile Uint32 rsvd714[16];
    /* Addr: h(6C200), d(442880) */
    volatile CSL_DFE_DPDA_DPDA_PREG_706_REGS dpda_preg_706[24];
    /* Addr: h(6C2C0), d(443072) */
    volatile Uint32 rsvd715[16];
    /* Addr: h(6C300), d(443136) */
    volatile CSL_DFE_DPDA_DPDA_PREG_707_REGS dpda_preg_707[24];
    /* Addr: h(6C3C0), d(443328) */
    volatile Uint32 rsvd716[16];
    /* Addr: h(6C400), d(443392) */
    volatile CSL_DFE_DPDA_DPDA_PREG_708_REGS dpda_preg_708[24];
    /* Addr: h(6C4C0), d(443584) */
    volatile Uint32 rsvd717[16];
    /* Addr: h(6C500), d(443648) */
    volatile CSL_DFE_DPDA_DPDA_PREG_709_REGS dpda_preg_709[24];
    /* Addr: h(6C5C0), d(443840) */
    volatile Uint32 rsvd718[16];
    /* Addr: h(6C600), d(443904) */
    volatile CSL_DFE_DPDA_DPDA_PREG_710_REGS dpda_preg_710[24];
    /* Addr: h(6C6C0), d(444096) */
    volatile Uint32 rsvd719[16];
    /* Addr: h(6C700), d(444160) */
    volatile CSL_DFE_DPDA_DPDA_PREG_711_REGS dpda_preg_711[24];
    /* Addr: h(6C7C0), d(444352) */
    volatile Uint32 rsvd720[16];
    /* Addr: h(6C800), d(444416) */
    volatile CSL_DFE_DPDA_DPDA_PREG_712_REGS dpda_preg_712[24];
    /* Addr: h(6C8C0), d(444608) */
    volatile Uint32 rsvd721[16];
    /* Addr: h(6C900), d(444672) */
    volatile CSL_DFE_DPDA_DPDA_PREG_713_REGS dpda_preg_713[24];
    /* Addr: h(6C9C0), d(444864) */
    volatile Uint32 rsvd722[16];
    /* Addr: h(6CA00), d(444928) */
    volatile CSL_DFE_DPDA_DPDA_PREG_714_REGS dpda_preg_714[24];
    /* Addr: h(6CAC0), d(445120) */
    volatile Uint32 rsvd723[16];
    /* Addr: h(6CB00), d(445184) */
    volatile CSL_DFE_DPDA_DPDA_PREG_715_REGS dpda_preg_715[24];
    /* Addr: h(6CBC0), d(445376) */
    volatile Uint32 rsvd724[16];
    /* Addr: h(6CC00), d(445440) */
    volatile CSL_DFE_DPDA_DPDA_PREG_716_REGS dpda_preg_716[24];
    /* Addr: h(6CCC0), d(445632) */
    volatile Uint32 rsvd725[16];
    /* Addr: h(6CD00), d(445696) */
    volatile CSL_DFE_DPDA_DPDA_PREG_717_REGS dpda_preg_717[24];
    /* Addr: h(6CDC0), d(445888) */
    volatile Uint32 rsvd726[16];
    /* Addr: h(6CE00), d(445952) */
    volatile CSL_DFE_DPDA_DPDA_PREG_718_REGS dpda_preg_718[24];
    /* Addr: h(6CEC0), d(446144) */
    volatile Uint32 rsvd727[16];
    /* Addr: h(6CF00), d(446208) */
    volatile CSL_DFE_DPDA_DPDA_PREG_719_REGS dpda_preg_719[24];
    /* Addr: h(6CFC0), d(446400) */
    volatile Uint32 rsvd728[16];
    /* Addr: h(6D000), d(446464) */
    volatile CSL_DFE_DPDA_DPDA_PREG_720_REGS dpda_preg_720[24];
    /* Addr: h(6D0C0), d(446656) */
    volatile Uint32 rsvd729[16];
    /* Addr: h(6D100), d(446720) */
    volatile CSL_DFE_DPDA_DPDA_PREG_721_REGS dpda_preg_721[24];
    /* Addr: h(6D1C0), d(446912) */
    volatile Uint32 rsvd730[16];
    /* Addr: h(6D200), d(446976) */
    volatile CSL_DFE_DPDA_DPDA_PREG_722_REGS dpda_preg_722[24];
    /* Addr: h(6D2C0), d(447168) */
    volatile Uint32 rsvd731[16];
    /* Addr: h(6D300), d(447232) */
    volatile CSL_DFE_DPDA_DPDA_PREG_723_REGS dpda_preg_723[24];
    /* Addr: h(6D3C0), d(447424) */
    volatile Uint32 rsvd732[16];
    /* Addr: h(6D400), d(447488) */
    volatile CSL_DFE_DPDA_DPDA_PREG_724_REGS dpda_preg_724[24];
    /* Addr: h(6D4C0), d(447680) */
    volatile Uint32 rsvd733[16];
    /* Addr: h(6D500), d(447744) */
    volatile CSL_DFE_DPDA_DPDA_PREG_725_REGS dpda_preg_725[24];
    /* Addr: h(6D5C0), d(447936) */
    volatile Uint32 rsvd734[16];
    /* Addr: h(6D600), d(448000) */
    volatile CSL_DFE_DPDA_DPDA_PREG_726_REGS dpda_preg_726[24];
    /* Addr: h(6D6C0), d(448192) */
    volatile Uint32 rsvd735[16];
    /* Addr: h(6D700), d(448256) */
    volatile CSL_DFE_DPDA_DPDA_PREG_727_REGS dpda_preg_727[24];
    /* Addr: h(6D7C0), d(448448) */
    volatile Uint32 rsvd736[16];
    /* Addr: h(6D800), d(448512) */
    volatile CSL_DFE_DPDA_DPDA_PREG_728_REGS dpda_preg_728[24];
    /* Addr: h(6D8C0), d(448704) */
    volatile Uint32 rsvd737[16];
    /* Addr: h(6D900), d(448768) */
    volatile CSL_DFE_DPDA_DPDA_PREG_729_REGS dpda_preg_729[24];
    /* Addr: h(6D9C0), d(448960) */
    volatile Uint32 rsvd738[16];
    /* Addr: h(6DA00), d(449024) */
    volatile CSL_DFE_DPDA_DPDA_PREG_730_REGS dpda_preg_730[24];
    /* Addr: h(6DAC0), d(449216) */
    volatile Uint32 rsvd739[16];
    /* Addr: h(6DB00), d(449280) */
    volatile CSL_DFE_DPDA_DPDA_PREG_731_REGS dpda_preg_731[24];
    /* Addr: h(6DBC0), d(449472) */
    volatile Uint32 rsvd740[16];
    /* Addr: h(6DC00), d(449536) */
    volatile CSL_DFE_DPDA_DPDA_PREG_732_REGS dpda_preg_732[24];
    /* Addr: h(6DCC0), d(449728) */
    volatile Uint32 rsvd741[16];
    /* Addr: h(6DD00), d(449792) */
    volatile CSL_DFE_DPDA_DPDA_PREG_733_REGS dpda_preg_733[24];
    /* Addr: h(6DDC0), d(449984) */
    volatile Uint32 rsvd742[16];
    /* Addr: h(6DE00), d(450048) */
    volatile CSL_DFE_DPDA_DPDA_PREG_734_REGS dpda_preg_734[24];
    /* Addr: h(6DEC0), d(450240) */
    volatile Uint32 rsvd743[16];
    /* Addr: h(6DF00), d(450304) */
    volatile CSL_DFE_DPDA_DPDA_PREG_735_REGS dpda_preg_735[24];
    /* Addr: h(6DFC0), d(450496) */
    volatile Uint32 rsvd744[16];
    /* Addr: h(6E000), d(450560) */
    volatile CSL_DFE_DPDA_DPDA_PREG_736_REGS dpda_preg_736[24];
    /* Addr: h(6E0C0), d(450752) */
    volatile Uint32 rsvd745[16];
    /* Addr: h(6E100), d(450816) */
    volatile CSL_DFE_DPDA_DPDA_PREG_737_REGS dpda_preg_737[24];
    /* Addr: h(6E1C0), d(451008) */
    volatile Uint32 rsvd746[16];
    /* Addr: h(6E200), d(451072) */
    volatile CSL_DFE_DPDA_DPDA_PREG_738_REGS dpda_preg_738[24];
    /* Addr: h(6E2C0), d(451264) */
    volatile Uint32 rsvd747[16];
    /* Addr: h(6E300), d(451328) */
    volatile CSL_DFE_DPDA_DPDA_PREG_739_REGS dpda_preg_739[24];
    /* Addr: h(6E3C0), d(451520) */
    volatile Uint32 rsvd748[16];
    /* Addr: h(6E400), d(451584) */
    volatile CSL_DFE_DPDA_DPDA_PREG_740_REGS dpda_preg_740[24];
    /* Addr: h(6E4C0), d(451776) */
    volatile Uint32 rsvd749[16];
    /* Addr: h(6E500), d(451840) */
    volatile CSL_DFE_DPDA_DPDA_PREG_741_REGS dpda_preg_741[24];
    /* Addr: h(6E5C0), d(452032) */
    volatile Uint32 rsvd750[16];
    /* Addr: h(6E600), d(452096) */
    volatile CSL_DFE_DPDA_DPDA_PREG_742_REGS dpda_preg_742[24];
    /* Addr: h(6E6C0), d(452288) */
    volatile Uint32 rsvd751[16];
    /* Addr: h(6E700), d(452352) */
    volatile CSL_DFE_DPDA_DPDA_PREG_743_REGS dpda_preg_743[24];
    /* Addr: h(6E7C0), d(452544) */
    volatile Uint32 rsvd752[16];
    /* Addr: h(6E800), d(452608) */
    volatile CSL_DFE_DPDA_DPDA_PREG_744_REGS dpda_preg_744[24];
    /* Addr: h(6E8C0), d(452800) */
    volatile Uint32 rsvd753[16];
    /* Addr: h(6E900), d(452864) */
    volatile CSL_DFE_DPDA_DPDA_PREG_745_REGS dpda_preg_745[24];
    /* Addr: h(6E9C0), d(453056) */
    volatile Uint32 rsvd754[16];
    /* Addr: h(6EA00), d(453120) */
    volatile CSL_DFE_DPDA_DPDA_PREG_746_REGS dpda_preg_746[24];
    /* Addr: h(6EAC0), d(453312) */
    volatile Uint32 rsvd755[16];
    /* Addr: h(6EB00), d(453376) */
    volatile CSL_DFE_DPDA_DPDA_PREG_747_REGS dpda_preg_747[24];
    /* Addr: h(6EBC0), d(453568) */
    volatile Uint32 rsvd756[16];
    /* Addr: h(6EC00), d(453632) */
    volatile CSL_DFE_DPDA_DPDA_PREG_748_REGS dpda_preg_748[24];
    /* Addr: h(6ECC0), d(453824) */
    volatile Uint32 rsvd757[16];
    /* Addr: h(6ED00), d(453888) */
    volatile CSL_DFE_DPDA_DPDA_PREG_749_REGS dpda_preg_749[24];
    /* Addr: h(6EDC0), d(454080) */
    volatile Uint32 rsvd758[16];
    /* Addr: h(6EE00), d(454144) */
    volatile CSL_DFE_DPDA_DPDA_PREG_750_REGS dpda_preg_750[24];
    /* Addr: h(6EEC0), d(454336) */
    volatile Uint32 rsvd759[16];
    /* Addr: h(6EF00), d(454400) */
    volatile CSL_DFE_DPDA_DPDA_PREG_751_REGS dpda_preg_751[24];
    /* Addr: h(6EFC0), d(454592) */
    volatile Uint32 rsvd760[16];
    /* Addr: h(6F000), d(454656) */
    volatile CSL_DFE_DPDA_DPDA_PREG_752_REGS dpda_preg_752[24];
    /* Addr: h(6F0C0), d(454848) */
    volatile Uint32 rsvd761[16];
    /* Addr: h(6F100), d(454912) */
    volatile CSL_DFE_DPDA_DPDA_PREG_753_REGS dpda_preg_753[24];
    /* Addr: h(6F1C0), d(455104) */
    volatile Uint32 rsvd762[16];
    /* Addr: h(6F200), d(455168) */
    volatile CSL_DFE_DPDA_DPDA_PREG_754_REGS dpda_preg_754[24];
    /* Addr: h(6F2C0), d(455360) */
    volatile Uint32 rsvd763[16];
    /* Addr: h(6F300), d(455424) */
    volatile CSL_DFE_DPDA_DPDA_PREG_755_REGS dpda_preg_755[24];
    /* Addr: h(6F3C0), d(455616) */
    volatile Uint32 rsvd764[16];
    /* Addr: h(6F400), d(455680) */
    volatile CSL_DFE_DPDA_DPDA_PREG_756_REGS dpda_preg_756[24];
    /* Addr: h(6F4C0), d(455872) */
    volatile Uint32 rsvd765[16];
    /* Addr: h(6F500), d(455936) */
    volatile CSL_DFE_DPDA_DPDA_PREG_757_REGS dpda_preg_757[24];
    /* Addr: h(6F5C0), d(456128) */
    volatile Uint32 rsvd766[16];
    /* Addr: h(6F600), d(456192) */
    volatile CSL_DFE_DPDA_DPDA_PREG_758_REGS dpda_preg_758[24];
    /* Addr: h(6F6C0), d(456384) */
    volatile Uint32 rsvd767[16];
    /* Addr: h(6F700), d(456448) */
    volatile CSL_DFE_DPDA_DPDA_PREG_759_REGS dpda_preg_759[24];
    /* Addr: h(6F7C0), d(456640) */
    volatile Uint32 rsvd768[16];
    /* Addr: h(6F800), d(456704) */
    volatile CSL_DFE_DPDA_DPDA_PREG_760_REGS dpda_preg_760[24];
    /* Addr: h(6F8C0), d(456896) */
    volatile Uint32 rsvd769[16];
    /* Addr: h(6F900), d(456960) */
    volatile CSL_DFE_DPDA_DPDA_PREG_761_REGS dpda_preg_761[24];
    /* Addr: h(6F9C0), d(457152) */
    volatile Uint32 rsvd770[16];
    /* Addr: h(6FA00), d(457216) */
    volatile CSL_DFE_DPDA_DPDA_PREG_762_REGS dpda_preg_762[24];
    /* Addr: h(6FAC0), d(457408) */
    volatile Uint32 rsvd771[16];
    /* Addr: h(6FB00), d(457472) */
    volatile CSL_DFE_DPDA_DPDA_PREG_763_REGS dpda_preg_763[24];
    /* Addr: h(6FBC0), d(457664) */
    volatile Uint32 rsvd772[16];
    /* Addr: h(6FC00), d(457728) */
    volatile CSL_DFE_DPDA_DPDA_PREG_764_REGS dpda_preg_764[24];
    /* Addr: h(6FCC0), d(457920) */
    volatile Uint32 rsvd773[16];
    /* Addr: h(6FD00), d(457984) */
    volatile CSL_DFE_DPDA_DPDA_PREG_765_REGS dpda_preg_765[24];
    /* Addr: h(6FDC0), d(458176) */
    volatile Uint32 rsvd774[16];
    /* Addr: h(6FE00), d(458240) */
    volatile CSL_DFE_DPDA_DPDA_PREG_766_REGS dpda_preg_766[24];
    /* Addr: h(6FEC0), d(458432) */
    volatile Uint32 rsvd775[16];
    /* Addr: h(6FF00), d(458496) */
    volatile CSL_DFE_DPDA_DPDA_PREG_767_REGS dpda_preg_767[24];
} CSL_DFE_DPDA_REGS;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* MASK */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 reserved_intrs : 18;
    Uint32 lutfill_exception_intr : 1;
    Uint32 int_processed_intr : 1;
    Uint32 int_read_complete_intr : 1;
    Uint32 simd_floatp_error_intr : 1;
    Uint32 sc_floatp_error_intr : 1;
    Uint32 idle_intr : 1;
    Uint32 prog2_intr : 1;
    Uint32 prog1_intr : 1;
    Uint32 stack_empty_intr : 1;
    Uint32 stack_full_intr : 1;
    Uint32 out_of_bound_prog_cnt_intr : 1;
    Uint32 branch_type_error_intr : 1;
    Uint32 out_of_bound_cr_intr : 1;
    Uint32 inst_type_error_intr : 1;
#else 
    Uint32 inst_type_error_intr : 1;
    Uint32 out_of_bound_cr_intr : 1;
    Uint32 branch_type_error_intr : 1;
    Uint32 out_of_bound_prog_cnt_intr : 1;
    Uint32 stack_full_intr : 1;
    Uint32 stack_empty_intr : 1;
    Uint32 prog1_intr : 1;
    Uint32 prog2_intr : 1;
    Uint32 idle_intr : 1;
    Uint32 sc_floatp_error_intr : 1;
    Uint32 simd_floatp_error_intr : 1;
    Uint32 int_read_complete_intr : 1;
    Uint32 int_processed_intr : 1;
    Uint32 lutfill_exception_intr : 1;
    Uint32 reserved_intrs : 18;
#endif 
} CSL_DFE_DPDA_MASK_REG;

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_INST_TYPE_ERROR_INTR_MASK (0x00000001u)
#define CSL_DFE_DPDA_MASK_REG_INST_TYPE_ERROR_INTR_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_MASK_REG_INST_TYPE_ERROR_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_OUT_OF_BOUND_CR_INTR_MASK (0x00000002u)
#define CSL_DFE_DPDA_MASK_REG_OUT_OF_BOUND_CR_INTR_SHIFT (0x00000001u)
#define CSL_DFE_DPDA_MASK_REG_OUT_OF_BOUND_CR_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_BRANCH_TYPE_ERROR_INTR_MASK (0x00000004u)
#define CSL_DFE_DPDA_MASK_REG_BRANCH_TYPE_ERROR_INTR_SHIFT (0x00000002u)
#define CSL_DFE_DPDA_MASK_REG_BRANCH_TYPE_ERROR_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_OUT_OF_BOUND_PROG_CNT_INTR_MASK (0x00000008u)
#define CSL_DFE_DPDA_MASK_REG_OUT_OF_BOUND_PROG_CNT_INTR_SHIFT (0x00000003u)
#define CSL_DFE_DPDA_MASK_REG_OUT_OF_BOUND_PROG_CNT_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_STACK_FULL_INTR_MASK (0x00000010u)
#define CSL_DFE_DPDA_MASK_REG_STACK_FULL_INTR_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_MASK_REG_STACK_FULL_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_STACK_EMPTY_INTR_MASK (0x00000020u)
#define CSL_DFE_DPDA_MASK_REG_STACK_EMPTY_INTR_SHIFT (0x00000005u)
#define CSL_DFE_DPDA_MASK_REG_STACK_EMPTY_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_PROG1_INTR_MASK (0x00000040u)
#define CSL_DFE_DPDA_MASK_REG_PROG1_INTR_SHIFT (0x00000006u)
#define CSL_DFE_DPDA_MASK_REG_PROG1_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_PROG2_INTR_MASK (0x00000080u)
#define CSL_DFE_DPDA_MASK_REG_PROG2_INTR_SHIFT (0x00000007u)
#define CSL_DFE_DPDA_MASK_REG_PROG2_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_IDLE_INTR_MASK (0x00000100u)
#define CSL_DFE_DPDA_MASK_REG_IDLE_INTR_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_MASK_REG_IDLE_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_SC_FLOATP_ERROR_INTR_MASK (0x00000200u)
#define CSL_DFE_DPDA_MASK_REG_SC_FLOATP_ERROR_INTR_SHIFT (0x00000009u)
#define CSL_DFE_DPDA_MASK_REG_SC_FLOATP_ERROR_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_SIMD_FLOATP_ERROR_INTR_MASK (0x00000400u)
#define CSL_DFE_DPDA_MASK_REG_SIMD_FLOATP_ERROR_INTR_SHIFT (0x0000000Au)
#define CSL_DFE_DPDA_MASK_REG_SIMD_FLOATP_ERROR_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_INT_READ_COMPLETE_INTR_MASK (0x00000800u)
#define CSL_DFE_DPDA_MASK_REG_INT_READ_COMPLETE_INTR_SHIFT (0x0000000Bu)
#define CSL_DFE_DPDA_MASK_REG_INT_READ_COMPLETE_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_INT_PROCESSED_INTR_MASK (0x00001000u)
#define CSL_DFE_DPDA_MASK_REG_INT_PROCESSED_INTR_SHIFT (0x0000000Cu)
#define CSL_DFE_DPDA_MASK_REG_INT_PROCESSED_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_LUTFILL_EXCEPTION_INTR_MASK (0x00002000u)
#define CSL_DFE_DPDA_MASK_REG_LUTFILL_EXCEPTION_INTR_SHIFT (0x0000000Du)
#define CSL_DFE_DPDA_MASK_REG_LUTFILL_EXCEPTION_INTR_RESETVAL (0x00000000u)

/* Mask which interrupts go out dpda interrupt pin. 1 to mask on, 0 to mask off. */
#define CSL_DFE_DPDA_MASK_REG_RESERVED_INTRS_MASK (0xFFFFC000u)
#define CSL_DFE_DPDA_MASK_REG_RESERVED_INTRS_SHIFT (0x0000000Eu)
#define CSL_DFE_DPDA_MASK_REG_RESERVED_INTRS_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_MASK_REG_ADDR (0x00000004u)
#define CSL_DFE_DPDA_MASK_REG_RESETVAL (0x00000000u)

/* STATUS */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 reserved_status : 18;
    Uint32 lutfill_exception_status : 1;
    Uint32 int_processed_status : 1;
    Uint32 int_read_complete_status : 1;
    Uint32 simd_floatp_error_status : 1;
    Uint32 sc_floatp_error_status : 1;
    Uint32 idle_status : 1;
    Uint32 prog2_status : 1;
    Uint32 prog1_status : 1;
    Uint32 stack_empty_status : 1;
    Uint32 stack_full_status : 1;
    Uint32 out_of_bound_prog_cnt_status : 1;
    Uint32 branch_type_error_status : 1;
    Uint32 out_of_bound_cr_status : 1;
    Uint32 inst_type_error_status : 1;
#else 
    Uint32 inst_type_error_status : 1;
    Uint32 out_of_bound_cr_status : 1;
    Uint32 branch_type_error_status : 1;
    Uint32 out_of_bound_prog_cnt_status : 1;
    Uint32 stack_full_status : 1;
    Uint32 stack_empty_status : 1;
    Uint32 prog1_status : 1;
    Uint32 prog2_status : 1;
    Uint32 idle_status : 1;
    Uint32 sc_floatp_error_status : 1;
    Uint32 simd_floatp_error_status : 1;
    Uint32 int_read_complete_status : 1;
    Uint32 int_processed_status : 1;
    Uint32 lutfill_exception_status : 1;
    Uint32 reserved_status : 18;
#endif 
} CSL_DFE_DPDA_STATUS_REG;

/* Goes high only if cr in an instruction is not recognized. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_INST_TYPE_ERROR_STATUS_MASK (0x00000001u)
#define CSL_DFE_DPDA_STATUS_REG_INST_TYPE_ERROR_STATUS_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_STATUS_REG_INST_TYPE_ERROR_STATUS_RESETVAL (0x00000000u)

/* Goes high only if an instruction is trying to write in a cr that does not exist. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_OUT_OF_BOUND_CR_STATUS_MASK (0x00000002u)
#define CSL_DFE_DPDA_STATUS_REG_OUT_OF_BOUND_CR_STATUS_SHIFT (0x00000001u)
#define CSL_DFE_DPDA_STATUS_REG_OUT_OF_BOUND_CR_STATUS_RESETVAL (0x00000000u)

/* Goes high only if a branch instruction has an unrecognized branch type. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_BRANCH_TYPE_ERROR_STATUS_MASK (0x00000004u)
#define CSL_DFE_DPDA_STATUS_REG_BRANCH_TYPE_ERROR_STATUS_SHIFT (0x00000002u)
#define CSL_DFE_DPDA_STATUS_REG_BRANCH_TYPE_ERROR_STATUS_RESETVAL (0x00000000u)

/* Goes high only if the program counter is out of bounds. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_OUT_OF_BOUND_PROG_CNT_STATUS_MASK (0x00000008u)
#define CSL_DFE_DPDA_STATUS_REG_OUT_OF_BOUND_PROG_CNT_STATUS_SHIFT (0x00000003u)
#define CSL_DFE_DPDA_STATUS_REG_OUT_OF_BOUND_PROG_CNT_STATUS_RESETVAL (0x00000000u)

/* Goes high only if the stack was full and we tried to put something more. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_STACK_FULL_STATUS_MASK (0x00000010u)
#define CSL_DFE_DPDA_STATUS_REG_STACK_FULL_STATUS_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_STATUS_REG_STACK_FULL_STATUS_RESETVAL (0x00000000u)

/* Goes high only if the stack was empty and we tried to retrieve something. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_STACK_EMPTY_STATUS_MASK (0x00000020u)
#define CSL_DFE_DPDA_STATUS_REG_STACK_EMPTY_STATUS_SHIFT (0x00000005u)
#define CSL_DFE_DPDA_STATUS_REG_STACK_EMPTY_STATUS_RESETVAL (0x00000000u)

/* Goes high only if a programmable interrupt within ig_regfile goes high. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_PROG1_STATUS_MASK (0x00000040u)
#define CSL_DFE_DPDA_STATUS_REG_PROG1_STATUS_SHIFT (0x00000006u)
#define CSL_DFE_DPDA_STATUS_REG_PROG1_STATUS_RESETVAL (0x00000000u)

/* Goes high only if a programmable interrupt within ig_regfile goes high. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_PROG2_STATUS_MASK (0x00000080u)
#define CSL_DFE_DPDA_STATUS_REG_PROG2_STATUS_SHIFT (0x00000007u)
#define CSL_DFE_DPDA_STATUS_REG_PROG2_STATUS_RESETVAL (0x00000000u)

/* Goes high when the status of the instruction generator goes from RUNNING to IDLE. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_IDLE_STATUS_MASK (0x00000100u)
#define CSL_DFE_DPDA_STATUS_REG_IDLE_STATUS_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_STATUS_REG_IDLE_STATUS_RESETVAL (0x00000000u)

/* Goes high when there is a floating point overflow of any kind in the scalar engine. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_SC_FLOATP_ERROR_STATUS_MASK (0x00000200u)
#define CSL_DFE_DPDA_STATUS_REG_SC_FLOATP_ERROR_STATUS_SHIFT (0x00000009u)
#define CSL_DFE_DPDA_STATUS_REG_SC_FLOATP_ERROR_STATUS_RESETVAL (0x00000000u)

/* Goes high when there is a floating point overflow of any kind in the SIMD engine. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_SIMD_FLOATP_ERROR_STATUS_MASK (0x00000400u)
#define CSL_DFE_DPDA_STATUS_REG_SIMD_FLOATP_ERROR_STATUS_SHIFT (0x0000000Au)
#define CSL_DFE_DPDA_STATUS_REG_SIMD_FLOATP_ERROR_STATUS_RESETVAL (0x00000000u)

/* Goes high when the instruction generator confirms the parameters from the interrupt have been recorded. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_INT_READ_COMPLETE_STATUS_MASK (0x00000800u)
#define CSL_DFE_DPDA_STATUS_REG_INT_READ_COMPLETE_STATUS_SHIFT (0x0000000Bu)
#define CSL_DFE_DPDA_STATUS_REG_INT_READ_COMPLETE_STATUS_RESETVAL (0x00000000u)

/* Goes high when the current interrupt request have been processed by the DPDA. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_INT_PROCESSED_STATUS_MASK (0x00001000u)
#define CSL_DFE_DPDA_STATUS_REG_INT_PROCESSED_STATUS_SHIFT (0x0000000Cu)
#define CSL_DFE_DPDA_STATUS_REG_INT_PROCESSED_STATUS_RESETVAL (0x00000000u)

/* Goes high when there is a floating point overflow or an slope overflow in the lutfill engine. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_LUTFILL_EXCEPTION_STATUS_MASK (0x00002000u)
#define CSL_DFE_DPDA_STATUS_REG_LUTFILL_EXCEPTION_STATUS_SHIFT (0x0000000Du)
#define CSL_DFE_DPDA_STATUS_REG_LUTFILL_EXCEPTION_STATUS_RESETVAL (0x00000000u)

/* These interrupts are as of now reserved. Goes low only when mpu writes a 0. MPU writing 1 does nothing. */
#define CSL_DFE_DPDA_STATUS_REG_RESERVED_STATUS_MASK (0xFFFFC000u)
#define CSL_DFE_DPDA_STATUS_REG_RESERVED_STATUS_SHIFT (0x0000000Eu)
#define CSL_DFE_DPDA_STATUS_REG_RESERVED_STATUS_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_STATUS_REG_ADDR (0x00000008u)
#define CSL_DFE_DPDA_STATUS_REG_RESETVAL (0x00000000u)

/* FORCE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 reserved_force : 18;
    Uint32 lutfill_exception_force : 1;
    Uint32 int_processed_force : 1;
    Uint32 int_read_complete_force : 1;
    Uint32 simd_floatp_error_force : 1;
    Uint32 sc_floatp_error_force : 1;
    Uint32 idle_force : 1;
    Uint32 prog2_force : 1;
    Uint32 prog1_force : 1;
    Uint32 stack_empty_force : 1;
    Uint32 stack_full_force : 1;
    Uint32 out_of_bound_prog_cnt_force : 1;
    Uint32 branch_type_error_force : 1;
    Uint32 out_of_bound_cr_force : 1;
    Uint32 inst_type_error_force : 1;
#else 
    Uint32 inst_type_error_force : 1;
    Uint32 out_of_bound_cr_force : 1;
    Uint32 branch_type_error_force : 1;
    Uint32 out_of_bound_prog_cnt_force : 1;
    Uint32 stack_full_force : 1;
    Uint32 stack_empty_force : 1;
    Uint32 prog1_force : 1;
    Uint32 prog2_force : 1;
    Uint32 idle_force : 1;
    Uint32 sc_floatp_error_force : 1;
    Uint32 simd_floatp_error_force : 1;
    Uint32 int_read_complete_force : 1;
    Uint32 int_processed_force : 1;
    Uint32 lutfill_exception_force : 1;
    Uint32 reserved_force : 18;
#endif 
} CSL_DFE_DPDA_FORCE_REG;

/* Set to 1 to force out_of_bound_cr_status high */
#define CSL_DFE_DPDA_FORCE_REG_INST_TYPE_ERROR_FORCE_MASK (0x00000001u)
#define CSL_DFE_DPDA_FORCE_REG_INST_TYPE_ERROR_FORCE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_FORCE_REG_INST_TYPE_ERROR_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force sc_div_by_zero_status high */
#define CSL_DFE_DPDA_FORCE_REG_OUT_OF_BOUND_CR_FORCE_MASK (0x00000002u)
#define CSL_DFE_DPDA_FORCE_REG_OUT_OF_BOUND_CR_FORCE_SHIFT (0x00000001u)
#define CSL_DFE_DPDA_FORCE_REG_OUT_OF_BOUND_CR_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force sc_sqrt_neg_status high */
#define CSL_DFE_DPDA_FORCE_REG_BRANCH_TYPE_ERROR_FORCE_MASK (0x00000004u)
#define CSL_DFE_DPDA_FORCE_REG_BRANCH_TYPE_ERROR_FORCE_SHIFT (0x00000002u)
#define CSL_DFE_DPDA_FORCE_REG_BRANCH_TYPE_ERROR_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force out_of_bound_prog_cnt_status high */
#define CSL_DFE_DPDA_FORCE_REG_OUT_OF_BOUND_PROG_CNT_FORCE_MASK (0x00000008u)
#define CSL_DFE_DPDA_FORCE_REG_OUT_OF_BOUND_PROG_CNT_FORCE_SHIFT (0x00000003u)
#define CSL_DFE_DPDA_FORCE_REG_OUT_OF_BOUND_PROG_CNT_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force stack_full_status high */
#define CSL_DFE_DPDA_FORCE_REG_STACK_FULL_FORCE_MASK (0x00000010u)
#define CSL_DFE_DPDA_FORCE_REG_STACK_FULL_FORCE_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_FORCE_REG_STACK_FULL_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force stack_empty_status high */
#define CSL_DFE_DPDA_FORCE_REG_STACK_EMPTY_FORCE_MASK (0x00000020u)
#define CSL_DFE_DPDA_FORCE_REG_STACK_EMPTY_FORCE_SHIFT (0x00000005u)
#define CSL_DFE_DPDA_FORCE_REG_STACK_EMPTY_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force prog1_status high */
#define CSL_DFE_DPDA_FORCE_REG_PROG1_FORCE_MASK (0x00000040u)
#define CSL_DFE_DPDA_FORCE_REG_PROG1_FORCE_SHIFT (0x00000006u)
#define CSL_DFE_DPDA_FORCE_REG_PROG1_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force prog2_status high */
#define CSL_DFE_DPDA_FORCE_REG_PROG2_FORCE_MASK (0x00000080u)
#define CSL_DFE_DPDA_FORCE_REG_PROG2_FORCE_SHIFT (0x00000007u)
#define CSL_DFE_DPDA_FORCE_REG_PROG2_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force idle_status high */
#define CSL_DFE_DPDA_FORCE_REG_IDLE_FORCE_MASK (0x00000100u)
#define CSL_DFE_DPDA_FORCE_REG_IDLE_FORCE_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_FORCE_REG_IDLE_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force sc_floatp_error_status high */
#define CSL_DFE_DPDA_FORCE_REG_SC_FLOATP_ERROR_FORCE_MASK (0x00000200u)
#define CSL_DFE_DPDA_FORCE_REG_SC_FLOATP_ERROR_FORCE_SHIFT (0x00000009u)
#define CSL_DFE_DPDA_FORCE_REG_SC_FLOATP_ERROR_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force simd_floatp_error_status high */
#define CSL_DFE_DPDA_FORCE_REG_SIMD_FLOATP_ERROR_FORCE_MASK (0x00000400u)
#define CSL_DFE_DPDA_FORCE_REG_SIMD_FLOATP_ERROR_FORCE_SHIFT (0x0000000Au)
#define CSL_DFE_DPDA_FORCE_REG_SIMD_FLOATP_ERROR_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force int_read_complete_status high */
#define CSL_DFE_DPDA_FORCE_REG_INT_READ_COMPLETE_FORCE_MASK (0x00000800u)
#define CSL_DFE_DPDA_FORCE_REG_INT_READ_COMPLETE_FORCE_SHIFT (0x0000000Bu)
#define CSL_DFE_DPDA_FORCE_REG_INT_READ_COMPLETE_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force int_processed_status high */
#define CSL_DFE_DPDA_FORCE_REG_INT_PROCESSED_FORCE_MASK (0x00001000u)
#define CSL_DFE_DPDA_FORCE_REG_INT_PROCESSED_FORCE_SHIFT (0x0000000Cu)
#define CSL_DFE_DPDA_FORCE_REG_INT_PROCESSED_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force lutfill_exception_status high */
#define CSL_DFE_DPDA_FORCE_REG_LUTFILL_EXCEPTION_FORCE_MASK (0x00002000u)
#define CSL_DFE_DPDA_FORCE_REG_LUTFILL_EXCEPTION_FORCE_SHIFT (0x0000000Du)
#define CSL_DFE_DPDA_FORCE_REG_LUTFILL_EXCEPTION_FORCE_RESETVAL (0x00000000u)

/* Set to 1 to force reserved_status high (to be specified) */
#define CSL_DFE_DPDA_FORCE_REG_RESERVED_FORCE_MASK (0xFFFFC000u)
#define CSL_DFE_DPDA_FORCE_REG_RESERVED_FORCE_SHIFT (0x0000000Eu)
#define CSL_DFE_DPDA_FORCE_REG_RESERVED_FORCE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_FORCE_REG_ADDR (0x0000000Cu)
#define CSL_DFE_DPDA_FORCE_REG_RESETVAL (0x00000000u)

/* INITS */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 25;
    Uint32 clear_data : 1;
    Uint32 init_state : 1;
    Uint32 init_clk_gate : 1;
    Uint32 inits_ssel : 4;
#else 
    Uint32 inits_ssel : 4;
    Uint32 init_clk_gate : 1;
    Uint32 init_state : 1;
    Uint32 clear_data : 1;
    Uint32 rsvd0 : 25;
#endif 
} CSL_DFE_DPDA_INITS_REG;

/* Inits selection */
#define CSL_DFE_DPDA_INITS_REG_INITS_SSEL_MASK (0x0000000Fu)
#define CSL_DFE_DPDA_INITS_REG_INITS_SSEL_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_INITS_REG_INITS_SSEL_RESETVAL (0x00000000u)

/* Init clock gating signal.  Not used. */
#define CSL_DFE_DPDA_INITS_REG_INIT_CLK_GATE_MASK (0x00000010u)
#define CSL_DFE_DPDA_INITS_REG_INIT_CLK_GATE_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_INITS_REG_INIT_CLK_GATE_RESETVAL (0x00000001u)

/* init state */
#define CSL_DFE_DPDA_INITS_REG_INIT_STATE_MASK (0x00000020u)
#define CSL_DFE_DPDA_INITS_REG_INIT_STATE_SHIFT (0x00000005u)
#define CSL_DFE_DPDA_INITS_REG_INIT_STATE_RESETVAL (0x00000001u)

/* clear data */
#define CSL_DFE_DPDA_INITS_REG_CLEAR_DATA_MASK (0x00000040u)
#define CSL_DFE_DPDA_INITS_REG_CLEAR_DATA_SHIFT (0x00000006u)
#define CSL_DFE_DPDA_INITS_REG_CLEAR_DATA_RESETVAL (0x00000001u)

#define CSL_DFE_DPDA_INITS_REG_ADDR (0x00000080u)
#define CSL_DFE_DPDA_INITS_REG_RESETVAL (0x00000070u)

/* JACOB_STATIC */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 6;
    Uint32 input_scale : 10;
    Uint32 reserved : 8;
    Uint32 lutfill_fp2i : 8;
#else 
    Uint32 lutfill_fp2i : 8;
    Uint32 reserved : 8;
    Uint32 input_scale : 10;
    Uint32 rsvd0 : 6;
#endif 
} CSL_DFE_DPDA_JACOB_STATIC_REG;

/* Scale factor of the conversion from custom floating point to integer. This is only used in the poly2lut operation. Not in the jacobian top but actually in between the simd engine and the interface between the dpda and dpd. */
#define CSL_DFE_DPDA_JACOB_STATIC_REG_LUTFILL_FP2I_MASK (0x000000FFu)
#define CSL_DFE_DPDA_JACOB_STATIC_REG_LUTFILL_FP2I_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JACOB_STATIC_REG_LUTFILL_FP2I_RESETVAL (0x00000000u)

/* Not used anymore.  */
#define CSL_DFE_DPDA_JACOB_STATIC_REG_RESERVED_MASK (0x0000FF00u)
#define CSL_DFE_DPDA_JACOB_STATIC_REG_RESERVED_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_JACOB_STATIC_REG_RESERVED_RESETVAL (0x00000000u)

/* Scale for the jacob generator mag/mag2 block */
#define CSL_DFE_DPDA_JACOB_STATIC_REG_INPUT_SCALE_MASK (0x03FF0000u)
#define CSL_DFE_DPDA_JACOB_STATIC_REG_INPUT_SCALE_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_JACOB_STATIC_REG_INPUT_SCALE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JACOB_STATIC_REG_ADDR (0x00000084u)
#define CSL_DFE_DPDA_JACOB_STATIC_REG_RESETVAL (0x00000000u)

/* MAIN_CONTROL */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd1 : 1;
    Uint32 dsp_antenna_enabled_master : 1;
    Uint32 dsp_interrrupt_master : 1;
    Uint32 cg_dsp_start : 1;
    Uint32 obsolete_interrupt_location : 12;
    Uint32 rsvd0 : 5;
    Uint32 cg_dsp_idle : 1;
    Uint32 obsolete_dsp_interrupt : 1;
    Uint32 set_cg_dsp_resume : 1;
    Uint32 cond_dsp : 1;
    Uint32 stack_depth_to_load : 6;
    Uint32 overwrite_stack_depth : 1;
#else 
    Uint32 overwrite_stack_depth : 1;
    Uint32 stack_depth_to_load : 6;
    Uint32 cond_dsp : 1;
    Uint32 set_cg_dsp_resume : 1;
    Uint32 obsolete_dsp_interrupt : 1;
    Uint32 cg_dsp_idle : 1;
    Uint32 rsvd0 : 5;
    Uint32 obsolete_interrupt_location : 12;
    Uint32 cg_dsp_start : 1;
    Uint32 dsp_interrrupt_master : 1;
    Uint32 dsp_antenna_enabled_master : 1;
    Uint32 rsvd1 : 1;
#endif 
} CSL_DFE_DPDA_MAIN_CONTROL_REG;

/* Enable to load stack_depth_to_load */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_OVERWRITE_STACK_DEPTH_MASK (0x00000001u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_OVERWRITE_STACK_DEPTH_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_OVERWRITE_STACK_DEPTH_RESETVAL (0x00000000u)

/* It is possible to directly manipulate the stack by loading an specific depth.  */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_STACK_DEPTH_TO_LOAD_MASK (0x0000007Eu)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_STACK_DEPTH_TO_LOAD_SHIFT (0x00000001u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_STACK_DEPTH_TO_LOAD_RESETVAL (0x00000000u)

/* cond_dsp allows DSP to set a bit in the cond_register within instruction generator */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_COND_DSP_MASK (0x00000080u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_COND_DSP_SHIFT (0x00000007u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_COND_DSP_RESETVAL (0x00000000u)

/* It sets the dpda to resume in debug mode after it has stalled */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_SET_CG_DSP_RESUME_MASK (0x00000100u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_SET_CG_DSP_RESUME_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_SET_CG_DSP_RESUME_RESETVAL (0x00000000u)

/* not used any more */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_OBSOLETE_DSP_INTERRUPT_MASK (0x00000200u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_OBSOLETE_DSP_INTERRUPT_SHIFT (0x00000009u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_OBSOLETE_DSP_INTERRUPT_RESETVAL (0x00000000u)

/* It makes the DPDA go to IDLE mode */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_CG_DSP_IDLE_MASK (0x00000400u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_CG_DSP_IDLE_SHIFT (0x0000000Au)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_CG_DSP_IDLE_RESETVAL (0x00000000u)

/* Not used anymore.  */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_OBSOLETE_INTERRUPT_LOCATION_MASK (0x0FFF0000u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_OBSOLETE_INTERRUPT_LOCATION_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_OBSOLETE_INTERRUPT_LOCATION_RESETVAL (0x00000000u)

/* 1'b1 used to start the dpda. 1'b0 otherwise.  */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_CG_DSP_START_MASK (0x10000000u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_CG_DSP_START_SHIFT (0x0000001Cu)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_CG_DSP_START_RESETVAL (0x00000000u)

/* 1'b0 = The arbiter controls the dpda interrupt port. 1'b1 = The DSP controls the dpda interrupt port.  */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_DSP_INTERRRUPT_MASTER_MASK (0x20000000u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_DSP_INTERRRUPT_MASTER_SHIFT (0x0000001Du)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_DSP_INTERRRUPT_MASTER_RESETVAL (0x00000001u)

/* 1'b0 = The arbiter controls the antenna_enabled port. 1'b1 = The DSP controls the antenna_enabled port.  */
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_DSP_ANTENNA_ENABLED_MASTER_MASK (0x40000000u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_DSP_ANTENNA_ENABLED_MASTER_SHIFT (0x0000001Eu)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_DSP_ANTENNA_ENABLED_MASTER_RESETVAL (0x00000001u)

#define CSL_DFE_DPDA_MAIN_CONTROL_REG_ADDR (0x00000088u)
#define CSL_DFE_DPDA_MAIN_CONTROL_REG_RESETVAL (0x60000000u)

/* INTERRUPT_PARAMS */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd1 : 4;
    Uint32 param2_dpd : 12;
    Uint32 rsvd0 : 4;
    Uint32 param1_dpd : 12;
#else 
    Uint32 param1_dpd : 12;
    Uint32 rsvd0 : 4;
    Uint32 param2_dpd : 12;
    Uint32 rsvd1 : 4;
#endif 
} CSL_DFE_DPDA_INTERRUPT_PARAMS_REG;

/* param1 for the interrupt request generated by the DSP */
#define CSL_DFE_DPDA_INTERRUPT_PARAMS_REG_PARAM1_DPD_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_INTERRUPT_PARAMS_REG_PARAM1_DPD_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_INTERRUPT_PARAMS_REG_PARAM1_DPD_RESETVAL (0x00000000u)

/* param2 for the interrupt request generated by the DSP */
#define CSL_DFE_DPDA_INTERRUPT_PARAMS_REG_PARAM2_DPD_MASK (0x0FFF0000u)
#define CSL_DFE_DPDA_INTERRUPT_PARAMS_REG_PARAM2_DPD_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_INTERRUPT_PARAMS_REG_PARAM2_DPD_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_INTERRUPT_PARAMS_REG_ADDR (0x0000008Cu)
#define CSL_DFE_DPDA_INTERRUPT_PARAMS_REG_RESETVAL (0x00000000u)

/* INTERRUPT_MAIN_AND_REQ */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd1 : 4;
    Uint32 new_int_dpd : 1;
    Uint32 antenna_dpd : 3;
    Uint32 antenna_enabled_dpd : 8;
    Uint32 rsvd0 : 4;
    Uint32 interrupt_address_dpd : 12;
#else 
    Uint32 interrupt_address_dpd : 12;
    Uint32 rsvd0 : 4;
    Uint32 antenna_enabled_dpd : 8;
    Uint32 antenna_dpd : 3;
    Uint32 new_int_dpd : 1;
    Uint32 rsvd1 : 4;
#endif 
} CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG;

/* Location of the requested interrrupt routine within the program memory. This is a relative offset with respect to the initial position in which each address is 64. It is antenna dependent, but not solution dependent.  */
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_INTERRUPT_ADDRESS_DPD_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_INTERRUPT_ADDRESS_DPD_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_INTERRUPT_ADDRESS_DPD_RESETVAL (0x00000000u)

/* For each bit the corresponding antenna is enabled (1'b1) or disabled (1'b0).  */
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_ANTENNA_ENABLED_DPD_MASK (0x00FF0000u)
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_ANTENNA_ENABLED_DPD_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_ANTENNA_ENABLED_DPD_RESETVAL (0x00000000u)

/* The antenna number associated to the interrupt requested */
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_ANTENNA_DPD_MASK (0x07000000u)
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_ANTENNA_DPD_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_ANTENNA_DPD_RESETVAL (0x00000000u)

/* Raising the bit requestts the interrupt. */
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_NEW_INT_DPD_MASK (0x08000000u)
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_NEW_INT_DPD_SHIFT (0x0000001Bu)
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_NEW_INT_DPD_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_ADDR (0x00000090u)
#define CSL_DFE_DPDA_INTERRUPT_MAIN_AND_REQ_REG_RESETVAL (0x00000000u)

/* EXPONENTS */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 16;
    Uint32 exp_i2fp : 8;
    Uint32 exp_fp2i : 8;
#else 
    Uint32 exp_fp2i : 8;
    Uint32 exp_i2fp : 8;
    Uint32 rsvd0 : 16;
#endif 
} CSL_DFE_DPDA_EXPONENTS_REG;

/* Offset to the exponent. This allows to have an additional scale factor when generating the poly2lut contents */
#define CSL_DFE_DPDA_EXPONENTS_REG_EXP_FP2I_MASK (0x000000FFu)
#define CSL_DFE_DPDA_EXPONENTS_REG_EXP_FP2I_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_EXPONENTS_REG_EXP_FP2I_RESETVAL (0x00000010u)

/* Offset to the exponent while converting from custom floating point to integers */
#define CSL_DFE_DPDA_EXPONENTS_REG_EXP_I2FP_MASK (0x0000FF00u)
#define CSL_DFE_DPDA_EXPONENTS_REG_EXP_I2FP_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_EXPONENTS_REG_EXP_I2FP_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_EXPONENTS_REG_ADDR (0x00000094u)
#define CSL_DFE_DPDA_EXPONENTS_REG_RESETVAL (0x00000010u)

/* TESTBUS_CONTROL */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 27;
    Uint32 testbus_control : 5;
#else 
    Uint32 testbus_control : 5;
    Uint32 rsvd0 : 27;
#endif 
} CSL_DFE_DPDA_TESTBUS_CONTROL_REG;

/* Control to the test bus. Current contents described in RTL */
#define CSL_DFE_DPDA_TESTBUS_CONTROL_REG_TESTBUS_CONTROL_MASK (0x0000001Fu)
#define CSL_DFE_DPDA_TESTBUS_CONTROL_REG_TESTBUS_CONTROL_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_TESTBUS_CONTROL_REG_TESTBUS_CONTROL_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_TESTBUS_CONTROL_REG_ADDR (0x00000098u)
#define CSL_DFE_DPDA_TESTBUS_CONTROL_REG_RESETVAL (0x00000000u)

/* DEBUG_BREAKPOINT */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 breakpoint : 32;
#else 
    Uint32 breakpoint : 32;
#endif 
} CSL_DFE_DPDA_DEBUG_BREAKPOINT_REG;

/* To match with either the program_counter or the timer.  */
#define CSL_DFE_DPDA_DEBUG_BREAKPOINT_REG_BREAKPOINT_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DEBUG_BREAKPOINT_REG_BREAKPOINT_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DEBUG_BREAKPOINT_REG_BREAKPOINT_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DEBUG_BREAKPOINT_REG_ADDR (0x0000009Cu)
#define CSL_DFE_DPDA_DEBUG_BREAKPOINT_REG_RESETVAL (0x00000000u)

/* DEBUG_SETS */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 threshold_slope : 16;
    Uint32 rsvd0 : 13;
    Uint32 abort_current_adaption : 1;
    Uint32 match_program_counter : 2;
#else 
    Uint32 match_program_counter : 2;
    Uint32 abort_current_adaption : 1;
    Uint32 rsvd0 : 13;
    Uint32 threshold_slope : 16;
#endif 
} CSL_DFE_DPDA_DEBUG_SETS_REG;

/* 0 no debugging, 1 break on time, 2 break on program count */
#define CSL_DFE_DPDA_DEBUG_SETS_REG_MATCH_PROGRAM_COUNTER_MASK (0x00000003u)
#define CSL_DFE_DPDA_DEBUG_SETS_REG_MATCH_PROGRAM_COUNTER_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DEBUG_SETS_REG_MATCH_PROGRAM_COUNTER_RESETVAL (0x00000000u)

/* 1'b0: Debugging mode: If exception happens in dpda, send interrupt and stop.  */
#define CSL_DFE_DPDA_DEBUG_SETS_REG_ABORT_CURRENT_ADAPTION_MASK (0x00000004u)
#define CSL_DFE_DPDA_DEBUG_SETS_REG_ABORT_CURRENT_ADAPTION_SHIFT (0x00000002u)
#define CSL_DFE_DPDA_DEBUG_SETS_REG_ABORT_CURRENT_ADAPTION_RESETVAL (0x00000000u)

/* this is an unsigned threshold that checks if the slopes generated to the LUTs in DPD datapath overflow */
#define CSL_DFE_DPDA_DEBUG_SETS_REG_THRESHOLD_SLOPE_MASK (0xFFFF0000u)
#define CSL_DFE_DPDA_DEBUG_SETS_REG_THRESHOLD_SLOPE_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_DEBUG_SETS_REG_THRESHOLD_SLOPE_RESETVAL (0x00000400u)

#define CSL_DFE_DPDA_DEBUG_SETS_REG_ADDR (0x000000A0u)
#define CSL_DFE_DPDA_DEBUG_SETS_REG_RESETVAL (0x04000000u)

/* CR0_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 6;
    Uint32 fb_step_2 : 1;
    Uint32 ref_step_2 : 1;
    Uint32 fbr_offset : 8;
    Uint32 fbw_offset : 8;
    Uint32 refr_offset : 8;
#else 
    Uint32 refr_offset : 8;
    Uint32 fbw_offset : 8;
    Uint32 fbr_offset : 8;
    Uint32 ref_step_2 : 1;
    Uint32 fb_step_2 : 1;
    Uint32 rsvd0 : 6;
#endif 
} CSL_DFE_DPDA_CR0_0_REG;

/* Offset for the read address of the reference read port between the DPDA and CB */
#define CSL_DFE_DPDA_CR0_0_REG_REFR_OFFSET_MASK (0x000000FFu)
#define CSL_DFE_DPDA_CR0_0_REG_REFR_OFFSET_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR0_0_REG_REFR_OFFSET_RESETVAL (0x00000000u)

/* Offset for the read address of the feedback read port between the DPDA and CB */
#define CSL_DFE_DPDA_CR0_0_REG_FBW_OFFSET_MASK (0x0000FF00u)
#define CSL_DFE_DPDA_CR0_0_REG_FBW_OFFSET_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_CR0_0_REG_FBW_OFFSET_RESETVAL (0x00000000u)

/* Offset for the write address of the feedback write port between the DPDA and CB */
#define CSL_DFE_DPDA_CR0_0_REG_FBR_OFFSET_MASK (0x00FF0000u)
#define CSL_DFE_DPDA_CR0_0_REG_FBR_OFFSET_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_CR0_0_REG_FBR_OFFSET_RESETVAL (0x00000000u)

/* If 1'b1, the address associated with the reference will increase by 2 every clock cycle. If 1'b1, it will increase by 1.  */
#define CSL_DFE_DPDA_CR0_0_REG_REF_STEP_2_MASK (0x01000000u)
#define CSL_DFE_DPDA_CR0_0_REG_REF_STEP_2_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_CR0_0_REG_REF_STEP_2_RESETVAL (0x00000000u)

/* If 1'b1, the address associated with the feedback will increase by 2 every clock cycle. If 1'b1, it will increase by 1.  */
#define CSL_DFE_DPDA_CR0_0_REG_FB_STEP_2_MASK (0x02000000u)
#define CSL_DFE_DPDA_CR0_0_REG_FB_STEP_2_SHIFT (0x00000019u)
#define CSL_DFE_DPDA_CR0_0_REG_FB_STEP_2_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR0_0_REG_ADDR (0x000000C0u)
#define CSL_DFE_DPDA_CR0_0_REG_RESETVAL (0x00000000u)

/* CR0_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 cb_snippet_size : 16;
    Uint32 cb_blanking : 8;
    Uint32 cb_blank_off : 8;
#else 
    Uint32 cb_blank_off : 8;
    Uint32 cb_blanking : 8;
    Uint32 cb_snippet_size : 16;
#endif 
} CSL_DFE_DPDA_CR0_1_REG;

/* Number of clock cycles that are blanked off at the beginning of the capture buffer read, before each subcapture buffer is received */
#define CSL_DFE_DPDA_CR0_1_REG_CB_BLANK_OFF_MASK (0x000000FFu)
#define CSL_DFE_DPDA_CR0_1_REG_CB_BLANK_OFF_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR0_1_REG_CB_BLANK_OFF_RESETVAL (0x00000000u)

/* Number of clock cycles that are blanked off at the beginning of each snippet when sending samples through the jacobian generator.  */
#define CSL_DFE_DPDA_CR0_1_REG_CB_BLANKING_MASK (0x0000FF00u)
#define CSL_DFE_DPDA_CR0_1_REG_CB_BLANKING_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_CR0_1_REG_CB_BLANKING_RESETVAL (0x00000000u)

/* Size of the snippet within the capture buffer.  */
#define CSL_DFE_DPDA_CR0_1_REG_CB_SNIPPET_SIZE_MASK (0xFFFF0000u)
#define CSL_DFE_DPDA_CR0_1_REG_CB_SNIPPET_SIZE_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_CR0_1_REG_CB_SNIPPET_SIZE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR0_1_REG_ADDR (0x000000C4u)
#define CSL_DFE_DPDA_CR0_1_REG_RESETVAL (0x00000000u)

/* CR1_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 11;
    Uint32 master_lut : 5;
    Uint32 simd_lut : 16;
#else 
    Uint32 simd_lut : 16;
    Uint32 master_lut : 5;
    Uint32 rsvd0 : 11;
#endif 
} CSL_DFE_DPDA_CR1_0_REG;

/* data[15:0] = {lut_07[1:0],lut_06[1:0],lut_05[1:0],lut_04[1:0],lut_03[1:0],lut_02[1:0],lut_01[1:0],lut_00[1:0]}  */
#define CSL_DFE_DPDA_CR1_0_REG_SIMD_LUT_MASK (0x0000FFFFu)
#define CSL_DFE_DPDA_CR1_0_REG_SIMD_LUT_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR1_0_REG_SIMD_LUT_RESETVAL (0x00000000u)

/* This is the index of the master lut (for Lamarr only 10 possible bases are present)  */
#define CSL_DFE_DPDA_CR1_0_REG_MASTER_LUT_MASK (0x001F0000u)
#define CSL_DFE_DPDA_CR1_0_REG_MASTER_LUT_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_CR1_0_REG_MASTER_LUT_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR1_0_REG_ADDR (0x000000C8u)
#define CSL_DFE_DPDA_CR1_0_REG_RESETVAL (0x00000000u)

/* CR1_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 8;
    Uint32 zcol : 24;
#else 
    Uint32 zcol : 24;
    Uint32 rsvd0 : 8;
#endif 
} CSL_DFE_DPDA_CR1_1_REG;

/* (1'b1)Enables or disables each column of the jacobian generator.  */
#define CSL_DFE_DPDA_CR1_1_REG_ZCOL_MASK (0x00FFFFFFu)
#define CSL_DFE_DPDA_CR1_1_REG_ZCOL_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR1_1_REG_ZCOL_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR1_1_REG_ADDR (0x000000CCu)
#define CSL_DFE_DPDA_CR1_1_REG_RESETVAL (0x00000000u)

/* CR2_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 8;
    Uint32 preg_rmask : 24;
#else 
    Uint32 preg_rmask : 24;
    Uint32 rsvd0 : 8;
#endif 
} CSL_DFE_DPDA_CR2_0_REG;

/* For each of the 24 columns, it enables or disables reading from the preg.  */
#define CSL_DFE_DPDA_CR2_0_REG_PREG_RMASK_MASK (0x00FFFFFFu)
#define CSL_DFE_DPDA_CR2_0_REG_PREG_RMASK_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR2_0_REG_PREG_RMASK_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR2_0_REG_ADDR (0x000000D0u)
#define CSL_DFE_DPDA_CR2_0_REG_RESETVAL (0x00000000u)

/* CR2_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 8;
    Uint32 preg_wmask : 24;
#else 
    Uint32 preg_wmask : 24;
    Uint32 rsvd0 : 8;
#endif 
} CSL_DFE_DPDA_CR2_1_REG;

/* For each of the 24 columns, it enables or disables writing in the preg.  */
#define CSL_DFE_DPDA_CR2_1_REG_PREG_WMASK_MASK (0x00FFFFFFu)
#define CSL_DFE_DPDA_CR2_1_REG_PREG_WMASK_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR2_1_REG_PREG_WMASK_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR2_1_REG_ADDR (0x000000D4u)
#define CSL_DFE_DPDA_CR2_1_REG_RESETVAL (0x00000000u)

/* CR3 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 8;
    Uint32 mux_dly_cmplx_common : 4;
    Uint32 mux_dly_mag_common : 4;
    Uint32 mux_j_dly_master : 2;
    Uint32 loopbk_en : 8;
    Uint32 mag : 1;
    Uint32 interrupt_enable : 1;
    Uint32 mux_lut_gen : 1;
    Uint32 jacobian_2x_mode : 1;
    Uint32 mux_use_jacobian_input : 2;
#else 
    Uint32 mux_use_jacobian_input : 2;
    Uint32 jacobian_2x_mode : 1;
    Uint32 mux_lut_gen : 1;
    Uint32 interrupt_enable : 1;
    Uint32 mag : 1;
    Uint32 loopbk_en : 8;
    Uint32 mux_j_dly_master : 2;
    Uint32 mux_dly_mag_common : 4;
    Uint32 mux_dly_cmplx_common : 4;
    Uint32 rsvd0 : 8;
#endif 
} CSL_DFE_DPDA_CR3_REG;

/* It allows to use the reference as a second input to the scalar engine.  */
#define CSL_DFE_DPDA_CR3_REG_MUX_USE_JACOBIAN_INPUT_MASK (0x00000003u)
#define CSL_DFE_DPDA_CR3_REG_MUX_USE_JACOBIAN_INPUT_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR3_REG_MUX_USE_JACOBIAN_INPUT_RESETVAL (0x00000000u)

/* It sets the jacobian generator in 2x mode if 1'b1 */
#define CSL_DFE_DPDA_CR3_REG_JACOBIAN_2X_MODE_MASK (0x00000004u)
#define CSL_DFE_DPDA_CR3_REG_JACOBIAN_2X_MODE_SHIFT (0x00000002u)
#define CSL_DFE_DPDA_CR3_REG_JACOBIAN_2X_MODE_RESETVAL (0x00000000u)

/* mux_lut_gen from cr3. If 1, jacobian generator and interface with dpd are in lutfill mode.  */
#define CSL_DFE_DPDA_CR3_REG_MUX_LUT_GEN_MASK (0x00000008u)
#define CSL_DFE_DPDA_CR3_REG_MUX_LUT_GEN_SHIFT (0x00000003u)
#define CSL_DFE_DPDA_CR3_REG_MUX_LUT_GEN_RESETVAL (0x00000000u)

/* If 1'b1, DPDA has interrupts enabled (these are the ones coming from either the arbiter or the DSP). If 1'b0, DPDA has interrupts disabled (most of the time).  */
#define CSL_DFE_DPDA_CR3_REG_INTERRUPT_ENABLE_MASK (0x00000010u)
#define CSL_DFE_DPDA_CR3_REG_INTERRUPT_ENABLE_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_CR3_REG_INTERRUPT_ENABLE_RESETVAL (0x00000000u)

/* If 1'b1, the mag2mag block in the jacobian generator is outputing the modulus of the samples (The output of the sqrt block). If 1'b0, the mag squared is used intead. */
#define CSL_DFE_DPDA_CR3_REG_MAG_MASK (0x00000020u)
#define CSL_DFE_DPDA_CR3_REG_MAG_SHIFT (0x00000005u)
#define CSL_DFE_DPDA_CR3_REG_MAG_RESETVAL (0x00000000u)

/* Need to document use */
#define CSL_DFE_DPDA_CR3_REG_LOOPBK_EN_MASK (0x00003FC0u)
#define CSL_DFE_DPDA_CR3_REG_LOOPBK_EN_SHIFT (0x00000006u)
#define CSL_DFE_DPDA_CR3_REG_LOOPBK_EN_RESETVAL (0x00000000u)

/* Possibly not needed.  */
#define CSL_DFE_DPDA_CR3_REG_MUX_J_DLY_MASTER_MASK (0x0000C000u)
#define CSL_DFE_DPDA_CR3_REG_MUX_J_DLY_MASTER_SHIFT (0x0000000Eu)
#define CSL_DFE_DPDA_CR3_REG_MUX_J_DLY_MASTER_RESETVAL (0x00000000u)

/* Additional common delay introduced to the magnitude samples within the jacobian generator, in number of cycles. */
#define CSL_DFE_DPDA_CR3_REG_MUX_DLY_MAG_COMMON_MASK (0x000F0000u)
#define CSL_DFE_DPDA_CR3_REG_MUX_DLY_MAG_COMMON_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_CR3_REG_MUX_DLY_MAG_COMMON_RESETVAL (0x00000000u)

/* Additional common delay introduced to the complex samples within the jacobian generator, in number of cycles.  */
#define CSL_DFE_DPDA_CR3_REG_MUX_DLY_CMPLX_COMMON_MASK (0x00F00000u)
#define CSL_DFE_DPDA_CR3_REG_MUX_DLY_CMPLX_COMMON_SHIFT (0x00000014u)
#define CSL_DFE_DPDA_CR3_REG_MUX_DLY_CMPLX_COMMON_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR3_REG_ADDR (0x000000D8u)
#define CSL_DFE_DPDA_CR3_REG_RESETVAL (0x00000000u)

/* CR4_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd1 : 8;
    Uint32 mux_bypass : 8;
    Uint32 mux_prev_cell : 8;
    Uint32 rsvd0 : 2;
    Uint32 mux_dly_mag_master : 2;
    Uint32 mux_dly_cmplx_master : 2;
    Uint32 mux_bypass_master : 1;
    Uint32 en_master : 1;
#else 
    Uint32 en_master : 1;
    Uint32 mux_bypass_master : 1;
    Uint32 mux_dly_cmplx_master : 2;
    Uint32 mux_dly_mag_master : 2;
    Uint32 rsvd0 : 2;
    Uint32 mux_prev_cell : 8;
    Uint32 mux_bypass : 8;
    Uint32 rsvd1 : 8;
#endif 
} CSL_DFE_DPDA_CR4_0_REG;

/* If 1'b1, the output of the jacobian master cell is enabled. */
#define CSL_DFE_DPDA_CR4_0_REG_EN_MASTER_MASK (0x00000001u)
#define CSL_DFE_DPDA_CR4_0_REG_EN_MASTER_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR4_0_REG_EN_MASTER_RESETVAL (0x00000000u)

/* mux_bypass for the master cell of the jacobian generator */
#define CSL_DFE_DPDA_CR4_0_REG_MUX_BYPASS_MASTER_MASK (0x00000002u)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_BYPASS_MASTER_SHIFT (0x00000001u)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_BYPASS_MASTER_RESETVAL (0x00000000u)

/* mux_dly_complex for the master cell of the jacobian generator. Valid values are 2'b00, 2'b01, 2'b10 */
#define CSL_DFE_DPDA_CR4_0_REG_MUX_DLY_CMPLX_MASTER_MASK (0x0000000Cu)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_DLY_CMPLX_MASTER_SHIFT (0x00000002u)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_DLY_CMPLX_MASTER_RESETVAL (0x00000000u)

/* mux_dly_mag for the master cell of the jacobian generator. Valid values are 2'b00, 2'b01, 2'b10 */
#define CSL_DFE_DPDA_CR4_0_REG_MUX_DLY_MAG_MASTER_MASK (0x00000030u)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_DLY_MAG_MASTER_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_DLY_MAG_MASTER_RESETVAL (0x00000000u)

/* mux_prev_cell for each of the jacobian standard cells. If 1'b1, the output of the LUT in the previous cell is taken as input to the output delay line of the current cell */
#define CSL_DFE_DPDA_CR4_0_REG_MUX_PREV_CELL_MASK (0x0000FF00u)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_PREV_CELL_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_PREV_CELL_RESETVAL (0x00000000u)

/* mux_bypass for each of the jacobian standard cells. If 1'b1, the outptu of the LUT is simply the signal input of the jacobian cell.  */
#define CSL_DFE_DPDA_CR4_0_REG_MUX_BYPASS_MASK (0x00FF0000u)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_BYPASS_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_CR4_0_REG_MUX_BYPASS_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR4_0_REG_ADDR (0x000000DCu)
#define CSL_DFE_DPDA_CR4_0_REG_RESETVAL (0x00000000u)

/* CR4_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 10;
    Uint32 mux_dly_mag : 6;
    Uint32 mux_dly_cmplx : 16;
#else 
    Uint32 mux_dly_cmplx : 16;
    Uint32 mux_dly_mag : 6;
    Uint32 rsvd0 : 10;
#endif 
} CSL_DFE_DPDA_CR4_1_REG;

/* data[15:0] = {mux_dly_cmplx_07[1:0],mux_dly_cmplx_06[1:0],mux_dly_cmplx_05[1:0],mux_dly_cmplx_04[1:0],mux_dly_cmplx_03[1:0],mux_dly_cmplx_02[1:0],mux_dly_cmplx_01[1:0],mux_dly_cmplx_00[1:0]}  */
#define CSL_DFE_DPDA_CR4_1_REG_MUX_DLY_CMPLX_MASK (0x0000FFFFu)
#define CSL_DFE_DPDA_CR4_1_REG_MUX_DLY_CMPLX_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR4_1_REG_MUX_DLY_CMPLX_RESETVAL (0x00000000u)

/* data[15:0] = {mux_dly_mag_07[1:0],mux_dly_mag_06[1:0],mux_dly_mag_05[1:0],mux_dly_mag_04[1:0],mux_dly_mag_03[1:0],mux_dly_mag_02[1:0],mux_dly_mag_01[1:0],mux_dly_mag_00[1:0]}  */
#define CSL_DFE_DPDA_CR4_1_REG_MUX_DLY_MAG_MASK (0x003F0000u)
#define CSL_DFE_DPDA_CR4_1_REG_MUX_DLY_MAG_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_CR4_1_REG_MUX_DLY_MAG_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR4_1_REG_ADDR (0x000000E0u)
#define CSL_DFE_DPDA_CR4_1_REG_RESETVAL (0x00000000u)

/* CR5_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 cr5_lsb : 27;
    Uint32 cb_dpd_in : 1;
    Uint32 cb_request_antenna : 3;
    Uint32 cb_request : 1;
#else 
    Uint32 cb_request : 1;
    Uint32 cb_request_antenna : 3;
    Uint32 cb_dpd_in : 1;
    Uint32 cr5_lsb : 27;
#endif 
} CSL_DFE_DPDA_CR5_0_REG;

/* 1'b1: DPDA requests a capture buffer. 1'b0: DPDA does not request a capture buffer */
#define CSL_DFE_DPDA_CR5_0_REG_CB_REQUEST_MASK (0x00000001u)
#define CSL_DFE_DPDA_CR5_0_REG_CB_REQUEST_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR5_0_REG_CB_REQUEST_RESETVAL (0x00000000u)

/* Number of antenna to which the capture buffer requested corresponds */
#define CSL_DFE_DPDA_CR5_0_REG_CB_REQUEST_ANTENNA_MASK (0x0000000Eu)
#define CSL_DFE_DPDA_CR5_0_REG_CB_REQUEST_ANTENNA_SHIFT (0x00000001u)
#define CSL_DFE_DPDA_CR5_0_REG_CB_REQUEST_ANTENNA_RESETVAL (0x00000000u)

/* If 1'b1, the capture buffer requested corresponds to dpd input. If 1'b0 it corresponds to dpd output. */
#define CSL_DFE_DPDA_CR5_0_REG_CB_DPD_IN_MASK (0x00000010u)
#define CSL_DFE_DPDA_CR5_0_REG_CB_DPD_IN_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_CR5_0_REG_CB_DPD_IN_RESETVAL (0x00000000u)

/* reserved part of cr5 */
#define CSL_DFE_DPDA_CR5_0_REG_CR5_LSB_MASK (0xFFFFFFE0u)
#define CSL_DFE_DPDA_CR5_0_REG_CR5_LSB_SHIFT (0x00000005u)
#define CSL_DFE_DPDA_CR5_0_REG_CR5_LSB_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR5_0_REG_ADDR (0x000000E4u)
#define CSL_DFE_DPDA_CR5_0_REG_RESETVAL (0x00000000u)

/* CR5_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 6;
    Uint32 cr5_msb : 26;
#else 
    Uint32 cr5_msb : 26;
    Uint32 rsvd0 : 6;
#endif 
} CSL_DFE_DPDA_CR5_1_REG;

/* reserved part of cr5 */
#define CSL_DFE_DPDA_CR5_1_REG_CR5_MSB_MASK (0x03FFFFFFu)
#define CSL_DFE_DPDA_CR5_1_REG_CR5_MSB_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CR5_1_REG_CR5_MSB_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CR5_1_REG_ADDR (0x000000E8u)
#define CSL_DFE_DPDA_CR5_1_REG_RESETVAL (0x00000000u)

/* JACOB_OP_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 2;
    Uint32 sc_accum : 3;
    Uint32 sc_mult : 3;
    Uint32 sc_mag : 1;
    Uint32 sc_sab : 3;
    Uint32 sc_saa : 3;
    Uint32 sc_smag : 3;
    Uint32 sc_smb : 3;
    Uint32 sc_sma : 3;
    Uint32 bc_enable : 1;
    Uint32 bc_s : 3;
    Uint32 ref_ram : 1;
    Uint32 fb_ram : 2;
    Uint32 load : 1;
#else 
    Uint32 load : 1;
    Uint32 fb_ram : 2;
    Uint32 ref_ram : 1;
    Uint32 bc_s : 3;
    Uint32 bc_enable : 1;
    Uint32 sc_sma : 3;
    Uint32 sc_smb : 3;
    Uint32 sc_smag : 3;
    Uint32 sc_saa : 3;
    Uint32 sc_sab : 3;
    Uint32 sc_mag : 1;
    Uint32 sc_mult : 3;
    Uint32 sc_accum : 3;
    Uint32 rsvd0 : 2;
#endif 
} CSL_DFE_DPDA_JACOB_OP_0_REG;

/* load ram address counters d,z,ref,fb to their initial values */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_LOAD_MASK (0x00000001u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_LOAD_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_LOAD_RESETVAL (0x00000000u)

/* Feedback ram enables. 2'b00 Idle, 2'b01 Write, 2'b10 Read, 2'b11 Both  */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_FB_RAM_MASK (0x00000006u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_FB_RAM_SHIFT (0x00000001u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_FB_RAM_RESETVAL (0x00000000u)

/* Reference ram enable. 1'b0 Idle, 1'b1 Read */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_REF_RAM_MASK (0x00000008u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_REF_RAM_SHIFT (0x00000003u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_REF_RAM_RESETVAL (0x00000000u)

/* select  for broadcast line (0: sc_reg, 1: add, 2: mult, 3: ref, 4: fb, 5: div, 6: master column) */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_BC_S_MASK (0x00000070u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_BC_S_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_BC_S_RESETVAL (0x00000000u)

/* enable for broadcast line, active high */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_BC_ENABLE_MASK (0x00000080u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_BC_ENABLE_SHIFT (0x00000007u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_BC_ENABLE_RESETVAL (0x00000000u)

/* sc_sma (sc_reg, add, mult, ref, fb, SIMD,zero, hold) */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SMA_MASK (0x00000700u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SMA_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SMA_RESETVAL (0x00000000u)

/* sc_smb (sc_reg, add, mult, ref, fb, SIMD,zero, hold) */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SMB_MASK (0x00003800u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SMB_SHIFT (0x0000000Bu)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SMB_RESETVAL (0x00000000u)

/* sc_smag (sc_reg, add, mult, ref, fb, SIMD,zero, hold) */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SMAG_MASK (0x0001C000u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SMAG_SHIFT (0x0000000Eu)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SMAG_RESETVAL (0x00000000u)

/* sc_saa (sc_reg, add, mult, ref, fb, SIMD,zero, hold) */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SAA_MASK (0x000E0000u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SAA_SHIFT (0x00000011u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SAA_RESETVAL (0x00000000u)

/* sc_sab (sc_reg, add, mult, ref, fb, SIMD,zero, hold) */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SAB_MASK (0x00700000u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SAB_SHIFT (0x00000014u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_SAB_RESETVAL (0x00000000u)

/* sc_mag (noop=>cken=0,  accum ) */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_MAG_MASK (0x00800000u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_MAG_SHIFT (0x00000017u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_MAG_RESETVAL (0x00000000u)

/* sc_mult  (noop=>cken=0, AxB, AxB*, Re(A)/Re(B), sqrt(Re(A)), 1/Re(B)) */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_MULT_MASK (0x07000000u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_MULT_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_MULT_RESETVAL (0x00000000u)

/* sc_accum (noop=>cken=0,A+B, A-B,accum(A),max ) */
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_ACCUM_MASK (0x38000000u)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_ACCUM_SHIFT (0x0000001Bu)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_SC_ACCUM_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JACOB_OP_0_REG_ADDR (0x000000ECu)
#define CSL_DFE_DPDA_JACOB_OP_0_REG_RESETVAL (0x00000000u)

/* JACOB_OP_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 fb_wsrc : 1;
    Uint32 sc_compare : 1;
    Uint32 sc_reg_add : 6;
    Uint32 sc_reg_con : 4;
#else 
    Uint32 sc_reg_con : 4;
    Uint32 sc_reg_add : 6;
    Uint32 sc_compare : 1;
    Uint32 fb_wsrc : 1;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_JACOB_OP_1_REG;

/* sc_reg_con (0 - noop, 1- read, writes from 2-max,3- sqrt, 4-sum_mag2, 5-asa, 6-cmpy, 7-div, 8-sc_reg, 9-simd) */
#define CSL_DFE_DPDA_JACOB_OP_1_REG_SC_REG_CON_MASK (0x0000000Fu)
#define CSL_DFE_DPDA_JACOB_OP_1_REG_SC_REG_CON_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JACOB_OP_1_REG_SC_REG_CON_RESETVAL (0x00000000u)

/* sc_reg_add (shared between read and write) */
#define CSL_DFE_DPDA_JACOB_OP_1_REG_SC_REG_ADD_MASK (0x000003F0u)
#define CSL_DFE_DPDA_JACOB_OP_1_REG_SC_REG_ADD_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_JACOB_OP_1_REG_SC_REG_ADD_RESETVAL (0x00000000u)

/* sc_compare */
#define CSL_DFE_DPDA_JACOB_OP_1_REG_SC_COMPARE_MASK (0x00000400u)
#define CSL_DFE_DPDA_JACOB_OP_1_REG_SC_COMPARE_SHIFT (0x0000000Au)
#define CSL_DFE_DPDA_JACOB_OP_1_REG_SC_COMPARE_RESETVAL (0x00000000u)

/* fb_wsrc */
#define CSL_DFE_DPDA_JACOB_OP_1_REG_FB_WSRC_MASK (0x00000800u)
#define CSL_DFE_DPDA_JACOB_OP_1_REG_FB_WSRC_SHIFT (0x0000000Bu)
#define CSL_DFE_DPDA_JACOB_OP_1_REG_FB_WSRC_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JACOB_OP_1_REG_ADDR (0x000000F0u)
#define CSL_DFE_DPDA_JACOB_OP_1_REG_RESETVAL (0x00000000u)

/* SIMD_OP_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 simd_sum_op : 3;
    Uint32 simd_sum_inb : 1;
    Uint32 simd_sum_ina : 1;
    Uint32 simd_mult : 3;
    Uint32 simd_mult_inb : 2;
    Uint32 simd_mult_ina : 2;
    Uint32 simd_ck_en : 1;
    Uint32 zpreg1 : 1;
    Uint32 zpreg0 : 1;
    Uint32 preg1_right_shift : 1;
    Uint32 preg0_left_shift : 1;
    Uint32 preg_w_src : 2;
    Uint32 preg_wen : 1;
    Uint32 preg_ren : 3;
#else 
    Uint32 preg_ren : 3;
    Uint32 preg_wen : 1;
    Uint32 preg_w_src : 2;
    Uint32 preg0_left_shift : 1;
    Uint32 preg1_right_shift : 1;
    Uint32 zpreg0 : 1;
    Uint32 zpreg1 : 1;
    Uint32 simd_ck_en : 1;
    Uint32 simd_mult_ina : 2;
    Uint32 simd_mult_inb : 2;
    Uint32 simd_mult : 3;
    Uint32 simd_sum_ina : 1;
    Uint32 simd_sum_inb : 1;
    Uint32 simd_sum_op : 3;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_SIMD_OP_0_REG;

/* enables for destinations preg0, preg1, and preg2 */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG_REN_MASK (0x00000007u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG_REN_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG_REN_RESETVAL (0x00000000u)

/*  write enable for the solutions memory. Reads and  write may not be enabled at the same time */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG_WEN_MASK (0x00000008u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG_WEN_SHIFT (0x00000003u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG_WEN_RESETVAL (0x00000000u)

/* Source for writing in solutions memory   0 - preg0, 1 - preg1, 2 - adder, 3 - force to zero */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG_W_SRC_MASK (0x00000030u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG_W_SRC_SHIFT (0x00000004u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG_W_SRC_RESETVAL (0x00000000u)

/* If 1'b1, the contents of preg0 are shifted to the left.  */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG0_LEFT_SHIFT_MASK (0x00000040u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG0_LEFT_SHIFT_SHIFT (0x00000006u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG0_LEFT_SHIFT_RESETVAL (0x00000000u)

/* If 1'b1, the contents of preg1 are shifted to the right */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG1_RIGHT_SHIFT_MASK (0x00000080u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG1_RIGHT_SHIFT_SHIFT (0x00000007u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_PREG1_RIGHT_SHIFT_RESETVAL (0x00000000u)

/* If 1'b1, preg0 is reset */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_ZPREG0_MASK (0x00000100u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_ZPREG0_SHIFT (0x00000008u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_ZPREG0_RESETVAL (0x00000000u)

/* If 1;b1, preg1 and preg2 are reset */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_ZPREG1_MASK (0x00000200u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_ZPREG1_SHIFT (0x00000009u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_ZPREG1_RESETVAL (0x00000000u)

/* If 1;b1, the SIMD engine is enabled.  */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_CK_EN_MASK (0x00000400u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_CK_EN_SHIFT (0x0000000Au)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_CK_EN_RESETVAL (0x00000000u)

/* Input A to the multipliers in the SIMD: 2'b00 0, 2'b01 Jacobian, 2'b10 Broadcast, 2'b11 Preg1 */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_MULT_INA_MASK (0x00001800u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_MULT_INA_SHIFT (0x0000000Bu)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_MULT_INA_RESETVAL (0x00000000u)

/* Input B to the multipliers in the SIMD: 2'b00 0, 2'b01 Jacobian, 2'b10 Broadcast, 2'b11 Preg2 */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_MULT_INB_MASK (0x00006000u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_MULT_INB_SHIFT (0x0000000Du)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_MULT_INB_RESETVAL (0x00000000u)

/* operation in the SIMD multipliers (cmult, mag^2), conjA, conjB .  0 AxB,  2 A*xB, 3 AxA*=mag^2(A), 4 AxB*,  5 A*xA=mag^2(A), 6 A*xB*=(AxB)*  Useless ops , 1 AxA,7 A*xA*.   */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_MULT_MASK (0x00038000u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_MULT_SHIFT (0x0000000Fu)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_MULT_RESETVAL (0x00000000u)

/* Input to the A branch in the accumulators of the SIMD (1'b0 broadcast, 1'b1 preg0) */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_SUM_INA_MASK (0x00040000u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_SUM_INA_SHIFT (0x00000012u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_SUM_INA_RESETVAL (0x00000000u)

/* Input to the B branch in the accumulators of the SIMD (1'b0 cmpy, 1'b1 preg2) */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_SUM_INB_MASK (0x00080000u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_SUM_INB_SHIFT (0x00000013u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_SUM_INB_RESETVAL (0x00000000u)

/* Operation in the tree and accumulator (3'b000 Noop/3'b001 add/3'b010 sub/3'b011 max/3'b100 lutfill/3'b101 scalar/3'b110 accum ). Tree operates on inB. Tree has two outputs - a 3 word vector for LUTfill and a scalar for scalar operations.  Max output is to scalar.  */
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_SUM_OP_MASK (0x00700000u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_SUM_OP_SHIFT (0x00000014u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_SIMD_SUM_OP_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SIMD_OP_0_REG_ADDR (0x000000F4u)
#define CSL_DFE_DPDA_SIMD_OP_0_REG_RESETVAL (0x00000000u)

/* SIMD_OP_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 3;
    Uint32 ig_inmediate : 8;
    Uint32 ig_register_comparison : 1;
    Uint32 ig_op : 2;
    Uint32 ig_dest : 6;
    Uint32 ig_srcb : 6;
    Uint32 ig_srca : 6;
#else 
    Uint32 ig_srca : 6;
    Uint32 ig_srcb : 6;
    Uint32 ig_dest : 6;
    Uint32 ig_op : 2;
    Uint32 ig_register_comparison : 1;
    Uint32 ig_inmediate : 8;
    Uint32 rsvd0 : 3;
#endif 
} CSL_DFE_DPDA_SIMD_OP_1_REG;

/* Address of source A in the instruction generator regfile */
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_SRCA_MASK (0x0000003Fu)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_SRCA_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_SRCA_RESETVAL (0x00000000u)

/* Address of source B in the instruction generator regfile */
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_SRCB_MASK (0x00000FC0u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_SRCB_SHIFT (0x00000006u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_SRCB_RESETVAL (0x00000000u)

/* Address to write in the instruction generator regfile. If 6'b0, no writes happen with this SIMD instruction */
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_DEST_MASK (0x0003F000u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_DEST_SHIFT (0x0000000Cu)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_DEST_RESETVAL (0x00000000u)

/*  (0 A+B, 1 A-B,2 bitwise A&B then or all bits, 3-load srcA to dest) */
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_OP_MASK (0x000C0000u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_OP_SHIFT (0x00000012u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_OP_RESETVAL (0x00000000u)

/* Enable to register ig0 and igneg in the instruction generator */
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_REGISTER_COMPARISON_MASK (0x00100000u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_REGISTER_COMPARISON_SHIFT (0x00000014u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_REGISTER_COMPARISON_RESETVAL (0x00000000u)

/* Immediate for instruction generator regfile operator */
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_INMEDIATE_MASK (0x1FE00000u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_INMEDIATE_SHIFT (0x00000015u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_IG_INMEDIATE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SIMD_OP_1_REG_ADDR (0x000000F8u)
#define CSL_DFE_DPDA_SIMD_OP_1_REG_RESETVAL (0x00000000u)

/* LUTFILL_OP */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 8;
    Uint32 csynch : 1;
    Uint32 fsynch : 1;
    Uint32 block_enable : 17;
    Uint32 row : 3;
    Uint32 lutfill_output : 1;
    Uint32 lutfill_firstpass : 1;
#else 
    Uint32 lutfill_firstpass : 1;
    Uint32 lutfill_output : 1;
    Uint32 row : 3;
    Uint32 block_enable : 17;
    Uint32 fsynch : 1;
    Uint32 csynch : 1;
    Uint32 rsvd0 : 8;
#endif 
} CSL_DFE_DPDA_LUTFILL_OP_REG;

/* If 1'b1, the instruction corresponds to a first pass for a specific row within 1 or more blocks */
#define CSL_DFE_DPDA_LUTFILL_OP_REG_LUTFILL_FIRSTPASS_MASK (0x00000001u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_LUTFILL_FIRSTPASS_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_LUTFILL_FIRSTPASS_RESETVAL (0x00000000u)

/* If 1'b1, the instruction corresponds to the last pass for a specific row within 1 or more blocks */
#define CSL_DFE_DPDA_LUTFILL_OP_REG_LUTFILL_OUTPUT_MASK (0x00000002u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_LUTFILL_OUTPUT_SHIFT (0x00000001u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_LUTFILL_OUTPUT_RESETVAL (0x00000000u)

/* Indicates the row (within 1 or more blocks) that are written. Check DPD datapath documentation for mapping to actual physical rows depending on the mode.  */
#define CSL_DFE_DPDA_LUTFILL_OP_REG_ROW_MASK (0x0000001Cu)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_ROW_SHIFT (0x00000002u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_ROW_RESETVAL (0x00000000u)

/* 16 bits, 1 for each possible block in DPD datapath. Lamarr only instantiates 4. Only those blocks enabled will record the samples.  */
#define CSL_DFE_DPDA_LUTFILL_OP_REG_BLOCK_ENABLE_MASK (0x003FFFE0u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_BLOCK_ENABLE_SHIFT (0x00000005u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_BLOCK_ENABLE_RESETVAL (0x00000000u)

/* Pulsed signal that goes up when a synch is sent from DPDA to DPD datapath for the fine DPD cells.  */
#define CSL_DFE_DPDA_LUTFILL_OP_REG_FSYNCH_MASK (0x00400000u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_FSYNCH_SHIFT (0x00000016u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_FSYNCH_RESETVAL (0x00000000u)

/* Pulsed signal that goes up when a synch is sent from DPDA to DPD datapath for the coarse DPD cells. */
#define CSL_DFE_DPDA_LUTFILL_OP_REG_CSYNCH_MASK (0x00800000u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_CSYNCH_SHIFT (0x00000017u)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_CSYNCH_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_LUTFILL_OP_REG_ADDR (0x000000FCu)
#define CSL_DFE_DPDA_LUTFILL_OP_REG_RESETVAL (0x00000000u)

/* IG_COUNTERS */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd1 : 3;
    Uint32 repeatcnt : 14;
    Uint32 rsvd0 : 3;
    Uint32 program_cnt_dly1 : 12;
#else 
    Uint32 program_cnt_dly1 : 12;
    Uint32 rsvd0 : 3;
    Uint32 repeatcnt : 14;
    Uint32 rsvd1 : 3;
#endif 
} CSL_DFE_DPDA_IG_COUNTERS_REG;

/* This is program counter from the previous cycle. Need to read before accessing the instruction memory to let the system in the same condition afterwards */
#define CSL_DFE_DPDA_IG_COUNTERS_REG_PROGRAM_CNT_DLY1_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_IG_COUNTERS_REG_PROGRAM_CNT_DLY1_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_IG_COUNTERS_REG_PROGRAM_CNT_DLY1_RESETVAL (0x00000000u)

/* This is repeat counter for the current instruction being executed. Relevant in SIMD_OP, JACOB_OP and LUTFILL_OP */
#define CSL_DFE_DPDA_IG_COUNTERS_REG_REPEATCNT_MASK (0x1FFF8000u)
#define CSL_DFE_DPDA_IG_COUNTERS_REG_REPEATCNT_SHIFT (0x0000000Fu)
#define CSL_DFE_DPDA_IG_COUNTERS_REG_REPEATCNT_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_IG_COUNTERS_REG_ADDR (0x00000100u)
#define CSL_DFE_DPDA_IG_COUNTERS_REG_RESETVAL (0x00000000u)

/* TIME_REG */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 time_reg : 32;
#else 
    Uint32 time_reg : 32;
#endif 
} CSL_DFE_DPDA_TIME_REG_REG;

/* Internal timer register.  */
#define CSL_DFE_DPDA_TIME_REG_REG_TIME_REG_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_TIME_REG_REG_TIME_REG_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_TIME_REG_REG_TIME_REG_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_TIME_REG_REG_ADDR (0x00000104u)
#define CSL_DFE_DPDA_TIME_REG_REG_RESETVAL (0x00000000u)

/* LUTFILL_MAIN */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 22;
    Uint32 dpd_clken : 1;
    Uint32 step_counter : 9;
#else 
    Uint32 step_counter : 9;
    Uint32 dpd_clken : 1;
    Uint32 rsvd0 : 22;
#endif 
} CSL_DFE_DPDA_LUTFILL_MAIN_REG;

/* Tracks the step counter variable. */
#define CSL_DFE_DPDA_LUTFILL_MAIN_REG_STEP_COUNTER_MASK (0x000001FFu)
#define CSL_DFE_DPDA_LUTFILL_MAIN_REG_STEP_COUNTER_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_LUTFILL_MAIN_REG_STEP_COUNTER_RESETVAL (0x00000000u)

/* The interface with dpd is enabled. */
#define CSL_DFE_DPDA_LUTFILL_MAIN_REG_DPD_CLKEN_MASK (0x00000200u)
#define CSL_DFE_DPDA_LUTFILL_MAIN_REG_DPD_CLKEN_SHIFT (0x00000009u)
#define CSL_DFE_DPDA_LUTFILL_MAIN_REG_DPD_CLKEN_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_LUTFILL_MAIN_REG_ADDR (0x00000108u)
#define CSL_DFE_DPDA_LUTFILL_MAIN_REG_RESETVAL (0x00000000u)

/* LUTFILL_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd1 : 6;
    Uint32 dpd_slope_q0 : 10;
    Uint32 rsvd0 : 6;
    Uint32 dpd_slope_i0 : 10;
#else 
    Uint32 dpd_slope_i0 : 10;
    Uint32 rsvd0 : 6;
    Uint32 dpd_slope_q0 : 10;
    Uint32 rsvd1 : 6;
#endif 
} CSL_DFE_DPDA_LUTFILL_0_REG;

/* Value in the current clock cycle of the slope going into dpda, for the first out of three exits, addressing a row, real part.  */
#define CSL_DFE_DPDA_LUTFILL_0_REG_DPD_SLOPE_I0_MASK (0x000003FFu)
#define CSL_DFE_DPDA_LUTFILL_0_REG_DPD_SLOPE_I0_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_LUTFILL_0_REG_DPD_SLOPE_I0_RESETVAL (0x00000000u)

/* Value in the current clock cycle of the slope going into dpda, for the first out of three exits, addressing a row, imag part.  */
#define CSL_DFE_DPDA_LUTFILL_0_REG_DPD_SLOPE_Q0_MASK (0x03FF0000u)
#define CSL_DFE_DPDA_LUTFILL_0_REG_DPD_SLOPE_Q0_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_LUTFILL_0_REG_DPD_SLOPE_Q0_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_LUTFILL_0_REG_ADDR (0x0000010Cu)
#define CSL_DFE_DPDA_LUTFILL_0_REG_RESETVAL (0x00000000u)

/* LUTFILL_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd1 : 6;
    Uint32 dpd_slope_q1 : 10;
    Uint32 rsvd0 : 6;
    Uint32 dpd_slope_i1 : 10;
#else 
    Uint32 dpd_slope_i1 : 10;
    Uint32 rsvd0 : 6;
    Uint32 dpd_slope_q1 : 10;
    Uint32 rsvd1 : 6;
#endif 
} CSL_DFE_DPDA_LUTFILL_1_REG;

/* Value in the current clock cycle of the slope going into dpda, for the second out of three exits, addressing a row, real part.  */
#define CSL_DFE_DPDA_LUTFILL_1_REG_DPD_SLOPE_I1_MASK (0x000003FFu)
#define CSL_DFE_DPDA_LUTFILL_1_REG_DPD_SLOPE_I1_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_LUTFILL_1_REG_DPD_SLOPE_I1_RESETVAL (0x00000000u)

/* Value in the current clock cycle of the slope going into dpda, for the second out of three exits, addressing a row, imag part.  */
#define CSL_DFE_DPDA_LUTFILL_1_REG_DPD_SLOPE_Q1_MASK (0x03FF0000u)
#define CSL_DFE_DPDA_LUTFILL_1_REG_DPD_SLOPE_Q1_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_LUTFILL_1_REG_DPD_SLOPE_Q1_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_LUTFILL_1_REG_ADDR (0x00000110u)
#define CSL_DFE_DPDA_LUTFILL_1_REG_RESETVAL (0x00000000u)

/* LUTFILL_2 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd1 : 6;
    Uint32 dpd_slope_q2 : 10;
    Uint32 rsvd0 : 6;
    Uint32 dpd_slope_i2 : 10;
#else 
    Uint32 dpd_slope_i2 : 10;
    Uint32 rsvd0 : 6;
    Uint32 dpd_slope_q2 : 10;
    Uint32 rsvd1 : 6;
#endif 
} CSL_DFE_DPDA_LUTFILL_2_REG;

/* Value in the current clock cycle of the slope going into dpda, for the third out of three exits, addressing a row, real part.  */
#define CSL_DFE_DPDA_LUTFILL_2_REG_DPD_SLOPE_I2_MASK (0x000003FFu)
#define CSL_DFE_DPDA_LUTFILL_2_REG_DPD_SLOPE_I2_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_LUTFILL_2_REG_DPD_SLOPE_I2_RESETVAL (0x00000000u)

/* Value in the current clock cycle of the slope going into dpda, for the third out of three exits, addressing a row, imag part.  */
#define CSL_DFE_DPDA_LUTFILL_2_REG_DPD_SLOPE_Q2_MASK (0x03FF0000u)
#define CSL_DFE_DPDA_LUTFILL_2_REG_DPD_SLOPE_Q2_SHIFT (0x00000010u)
#define CSL_DFE_DPDA_LUTFILL_2_REG_DPD_SLOPE_Q2_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_LUTFILL_2_REG_ADDR (0x00000114u)
#define CSL_DFE_DPDA_LUTFILL_2_REG_RESETVAL (0x00000000u)

/* CFP_BROADCAST_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 se_broadcaste : 8;
    Uint32 rsvd0 : 1;
    Uint32 se_broadcasti : 23;
#else 
    Uint32 se_broadcasti : 23;
    Uint32 rsvd0 : 1;
    Uint32 se_broadcaste : 8;
#endif 
} CSL_DFE_DPDA_CFP_BROADCAST_I_E_REG;

/* SIMD broadcast line real part */
#define CSL_DFE_DPDA_CFP_BROADCAST_I_E_REG_SE_BROADCASTI_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_CFP_BROADCAST_I_E_REG_SE_BROADCASTI_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CFP_BROADCAST_I_E_REG_SE_BROADCASTI_RESETVAL (0x00000000u)

/* SIMD broadcast line exponent */
#define CSL_DFE_DPDA_CFP_BROADCAST_I_E_REG_SE_BROADCASTE_MASK (0xFF000000u)
#define CSL_DFE_DPDA_CFP_BROADCAST_I_E_REG_SE_BROADCASTE_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_CFP_BROADCAST_I_E_REG_SE_BROADCASTE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CFP_BROADCAST_I_E_REG_ADDR (0x00000118u)
#define CSL_DFE_DPDA_CFP_BROADCAST_I_E_REG_RESETVAL (0x00000000u)

/* CFP_BROADCAST_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 se_broadcastq : 23;
#else 
    Uint32 se_broadcastq : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_CFP_BROADCAST_Q_REG;

/* SIMD broadcast line imag part */
#define CSL_DFE_DPDA_CFP_BROADCAST_Q_REG_SE_BROADCASTQ_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_CFP_BROADCAST_Q_REG_SE_BROADCASTQ_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_CFP_BROADCAST_Q_REG_SE_BROADCASTQ_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_CFP_BROADCAST_Q_REG_ADDR (0x0000011Cu)
#define CSL_DFE_DPDA_CFP_BROADCAST_Q_REG_RESETVAL (0x00000000u)

/* JG_MASTER_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 jg_j_out_exp_master : 8;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_real_master : 23;
#else 
    Uint32 jg_j_out_real_master : 23;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_exp_master : 8;
#endif 
} CSL_DFE_DPDA_JG_MASTER_I_E_REG;

/* Jacobian Generator Master Real Part */
#define CSL_DFE_DPDA_JG_MASTER_I_E_REG_JG_J_OUT_REAL_MASTER_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_MASTER_I_E_REG_JG_J_OUT_REAL_MASTER_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_MASTER_I_E_REG_JG_J_OUT_REAL_MASTER_RESETVAL (0x00000000u)

/* Jacobian Generator Master Exponent */
#define CSL_DFE_DPDA_JG_MASTER_I_E_REG_JG_J_OUT_EXP_MASTER_MASK (0xFF000000u)
#define CSL_DFE_DPDA_JG_MASTER_I_E_REG_JG_J_OUT_EXP_MASTER_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JG_MASTER_I_E_REG_JG_J_OUT_EXP_MASTER_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_MASTER_I_E_REG_ADDR (0x00000120u)
#define CSL_DFE_DPDA_JG_MASTER_I_E_REG_RESETVAL (0x00000000u)

/* JG_MASTER_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 jg_j_out_imag_master : 23;
#else 
    Uint32 jg_j_out_imag_master : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_JG_MASTER_Q_REG;

/* Jacobian Generator Master Imag Part */
#define CSL_DFE_DPDA_JG_MASTER_Q_REG_JG_J_OUT_IMAG_MASTER_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_MASTER_Q_REG_JG_J_OUT_IMAG_MASTER_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_MASTER_Q_REG_JG_J_OUT_IMAG_MASTER_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_MASTER_Q_REG_ADDR (0x00000124u)
#define CSL_DFE_DPDA_JG_MASTER_Q_REG_RESETVAL (0x00000000u)

/* JG_COLUMN0_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 jg_j_out_exp_0 : 8;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_real_0 : 23;
#else 
    Uint32 jg_j_out_real_0 : 23;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_exp_0 : 8;
#endif 
} CSL_DFE_DPDA_JG_COLUMN0_I_E_REG;

/* Jacobian Generator Column 0 Real Part */
#define CSL_DFE_DPDA_JG_COLUMN0_I_E_REG_JG_J_OUT_REAL_0_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN0_I_E_REG_JG_J_OUT_REAL_0_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN0_I_E_REG_JG_J_OUT_REAL_0_RESETVAL (0x00000000u)

/* Jacobian Generator Column 0 Exponent */
#define CSL_DFE_DPDA_JG_COLUMN0_I_E_REG_JG_J_OUT_EXP_0_MASK (0xFF000000u)
#define CSL_DFE_DPDA_JG_COLUMN0_I_E_REG_JG_J_OUT_EXP_0_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JG_COLUMN0_I_E_REG_JG_J_OUT_EXP_0_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN0_I_E_REG_ADDR (0x00000128u)
#define CSL_DFE_DPDA_JG_COLUMN0_I_E_REG_RESETVAL (0x00000000u)

/* JG_COLUMN0_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 jg_j_out_imag_0 : 23;
#else 
    Uint32 jg_j_out_imag_0 : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_JG_COLUMN0_Q_REG;

/* Jacobian Generator Column 0 Imag Part */
#define CSL_DFE_DPDA_JG_COLUMN0_Q_REG_JG_J_OUT_IMAG_0_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN0_Q_REG_JG_J_OUT_IMAG_0_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN0_Q_REG_JG_J_OUT_IMAG_0_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN0_Q_REG_ADDR (0x0000012Cu)
#define CSL_DFE_DPDA_JG_COLUMN0_Q_REG_RESETVAL (0x00000000u)

/* JG_COLUMN1_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 jg_j_out_exp_1 : 8;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_real_1 : 23;
#else 
    Uint32 jg_j_out_real_1 : 23;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_exp_1 : 8;
#endif 
} CSL_DFE_DPDA_JG_COLUMN1_I_E_REG;

/* Jacobian Generator Column 1 Real Part */
#define CSL_DFE_DPDA_JG_COLUMN1_I_E_REG_JG_J_OUT_REAL_1_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN1_I_E_REG_JG_J_OUT_REAL_1_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN1_I_E_REG_JG_J_OUT_REAL_1_RESETVAL (0x00000000u)

/* Jacobian Generator Column 1 Exponent */
#define CSL_DFE_DPDA_JG_COLUMN1_I_E_REG_JG_J_OUT_EXP_1_MASK (0xFF000000u)
#define CSL_DFE_DPDA_JG_COLUMN1_I_E_REG_JG_J_OUT_EXP_1_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JG_COLUMN1_I_E_REG_JG_J_OUT_EXP_1_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN1_I_E_REG_ADDR (0x00000130u)
#define CSL_DFE_DPDA_JG_COLUMN1_I_E_REG_RESETVAL (0x00000000u)

/* JG_COLUMN1_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 jg_j_out_imag_1 : 23;
#else 
    Uint32 jg_j_out_imag_1 : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_JG_COLUMN1_Q_REG;

/* Jacobian Generator Column 1 Imag Part */
#define CSL_DFE_DPDA_JG_COLUMN1_Q_REG_JG_J_OUT_IMAG_1_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN1_Q_REG_JG_J_OUT_IMAG_1_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN1_Q_REG_JG_J_OUT_IMAG_1_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN1_Q_REG_ADDR (0x00000134u)
#define CSL_DFE_DPDA_JG_COLUMN1_Q_REG_RESETVAL (0x00000000u)

/* JG_COLUMN2_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 jg_j_out_exp_2 : 8;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_real_2 : 23;
#else 
    Uint32 jg_j_out_real_2 : 23;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_exp_2 : 8;
#endif 
} CSL_DFE_DPDA_JG_COLUMN2_I_E_REG;

/* Jacobian Generator Column 2 Real Part */
#define CSL_DFE_DPDA_JG_COLUMN2_I_E_REG_JG_J_OUT_REAL_2_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN2_I_E_REG_JG_J_OUT_REAL_2_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN2_I_E_REG_JG_J_OUT_REAL_2_RESETVAL (0x00000000u)

/* Jacobian Generator Column 2 Exponent */
#define CSL_DFE_DPDA_JG_COLUMN2_I_E_REG_JG_J_OUT_EXP_2_MASK (0xFF000000u)
#define CSL_DFE_DPDA_JG_COLUMN2_I_E_REG_JG_J_OUT_EXP_2_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JG_COLUMN2_I_E_REG_JG_J_OUT_EXP_2_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN2_I_E_REG_ADDR (0x00000138u)
#define CSL_DFE_DPDA_JG_COLUMN2_I_E_REG_RESETVAL (0x00000000u)

/* JG_COLUMN2_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 jg_j_out_imag_2 : 23;
#else 
    Uint32 jg_j_out_imag_2 : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_JG_COLUMN2_Q_REG;

/* Jacobian Generator Column 2 Imag Part */
#define CSL_DFE_DPDA_JG_COLUMN2_Q_REG_JG_J_OUT_IMAG_2_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN2_Q_REG_JG_J_OUT_IMAG_2_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN2_Q_REG_JG_J_OUT_IMAG_2_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN2_Q_REG_ADDR (0x0000013Cu)
#define CSL_DFE_DPDA_JG_COLUMN2_Q_REG_RESETVAL (0x00000000u)

/* JG_COLUMN3_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 jg_j_out_exp_3 : 8;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_real_3 : 23;
#else 
    Uint32 jg_j_out_real_3 : 23;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_exp_3 : 8;
#endif 
} CSL_DFE_DPDA_JG_COLUMN3_I_E_REG;

/* Jacobian Generator Column 3 Real Part */
#define CSL_DFE_DPDA_JG_COLUMN3_I_E_REG_JG_J_OUT_REAL_3_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN3_I_E_REG_JG_J_OUT_REAL_3_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN3_I_E_REG_JG_J_OUT_REAL_3_RESETVAL (0x00000000u)

/* Jacobian Generator Column 3 Exponent */
#define CSL_DFE_DPDA_JG_COLUMN3_I_E_REG_JG_J_OUT_EXP_3_MASK (0xFF000000u)
#define CSL_DFE_DPDA_JG_COLUMN3_I_E_REG_JG_J_OUT_EXP_3_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JG_COLUMN3_I_E_REG_JG_J_OUT_EXP_3_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN3_I_E_REG_ADDR (0x00000140u)
#define CSL_DFE_DPDA_JG_COLUMN3_I_E_REG_RESETVAL (0x00000000u)

/* JG_COLUMN3_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 jg_j_out_imag_3 : 23;
#else 
    Uint32 jg_j_out_imag_3 : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_JG_COLUMN3_Q_REG;

/* Jacobian Generator Column 3 Imag Part */
#define CSL_DFE_DPDA_JG_COLUMN3_Q_REG_JG_J_OUT_IMAG_3_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN3_Q_REG_JG_J_OUT_IMAG_3_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN3_Q_REG_JG_J_OUT_IMAG_3_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN3_Q_REG_ADDR (0x00000144u)
#define CSL_DFE_DPDA_JG_COLUMN3_Q_REG_RESETVAL (0x00000000u)

/* JG_COLUMN4_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 jg_j_out_exp_4 : 8;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_real_4 : 23;
#else 
    Uint32 jg_j_out_real_4 : 23;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_exp_4 : 8;
#endif 
} CSL_DFE_DPDA_JG_COLUMN4_I_E_REG;

/* Jacobian Generator Column 4 Real Part */
#define CSL_DFE_DPDA_JG_COLUMN4_I_E_REG_JG_J_OUT_REAL_4_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN4_I_E_REG_JG_J_OUT_REAL_4_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN4_I_E_REG_JG_J_OUT_REAL_4_RESETVAL (0x00000000u)

/* Jacobian Generator Column 4 Exponent */
#define CSL_DFE_DPDA_JG_COLUMN4_I_E_REG_JG_J_OUT_EXP_4_MASK (0xFF000000u)
#define CSL_DFE_DPDA_JG_COLUMN4_I_E_REG_JG_J_OUT_EXP_4_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JG_COLUMN4_I_E_REG_JG_J_OUT_EXP_4_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN4_I_E_REG_ADDR (0x00000148u)
#define CSL_DFE_DPDA_JG_COLUMN4_I_E_REG_RESETVAL (0x00000000u)

/* JG_COLUMN4_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 jg_j_out_imag_4 : 23;
#else 
    Uint32 jg_j_out_imag_4 : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_JG_COLUMN4_Q_REG;

/* Jacobian Generator Column 4 Imag Part */
#define CSL_DFE_DPDA_JG_COLUMN4_Q_REG_JG_J_OUT_IMAG_4_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN4_Q_REG_JG_J_OUT_IMAG_4_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN4_Q_REG_JG_J_OUT_IMAG_4_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN4_Q_REG_ADDR (0x0000014Cu)
#define CSL_DFE_DPDA_JG_COLUMN4_Q_REG_RESETVAL (0x00000000u)

/* JG_COLUMN5_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 jg_j_out_exp_5 : 8;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_real_5 : 23;
#else 
    Uint32 jg_j_out_real_5 : 23;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_exp_5 : 8;
#endif 
} CSL_DFE_DPDA_JG_COLUMN5_I_E_REG;

/* Jacobian Generator Column 5 Real Part */
#define CSL_DFE_DPDA_JG_COLUMN5_I_E_REG_JG_J_OUT_REAL_5_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN5_I_E_REG_JG_J_OUT_REAL_5_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN5_I_E_REG_JG_J_OUT_REAL_5_RESETVAL (0x00000000u)

/* Jacobian Generator Column 5 Exponent */
#define CSL_DFE_DPDA_JG_COLUMN5_I_E_REG_JG_J_OUT_EXP_5_MASK (0xFF000000u)
#define CSL_DFE_DPDA_JG_COLUMN5_I_E_REG_JG_J_OUT_EXP_5_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JG_COLUMN5_I_E_REG_JG_J_OUT_EXP_5_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN5_I_E_REG_ADDR (0x00000150u)
#define CSL_DFE_DPDA_JG_COLUMN5_I_E_REG_RESETVAL (0x00000000u)

/* JG_COLUMN5_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 jg_j_out_imag_5 : 23;
#else 
    Uint32 jg_j_out_imag_5 : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_JG_COLUMN5_Q_REG;

/* Jacobian Generator Column 5 Imag Part */
#define CSL_DFE_DPDA_JG_COLUMN5_Q_REG_JG_J_OUT_IMAG_5_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN5_Q_REG_JG_J_OUT_IMAG_5_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN5_Q_REG_JG_J_OUT_IMAG_5_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN5_Q_REG_ADDR (0x00000154u)
#define CSL_DFE_DPDA_JG_COLUMN5_Q_REG_RESETVAL (0x00000000u)

/* JG_COLUMN6_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 jg_j_out_exp_6 : 8;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_real_6 : 23;
#else 
    Uint32 jg_j_out_real_6 : 23;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_exp_6 : 8;
#endif 
} CSL_DFE_DPDA_JG_COLUMN6_I_E_REG;

/* Jacobian Generator Column 6 Real Part */
#define CSL_DFE_DPDA_JG_COLUMN6_I_E_REG_JG_J_OUT_REAL_6_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN6_I_E_REG_JG_J_OUT_REAL_6_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN6_I_E_REG_JG_J_OUT_REAL_6_RESETVAL (0x00000000u)

/* Jacobian Generator Column 6 Exponent */
#define CSL_DFE_DPDA_JG_COLUMN6_I_E_REG_JG_J_OUT_EXP_6_MASK (0xFF000000u)
#define CSL_DFE_DPDA_JG_COLUMN6_I_E_REG_JG_J_OUT_EXP_6_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JG_COLUMN6_I_E_REG_JG_J_OUT_EXP_6_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN6_I_E_REG_ADDR (0x00000158u)
#define CSL_DFE_DPDA_JG_COLUMN6_I_E_REG_RESETVAL (0x00000000u)

/* JG_COLUMN6_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 jg_j_out_imag_6 : 23;
#else 
    Uint32 jg_j_out_imag_6 : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_JG_COLUMN6_Q_REG;

/* Jacobian Generator Column 6 Imag Part */
#define CSL_DFE_DPDA_JG_COLUMN6_Q_REG_JG_J_OUT_IMAG_6_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN6_Q_REG_JG_J_OUT_IMAG_6_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN6_Q_REG_JG_J_OUT_IMAG_6_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN6_Q_REG_ADDR (0x0000015Cu)
#define CSL_DFE_DPDA_JG_COLUMN6_Q_REG_RESETVAL (0x00000000u)

/* JG_COLUMN7_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 jg_j_out_exp_7 : 8;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_real_7 : 23;
#else 
    Uint32 jg_j_out_real_7 : 23;
    Uint32 rsvd0 : 1;
    Uint32 jg_j_out_exp_7 : 8;
#endif 
} CSL_DFE_DPDA_JG_COLUMN7_I_E_REG;

/* Jacobian Generator Column 7 Real Part */
#define CSL_DFE_DPDA_JG_COLUMN7_I_E_REG_JG_J_OUT_REAL_7_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN7_I_E_REG_JG_J_OUT_REAL_7_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN7_I_E_REG_JG_J_OUT_REAL_7_RESETVAL (0x00000000u)

/* Jacobian Generator Column 7 Exponent */
#define CSL_DFE_DPDA_JG_COLUMN7_I_E_REG_JG_J_OUT_EXP_7_MASK (0xFF000000u)
#define CSL_DFE_DPDA_JG_COLUMN7_I_E_REG_JG_J_OUT_EXP_7_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_JG_COLUMN7_I_E_REG_JG_J_OUT_EXP_7_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN7_I_E_REG_ADDR (0x00000160u)
#define CSL_DFE_DPDA_JG_COLUMN7_I_E_REG_RESETVAL (0x00000000u)

/* JG_COLUMN7_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 jg_j_out_imag_7 : 23;
#else 
    Uint32 jg_j_out_imag_7 : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_JG_COLUMN7_Q_REG;

/* Jacobian Generator Column 7 Imag Part */
#define CSL_DFE_DPDA_JG_COLUMN7_Q_REG_JG_J_OUT_IMAG_7_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_JG_COLUMN7_Q_REG_JG_J_OUT_IMAG_7_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_JG_COLUMN7_Q_REG_JG_J_OUT_IMAG_7_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_JG_COLUMN7_Q_REG_ADDR (0x00000164u)
#define CSL_DFE_DPDA_JG_COLUMN7_Q_REG_RESETVAL (0x00000000u)

/* SE_SCALAR_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 se_scalare : 8;
    Uint32 rsvd0 : 1;
    Uint32 se_scalari : 23;
#else 
    Uint32 se_scalari : 23;
    Uint32 rsvd0 : 1;
    Uint32 se_scalare : 8;
#endif 
} CSL_DFE_DPDA_SE_SCALAR_I_E_REG;

/* SIMD Engine, Scalar output, Real Part */
#define CSL_DFE_DPDA_SE_SCALAR_I_E_REG_SE_SCALARI_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SE_SCALAR_I_E_REG_SE_SCALARI_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SE_SCALAR_I_E_REG_SE_SCALARI_RESETVAL (0x00000000u)

/* SIMD Engine, Scalar output, Exponent */
#define CSL_DFE_DPDA_SE_SCALAR_I_E_REG_SE_SCALARE_MASK (0xFF000000u)
#define CSL_DFE_DPDA_SE_SCALAR_I_E_REG_SE_SCALARE_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_SE_SCALAR_I_E_REG_SE_SCALARE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SE_SCALAR_I_E_REG_ADDR (0x00000168u)
#define CSL_DFE_DPDA_SE_SCALAR_I_E_REG_RESETVAL (0x00000000u)

/* SE_SCALAR_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 se_scalarq : 23;
#else 
    Uint32 se_scalarq : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_SE_SCALAR_Q_REG;

/* SIMD Engine, Scalar output, Imag Part */
#define CSL_DFE_DPDA_SE_SCALAR_Q_REG_SE_SCALARQ_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SE_SCALAR_Q_REG_SE_SCALARQ_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SE_SCALAR_Q_REG_SE_SCALARQ_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SE_SCALAR_Q_REG_ADDR (0x0000016Cu)
#define CSL_DFE_DPDA_SE_SCALAR_Q_REG_RESETVAL (0x00000000u)

/* SE_LUTFILL_CFP0_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 se_lutfill0_e : 8;
    Uint32 rsvd0 : 1;
    Uint32 se_lutfill0_i : 23;
#else 
    Uint32 se_lutfill0_i : 23;
    Uint32 rsvd0 : 1;
    Uint32 se_lutfill0_e : 8;
#endif 
} CSL_DFE_DPDA_SE_LUTFILL_CFP0_I_E_REG;

/* SIMD Engine, Lutfill output 0, Real Part */
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_I_E_REG_SE_LUTFILL0_I_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_I_E_REG_SE_LUTFILL0_I_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_I_E_REG_SE_LUTFILL0_I_RESETVAL (0x00000000u)

/* SIMD Engine, Lutfill output 0, Exponent */
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_I_E_REG_SE_LUTFILL0_E_MASK (0xFF000000u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_I_E_REG_SE_LUTFILL0_E_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_I_E_REG_SE_LUTFILL0_E_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_I_E_REG_ADDR (0x00000170u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_I_E_REG_RESETVAL (0x00000000u)

/* SE_LUTFILL_CFP0_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 se_lutfill0_q : 23;
#else 
    Uint32 se_lutfill0_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_SE_LUTFILL_CFP0_Q_REG;

/* SIMD Engine, Lutfill output 0, Imag Part */
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_Q_REG_SE_LUTFILL0_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_Q_REG_SE_LUTFILL0_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_Q_REG_SE_LUTFILL0_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_Q_REG_ADDR (0x00000174u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP0_Q_REG_RESETVAL (0x00000000u)

/* SE_LUTFILL_CFP1_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 se_lutfill1_e : 8;
    Uint32 rsvd0 : 1;
    Uint32 se_lutfill1_i : 23;
#else 
    Uint32 se_lutfill1_i : 23;
    Uint32 rsvd0 : 1;
    Uint32 se_lutfill1_e : 8;
#endif 
} CSL_DFE_DPDA_SE_LUTFILL_CFP1_I_E_REG;

/* SIMD Engine, Lutfill output 1, Real Part */
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_I_E_REG_SE_LUTFILL1_I_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_I_E_REG_SE_LUTFILL1_I_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_I_E_REG_SE_LUTFILL1_I_RESETVAL (0x00000000u)

/* SIMD Engine, Lutfill output 1, Exponent */
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_I_E_REG_SE_LUTFILL1_E_MASK (0xFF000000u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_I_E_REG_SE_LUTFILL1_E_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_I_E_REG_SE_LUTFILL1_E_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_I_E_REG_ADDR (0x00000178u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_I_E_REG_RESETVAL (0x00000000u)

/* SE_LUTFILL_CFP1_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 se_lutfill1_q : 23;
#else 
    Uint32 se_lutfill1_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_SE_LUTFILL_CFP1_Q_REG;

/* SIMD Engine, Lutfill output 1, Imag Part */
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_Q_REG_SE_LUTFILL1_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_Q_REG_SE_LUTFILL1_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_Q_REG_SE_LUTFILL1_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_Q_REG_ADDR (0x0000017Cu)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP1_Q_REG_RESETVAL (0x00000000u)

/* SE_LUTFILL_CFP2_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 se_lutfill2_e : 8;
    Uint32 rsvd0 : 1;
    Uint32 se_lutfill2_i : 23;
#else 
    Uint32 se_lutfill2_i : 23;
    Uint32 rsvd0 : 1;
    Uint32 se_lutfill2_e : 8;
#endif 
} CSL_DFE_DPDA_SE_LUTFILL_CFP2_I_E_REG;

/* SIMD Engine, Lutfill output 2, Real Part */
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_I_E_REG_SE_LUTFILL2_I_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_I_E_REG_SE_LUTFILL2_I_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_I_E_REG_SE_LUTFILL2_I_RESETVAL (0x00000000u)

/* SIMD Engine, Lutfill output 2, Exponent */
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_I_E_REG_SE_LUTFILL2_E_MASK (0xFF000000u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_I_E_REG_SE_LUTFILL2_E_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_I_E_REG_SE_LUTFILL2_E_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_I_E_REG_ADDR (0x00000180u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_I_E_REG_RESETVAL (0x00000000u)

/* SE_LUTFILL_CFP2_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 se_lutfill2_q : 23;
#else 
    Uint32 se_lutfill2_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_SE_LUTFILL_CFP2_Q_REG;

/* SIMD Engine, Lutfill output 2 Imag Part */
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_Q_REG_SE_LUTFILL2_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_Q_REG_SE_LUTFILL2_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_Q_REG_SE_LUTFILL2_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_Q_REG_ADDR (0x00000184u)
#define CSL_DFE_DPDA_SE_LUTFILL_CFP2_Q_REG_RESETVAL (0x00000000u)

/* SC_MULT_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 sc_mult_exp : 8;
    Uint32 rsvd0 : 1;
    Uint32 sc_mult_real_mnt : 23;
#else 
    Uint32 sc_mult_real_mnt : 23;
    Uint32 rsvd0 : 1;
    Uint32 sc_mult_exp : 8;
#endif 
} CSL_DFE_DPDA_SC_MULT_I_E_REG;

/* Scalar Engine, Output of Multiplier, Real Part */
#define CSL_DFE_DPDA_SC_MULT_I_E_REG_SC_MULT_REAL_MNT_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SC_MULT_I_E_REG_SC_MULT_REAL_MNT_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SC_MULT_I_E_REG_SC_MULT_REAL_MNT_RESETVAL (0x00000000u)

/* Scalar Engine, Output of Multiplier, Exponent */
#define CSL_DFE_DPDA_SC_MULT_I_E_REG_SC_MULT_EXP_MASK (0xFF000000u)
#define CSL_DFE_DPDA_SC_MULT_I_E_REG_SC_MULT_EXP_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_SC_MULT_I_E_REG_SC_MULT_EXP_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SC_MULT_I_E_REG_ADDR (0x00000188u)
#define CSL_DFE_DPDA_SC_MULT_I_E_REG_RESETVAL (0x00000000u)

/* SC_MULT_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 sc_mult_imag_mnt : 23;
#else 
    Uint32 sc_mult_imag_mnt : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_SC_MULT_Q_REG;

/* Scalar Engine, Output of Multiplier, Imag Part */
#define CSL_DFE_DPDA_SC_MULT_Q_REG_SC_MULT_IMAG_MNT_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SC_MULT_Q_REG_SC_MULT_IMAG_MNT_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SC_MULT_Q_REG_SC_MULT_IMAG_MNT_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SC_MULT_Q_REG_ADDR (0x0000018Cu)
#define CSL_DFE_DPDA_SC_MULT_Q_REG_RESETVAL (0x00000000u)

/* SC_ACCUM_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 sc_accum_exp : 8;
    Uint32 rsvd0 : 1;
    Uint32 sc_accum_real_mnt : 23;
#else 
    Uint32 sc_accum_real_mnt : 23;
    Uint32 rsvd0 : 1;
    Uint32 sc_accum_exp : 8;
#endif 
} CSL_DFE_DPDA_SC_ACCUM_I_E_REG;

/* Scalar Engine, Output of Accumulator, Real Part */
#define CSL_DFE_DPDA_SC_ACCUM_I_E_REG_SC_ACCUM_REAL_MNT_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SC_ACCUM_I_E_REG_SC_ACCUM_REAL_MNT_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SC_ACCUM_I_E_REG_SC_ACCUM_REAL_MNT_RESETVAL (0x00000000u)

/* Scalar Engine, Output of Accumulator, Exponent */
#define CSL_DFE_DPDA_SC_ACCUM_I_E_REG_SC_ACCUM_EXP_MASK (0xFF000000u)
#define CSL_DFE_DPDA_SC_ACCUM_I_E_REG_SC_ACCUM_EXP_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_SC_ACCUM_I_E_REG_SC_ACCUM_EXP_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SC_ACCUM_I_E_REG_ADDR (0x00000190u)
#define CSL_DFE_DPDA_SC_ACCUM_I_E_REG_RESETVAL (0x00000000u)

/* SC_ACCUM_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 sc_accum_imag_mnt : 23;
#else 
    Uint32 sc_accum_imag_mnt : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_SC_ACCUM_Q_REG;

/* Scalar Engine, Output of Accumulator, Imag Part */
#define CSL_DFE_DPDA_SC_ACCUM_Q_REG_SC_ACCUM_IMAG_MNT_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SC_ACCUM_Q_REG_SC_ACCUM_IMAG_MNT_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SC_ACCUM_Q_REG_SC_ACCUM_IMAG_MNT_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SC_ACCUM_Q_REG_ADDR (0x00000194u)
#define CSL_DFE_DPDA_SC_ACCUM_Q_REG_RESETVAL (0x00000000u)

/* SC_MAG_I_E */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 sc_mag_exp : 8;
    Uint32 rsvd0 : 1;
    Uint32 sc_mag_real_mnt : 23;
#else 
    Uint32 sc_mag_real_mnt : 23;
    Uint32 rsvd0 : 1;
    Uint32 sc_mag_exp : 8;
#endif 
} CSL_DFE_DPDA_SC_MAG_I_E_REG;

/* Scalar, magnitude */
#define CSL_DFE_DPDA_SC_MAG_I_E_REG_SC_MAG_REAL_MNT_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_SC_MAG_I_E_REG_SC_MAG_REAL_MNT_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_SC_MAG_I_E_REG_SC_MAG_REAL_MNT_RESETVAL (0x00000000u)

/* Jacobian Generator Column 7 Exponent */
#define CSL_DFE_DPDA_SC_MAG_I_E_REG_SC_MAG_EXP_MASK (0xFF000000u)
#define CSL_DFE_DPDA_SC_MAG_I_E_REG_SC_MAG_EXP_SHIFT (0x00000018u)
#define CSL_DFE_DPDA_SC_MAG_I_E_REG_SC_MAG_EXP_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_SC_MAG_I_E_REG_ADDR (0x00000198u)
#define CSL_DFE_DPDA_SC_MAG_I_E_REG_RESETVAL (0x00000000u)

/* DBG_ADDR_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 14;
    Uint32 stack_depth : 6;
    Uint32 program_cnt : 12;
#else 
    Uint32 program_cnt : 12;
    Uint32 stack_depth : 6;
    Uint32 rsvd0 : 14;
#endif 
} CSL_DFE_DPDA_DBG_ADDR_0_REG;

/* Program cnt (address for the instruction memory) */
#define CSL_DFE_DPDA_DBG_ADDR_0_REG_PROGRAM_CNT_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DBG_ADDR_0_REG_PROGRAM_CNT_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DBG_ADDR_0_REG_PROGRAM_CNT_RESETVAL (0x00000000u)

/* Current stack_depth in the instruction generation stack */
#define CSL_DFE_DPDA_DBG_ADDR_0_REG_STACK_DEPTH_MASK (0x0003F000u)
#define CSL_DFE_DPDA_DBG_ADDR_0_REG_STACK_DEPTH_SHIFT (0x0000000Cu)
#define CSL_DFE_DPDA_DBG_ADDR_0_REG_STACK_DEPTH_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DBG_ADDR_0_REG_ADDR (0x0000019Cu)
#define CSL_DFE_DPDA_DBG_ADDR_0_REG_RESETVAL (0x00000000u)

/* DBG_ADDR_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 8;
    Uint32 preg_aw_vec : 12;
    Uint32 preg_ar_vec : 12;
#else 
    Uint32 preg_ar_vec : 12;
    Uint32 preg_aw_vec : 12;
    Uint32 rsvd0 : 8;
#endif 
} CSL_DFE_DPDA_DBG_ADDR_1_REG;

/* Current read address for the solution memory */
#define CSL_DFE_DPDA_DBG_ADDR_1_REG_PREG_AR_VEC_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DBG_ADDR_1_REG_PREG_AR_VEC_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DBG_ADDR_1_REG_PREG_AR_VEC_RESETVAL (0x00000000u)

/* Current write address for the solution memory */
#define CSL_DFE_DPDA_DBG_ADDR_1_REG_PREG_AW_VEC_MASK (0x00FFF000u)
#define CSL_DFE_DPDA_DBG_ADDR_1_REG_PREG_AW_VEC_SHIFT (0x0000000Cu)
#define CSL_DFE_DPDA_DBG_ADDR_1_REG_PREG_AW_VEC_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DBG_ADDR_1_REG_ADDR (0x000001A0u)
#define CSL_DFE_DPDA_DBG_ADDR_1_REG_RESETVAL (0x00000000u)

/* DPDA_SCALAR_IE_REGISTER */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_scalar_ie_register : 31;
#else 
    Uint32 dpda_scalar_ie_register : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_SCALAR_IE_REGISTER_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_SCALAR_IE_REGISTER_REG_DPDA_SCALAR_IE_REGISTER_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_SCALAR_IE_REGISTER_REG_DPDA_SCALAR_IE_REGISTER_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_SCALAR_IE_REGISTER_REG_DPDA_SCALAR_IE_REGISTER_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_SCALAR_IE_REGISTER_REG_ADDR (0x00000200u)
#define CSL_DFE_DPDA_DPDA_SCALAR_IE_REGISTER_REG_RESETVAL (0x00000000u)

/* DPDA_SCALAR_Q_REGISTER */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_scalar_q_register : 23;
#else 
    Uint32 dpda_scalar_q_register : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_SCALAR_Q_REGISTER_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_SCALAR_Q_REGISTER_REG_DPDA_SCALAR_Q_REGISTER_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_SCALAR_Q_REGISTER_REG_DPDA_SCALAR_Q_REGISTER_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_SCALAR_Q_REGISTER_REG_DPDA_SCALAR_Q_REGISTER_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_SCALAR_Q_REGISTER_REG_ADDR (0x00000204u)
#define CSL_DFE_DPDA_DPDA_SCALAR_Q_REGISTER_REG_RESETVAL (0x00000000u)

/* DPDA_IG_REGFILE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_ig_regfile : 12;
#else 
    Uint32 dpda_ig_regfile : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_IG_REGFILE_REG;

/* data[11:0] = {temporary_ig_register[11:0]} */
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_REG_DPDA_IG_REGFILE_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_REG_DPDA_IG_REGFILE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_REG_DPDA_IG_REGFILE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IG_REGFILE_REG_ADDR (0x00000400u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_REG_RESETVAL (0x00000000u)

/* DPDA_IG_REGFILE_PREG_RADD */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_ig_regfile_preg_radd : 12;
#else 
    Uint32 dpda_ig_regfile_preg_radd : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_RADD_REG;

/* data[11:0] = preg_radd */
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_RADD_REG_DPDA_IG_REGFILE_PREG_RADD_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_RADD_REG_DPDA_IG_REGFILE_PREG_RADD_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_RADD_REG_DPDA_IG_REGFILE_PREG_RADD_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_RADD_REG_ADDR (0x000004DCu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_RADD_REG_RESETVAL (0x00000000u)

/* DPDA_IG_REGFILE_PREG_WADD */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_ig_regfile_preg_wadd : 12;
#else 
    Uint32 dpda_ig_regfile_preg_wadd : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_WADD_REG;

/* data[11:0] = preg_wadd */
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_WADD_REG_DPDA_IG_REGFILE_PREG_WADD_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_WADD_REG_DPDA_IG_REGFILE_PREG_WADD_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_WADD_REG_DPDA_IG_REGFILE_PREG_WADD_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_WADD_REG_ADDR (0x000004E0u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_PREG_WADD_REG_RESETVAL (0x00000000u)

/* DPDA_IG_REGFILE_DSP_STATUS1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_ig_regfile_dsp_status1 : 12;
#else 
    Uint32 dpda_ig_regfile_dsp_status1 : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_STATUS1_REG;

/* data[11:0] = DSP_status1 */
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_STATUS1_REG_DPDA_IG_REGFILE_DSP_STATUS1_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_STATUS1_REG_DPDA_IG_REGFILE_DSP_STATUS1_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_STATUS1_REG_DPDA_IG_REGFILE_DSP_STATUS1_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_STATUS1_REG_ADDR (0x000004E8u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_STATUS1_REG_RESETVAL (0x00000000u)

/* DPDA_IG_REGFILE_IMMEDIATE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_ig_regfile_immediate : 12;
#else 
    Uint32 dpda_ig_regfile_immediate : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_IG_REGFILE_IMMEDIATE_REG;

/* data[11:0] = immediate */
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_IMMEDIATE_REG_DPDA_IG_REGFILE_IMMEDIATE_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_IMMEDIATE_REG_DPDA_IG_REGFILE_IMMEDIATE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_IMMEDIATE_REG_DPDA_IG_REGFILE_IMMEDIATE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IG_REGFILE_IMMEDIATE_REG_ADDR (0x000004ECu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_IMMEDIATE_REG_RESETVAL (0x00000000u)

/* DPDA_IG_REGFILE_CB_STATUS */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_ig_regfile_cb_status : 12;
#else 
    Uint32 dpda_ig_regfile_cb_status : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_IG_REGFILE_CB_STATUS_REG;

/* data[11:0] = cb_status */
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_CB_STATUS_REG_DPDA_IG_REGFILE_CB_STATUS_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_CB_STATUS_REG_DPDA_IG_REGFILE_CB_STATUS_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_CB_STATUS_REG_DPDA_IG_REGFILE_CB_STATUS_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IG_REGFILE_CB_STATUS_REG_ADDR (0x000004F0u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_CB_STATUS_REG_RESETVAL (0x00000000u)

/* DPDA_IG_REGFILE_MASK_ADAP */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_ig_regfile_mask_adap : 12;
#else 
    Uint32 dpda_ig_regfile_mask_adap : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_IG_REGFILE_MASK_ADAP_REG;

/* data[11:0] = mask_adap */
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_MASK_ADAP_REG_DPDA_IG_REGFILE_MASK_ADAP_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_MASK_ADAP_REG_DPDA_IG_REGFILE_MASK_ADAP_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_MASK_ADAP_REG_DPDA_IG_REGFILE_MASK_ADAP_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IG_REGFILE_MASK_ADAP_REG_ADDR (0x000004F4u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_MASK_ADAP_REG_RESETVAL (0x00000000u)

/* DPDA_IG_REGFILE_DSP_PARAM1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_ig_regfile_dsp_param1 : 12;
#else 
    Uint32 dpda_ig_regfile_dsp_param1 : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM1_REG;

/* data[11:0] = DSP_param1 */
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM1_REG_DPDA_IG_REGFILE_DSP_PARAM1_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM1_REG_DPDA_IG_REGFILE_DSP_PARAM1_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM1_REG_DPDA_IG_REGFILE_DSP_PARAM1_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM1_REG_ADDR (0x000004F8u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM1_REG_RESETVAL (0x00000000u)

/* DPDA_IG_REGFILE_DSP_PARAM2 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_ig_regfile_dsp_param2 : 12;
#else 
    Uint32 dpda_ig_regfile_dsp_param2 : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM2_REG;

/* data[11:0] = DSP_param2 */
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM2_REG_DPDA_IG_REGFILE_DSP_PARAM2_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM2_REG_DPDA_IG_REGFILE_DSP_PARAM2_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM2_REG_DPDA_IG_REGFILE_DSP_PARAM2_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM2_REG_ADDR (0x000004FCu)
#define CSL_DFE_DPDA_DPDA_IG_REGFILE_DSP_PARAM2_REG_RESETVAL (0x00000000u)

/* DPDA_INTO_DPD4_RAM0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 10;
    Uint32 dpda_into_dpd4_ram0 : 22;
#else 
    Uint32 dpda_into_dpd4_ram0 : 22;
    Uint32 rsvd0 : 10;
#endif 
} CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM0_REG;

/* data[21:0] = offset_real[21:0] for even addresses */
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM0_REG_DPDA_INTO_DPD4_RAM0_MASK (0x003FFFFFu)
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM0_REG_DPDA_INTO_DPD4_RAM0_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM0_REG_DPDA_INTO_DPD4_RAM0_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM0_REG_ADDR (0x00000800u)
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM0_REG_RESETVAL (0x00000000u)

/* DPDA_INTO_DPD4_RAM1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 10;
    Uint32 dpda_into_dpd4_ram1 : 22;
#else 
    Uint32 dpda_into_dpd4_ram1 : 22;
    Uint32 rsvd0 : 10;
#endif 
} CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM1_REG;

/* data[21:0] = offset_real[21:0] for even addresses */
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM1_REG_DPDA_INTO_DPD4_RAM1_MASK (0x003FFFFFu)
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM1_REG_DPDA_INTO_DPD4_RAM1_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM1_REG_DPDA_INTO_DPD4_RAM1_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM1_REG_ADDR (0x00000C00u)
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM1_REG_RESETVAL (0x00000000u)

/* DPDA_INTO_DPD4_RAM2 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 10;
    Uint32 dpda_into_dpd4_ram2 : 22;
#else 
    Uint32 dpda_into_dpd4_ram2 : 22;
    Uint32 rsvd0 : 10;
#endif 
} CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM2_REG;

/* data[21:0] = offset_real[21:0] for even addresses */
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM2_REG_DPDA_INTO_DPD4_RAM2_MASK (0x003FFFFFu)
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM2_REG_DPDA_INTO_DPD4_RAM2_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM2_REG_DPDA_INTO_DPD4_RAM2_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM2_REG_ADDR (0x00001000u)
#define CSL_DFE_DPDA_DPDA_INTO_DPD4_RAM2_REG_RESETVAL (0x00000000u)

/* DPDA_STACK */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 20;
    Uint32 dpda_stack : 12;
#else 
    Uint32 dpda_stack : 12;
    Uint32 rsvd0 : 20;
#endif 
} CSL_DFE_DPDA_DPDA_STACK_REG;

/* data[11:0] = pointer within the preg memory. */
#define CSL_DFE_DPDA_DPDA_STACK_REG_DPDA_STACK_MASK (0x00000FFFu)
#define CSL_DFE_DPDA_DPDA_STACK_REG_DPDA_STACK_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_STACK_REG_DPDA_STACK_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_STACK_REG_ADDR (0x00001400u)
#define CSL_DFE_DPDA_DPDA_STACK_REG_RESETVAL (0x00000000u)

/* DPDA_LUT_MASTER */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_lut_master : 32;
#else 
    Uint32 dpda_lut_master : 32;
#endif 
} CSL_DFE_DPDA_DPDA_LUT_MASTER_REG;

/* data[31:0] = {slope_i[12:0], gain_i[18:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_LUT_MASTER_REG_DPDA_LUT_MASTER_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_LUT_MASTER_REG_DPDA_LUT_MASTER_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_LUT_MASTER_REG_DPDA_LUT_MASTER_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_LUT_MASTER_REG_ADDR (0x00004000u)
#define CSL_DFE_DPDA_DPDA_LUT_MASTER_REG_RESETVAL (0x00000000u)

/* DPDA_LUT_0 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_lut_0 : 32;
#else 
    Uint32 dpda_lut_0 : 32;
#endif 
} CSL_DFE_DPDA_DPDA_LUT_0_REG;

/* same as above */
#define CSL_DFE_DPDA_DPDA_LUT_0_REG_DPDA_LUT_0_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_LUT_0_REG_DPDA_LUT_0_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_LUT_0_REG_DPDA_LUT_0_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_LUT_0_REG_ADDR (0x00008000u)
#define CSL_DFE_DPDA_DPDA_LUT_0_REG_RESETVAL (0x00000000u)

/* DPDA_LUT_1 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_lut_1 : 32;
#else 
    Uint32 dpda_lut_1 : 32;
#endif 
} CSL_DFE_DPDA_DPDA_LUT_1_REG;

/* same as above */
#define CSL_DFE_DPDA_DPDA_LUT_1_REG_DPDA_LUT_1_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_LUT_1_REG_DPDA_LUT_1_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_LUT_1_REG_DPDA_LUT_1_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_LUT_1_REG_ADDR (0x00009000u)
#define CSL_DFE_DPDA_DPDA_LUT_1_REG_RESETVAL (0x00000000u)

/* DPDA_LUT_2 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_lut_2 : 32;
#else 
    Uint32 dpda_lut_2 : 32;
#endif 
} CSL_DFE_DPDA_DPDA_LUT_2_REG;

/* same as above */
#define CSL_DFE_DPDA_DPDA_LUT_2_REG_DPDA_LUT_2_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_LUT_2_REG_DPDA_LUT_2_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_LUT_2_REG_DPDA_LUT_2_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_LUT_2_REG_ADDR (0x0000A000u)
#define CSL_DFE_DPDA_DPDA_LUT_2_REG_RESETVAL (0x00000000u)

/* DPDA_LUT_3 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_lut_3 : 32;
#else 
    Uint32 dpda_lut_3 : 32;
#endif 
} CSL_DFE_DPDA_DPDA_LUT_3_REG;

/* same as above */
#define CSL_DFE_DPDA_DPDA_LUT_3_REG_DPDA_LUT_3_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_LUT_3_REG_DPDA_LUT_3_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_LUT_3_REG_DPDA_LUT_3_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_LUT_3_REG_ADDR (0x0000B000u)
#define CSL_DFE_DPDA_DPDA_LUT_3_REG_RESETVAL (0x00000000u)

/* DPDA_LUT_4 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_lut_4 : 32;
#else 
    Uint32 dpda_lut_4 : 32;
#endif 
} CSL_DFE_DPDA_DPDA_LUT_4_REG;

/* same as above */
#define CSL_DFE_DPDA_DPDA_LUT_4_REG_DPDA_LUT_4_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_LUT_4_REG_DPDA_LUT_4_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_LUT_4_REG_DPDA_LUT_4_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_LUT_4_REG_ADDR (0x0000C000u)
#define CSL_DFE_DPDA_DPDA_LUT_4_REG_RESETVAL (0x00000000u)

/* DPDA_LUT_5 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_lut_5 : 32;
#else 
    Uint32 dpda_lut_5 : 32;
#endif 
} CSL_DFE_DPDA_DPDA_LUT_5_REG;

/* same as above */
#define CSL_DFE_DPDA_DPDA_LUT_5_REG_DPDA_LUT_5_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_LUT_5_REG_DPDA_LUT_5_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_LUT_5_REG_DPDA_LUT_5_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_LUT_5_REG_ADDR (0x0000D000u)
#define CSL_DFE_DPDA_DPDA_LUT_5_REG_RESETVAL (0x00000000u)

/* DPDA_LUT_6 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_lut_6 : 32;
#else 
    Uint32 dpda_lut_6 : 32;
#endif 
} CSL_DFE_DPDA_DPDA_LUT_6_REG;

/* same as above */
#define CSL_DFE_DPDA_DPDA_LUT_6_REG_DPDA_LUT_6_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_LUT_6_REG_DPDA_LUT_6_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_LUT_6_REG_DPDA_LUT_6_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_LUT_6_REG_ADDR (0x0000E000u)
#define CSL_DFE_DPDA_DPDA_LUT_6_REG_RESETVAL (0x00000000u)

/* DPDA_LUT_7 */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_lut_7 : 32;
#else 
    Uint32 dpda_lut_7 : 32;
#endif 
} CSL_DFE_DPDA_DPDA_LUT_7_REG;

/* same as above */
#define CSL_DFE_DPDA_DPDA_LUT_7_REG_DPDA_LUT_7_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_LUT_7_REG_DPDA_LUT_7_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_LUT_7_REG_DPDA_LUT_7_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_LUT_7_REG_ADDR (0x0000F000u)
#define CSL_DFE_DPDA_DPDA_LUT_7_REG_RESETVAL (0x00000000u)

/* DPDA_IRAM */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 dpda_iram : 32;
#else 
    Uint32 dpda_iram : 32;
#endif 
} CSL_DFE_DPDA_DPDA_IRAM_REG;

/* data[31:0] = instruction[31:0] for even addresses */
#define CSL_DFE_DPDA_DPDA_IRAM_REG_DPDA_IRAM_MASK (0xFFFFFFFFu)
#define CSL_DFE_DPDA_DPDA_IRAM_REG_DPDA_IRAM_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_IRAM_REG_DPDA_IRAM_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_IRAM_REG_ADDR (0x00010000u)
#define CSL_DFE_DPDA_DPDA_IRAM_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_000_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_000_ie : 31;
#else 
    Uint32 dpda_preg_000_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_000_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_000_IE_REG_DPDA_PREG_000_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_000_IE_REG_DPDA_PREG_000_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_000_IE_REG_DPDA_PREG_000_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_000_IE_REG_ADDR (0x00040000u)
#define CSL_DFE_DPDA_DPDA_PREG_000_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_000_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_000_q : 23;
#else 
    Uint32 dpda_preg_000_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_000_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_000_Q_REG_DPDA_PREG_000_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_000_Q_REG_DPDA_PREG_000_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_000_Q_REG_DPDA_PREG_000_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_000_Q_REG_ADDR (0x00040004u)
#define CSL_DFE_DPDA_DPDA_PREG_000_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_001_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_001_ie : 31;
#else 
    Uint32 dpda_preg_001_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_001_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_001_IE_REG_DPDA_PREG_001_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_001_IE_REG_DPDA_PREG_001_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_001_IE_REG_DPDA_PREG_001_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_001_IE_REG_ADDR (0x00040100u)
#define CSL_DFE_DPDA_DPDA_PREG_001_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_001_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_001_q : 23;
#else 
    Uint32 dpda_preg_001_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_001_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_001_Q_REG_DPDA_PREG_001_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_001_Q_REG_DPDA_PREG_001_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_001_Q_REG_DPDA_PREG_001_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_001_Q_REG_ADDR (0x00040104u)
#define CSL_DFE_DPDA_DPDA_PREG_001_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_002_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_002_ie : 31;
#else 
    Uint32 dpda_preg_002_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_002_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_002_IE_REG_DPDA_PREG_002_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_002_IE_REG_DPDA_PREG_002_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_002_IE_REG_DPDA_PREG_002_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_002_IE_REG_ADDR (0x00040200u)
#define CSL_DFE_DPDA_DPDA_PREG_002_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_002_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_002_q : 23;
#else 
    Uint32 dpda_preg_002_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_002_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_002_Q_REG_DPDA_PREG_002_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_002_Q_REG_DPDA_PREG_002_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_002_Q_REG_DPDA_PREG_002_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_002_Q_REG_ADDR (0x00040204u)
#define CSL_DFE_DPDA_DPDA_PREG_002_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_003_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_003_ie : 31;
#else 
    Uint32 dpda_preg_003_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_003_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_003_IE_REG_DPDA_PREG_003_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_003_IE_REG_DPDA_PREG_003_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_003_IE_REG_DPDA_PREG_003_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_003_IE_REG_ADDR (0x00040300u)
#define CSL_DFE_DPDA_DPDA_PREG_003_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_003_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_003_q : 23;
#else 
    Uint32 dpda_preg_003_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_003_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_003_Q_REG_DPDA_PREG_003_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_003_Q_REG_DPDA_PREG_003_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_003_Q_REG_DPDA_PREG_003_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_003_Q_REG_ADDR (0x00040304u)
#define CSL_DFE_DPDA_DPDA_PREG_003_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_004_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_004_ie : 31;
#else 
    Uint32 dpda_preg_004_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_004_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_004_IE_REG_DPDA_PREG_004_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_004_IE_REG_DPDA_PREG_004_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_004_IE_REG_DPDA_PREG_004_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_004_IE_REG_ADDR (0x00040400u)
#define CSL_DFE_DPDA_DPDA_PREG_004_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_004_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_004_q : 23;
#else 
    Uint32 dpda_preg_004_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_004_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_004_Q_REG_DPDA_PREG_004_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_004_Q_REG_DPDA_PREG_004_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_004_Q_REG_DPDA_PREG_004_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_004_Q_REG_ADDR (0x00040404u)
#define CSL_DFE_DPDA_DPDA_PREG_004_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_005_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_005_ie : 31;
#else 
    Uint32 dpda_preg_005_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_005_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_005_IE_REG_DPDA_PREG_005_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_005_IE_REG_DPDA_PREG_005_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_005_IE_REG_DPDA_PREG_005_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_005_IE_REG_ADDR (0x00040500u)
#define CSL_DFE_DPDA_DPDA_PREG_005_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_005_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_005_q : 23;
#else 
    Uint32 dpda_preg_005_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_005_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_005_Q_REG_DPDA_PREG_005_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_005_Q_REG_DPDA_PREG_005_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_005_Q_REG_DPDA_PREG_005_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_005_Q_REG_ADDR (0x00040504u)
#define CSL_DFE_DPDA_DPDA_PREG_005_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_006_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_006_ie : 31;
#else 
    Uint32 dpda_preg_006_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_006_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_006_IE_REG_DPDA_PREG_006_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_006_IE_REG_DPDA_PREG_006_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_006_IE_REG_DPDA_PREG_006_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_006_IE_REG_ADDR (0x00040600u)
#define CSL_DFE_DPDA_DPDA_PREG_006_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_006_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_006_q : 23;
#else 
    Uint32 dpda_preg_006_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_006_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_006_Q_REG_DPDA_PREG_006_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_006_Q_REG_DPDA_PREG_006_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_006_Q_REG_DPDA_PREG_006_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_006_Q_REG_ADDR (0x00040604u)
#define CSL_DFE_DPDA_DPDA_PREG_006_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_007_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_007_ie : 31;
#else 
    Uint32 dpda_preg_007_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_007_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_007_IE_REG_DPDA_PREG_007_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_007_IE_REG_DPDA_PREG_007_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_007_IE_REG_DPDA_PREG_007_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_007_IE_REG_ADDR (0x00040700u)
#define CSL_DFE_DPDA_DPDA_PREG_007_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_007_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_007_q : 23;
#else 
    Uint32 dpda_preg_007_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_007_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_007_Q_REG_DPDA_PREG_007_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_007_Q_REG_DPDA_PREG_007_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_007_Q_REG_DPDA_PREG_007_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_007_Q_REG_ADDR (0x00040704u)
#define CSL_DFE_DPDA_DPDA_PREG_007_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_008_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_008_ie : 31;
#else 
    Uint32 dpda_preg_008_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_008_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_008_IE_REG_DPDA_PREG_008_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_008_IE_REG_DPDA_PREG_008_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_008_IE_REG_DPDA_PREG_008_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_008_IE_REG_ADDR (0x00040800u)
#define CSL_DFE_DPDA_DPDA_PREG_008_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_008_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_008_q : 23;
#else 
    Uint32 dpda_preg_008_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_008_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_008_Q_REG_DPDA_PREG_008_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_008_Q_REG_DPDA_PREG_008_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_008_Q_REG_DPDA_PREG_008_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_008_Q_REG_ADDR (0x00040804u)
#define CSL_DFE_DPDA_DPDA_PREG_008_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_009_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_009_ie : 31;
#else 
    Uint32 dpda_preg_009_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_009_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_009_IE_REG_DPDA_PREG_009_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_009_IE_REG_DPDA_PREG_009_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_009_IE_REG_DPDA_PREG_009_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_009_IE_REG_ADDR (0x00040900u)
#define CSL_DFE_DPDA_DPDA_PREG_009_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_009_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_009_q : 23;
#else 
    Uint32 dpda_preg_009_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_009_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_009_Q_REG_DPDA_PREG_009_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_009_Q_REG_DPDA_PREG_009_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_009_Q_REG_DPDA_PREG_009_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_009_Q_REG_ADDR (0x00040904u)
#define CSL_DFE_DPDA_DPDA_PREG_009_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_010_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_010_ie : 31;
#else 
    Uint32 dpda_preg_010_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_010_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_010_IE_REG_DPDA_PREG_010_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_010_IE_REG_DPDA_PREG_010_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_010_IE_REG_DPDA_PREG_010_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_010_IE_REG_ADDR (0x00040A00u)
#define CSL_DFE_DPDA_DPDA_PREG_010_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_010_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_010_q : 23;
#else 
    Uint32 dpda_preg_010_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_010_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_010_Q_REG_DPDA_PREG_010_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_010_Q_REG_DPDA_PREG_010_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_010_Q_REG_DPDA_PREG_010_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_010_Q_REG_ADDR (0x00040A04u)
#define CSL_DFE_DPDA_DPDA_PREG_010_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_011_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_011_ie : 31;
#else 
    Uint32 dpda_preg_011_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_011_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_011_IE_REG_DPDA_PREG_011_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_011_IE_REG_DPDA_PREG_011_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_011_IE_REG_DPDA_PREG_011_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_011_IE_REG_ADDR (0x00040B00u)
#define CSL_DFE_DPDA_DPDA_PREG_011_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_011_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_011_q : 23;
#else 
    Uint32 dpda_preg_011_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_011_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_011_Q_REG_DPDA_PREG_011_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_011_Q_REG_DPDA_PREG_011_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_011_Q_REG_DPDA_PREG_011_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_011_Q_REG_ADDR (0x00040B04u)
#define CSL_DFE_DPDA_DPDA_PREG_011_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_012_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_012_ie : 31;
#else 
    Uint32 dpda_preg_012_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_012_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_012_IE_REG_DPDA_PREG_012_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_012_IE_REG_DPDA_PREG_012_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_012_IE_REG_DPDA_PREG_012_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_012_IE_REG_ADDR (0x00040C00u)
#define CSL_DFE_DPDA_DPDA_PREG_012_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_012_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_012_q : 23;
#else 
    Uint32 dpda_preg_012_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_012_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_012_Q_REG_DPDA_PREG_012_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_012_Q_REG_DPDA_PREG_012_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_012_Q_REG_DPDA_PREG_012_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_012_Q_REG_ADDR (0x00040C04u)
#define CSL_DFE_DPDA_DPDA_PREG_012_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_013_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_013_ie : 31;
#else 
    Uint32 dpda_preg_013_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_013_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_013_IE_REG_DPDA_PREG_013_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_013_IE_REG_DPDA_PREG_013_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_013_IE_REG_DPDA_PREG_013_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_013_IE_REG_ADDR (0x00040D00u)
#define CSL_DFE_DPDA_DPDA_PREG_013_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_013_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_013_q : 23;
#else 
    Uint32 dpda_preg_013_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_013_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_013_Q_REG_DPDA_PREG_013_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_013_Q_REG_DPDA_PREG_013_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_013_Q_REG_DPDA_PREG_013_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_013_Q_REG_ADDR (0x00040D04u)
#define CSL_DFE_DPDA_DPDA_PREG_013_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_014_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_014_ie : 31;
#else 
    Uint32 dpda_preg_014_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_014_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_014_IE_REG_DPDA_PREG_014_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_014_IE_REG_DPDA_PREG_014_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_014_IE_REG_DPDA_PREG_014_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_014_IE_REG_ADDR (0x00040E00u)
#define CSL_DFE_DPDA_DPDA_PREG_014_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_014_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_014_q : 23;
#else 
    Uint32 dpda_preg_014_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_014_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_014_Q_REG_DPDA_PREG_014_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_014_Q_REG_DPDA_PREG_014_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_014_Q_REG_DPDA_PREG_014_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_014_Q_REG_ADDR (0x00040E04u)
#define CSL_DFE_DPDA_DPDA_PREG_014_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_015_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_015_ie : 31;
#else 
    Uint32 dpda_preg_015_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_015_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_015_IE_REG_DPDA_PREG_015_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_015_IE_REG_DPDA_PREG_015_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_015_IE_REG_DPDA_PREG_015_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_015_IE_REG_ADDR (0x00040F00u)
#define CSL_DFE_DPDA_DPDA_PREG_015_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_015_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_015_q : 23;
#else 
    Uint32 dpda_preg_015_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_015_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_015_Q_REG_DPDA_PREG_015_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_015_Q_REG_DPDA_PREG_015_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_015_Q_REG_DPDA_PREG_015_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_015_Q_REG_ADDR (0x00040F04u)
#define CSL_DFE_DPDA_DPDA_PREG_015_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_016_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_016_ie : 31;
#else 
    Uint32 dpda_preg_016_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_016_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_016_IE_REG_DPDA_PREG_016_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_016_IE_REG_DPDA_PREG_016_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_016_IE_REG_DPDA_PREG_016_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_016_IE_REG_ADDR (0x00041000u)
#define CSL_DFE_DPDA_DPDA_PREG_016_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_016_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_016_q : 23;
#else 
    Uint32 dpda_preg_016_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_016_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_016_Q_REG_DPDA_PREG_016_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_016_Q_REG_DPDA_PREG_016_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_016_Q_REG_DPDA_PREG_016_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_016_Q_REG_ADDR (0x00041004u)
#define CSL_DFE_DPDA_DPDA_PREG_016_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_017_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_017_ie : 31;
#else 
    Uint32 dpda_preg_017_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_017_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_017_IE_REG_DPDA_PREG_017_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_017_IE_REG_DPDA_PREG_017_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_017_IE_REG_DPDA_PREG_017_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_017_IE_REG_ADDR (0x00041100u)
#define CSL_DFE_DPDA_DPDA_PREG_017_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_017_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_017_q : 23;
#else 
    Uint32 dpda_preg_017_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_017_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_017_Q_REG_DPDA_PREG_017_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_017_Q_REG_DPDA_PREG_017_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_017_Q_REG_DPDA_PREG_017_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_017_Q_REG_ADDR (0x00041104u)
#define CSL_DFE_DPDA_DPDA_PREG_017_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_018_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_018_ie : 31;
#else 
    Uint32 dpda_preg_018_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_018_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_018_IE_REG_DPDA_PREG_018_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_018_IE_REG_DPDA_PREG_018_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_018_IE_REG_DPDA_PREG_018_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_018_IE_REG_ADDR (0x00041200u)
#define CSL_DFE_DPDA_DPDA_PREG_018_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_018_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_018_q : 23;
#else 
    Uint32 dpda_preg_018_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_018_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_018_Q_REG_DPDA_PREG_018_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_018_Q_REG_DPDA_PREG_018_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_018_Q_REG_DPDA_PREG_018_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_018_Q_REG_ADDR (0x00041204u)
#define CSL_DFE_DPDA_DPDA_PREG_018_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_019_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_019_ie : 31;
#else 
    Uint32 dpda_preg_019_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_019_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_019_IE_REG_DPDA_PREG_019_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_019_IE_REG_DPDA_PREG_019_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_019_IE_REG_DPDA_PREG_019_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_019_IE_REG_ADDR (0x00041300u)
#define CSL_DFE_DPDA_DPDA_PREG_019_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_019_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_019_q : 23;
#else 
    Uint32 dpda_preg_019_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_019_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_019_Q_REG_DPDA_PREG_019_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_019_Q_REG_DPDA_PREG_019_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_019_Q_REG_DPDA_PREG_019_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_019_Q_REG_ADDR (0x00041304u)
#define CSL_DFE_DPDA_DPDA_PREG_019_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_020_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_020_ie : 31;
#else 
    Uint32 dpda_preg_020_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_020_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_020_IE_REG_DPDA_PREG_020_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_020_IE_REG_DPDA_PREG_020_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_020_IE_REG_DPDA_PREG_020_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_020_IE_REG_ADDR (0x00041400u)
#define CSL_DFE_DPDA_DPDA_PREG_020_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_020_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_020_q : 23;
#else 
    Uint32 dpda_preg_020_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_020_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_020_Q_REG_DPDA_PREG_020_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_020_Q_REG_DPDA_PREG_020_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_020_Q_REG_DPDA_PREG_020_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_020_Q_REG_ADDR (0x00041404u)
#define CSL_DFE_DPDA_DPDA_PREG_020_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_021_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_021_ie : 31;
#else 
    Uint32 dpda_preg_021_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_021_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_021_IE_REG_DPDA_PREG_021_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_021_IE_REG_DPDA_PREG_021_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_021_IE_REG_DPDA_PREG_021_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_021_IE_REG_ADDR (0x00041500u)
#define CSL_DFE_DPDA_DPDA_PREG_021_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_021_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_021_q : 23;
#else 
    Uint32 dpda_preg_021_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_021_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_021_Q_REG_DPDA_PREG_021_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_021_Q_REG_DPDA_PREG_021_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_021_Q_REG_DPDA_PREG_021_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_021_Q_REG_ADDR (0x00041504u)
#define CSL_DFE_DPDA_DPDA_PREG_021_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_022_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_022_ie : 31;
#else 
    Uint32 dpda_preg_022_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_022_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_022_IE_REG_DPDA_PREG_022_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_022_IE_REG_DPDA_PREG_022_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_022_IE_REG_DPDA_PREG_022_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_022_IE_REG_ADDR (0x00041600u)
#define CSL_DFE_DPDA_DPDA_PREG_022_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_022_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_022_q : 23;
#else 
    Uint32 dpda_preg_022_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_022_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_022_Q_REG_DPDA_PREG_022_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_022_Q_REG_DPDA_PREG_022_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_022_Q_REG_DPDA_PREG_022_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_022_Q_REG_ADDR (0x00041604u)
#define CSL_DFE_DPDA_DPDA_PREG_022_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_023_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_023_ie : 31;
#else 
    Uint32 dpda_preg_023_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_023_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_023_IE_REG_DPDA_PREG_023_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_023_IE_REG_DPDA_PREG_023_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_023_IE_REG_DPDA_PREG_023_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_023_IE_REG_ADDR (0x00041700u)
#define CSL_DFE_DPDA_DPDA_PREG_023_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_023_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_023_q : 23;
#else 
    Uint32 dpda_preg_023_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_023_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_023_Q_REG_DPDA_PREG_023_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_023_Q_REG_DPDA_PREG_023_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_023_Q_REG_DPDA_PREG_023_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_023_Q_REG_ADDR (0x00041704u)
#define CSL_DFE_DPDA_DPDA_PREG_023_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_024_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_024_ie : 31;
#else 
    Uint32 dpda_preg_024_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_024_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_024_IE_REG_DPDA_PREG_024_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_024_IE_REG_DPDA_PREG_024_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_024_IE_REG_DPDA_PREG_024_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_024_IE_REG_ADDR (0x00041800u)
#define CSL_DFE_DPDA_DPDA_PREG_024_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_024_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_024_q : 23;
#else 
    Uint32 dpda_preg_024_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_024_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_024_Q_REG_DPDA_PREG_024_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_024_Q_REG_DPDA_PREG_024_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_024_Q_REG_DPDA_PREG_024_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_024_Q_REG_ADDR (0x00041804u)
#define CSL_DFE_DPDA_DPDA_PREG_024_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_025_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_025_ie : 31;
#else 
    Uint32 dpda_preg_025_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_025_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_025_IE_REG_DPDA_PREG_025_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_025_IE_REG_DPDA_PREG_025_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_025_IE_REG_DPDA_PREG_025_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_025_IE_REG_ADDR (0x00041900u)
#define CSL_DFE_DPDA_DPDA_PREG_025_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_025_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_025_q : 23;
#else 
    Uint32 dpda_preg_025_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_025_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_025_Q_REG_DPDA_PREG_025_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_025_Q_REG_DPDA_PREG_025_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_025_Q_REG_DPDA_PREG_025_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_025_Q_REG_ADDR (0x00041904u)
#define CSL_DFE_DPDA_DPDA_PREG_025_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_026_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_026_ie : 31;
#else 
    Uint32 dpda_preg_026_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_026_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_026_IE_REG_DPDA_PREG_026_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_026_IE_REG_DPDA_PREG_026_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_026_IE_REG_DPDA_PREG_026_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_026_IE_REG_ADDR (0x00041A00u)
#define CSL_DFE_DPDA_DPDA_PREG_026_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_026_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_026_q : 23;
#else 
    Uint32 dpda_preg_026_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_026_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_026_Q_REG_DPDA_PREG_026_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_026_Q_REG_DPDA_PREG_026_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_026_Q_REG_DPDA_PREG_026_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_026_Q_REG_ADDR (0x00041A04u)
#define CSL_DFE_DPDA_DPDA_PREG_026_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_027_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_027_ie : 31;
#else 
    Uint32 dpda_preg_027_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_027_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_027_IE_REG_DPDA_PREG_027_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_027_IE_REG_DPDA_PREG_027_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_027_IE_REG_DPDA_PREG_027_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_027_IE_REG_ADDR (0x00041B00u)
#define CSL_DFE_DPDA_DPDA_PREG_027_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_027_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_027_q : 23;
#else 
    Uint32 dpda_preg_027_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_027_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_027_Q_REG_DPDA_PREG_027_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_027_Q_REG_DPDA_PREG_027_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_027_Q_REG_DPDA_PREG_027_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_027_Q_REG_ADDR (0x00041B04u)
#define CSL_DFE_DPDA_DPDA_PREG_027_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_028_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_028_ie : 31;
#else 
    Uint32 dpda_preg_028_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_028_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_028_IE_REG_DPDA_PREG_028_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_028_IE_REG_DPDA_PREG_028_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_028_IE_REG_DPDA_PREG_028_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_028_IE_REG_ADDR (0x00041C00u)
#define CSL_DFE_DPDA_DPDA_PREG_028_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_028_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_028_q : 23;
#else 
    Uint32 dpda_preg_028_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_028_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_028_Q_REG_DPDA_PREG_028_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_028_Q_REG_DPDA_PREG_028_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_028_Q_REG_DPDA_PREG_028_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_028_Q_REG_ADDR (0x00041C04u)
#define CSL_DFE_DPDA_DPDA_PREG_028_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_029_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_029_ie : 31;
#else 
    Uint32 dpda_preg_029_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_029_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_029_IE_REG_DPDA_PREG_029_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_029_IE_REG_DPDA_PREG_029_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_029_IE_REG_DPDA_PREG_029_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_029_IE_REG_ADDR (0x00041D00u)
#define CSL_DFE_DPDA_DPDA_PREG_029_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_029_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_029_q : 23;
#else 
    Uint32 dpda_preg_029_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_029_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_029_Q_REG_DPDA_PREG_029_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_029_Q_REG_DPDA_PREG_029_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_029_Q_REG_DPDA_PREG_029_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_029_Q_REG_ADDR (0x00041D04u)
#define CSL_DFE_DPDA_DPDA_PREG_029_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_030_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_030_ie : 31;
#else 
    Uint32 dpda_preg_030_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_030_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_030_IE_REG_DPDA_PREG_030_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_030_IE_REG_DPDA_PREG_030_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_030_IE_REG_DPDA_PREG_030_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_030_IE_REG_ADDR (0x00041E00u)
#define CSL_DFE_DPDA_DPDA_PREG_030_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_030_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_030_q : 23;
#else 
    Uint32 dpda_preg_030_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_030_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_030_Q_REG_DPDA_PREG_030_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_030_Q_REG_DPDA_PREG_030_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_030_Q_REG_DPDA_PREG_030_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_030_Q_REG_ADDR (0x00041E04u)
#define CSL_DFE_DPDA_DPDA_PREG_030_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_031_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_031_ie : 31;
#else 
    Uint32 dpda_preg_031_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_031_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_031_IE_REG_DPDA_PREG_031_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_031_IE_REG_DPDA_PREG_031_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_031_IE_REG_DPDA_PREG_031_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_031_IE_REG_ADDR (0x00041F00u)
#define CSL_DFE_DPDA_DPDA_PREG_031_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_031_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_031_q : 23;
#else 
    Uint32 dpda_preg_031_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_031_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_031_Q_REG_DPDA_PREG_031_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_031_Q_REG_DPDA_PREG_031_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_031_Q_REG_DPDA_PREG_031_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_031_Q_REG_ADDR (0x00041F04u)
#define CSL_DFE_DPDA_DPDA_PREG_031_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_032_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_032_ie : 31;
#else 
    Uint32 dpda_preg_032_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_032_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_032_IE_REG_DPDA_PREG_032_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_032_IE_REG_DPDA_PREG_032_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_032_IE_REG_DPDA_PREG_032_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_032_IE_REG_ADDR (0x00042000u)
#define CSL_DFE_DPDA_DPDA_PREG_032_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_032_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_032_q : 23;
#else 
    Uint32 dpda_preg_032_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_032_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_032_Q_REG_DPDA_PREG_032_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_032_Q_REG_DPDA_PREG_032_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_032_Q_REG_DPDA_PREG_032_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_032_Q_REG_ADDR (0x00042004u)
#define CSL_DFE_DPDA_DPDA_PREG_032_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_033_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_033_ie : 31;
#else 
    Uint32 dpda_preg_033_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_033_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_033_IE_REG_DPDA_PREG_033_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_033_IE_REG_DPDA_PREG_033_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_033_IE_REG_DPDA_PREG_033_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_033_IE_REG_ADDR (0x00042100u)
#define CSL_DFE_DPDA_DPDA_PREG_033_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_033_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_033_q : 23;
#else 
    Uint32 dpda_preg_033_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_033_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_033_Q_REG_DPDA_PREG_033_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_033_Q_REG_DPDA_PREG_033_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_033_Q_REG_DPDA_PREG_033_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_033_Q_REG_ADDR (0x00042104u)
#define CSL_DFE_DPDA_DPDA_PREG_033_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_034_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_034_ie : 31;
#else 
    Uint32 dpda_preg_034_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_034_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_034_IE_REG_DPDA_PREG_034_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_034_IE_REG_DPDA_PREG_034_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_034_IE_REG_DPDA_PREG_034_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_034_IE_REG_ADDR (0x00042200u)
#define CSL_DFE_DPDA_DPDA_PREG_034_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_034_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_034_q : 23;
#else 
    Uint32 dpda_preg_034_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_034_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_034_Q_REG_DPDA_PREG_034_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_034_Q_REG_DPDA_PREG_034_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_034_Q_REG_DPDA_PREG_034_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_034_Q_REG_ADDR (0x00042204u)
#define CSL_DFE_DPDA_DPDA_PREG_034_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_035_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_035_ie : 31;
#else 
    Uint32 dpda_preg_035_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_035_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_035_IE_REG_DPDA_PREG_035_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_035_IE_REG_DPDA_PREG_035_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_035_IE_REG_DPDA_PREG_035_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_035_IE_REG_ADDR (0x00042300u)
#define CSL_DFE_DPDA_DPDA_PREG_035_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_035_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_035_q : 23;
#else 
    Uint32 dpda_preg_035_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_035_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_035_Q_REG_DPDA_PREG_035_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_035_Q_REG_DPDA_PREG_035_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_035_Q_REG_DPDA_PREG_035_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_035_Q_REG_ADDR (0x00042304u)
#define CSL_DFE_DPDA_DPDA_PREG_035_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_036_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_036_ie : 31;
#else 
    Uint32 dpda_preg_036_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_036_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_036_IE_REG_DPDA_PREG_036_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_036_IE_REG_DPDA_PREG_036_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_036_IE_REG_DPDA_PREG_036_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_036_IE_REG_ADDR (0x00042400u)
#define CSL_DFE_DPDA_DPDA_PREG_036_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_036_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_036_q : 23;
#else 
    Uint32 dpda_preg_036_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_036_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_036_Q_REG_DPDA_PREG_036_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_036_Q_REG_DPDA_PREG_036_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_036_Q_REG_DPDA_PREG_036_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_036_Q_REG_ADDR (0x00042404u)
#define CSL_DFE_DPDA_DPDA_PREG_036_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_037_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_037_ie : 31;
#else 
    Uint32 dpda_preg_037_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_037_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_037_IE_REG_DPDA_PREG_037_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_037_IE_REG_DPDA_PREG_037_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_037_IE_REG_DPDA_PREG_037_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_037_IE_REG_ADDR (0x00042500u)
#define CSL_DFE_DPDA_DPDA_PREG_037_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_037_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_037_q : 23;
#else 
    Uint32 dpda_preg_037_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_037_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_037_Q_REG_DPDA_PREG_037_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_037_Q_REG_DPDA_PREG_037_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_037_Q_REG_DPDA_PREG_037_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_037_Q_REG_ADDR (0x00042504u)
#define CSL_DFE_DPDA_DPDA_PREG_037_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_038_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_038_ie : 31;
#else 
    Uint32 dpda_preg_038_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_038_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_038_IE_REG_DPDA_PREG_038_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_038_IE_REG_DPDA_PREG_038_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_038_IE_REG_DPDA_PREG_038_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_038_IE_REG_ADDR (0x00042600u)
#define CSL_DFE_DPDA_DPDA_PREG_038_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_038_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_038_q : 23;
#else 
    Uint32 dpda_preg_038_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_038_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_038_Q_REG_DPDA_PREG_038_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_038_Q_REG_DPDA_PREG_038_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_038_Q_REG_DPDA_PREG_038_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_038_Q_REG_ADDR (0x00042604u)
#define CSL_DFE_DPDA_DPDA_PREG_038_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_039_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_039_ie : 31;
#else 
    Uint32 dpda_preg_039_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_039_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_039_IE_REG_DPDA_PREG_039_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_039_IE_REG_DPDA_PREG_039_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_039_IE_REG_DPDA_PREG_039_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_039_IE_REG_ADDR (0x00042700u)
#define CSL_DFE_DPDA_DPDA_PREG_039_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_039_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_039_q : 23;
#else 
    Uint32 dpda_preg_039_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_039_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_039_Q_REG_DPDA_PREG_039_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_039_Q_REG_DPDA_PREG_039_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_039_Q_REG_DPDA_PREG_039_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_039_Q_REG_ADDR (0x00042704u)
#define CSL_DFE_DPDA_DPDA_PREG_039_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_040_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_040_ie : 31;
#else 
    Uint32 dpda_preg_040_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_040_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_040_IE_REG_DPDA_PREG_040_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_040_IE_REG_DPDA_PREG_040_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_040_IE_REG_DPDA_PREG_040_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_040_IE_REG_ADDR (0x00042800u)
#define CSL_DFE_DPDA_DPDA_PREG_040_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_040_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_040_q : 23;
#else 
    Uint32 dpda_preg_040_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_040_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_040_Q_REG_DPDA_PREG_040_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_040_Q_REG_DPDA_PREG_040_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_040_Q_REG_DPDA_PREG_040_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_040_Q_REG_ADDR (0x00042804u)
#define CSL_DFE_DPDA_DPDA_PREG_040_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_041_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_041_ie : 31;
#else 
    Uint32 dpda_preg_041_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_041_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_041_IE_REG_DPDA_PREG_041_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_041_IE_REG_DPDA_PREG_041_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_041_IE_REG_DPDA_PREG_041_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_041_IE_REG_ADDR (0x00042900u)
#define CSL_DFE_DPDA_DPDA_PREG_041_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_041_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_041_q : 23;
#else 
    Uint32 dpda_preg_041_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_041_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_041_Q_REG_DPDA_PREG_041_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_041_Q_REG_DPDA_PREG_041_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_041_Q_REG_DPDA_PREG_041_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_041_Q_REG_ADDR (0x00042904u)
#define CSL_DFE_DPDA_DPDA_PREG_041_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_042_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_042_ie : 31;
#else 
    Uint32 dpda_preg_042_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_042_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_042_IE_REG_DPDA_PREG_042_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_042_IE_REG_DPDA_PREG_042_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_042_IE_REG_DPDA_PREG_042_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_042_IE_REG_ADDR (0x00042A00u)
#define CSL_DFE_DPDA_DPDA_PREG_042_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_042_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_042_q : 23;
#else 
    Uint32 dpda_preg_042_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_042_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_042_Q_REG_DPDA_PREG_042_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_042_Q_REG_DPDA_PREG_042_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_042_Q_REG_DPDA_PREG_042_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_042_Q_REG_ADDR (0x00042A04u)
#define CSL_DFE_DPDA_DPDA_PREG_042_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_043_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_043_ie : 31;
#else 
    Uint32 dpda_preg_043_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_043_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_043_IE_REG_DPDA_PREG_043_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_043_IE_REG_DPDA_PREG_043_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_043_IE_REG_DPDA_PREG_043_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_043_IE_REG_ADDR (0x00042B00u)
#define CSL_DFE_DPDA_DPDA_PREG_043_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_043_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_043_q : 23;
#else 
    Uint32 dpda_preg_043_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_043_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_043_Q_REG_DPDA_PREG_043_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_043_Q_REG_DPDA_PREG_043_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_043_Q_REG_DPDA_PREG_043_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_043_Q_REG_ADDR (0x00042B04u)
#define CSL_DFE_DPDA_DPDA_PREG_043_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_044_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_044_ie : 31;
#else 
    Uint32 dpda_preg_044_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_044_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_044_IE_REG_DPDA_PREG_044_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_044_IE_REG_DPDA_PREG_044_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_044_IE_REG_DPDA_PREG_044_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_044_IE_REG_ADDR (0x00042C00u)
#define CSL_DFE_DPDA_DPDA_PREG_044_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_044_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_044_q : 23;
#else 
    Uint32 dpda_preg_044_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_044_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_044_Q_REG_DPDA_PREG_044_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_044_Q_REG_DPDA_PREG_044_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_044_Q_REG_DPDA_PREG_044_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_044_Q_REG_ADDR (0x00042C04u)
#define CSL_DFE_DPDA_DPDA_PREG_044_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_045_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_045_ie : 31;
#else 
    Uint32 dpda_preg_045_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_045_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_045_IE_REG_DPDA_PREG_045_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_045_IE_REG_DPDA_PREG_045_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_045_IE_REG_DPDA_PREG_045_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_045_IE_REG_ADDR (0x00042D00u)
#define CSL_DFE_DPDA_DPDA_PREG_045_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_045_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_045_q : 23;
#else 
    Uint32 dpda_preg_045_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_045_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_045_Q_REG_DPDA_PREG_045_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_045_Q_REG_DPDA_PREG_045_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_045_Q_REG_DPDA_PREG_045_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_045_Q_REG_ADDR (0x00042D04u)
#define CSL_DFE_DPDA_DPDA_PREG_045_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_046_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_046_ie : 31;
#else 
    Uint32 dpda_preg_046_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_046_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_046_IE_REG_DPDA_PREG_046_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_046_IE_REG_DPDA_PREG_046_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_046_IE_REG_DPDA_PREG_046_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_046_IE_REG_ADDR (0x00042E00u)
#define CSL_DFE_DPDA_DPDA_PREG_046_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_046_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_046_q : 23;
#else 
    Uint32 dpda_preg_046_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_046_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_046_Q_REG_DPDA_PREG_046_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_046_Q_REG_DPDA_PREG_046_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_046_Q_REG_DPDA_PREG_046_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_046_Q_REG_ADDR (0x00042E04u)
#define CSL_DFE_DPDA_DPDA_PREG_046_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_047_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_047_ie : 31;
#else 
    Uint32 dpda_preg_047_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_047_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_047_IE_REG_DPDA_PREG_047_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_047_IE_REG_DPDA_PREG_047_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_047_IE_REG_DPDA_PREG_047_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_047_IE_REG_ADDR (0x00042F00u)
#define CSL_DFE_DPDA_DPDA_PREG_047_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_047_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_047_q : 23;
#else 
    Uint32 dpda_preg_047_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_047_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_047_Q_REG_DPDA_PREG_047_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_047_Q_REG_DPDA_PREG_047_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_047_Q_REG_DPDA_PREG_047_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_047_Q_REG_ADDR (0x00042F04u)
#define CSL_DFE_DPDA_DPDA_PREG_047_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_048_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_048_ie : 31;
#else 
    Uint32 dpda_preg_048_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_048_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_048_IE_REG_DPDA_PREG_048_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_048_IE_REG_DPDA_PREG_048_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_048_IE_REG_DPDA_PREG_048_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_048_IE_REG_ADDR (0x00043000u)
#define CSL_DFE_DPDA_DPDA_PREG_048_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_048_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_048_q : 23;
#else 
    Uint32 dpda_preg_048_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_048_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_048_Q_REG_DPDA_PREG_048_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_048_Q_REG_DPDA_PREG_048_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_048_Q_REG_DPDA_PREG_048_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_048_Q_REG_ADDR (0x00043004u)
#define CSL_DFE_DPDA_DPDA_PREG_048_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_049_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_049_ie : 31;
#else 
    Uint32 dpda_preg_049_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_049_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_049_IE_REG_DPDA_PREG_049_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_049_IE_REG_DPDA_PREG_049_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_049_IE_REG_DPDA_PREG_049_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_049_IE_REG_ADDR (0x00043100u)
#define CSL_DFE_DPDA_DPDA_PREG_049_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_049_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_049_q : 23;
#else 
    Uint32 dpda_preg_049_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_049_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_049_Q_REG_DPDA_PREG_049_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_049_Q_REG_DPDA_PREG_049_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_049_Q_REG_DPDA_PREG_049_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_049_Q_REG_ADDR (0x00043104u)
#define CSL_DFE_DPDA_DPDA_PREG_049_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_050_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_050_ie : 31;
#else 
    Uint32 dpda_preg_050_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_050_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_050_IE_REG_DPDA_PREG_050_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_050_IE_REG_DPDA_PREG_050_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_050_IE_REG_DPDA_PREG_050_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_050_IE_REG_ADDR (0x00043200u)
#define CSL_DFE_DPDA_DPDA_PREG_050_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_050_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_050_q : 23;
#else 
    Uint32 dpda_preg_050_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_050_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_050_Q_REG_DPDA_PREG_050_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_050_Q_REG_DPDA_PREG_050_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_050_Q_REG_DPDA_PREG_050_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_050_Q_REG_ADDR (0x00043204u)
#define CSL_DFE_DPDA_DPDA_PREG_050_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_051_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_051_ie : 31;
#else 
    Uint32 dpda_preg_051_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_051_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_051_IE_REG_DPDA_PREG_051_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_051_IE_REG_DPDA_PREG_051_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_051_IE_REG_DPDA_PREG_051_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_051_IE_REG_ADDR (0x00043300u)
#define CSL_DFE_DPDA_DPDA_PREG_051_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_051_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_051_q : 23;
#else 
    Uint32 dpda_preg_051_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_051_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_051_Q_REG_DPDA_PREG_051_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_051_Q_REG_DPDA_PREG_051_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_051_Q_REG_DPDA_PREG_051_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_051_Q_REG_ADDR (0x00043304u)
#define CSL_DFE_DPDA_DPDA_PREG_051_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_052_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_052_ie : 31;
#else 
    Uint32 dpda_preg_052_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_052_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_052_IE_REG_DPDA_PREG_052_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_052_IE_REG_DPDA_PREG_052_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_052_IE_REG_DPDA_PREG_052_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_052_IE_REG_ADDR (0x00043400u)
#define CSL_DFE_DPDA_DPDA_PREG_052_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_052_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_052_q : 23;
#else 
    Uint32 dpda_preg_052_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_052_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_052_Q_REG_DPDA_PREG_052_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_052_Q_REG_DPDA_PREG_052_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_052_Q_REG_DPDA_PREG_052_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_052_Q_REG_ADDR (0x00043404u)
#define CSL_DFE_DPDA_DPDA_PREG_052_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_053_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_053_ie : 31;
#else 
    Uint32 dpda_preg_053_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_053_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_053_IE_REG_DPDA_PREG_053_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_053_IE_REG_DPDA_PREG_053_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_053_IE_REG_DPDA_PREG_053_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_053_IE_REG_ADDR (0x00043500u)
#define CSL_DFE_DPDA_DPDA_PREG_053_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_053_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_053_q : 23;
#else 
    Uint32 dpda_preg_053_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_053_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_053_Q_REG_DPDA_PREG_053_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_053_Q_REG_DPDA_PREG_053_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_053_Q_REG_DPDA_PREG_053_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_053_Q_REG_ADDR (0x00043504u)
#define CSL_DFE_DPDA_DPDA_PREG_053_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_054_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_054_ie : 31;
#else 
    Uint32 dpda_preg_054_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_054_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_054_IE_REG_DPDA_PREG_054_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_054_IE_REG_DPDA_PREG_054_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_054_IE_REG_DPDA_PREG_054_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_054_IE_REG_ADDR (0x00043600u)
#define CSL_DFE_DPDA_DPDA_PREG_054_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_054_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_054_q : 23;
#else 
    Uint32 dpda_preg_054_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_054_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_054_Q_REG_DPDA_PREG_054_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_054_Q_REG_DPDA_PREG_054_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_054_Q_REG_DPDA_PREG_054_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_054_Q_REG_ADDR (0x00043604u)
#define CSL_DFE_DPDA_DPDA_PREG_054_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_055_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_055_ie : 31;
#else 
    Uint32 dpda_preg_055_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_055_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_055_IE_REG_DPDA_PREG_055_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_055_IE_REG_DPDA_PREG_055_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_055_IE_REG_DPDA_PREG_055_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_055_IE_REG_ADDR (0x00043700u)
#define CSL_DFE_DPDA_DPDA_PREG_055_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_055_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_055_q : 23;
#else 
    Uint32 dpda_preg_055_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_055_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_055_Q_REG_DPDA_PREG_055_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_055_Q_REG_DPDA_PREG_055_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_055_Q_REG_DPDA_PREG_055_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_055_Q_REG_ADDR (0x00043704u)
#define CSL_DFE_DPDA_DPDA_PREG_055_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_056_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_056_ie : 31;
#else 
    Uint32 dpda_preg_056_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_056_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_056_IE_REG_DPDA_PREG_056_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_056_IE_REG_DPDA_PREG_056_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_056_IE_REG_DPDA_PREG_056_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_056_IE_REG_ADDR (0x00043800u)
#define CSL_DFE_DPDA_DPDA_PREG_056_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_056_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_056_q : 23;
#else 
    Uint32 dpda_preg_056_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_056_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_056_Q_REG_DPDA_PREG_056_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_056_Q_REG_DPDA_PREG_056_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_056_Q_REG_DPDA_PREG_056_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_056_Q_REG_ADDR (0x00043804u)
#define CSL_DFE_DPDA_DPDA_PREG_056_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_057_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_057_ie : 31;
#else 
    Uint32 dpda_preg_057_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_057_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_057_IE_REG_DPDA_PREG_057_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_057_IE_REG_DPDA_PREG_057_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_057_IE_REG_DPDA_PREG_057_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_057_IE_REG_ADDR (0x00043900u)
#define CSL_DFE_DPDA_DPDA_PREG_057_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_057_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_057_q : 23;
#else 
    Uint32 dpda_preg_057_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_057_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_057_Q_REG_DPDA_PREG_057_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_057_Q_REG_DPDA_PREG_057_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_057_Q_REG_DPDA_PREG_057_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_057_Q_REG_ADDR (0x00043904u)
#define CSL_DFE_DPDA_DPDA_PREG_057_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_058_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_058_ie : 31;
#else 
    Uint32 dpda_preg_058_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_058_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_058_IE_REG_DPDA_PREG_058_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_058_IE_REG_DPDA_PREG_058_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_058_IE_REG_DPDA_PREG_058_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_058_IE_REG_ADDR (0x00043A00u)
#define CSL_DFE_DPDA_DPDA_PREG_058_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_058_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_058_q : 23;
#else 
    Uint32 dpda_preg_058_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_058_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_058_Q_REG_DPDA_PREG_058_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_058_Q_REG_DPDA_PREG_058_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_058_Q_REG_DPDA_PREG_058_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_058_Q_REG_ADDR (0x00043A04u)
#define CSL_DFE_DPDA_DPDA_PREG_058_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_059_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_059_ie : 31;
#else 
    Uint32 dpda_preg_059_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_059_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_059_IE_REG_DPDA_PREG_059_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_059_IE_REG_DPDA_PREG_059_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_059_IE_REG_DPDA_PREG_059_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_059_IE_REG_ADDR (0x00043B00u)
#define CSL_DFE_DPDA_DPDA_PREG_059_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_059_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_059_q : 23;
#else 
    Uint32 dpda_preg_059_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_059_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_059_Q_REG_DPDA_PREG_059_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_059_Q_REG_DPDA_PREG_059_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_059_Q_REG_DPDA_PREG_059_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_059_Q_REG_ADDR (0x00043B04u)
#define CSL_DFE_DPDA_DPDA_PREG_059_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_060_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_060_ie : 31;
#else 
    Uint32 dpda_preg_060_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_060_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_060_IE_REG_DPDA_PREG_060_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_060_IE_REG_DPDA_PREG_060_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_060_IE_REG_DPDA_PREG_060_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_060_IE_REG_ADDR (0x00043C00u)
#define CSL_DFE_DPDA_DPDA_PREG_060_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_060_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_060_q : 23;
#else 
    Uint32 dpda_preg_060_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_060_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_060_Q_REG_DPDA_PREG_060_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_060_Q_REG_DPDA_PREG_060_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_060_Q_REG_DPDA_PREG_060_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_060_Q_REG_ADDR (0x00043C04u)
#define CSL_DFE_DPDA_DPDA_PREG_060_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_061_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_061_ie : 31;
#else 
    Uint32 dpda_preg_061_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_061_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_061_IE_REG_DPDA_PREG_061_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_061_IE_REG_DPDA_PREG_061_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_061_IE_REG_DPDA_PREG_061_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_061_IE_REG_ADDR (0x00043D00u)
#define CSL_DFE_DPDA_DPDA_PREG_061_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_061_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_061_q : 23;
#else 
    Uint32 dpda_preg_061_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_061_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_061_Q_REG_DPDA_PREG_061_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_061_Q_REG_DPDA_PREG_061_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_061_Q_REG_DPDA_PREG_061_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_061_Q_REG_ADDR (0x00043D04u)
#define CSL_DFE_DPDA_DPDA_PREG_061_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_062_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_062_ie : 31;
#else 
    Uint32 dpda_preg_062_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_062_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_062_IE_REG_DPDA_PREG_062_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_062_IE_REG_DPDA_PREG_062_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_062_IE_REG_DPDA_PREG_062_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_062_IE_REG_ADDR (0x00043E00u)
#define CSL_DFE_DPDA_DPDA_PREG_062_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_062_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_062_q : 23;
#else 
    Uint32 dpda_preg_062_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_062_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_062_Q_REG_DPDA_PREG_062_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_062_Q_REG_DPDA_PREG_062_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_062_Q_REG_DPDA_PREG_062_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_062_Q_REG_ADDR (0x00043E04u)
#define CSL_DFE_DPDA_DPDA_PREG_062_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_063_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_063_ie : 31;
#else 
    Uint32 dpda_preg_063_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_063_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_063_IE_REG_DPDA_PREG_063_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_063_IE_REG_DPDA_PREG_063_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_063_IE_REG_DPDA_PREG_063_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_063_IE_REG_ADDR (0x00043F00u)
#define CSL_DFE_DPDA_DPDA_PREG_063_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_063_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_063_q : 23;
#else 
    Uint32 dpda_preg_063_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_063_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_063_Q_REG_DPDA_PREG_063_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_063_Q_REG_DPDA_PREG_063_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_063_Q_REG_DPDA_PREG_063_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_063_Q_REG_ADDR (0x00043F04u)
#define CSL_DFE_DPDA_DPDA_PREG_063_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_064_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_064_ie : 31;
#else 
    Uint32 dpda_preg_064_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_064_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_064_IE_REG_DPDA_PREG_064_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_064_IE_REG_DPDA_PREG_064_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_064_IE_REG_DPDA_PREG_064_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_064_IE_REG_ADDR (0x00044000u)
#define CSL_DFE_DPDA_DPDA_PREG_064_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_064_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_064_q : 23;
#else 
    Uint32 dpda_preg_064_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_064_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_064_Q_REG_DPDA_PREG_064_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_064_Q_REG_DPDA_PREG_064_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_064_Q_REG_DPDA_PREG_064_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_064_Q_REG_ADDR (0x00044004u)
#define CSL_DFE_DPDA_DPDA_PREG_064_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_065_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_065_ie : 31;
#else 
    Uint32 dpda_preg_065_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_065_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_065_IE_REG_DPDA_PREG_065_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_065_IE_REG_DPDA_PREG_065_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_065_IE_REG_DPDA_PREG_065_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_065_IE_REG_ADDR (0x00044100u)
#define CSL_DFE_DPDA_DPDA_PREG_065_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_065_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_065_q : 23;
#else 
    Uint32 dpda_preg_065_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_065_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_065_Q_REG_DPDA_PREG_065_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_065_Q_REG_DPDA_PREG_065_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_065_Q_REG_DPDA_PREG_065_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_065_Q_REG_ADDR (0x00044104u)
#define CSL_DFE_DPDA_DPDA_PREG_065_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_066_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_066_ie : 31;
#else 
    Uint32 dpda_preg_066_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_066_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_066_IE_REG_DPDA_PREG_066_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_066_IE_REG_DPDA_PREG_066_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_066_IE_REG_DPDA_PREG_066_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_066_IE_REG_ADDR (0x00044200u)
#define CSL_DFE_DPDA_DPDA_PREG_066_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_066_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_066_q : 23;
#else 
    Uint32 dpda_preg_066_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_066_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_066_Q_REG_DPDA_PREG_066_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_066_Q_REG_DPDA_PREG_066_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_066_Q_REG_DPDA_PREG_066_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_066_Q_REG_ADDR (0x00044204u)
#define CSL_DFE_DPDA_DPDA_PREG_066_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_067_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_067_ie : 31;
#else 
    Uint32 dpda_preg_067_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_067_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_067_IE_REG_DPDA_PREG_067_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_067_IE_REG_DPDA_PREG_067_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_067_IE_REG_DPDA_PREG_067_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_067_IE_REG_ADDR (0x00044300u)
#define CSL_DFE_DPDA_DPDA_PREG_067_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_067_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_067_q : 23;
#else 
    Uint32 dpda_preg_067_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_067_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_067_Q_REG_DPDA_PREG_067_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_067_Q_REG_DPDA_PREG_067_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_067_Q_REG_DPDA_PREG_067_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_067_Q_REG_ADDR (0x00044304u)
#define CSL_DFE_DPDA_DPDA_PREG_067_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_068_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_068_ie : 31;
#else 
    Uint32 dpda_preg_068_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_068_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_068_IE_REG_DPDA_PREG_068_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_068_IE_REG_DPDA_PREG_068_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_068_IE_REG_DPDA_PREG_068_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_068_IE_REG_ADDR (0x00044400u)
#define CSL_DFE_DPDA_DPDA_PREG_068_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_068_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_068_q : 23;
#else 
    Uint32 dpda_preg_068_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_068_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_068_Q_REG_DPDA_PREG_068_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_068_Q_REG_DPDA_PREG_068_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_068_Q_REG_DPDA_PREG_068_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_068_Q_REG_ADDR (0x00044404u)
#define CSL_DFE_DPDA_DPDA_PREG_068_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_069_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_069_ie : 31;
#else 
    Uint32 dpda_preg_069_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_069_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_069_IE_REG_DPDA_PREG_069_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_069_IE_REG_DPDA_PREG_069_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_069_IE_REG_DPDA_PREG_069_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_069_IE_REG_ADDR (0x00044500u)
#define CSL_DFE_DPDA_DPDA_PREG_069_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_069_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_069_q : 23;
#else 
    Uint32 dpda_preg_069_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_069_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_069_Q_REG_DPDA_PREG_069_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_069_Q_REG_DPDA_PREG_069_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_069_Q_REG_DPDA_PREG_069_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_069_Q_REG_ADDR (0x00044504u)
#define CSL_DFE_DPDA_DPDA_PREG_069_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_070_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_070_ie : 31;
#else 
    Uint32 dpda_preg_070_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_070_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_070_IE_REG_DPDA_PREG_070_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_070_IE_REG_DPDA_PREG_070_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_070_IE_REG_DPDA_PREG_070_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_070_IE_REG_ADDR (0x00044600u)
#define CSL_DFE_DPDA_DPDA_PREG_070_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_070_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_070_q : 23;
#else 
    Uint32 dpda_preg_070_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_070_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_070_Q_REG_DPDA_PREG_070_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_070_Q_REG_DPDA_PREG_070_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_070_Q_REG_DPDA_PREG_070_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_070_Q_REG_ADDR (0x00044604u)
#define CSL_DFE_DPDA_DPDA_PREG_070_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_071_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_071_ie : 31;
#else 
    Uint32 dpda_preg_071_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_071_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_071_IE_REG_DPDA_PREG_071_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_071_IE_REG_DPDA_PREG_071_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_071_IE_REG_DPDA_PREG_071_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_071_IE_REG_ADDR (0x00044700u)
#define CSL_DFE_DPDA_DPDA_PREG_071_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_071_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_071_q : 23;
#else 
    Uint32 dpda_preg_071_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_071_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_071_Q_REG_DPDA_PREG_071_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_071_Q_REG_DPDA_PREG_071_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_071_Q_REG_DPDA_PREG_071_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_071_Q_REG_ADDR (0x00044704u)
#define CSL_DFE_DPDA_DPDA_PREG_071_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_072_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_072_ie : 31;
#else 
    Uint32 dpda_preg_072_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_072_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_072_IE_REG_DPDA_PREG_072_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_072_IE_REG_DPDA_PREG_072_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_072_IE_REG_DPDA_PREG_072_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_072_IE_REG_ADDR (0x00044800u)
#define CSL_DFE_DPDA_DPDA_PREG_072_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_072_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_072_q : 23;
#else 
    Uint32 dpda_preg_072_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_072_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_072_Q_REG_DPDA_PREG_072_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_072_Q_REG_DPDA_PREG_072_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_072_Q_REG_DPDA_PREG_072_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_072_Q_REG_ADDR (0x00044804u)
#define CSL_DFE_DPDA_DPDA_PREG_072_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_073_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_073_ie : 31;
#else 
    Uint32 dpda_preg_073_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_073_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_073_IE_REG_DPDA_PREG_073_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_073_IE_REG_DPDA_PREG_073_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_073_IE_REG_DPDA_PREG_073_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_073_IE_REG_ADDR (0x00044900u)
#define CSL_DFE_DPDA_DPDA_PREG_073_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_073_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_073_q : 23;
#else 
    Uint32 dpda_preg_073_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_073_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_073_Q_REG_DPDA_PREG_073_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_073_Q_REG_DPDA_PREG_073_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_073_Q_REG_DPDA_PREG_073_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_073_Q_REG_ADDR (0x00044904u)
#define CSL_DFE_DPDA_DPDA_PREG_073_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_074_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_074_ie : 31;
#else 
    Uint32 dpda_preg_074_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_074_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_074_IE_REG_DPDA_PREG_074_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_074_IE_REG_DPDA_PREG_074_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_074_IE_REG_DPDA_PREG_074_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_074_IE_REG_ADDR (0x00044A00u)
#define CSL_DFE_DPDA_DPDA_PREG_074_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_074_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_074_q : 23;
#else 
    Uint32 dpda_preg_074_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_074_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_074_Q_REG_DPDA_PREG_074_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_074_Q_REG_DPDA_PREG_074_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_074_Q_REG_DPDA_PREG_074_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_074_Q_REG_ADDR (0x00044A04u)
#define CSL_DFE_DPDA_DPDA_PREG_074_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_075_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_075_ie : 31;
#else 
    Uint32 dpda_preg_075_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_075_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_075_IE_REG_DPDA_PREG_075_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_075_IE_REG_DPDA_PREG_075_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_075_IE_REG_DPDA_PREG_075_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_075_IE_REG_ADDR (0x00044B00u)
#define CSL_DFE_DPDA_DPDA_PREG_075_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_075_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_075_q : 23;
#else 
    Uint32 dpda_preg_075_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_075_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_075_Q_REG_DPDA_PREG_075_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_075_Q_REG_DPDA_PREG_075_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_075_Q_REG_DPDA_PREG_075_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_075_Q_REG_ADDR (0x00044B04u)
#define CSL_DFE_DPDA_DPDA_PREG_075_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_076_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_076_ie : 31;
#else 
    Uint32 dpda_preg_076_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_076_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_076_IE_REG_DPDA_PREG_076_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_076_IE_REG_DPDA_PREG_076_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_076_IE_REG_DPDA_PREG_076_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_076_IE_REG_ADDR (0x00044C00u)
#define CSL_DFE_DPDA_DPDA_PREG_076_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_076_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_076_q : 23;
#else 
    Uint32 dpda_preg_076_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_076_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_076_Q_REG_DPDA_PREG_076_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_076_Q_REG_DPDA_PREG_076_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_076_Q_REG_DPDA_PREG_076_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_076_Q_REG_ADDR (0x00044C04u)
#define CSL_DFE_DPDA_DPDA_PREG_076_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_077_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_077_ie : 31;
#else 
    Uint32 dpda_preg_077_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_077_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_077_IE_REG_DPDA_PREG_077_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_077_IE_REG_DPDA_PREG_077_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_077_IE_REG_DPDA_PREG_077_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_077_IE_REG_ADDR (0x00044D00u)
#define CSL_DFE_DPDA_DPDA_PREG_077_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_077_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_077_q : 23;
#else 
    Uint32 dpda_preg_077_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_077_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_077_Q_REG_DPDA_PREG_077_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_077_Q_REG_DPDA_PREG_077_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_077_Q_REG_DPDA_PREG_077_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_077_Q_REG_ADDR (0x00044D04u)
#define CSL_DFE_DPDA_DPDA_PREG_077_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_078_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_078_ie : 31;
#else 
    Uint32 dpda_preg_078_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_078_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_078_IE_REG_DPDA_PREG_078_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_078_IE_REG_DPDA_PREG_078_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_078_IE_REG_DPDA_PREG_078_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_078_IE_REG_ADDR (0x00044E00u)
#define CSL_DFE_DPDA_DPDA_PREG_078_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_078_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_078_q : 23;
#else 
    Uint32 dpda_preg_078_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_078_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_078_Q_REG_DPDA_PREG_078_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_078_Q_REG_DPDA_PREG_078_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_078_Q_REG_DPDA_PREG_078_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_078_Q_REG_ADDR (0x00044E04u)
#define CSL_DFE_DPDA_DPDA_PREG_078_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_079_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_079_ie : 31;
#else 
    Uint32 dpda_preg_079_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_079_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_079_IE_REG_DPDA_PREG_079_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_079_IE_REG_DPDA_PREG_079_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_079_IE_REG_DPDA_PREG_079_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_079_IE_REG_ADDR (0x00044F00u)
#define CSL_DFE_DPDA_DPDA_PREG_079_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_079_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_079_q : 23;
#else 
    Uint32 dpda_preg_079_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_079_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_079_Q_REG_DPDA_PREG_079_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_079_Q_REG_DPDA_PREG_079_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_079_Q_REG_DPDA_PREG_079_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_079_Q_REG_ADDR (0x00044F04u)
#define CSL_DFE_DPDA_DPDA_PREG_079_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_080_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_080_ie : 31;
#else 
    Uint32 dpda_preg_080_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_080_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_080_IE_REG_DPDA_PREG_080_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_080_IE_REG_DPDA_PREG_080_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_080_IE_REG_DPDA_PREG_080_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_080_IE_REG_ADDR (0x00045000u)
#define CSL_DFE_DPDA_DPDA_PREG_080_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_080_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_080_q : 23;
#else 
    Uint32 dpda_preg_080_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_080_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_080_Q_REG_DPDA_PREG_080_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_080_Q_REG_DPDA_PREG_080_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_080_Q_REG_DPDA_PREG_080_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_080_Q_REG_ADDR (0x00045004u)
#define CSL_DFE_DPDA_DPDA_PREG_080_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_081_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_081_ie : 31;
#else 
    Uint32 dpda_preg_081_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_081_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_081_IE_REG_DPDA_PREG_081_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_081_IE_REG_DPDA_PREG_081_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_081_IE_REG_DPDA_PREG_081_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_081_IE_REG_ADDR (0x00045100u)
#define CSL_DFE_DPDA_DPDA_PREG_081_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_081_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_081_q : 23;
#else 
    Uint32 dpda_preg_081_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_081_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_081_Q_REG_DPDA_PREG_081_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_081_Q_REG_DPDA_PREG_081_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_081_Q_REG_DPDA_PREG_081_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_081_Q_REG_ADDR (0x00045104u)
#define CSL_DFE_DPDA_DPDA_PREG_081_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_082_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_082_ie : 31;
#else 
    Uint32 dpda_preg_082_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_082_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_082_IE_REG_DPDA_PREG_082_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_082_IE_REG_DPDA_PREG_082_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_082_IE_REG_DPDA_PREG_082_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_082_IE_REG_ADDR (0x00045200u)
#define CSL_DFE_DPDA_DPDA_PREG_082_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_082_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_082_q : 23;
#else 
    Uint32 dpda_preg_082_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_082_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_082_Q_REG_DPDA_PREG_082_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_082_Q_REG_DPDA_PREG_082_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_082_Q_REG_DPDA_PREG_082_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_082_Q_REG_ADDR (0x00045204u)
#define CSL_DFE_DPDA_DPDA_PREG_082_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_083_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_083_ie : 31;
#else 
    Uint32 dpda_preg_083_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_083_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_083_IE_REG_DPDA_PREG_083_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_083_IE_REG_DPDA_PREG_083_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_083_IE_REG_DPDA_PREG_083_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_083_IE_REG_ADDR (0x00045300u)
#define CSL_DFE_DPDA_DPDA_PREG_083_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_083_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_083_q : 23;
#else 
    Uint32 dpda_preg_083_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_083_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_083_Q_REG_DPDA_PREG_083_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_083_Q_REG_DPDA_PREG_083_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_083_Q_REG_DPDA_PREG_083_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_083_Q_REG_ADDR (0x00045304u)
#define CSL_DFE_DPDA_DPDA_PREG_083_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_084_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_084_ie : 31;
#else 
    Uint32 dpda_preg_084_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_084_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_084_IE_REG_DPDA_PREG_084_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_084_IE_REG_DPDA_PREG_084_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_084_IE_REG_DPDA_PREG_084_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_084_IE_REG_ADDR (0x00045400u)
#define CSL_DFE_DPDA_DPDA_PREG_084_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_084_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_084_q : 23;
#else 
    Uint32 dpda_preg_084_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_084_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_084_Q_REG_DPDA_PREG_084_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_084_Q_REG_DPDA_PREG_084_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_084_Q_REG_DPDA_PREG_084_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_084_Q_REG_ADDR (0x00045404u)
#define CSL_DFE_DPDA_DPDA_PREG_084_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_085_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_085_ie : 31;
#else 
    Uint32 dpda_preg_085_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_085_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_085_IE_REG_DPDA_PREG_085_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_085_IE_REG_DPDA_PREG_085_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_085_IE_REG_DPDA_PREG_085_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_085_IE_REG_ADDR (0x00045500u)
#define CSL_DFE_DPDA_DPDA_PREG_085_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_085_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_085_q : 23;
#else 
    Uint32 dpda_preg_085_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_085_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_085_Q_REG_DPDA_PREG_085_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_085_Q_REG_DPDA_PREG_085_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_085_Q_REG_DPDA_PREG_085_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_085_Q_REG_ADDR (0x00045504u)
#define CSL_DFE_DPDA_DPDA_PREG_085_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_086_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_086_ie : 31;
#else 
    Uint32 dpda_preg_086_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_086_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_086_IE_REG_DPDA_PREG_086_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_086_IE_REG_DPDA_PREG_086_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_086_IE_REG_DPDA_PREG_086_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_086_IE_REG_ADDR (0x00045600u)
#define CSL_DFE_DPDA_DPDA_PREG_086_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_086_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_086_q : 23;
#else 
    Uint32 dpda_preg_086_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_086_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_086_Q_REG_DPDA_PREG_086_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_086_Q_REG_DPDA_PREG_086_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_086_Q_REG_DPDA_PREG_086_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_086_Q_REG_ADDR (0x00045604u)
#define CSL_DFE_DPDA_DPDA_PREG_086_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_087_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_087_ie : 31;
#else 
    Uint32 dpda_preg_087_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_087_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_087_IE_REG_DPDA_PREG_087_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_087_IE_REG_DPDA_PREG_087_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_087_IE_REG_DPDA_PREG_087_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_087_IE_REG_ADDR (0x00045700u)
#define CSL_DFE_DPDA_DPDA_PREG_087_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_087_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_087_q : 23;
#else 
    Uint32 dpda_preg_087_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_087_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_087_Q_REG_DPDA_PREG_087_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_087_Q_REG_DPDA_PREG_087_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_087_Q_REG_DPDA_PREG_087_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_087_Q_REG_ADDR (0x00045704u)
#define CSL_DFE_DPDA_DPDA_PREG_087_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_088_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_088_ie : 31;
#else 
    Uint32 dpda_preg_088_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_088_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_088_IE_REG_DPDA_PREG_088_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_088_IE_REG_DPDA_PREG_088_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_088_IE_REG_DPDA_PREG_088_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_088_IE_REG_ADDR (0x00045800u)
#define CSL_DFE_DPDA_DPDA_PREG_088_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_088_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_088_q : 23;
#else 
    Uint32 dpda_preg_088_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_088_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_088_Q_REG_DPDA_PREG_088_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_088_Q_REG_DPDA_PREG_088_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_088_Q_REG_DPDA_PREG_088_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_088_Q_REG_ADDR (0x00045804u)
#define CSL_DFE_DPDA_DPDA_PREG_088_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_089_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_089_ie : 31;
#else 
    Uint32 dpda_preg_089_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_089_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_089_IE_REG_DPDA_PREG_089_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_089_IE_REG_DPDA_PREG_089_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_089_IE_REG_DPDA_PREG_089_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_089_IE_REG_ADDR (0x00045900u)
#define CSL_DFE_DPDA_DPDA_PREG_089_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_089_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_089_q : 23;
#else 
    Uint32 dpda_preg_089_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_089_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_089_Q_REG_DPDA_PREG_089_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_089_Q_REG_DPDA_PREG_089_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_089_Q_REG_DPDA_PREG_089_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_089_Q_REG_ADDR (0x00045904u)
#define CSL_DFE_DPDA_DPDA_PREG_089_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_090_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_090_ie : 31;
#else 
    Uint32 dpda_preg_090_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_090_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_090_IE_REG_DPDA_PREG_090_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_090_IE_REG_DPDA_PREG_090_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_090_IE_REG_DPDA_PREG_090_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_090_IE_REG_ADDR (0x00045A00u)
#define CSL_DFE_DPDA_DPDA_PREG_090_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_090_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_090_q : 23;
#else 
    Uint32 dpda_preg_090_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_090_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_090_Q_REG_DPDA_PREG_090_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_090_Q_REG_DPDA_PREG_090_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_090_Q_REG_DPDA_PREG_090_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_090_Q_REG_ADDR (0x00045A04u)
#define CSL_DFE_DPDA_DPDA_PREG_090_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_091_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_091_ie : 31;
#else 
    Uint32 dpda_preg_091_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_091_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_091_IE_REG_DPDA_PREG_091_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_091_IE_REG_DPDA_PREG_091_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_091_IE_REG_DPDA_PREG_091_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_091_IE_REG_ADDR (0x00045B00u)
#define CSL_DFE_DPDA_DPDA_PREG_091_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_091_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_091_q : 23;
#else 
    Uint32 dpda_preg_091_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_091_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_091_Q_REG_DPDA_PREG_091_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_091_Q_REG_DPDA_PREG_091_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_091_Q_REG_DPDA_PREG_091_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_091_Q_REG_ADDR (0x00045B04u)
#define CSL_DFE_DPDA_DPDA_PREG_091_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_092_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_092_ie : 31;
#else 
    Uint32 dpda_preg_092_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_092_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_092_IE_REG_DPDA_PREG_092_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_092_IE_REG_DPDA_PREG_092_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_092_IE_REG_DPDA_PREG_092_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_092_IE_REG_ADDR (0x00045C00u)
#define CSL_DFE_DPDA_DPDA_PREG_092_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_092_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_092_q : 23;
#else 
    Uint32 dpda_preg_092_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_092_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_092_Q_REG_DPDA_PREG_092_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_092_Q_REG_DPDA_PREG_092_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_092_Q_REG_DPDA_PREG_092_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_092_Q_REG_ADDR (0x00045C04u)
#define CSL_DFE_DPDA_DPDA_PREG_092_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_093_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_093_ie : 31;
#else 
    Uint32 dpda_preg_093_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_093_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_093_IE_REG_DPDA_PREG_093_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_093_IE_REG_DPDA_PREG_093_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_093_IE_REG_DPDA_PREG_093_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_093_IE_REG_ADDR (0x00045D00u)
#define CSL_DFE_DPDA_DPDA_PREG_093_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_093_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_093_q : 23;
#else 
    Uint32 dpda_preg_093_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_093_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_093_Q_REG_DPDA_PREG_093_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_093_Q_REG_DPDA_PREG_093_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_093_Q_REG_DPDA_PREG_093_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_093_Q_REG_ADDR (0x00045D04u)
#define CSL_DFE_DPDA_DPDA_PREG_093_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_094_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_094_ie : 31;
#else 
    Uint32 dpda_preg_094_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_094_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_094_IE_REG_DPDA_PREG_094_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_094_IE_REG_DPDA_PREG_094_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_094_IE_REG_DPDA_PREG_094_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_094_IE_REG_ADDR (0x00045E00u)
#define CSL_DFE_DPDA_DPDA_PREG_094_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_094_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_094_q : 23;
#else 
    Uint32 dpda_preg_094_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_094_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_094_Q_REG_DPDA_PREG_094_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_094_Q_REG_DPDA_PREG_094_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_094_Q_REG_DPDA_PREG_094_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_094_Q_REG_ADDR (0x00045E04u)
#define CSL_DFE_DPDA_DPDA_PREG_094_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_095_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_095_ie : 31;
#else 
    Uint32 dpda_preg_095_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_095_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_095_IE_REG_DPDA_PREG_095_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_095_IE_REG_DPDA_PREG_095_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_095_IE_REG_DPDA_PREG_095_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_095_IE_REG_ADDR (0x00045F00u)
#define CSL_DFE_DPDA_DPDA_PREG_095_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_095_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_095_q : 23;
#else 
    Uint32 dpda_preg_095_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_095_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_095_Q_REG_DPDA_PREG_095_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_095_Q_REG_DPDA_PREG_095_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_095_Q_REG_DPDA_PREG_095_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_095_Q_REG_ADDR (0x00045F04u)
#define CSL_DFE_DPDA_DPDA_PREG_095_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_096_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_096_ie : 31;
#else 
    Uint32 dpda_preg_096_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_096_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_096_IE_REG_DPDA_PREG_096_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_096_IE_REG_DPDA_PREG_096_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_096_IE_REG_DPDA_PREG_096_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_096_IE_REG_ADDR (0x00046000u)
#define CSL_DFE_DPDA_DPDA_PREG_096_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_096_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_096_q : 23;
#else 
    Uint32 dpda_preg_096_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_096_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_096_Q_REG_DPDA_PREG_096_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_096_Q_REG_DPDA_PREG_096_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_096_Q_REG_DPDA_PREG_096_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_096_Q_REG_ADDR (0x00046004u)
#define CSL_DFE_DPDA_DPDA_PREG_096_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_097_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_097_ie : 31;
#else 
    Uint32 dpda_preg_097_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_097_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_097_IE_REG_DPDA_PREG_097_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_097_IE_REG_DPDA_PREG_097_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_097_IE_REG_DPDA_PREG_097_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_097_IE_REG_ADDR (0x00046100u)
#define CSL_DFE_DPDA_DPDA_PREG_097_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_097_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_097_q : 23;
#else 
    Uint32 dpda_preg_097_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_097_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_097_Q_REG_DPDA_PREG_097_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_097_Q_REG_DPDA_PREG_097_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_097_Q_REG_DPDA_PREG_097_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_097_Q_REG_ADDR (0x00046104u)
#define CSL_DFE_DPDA_DPDA_PREG_097_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_098_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_098_ie : 31;
#else 
    Uint32 dpda_preg_098_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_098_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_098_IE_REG_DPDA_PREG_098_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_098_IE_REG_DPDA_PREG_098_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_098_IE_REG_DPDA_PREG_098_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_098_IE_REG_ADDR (0x00046200u)
#define CSL_DFE_DPDA_DPDA_PREG_098_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_098_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_098_q : 23;
#else 
    Uint32 dpda_preg_098_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_098_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_098_Q_REG_DPDA_PREG_098_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_098_Q_REG_DPDA_PREG_098_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_098_Q_REG_DPDA_PREG_098_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_098_Q_REG_ADDR (0x00046204u)
#define CSL_DFE_DPDA_DPDA_PREG_098_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_099_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_099_ie : 31;
#else 
    Uint32 dpda_preg_099_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_099_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_099_IE_REG_DPDA_PREG_099_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_099_IE_REG_DPDA_PREG_099_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_099_IE_REG_DPDA_PREG_099_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_099_IE_REG_ADDR (0x00046300u)
#define CSL_DFE_DPDA_DPDA_PREG_099_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_099_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_099_q : 23;
#else 
    Uint32 dpda_preg_099_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_099_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_099_Q_REG_DPDA_PREG_099_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_099_Q_REG_DPDA_PREG_099_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_099_Q_REG_DPDA_PREG_099_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_099_Q_REG_ADDR (0x00046304u)
#define CSL_DFE_DPDA_DPDA_PREG_099_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_100_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_100_ie : 31;
#else 
    Uint32 dpda_preg_100_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_100_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_100_IE_REG_DPDA_PREG_100_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_100_IE_REG_DPDA_PREG_100_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_100_IE_REG_DPDA_PREG_100_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_100_IE_REG_ADDR (0x00046400u)
#define CSL_DFE_DPDA_DPDA_PREG_100_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_100_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_100_q : 23;
#else 
    Uint32 dpda_preg_100_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_100_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_100_Q_REG_DPDA_PREG_100_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_100_Q_REG_DPDA_PREG_100_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_100_Q_REG_DPDA_PREG_100_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_100_Q_REG_ADDR (0x00046404u)
#define CSL_DFE_DPDA_DPDA_PREG_100_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_101_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_101_ie : 31;
#else 
    Uint32 dpda_preg_101_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_101_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_101_IE_REG_DPDA_PREG_101_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_101_IE_REG_DPDA_PREG_101_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_101_IE_REG_DPDA_PREG_101_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_101_IE_REG_ADDR (0x00046500u)
#define CSL_DFE_DPDA_DPDA_PREG_101_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_101_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_101_q : 23;
#else 
    Uint32 dpda_preg_101_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_101_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_101_Q_REG_DPDA_PREG_101_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_101_Q_REG_DPDA_PREG_101_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_101_Q_REG_DPDA_PREG_101_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_101_Q_REG_ADDR (0x00046504u)
#define CSL_DFE_DPDA_DPDA_PREG_101_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_102_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_102_ie : 31;
#else 
    Uint32 dpda_preg_102_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_102_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_102_IE_REG_DPDA_PREG_102_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_102_IE_REG_DPDA_PREG_102_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_102_IE_REG_DPDA_PREG_102_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_102_IE_REG_ADDR (0x00046600u)
#define CSL_DFE_DPDA_DPDA_PREG_102_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_102_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_102_q : 23;
#else 
    Uint32 dpda_preg_102_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_102_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_102_Q_REG_DPDA_PREG_102_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_102_Q_REG_DPDA_PREG_102_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_102_Q_REG_DPDA_PREG_102_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_102_Q_REG_ADDR (0x00046604u)
#define CSL_DFE_DPDA_DPDA_PREG_102_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_103_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_103_ie : 31;
#else 
    Uint32 dpda_preg_103_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_103_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_103_IE_REG_DPDA_PREG_103_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_103_IE_REG_DPDA_PREG_103_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_103_IE_REG_DPDA_PREG_103_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_103_IE_REG_ADDR (0x00046700u)
#define CSL_DFE_DPDA_DPDA_PREG_103_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_103_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_103_q : 23;
#else 
    Uint32 dpda_preg_103_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_103_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_103_Q_REG_DPDA_PREG_103_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_103_Q_REG_DPDA_PREG_103_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_103_Q_REG_DPDA_PREG_103_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_103_Q_REG_ADDR (0x00046704u)
#define CSL_DFE_DPDA_DPDA_PREG_103_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_104_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_104_ie : 31;
#else 
    Uint32 dpda_preg_104_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_104_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_104_IE_REG_DPDA_PREG_104_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_104_IE_REG_DPDA_PREG_104_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_104_IE_REG_DPDA_PREG_104_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_104_IE_REG_ADDR (0x00046800u)
#define CSL_DFE_DPDA_DPDA_PREG_104_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_104_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_104_q : 23;
#else 
    Uint32 dpda_preg_104_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_104_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_104_Q_REG_DPDA_PREG_104_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_104_Q_REG_DPDA_PREG_104_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_104_Q_REG_DPDA_PREG_104_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_104_Q_REG_ADDR (0x00046804u)
#define CSL_DFE_DPDA_DPDA_PREG_104_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_105_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_105_ie : 31;
#else 
    Uint32 dpda_preg_105_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_105_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_105_IE_REG_DPDA_PREG_105_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_105_IE_REG_DPDA_PREG_105_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_105_IE_REG_DPDA_PREG_105_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_105_IE_REG_ADDR (0x00046900u)
#define CSL_DFE_DPDA_DPDA_PREG_105_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_105_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_105_q : 23;
#else 
    Uint32 dpda_preg_105_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_105_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_105_Q_REG_DPDA_PREG_105_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_105_Q_REG_DPDA_PREG_105_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_105_Q_REG_DPDA_PREG_105_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_105_Q_REG_ADDR (0x00046904u)
#define CSL_DFE_DPDA_DPDA_PREG_105_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_106_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_106_ie : 31;
#else 
    Uint32 dpda_preg_106_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_106_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_106_IE_REG_DPDA_PREG_106_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_106_IE_REG_DPDA_PREG_106_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_106_IE_REG_DPDA_PREG_106_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_106_IE_REG_ADDR (0x00046A00u)
#define CSL_DFE_DPDA_DPDA_PREG_106_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_106_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_106_q : 23;
#else 
    Uint32 dpda_preg_106_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_106_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_106_Q_REG_DPDA_PREG_106_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_106_Q_REG_DPDA_PREG_106_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_106_Q_REG_DPDA_PREG_106_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_106_Q_REG_ADDR (0x00046A04u)
#define CSL_DFE_DPDA_DPDA_PREG_106_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_107_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_107_ie : 31;
#else 
    Uint32 dpda_preg_107_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_107_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_107_IE_REG_DPDA_PREG_107_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_107_IE_REG_DPDA_PREG_107_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_107_IE_REG_DPDA_PREG_107_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_107_IE_REG_ADDR (0x00046B00u)
#define CSL_DFE_DPDA_DPDA_PREG_107_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_107_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_107_q : 23;
#else 
    Uint32 dpda_preg_107_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_107_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_107_Q_REG_DPDA_PREG_107_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_107_Q_REG_DPDA_PREG_107_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_107_Q_REG_DPDA_PREG_107_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_107_Q_REG_ADDR (0x00046B04u)
#define CSL_DFE_DPDA_DPDA_PREG_107_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_108_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_108_ie : 31;
#else 
    Uint32 dpda_preg_108_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_108_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_108_IE_REG_DPDA_PREG_108_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_108_IE_REG_DPDA_PREG_108_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_108_IE_REG_DPDA_PREG_108_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_108_IE_REG_ADDR (0x00046C00u)
#define CSL_DFE_DPDA_DPDA_PREG_108_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_108_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_108_q : 23;
#else 
    Uint32 dpda_preg_108_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_108_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_108_Q_REG_DPDA_PREG_108_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_108_Q_REG_DPDA_PREG_108_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_108_Q_REG_DPDA_PREG_108_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_108_Q_REG_ADDR (0x00046C04u)
#define CSL_DFE_DPDA_DPDA_PREG_108_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_109_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_109_ie : 31;
#else 
    Uint32 dpda_preg_109_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_109_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_109_IE_REG_DPDA_PREG_109_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_109_IE_REG_DPDA_PREG_109_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_109_IE_REG_DPDA_PREG_109_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_109_IE_REG_ADDR (0x00046D00u)
#define CSL_DFE_DPDA_DPDA_PREG_109_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_109_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_109_q : 23;
#else 
    Uint32 dpda_preg_109_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_109_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_109_Q_REG_DPDA_PREG_109_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_109_Q_REG_DPDA_PREG_109_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_109_Q_REG_DPDA_PREG_109_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_109_Q_REG_ADDR (0x00046D04u)
#define CSL_DFE_DPDA_DPDA_PREG_109_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_110_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_110_ie : 31;
#else 
    Uint32 dpda_preg_110_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_110_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_110_IE_REG_DPDA_PREG_110_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_110_IE_REG_DPDA_PREG_110_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_110_IE_REG_DPDA_PREG_110_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_110_IE_REG_ADDR (0x00046E00u)
#define CSL_DFE_DPDA_DPDA_PREG_110_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_110_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_110_q : 23;
#else 
    Uint32 dpda_preg_110_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_110_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_110_Q_REG_DPDA_PREG_110_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_110_Q_REG_DPDA_PREG_110_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_110_Q_REG_DPDA_PREG_110_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_110_Q_REG_ADDR (0x00046E04u)
#define CSL_DFE_DPDA_DPDA_PREG_110_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_111_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_111_ie : 31;
#else 
    Uint32 dpda_preg_111_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_111_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_111_IE_REG_DPDA_PREG_111_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_111_IE_REG_DPDA_PREG_111_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_111_IE_REG_DPDA_PREG_111_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_111_IE_REG_ADDR (0x00046F00u)
#define CSL_DFE_DPDA_DPDA_PREG_111_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_111_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_111_q : 23;
#else 
    Uint32 dpda_preg_111_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_111_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_111_Q_REG_DPDA_PREG_111_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_111_Q_REG_DPDA_PREG_111_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_111_Q_REG_DPDA_PREG_111_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_111_Q_REG_ADDR (0x00046F04u)
#define CSL_DFE_DPDA_DPDA_PREG_111_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_112_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_112_ie : 31;
#else 
    Uint32 dpda_preg_112_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_112_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_112_IE_REG_DPDA_PREG_112_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_112_IE_REG_DPDA_PREG_112_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_112_IE_REG_DPDA_PREG_112_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_112_IE_REG_ADDR (0x00047000u)
#define CSL_DFE_DPDA_DPDA_PREG_112_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_112_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_112_q : 23;
#else 
    Uint32 dpda_preg_112_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_112_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_112_Q_REG_DPDA_PREG_112_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_112_Q_REG_DPDA_PREG_112_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_112_Q_REG_DPDA_PREG_112_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_112_Q_REG_ADDR (0x00047004u)
#define CSL_DFE_DPDA_DPDA_PREG_112_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_113_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_113_ie : 31;
#else 
    Uint32 dpda_preg_113_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_113_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_113_IE_REG_DPDA_PREG_113_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_113_IE_REG_DPDA_PREG_113_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_113_IE_REG_DPDA_PREG_113_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_113_IE_REG_ADDR (0x00047100u)
#define CSL_DFE_DPDA_DPDA_PREG_113_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_113_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_113_q : 23;
#else 
    Uint32 dpda_preg_113_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_113_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_113_Q_REG_DPDA_PREG_113_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_113_Q_REG_DPDA_PREG_113_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_113_Q_REG_DPDA_PREG_113_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_113_Q_REG_ADDR (0x00047104u)
#define CSL_DFE_DPDA_DPDA_PREG_113_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_114_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_114_ie : 31;
#else 
    Uint32 dpda_preg_114_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_114_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_114_IE_REG_DPDA_PREG_114_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_114_IE_REG_DPDA_PREG_114_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_114_IE_REG_DPDA_PREG_114_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_114_IE_REG_ADDR (0x00047200u)
#define CSL_DFE_DPDA_DPDA_PREG_114_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_114_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_114_q : 23;
#else 
    Uint32 dpda_preg_114_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_114_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_114_Q_REG_DPDA_PREG_114_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_114_Q_REG_DPDA_PREG_114_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_114_Q_REG_DPDA_PREG_114_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_114_Q_REG_ADDR (0x00047204u)
#define CSL_DFE_DPDA_DPDA_PREG_114_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_115_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_115_ie : 31;
#else 
    Uint32 dpda_preg_115_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_115_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_115_IE_REG_DPDA_PREG_115_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_115_IE_REG_DPDA_PREG_115_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_115_IE_REG_DPDA_PREG_115_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_115_IE_REG_ADDR (0x00047300u)
#define CSL_DFE_DPDA_DPDA_PREG_115_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_115_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_115_q : 23;
#else 
    Uint32 dpda_preg_115_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_115_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_115_Q_REG_DPDA_PREG_115_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_115_Q_REG_DPDA_PREG_115_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_115_Q_REG_DPDA_PREG_115_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_115_Q_REG_ADDR (0x00047304u)
#define CSL_DFE_DPDA_DPDA_PREG_115_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_116_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_116_ie : 31;
#else 
    Uint32 dpda_preg_116_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_116_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_116_IE_REG_DPDA_PREG_116_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_116_IE_REG_DPDA_PREG_116_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_116_IE_REG_DPDA_PREG_116_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_116_IE_REG_ADDR (0x00047400u)
#define CSL_DFE_DPDA_DPDA_PREG_116_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_116_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_116_q : 23;
#else 
    Uint32 dpda_preg_116_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_116_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_116_Q_REG_DPDA_PREG_116_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_116_Q_REG_DPDA_PREG_116_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_116_Q_REG_DPDA_PREG_116_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_116_Q_REG_ADDR (0x00047404u)
#define CSL_DFE_DPDA_DPDA_PREG_116_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_117_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_117_ie : 31;
#else 
    Uint32 dpda_preg_117_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_117_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_117_IE_REG_DPDA_PREG_117_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_117_IE_REG_DPDA_PREG_117_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_117_IE_REG_DPDA_PREG_117_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_117_IE_REG_ADDR (0x00047500u)
#define CSL_DFE_DPDA_DPDA_PREG_117_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_117_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_117_q : 23;
#else 
    Uint32 dpda_preg_117_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_117_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_117_Q_REG_DPDA_PREG_117_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_117_Q_REG_DPDA_PREG_117_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_117_Q_REG_DPDA_PREG_117_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_117_Q_REG_ADDR (0x00047504u)
#define CSL_DFE_DPDA_DPDA_PREG_117_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_118_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_118_ie : 31;
#else 
    Uint32 dpda_preg_118_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_118_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_118_IE_REG_DPDA_PREG_118_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_118_IE_REG_DPDA_PREG_118_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_118_IE_REG_DPDA_PREG_118_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_118_IE_REG_ADDR (0x00047600u)
#define CSL_DFE_DPDA_DPDA_PREG_118_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_118_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_118_q : 23;
#else 
    Uint32 dpda_preg_118_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_118_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_118_Q_REG_DPDA_PREG_118_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_118_Q_REG_DPDA_PREG_118_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_118_Q_REG_DPDA_PREG_118_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_118_Q_REG_ADDR (0x00047604u)
#define CSL_DFE_DPDA_DPDA_PREG_118_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_119_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_119_ie : 31;
#else 
    Uint32 dpda_preg_119_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_119_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_119_IE_REG_DPDA_PREG_119_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_119_IE_REG_DPDA_PREG_119_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_119_IE_REG_DPDA_PREG_119_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_119_IE_REG_ADDR (0x00047700u)
#define CSL_DFE_DPDA_DPDA_PREG_119_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_119_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_119_q : 23;
#else 
    Uint32 dpda_preg_119_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_119_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_119_Q_REG_DPDA_PREG_119_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_119_Q_REG_DPDA_PREG_119_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_119_Q_REG_DPDA_PREG_119_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_119_Q_REG_ADDR (0x00047704u)
#define CSL_DFE_DPDA_DPDA_PREG_119_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_120_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_120_ie : 31;
#else 
    Uint32 dpda_preg_120_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_120_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_120_IE_REG_DPDA_PREG_120_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_120_IE_REG_DPDA_PREG_120_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_120_IE_REG_DPDA_PREG_120_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_120_IE_REG_ADDR (0x00047800u)
#define CSL_DFE_DPDA_DPDA_PREG_120_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_120_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_120_q : 23;
#else 
    Uint32 dpda_preg_120_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_120_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_120_Q_REG_DPDA_PREG_120_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_120_Q_REG_DPDA_PREG_120_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_120_Q_REG_DPDA_PREG_120_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_120_Q_REG_ADDR (0x00047804u)
#define CSL_DFE_DPDA_DPDA_PREG_120_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_121_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_121_ie : 31;
#else 
    Uint32 dpda_preg_121_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_121_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_121_IE_REG_DPDA_PREG_121_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_121_IE_REG_DPDA_PREG_121_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_121_IE_REG_DPDA_PREG_121_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_121_IE_REG_ADDR (0x00047900u)
#define CSL_DFE_DPDA_DPDA_PREG_121_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_121_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_121_q : 23;
#else 
    Uint32 dpda_preg_121_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_121_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_121_Q_REG_DPDA_PREG_121_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_121_Q_REG_DPDA_PREG_121_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_121_Q_REG_DPDA_PREG_121_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_121_Q_REG_ADDR (0x00047904u)
#define CSL_DFE_DPDA_DPDA_PREG_121_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_122_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_122_ie : 31;
#else 
    Uint32 dpda_preg_122_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_122_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_122_IE_REG_DPDA_PREG_122_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_122_IE_REG_DPDA_PREG_122_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_122_IE_REG_DPDA_PREG_122_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_122_IE_REG_ADDR (0x00047A00u)
#define CSL_DFE_DPDA_DPDA_PREG_122_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_122_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_122_q : 23;
#else 
    Uint32 dpda_preg_122_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_122_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_122_Q_REG_DPDA_PREG_122_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_122_Q_REG_DPDA_PREG_122_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_122_Q_REG_DPDA_PREG_122_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_122_Q_REG_ADDR (0x00047A04u)
#define CSL_DFE_DPDA_DPDA_PREG_122_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_123_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_123_ie : 31;
#else 
    Uint32 dpda_preg_123_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_123_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_123_IE_REG_DPDA_PREG_123_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_123_IE_REG_DPDA_PREG_123_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_123_IE_REG_DPDA_PREG_123_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_123_IE_REG_ADDR (0x00047B00u)
#define CSL_DFE_DPDA_DPDA_PREG_123_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_123_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_123_q : 23;
#else 
    Uint32 dpda_preg_123_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_123_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_123_Q_REG_DPDA_PREG_123_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_123_Q_REG_DPDA_PREG_123_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_123_Q_REG_DPDA_PREG_123_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_123_Q_REG_ADDR (0x00047B04u)
#define CSL_DFE_DPDA_DPDA_PREG_123_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_124_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_124_ie : 31;
#else 
    Uint32 dpda_preg_124_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_124_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_124_IE_REG_DPDA_PREG_124_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_124_IE_REG_DPDA_PREG_124_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_124_IE_REG_DPDA_PREG_124_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_124_IE_REG_ADDR (0x00047C00u)
#define CSL_DFE_DPDA_DPDA_PREG_124_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_124_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_124_q : 23;
#else 
    Uint32 dpda_preg_124_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_124_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_124_Q_REG_DPDA_PREG_124_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_124_Q_REG_DPDA_PREG_124_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_124_Q_REG_DPDA_PREG_124_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_124_Q_REG_ADDR (0x00047C04u)
#define CSL_DFE_DPDA_DPDA_PREG_124_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_125_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_125_ie : 31;
#else 
    Uint32 dpda_preg_125_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_125_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_125_IE_REG_DPDA_PREG_125_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_125_IE_REG_DPDA_PREG_125_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_125_IE_REG_DPDA_PREG_125_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_125_IE_REG_ADDR (0x00047D00u)
#define CSL_DFE_DPDA_DPDA_PREG_125_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_125_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_125_q : 23;
#else 
    Uint32 dpda_preg_125_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_125_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_125_Q_REG_DPDA_PREG_125_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_125_Q_REG_DPDA_PREG_125_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_125_Q_REG_DPDA_PREG_125_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_125_Q_REG_ADDR (0x00047D04u)
#define CSL_DFE_DPDA_DPDA_PREG_125_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_126_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_126_ie : 31;
#else 
    Uint32 dpda_preg_126_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_126_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_126_IE_REG_DPDA_PREG_126_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_126_IE_REG_DPDA_PREG_126_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_126_IE_REG_DPDA_PREG_126_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_126_IE_REG_ADDR (0x00047E00u)
#define CSL_DFE_DPDA_DPDA_PREG_126_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_126_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_126_q : 23;
#else 
    Uint32 dpda_preg_126_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_126_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_126_Q_REG_DPDA_PREG_126_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_126_Q_REG_DPDA_PREG_126_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_126_Q_REG_DPDA_PREG_126_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_126_Q_REG_ADDR (0x00047E04u)
#define CSL_DFE_DPDA_DPDA_PREG_126_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_127_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_127_ie : 31;
#else 
    Uint32 dpda_preg_127_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_127_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_127_IE_REG_DPDA_PREG_127_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_127_IE_REG_DPDA_PREG_127_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_127_IE_REG_DPDA_PREG_127_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_127_IE_REG_ADDR (0x00047F00u)
#define CSL_DFE_DPDA_DPDA_PREG_127_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_127_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_127_q : 23;
#else 
    Uint32 dpda_preg_127_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_127_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_127_Q_REG_DPDA_PREG_127_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_127_Q_REG_DPDA_PREG_127_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_127_Q_REG_DPDA_PREG_127_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_127_Q_REG_ADDR (0x00047F04u)
#define CSL_DFE_DPDA_DPDA_PREG_127_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_128_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_128_ie : 31;
#else 
    Uint32 dpda_preg_128_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_128_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_128_IE_REG_DPDA_PREG_128_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_128_IE_REG_DPDA_PREG_128_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_128_IE_REG_DPDA_PREG_128_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_128_IE_REG_ADDR (0x00048000u)
#define CSL_DFE_DPDA_DPDA_PREG_128_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_128_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_128_q : 23;
#else 
    Uint32 dpda_preg_128_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_128_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_128_Q_REG_DPDA_PREG_128_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_128_Q_REG_DPDA_PREG_128_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_128_Q_REG_DPDA_PREG_128_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_128_Q_REG_ADDR (0x00048004u)
#define CSL_DFE_DPDA_DPDA_PREG_128_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_129_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_129_ie : 31;
#else 
    Uint32 dpda_preg_129_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_129_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_129_IE_REG_DPDA_PREG_129_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_129_IE_REG_DPDA_PREG_129_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_129_IE_REG_DPDA_PREG_129_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_129_IE_REG_ADDR (0x00048100u)
#define CSL_DFE_DPDA_DPDA_PREG_129_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_129_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_129_q : 23;
#else 
    Uint32 dpda_preg_129_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_129_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_129_Q_REG_DPDA_PREG_129_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_129_Q_REG_DPDA_PREG_129_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_129_Q_REG_DPDA_PREG_129_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_129_Q_REG_ADDR (0x00048104u)
#define CSL_DFE_DPDA_DPDA_PREG_129_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_130_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_130_ie : 31;
#else 
    Uint32 dpda_preg_130_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_130_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_130_IE_REG_DPDA_PREG_130_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_130_IE_REG_DPDA_PREG_130_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_130_IE_REG_DPDA_PREG_130_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_130_IE_REG_ADDR (0x00048200u)
#define CSL_DFE_DPDA_DPDA_PREG_130_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_130_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_130_q : 23;
#else 
    Uint32 dpda_preg_130_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_130_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_130_Q_REG_DPDA_PREG_130_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_130_Q_REG_DPDA_PREG_130_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_130_Q_REG_DPDA_PREG_130_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_130_Q_REG_ADDR (0x00048204u)
#define CSL_DFE_DPDA_DPDA_PREG_130_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_131_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_131_ie : 31;
#else 
    Uint32 dpda_preg_131_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_131_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_131_IE_REG_DPDA_PREG_131_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_131_IE_REG_DPDA_PREG_131_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_131_IE_REG_DPDA_PREG_131_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_131_IE_REG_ADDR (0x00048300u)
#define CSL_DFE_DPDA_DPDA_PREG_131_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_131_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_131_q : 23;
#else 
    Uint32 dpda_preg_131_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_131_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_131_Q_REG_DPDA_PREG_131_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_131_Q_REG_DPDA_PREG_131_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_131_Q_REG_DPDA_PREG_131_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_131_Q_REG_ADDR (0x00048304u)
#define CSL_DFE_DPDA_DPDA_PREG_131_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_132_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_132_ie : 31;
#else 
    Uint32 dpda_preg_132_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_132_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_132_IE_REG_DPDA_PREG_132_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_132_IE_REG_DPDA_PREG_132_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_132_IE_REG_DPDA_PREG_132_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_132_IE_REG_ADDR (0x00048400u)
#define CSL_DFE_DPDA_DPDA_PREG_132_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_132_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_132_q : 23;
#else 
    Uint32 dpda_preg_132_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_132_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_132_Q_REG_DPDA_PREG_132_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_132_Q_REG_DPDA_PREG_132_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_132_Q_REG_DPDA_PREG_132_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_132_Q_REG_ADDR (0x00048404u)
#define CSL_DFE_DPDA_DPDA_PREG_132_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_133_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_133_ie : 31;
#else 
    Uint32 dpda_preg_133_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_133_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_133_IE_REG_DPDA_PREG_133_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_133_IE_REG_DPDA_PREG_133_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_133_IE_REG_DPDA_PREG_133_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_133_IE_REG_ADDR (0x00048500u)
#define CSL_DFE_DPDA_DPDA_PREG_133_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_133_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_133_q : 23;
#else 
    Uint32 dpda_preg_133_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_133_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_133_Q_REG_DPDA_PREG_133_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_133_Q_REG_DPDA_PREG_133_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_133_Q_REG_DPDA_PREG_133_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_133_Q_REG_ADDR (0x00048504u)
#define CSL_DFE_DPDA_DPDA_PREG_133_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_134_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_134_ie : 31;
#else 
    Uint32 dpda_preg_134_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_134_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_134_IE_REG_DPDA_PREG_134_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_134_IE_REG_DPDA_PREG_134_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_134_IE_REG_DPDA_PREG_134_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_134_IE_REG_ADDR (0x00048600u)
#define CSL_DFE_DPDA_DPDA_PREG_134_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_134_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_134_q : 23;
#else 
    Uint32 dpda_preg_134_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_134_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_134_Q_REG_DPDA_PREG_134_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_134_Q_REG_DPDA_PREG_134_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_134_Q_REG_DPDA_PREG_134_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_134_Q_REG_ADDR (0x00048604u)
#define CSL_DFE_DPDA_DPDA_PREG_134_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_135_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_135_ie : 31;
#else 
    Uint32 dpda_preg_135_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_135_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_135_IE_REG_DPDA_PREG_135_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_135_IE_REG_DPDA_PREG_135_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_135_IE_REG_DPDA_PREG_135_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_135_IE_REG_ADDR (0x00048700u)
#define CSL_DFE_DPDA_DPDA_PREG_135_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_135_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_135_q : 23;
#else 
    Uint32 dpda_preg_135_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_135_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_135_Q_REG_DPDA_PREG_135_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_135_Q_REG_DPDA_PREG_135_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_135_Q_REG_DPDA_PREG_135_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_135_Q_REG_ADDR (0x00048704u)
#define CSL_DFE_DPDA_DPDA_PREG_135_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_136_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_136_ie : 31;
#else 
    Uint32 dpda_preg_136_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_136_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_136_IE_REG_DPDA_PREG_136_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_136_IE_REG_DPDA_PREG_136_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_136_IE_REG_DPDA_PREG_136_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_136_IE_REG_ADDR (0x00048800u)
#define CSL_DFE_DPDA_DPDA_PREG_136_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_136_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_136_q : 23;
#else 
    Uint32 dpda_preg_136_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_136_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_136_Q_REG_DPDA_PREG_136_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_136_Q_REG_DPDA_PREG_136_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_136_Q_REG_DPDA_PREG_136_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_136_Q_REG_ADDR (0x00048804u)
#define CSL_DFE_DPDA_DPDA_PREG_136_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_137_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_137_ie : 31;
#else 
    Uint32 dpda_preg_137_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_137_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_137_IE_REG_DPDA_PREG_137_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_137_IE_REG_DPDA_PREG_137_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_137_IE_REG_DPDA_PREG_137_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_137_IE_REG_ADDR (0x00048900u)
#define CSL_DFE_DPDA_DPDA_PREG_137_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_137_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_137_q : 23;
#else 
    Uint32 dpda_preg_137_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_137_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_137_Q_REG_DPDA_PREG_137_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_137_Q_REG_DPDA_PREG_137_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_137_Q_REG_DPDA_PREG_137_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_137_Q_REG_ADDR (0x00048904u)
#define CSL_DFE_DPDA_DPDA_PREG_137_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_138_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_138_ie : 31;
#else 
    Uint32 dpda_preg_138_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_138_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_138_IE_REG_DPDA_PREG_138_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_138_IE_REG_DPDA_PREG_138_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_138_IE_REG_DPDA_PREG_138_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_138_IE_REG_ADDR (0x00048A00u)
#define CSL_DFE_DPDA_DPDA_PREG_138_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_138_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_138_q : 23;
#else 
    Uint32 dpda_preg_138_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_138_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_138_Q_REG_DPDA_PREG_138_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_138_Q_REG_DPDA_PREG_138_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_138_Q_REG_DPDA_PREG_138_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_138_Q_REG_ADDR (0x00048A04u)
#define CSL_DFE_DPDA_DPDA_PREG_138_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_139_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_139_ie : 31;
#else 
    Uint32 dpda_preg_139_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_139_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_139_IE_REG_DPDA_PREG_139_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_139_IE_REG_DPDA_PREG_139_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_139_IE_REG_DPDA_PREG_139_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_139_IE_REG_ADDR (0x00048B00u)
#define CSL_DFE_DPDA_DPDA_PREG_139_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_139_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_139_q : 23;
#else 
    Uint32 dpda_preg_139_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_139_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_139_Q_REG_DPDA_PREG_139_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_139_Q_REG_DPDA_PREG_139_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_139_Q_REG_DPDA_PREG_139_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_139_Q_REG_ADDR (0x00048B04u)
#define CSL_DFE_DPDA_DPDA_PREG_139_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_140_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_140_ie : 31;
#else 
    Uint32 dpda_preg_140_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_140_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_140_IE_REG_DPDA_PREG_140_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_140_IE_REG_DPDA_PREG_140_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_140_IE_REG_DPDA_PREG_140_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_140_IE_REG_ADDR (0x00048C00u)
#define CSL_DFE_DPDA_DPDA_PREG_140_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_140_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_140_q : 23;
#else 
    Uint32 dpda_preg_140_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_140_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_140_Q_REG_DPDA_PREG_140_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_140_Q_REG_DPDA_PREG_140_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_140_Q_REG_DPDA_PREG_140_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_140_Q_REG_ADDR (0x00048C04u)
#define CSL_DFE_DPDA_DPDA_PREG_140_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_141_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_141_ie : 31;
#else 
    Uint32 dpda_preg_141_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_141_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_141_IE_REG_DPDA_PREG_141_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_141_IE_REG_DPDA_PREG_141_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_141_IE_REG_DPDA_PREG_141_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_141_IE_REG_ADDR (0x00048D00u)
#define CSL_DFE_DPDA_DPDA_PREG_141_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_141_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_141_q : 23;
#else 
    Uint32 dpda_preg_141_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_141_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_141_Q_REG_DPDA_PREG_141_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_141_Q_REG_DPDA_PREG_141_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_141_Q_REG_DPDA_PREG_141_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_141_Q_REG_ADDR (0x00048D04u)
#define CSL_DFE_DPDA_DPDA_PREG_141_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_142_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_142_ie : 31;
#else 
    Uint32 dpda_preg_142_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_142_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_142_IE_REG_DPDA_PREG_142_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_142_IE_REG_DPDA_PREG_142_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_142_IE_REG_DPDA_PREG_142_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_142_IE_REG_ADDR (0x00048E00u)
#define CSL_DFE_DPDA_DPDA_PREG_142_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_142_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_142_q : 23;
#else 
    Uint32 dpda_preg_142_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_142_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_142_Q_REG_DPDA_PREG_142_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_142_Q_REG_DPDA_PREG_142_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_142_Q_REG_DPDA_PREG_142_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_142_Q_REG_ADDR (0x00048E04u)
#define CSL_DFE_DPDA_DPDA_PREG_142_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_143_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_143_ie : 31;
#else 
    Uint32 dpda_preg_143_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_143_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_143_IE_REG_DPDA_PREG_143_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_143_IE_REG_DPDA_PREG_143_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_143_IE_REG_DPDA_PREG_143_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_143_IE_REG_ADDR (0x00048F00u)
#define CSL_DFE_DPDA_DPDA_PREG_143_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_143_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_143_q : 23;
#else 
    Uint32 dpda_preg_143_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_143_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_143_Q_REG_DPDA_PREG_143_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_143_Q_REG_DPDA_PREG_143_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_143_Q_REG_DPDA_PREG_143_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_143_Q_REG_ADDR (0x00048F04u)
#define CSL_DFE_DPDA_DPDA_PREG_143_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_144_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_144_ie : 31;
#else 
    Uint32 dpda_preg_144_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_144_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_144_IE_REG_DPDA_PREG_144_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_144_IE_REG_DPDA_PREG_144_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_144_IE_REG_DPDA_PREG_144_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_144_IE_REG_ADDR (0x00049000u)
#define CSL_DFE_DPDA_DPDA_PREG_144_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_144_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_144_q : 23;
#else 
    Uint32 dpda_preg_144_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_144_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_144_Q_REG_DPDA_PREG_144_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_144_Q_REG_DPDA_PREG_144_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_144_Q_REG_DPDA_PREG_144_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_144_Q_REG_ADDR (0x00049004u)
#define CSL_DFE_DPDA_DPDA_PREG_144_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_145_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_145_ie : 31;
#else 
    Uint32 dpda_preg_145_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_145_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_145_IE_REG_DPDA_PREG_145_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_145_IE_REG_DPDA_PREG_145_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_145_IE_REG_DPDA_PREG_145_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_145_IE_REG_ADDR (0x00049100u)
#define CSL_DFE_DPDA_DPDA_PREG_145_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_145_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_145_q : 23;
#else 
    Uint32 dpda_preg_145_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_145_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_145_Q_REG_DPDA_PREG_145_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_145_Q_REG_DPDA_PREG_145_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_145_Q_REG_DPDA_PREG_145_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_145_Q_REG_ADDR (0x00049104u)
#define CSL_DFE_DPDA_DPDA_PREG_145_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_146_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_146_ie : 31;
#else 
    Uint32 dpda_preg_146_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_146_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_146_IE_REG_DPDA_PREG_146_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_146_IE_REG_DPDA_PREG_146_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_146_IE_REG_DPDA_PREG_146_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_146_IE_REG_ADDR (0x00049200u)
#define CSL_DFE_DPDA_DPDA_PREG_146_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_146_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_146_q : 23;
#else 
    Uint32 dpda_preg_146_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_146_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_146_Q_REG_DPDA_PREG_146_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_146_Q_REG_DPDA_PREG_146_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_146_Q_REG_DPDA_PREG_146_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_146_Q_REG_ADDR (0x00049204u)
#define CSL_DFE_DPDA_DPDA_PREG_146_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_147_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_147_ie : 31;
#else 
    Uint32 dpda_preg_147_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_147_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_147_IE_REG_DPDA_PREG_147_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_147_IE_REG_DPDA_PREG_147_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_147_IE_REG_DPDA_PREG_147_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_147_IE_REG_ADDR (0x00049300u)
#define CSL_DFE_DPDA_DPDA_PREG_147_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_147_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_147_q : 23;
#else 
    Uint32 dpda_preg_147_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_147_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_147_Q_REG_DPDA_PREG_147_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_147_Q_REG_DPDA_PREG_147_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_147_Q_REG_DPDA_PREG_147_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_147_Q_REG_ADDR (0x00049304u)
#define CSL_DFE_DPDA_DPDA_PREG_147_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_148_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_148_ie : 31;
#else 
    Uint32 dpda_preg_148_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_148_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_148_IE_REG_DPDA_PREG_148_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_148_IE_REG_DPDA_PREG_148_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_148_IE_REG_DPDA_PREG_148_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_148_IE_REG_ADDR (0x00049400u)
#define CSL_DFE_DPDA_DPDA_PREG_148_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_148_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_148_q : 23;
#else 
    Uint32 dpda_preg_148_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_148_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_148_Q_REG_DPDA_PREG_148_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_148_Q_REG_DPDA_PREG_148_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_148_Q_REG_DPDA_PREG_148_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_148_Q_REG_ADDR (0x00049404u)
#define CSL_DFE_DPDA_DPDA_PREG_148_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_149_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_149_ie : 31;
#else 
    Uint32 dpda_preg_149_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_149_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_149_IE_REG_DPDA_PREG_149_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_149_IE_REG_DPDA_PREG_149_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_149_IE_REG_DPDA_PREG_149_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_149_IE_REG_ADDR (0x00049500u)
#define CSL_DFE_DPDA_DPDA_PREG_149_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_149_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_149_q : 23;
#else 
    Uint32 dpda_preg_149_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_149_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_149_Q_REG_DPDA_PREG_149_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_149_Q_REG_DPDA_PREG_149_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_149_Q_REG_DPDA_PREG_149_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_149_Q_REG_ADDR (0x00049504u)
#define CSL_DFE_DPDA_DPDA_PREG_149_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_150_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_150_ie : 31;
#else 
    Uint32 dpda_preg_150_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_150_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_150_IE_REG_DPDA_PREG_150_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_150_IE_REG_DPDA_PREG_150_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_150_IE_REG_DPDA_PREG_150_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_150_IE_REG_ADDR (0x00049600u)
#define CSL_DFE_DPDA_DPDA_PREG_150_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_150_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_150_q : 23;
#else 
    Uint32 dpda_preg_150_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_150_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_150_Q_REG_DPDA_PREG_150_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_150_Q_REG_DPDA_PREG_150_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_150_Q_REG_DPDA_PREG_150_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_150_Q_REG_ADDR (0x00049604u)
#define CSL_DFE_DPDA_DPDA_PREG_150_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_151_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_151_ie : 31;
#else 
    Uint32 dpda_preg_151_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_151_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_151_IE_REG_DPDA_PREG_151_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_151_IE_REG_DPDA_PREG_151_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_151_IE_REG_DPDA_PREG_151_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_151_IE_REG_ADDR (0x00049700u)
#define CSL_DFE_DPDA_DPDA_PREG_151_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_151_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_151_q : 23;
#else 
    Uint32 dpda_preg_151_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_151_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_151_Q_REG_DPDA_PREG_151_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_151_Q_REG_DPDA_PREG_151_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_151_Q_REG_DPDA_PREG_151_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_151_Q_REG_ADDR (0x00049704u)
#define CSL_DFE_DPDA_DPDA_PREG_151_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_152_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_152_ie : 31;
#else 
    Uint32 dpda_preg_152_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_152_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_152_IE_REG_DPDA_PREG_152_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_152_IE_REG_DPDA_PREG_152_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_152_IE_REG_DPDA_PREG_152_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_152_IE_REG_ADDR (0x00049800u)
#define CSL_DFE_DPDA_DPDA_PREG_152_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_152_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_152_q : 23;
#else 
    Uint32 dpda_preg_152_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_152_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_152_Q_REG_DPDA_PREG_152_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_152_Q_REG_DPDA_PREG_152_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_152_Q_REG_DPDA_PREG_152_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_152_Q_REG_ADDR (0x00049804u)
#define CSL_DFE_DPDA_DPDA_PREG_152_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_153_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_153_ie : 31;
#else 
    Uint32 dpda_preg_153_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_153_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_153_IE_REG_DPDA_PREG_153_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_153_IE_REG_DPDA_PREG_153_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_153_IE_REG_DPDA_PREG_153_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_153_IE_REG_ADDR (0x00049900u)
#define CSL_DFE_DPDA_DPDA_PREG_153_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_153_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_153_q : 23;
#else 
    Uint32 dpda_preg_153_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_153_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_153_Q_REG_DPDA_PREG_153_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_153_Q_REG_DPDA_PREG_153_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_153_Q_REG_DPDA_PREG_153_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_153_Q_REG_ADDR (0x00049904u)
#define CSL_DFE_DPDA_DPDA_PREG_153_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_154_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_154_ie : 31;
#else 
    Uint32 dpda_preg_154_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_154_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_154_IE_REG_DPDA_PREG_154_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_154_IE_REG_DPDA_PREG_154_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_154_IE_REG_DPDA_PREG_154_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_154_IE_REG_ADDR (0x00049A00u)
#define CSL_DFE_DPDA_DPDA_PREG_154_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_154_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_154_q : 23;
#else 
    Uint32 dpda_preg_154_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_154_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_154_Q_REG_DPDA_PREG_154_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_154_Q_REG_DPDA_PREG_154_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_154_Q_REG_DPDA_PREG_154_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_154_Q_REG_ADDR (0x00049A04u)
#define CSL_DFE_DPDA_DPDA_PREG_154_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_155_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_155_ie : 31;
#else 
    Uint32 dpda_preg_155_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_155_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_155_IE_REG_DPDA_PREG_155_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_155_IE_REG_DPDA_PREG_155_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_155_IE_REG_DPDA_PREG_155_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_155_IE_REG_ADDR (0x00049B00u)
#define CSL_DFE_DPDA_DPDA_PREG_155_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_155_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_155_q : 23;
#else 
    Uint32 dpda_preg_155_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_155_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_155_Q_REG_DPDA_PREG_155_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_155_Q_REG_DPDA_PREG_155_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_155_Q_REG_DPDA_PREG_155_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_155_Q_REG_ADDR (0x00049B04u)
#define CSL_DFE_DPDA_DPDA_PREG_155_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_156_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_156_ie : 31;
#else 
    Uint32 dpda_preg_156_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_156_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_156_IE_REG_DPDA_PREG_156_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_156_IE_REG_DPDA_PREG_156_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_156_IE_REG_DPDA_PREG_156_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_156_IE_REG_ADDR (0x00049C00u)
#define CSL_DFE_DPDA_DPDA_PREG_156_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_156_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_156_q : 23;
#else 
    Uint32 dpda_preg_156_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_156_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_156_Q_REG_DPDA_PREG_156_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_156_Q_REG_DPDA_PREG_156_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_156_Q_REG_DPDA_PREG_156_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_156_Q_REG_ADDR (0x00049C04u)
#define CSL_DFE_DPDA_DPDA_PREG_156_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_157_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_157_ie : 31;
#else 
    Uint32 dpda_preg_157_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_157_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_157_IE_REG_DPDA_PREG_157_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_157_IE_REG_DPDA_PREG_157_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_157_IE_REG_DPDA_PREG_157_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_157_IE_REG_ADDR (0x00049D00u)
#define CSL_DFE_DPDA_DPDA_PREG_157_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_157_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_157_q : 23;
#else 
    Uint32 dpda_preg_157_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_157_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_157_Q_REG_DPDA_PREG_157_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_157_Q_REG_DPDA_PREG_157_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_157_Q_REG_DPDA_PREG_157_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_157_Q_REG_ADDR (0x00049D04u)
#define CSL_DFE_DPDA_DPDA_PREG_157_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_158_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_158_ie : 31;
#else 
    Uint32 dpda_preg_158_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_158_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_158_IE_REG_DPDA_PREG_158_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_158_IE_REG_DPDA_PREG_158_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_158_IE_REG_DPDA_PREG_158_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_158_IE_REG_ADDR (0x00049E00u)
#define CSL_DFE_DPDA_DPDA_PREG_158_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_158_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_158_q : 23;
#else 
    Uint32 dpda_preg_158_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_158_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_158_Q_REG_DPDA_PREG_158_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_158_Q_REG_DPDA_PREG_158_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_158_Q_REG_DPDA_PREG_158_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_158_Q_REG_ADDR (0x00049E04u)
#define CSL_DFE_DPDA_DPDA_PREG_158_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_159_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_159_ie : 31;
#else 
    Uint32 dpda_preg_159_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_159_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_159_IE_REG_DPDA_PREG_159_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_159_IE_REG_DPDA_PREG_159_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_159_IE_REG_DPDA_PREG_159_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_159_IE_REG_ADDR (0x00049F00u)
#define CSL_DFE_DPDA_DPDA_PREG_159_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_159_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_159_q : 23;
#else 
    Uint32 dpda_preg_159_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_159_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_159_Q_REG_DPDA_PREG_159_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_159_Q_REG_DPDA_PREG_159_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_159_Q_REG_DPDA_PREG_159_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_159_Q_REG_ADDR (0x00049F04u)
#define CSL_DFE_DPDA_DPDA_PREG_159_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_160_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_160_ie : 31;
#else 
    Uint32 dpda_preg_160_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_160_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_160_IE_REG_DPDA_PREG_160_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_160_IE_REG_DPDA_PREG_160_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_160_IE_REG_DPDA_PREG_160_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_160_IE_REG_ADDR (0x0004A000u)
#define CSL_DFE_DPDA_DPDA_PREG_160_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_160_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_160_q : 23;
#else 
    Uint32 dpda_preg_160_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_160_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_160_Q_REG_DPDA_PREG_160_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_160_Q_REG_DPDA_PREG_160_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_160_Q_REG_DPDA_PREG_160_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_160_Q_REG_ADDR (0x0004A004u)
#define CSL_DFE_DPDA_DPDA_PREG_160_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_161_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_161_ie : 31;
#else 
    Uint32 dpda_preg_161_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_161_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_161_IE_REG_DPDA_PREG_161_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_161_IE_REG_DPDA_PREG_161_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_161_IE_REG_DPDA_PREG_161_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_161_IE_REG_ADDR (0x0004A100u)
#define CSL_DFE_DPDA_DPDA_PREG_161_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_161_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_161_q : 23;
#else 
    Uint32 dpda_preg_161_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_161_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_161_Q_REG_DPDA_PREG_161_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_161_Q_REG_DPDA_PREG_161_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_161_Q_REG_DPDA_PREG_161_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_161_Q_REG_ADDR (0x0004A104u)
#define CSL_DFE_DPDA_DPDA_PREG_161_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_162_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_162_ie : 31;
#else 
    Uint32 dpda_preg_162_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_162_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_162_IE_REG_DPDA_PREG_162_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_162_IE_REG_DPDA_PREG_162_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_162_IE_REG_DPDA_PREG_162_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_162_IE_REG_ADDR (0x0004A200u)
#define CSL_DFE_DPDA_DPDA_PREG_162_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_162_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_162_q : 23;
#else 
    Uint32 dpda_preg_162_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_162_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_162_Q_REG_DPDA_PREG_162_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_162_Q_REG_DPDA_PREG_162_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_162_Q_REG_DPDA_PREG_162_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_162_Q_REG_ADDR (0x0004A204u)
#define CSL_DFE_DPDA_DPDA_PREG_162_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_163_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_163_ie : 31;
#else 
    Uint32 dpda_preg_163_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_163_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_163_IE_REG_DPDA_PREG_163_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_163_IE_REG_DPDA_PREG_163_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_163_IE_REG_DPDA_PREG_163_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_163_IE_REG_ADDR (0x0004A300u)
#define CSL_DFE_DPDA_DPDA_PREG_163_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_163_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_163_q : 23;
#else 
    Uint32 dpda_preg_163_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_163_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_163_Q_REG_DPDA_PREG_163_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_163_Q_REG_DPDA_PREG_163_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_163_Q_REG_DPDA_PREG_163_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_163_Q_REG_ADDR (0x0004A304u)
#define CSL_DFE_DPDA_DPDA_PREG_163_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_164_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_164_ie : 31;
#else 
    Uint32 dpda_preg_164_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_164_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_164_IE_REG_DPDA_PREG_164_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_164_IE_REG_DPDA_PREG_164_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_164_IE_REG_DPDA_PREG_164_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_164_IE_REG_ADDR (0x0004A400u)
#define CSL_DFE_DPDA_DPDA_PREG_164_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_164_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_164_q : 23;
#else 
    Uint32 dpda_preg_164_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_164_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_164_Q_REG_DPDA_PREG_164_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_164_Q_REG_DPDA_PREG_164_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_164_Q_REG_DPDA_PREG_164_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_164_Q_REG_ADDR (0x0004A404u)
#define CSL_DFE_DPDA_DPDA_PREG_164_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_165_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_165_ie : 31;
#else 
    Uint32 dpda_preg_165_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_165_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_165_IE_REG_DPDA_PREG_165_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_165_IE_REG_DPDA_PREG_165_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_165_IE_REG_DPDA_PREG_165_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_165_IE_REG_ADDR (0x0004A500u)
#define CSL_DFE_DPDA_DPDA_PREG_165_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_165_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_165_q : 23;
#else 
    Uint32 dpda_preg_165_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_165_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_165_Q_REG_DPDA_PREG_165_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_165_Q_REG_DPDA_PREG_165_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_165_Q_REG_DPDA_PREG_165_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_165_Q_REG_ADDR (0x0004A504u)
#define CSL_DFE_DPDA_DPDA_PREG_165_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_166_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_166_ie : 31;
#else 
    Uint32 dpda_preg_166_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_166_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_166_IE_REG_DPDA_PREG_166_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_166_IE_REG_DPDA_PREG_166_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_166_IE_REG_DPDA_PREG_166_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_166_IE_REG_ADDR (0x0004A600u)
#define CSL_DFE_DPDA_DPDA_PREG_166_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_166_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_166_q : 23;
#else 
    Uint32 dpda_preg_166_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_166_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_166_Q_REG_DPDA_PREG_166_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_166_Q_REG_DPDA_PREG_166_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_166_Q_REG_DPDA_PREG_166_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_166_Q_REG_ADDR (0x0004A604u)
#define CSL_DFE_DPDA_DPDA_PREG_166_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_167_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_167_ie : 31;
#else 
    Uint32 dpda_preg_167_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_167_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_167_IE_REG_DPDA_PREG_167_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_167_IE_REG_DPDA_PREG_167_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_167_IE_REG_DPDA_PREG_167_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_167_IE_REG_ADDR (0x0004A700u)
#define CSL_DFE_DPDA_DPDA_PREG_167_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_167_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_167_q : 23;
#else 
    Uint32 dpda_preg_167_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_167_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_167_Q_REG_DPDA_PREG_167_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_167_Q_REG_DPDA_PREG_167_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_167_Q_REG_DPDA_PREG_167_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_167_Q_REG_ADDR (0x0004A704u)
#define CSL_DFE_DPDA_DPDA_PREG_167_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_168_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_168_ie : 31;
#else 
    Uint32 dpda_preg_168_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_168_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_168_IE_REG_DPDA_PREG_168_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_168_IE_REG_DPDA_PREG_168_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_168_IE_REG_DPDA_PREG_168_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_168_IE_REG_ADDR (0x0004A800u)
#define CSL_DFE_DPDA_DPDA_PREG_168_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_168_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_168_q : 23;
#else 
    Uint32 dpda_preg_168_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_168_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_168_Q_REG_DPDA_PREG_168_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_168_Q_REG_DPDA_PREG_168_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_168_Q_REG_DPDA_PREG_168_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_168_Q_REG_ADDR (0x0004A804u)
#define CSL_DFE_DPDA_DPDA_PREG_168_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_169_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_169_ie : 31;
#else 
    Uint32 dpda_preg_169_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_169_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_169_IE_REG_DPDA_PREG_169_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_169_IE_REG_DPDA_PREG_169_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_169_IE_REG_DPDA_PREG_169_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_169_IE_REG_ADDR (0x0004A900u)
#define CSL_DFE_DPDA_DPDA_PREG_169_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_169_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_169_q : 23;
#else 
    Uint32 dpda_preg_169_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_169_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_169_Q_REG_DPDA_PREG_169_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_169_Q_REG_DPDA_PREG_169_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_169_Q_REG_DPDA_PREG_169_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_169_Q_REG_ADDR (0x0004A904u)
#define CSL_DFE_DPDA_DPDA_PREG_169_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_170_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_170_ie : 31;
#else 
    Uint32 dpda_preg_170_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_170_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_170_IE_REG_DPDA_PREG_170_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_170_IE_REG_DPDA_PREG_170_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_170_IE_REG_DPDA_PREG_170_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_170_IE_REG_ADDR (0x0004AA00u)
#define CSL_DFE_DPDA_DPDA_PREG_170_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_170_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_170_q : 23;
#else 
    Uint32 dpda_preg_170_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_170_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_170_Q_REG_DPDA_PREG_170_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_170_Q_REG_DPDA_PREG_170_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_170_Q_REG_DPDA_PREG_170_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_170_Q_REG_ADDR (0x0004AA04u)
#define CSL_DFE_DPDA_DPDA_PREG_170_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_171_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_171_ie : 31;
#else 
    Uint32 dpda_preg_171_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_171_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_171_IE_REG_DPDA_PREG_171_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_171_IE_REG_DPDA_PREG_171_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_171_IE_REG_DPDA_PREG_171_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_171_IE_REG_ADDR (0x0004AB00u)
#define CSL_DFE_DPDA_DPDA_PREG_171_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_171_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_171_q : 23;
#else 
    Uint32 dpda_preg_171_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_171_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_171_Q_REG_DPDA_PREG_171_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_171_Q_REG_DPDA_PREG_171_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_171_Q_REG_DPDA_PREG_171_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_171_Q_REG_ADDR (0x0004AB04u)
#define CSL_DFE_DPDA_DPDA_PREG_171_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_172_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_172_ie : 31;
#else 
    Uint32 dpda_preg_172_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_172_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_172_IE_REG_DPDA_PREG_172_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_172_IE_REG_DPDA_PREG_172_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_172_IE_REG_DPDA_PREG_172_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_172_IE_REG_ADDR (0x0004AC00u)
#define CSL_DFE_DPDA_DPDA_PREG_172_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_172_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_172_q : 23;
#else 
    Uint32 dpda_preg_172_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_172_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_172_Q_REG_DPDA_PREG_172_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_172_Q_REG_DPDA_PREG_172_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_172_Q_REG_DPDA_PREG_172_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_172_Q_REG_ADDR (0x0004AC04u)
#define CSL_DFE_DPDA_DPDA_PREG_172_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_173_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_173_ie : 31;
#else 
    Uint32 dpda_preg_173_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_173_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_173_IE_REG_DPDA_PREG_173_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_173_IE_REG_DPDA_PREG_173_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_173_IE_REG_DPDA_PREG_173_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_173_IE_REG_ADDR (0x0004AD00u)
#define CSL_DFE_DPDA_DPDA_PREG_173_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_173_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_173_q : 23;
#else 
    Uint32 dpda_preg_173_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_173_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_173_Q_REG_DPDA_PREG_173_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_173_Q_REG_DPDA_PREG_173_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_173_Q_REG_DPDA_PREG_173_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_173_Q_REG_ADDR (0x0004AD04u)
#define CSL_DFE_DPDA_DPDA_PREG_173_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_174_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_174_ie : 31;
#else 
    Uint32 dpda_preg_174_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_174_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_174_IE_REG_DPDA_PREG_174_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_174_IE_REG_DPDA_PREG_174_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_174_IE_REG_DPDA_PREG_174_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_174_IE_REG_ADDR (0x0004AE00u)
#define CSL_DFE_DPDA_DPDA_PREG_174_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_174_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_174_q : 23;
#else 
    Uint32 dpda_preg_174_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_174_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_174_Q_REG_DPDA_PREG_174_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_174_Q_REG_DPDA_PREG_174_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_174_Q_REG_DPDA_PREG_174_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_174_Q_REG_ADDR (0x0004AE04u)
#define CSL_DFE_DPDA_DPDA_PREG_174_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_175_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_175_ie : 31;
#else 
    Uint32 dpda_preg_175_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_175_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_175_IE_REG_DPDA_PREG_175_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_175_IE_REG_DPDA_PREG_175_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_175_IE_REG_DPDA_PREG_175_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_175_IE_REG_ADDR (0x0004AF00u)
#define CSL_DFE_DPDA_DPDA_PREG_175_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_175_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_175_q : 23;
#else 
    Uint32 dpda_preg_175_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_175_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_175_Q_REG_DPDA_PREG_175_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_175_Q_REG_DPDA_PREG_175_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_175_Q_REG_DPDA_PREG_175_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_175_Q_REG_ADDR (0x0004AF04u)
#define CSL_DFE_DPDA_DPDA_PREG_175_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_176_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_176_ie : 31;
#else 
    Uint32 dpda_preg_176_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_176_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_176_IE_REG_DPDA_PREG_176_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_176_IE_REG_DPDA_PREG_176_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_176_IE_REG_DPDA_PREG_176_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_176_IE_REG_ADDR (0x0004B000u)
#define CSL_DFE_DPDA_DPDA_PREG_176_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_176_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_176_q : 23;
#else 
    Uint32 dpda_preg_176_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_176_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_176_Q_REG_DPDA_PREG_176_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_176_Q_REG_DPDA_PREG_176_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_176_Q_REG_DPDA_PREG_176_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_176_Q_REG_ADDR (0x0004B004u)
#define CSL_DFE_DPDA_DPDA_PREG_176_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_177_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_177_ie : 31;
#else 
    Uint32 dpda_preg_177_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_177_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_177_IE_REG_DPDA_PREG_177_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_177_IE_REG_DPDA_PREG_177_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_177_IE_REG_DPDA_PREG_177_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_177_IE_REG_ADDR (0x0004B100u)
#define CSL_DFE_DPDA_DPDA_PREG_177_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_177_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_177_q : 23;
#else 
    Uint32 dpda_preg_177_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_177_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_177_Q_REG_DPDA_PREG_177_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_177_Q_REG_DPDA_PREG_177_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_177_Q_REG_DPDA_PREG_177_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_177_Q_REG_ADDR (0x0004B104u)
#define CSL_DFE_DPDA_DPDA_PREG_177_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_178_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_178_ie : 31;
#else 
    Uint32 dpda_preg_178_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_178_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_178_IE_REG_DPDA_PREG_178_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_178_IE_REG_DPDA_PREG_178_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_178_IE_REG_DPDA_PREG_178_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_178_IE_REG_ADDR (0x0004B200u)
#define CSL_DFE_DPDA_DPDA_PREG_178_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_178_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_178_q : 23;
#else 
    Uint32 dpda_preg_178_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_178_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_178_Q_REG_DPDA_PREG_178_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_178_Q_REG_DPDA_PREG_178_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_178_Q_REG_DPDA_PREG_178_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_178_Q_REG_ADDR (0x0004B204u)
#define CSL_DFE_DPDA_DPDA_PREG_178_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_179_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_179_ie : 31;
#else 
    Uint32 dpda_preg_179_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_179_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_179_IE_REG_DPDA_PREG_179_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_179_IE_REG_DPDA_PREG_179_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_179_IE_REG_DPDA_PREG_179_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_179_IE_REG_ADDR (0x0004B300u)
#define CSL_DFE_DPDA_DPDA_PREG_179_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_179_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_179_q : 23;
#else 
    Uint32 dpda_preg_179_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_179_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_179_Q_REG_DPDA_PREG_179_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_179_Q_REG_DPDA_PREG_179_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_179_Q_REG_DPDA_PREG_179_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_179_Q_REG_ADDR (0x0004B304u)
#define CSL_DFE_DPDA_DPDA_PREG_179_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_180_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_180_ie : 31;
#else 
    Uint32 dpda_preg_180_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_180_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_180_IE_REG_DPDA_PREG_180_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_180_IE_REG_DPDA_PREG_180_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_180_IE_REG_DPDA_PREG_180_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_180_IE_REG_ADDR (0x0004B400u)
#define CSL_DFE_DPDA_DPDA_PREG_180_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_180_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_180_q : 23;
#else 
    Uint32 dpda_preg_180_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_180_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_180_Q_REG_DPDA_PREG_180_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_180_Q_REG_DPDA_PREG_180_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_180_Q_REG_DPDA_PREG_180_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_180_Q_REG_ADDR (0x0004B404u)
#define CSL_DFE_DPDA_DPDA_PREG_180_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_181_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_181_ie : 31;
#else 
    Uint32 dpda_preg_181_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_181_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_181_IE_REG_DPDA_PREG_181_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_181_IE_REG_DPDA_PREG_181_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_181_IE_REG_DPDA_PREG_181_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_181_IE_REG_ADDR (0x0004B500u)
#define CSL_DFE_DPDA_DPDA_PREG_181_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_181_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_181_q : 23;
#else 
    Uint32 dpda_preg_181_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_181_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_181_Q_REG_DPDA_PREG_181_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_181_Q_REG_DPDA_PREG_181_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_181_Q_REG_DPDA_PREG_181_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_181_Q_REG_ADDR (0x0004B504u)
#define CSL_DFE_DPDA_DPDA_PREG_181_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_182_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_182_ie : 31;
#else 
    Uint32 dpda_preg_182_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_182_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_182_IE_REG_DPDA_PREG_182_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_182_IE_REG_DPDA_PREG_182_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_182_IE_REG_DPDA_PREG_182_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_182_IE_REG_ADDR (0x0004B600u)
#define CSL_DFE_DPDA_DPDA_PREG_182_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_182_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_182_q : 23;
#else 
    Uint32 dpda_preg_182_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_182_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_182_Q_REG_DPDA_PREG_182_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_182_Q_REG_DPDA_PREG_182_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_182_Q_REG_DPDA_PREG_182_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_182_Q_REG_ADDR (0x0004B604u)
#define CSL_DFE_DPDA_DPDA_PREG_182_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_183_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_183_ie : 31;
#else 
    Uint32 dpda_preg_183_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_183_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_183_IE_REG_DPDA_PREG_183_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_183_IE_REG_DPDA_PREG_183_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_183_IE_REG_DPDA_PREG_183_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_183_IE_REG_ADDR (0x0004B700u)
#define CSL_DFE_DPDA_DPDA_PREG_183_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_183_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_183_q : 23;
#else 
    Uint32 dpda_preg_183_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_183_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_183_Q_REG_DPDA_PREG_183_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_183_Q_REG_DPDA_PREG_183_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_183_Q_REG_DPDA_PREG_183_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_183_Q_REG_ADDR (0x0004B704u)
#define CSL_DFE_DPDA_DPDA_PREG_183_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_184_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_184_ie : 31;
#else 
    Uint32 dpda_preg_184_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_184_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_184_IE_REG_DPDA_PREG_184_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_184_IE_REG_DPDA_PREG_184_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_184_IE_REG_DPDA_PREG_184_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_184_IE_REG_ADDR (0x0004B800u)
#define CSL_DFE_DPDA_DPDA_PREG_184_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_184_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_184_q : 23;
#else 
    Uint32 dpda_preg_184_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_184_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_184_Q_REG_DPDA_PREG_184_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_184_Q_REG_DPDA_PREG_184_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_184_Q_REG_DPDA_PREG_184_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_184_Q_REG_ADDR (0x0004B804u)
#define CSL_DFE_DPDA_DPDA_PREG_184_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_185_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_185_ie : 31;
#else 
    Uint32 dpda_preg_185_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_185_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_185_IE_REG_DPDA_PREG_185_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_185_IE_REG_DPDA_PREG_185_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_185_IE_REG_DPDA_PREG_185_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_185_IE_REG_ADDR (0x0004B900u)
#define CSL_DFE_DPDA_DPDA_PREG_185_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_185_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_185_q : 23;
#else 
    Uint32 dpda_preg_185_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_185_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_185_Q_REG_DPDA_PREG_185_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_185_Q_REG_DPDA_PREG_185_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_185_Q_REG_DPDA_PREG_185_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_185_Q_REG_ADDR (0x0004B904u)
#define CSL_DFE_DPDA_DPDA_PREG_185_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_186_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_186_ie : 31;
#else 
    Uint32 dpda_preg_186_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_186_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_186_IE_REG_DPDA_PREG_186_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_186_IE_REG_DPDA_PREG_186_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_186_IE_REG_DPDA_PREG_186_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_186_IE_REG_ADDR (0x0004BA00u)
#define CSL_DFE_DPDA_DPDA_PREG_186_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_186_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_186_q : 23;
#else 
    Uint32 dpda_preg_186_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_186_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_186_Q_REG_DPDA_PREG_186_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_186_Q_REG_DPDA_PREG_186_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_186_Q_REG_DPDA_PREG_186_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_186_Q_REG_ADDR (0x0004BA04u)
#define CSL_DFE_DPDA_DPDA_PREG_186_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_187_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_187_ie : 31;
#else 
    Uint32 dpda_preg_187_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_187_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_187_IE_REG_DPDA_PREG_187_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_187_IE_REG_DPDA_PREG_187_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_187_IE_REG_DPDA_PREG_187_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_187_IE_REG_ADDR (0x0004BB00u)
#define CSL_DFE_DPDA_DPDA_PREG_187_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_187_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_187_q : 23;
#else 
    Uint32 dpda_preg_187_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_187_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_187_Q_REG_DPDA_PREG_187_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_187_Q_REG_DPDA_PREG_187_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_187_Q_REG_DPDA_PREG_187_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_187_Q_REG_ADDR (0x0004BB04u)
#define CSL_DFE_DPDA_DPDA_PREG_187_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_188_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_188_ie : 31;
#else 
    Uint32 dpda_preg_188_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_188_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_188_IE_REG_DPDA_PREG_188_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_188_IE_REG_DPDA_PREG_188_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_188_IE_REG_DPDA_PREG_188_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_188_IE_REG_ADDR (0x0004BC00u)
#define CSL_DFE_DPDA_DPDA_PREG_188_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_188_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_188_q : 23;
#else 
    Uint32 dpda_preg_188_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_188_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_188_Q_REG_DPDA_PREG_188_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_188_Q_REG_DPDA_PREG_188_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_188_Q_REG_DPDA_PREG_188_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_188_Q_REG_ADDR (0x0004BC04u)
#define CSL_DFE_DPDA_DPDA_PREG_188_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_189_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_189_ie : 31;
#else 
    Uint32 dpda_preg_189_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_189_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_189_IE_REG_DPDA_PREG_189_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_189_IE_REG_DPDA_PREG_189_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_189_IE_REG_DPDA_PREG_189_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_189_IE_REG_ADDR (0x0004BD00u)
#define CSL_DFE_DPDA_DPDA_PREG_189_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_189_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_189_q : 23;
#else 
    Uint32 dpda_preg_189_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_189_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_189_Q_REG_DPDA_PREG_189_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_189_Q_REG_DPDA_PREG_189_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_189_Q_REG_DPDA_PREG_189_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_189_Q_REG_ADDR (0x0004BD04u)
#define CSL_DFE_DPDA_DPDA_PREG_189_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_190_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_190_ie : 31;
#else 
    Uint32 dpda_preg_190_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_190_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_190_IE_REG_DPDA_PREG_190_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_190_IE_REG_DPDA_PREG_190_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_190_IE_REG_DPDA_PREG_190_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_190_IE_REG_ADDR (0x0004BE00u)
#define CSL_DFE_DPDA_DPDA_PREG_190_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_190_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_190_q : 23;
#else 
    Uint32 dpda_preg_190_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_190_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_190_Q_REG_DPDA_PREG_190_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_190_Q_REG_DPDA_PREG_190_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_190_Q_REG_DPDA_PREG_190_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_190_Q_REG_ADDR (0x0004BE04u)
#define CSL_DFE_DPDA_DPDA_PREG_190_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_191_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_191_ie : 31;
#else 
    Uint32 dpda_preg_191_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_191_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_191_IE_REG_DPDA_PREG_191_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_191_IE_REG_DPDA_PREG_191_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_191_IE_REG_DPDA_PREG_191_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_191_IE_REG_ADDR (0x0004BF00u)
#define CSL_DFE_DPDA_DPDA_PREG_191_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_191_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_191_q : 23;
#else 
    Uint32 dpda_preg_191_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_191_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_191_Q_REG_DPDA_PREG_191_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_191_Q_REG_DPDA_PREG_191_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_191_Q_REG_DPDA_PREG_191_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_191_Q_REG_ADDR (0x0004BF04u)
#define CSL_DFE_DPDA_DPDA_PREG_191_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_192_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_192_ie : 31;
#else 
    Uint32 dpda_preg_192_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_192_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_192_IE_REG_DPDA_PREG_192_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_192_IE_REG_DPDA_PREG_192_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_192_IE_REG_DPDA_PREG_192_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_192_IE_REG_ADDR (0x0004C000u)
#define CSL_DFE_DPDA_DPDA_PREG_192_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_192_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_192_q : 23;
#else 
    Uint32 dpda_preg_192_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_192_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_192_Q_REG_DPDA_PREG_192_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_192_Q_REG_DPDA_PREG_192_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_192_Q_REG_DPDA_PREG_192_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_192_Q_REG_ADDR (0x0004C004u)
#define CSL_DFE_DPDA_DPDA_PREG_192_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_193_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_193_ie : 31;
#else 
    Uint32 dpda_preg_193_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_193_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_193_IE_REG_DPDA_PREG_193_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_193_IE_REG_DPDA_PREG_193_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_193_IE_REG_DPDA_PREG_193_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_193_IE_REG_ADDR (0x0004C100u)
#define CSL_DFE_DPDA_DPDA_PREG_193_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_193_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_193_q : 23;
#else 
    Uint32 dpda_preg_193_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_193_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_193_Q_REG_DPDA_PREG_193_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_193_Q_REG_DPDA_PREG_193_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_193_Q_REG_DPDA_PREG_193_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_193_Q_REG_ADDR (0x0004C104u)
#define CSL_DFE_DPDA_DPDA_PREG_193_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_194_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_194_ie : 31;
#else 
    Uint32 dpda_preg_194_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_194_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_194_IE_REG_DPDA_PREG_194_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_194_IE_REG_DPDA_PREG_194_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_194_IE_REG_DPDA_PREG_194_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_194_IE_REG_ADDR (0x0004C200u)
#define CSL_DFE_DPDA_DPDA_PREG_194_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_194_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_194_q : 23;
#else 
    Uint32 dpda_preg_194_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_194_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_194_Q_REG_DPDA_PREG_194_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_194_Q_REG_DPDA_PREG_194_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_194_Q_REG_DPDA_PREG_194_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_194_Q_REG_ADDR (0x0004C204u)
#define CSL_DFE_DPDA_DPDA_PREG_194_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_195_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_195_ie : 31;
#else 
    Uint32 dpda_preg_195_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_195_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_195_IE_REG_DPDA_PREG_195_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_195_IE_REG_DPDA_PREG_195_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_195_IE_REG_DPDA_PREG_195_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_195_IE_REG_ADDR (0x0004C300u)
#define CSL_DFE_DPDA_DPDA_PREG_195_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_195_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_195_q : 23;
#else 
    Uint32 dpda_preg_195_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_195_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_195_Q_REG_DPDA_PREG_195_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_195_Q_REG_DPDA_PREG_195_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_195_Q_REG_DPDA_PREG_195_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_195_Q_REG_ADDR (0x0004C304u)
#define CSL_DFE_DPDA_DPDA_PREG_195_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_196_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_196_ie : 31;
#else 
    Uint32 dpda_preg_196_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_196_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_196_IE_REG_DPDA_PREG_196_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_196_IE_REG_DPDA_PREG_196_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_196_IE_REG_DPDA_PREG_196_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_196_IE_REG_ADDR (0x0004C400u)
#define CSL_DFE_DPDA_DPDA_PREG_196_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_196_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_196_q : 23;
#else 
    Uint32 dpda_preg_196_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_196_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_196_Q_REG_DPDA_PREG_196_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_196_Q_REG_DPDA_PREG_196_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_196_Q_REG_DPDA_PREG_196_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_196_Q_REG_ADDR (0x0004C404u)
#define CSL_DFE_DPDA_DPDA_PREG_196_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_197_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_197_ie : 31;
#else 
    Uint32 dpda_preg_197_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_197_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_197_IE_REG_DPDA_PREG_197_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_197_IE_REG_DPDA_PREG_197_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_197_IE_REG_DPDA_PREG_197_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_197_IE_REG_ADDR (0x0004C500u)
#define CSL_DFE_DPDA_DPDA_PREG_197_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_197_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_197_q : 23;
#else 
    Uint32 dpda_preg_197_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_197_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_197_Q_REG_DPDA_PREG_197_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_197_Q_REG_DPDA_PREG_197_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_197_Q_REG_DPDA_PREG_197_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_197_Q_REG_ADDR (0x0004C504u)
#define CSL_DFE_DPDA_DPDA_PREG_197_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_198_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_198_ie : 31;
#else 
    Uint32 dpda_preg_198_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_198_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_198_IE_REG_DPDA_PREG_198_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_198_IE_REG_DPDA_PREG_198_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_198_IE_REG_DPDA_PREG_198_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_198_IE_REG_ADDR (0x0004C600u)
#define CSL_DFE_DPDA_DPDA_PREG_198_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_198_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_198_q : 23;
#else 
    Uint32 dpda_preg_198_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_198_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_198_Q_REG_DPDA_PREG_198_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_198_Q_REG_DPDA_PREG_198_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_198_Q_REG_DPDA_PREG_198_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_198_Q_REG_ADDR (0x0004C604u)
#define CSL_DFE_DPDA_DPDA_PREG_198_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_199_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_199_ie : 31;
#else 
    Uint32 dpda_preg_199_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_199_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_199_IE_REG_DPDA_PREG_199_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_199_IE_REG_DPDA_PREG_199_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_199_IE_REG_DPDA_PREG_199_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_199_IE_REG_ADDR (0x0004C700u)
#define CSL_DFE_DPDA_DPDA_PREG_199_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_199_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_199_q : 23;
#else 
    Uint32 dpda_preg_199_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_199_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_199_Q_REG_DPDA_PREG_199_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_199_Q_REG_DPDA_PREG_199_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_199_Q_REG_DPDA_PREG_199_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_199_Q_REG_ADDR (0x0004C704u)
#define CSL_DFE_DPDA_DPDA_PREG_199_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_200_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_200_ie : 31;
#else 
    Uint32 dpda_preg_200_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_200_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_200_IE_REG_DPDA_PREG_200_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_200_IE_REG_DPDA_PREG_200_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_200_IE_REG_DPDA_PREG_200_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_200_IE_REG_ADDR (0x0004C800u)
#define CSL_DFE_DPDA_DPDA_PREG_200_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_200_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_200_q : 23;
#else 
    Uint32 dpda_preg_200_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_200_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_200_Q_REG_DPDA_PREG_200_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_200_Q_REG_DPDA_PREG_200_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_200_Q_REG_DPDA_PREG_200_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_200_Q_REG_ADDR (0x0004C804u)
#define CSL_DFE_DPDA_DPDA_PREG_200_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_201_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_201_ie : 31;
#else 
    Uint32 dpda_preg_201_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_201_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_201_IE_REG_DPDA_PREG_201_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_201_IE_REG_DPDA_PREG_201_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_201_IE_REG_DPDA_PREG_201_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_201_IE_REG_ADDR (0x0004C900u)
#define CSL_DFE_DPDA_DPDA_PREG_201_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_201_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_201_q : 23;
#else 
    Uint32 dpda_preg_201_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_201_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_201_Q_REG_DPDA_PREG_201_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_201_Q_REG_DPDA_PREG_201_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_201_Q_REG_DPDA_PREG_201_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_201_Q_REG_ADDR (0x0004C904u)
#define CSL_DFE_DPDA_DPDA_PREG_201_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_202_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_202_ie : 31;
#else 
    Uint32 dpda_preg_202_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_202_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_202_IE_REG_DPDA_PREG_202_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_202_IE_REG_DPDA_PREG_202_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_202_IE_REG_DPDA_PREG_202_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_202_IE_REG_ADDR (0x0004CA00u)
#define CSL_DFE_DPDA_DPDA_PREG_202_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_202_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_202_q : 23;
#else 
    Uint32 dpda_preg_202_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_202_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_202_Q_REG_DPDA_PREG_202_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_202_Q_REG_DPDA_PREG_202_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_202_Q_REG_DPDA_PREG_202_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_202_Q_REG_ADDR (0x0004CA04u)
#define CSL_DFE_DPDA_DPDA_PREG_202_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_203_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_203_ie : 31;
#else 
    Uint32 dpda_preg_203_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_203_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_203_IE_REG_DPDA_PREG_203_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_203_IE_REG_DPDA_PREG_203_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_203_IE_REG_DPDA_PREG_203_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_203_IE_REG_ADDR (0x0004CB00u)
#define CSL_DFE_DPDA_DPDA_PREG_203_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_203_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_203_q : 23;
#else 
    Uint32 dpda_preg_203_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_203_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_203_Q_REG_DPDA_PREG_203_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_203_Q_REG_DPDA_PREG_203_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_203_Q_REG_DPDA_PREG_203_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_203_Q_REG_ADDR (0x0004CB04u)
#define CSL_DFE_DPDA_DPDA_PREG_203_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_204_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_204_ie : 31;
#else 
    Uint32 dpda_preg_204_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_204_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_204_IE_REG_DPDA_PREG_204_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_204_IE_REG_DPDA_PREG_204_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_204_IE_REG_DPDA_PREG_204_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_204_IE_REG_ADDR (0x0004CC00u)
#define CSL_DFE_DPDA_DPDA_PREG_204_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_204_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_204_q : 23;
#else 
    Uint32 dpda_preg_204_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_204_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_204_Q_REG_DPDA_PREG_204_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_204_Q_REG_DPDA_PREG_204_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_204_Q_REG_DPDA_PREG_204_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_204_Q_REG_ADDR (0x0004CC04u)
#define CSL_DFE_DPDA_DPDA_PREG_204_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_205_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_205_ie : 31;
#else 
    Uint32 dpda_preg_205_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_205_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_205_IE_REG_DPDA_PREG_205_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_205_IE_REG_DPDA_PREG_205_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_205_IE_REG_DPDA_PREG_205_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_205_IE_REG_ADDR (0x0004CD00u)
#define CSL_DFE_DPDA_DPDA_PREG_205_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_205_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_205_q : 23;
#else 
    Uint32 dpda_preg_205_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_205_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_205_Q_REG_DPDA_PREG_205_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_205_Q_REG_DPDA_PREG_205_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_205_Q_REG_DPDA_PREG_205_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_205_Q_REG_ADDR (0x0004CD04u)
#define CSL_DFE_DPDA_DPDA_PREG_205_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_206_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_206_ie : 31;
#else 
    Uint32 dpda_preg_206_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_206_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_206_IE_REG_DPDA_PREG_206_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_206_IE_REG_DPDA_PREG_206_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_206_IE_REG_DPDA_PREG_206_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_206_IE_REG_ADDR (0x0004CE00u)
#define CSL_DFE_DPDA_DPDA_PREG_206_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_206_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_206_q : 23;
#else 
    Uint32 dpda_preg_206_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_206_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_206_Q_REG_DPDA_PREG_206_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_206_Q_REG_DPDA_PREG_206_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_206_Q_REG_DPDA_PREG_206_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_206_Q_REG_ADDR (0x0004CE04u)
#define CSL_DFE_DPDA_DPDA_PREG_206_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_207_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_207_ie : 31;
#else 
    Uint32 dpda_preg_207_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_207_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_207_IE_REG_DPDA_PREG_207_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_207_IE_REG_DPDA_PREG_207_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_207_IE_REG_DPDA_PREG_207_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_207_IE_REG_ADDR (0x0004CF00u)
#define CSL_DFE_DPDA_DPDA_PREG_207_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_207_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_207_q : 23;
#else 
    Uint32 dpda_preg_207_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_207_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_207_Q_REG_DPDA_PREG_207_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_207_Q_REG_DPDA_PREG_207_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_207_Q_REG_DPDA_PREG_207_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_207_Q_REG_ADDR (0x0004CF04u)
#define CSL_DFE_DPDA_DPDA_PREG_207_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_208_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_208_ie : 31;
#else 
    Uint32 dpda_preg_208_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_208_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_208_IE_REG_DPDA_PREG_208_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_208_IE_REG_DPDA_PREG_208_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_208_IE_REG_DPDA_PREG_208_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_208_IE_REG_ADDR (0x0004D000u)
#define CSL_DFE_DPDA_DPDA_PREG_208_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_208_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_208_q : 23;
#else 
    Uint32 dpda_preg_208_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_208_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_208_Q_REG_DPDA_PREG_208_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_208_Q_REG_DPDA_PREG_208_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_208_Q_REG_DPDA_PREG_208_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_208_Q_REG_ADDR (0x0004D004u)
#define CSL_DFE_DPDA_DPDA_PREG_208_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_209_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_209_ie : 31;
#else 
    Uint32 dpda_preg_209_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_209_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_209_IE_REG_DPDA_PREG_209_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_209_IE_REG_DPDA_PREG_209_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_209_IE_REG_DPDA_PREG_209_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_209_IE_REG_ADDR (0x0004D100u)
#define CSL_DFE_DPDA_DPDA_PREG_209_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_209_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_209_q : 23;
#else 
    Uint32 dpda_preg_209_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_209_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_209_Q_REG_DPDA_PREG_209_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_209_Q_REG_DPDA_PREG_209_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_209_Q_REG_DPDA_PREG_209_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_209_Q_REG_ADDR (0x0004D104u)
#define CSL_DFE_DPDA_DPDA_PREG_209_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_210_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_210_ie : 31;
#else 
    Uint32 dpda_preg_210_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_210_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_210_IE_REG_DPDA_PREG_210_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_210_IE_REG_DPDA_PREG_210_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_210_IE_REG_DPDA_PREG_210_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_210_IE_REG_ADDR (0x0004D200u)
#define CSL_DFE_DPDA_DPDA_PREG_210_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_210_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_210_q : 23;
#else 
    Uint32 dpda_preg_210_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_210_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_210_Q_REG_DPDA_PREG_210_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_210_Q_REG_DPDA_PREG_210_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_210_Q_REG_DPDA_PREG_210_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_210_Q_REG_ADDR (0x0004D204u)
#define CSL_DFE_DPDA_DPDA_PREG_210_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_211_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_211_ie : 31;
#else 
    Uint32 dpda_preg_211_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_211_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_211_IE_REG_DPDA_PREG_211_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_211_IE_REG_DPDA_PREG_211_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_211_IE_REG_DPDA_PREG_211_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_211_IE_REG_ADDR (0x0004D300u)
#define CSL_DFE_DPDA_DPDA_PREG_211_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_211_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_211_q : 23;
#else 
    Uint32 dpda_preg_211_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_211_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_211_Q_REG_DPDA_PREG_211_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_211_Q_REG_DPDA_PREG_211_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_211_Q_REG_DPDA_PREG_211_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_211_Q_REG_ADDR (0x0004D304u)
#define CSL_DFE_DPDA_DPDA_PREG_211_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_212_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_212_ie : 31;
#else 
    Uint32 dpda_preg_212_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_212_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_212_IE_REG_DPDA_PREG_212_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_212_IE_REG_DPDA_PREG_212_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_212_IE_REG_DPDA_PREG_212_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_212_IE_REG_ADDR (0x0004D400u)
#define CSL_DFE_DPDA_DPDA_PREG_212_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_212_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_212_q : 23;
#else 
    Uint32 dpda_preg_212_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_212_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_212_Q_REG_DPDA_PREG_212_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_212_Q_REG_DPDA_PREG_212_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_212_Q_REG_DPDA_PREG_212_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_212_Q_REG_ADDR (0x0004D404u)
#define CSL_DFE_DPDA_DPDA_PREG_212_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_213_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_213_ie : 31;
#else 
    Uint32 dpda_preg_213_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_213_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_213_IE_REG_DPDA_PREG_213_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_213_IE_REG_DPDA_PREG_213_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_213_IE_REG_DPDA_PREG_213_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_213_IE_REG_ADDR (0x0004D500u)
#define CSL_DFE_DPDA_DPDA_PREG_213_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_213_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_213_q : 23;
#else 
    Uint32 dpda_preg_213_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_213_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_213_Q_REG_DPDA_PREG_213_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_213_Q_REG_DPDA_PREG_213_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_213_Q_REG_DPDA_PREG_213_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_213_Q_REG_ADDR (0x0004D504u)
#define CSL_DFE_DPDA_DPDA_PREG_213_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_214_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_214_ie : 31;
#else 
    Uint32 dpda_preg_214_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_214_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_214_IE_REG_DPDA_PREG_214_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_214_IE_REG_DPDA_PREG_214_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_214_IE_REG_DPDA_PREG_214_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_214_IE_REG_ADDR (0x0004D600u)
#define CSL_DFE_DPDA_DPDA_PREG_214_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_214_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_214_q : 23;
#else 
    Uint32 dpda_preg_214_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_214_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_214_Q_REG_DPDA_PREG_214_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_214_Q_REG_DPDA_PREG_214_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_214_Q_REG_DPDA_PREG_214_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_214_Q_REG_ADDR (0x0004D604u)
#define CSL_DFE_DPDA_DPDA_PREG_214_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_215_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_215_ie : 31;
#else 
    Uint32 dpda_preg_215_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_215_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_215_IE_REG_DPDA_PREG_215_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_215_IE_REG_DPDA_PREG_215_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_215_IE_REG_DPDA_PREG_215_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_215_IE_REG_ADDR (0x0004D700u)
#define CSL_DFE_DPDA_DPDA_PREG_215_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_215_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_215_q : 23;
#else 
    Uint32 dpda_preg_215_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_215_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_215_Q_REG_DPDA_PREG_215_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_215_Q_REG_DPDA_PREG_215_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_215_Q_REG_DPDA_PREG_215_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_215_Q_REG_ADDR (0x0004D704u)
#define CSL_DFE_DPDA_DPDA_PREG_215_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_216_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_216_ie : 31;
#else 
    Uint32 dpda_preg_216_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_216_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_216_IE_REG_DPDA_PREG_216_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_216_IE_REG_DPDA_PREG_216_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_216_IE_REG_DPDA_PREG_216_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_216_IE_REG_ADDR (0x0004D800u)
#define CSL_DFE_DPDA_DPDA_PREG_216_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_216_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_216_q : 23;
#else 
    Uint32 dpda_preg_216_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_216_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_216_Q_REG_DPDA_PREG_216_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_216_Q_REG_DPDA_PREG_216_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_216_Q_REG_DPDA_PREG_216_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_216_Q_REG_ADDR (0x0004D804u)
#define CSL_DFE_DPDA_DPDA_PREG_216_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_217_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_217_ie : 31;
#else 
    Uint32 dpda_preg_217_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_217_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_217_IE_REG_DPDA_PREG_217_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_217_IE_REG_DPDA_PREG_217_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_217_IE_REG_DPDA_PREG_217_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_217_IE_REG_ADDR (0x0004D900u)
#define CSL_DFE_DPDA_DPDA_PREG_217_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_217_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_217_q : 23;
#else 
    Uint32 dpda_preg_217_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_217_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_217_Q_REG_DPDA_PREG_217_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_217_Q_REG_DPDA_PREG_217_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_217_Q_REG_DPDA_PREG_217_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_217_Q_REG_ADDR (0x0004D904u)
#define CSL_DFE_DPDA_DPDA_PREG_217_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_218_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_218_ie : 31;
#else 
    Uint32 dpda_preg_218_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_218_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_218_IE_REG_DPDA_PREG_218_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_218_IE_REG_DPDA_PREG_218_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_218_IE_REG_DPDA_PREG_218_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_218_IE_REG_ADDR (0x0004DA00u)
#define CSL_DFE_DPDA_DPDA_PREG_218_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_218_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_218_q : 23;
#else 
    Uint32 dpda_preg_218_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_218_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_218_Q_REG_DPDA_PREG_218_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_218_Q_REG_DPDA_PREG_218_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_218_Q_REG_DPDA_PREG_218_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_218_Q_REG_ADDR (0x0004DA04u)
#define CSL_DFE_DPDA_DPDA_PREG_218_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_219_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_219_ie : 31;
#else 
    Uint32 dpda_preg_219_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_219_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_219_IE_REG_DPDA_PREG_219_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_219_IE_REG_DPDA_PREG_219_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_219_IE_REG_DPDA_PREG_219_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_219_IE_REG_ADDR (0x0004DB00u)
#define CSL_DFE_DPDA_DPDA_PREG_219_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_219_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_219_q : 23;
#else 
    Uint32 dpda_preg_219_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_219_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_219_Q_REG_DPDA_PREG_219_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_219_Q_REG_DPDA_PREG_219_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_219_Q_REG_DPDA_PREG_219_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_219_Q_REG_ADDR (0x0004DB04u)
#define CSL_DFE_DPDA_DPDA_PREG_219_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_220_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_220_ie : 31;
#else 
    Uint32 dpda_preg_220_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_220_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_220_IE_REG_DPDA_PREG_220_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_220_IE_REG_DPDA_PREG_220_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_220_IE_REG_DPDA_PREG_220_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_220_IE_REG_ADDR (0x0004DC00u)
#define CSL_DFE_DPDA_DPDA_PREG_220_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_220_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_220_q : 23;
#else 
    Uint32 dpda_preg_220_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_220_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_220_Q_REG_DPDA_PREG_220_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_220_Q_REG_DPDA_PREG_220_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_220_Q_REG_DPDA_PREG_220_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_220_Q_REG_ADDR (0x0004DC04u)
#define CSL_DFE_DPDA_DPDA_PREG_220_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_221_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_221_ie : 31;
#else 
    Uint32 dpda_preg_221_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_221_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_221_IE_REG_DPDA_PREG_221_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_221_IE_REG_DPDA_PREG_221_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_221_IE_REG_DPDA_PREG_221_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_221_IE_REG_ADDR (0x0004DD00u)
#define CSL_DFE_DPDA_DPDA_PREG_221_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_221_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_221_q : 23;
#else 
    Uint32 dpda_preg_221_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_221_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_221_Q_REG_DPDA_PREG_221_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_221_Q_REG_DPDA_PREG_221_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_221_Q_REG_DPDA_PREG_221_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_221_Q_REG_ADDR (0x0004DD04u)
#define CSL_DFE_DPDA_DPDA_PREG_221_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_222_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_222_ie : 31;
#else 
    Uint32 dpda_preg_222_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_222_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_222_IE_REG_DPDA_PREG_222_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_222_IE_REG_DPDA_PREG_222_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_222_IE_REG_DPDA_PREG_222_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_222_IE_REG_ADDR (0x0004DE00u)
#define CSL_DFE_DPDA_DPDA_PREG_222_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_222_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_222_q : 23;
#else 
    Uint32 dpda_preg_222_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_222_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_222_Q_REG_DPDA_PREG_222_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_222_Q_REG_DPDA_PREG_222_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_222_Q_REG_DPDA_PREG_222_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_222_Q_REG_ADDR (0x0004DE04u)
#define CSL_DFE_DPDA_DPDA_PREG_222_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_223_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_223_ie : 31;
#else 
    Uint32 dpda_preg_223_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_223_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_223_IE_REG_DPDA_PREG_223_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_223_IE_REG_DPDA_PREG_223_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_223_IE_REG_DPDA_PREG_223_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_223_IE_REG_ADDR (0x0004DF00u)
#define CSL_DFE_DPDA_DPDA_PREG_223_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_223_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_223_q : 23;
#else 
    Uint32 dpda_preg_223_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_223_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_223_Q_REG_DPDA_PREG_223_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_223_Q_REG_DPDA_PREG_223_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_223_Q_REG_DPDA_PREG_223_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_223_Q_REG_ADDR (0x0004DF04u)
#define CSL_DFE_DPDA_DPDA_PREG_223_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_224_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_224_ie : 31;
#else 
    Uint32 dpda_preg_224_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_224_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_224_IE_REG_DPDA_PREG_224_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_224_IE_REG_DPDA_PREG_224_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_224_IE_REG_DPDA_PREG_224_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_224_IE_REG_ADDR (0x0004E000u)
#define CSL_DFE_DPDA_DPDA_PREG_224_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_224_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_224_q : 23;
#else 
    Uint32 dpda_preg_224_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_224_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_224_Q_REG_DPDA_PREG_224_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_224_Q_REG_DPDA_PREG_224_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_224_Q_REG_DPDA_PREG_224_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_224_Q_REG_ADDR (0x0004E004u)
#define CSL_DFE_DPDA_DPDA_PREG_224_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_225_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_225_ie : 31;
#else 
    Uint32 dpda_preg_225_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_225_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_225_IE_REG_DPDA_PREG_225_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_225_IE_REG_DPDA_PREG_225_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_225_IE_REG_DPDA_PREG_225_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_225_IE_REG_ADDR (0x0004E100u)
#define CSL_DFE_DPDA_DPDA_PREG_225_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_225_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_225_q : 23;
#else 
    Uint32 dpda_preg_225_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_225_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_225_Q_REG_DPDA_PREG_225_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_225_Q_REG_DPDA_PREG_225_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_225_Q_REG_DPDA_PREG_225_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_225_Q_REG_ADDR (0x0004E104u)
#define CSL_DFE_DPDA_DPDA_PREG_225_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_226_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_226_ie : 31;
#else 
    Uint32 dpda_preg_226_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_226_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_226_IE_REG_DPDA_PREG_226_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_226_IE_REG_DPDA_PREG_226_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_226_IE_REG_DPDA_PREG_226_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_226_IE_REG_ADDR (0x0004E200u)
#define CSL_DFE_DPDA_DPDA_PREG_226_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_226_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_226_q : 23;
#else 
    Uint32 dpda_preg_226_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_226_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_226_Q_REG_DPDA_PREG_226_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_226_Q_REG_DPDA_PREG_226_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_226_Q_REG_DPDA_PREG_226_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_226_Q_REG_ADDR (0x0004E204u)
#define CSL_DFE_DPDA_DPDA_PREG_226_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_227_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_227_ie : 31;
#else 
    Uint32 dpda_preg_227_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_227_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_227_IE_REG_DPDA_PREG_227_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_227_IE_REG_DPDA_PREG_227_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_227_IE_REG_DPDA_PREG_227_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_227_IE_REG_ADDR (0x0004E300u)
#define CSL_DFE_DPDA_DPDA_PREG_227_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_227_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_227_q : 23;
#else 
    Uint32 dpda_preg_227_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_227_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_227_Q_REG_DPDA_PREG_227_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_227_Q_REG_DPDA_PREG_227_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_227_Q_REG_DPDA_PREG_227_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_227_Q_REG_ADDR (0x0004E304u)
#define CSL_DFE_DPDA_DPDA_PREG_227_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_228_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_228_ie : 31;
#else 
    Uint32 dpda_preg_228_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_228_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_228_IE_REG_DPDA_PREG_228_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_228_IE_REG_DPDA_PREG_228_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_228_IE_REG_DPDA_PREG_228_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_228_IE_REG_ADDR (0x0004E400u)
#define CSL_DFE_DPDA_DPDA_PREG_228_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_228_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_228_q : 23;
#else 
    Uint32 dpda_preg_228_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_228_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_228_Q_REG_DPDA_PREG_228_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_228_Q_REG_DPDA_PREG_228_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_228_Q_REG_DPDA_PREG_228_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_228_Q_REG_ADDR (0x0004E404u)
#define CSL_DFE_DPDA_DPDA_PREG_228_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_229_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_229_ie : 31;
#else 
    Uint32 dpda_preg_229_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_229_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_229_IE_REG_DPDA_PREG_229_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_229_IE_REG_DPDA_PREG_229_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_229_IE_REG_DPDA_PREG_229_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_229_IE_REG_ADDR (0x0004E500u)
#define CSL_DFE_DPDA_DPDA_PREG_229_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_229_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_229_q : 23;
#else 
    Uint32 dpda_preg_229_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_229_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_229_Q_REG_DPDA_PREG_229_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_229_Q_REG_DPDA_PREG_229_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_229_Q_REG_DPDA_PREG_229_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_229_Q_REG_ADDR (0x0004E504u)
#define CSL_DFE_DPDA_DPDA_PREG_229_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_230_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_230_ie : 31;
#else 
    Uint32 dpda_preg_230_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_230_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_230_IE_REG_DPDA_PREG_230_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_230_IE_REG_DPDA_PREG_230_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_230_IE_REG_DPDA_PREG_230_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_230_IE_REG_ADDR (0x0004E600u)
#define CSL_DFE_DPDA_DPDA_PREG_230_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_230_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_230_q : 23;
#else 
    Uint32 dpda_preg_230_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_230_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_230_Q_REG_DPDA_PREG_230_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_230_Q_REG_DPDA_PREG_230_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_230_Q_REG_DPDA_PREG_230_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_230_Q_REG_ADDR (0x0004E604u)
#define CSL_DFE_DPDA_DPDA_PREG_230_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_231_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_231_ie : 31;
#else 
    Uint32 dpda_preg_231_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_231_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_231_IE_REG_DPDA_PREG_231_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_231_IE_REG_DPDA_PREG_231_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_231_IE_REG_DPDA_PREG_231_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_231_IE_REG_ADDR (0x0004E700u)
#define CSL_DFE_DPDA_DPDA_PREG_231_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_231_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_231_q : 23;
#else 
    Uint32 dpda_preg_231_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_231_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_231_Q_REG_DPDA_PREG_231_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_231_Q_REG_DPDA_PREG_231_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_231_Q_REG_DPDA_PREG_231_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_231_Q_REG_ADDR (0x0004E704u)
#define CSL_DFE_DPDA_DPDA_PREG_231_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_232_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_232_ie : 31;
#else 
    Uint32 dpda_preg_232_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_232_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_232_IE_REG_DPDA_PREG_232_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_232_IE_REG_DPDA_PREG_232_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_232_IE_REG_DPDA_PREG_232_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_232_IE_REG_ADDR (0x0004E800u)
#define CSL_DFE_DPDA_DPDA_PREG_232_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_232_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_232_q : 23;
#else 
    Uint32 dpda_preg_232_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_232_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_232_Q_REG_DPDA_PREG_232_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_232_Q_REG_DPDA_PREG_232_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_232_Q_REG_DPDA_PREG_232_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_232_Q_REG_ADDR (0x0004E804u)
#define CSL_DFE_DPDA_DPDA_PREG_232_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_233_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_233_ie : 31;
#else 
    Uint32 dpda_preg_233_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_233_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_233_IE_REG_DPDA_PREG_233_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_233_IE_REG_DPDA_PREG_233_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_233_IE_REG_DPDA_PREG_233_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_233_IE_REG_ADDR (0x0004E900u)
#define CSL_DFE_DPDA_DPDA_PREG_233_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_233_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_233_q : 23;
#else 
    Uint32 dpda_preg_233_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_233_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_233_Q_REG_DPDA_PREG_233_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_233_Q_REG_DPDA_PREG_233_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_233_Q_REG_DPDA_PREG_233_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_233_Q_REG_ADDR (0x0004E904u)
#define CSL_DFE_DPDA_DPDA_PREG_233_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_234_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_234_ie : 31;
#else 
    Uint32 dpda_preg_234_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_234_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_234_IE_REG_DPDA_PREG_234_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_234_IE_REG_DPDA_PREG_234_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_234_IE_REG_DPDA_PREG_234_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_234_IE_REG_ADDR (0x0004EA00u)
#define CSL_DFE_DPDA_DPDA_PREG_234_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_234_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_234_q : 23;
#else 
    Uint32 dpda_preg_234_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_234_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_234_Q_REG_DPDA_PREG_234_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_234_Q_REG_DPDA_PREG_234_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_234_Q_REG_DPDA_PREG_234_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_234_Q_REG_ADDR (0x0004EA04u)
#define CSL_DFE_DPDA_DPDA_PREG_234_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_235_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_235_ie : 31;
#else 
    Uint32 dpda_preg_235_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_235_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_235_IE_REG_DPDA_PREG_235_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_235_IE_REG_DPDA_PREG_235_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_235_IE_REG_DPDA_PREG_235_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_235_IE_REG_ADDR (0x0004EB00u)
#define CSL_DFE_DPDA_DPDA_PREG_235_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_235_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_235_q : 23;
#else 
    Uint32 dpda_preg_235_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_235_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_235_Q_REG_DPDA_PREG_235_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_235_Q_REG_DPDA_PREG_235_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_235_Q_REG_DPDA_PREG_235_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_235_Q_REG_ADDR (0x0004EB04u)
#define CSL_DFE_DPDA_DPDA_PREG_235_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_236_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_236_ie : 31;
#else 
    Uint32 dpda_preg_236_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_236_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_236_IE_REG_DPDA_PREG_236_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_236_IE_REG_DPDA_PREG_236_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_236_IE_REG_DPDA_PREG_236_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_236_IE_REG_ADDR (0x0004EC00u)
#define CSL_DFE_DPDA_DPDA_PREG_236_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_236_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_236_q : 23;
#else 
    Uint32 dpda_preg_236_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_236_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_236_Q_REG_DPDA_PREG_236_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_236_Q_REG_DPDA_PREG_236_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_236_Q_REG_DPDA_PREG_236_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_236_Q_REG_ADDR (0x0004EC04u)
#define CSL_DFE_DPDA_DPDA_PREG_236_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_237_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_237_ie : 31;
#else 
    Uint32 dpda_preg_237_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_237_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_237_IE_REG_DPDA_PREG_237_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_237_IE_REG_DPDA_PREG_237_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_237_IE_REG_DPDA_PREG_237_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_237_IE_REG_ADDR (0x0004ED00u)
#define CSL_DFE_DPDA_DPDA_PREG_237_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_237_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_237_q : 23;
#else 
    Uint32 dpda_preg_237_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_237_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_237_Q_REG_DPDA_PREG_237_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_237_Q_REG_DPDA_PREG_237_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_237_Q_REG_DPDA_PREG_237_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_237_Q_REG_ADDR (0x0004ED04u)
#define CSL_DFE_DPDA_DPDA_PREG_237_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_238_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_238_ie : 31;
#else 
    Uint32 dpda_preg_238_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_238_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_238_IE_REG_DPDA_PREG_238_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_238_IE_REG_DPDA_PREG_238_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_238_IE_REG_DPDA_PREG_238_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_238_IE_REG_ADDR (0x0004EE00u)
#define CSL_DFE_DPDA_DPDA_PREG_238_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_238_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_238_q : 23;
#else 
    Uint32 dpda_preg_238_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_238_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_238_Q_REG_DPDA_PREG_238_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_238_Q_REG_DPDA_PREG_238_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_238_Q_REG_DPDA_PREG_238_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_238_Q_REG_ADDR (0x0004EE04u)
#define CSL_DFE_DPDA_DPDA_PREG_238_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_239_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_239_ie : 31;
#else 
    Uint32 dpda_preg_239_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_239_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_239_IE_REG_DPDA_PREG_239_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_239_IE_REG_DPDA_PREG_239_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_239_IE_REG_DPDA_PREG_239_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_239_IE_REG_ADDR (0x0004EF00u)
#define CSL_DFE_DPDA_DPDA_PREG_239_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_239_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_239_q : 23;
#else 
    Uint32 dpda_preg_239_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_239_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_239_Q_REG_DPDA_PREG_239_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_239_Q_REG_DPDA_PREG_239_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_239_Q_REG_DPDA_PREG_239_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_239_Q_REG_ADDR (0x0004EF04u)
#define CSL_DFE_DPDA_DPDA_PREG_239_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_240_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_240_ie : 31;
#else 
    Uint32 dpda_preg_240_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_240_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_240_IE_REG_DPDA_PREG_240_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_240_IE_REG_DPDA_PREG_240_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_240_IE_REG_DPDA_PREG_240_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_240_IE_REG_ADDR (0x0004F000u)
#define CSL_DFE_DPDA_DPDA_PREG_240_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_240_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_240_q : 23;
#else 
    Uint32 dpda_preg_240_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_240_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_240_Q_REG_DPDA_PREG_240_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_240_Q_REG_DPDA_PREG_240_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_240_Q_REG_DPDA_PREG_240_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_240_Q_REG_ADDR (0x0004F004u)
#define CSL_DFE_DPDA_DPDA_PREG_240_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_241_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_241_ie : 31;
#else 
    Uint32 dpda_preg_241_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_241_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_241_IE_REG_DPDA_PREG_241_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_241_IE_REG_DPDA_PREG_241_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_241_IE_REG_DPDA_PREG_241_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_241_IE_REG_ADDR (0x0004F100u)
#define CSL_DFE_DPDA_DPDA_PREG_241_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_241_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_241_q : 23;
#else 
    Uint32 dpda_preg_241_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_241_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_241_Q_REG_DPDA_PREG_241_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_241_Q_REG_DPDA_PREG_241_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_241_Q_REG_DPDA_PREG_241_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_241_Q_REG_ADDR (0x0004F104u)
#define CSL_DFE_DPDA_DPDA_PREG_241_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_242_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_242_ie : 31;
#else 
    Uint32 dpda_preg_242_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_242_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_242_IE_REG_DPDA_PREG_242_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_242_IE_REG_DPDA_PREG_242_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_242_IE_REG_DPDA_PREG_242_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_242_IE_REG_ADDR (0x0004F200u)
#define CSL_DFE_DPDA_DPDA_PREG_242_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_242_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_242_q : 23;
#else 
    Uint32 dpda_preg_242_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_242_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_242_Q_REG_DPDA_PREG_242_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_242_Q_REG_DPDA_PREG_242_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_242_Q_REG_DPDA_PREG_242_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_242_Q_REG_ADDR (0x0004F204u)
#define CSL_DFE_DPDA_DPDA_PREG_242_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_243_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_243_ie : 31;
#else 
    Uint32 dpda_preg_243_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_243_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_243_IE_REG_DPDA_PREG_243_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_243_IE_REG_DPDA_PREG_243_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_243_IE_REG_DPDA_PREG_243_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_243_IE_REG_ADDR (0x0004F300u)
#define CSL_DFE_DPDA_DPDA_PREG_243_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_243_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_243_q : 23;
#else 
    Uint32 dpda_preg_243_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_243_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_243_Q_REG_DPDA_PREG_243_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_243_Q_REG_DPDA_PREG_243_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_243_Q_REG_DPDA_PREG_243_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_243_Q_REG_ADDR (0x0004F304u)
#define CSL_DFE_DPDA_DPDA_PREG_243_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_244_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_244_ie : 31;
#else 
    Uint32 dpda_preg_244_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_244_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_244_IE_REG_DPDA_PREG_244_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_244_IE_REG_DPDA_PREG_244_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_244_IE_REG_DPDA_PREG_244_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_244_IE_REG_ADDR (0x0004F400u)
#define CSL_DFE_DPDA_DPDA_PREG_244_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_244_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_244_q : 23;
#else 
    Uint32 dpda_preg_244_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_244_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_244_Q_REG_DPDA_PREG_244_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_244_Q_REG_DPDA_PREG_244_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_244_Q_REG_DPDA_PREG_244_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_244_Q_REG_ADDR (0x0004F404u)
#define CSL_DFE_DPDA_DPDA_PREG_244_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_245_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_245_ie : 31;
#else 
    Uint32 dpda_preg_245_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_245_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_245_IE_REG_DPDA_PREG_245_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_245_IE_REG_DPDA_PREG_245_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_245_IE_REG_DPDA_PREG_245_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_245_IE_REG_ADDR (0x0004F500u)
#define CSL_DFE_DPDA_DPDA_PREG_245_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_245_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_245_q : 23;
#else 
    Uint32 dpda_preg_245_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_245_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_245_Q_REG_DPDA_PREG_245_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_245_Q_REG_DPDA_PREG_245_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_245_Q_REG_DPDA_PREG_245_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_245_Q_REG_ADDR (0x0004F504u)
#define CSL_DFE_DPDA_DPDA_PREG_245_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_246_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_246_ie : 31;
#else 
    Uint32 dpda_preg_246_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_246_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_246_IE_REG_DPDA_PREG_246_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_246_IE_REG_DPDA_PREG_246_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_246_IE_REG_DPDA_PREG_246_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_246_IE_REG_ADDR (0x0004F600u)
#define CSL_DFE_DPDA_DPDA_PREG_246_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_246_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_246_q : 23;
#else 
    Uint32 dpda_preg_246_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_246_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_246_Q_REG_DPDA_PREG_246_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_246_Q_REG_DPDA_PREG_246_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_246_Q_REG_DPDA_PREG_246_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_246_Q_REG_ADDR (0x0004F604u)
#define CSL_DFE_DPDA_DPDA_PREG_246_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_247_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_247_ie : 31;
#else 
    Uint32 dpda_preg_247_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_247_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_247_IE_REG_DPDA_PREG_247_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_247_IE_REG_DPDA_PREG_247_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_247_IE_REG_DPDA_PREG_247_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_247_IE_REG_ADDR (0x0004F700u)
#define CSL_DFE_DPDA_DPDA_PREG_247_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_247_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_247_q : 23;
#else 
    Uint32 dpda_preg_247_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_247_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_247_Q_REG_DPDA_PREG_247_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_247_Q_REG_DPDA_PREG_247_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_247_Q_REG_DPDA_PREG_247_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_247_Q_REG_ADDR (0x0004F704u)
#define CSL_DFE_DPDA_DPDA_PREG_247_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_248_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_248_ie : 31;
#else 
    Uint32 dpda_preg_248_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_248_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_248_IE_REG_DPDA_PREG_248_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_248_IE_REG_DPDA_PREG_248_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_248_IE_REG_DPDA_PREG_248_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_248_IE_REG_ADDR (0x0004F800u)
#define CSL_DFE_DPDA_DPDA_PREG_248_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_248_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_248_q : 23;
#else 
    Uint32 dpda_preg_248_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_248_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_248_Q_REG_DPDA_PREG_248_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_248_Q_REG_DPDA_PREG_248_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_248_Q_REG_DPDA_PREG_248_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_248_Q_REG_ADDR (0x0004F804u)
#define CSL_DFE_DPDA_DPDA_PREG_248_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_249_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_249_ie : 31;
#else 
    Uint32 dpda_preg_249_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_249_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_249_IE_REG_DPDA_PREG_249_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_249_IE_REG_DPDA_PREG_249_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_249_IE_REG_DPDA_PREG_249_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_249_IE_REG_ADDR (0x0004F900u)
#define CSL_DFE_DPDA_DPDA_PREG_249_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_249_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_249_q : 23;
#else 
    Uint32 dpda_preg_249_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_249_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_249_Q_REG_DPDA_PREG_249_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_249_Q_REG_DPDA_PREG_249_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_249_Q_REG_DPDA_PREG_249_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_249_Q_REG_ADDR (0x0004F904u)
#define CSL_DFE_DPDA_DPDA_PREG_249_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_250_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_250_ie : 31;
#else 
    Uint32 dpda_preg_250_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_250_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_250_IE_REG_DPDA_PREG_250_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_250_IE_REG_DPDA_PREG_250_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_250_IE_REG_DPDA_PREG_250_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_250_IE_REG_ADDR (0x0004FA00u)
#define CSL_DFE_DPDA_DPDA_PREG_250_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_250_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_250_q : 23;
#else 
    Uint32 dpda_preg_250_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_250_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_250_Q_REG_DPDA_PREG_250_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_250_Q_REG_DPDA_PREG_250_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_250_Q_REG_DPDA_PREG_250_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_250_Q_REG_ADDR (0x0004FA04u)
#define CSL_DFE_DPDA_DPDA_PREG_250_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_251_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_251_ie : 31;
#else 
    Uint32 dpda_preg_251_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_251_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_251_IE_REG_DPDA_PREG_251_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_251_IE_REG_DPDA_PREG_251_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_251_IE_REG_DPDA_PREG_251_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_251_IE_REG_ADDR (0x0004FB00u)
#define CSL_DFE_DPDA_DPDA_PREG_251_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_251_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_251_q : 23;
#else 
    Uint32 dpda_preg_251_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_251_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_251_Q_REG_DPDA_PREG_251_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_251_Q_REG_DPDA_PREG_251_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_251_Q_REG_DPDA_PREG_251_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_251_Q_REG_ADDR (0x0004FB04u)
#define CSL_DFE_DPDA_DPDA_PREG_251_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_252_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_252_ie : 31;
#else 
    Uint32 dpda_preg_252_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_252_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_252_IE_REG_DPDA_PREG_252_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_252_IE_REG_DPDA_PREG_252_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_252_IE_REG_DPDA_PREG_252_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_252_IE_REG_ADDR (0x0004FC00u)
#define CSL_DFE_DPDA_DPDA_PREG_252_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_252_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_252_q : 23;
#else 
    Uint32 dpda_preg_252_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_252_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_252_Q_REG_DPDA_PREG_252_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_252_Q_REG_DPDA_PREG_252_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_252_Q_REG_DPDA_PREG_252_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_252_Q_REG_ADDR (0x0004FC04u)
#define CSL_DFE_DPDA_DPDA_PREG_252_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_253_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_253_ie : 31;
#else 
    Uint32 dpda_preg_253_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_253_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_253_IE_REG_DPDA_PREG_253_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_253_IE_REG_DPDA_PREG_253_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_253_IE_REG_DPDA_PREG_253_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_253_IE_REG_ADDR (0x0004FD00u)
#define CSL_DFE_DPDA_DPDA_PREG_253_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_253_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_253_q : 23;
#else 
    Uint32 dpda_preg_253_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_253_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_253_Q_REG_DPDA_PREG_253_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_253_Q_REG_DPDA_PREG_253_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_253_Q_REG_DPDA_PREG_253_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_253_Q_REG_ADDR (0x0004FD04u)
#define CSL_DFE_DPDA_DPDA_PREG_253_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_254_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_254_ie : 31;
#else 
    Uint32 dpda_preg_254_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_254_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_254_IE_REG_DPDA_PREG_254_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_254_IE_REG_DPDA_PREG_254_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_254_IE_REG_DPDA_PREG_254_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_254_IE_REG_ADDR (0x0004FE00u)
#define CSL_DFE_DPDA_DPDA_PREG_254_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_254_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_254_q : 23;
#else 
    Uint32 dpda_preg_254_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_254_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_254_Q_REG_DPDA_PREG_254_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_254_Q_REG_DPDA_PREG_254_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_254_Q_REG_DPDA_PREG_254_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_254_Q_REG_ADDR (0x0004FE04u)
#define CSL_DFE_DPDA_DPDA_PREG_254_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_255_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_255_ie : 31;
#else 
    Uint32 dpda_preg_255_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_255_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_255_IE_REG_DPDA_PREG_255_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_255_IE_REG_DPDA_PREG_255_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_255_IE_REG_DPDA_PREG_255_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_255_IE_REG_ADDR (0x0004FF00u)
#define CSL_DFE_DPDA_DPDA_PREG_255_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_255_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_255_q : 23;
#else 
    Uint32 dpda_preg_255_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_255_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_255_Q_REG_DPDA_PREG_255_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_255_Q_REG_DPDA_PREG_255_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_255_Q_REG_DPDA_PREG_255_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_255_Q_REG_ADDR (0x0004FF04u)
#define CSL_DFE_DPDA_DPDA_PREG_255_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_256_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_256_ie : 31;
#else 
    Uint32 dpda_preg_256_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_256_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_256_IE_REG_DPDA_PREG_256_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_256_IE_REG_DPDA_PREG_256_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_256_IE_REG_DPDA_PREG_256_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_256_IE_REG_ADDR (0x00050000u)
#define CSL_DFE_DPDA_DPDA_PREG_256_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_256_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_256_q : 23;
#else 
    Uint32 dpda_preg_256_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_256_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_256_Q_REG_DPDA_PREG_256_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_256_Q_REG_DPDA_PREG_256_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_256_Q_REG_DPDA_PREG_256_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_256_Q_REG_ADDR (0x00050004u)
#define CSL_DFE_DPDA_DPDA_PREG_256_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_257_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_257_ie : 31;
#else 
    Uint32 dpda_preg_257_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_257_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_257_IE_REG_DPDA_PREG_257_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_257_IE_REG_DPDA_PREG_257_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_257_IE_REG_DPDA_PREG_257_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_257_IE_REG_ADDR (0x00050100u)
#define CSL_DFE_DPDA_DPDA_PREG_257_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_257_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_257_q : 23;
#else 
    Uint32 dpda_preg_257_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_257_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_257_Q_REG_DPDA_PREG_257_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_257_Q_REG_DPDA_PREG_257_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_257_Q_REG_DPDA_PREG_257_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_257_Q_REG_ADDR (0x00050104u)
#define CSL_DFE_DPDA_DPDA_PREG_257_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_258_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_258_ie : 31;
#else 
    Uint32 dpda_preg_258_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_258_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_258_IE_REG_DPDA_PREG_258_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_258_IE_REG_DPDA_PREG_258_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_258_IE_REG_DPDA_PREG_258_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_258_IE_REG_ADDR (0x00050200u)
#define CSL_DFE_DPDA_DPDA_PREG_258_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_258_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_258_q : 23;
#else 
    Uint32 dpda_preg_258_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_258_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_258_Q_REG_DPDA_PREG_258_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_258_Q_REG_DPDA_PREG_258_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_258_Q_REG_DPDA_PREG_258_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_258_Q_REG_ADDR (0x00050204u)
#define CSL_DFE_DPDA_DPDA_PREG_258_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_259_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_259_ie : 31;
#else 
    Uint32 dpda_preg_259_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_259_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_259_IE_REG_DPDA_PREG_259_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_259_IE_REG_DPDA_PREG_259_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_259_IE_REG_DPDA_PREG_259_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_259_IE_REG_ADDR (0x00050300u)
#define CSL_DFE_DPDA_DPDA_PREG_259_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_259_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_259_q : 23;
#else 
    Uint32 dpda_preg_259_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_259_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_259_Q_REG_DPDA_PREG_259_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_259_Q_REG_DPDA_PREG_259_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_259_Q_REG_DPDA_PREG_259_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_259_Q_REG_ADDR (0x00050304u)
#define CSL_DFE_DPDA_DPDA_PREG_259_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_260_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_260_ie : 31;
#else 
    Uint32 dpda_preg_260_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_260_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_260_IE_REG_DPDA_PREG_260_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_260_IE_REG_DPDA_PREG_260_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_260_IE_REG_DPDA_PREG_260_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_260_IE_REG_ADDR (0x00050400u)
#define CSL_DFE_DPDA_DPDA_PREG_260_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_260_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_260_q : 23;
#else 
    Uint32 dpda_preg_260_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_260_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_260_Q_REG_DPDA_PREG_260_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_260_Q_REG_DPDA_PREG_260_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_260_Q_REG_DPDA_PREG_260_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_260_Q_REG_ADDR (0x00050404u)
#define CSL_DFE_DPDA_DPDA_PREG_260_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_261_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_261_ie : 31;
#else 
    Uint32 dpda_preg_261_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_261_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_261_IE_REG_DPDA_PREG_261_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_261_IE_REG_DPDA_PREG_261_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_261_IE_REG_DPDA_PREG_261_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_261_IE_REG_ADDR (0x00050500u)
#define CSL_DFE_DPDA_DPDA_PREG_261_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_261_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_261_q : 23;
#else 
    Uint32 dpda_preg_261_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_261_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_261_Q_REG_DPDA_PREG_261_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_261_Q_REG_DPDA_PREG_261_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_261_Q_REG_DPDA_PREG_261_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_261_Q_REG_ADDR (0x00050504u)
#define CSL_DFE_DPDA_DPDA_PREG_261_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_262_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_262_ie : 31;
#else 
    Uint32 dpda_preg_262_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_262_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_262_IE_REG_DPDA_PREG_262_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_262_IE_REG_DPDA_PREG_262_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_262_IE_REG_DPDA_PREG_262_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_262_IE_REG_ADDR (0x00050600u)
#define CSL_DFE_DPDA_DPDA_PREG_262_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_262_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_262_q : 23;
#else 
    Uint32 dpda_preg_262_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_262_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_262_Q_REG_DPDA_PREG_262_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_262_Q_REG_DPDA_PREG_262_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_262_Q_REG_DPDA_PREG_262_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_262_Q_REG_ADDR (0x00050604u)
#define CSL_DFE_DPDA_DPDA_PREG_262_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_263_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_263_ie : 31;
#else 
    Uint32 dpda_preg_263_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_263_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_263_IE_REG_DPDA_PREG_263_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_263_IE_REG_DPDA_PREG_263_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_263_IE_REG_DPDA_PREG_263_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_263_IE_REG_ADDR (0x00050700u)
#define CSL_DFE_DPDA_DPDA_PREG_263_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_263_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_263_q : 23;
#else 
    Uint32 dpda_preg_263_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_263_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_263_Q_REG_DPDA_PREG_263_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_263_Q_REG_DPDA_PREG_263_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_263_Q_REG_DPDA_PREG_263_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_263_Q_REG_ADDR (0x00050704u)
#define CSL_DFE_DPDA_DPDA_PREG_263_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_264_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_264_ie : 31;
#else 
    Uint32 dpda_preg_264_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_264_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_264_IE_REG_DPDA_PREG_264_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_264_IE_REG_DPDA_PREG_264_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_264_IE_REG_DPDA_PREG_264_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_264_IE_REG_ADDR (0x00050800u)
#define CSL_DFE_DPDA_DPDA_PREG_264_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_264_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_264_q : 23;
#else 
    Uint32 dpda_preg_264_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_264_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_264_Q_REG_DPDA_PREG_264_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_264_Q_REG_DPDA_PREG_264_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_264_Q_REG_DPDA_PREG_264_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_264_Q_REG_ADDR (0x00050804u)
#define CSL_DFE_DPDA_DPDA_PREG_264_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_265_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_265_ie : 31;
#else 
    Uint32 dpda_preg_265_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_265_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_265_IE_REG_DPDA_PREG_265_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_265_IE_REG_DPDA_PREG_265_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_265_IE_REG_DPDA_PREG_265_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_265_IE_REG_ADDR (0x00050900u)
#define CSL_DFE_DPDA_DPDA_PREG_265_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_265_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_265_q : 23;
#else 
    Uint32 dpda_preg_265_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_265_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_265_Q_REG_DPDA_PREG_265_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_265_Q_REG_DPDA_PREG_265_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_265_Q_REG_DPDA_PREG_265_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_265_Q_REG_ADDR (0x00050904u)
#define CSL_DFE_DPDA_DPDA_PREG_265_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_266_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_266_ie : 31;
#else 
    Uint32 dpda_preg_266_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_266_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_266_IE_REG_DPDA_PREG_266_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_266_IE_REG_DPDA_PREG_266_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_266_IE_REG_DPDA_PREG_266_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_266_IE_REG_ADDR (0x00050A00u)
#define CSL_DFE_DPDA_DPDA_PREG_266_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_266_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_266_q : 23;
#else 
    Uint32 dpda_preg_266_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_266_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_266_Q_REG_DPDA_PREG_266_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_266_Q_REG_DPDA_PREG_266_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_266_Q_REG_DPDA_PREG_266_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_266_Q_REG_ADDR (0x00050A04u)
#define CSL_DFE_DPDA_DPDA_PREG_266_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_267_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_267_ie : 31;
#else 
    Uint32 dpda_preg_267_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_267_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_267_IE_REG_DPDA_PREG_267_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_267_IE_REG_DPDA_PREG_267_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_267_IE_REG_DPDA_PREG_267_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_267_IE_REG_ADDR (0x00050B00u)
#define CSL_DFE_DPDA_DPDA_PREG_267_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_267_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_267_q : 23;
#else 
    Uint32 dpda_preg_267_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_267_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_267_Q_REG_DPDA_PREG_267_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_267_Q_REG_DPDA_PREG_267_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_267_Q_REG_DPDA_PREG_267_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_267_Q_REG_ADDR (0x00050B04u)
#define CSL_DFE_DPDA_DPDA_PREG_267_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_268_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_268_ie : 31;
#else 
    Uint32 dpda_preg_268_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_268_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_268_IE_REG_DPDA_PREG_268_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_268_IE_REG_DPDA_PREG_268_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_268_IE_REG_DPDA_PREG_268_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_268_IE_REG_ADDR (0x00050C00u)
#define CSL_DFE_DPDA_DPDA_PREG_268_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_268_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_268_q : 23;
#else 
    Uint32 dpda_preg_268_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_268_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_268_Q_REG_DPDA_PREG_268_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_268_Q_REG_DPDA_PREG_268_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_268_Q_REG_DPDA_PREG_268_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_268_Q_REG_ADDR (0x00050C04u)
#define CSL_DFE_DPDA_DPDA_PREG_268_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_269_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_269_ie : 31;
#else 
    Uint32 dpda_preg_269_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_269_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_269_IE_REG_DPDA_PREG_269_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_269_IE_REG_DPDA_PREG_269_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_269_IE_REG_DPDA_PREG_269_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_269_IE_REG_ADDR (0x00050D00u)
#define CSL_DFE_DPDA_DPDA_PREG_269_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_269_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_269_q : 23;
#else 
    Uint32 dpda_preg_269_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_269_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_269_Q_REG_DPDA_PREG_269_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_269_Q_REG_DPDA_PREG_269_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_269_Q_REG_DPDA_PREG_269_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_269_Q_REG_ADDR (0x00050D04u)
#define CSL_DFE_DPDA_DPDA_PREG_269_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_270_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_270_ie : 31;
#else 
    Uint32 dpda_preg_270_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_270_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_270_IE_REG_DPDA_PREG_270_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_270_IE_REG_DPDA_PREG_270_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_270_IE_REG_DPDA_PREG_270_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_270_IE_REG_ADDR (0x00050E00u)
#define CSL_DFE_DPDA_DPDA_PREG_270_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_270_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_270_q : 23;
#else 
    Uint32 dpda_preg_270_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_270_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_270_Q_REG_DPDA_PREG_270_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_270_Q_REG_DPDA_PREG_270_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_270_Q_REG_DPDA_PREG_270_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_270_Q_REG_ADDR (0x00050E04u)
#define CSL_DFE_DPDA_DPDA_PREG_270_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_271_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_271_ie : 31;
#else 
    Uint32 dpda_preg_271_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_271_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_271_IE_REG_DPDA_PREG_271_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_271_IE_REG_DPDA_PREG_271_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_271_IE_REG_DPDA_PREG_271_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_271_IE_REG_ADDR (0x00050F00u)
#define CSL_DFE_DPDA_DPDA_PREG_271_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_271_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_271_q : 23;
#else 
    Uint32 dpda_preg_271_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_271_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_271_Q_REG_DPDA_PREG_271_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_271_Q_REG_DPDA_PREG_271_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_271_Q_REG_DPDA_PREG_271_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_271_Q_REG_ADDR (0x00050F04u)
#define CSL_DFE_DPDA_DPDA_PREG_271_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_272_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_272_ie : 31;
#else 
    Uint32 dpda_preg_272_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_272_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_272_IE_REG_DPDA_PREG_272_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_272_IE_REG_DPDA_PREG_272_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_272_IE_REG_DPDA_PREG_272_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_272_IE_REG_ADDR (0x00051000u)
#define CSL_DFE_DPDA_DPDA_PREG_272_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_272_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_272_q : 23;
#else 
    Uint32 dpda_preg_272_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_272_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_272_Q_REG_DPDA_PREG_272_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_272_Q_REG_DPDA_PREG_272_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_272_Q_REG_DPDA_PREG_272_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_272_Q_REG_ADDR (0x00051004u)
#define CSL_DFE_DPDA_DPDA_PREG_272_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_273_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_273_ie : 31;
#else 
    Uint32 dpda_preg_273_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_273_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_273_IE_REG_DPDA_PREG_273_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_273_IE_REG_DPDA_PREG_273_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_273_IE_REG_DPDA_PREG_273_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_273_IE_REG_ADDR (0x00051100u)
#define CSL_DFE_DPDA_DPDA_PREG_273_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_273_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_273_q : 23;
#else 
    Uint32 dpda_preg_273_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_273_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_273_Q_REG_DPDA_PREG_273_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_273_Q_REG_DPDA_PREG_273_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_273_Q_REG_DPDA_PREG_273_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_273_Q_REG_ADDR (0x00051104u)
#define CSL_DFE_DPDA_DPDA_PREG_273_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_274_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_274_ie : 31;
#else 
    Uint32 dpda_preg_274_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_274_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_274_IE_REG_DPDA_PREG_274_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_274_IE_REG_DPDA_PREG_274_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_274_IE_REG_DPDA_PREG_274_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_274_IE_REG_ADDR (0x00051200u)
#define CSL_DFE_DPDA_DPDA_PREG_274_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_274_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_274_q : 23;
#else 
    Uint32 dpda_preg_274_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_274_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_274_Q_REG_DPDA_PREG_274_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_274_Q_REG_DPDA_PREG_274_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_274_Q_REG_DPDA_PREG_274_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_274_Q_REG_ADDR (0x00051204u)
#define CSL_DFE_DPDA_DPDA_PREG_274_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_275_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_275_ie : 31;
#else 
    Uint32 dpda_preg_275_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_275_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_275_IE_REG_DPDA_PREG_275_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_275_IE_REG_DPDA_PREG_275_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_275_IE_REG_DPDA_PREG_275_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_275_IE_REG_ADDR (0x00051300u)
#define CSL_DFE_DPDA_DPDA_PREG_275_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_275_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_275_q : 23;
#else 
    Uint32 dpda_preg_275_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_275_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_275_Q_REG_DPDA_PREG_275_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_275_Q_REG_DPDA_PREG_275_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_275_Q_REG_DPDA_PREG_275_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_275_Q_REG_ADDR (0x00051304u)
#define CSL_DFE_DPDA_DPDA_PREG_275_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_276_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_276_ie : 31;
#else 
    Uint32 dpda_preg_276_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_276_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_276_IE_REG_DPDA_PREG_276_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_276_IE_REG_DPDA_PREG_276_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_276_IE_REG_DPDA_PREG_276_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_276_IE_REG_ADDR (0x00051400u)
#define CSL_DFE_DPDA_DPDA_PREG_276_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_276_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_276_q : 23;
#else 
    Uint32 dpda_preg_276_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_276_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_276_Q_REG_DPDA_PREG_276_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_276_Q_REG_DPDA_PREG_276_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_276_Q_REG_DPDA_PREG_276_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_276_Q_REG_ADDR (0x00051404u)
#define CSL_DFE_DPDA_DPDA_PREG_276_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_277_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_277_ie : 31;
#else 
    Uint32 dpda_preg_277_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_277_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_277_IE_REG_DPDA_PREG_277_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_277_IE_REG_DPDA_PREG_277_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_277_IE_REG_DPDA_PREG_277_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_277_IE_REG_ADDR (0x00051500u)
#define CSL_DFE_DPDA_DPDA_PREG_277_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_277_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_277_q : 23;
#else 
    Uint32 dpda_preg_277_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_277_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_277_Q_REG_DPDA_PREG_277_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_277_Q_REG_DPDA_PREG_277_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_277_Q_REG_DPDA_PREG_277_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_277_Q_REG_ADDR (0x00051504u)
#define CSL_DFE_DPDA_DPDA_PREG_277_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_278_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_278_ie : 31;
#else 
    Uint32 dpda_preg_278_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_278_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_278_IE_REG_DPDA_PREG_278_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_278_IE_REG_DPDA_PREG_278_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_278_IE_REG_DPDA_PREG_278_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_278_IE_REG_ADDR (0x00051600u)
#define CSL_DFE_DPDA_DPDA_PREG_278_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_278_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_278_q : 23;
#else 
    Uint32 dpda_preg_278_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_278_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_278_Q_REG_DPDA_PREG_278_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_278_Q_REG_DPDA_PREG_278_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_278_Q_REG_DPDA_PREG_278_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_278_Q_REG_ADDR (0x00051604u)
#define CSL_DFE_DPDA_DPDA_PREG_278_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_279_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_279_ie : 31;
#else 
    Uint32 dpda_preg_279_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_279_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_279_IE_REG_DPDA_PREG_279_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_279_IE_REG_DPDA_PREG_279_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_279_IE_REG_DPDA_PREG_279_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_279_IE_REG_ADDR (0x00051700u)
#define CSL_DFE_DPDA_DPDA_PREG_279_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_279_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_279_q : 23;
#else 
    Uint32 dpda_preg_279_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_279_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_279_Q_REG_DPDA_PREG_279_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_279_Q_REG_DPDA_PREG_279_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_279_Q_REG_DPDA_PREG_279_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_279_Q_REG_ADDR (0x00051704u)
#define CSL_DFE_DPDA_DPDA_PREG_279_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_280_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_280_ie : 31;
#else 
    Uint32 dpda_preg_280_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_280_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_280_IE_REG_DPDA_PREG_280_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_280_IE_REG_DPDA_PREG_280_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_280_IE_REG_DPDA_PREG_280_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_280_IE_REG_ADDR (0x00051800u)
#define CSL_DFE_DPDA_DPDA_PREG_280_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_280_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_280_q : 23;
#else 
    Uint32 dpda_preg_280_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_280_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_280_Q_REG_DPDA_PREG_280_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_280_Q_REG_DPDA_PREG_280_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_280_Q_REG_DPDA_PREG_280_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_280_Q_REG_ADDR (0x00051804u)
#define CSL_DFE_DPDA_DPDA_PREG_280_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_281_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_281_ie : 31;
#else 
    Uint32 dpda_preg_281_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_281_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_281_IE_REG_DPDA_PREG_281_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_281_IE_REG_DPDA_PREG_281_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_281_IE_REG_DPDA_PREG_281_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_281_IE_REG_ADDR (0x00051900u)
#define CSL_DFE_DPDA_DPDA_PREG_281_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_281_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_281_q : 23;
#else 
    Uint32 dpda_preg_281_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_281_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_281_Q_REG_DPDA_PREG_281_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_281_Q_REG_DPDA_PREG_281_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_281_Q_REG_DPDA_PREG_281_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_281_Q_REG_ADDR (0x00051904u)
#define CSL_DFE_DPDA_DPDA_PREG_281_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_282_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_282_ie : 31;
#else 
    Uint32 dpda_preg_282_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_282_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_282_IE_REG_DPDA_PREG_282_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_282_IE_REG_DPDA_PREG_282_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_282_IE_REG_DPDA_PREG_282_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_282_IE_REG_ADDR (0x00051A00u)
#define CSL_DFE_DPDA_DPDA_PREG_282_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_282_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_282_q : 23;
#else 
    Uint32 dpda_preg_282_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_282_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_282_Q_REG_DPDA_PREG_282_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_282_Q_REG_DPDA_PREG_282_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_282_Q_REG_DPDA_PREG_282_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_282_Q_REG_ADDR (0x00051A04u)
#define CSL_DFE_DPDA_DPDA_PREG_282_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_283_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_283_ie : 31;
#else 
    Uint32 dpda_preg_283_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_283_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_283_IE_REG_DPDA_PREG_283_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_283_IE_REG_DPDA_PREG_283_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_283_IE_REG_DPDA_PREG_283_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_283_IE_REG_ADDR (0x00051B00u)
#define CSL_DFE_DPDA_DPDA_PREG_283_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_283_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_283_q : 23;
#else 
    Uint32 dpda_preg_283_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_283_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_283_Q_REG_DPDA_PREG_283_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_283_Q_REG_DPDA_PREG_283_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_283_Q_REG_DPDA_PREG_283_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_283_Q_REG_ADDR (0x00051B04u)
#define CSL_DFE_DPDA_DPDA_PREG_283_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_284_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_284_ie : 31;
#else 
    Uint32 dpda_preg_284_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_284_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_284_IE_REG_DPDA_PREG_284_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_284_IE_REG_DPDA_PREG_284_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_284_IE_REG_DPDA_PREG_284_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_284_IE_REG_ADDR (0x00051C00u)
#define CSL_DFE_DPDA_DPDA_PREG_284_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_284_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_284_q : 23;
#else 
    Uint32 dpda_preg_284_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_284_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_284_Q_REG_DPDA_PREG_284_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_284_Q_REG_DPDA_PREG_284_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_284_Q_REG_DPDA_PREG_284_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_284_Q_REG_ADDR (0x00051C04u)
#define CSL_DFE_DPDA_DPDA_PREG_284_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_285_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_285_ie : 31;
#else 
    Uint32 dpda_preg_285_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_285_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_285_IE_REG_DPDA_PREG_285_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_285_IE_REG_DPDA_PREG_285_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_285_IE_REG_DPDA_PREG_285_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_285_IE_REG_ADDR (0x00051D00u)
#define CSL_DFE_DPDA_DPDA_PREG_285_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_285_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_285_q : 23;
#else 
    Uint32 dpda_preg_285_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_285_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_285_Q_REG_DPDA_PREG_285_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_285_Q_REG_DPDA_PREG_285_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_285_Q_REG_DPDA_PREG_285_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_285_Q_REG_ADDR (0x00051D04u)
#define CSL_DFE_DPDA_DPDA_PREG_285_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_286_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_286_ie : 31;
#else 
    Uint32 dpda_preg_286_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_286_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_286_IE_REG_DPDA_PREG_286_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_286_IE_REG_DPDA_PREG_286_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_286_IE_REG_DPDA_PREG_286_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_286_IE_REG_ADDR (0x00051E00u)
#define CSL_DFE_DPDA_DPDA_PREG_286_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_286_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_286_q : 23;
#else 
    Uint32 dpda_preg_286_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_286_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_286_Q_REG_DPDA_PREG_286_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_286_Q_REG_DPDA_PREG_286_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_286_Q_REG_DPDA_PREG_286_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_286_Q_REG_ADDR (0x00051E04u)
#define CSL_DFE_DPDA_DPDA_PREG_286_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_287_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_287_ie : 31;
#else 
    Uint32 dpda_preg_287_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_287_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_287_IE_REG_DPDA_PREG_287_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_287_IE_REG_DPDA_PREG_287_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_287_IE_REG_DPDA_PREG_287_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_287_IE_REG_ADDR (0x00051F00u)
#define CSL_DFE_DPDA_DPDA_PREG_287_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_287_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_287_q : 23;
#else 
    Uint32 dpda_preg_287_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_287_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_287_Q_REG_DPDA_PREG_287_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_287_Q_REG_DPDA_PREG_287_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_287_Q_REG_DPDA_PREG_287_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_287_Q_REG_ADDR (0x00051F04u)
#define CSL_DFE_DPDA_DPDA_PREG_287_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_288_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_288_ie : 31;
#else 
    Uint32 dpda_preg_288_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_288_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_288_IE_REG_DPDA_PREG_288_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_288_IE_REG_DPDA_PREG_288_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_288_IE_REG_DPDA_PREG_288_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_288_IE_REG_ADDR (0x00052000u)
#define CSL_DFE_DPDA_DPDA_PREG_288_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_288_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_288_q : 23;
#else 
    Uint32 dpda_preg_288_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_288_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_288_Q_REG_DPDA_PREG_288_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_288_Q_REG_DPDA_PREG_288_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_288_Q_REG_DPDA_PREG_288_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_288_Q_REG_ADDR (0x00052004u)
#define CSL_DFE_DPDA_DPDA_PREG_288_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_289_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_289_ie : 31;
#else 
    Uint32 dpda_preg_289_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_289_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_289_IE_REG_DPDA_PREG_289_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_289_IE_REG_DPDA_PREG_289_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_289_IE_REG_DPDA_PREG_289_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_289_IE_REG_ADDR (0x00052100u)
#define CSL_DFE_DPDA_DPDA_PREG_289_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_289_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_289_q : 23;
#else 
    Uint32 dpda_preg_289_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_289_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_289_Q_REG_DPDA_PREG_289_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_289_Q_REG_DPDA_PREG_289_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_289_Q_REG_DPDA_PREG_289_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_289_Q_REG_ADDR (0x00052104u)
#define CSL_DFE_DPDA_DPDA_PREG_289_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_290_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_290_ie : 31;
#else 
    Uint32 dpda_preg_290_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_290_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_290_IE_REG_DPDA_PREG_290_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_290_IE_REG_DPDA_PREG_290_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_290_IE_REG_DPDA_PREG_290_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_290_IE_REG_ADDR (0x00052200u)
#define CSL_DFE_DPDA_DPDA_PREG_290_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_290_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_290_q : 23;
#else 
    Uint32 dpda_preg_290_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_290_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_290_Q_REG_DPDA_PREG_290_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_290_Q_REG_DPDA_PREG_290_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_290_Q_REG_DPDA_PREG_290_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_290_Q_REG_ADDR (0x00052204u)
#define CSL_DFE_DPDA_DPDA_PREG_290_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_291_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_291_ie : 31;
#else 
    Uint32 dpda_preg_291_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_291_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_291_IE_REG_DPDA_PREG_291_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_291_IE_REG_DPDA_PREG_291_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_291_IE_REG_DPDA_PREG_291_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_291_IE_REG_ADDR (0x00052300u)
#define CSL_DFE_DPDA_DPDA_PREG_291_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_291_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_291_q : 23;
#else 
    Uint32 dpda_preg_291_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_291_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_291_Q_REG_DPDA_PREG_291_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_291_Q_REG_DPDA_PREG_291_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_291_Q_REG_DPDA_PREG_291_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_291_Q_REG_ADDR (0x00052304u)
#define CSL_DFE_DPDA_DPDA_PREG_291_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_292_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_292_ie : 31;
#else 
    Uint32 dpda_preg_292_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_292_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_292_IE_REG_DPDA_PREG_292_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_292_IE_REG_DPDA_PREG_292_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_292_IE_REG_DPDA_PREG_292_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_292_IE_REG_ADDR (0x00052400u)
#define CSL_DFE_DPDA_DPDA_PREG_292_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_292_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_292_q : 23;
#else 
    Uint32 dpda_preg_292_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_292_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_292_Q_REG_DPDA_PREG_292_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_292_Q_REG_DPDA_PREG_292_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_292_Q_REG_DPDA_PREG_292_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_292_Q_REG_ADDR (0x00052404u)
#define CSL_DFE_DPDA_DPDA_PREG_292_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_293_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_293_ie : 31;
#else 
    Uint32 dpda_preg_293_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_293_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_293_IE_REG_DPDA_PREG_293_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_293_IE_REG_DPDA_PREG_293_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_293_IE_REG_DPDA_PREG_293_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_293_IE_REG_ADDR (0x00052500u)
#define CSL_DFE_DPDA_DPDA_PREG_293_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_293_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_293_q : 23;
#else 
    Uint32 dpda_preg_293_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_293_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_293_Q_REG_DPDA_PREG_293_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_293_Q_REG_DPDA_PREG_293_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_293_Q_REG_DPDA_PREG_293_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_293_Q_REG_ADDR (0x00052504u)
#define CSL_DFE_DPDA_DPDA_PREG_293_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_294_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_294_ie : 31;
#else 
    Uint32 dpda_preg_294_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_294_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_294_IE_REG_DPDA_PREG_294_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_294_IE_REG_DPDA_PREG_294_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_294_IE_REG_DPDA_PREG_294_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_294_IE_REG_ADDR (0x00052600u)
#define CSL_DFE_DPDA_DPDA_PREG_294_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_294_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_294_q : 23;
#else 
    Uint32 dpda_preg_294_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_294_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_294_Q_REG_DPDA_PREG_294_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_294_Q_REG_DPDA_PREG_294_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_294_Q_REG_DPDA_PREG_294_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_294_Q_REG_ADDR (0x00052604u)
#define CSL_DFE_DPDA_DPDA_PREG_294_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_295_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_295_ie : 31;
#else 
    Uint32 dpda_preg_295_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_295_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_295_IE_REG_DPDA_PREG_295_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_295_IE_REG_DPDA_PREG_295_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_295_IE_REG_DPDA_PREG_295_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_295_IE_REG_ADDR (0x00052700u)
#define CSL_DFE_DPDA_DPDA_PREG_295_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_295_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_295_q : 23;
#else 
    Uint32 dpda_preg_295_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_295_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_295_Q_REG_DPDA_PREG_295_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_295_Q_REG_DPDA_PREG_295_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_295_Q_REG_DPDA_PREG_295_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_295_Q_REG_ADDR (0x00052704u)
#define CSL_DFE_DPDA_DPDA_PREG_295_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_296_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_296_ie : 31;
#else 
    Uint32 dpda_preg_296_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_296_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_296_IE_REG_DPDA_PREG_296_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_296_IE_REG_DPDA_PREG_296_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_296_IE_REG_DPDA_PREG_296_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_296_IE_REG_ADDR (0x00052800u)
#define CSL_DFE_DPDA_DPDA_PREG_296_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_296_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_296_q : 23;
#else 
    Uint32 dpda_preg_296_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_296_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_296_Q_REG_DPDA_PREG_296_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_296_Q_REG_DPDA_PREG_296_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_296_Q_REG_DPDA_PREG_296_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_296_Q_REG_ADDR (0x00052804u)
#define CSL_DFE_DPDA_DPDA_PREG_296_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_297_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_297_ie : 31;
#else 
    Uint32 dpda_preg_297_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_297_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_297_IE_REG_DPDA_PREG_297_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_297_IE_REG_DPDA_PREG_297_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_297_IE_REG_DPDA_PREG_297_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_297_IE_REG_ADDR (0x00052900u)
#define CSL_DFE_DPDA_DPDA_PREG_297_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_297_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_297_q : 23;
#else 
    Uint32 dpda_preg_297_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_297_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_297_Q_REG_DPDA_PREG_297_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_297_Q_REG_DPDA_PREG_297_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_297_Q_REG_DPDA_PREG_297_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_297_Q_REG_ADDR (0x00052904u)
#define CSL_DFE_DPDA_DPDA_PREG_297_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_298_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_298_ie : 31;
#else 
    Uint32 dpda_preg_298_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_298_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_298_IE_REG_DPDA_PREG_298_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_298_IE_REG_DPDA_PREG_298_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_298_IE_REG_DPDA_PREG_298_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_298_IE_REG_ADDR (0x00052A00u)
#define CSL_DFE_DPDA_DPDA_PREG_298_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_298_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_298_q : 23;
#else 
    Uint32 dpda_preg_298_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_298_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_298_Q_REG_DPDA_PREG_298_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_298_Q_REG_DPDA_PREG_298_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_298_Q_REG_DPDA_PREG_298_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_298_Q_REG_ADDR (0x00052A04u)
#define CSL_DFE_DPDA_DPDA_PREG_298_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_299_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_299_ie : 31;
#else 
    Uint32 dpda_preg_299_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_299_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_299_IE_REG_DPDA_PREG_299_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_299_IE_REG_DPDA_PREG_299_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_299_IE_REG_DPDA_PREG_299_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_299_IE_REG_ADDR (0x00052B00u)
#define CSL_DFE_DPDA_DPDA_PREG_299_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_299_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_299_q : 23;
#else 
    Uint32 dpda_preg_299_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_299_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_299_Q_REG_DPDA_PREG_299_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_299_Q_REG_DPDA_PREG_299_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_299_Q_REG_DPDA_PREG_299_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_299_Q_REG_ADDR (0x00052B04u)
#define CSL_DFE_DPDA_DPDA_PREG_299_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_300_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_300_ie : 31;
#else 
    Uint32 dpda_preg_300_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_300_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_300_IE_REG_DPDA_PREG_300_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_300_IE_REG_DPDA_PREG_300_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_300_IE_REG_DPDA_PREG_300_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_300_IE_REG_ADDR (0x00052C00u)
#define CSL_DFE_DPDA_DPDA_PREG_300_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_300_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_300_q : 23;
#else 
    Uint32 dpda_preg_300_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_300_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_300_Q_REG_DPDA_PREG_300_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_300_Q_REG_DPDA_PREG_300_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_300_Q_REG_DPDA_PREG_300_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_300_Q_REG_ADDR (0x00052C04u)
#define CSL_DFE_DPDA_DPDA_PREG_300_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_301_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_301_ie : 31;
#else 
    Uint32 dpda_preg_301_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_301_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_301_IE_REG_DPDA_PREG_301_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_301_IE_REG_DPDA_PREG_301_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_301_IE_REG_DPDA_PREG_301_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_301_IE_REG_ADDR (0x00052D00u)
#define CSL_DFE_DPDA_DPDA_PREG_301_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_301_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_301_q : 23;
#else 
    Uint32 dpda_preg_301_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_301_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_301_Q_REG_DPDA_PREG_301_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_301_Q_REG_DPDA_PREG_301_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_301_Q_REG_DPDA_PREG_301_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_301_Q_REG_ADDR (0x00052D04u)
#define CSL_DFE_DPDA_DPDA_PREG_301_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_302_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_302_ie : 31;
#else 
    Uint32 dpda_preg_302_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_302_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_302_IE_REG_DPDA_PREG_302_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_302_IE_REG_DPDA_PREG_302_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_302_IE_REG_DPDA_PREG_302_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_302_IE_REG_ADDR (0x00052E00u)
#define CSL_DFE_DPDA_DPDA_PREG_302_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_302_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_302_q : 23;
#else 
    Uint32 dpda_preg_302_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_302_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_302_Q_REG_DPDA_PREG_302_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_302_Q_REG_DPDA_PREG_302_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_302_Q_REG_DPDA_PREG_302_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_302_Q_REG_ADDR (0x00052E04u)
#define CSL_DFE_DPDA_DPDA_PREG_302_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_303_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_303_ie : 31;
#else 
    Uint32 dpda_preg_303_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_303_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_303_IE_REG_DPDA_PREG_303_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_303_IE_REG_DPDA_PREG_303_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_303_IE_REG_DPDA_PREG_303_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_303_IE_REG_ADDR (0x00052F00u)
#define CSL_DFE_DPDA_DPDA_PREG_303_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_303_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_303_q : 23;
#else 
    Uint32 dpda_preg_303_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_303_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_303_Q_REG_DPDA_PREG_303_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_303_Q_REG_DPDA_PREG_303_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_303_Q_REG_DPDA_PREG_303_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_303_Q_REG_ADDR (0x00052F04u)
#define CSL_DFE_DPDA_DPDA_PREG_303_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_304_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_304_ie : 31;
#else 
    Uint32 dpda_preg_304_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_304_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_304_IE_REG_DPDA_PREG_304_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_304_IE_REG_DPDA_PREG_304_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_304_IE_REG_DPDA_PREG_304_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_304_IE_REG_ADDR (0x00053000u)
#define CSL_DFE_DPDA_DPDA_PREG_304_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_304_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_304_q : 23;
#else 
    Uint32 dpda_preg_304_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_304_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_304_Q_REG_DPDA_PREG_304_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_304_Q_REG_DPDA_PREG_304_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_304_Q_REG_DPDA_PREG_304_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_304_Q_REG_ADDR (0x00053004u)
#define CSL_DFE_DPDA_DPDA_PREG_304_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_305_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_305_ie : 31;
#else 
    Uint32 dpda_preg_305_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_305_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_305_IE_REG_DPDA_PREG_305_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_305_IE_REG_DPDA_PREG_305_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_305_IE_REG_DPDA_PREG_305_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_305_IE_REG_ADDR (0x00053100u)
#define CSL_DFE_DPDA_DPDA_PREG_305_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_305_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_305_q : 23;
#else 
    Uint32 dpda_preg_305_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_305_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_305_Q_REG_DPDA_PREG_305_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_305_Q_REG_DPDA_PREG_305_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_305_Q_REG_DPDA_PREG_305_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_305_Q_REG_ADDR (0x00053104u)
#define CSL_DFE_DPDA_DPDA_PREG_305_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_306_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_306_ie : 31;
#else 
    Uint32 dpda_preg_306_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_306_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_306_IE_REG_DPDA_PREG_306_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_306_IE_REG_DPDA_PREG_306_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_306_IE_REG_DPDA_PREG_306_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_306_IE_REG_ADDR (0x00053200u)
#define CSL_DFE_DPDA_DPDA_PREG_306_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_306_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_306_q : 23;
#else 
    Uint32 dpda_preg_306_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_306_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_306_Q_REG_DPDA_PREG_306_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_306_Q_REG_DPDA_PREG_306_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_306_Q_REG_DPDA_PREG_306_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_306_Q_REG_ADDR (0x00053204u)
#define CSL_DFE_DPDA_DPDA_PREG_306_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_307_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_307_ie : 31;
#else 
    Uint32 dpda_preg_307_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_307_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_307_IE_REG_DPDA_PREG_307_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_307_IE_REG_DPDA_PREG_307_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_307_IE_REG_DPDA_PREG_307_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_307_IE_REG_ADDR (0x00053300u)
#define CSL_DFE_DPDA_DPDA_PREG_307_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_307_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_307_q : 23;
#else 
    Uint32 dpda_preg_307_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_307_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_307_Q_REG_DPDA_PREG_307_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_307_Q_REG_DPDA_PREG_307_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_307_Q_REG_DPDA_PREG_307_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_307_Q_REG_ADDR (0x00053304u)
#define CSL_DFE_DPDA_DPDA_PREG_307_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_308_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_308_ie : 31;
#else 
    Uint32 dpda_preg_308_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_308_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_308_IE_REG_DPDA_PREG_308_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_308_IE_REG_DPDA_PREG_308_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_308_IE_REG_DPDA_PREG_308_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_308_IE_REG_ADDR (0x00053400u)
#define CSL_DFE_DPDA_DPDA_PREG_308_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_308_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_308_q : 23;
#else 
    Uint32 dpda_preg_308_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_308_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_308_Q_REG_DPDA_PREG_308_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_308_Q_REG_DPDA_PREG_308_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_308_Q_REG_DPDA_PREG_308_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_308_Q_REG_ADDR (0x00053404u)
#define CSL_DFE_DPDA_DPDA_PREG_308_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_309_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_309_ie : 31;
#else 
    Uint32 dpda_preg_309_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_309_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_309_IE_REG_DPDA_PREG_309_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_309_IE_REG_DPDA_PREG_309_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_309_IE_REG_DPDA_PREG_309_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_309_IE_REG_ADDR (0x00053500u)
#define CSL_DFE_DPDA_DPDA_PREG_309_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_309_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_309_q : 23;
#else 
    Uint32 dpda_preg_309_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_309_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_309_Q_REG_DPDA_PREG_309_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_309_Q_REG_DPDA_PREG_309_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_309_Q_REG_DPDA_PREG_309_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_309_Q_REG_ADDR (0x00053504u)
#define CSL_DFE_DPDA_DPDA_PREG_309_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_310_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_310_ie : 31;
#else 
    Uint32 dpda_preg_310_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_310_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_310_IE_REG_DPDA_PREG_310_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_310_IE_REG_DPDA_PREG_310_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_310_IE_REG_DPDA_PREG_310_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_310_IE_REG_ADDR (0x00053600u)
#define CSL_DFE_DPDA_DPDA_PREG_310_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_310_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_310_q : 23;
#else 
    Uint32 dpda_preg_310_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_310_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_310_Q_REG_DPDA_PREG_310_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_310_Q_REG_DPDA_PREG_310_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_310_Q_REG_DPDA_PREG_310_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_310_Q_REG_ADDR (0x00053604u)
#define CSL_DFE_DPDA_DPDA_PREG_310_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_311_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_311_ie : 31;
#else 
    Uint32 dpda_preg_311_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_311_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_311_IE_REG_DPDA_PREG_311_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_311_IE_REG_DPDA_PREG_311_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_311_IE_REG_DPDA_PREG_311_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_311_IE_REG_ADDR (0x00053700u)
#define CSL_DFE_DPDA_DPDA_PREG_311_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_311_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_311_q : 23;
#else 
    Uint32 dpda_preg_311_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_311_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_311_Q_REG_DPDA_PREG_311_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_311_Q_REG_DPDA_PREG_311_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_311_Q_REG_DPDA_PREG_311_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_311_Q_REG_ADDR (0x00053704u)
#define CSL_DFE_DPDA_DPDA_PREG_311_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_312_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_312_ie : 31;
#else 
    Uint32 dpda_preg_312_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_312_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_312_IE_REG_DPDA_PREG_312_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_312_IE_REG_DPDA_PREG_312_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_312_IE_REG_DPDA_PREG_312_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_312_IE_REG_ADDR (0x00053800u)
#define CSL_DFE_DPDA_DPDA_PREG_312_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_312_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_312_q : 23;
#else 
    Uint32 dpda_preg_312_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_312_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_312_Q_REG_DPDA_PREG_312_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_312_Q_REG_DPDA_PREG_312_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_312_Q_REG_DPDA_PREG_312_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_312_Q_REG_ADDR (0x00053804u)
#define CSL_DFE_DPDA_DPDA_PREG_312_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_313_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_313_ie : 31;
#else 
    Uint32 dpda_preg_313_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_313_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_313_IE_REG_DPDA_PREG_313_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_313_IE_REG_DPDA_PREG_313_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_313_IE_REG_DPDA_PREG_313_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_313_IE_REG_ADDR (0x00053900u)
#define CSL_DFE_DPDA_DPDA_PREG_313_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_313_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_313_q : 23;
#else 
    Uint32 dpda_preg_313_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_313_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_313_Q_REG_DPDA_PREG_313_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_313_Q_REG_DPDA_PREG_313_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_313_Q_REG_DPDA_PREG_313_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_313_Q_REG_ADDR (0x00053904u)
#define CSL_DFE_DPDA_DPDA_PREG_313_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_314_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_314_ie : 31;
#else 
    Uint32 dpda_preg_314_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_314_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_314_IE_REG_DPDA_PREG_314_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_314_IE_REG_DPDA_PREG_314_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_314_IE_REG_DPDA_PREG_314_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_314_IE_REG_ADDR (0x00053A00u)
#define CSL_DFE_DPDA_DPDA_PREG_314_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_314_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_314_q : 23;
#else 
    Uint32 dpda_preg_314_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_314_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_314_Q_REG_DPDA_PREG_314_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_314_Q_REG_DPDA_PREG_314_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_314_Q_REG_DPDA_PREG_314_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_314_Q_REG_ADDR (0x00053A04u)
#define CSL_DFE_DPDA_DPDA_PREG_314_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_315_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_315_ie : 31;
#else 
    Uint32 dpda_preg_315_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_315_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_315_IE_REG_DPDA_PREG_315_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_315_IE_REG_DPDA_PREG_315_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_315_IE_REG_DPDA_PREG_315_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_315_IE_REG_ADDR (0x00053B00u)
#define CSL_DFE_DPDA_DPDA_PREG_315_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_315_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_315_q : 23;
#else 
    Uint32 dpda_preg_315_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_315_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_315_Q_REG_DPDA_PREG_315_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_315_Q_REG_DPDA_PREG_315_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_315_Q_REG_DPDA_PREG_315_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_315_Q_REG_ADDR (0x00053B04u)
#define CSL_DFE_DPDA_DPDA_PREG_315_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_316_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_316_ie : 31;
#else 
    Uint32 dpda_preg_316_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_316_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_316_IE_REG_DPDA_PREG_316_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_316_IE_REG_DPDA_PREG_316_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_316_IE_REG_DPDA_PREG_316_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_316_IE_REG_ADDR (0x00053C00u)
#define CSL_DFE_DPDA_DPDA_PREG_316_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_316_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_316_q : 23;
#else 
    Uint32 dpda_preg_316_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_316_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_316_Q_REG_DPDA_PREG_316_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_316_Q_REG_DPDA_PREG_316_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_316_Q_REG_DPDA_PREG_316_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_316_Q_REG_ADDR (0x00053C04u)
#define CSL_DFE_DPDA_DPDA_PREG_316_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_317_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_317_ie : 31;
#else 
    Uint32 dpda_preg_317_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_317_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_317_IE_REG_DPDA_PREG_317_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_317_IE_REG_DPDA_PREG_317_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_317_IE_REG_DPDA_PREG_317_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_317_IE_REG_ADDR (0x00053D00u)
#define CSL_DFE_DPDA_DPDA_PREG_317_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_317_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_317_q : 23;
#else 
    Uint32 dpda_preg_317_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_317_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_317_Q_REG_DPDA_PREG_317_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_317_Q_REG_DPDA_PREG_317_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_317_Q_REG_DPDA_PREG_317_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_317_Q_REG_ADDR (0x00053D04u)
#define CSL_DFE_DPDA_DPDA_PREG_317_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_318_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_318_ie : 31;
#else 
    Uint32 dpda_preg_318_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_318_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_318_IE_REG_DPDA_PREG_318_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_318_IE_REG_DPDA_PREG_318_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_318_IE_REG_DPDA_PREG_318_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_318_IE_REG_ADDR (0x00053E00u)
#define CSL_DFE_DPDA_DPDA_PREG_318_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_318_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_318_q : 23;
#else 
    Uint32 dpda_preg_318_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_318_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_318_Q_REG_DPDA_PREG_318_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_318_Q_REG_DPDA_PREG_318_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_318_Q_REG_DPDA_PREG_318_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_318_Q_REG_ADDR (0x00053E04u)
#define CSL_DFE_DPDA_DPDA_PREG_318_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_319_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_319_ie : 31;
#else 
    Uint32 dpda_preg_319_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_319_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_319_IE_REG_DPDA_PREG_319_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_319_IE_REG_DPDA_PREG_319_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_319_IE_REG_DPDA_PREG_319_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_319_IE_REG_ADDR (0x00053F00u)
#define CSL_DFE_DPDA_DPDA_PREG_319_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_319_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_319_q : 23;
#else 
    Uint32 dpda_preg_319_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_319_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_319_Q_REG_DPDA_PREG_319_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_319_Q_REG_DPDA_PREG_319_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_319_Q_REG_DPDA_PREG_319_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_319_Q_REG_ADDR (0x00053F04u)
#define CSL_DFE_DPDA_DPDA_PREG_319_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_320_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_320_ie : 31;
#else 
    Uint32 dpda_preg_320_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_320_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_320_IE_REG_DPDA_PREG_320_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_320_IE_REG_DPDA_PREG_320_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_320_IE_REG_DPDA_PREG_320_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_320_IE_REG_ADDR (0x00054000u)
#define CSL_DFE_DPDA_DPDA_PREG_320_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_320_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_320_q : 23;
#else 
    Uint32 dpda_preg_320_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_320_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_320_Q_REG_DPDA_PREG_320_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_320_Q_REG_DPDA_PREG_320_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_320_Q_REG_DPDA_PREG_320_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_320_Q_REG_ADDR (0x00054004u)
#define CSL_DFE_DPDA_DPDA_PREG_320_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_321_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_321_ie : 31;
#else 
    Uint32 dpda_preg_321_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_321_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_321_IE_REG_DPDA_PREG_321_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_321_IE_REG_DPDA_PREG_321_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_321_IE_REG_DPDA_PREG_321_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_321_IE_REG_ADDR (0x00054100u)
#define CSL_DFE_DPDA_DPDA_PREG_321_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_321_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_321_q : 23;
#else 
    Uint32 dpda_preg_321_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_321_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_321_Q_REG_DPDA_PREG_321_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_321_Q_REG_DPDA_PREG_321_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_321_Q_REG_DPDA_PREG_321_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_321_Q_REG_ADDR (0x00054104u)
#define CSL_DFE_DPDA_DPDA_PREG_321_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_322_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_322_ie : 31;
#else 
    Uint32 dpda_preg_322_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_322_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_322_IE_REG_DPDA_PREG_322_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_322_IE_REG_DPDA_PREG_322_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_322_IE_REG_DPDA_PREG_322_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_322_IE_REG_ADDR (0x00054200u)
#define CSL_DFE_DPDA_DPDA_PREG_322_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_322_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_322_q : 23;
#else 
    Uint32 dpda_preg_322_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_322_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_322_Q_REG_DPDA_PREG_322_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_322_Q_REG_DPDA_PREG_322_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_322_Q_REG_DPDA_PREG_322_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_322_Q_REG_ADDR (0x00054204u)
#define CSL_DFE_DPDA_DPDA_PREG_322_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_323_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_323_ie : 31;
#else 
    Uint32 dpda_preg_323_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_323_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_323_IE_REG_DPDA_PREG_323_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_323_IE_REG_DPDA_PREG_323_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_323_IE_REG_DPDA_PREG_323_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_323_IE_REG_ADDR (0x00054300u)
#define CSL_DFE_DPDA_DPDA_PREG_323_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_323_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_323_q : 23;
#else 
    Uint32 dpda_preg_323_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_323_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_323_Q_REG_DPDA_PREG_323_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_323_Q_REG_DPDA_PREG_323_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_323_Q_REG_DPDA_PREG_323_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_323_Q_REG_ADDR (0x00054304u)
#define CSL_DFE_DPDA_DPDA_PREG_323_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_324_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_324_ie : 31;
#else 
    Uint32 dpda_preg_324_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_324_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_324_IE_REG_DPDA_PREG_324_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_324_IE_REG_DPDA_PREG_324_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_324_IE_REG_DPDA_PREG_324_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_324_IE_REG_ADDR (0x00054400u)
#define CSL_DFE_DPDA_DPDA_PREG_324_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_324_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_324_q : 23;
#else 
    Uint32 dpda_preg_324_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_324_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_324_Q_REG_DPDA_PREG_324_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_324_Q_REG_DPDA_PREG_324_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_324_Q_REG_DPDA_PREG_324_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_324_Q_REG_ADDR (0x00054404u)
#define CSL_DFE_DPDA_DPDA_PREG_324_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_325_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_325_ie : 31;
#else 
    Uint32 dpda_preg_325_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_325_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_325_IE_REG_DPDA_PREG_325_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_325_IE_REG_DPDA_PREG_325_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_325_IE_REG_DPDA_PREG_325_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_325_IE_REG_ADDR (0x00054500u)
#define CSL_DFE_DPDA_DPDA_PREG_325_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_325_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_325_q : 23;
#else 
    Uint32 dpda_preg_325_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_325_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_325_Q_REG_DPDA_PREG_325_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_325_Q_REG_DPDA_PREG_325_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_325_Q_REG_DPDA_PREG_325_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_325_Q_REG_ADDR (0x00054504u)
#define CSL_DFE_DPDA_DPDA_PREG_325_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_326_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_326_ie : 31;
#else 
    Uint32 dpda_preg_326_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_326_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_326_IE_REG_DPDA_PREG_326_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_326_IE_REG_DPDA_PREG_326_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_326_IE_REG_DPDA_PREG_326_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_326_IE_REG_ADDR (0x00054600u)
#define CSL_DFE_DPDA_DPDA_PREG_326_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_326_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_326_q : 23;
#else 
    Uint32 dpda_preg_326_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_326_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_326_Q_REG_DPDA_PREG_326_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_326_Q_REG_DPDA_PREG_326_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_326_Q_REG_DPDA_PREG_326_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_326_Q_REG_ADDR (0x00054604u)
#define CSL_DFE_DPDA_DPDA_PREG_326_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_327_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_327_ie : 31;
#else 
    Uint32 dpda_preg_327_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_327_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_327_IE_REG_DPDA_PREG_327_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_327_IE_REG_DPDA_PREG_327_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_327_IE_REG_DPDA_PREG_327_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_327_IE_REG_ADDR (0x00054700u)
#define CSL_DFE_DPDA_DPDA_PREG_327_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_327_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_327_q : 23;
#else 
    Uint32 dpda_preg_327_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_327_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_327_Q_REG_DPDA_PREG_327_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_327_Q_REG_DPDA_PREG_327_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_327_Q_REG_DPDA_PREG_327_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_327_Q_REG_ADDR (0x00054704u)
#define CSL_DFE_DPDA_DPDA_PREG_327_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_328_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_328_ie : 31;
#else 
    Uint32 dpda_preg_328_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_328_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_328_IE_REG_DPDA_PREG_328_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_328_IE_REG_DPDA_PREG_328_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_328_IE_REG_DPDA_PREG_328_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_328_IE_REG_ADDR (0x00054800u)
#define CSL_DFE_DPDA_DPDA_PREG_328_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_328_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_328_q : 23;
#else 
    Uint32 dpda_preg_328_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_328_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_328_Q_REG_DPDA_PREG_328_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_328_Q_REG_DPDA_PREG_328_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_328_Q_REG_DPDA_PREG_328_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_328_Q_REG_ADDR (0x00054804u)
#define CSL_DFE_DPDA_DPDA_PREG_328_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_329_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_329_ie : 31;
#else 
    Uint32 dpda_preg_329_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_329_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_329_IE_REG_DPDA_PREG_329_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_329_IE_REG_DPDA_PREG_329_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_329_IE_REG_DPDA_PREG_329_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_329_IE_REG_ADDR (0x00054900u)
#define CSL_DFE_DPDA_DPDA_PREG_329_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_329_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_329_q : 23;
#else 
    Uint32 dpda_preg_329_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_329_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_329_Q_REG_DPDA_PREG_329_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_329_Q_REG_DPDA_PREG_329_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_329_Q_REG_DPDA_PREG_329_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_329_Q_REG_ADDR (0x00054904u)
#define CSL_DFE_DPDA_DPDA_PREG_329_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_330_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_330_ie : 31;
#else 
    Uint32 dpda_preg_330_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_330_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_330_IE_REG_DPDA_PREG_330_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_330_IE_REG_DPDA_PREG_330_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_330_IE_REG_DPDA_PREG_330_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_330_IE_REG_ADDR (0x00054A00u)
#define CSL_DFE_DPDA_DPDA_PREG_330_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_330_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_330_q : 23;
#else 
    Uint32 dpda_preg_330_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_330_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_330_Q_REG_DPDA_PREG_330_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_330_Q_REG_DPDA_PREG_330_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_330_Q_REG_DPDA_PREG_330_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_330_Q_REG_ADDR (0x00054A04u)
#define CSL_DFE_DPDA_DPDA_PREG_330_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_331_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_331_ie : 31;
#else 
    Uint32 dpda_preg_331_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_331_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_331_IE_REG_DPDA_PREG_331_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_331_IE_REG_DPDA_PREG_331_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_331_IE_REG_DPDA_PREG_331_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_331_IE_REG_ADDR (0x00054B00u)
#define CSL_DFE_DPDA_DPDA_PREG_331_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_331_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_331_q : 23;
#else 
    Uint32 dpda_preg_331_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_331_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_331_Q_REG_DPDA_PREG_331_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_331_Q_REG_DPDA_PREG_331_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_331_Q_REG_DPDA_PREG_331_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_331_Q_REG_ADDR (0x00054B04u)
#define CSL_DFE_DPDA_DPDA_PREG_331_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_332_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_332_ie : 31;
#else 
    Uint32 dpda_preg_332_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_332_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_332_IE_REG_DPDA_PREG_332_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_332_IE_REG_DPDA_PREG_332_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_332_IE_REG_DPDA_PREG_332_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_332_IE_REG_ADDR (0x00054C00u)
#define CSL_DFE_DPDA_DPDA_PREG_332_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_332_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_332_q : 23;
#else 
    Uint32 dpda_preg_332_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_332_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_332_Q_REG_DPDA_PREG_332_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_332_Q_REG_DPDA_PREG_332_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_332_Q_REG_DPDA_PREG_332_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_332_Q_REG_ADDR (0x00054C04u)
#define CSL_DFE_DPDA_DPDA_PREG_332_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_333_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_333_ie : 31;
#else 
    Uint32 dpda_preg_333_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_333_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_333_IE_REG_DPDA_PREG_333_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_333_IE_REG_DPDA_PREG_333_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_333_IE_REG_DPDA_PREG_333_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_333_IE_REG_ADDR (0x00054D00u)
#define CSL_DFE_DPDA_DPDA_PREG_333_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_333_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_333_q : 23;
#else 
    Uint32 dpda_preg_333_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_333_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_333_Q_REG_DPDA_PREG_333_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_333_Q_REG_DPDA_PREG_333_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_333_Q_REG_DPDA_PREG_333_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_333_Q_REG_ADDR (0x00054D04u)
#define CSL_DFE_DPDA_DPDA_PREG_333_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_334_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_334_ie : 31;
#else 
    Uint32 dpda_preg_334_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_334_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_334_IE_REG_DPDA_PREG_334_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_334_IE_REG_DPDA_PREG_334_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_334_IE_REG_DPDA_PREG_334_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_334_IE_REG_ADDR (0x00054E00u)
#define CSL_DFE_DPDA_DPDA_PREG_334_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_334_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_334_q : 23;
#else 
    Uint32 dpda_preg_334_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_334_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_334_Q_REG_DPDA_PREG_334_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_334_Q_REG_DPDA_PREG_334_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_334_Q_REG_DPDA_PREG_334_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_334_Q_REG_ADDR (0x00054E04u)
#define CSL_DFE_DPDA_DPDA_PREG_334_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_335_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_335_ie : 31;
#else 
    Uint32 dpda_preg_335_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_335_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_335_IE_REG_DPDA_PREG_335_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_335_IE_REG_DPDA_PREG_335_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_335_IE_REG_DPDA_PREG_335_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_335_IE_REG_ADDR (0x00054F00u)
#define CSL_DFE_DPDA_DPDA_PREG_335_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_335_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_335_q : 23;
#else 
    Uint32 dpda_preg_335_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_335_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_335_Q_REG_DPDA_PREG_335_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_335_Q_REG_DPDA_PREG_335_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_335_Q_REG_DPDA_PREG_335_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_335_Q_REG_ADDR (0x00054F04u)
#define CSL_DFE_DPDA_DPDA_PREG_335_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_336_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_336_ie : 31;
#else 
    Uint32 dpda_preg_336_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_336_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_336_IE_REG_DPDA_PREG_336_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_336_IE_REG_DPDA_PREG_336_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_336_IE_REG_DPDA_PREG_336_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_336_IE_REG_ADDR (0x00055000u)
#define CSL_DFE_DPDA_DPDA_PREG_336_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_336_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_336_q : 23;
#else 
    Uint32 dpda_preg_336_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_336_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_336_Q_REG_DPDA_PREG_336_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_336_Q_REG_DPDA_PREG_336_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_336_Q_REG_DPDA_PREG_336_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_336_Q_REG_ADDR (0x00055004u)
#define CSL_DFE_DPDA_DPDA_PREG_336_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_337_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_337_ie : 31;
#else 
    Uint32 dpda_preg_337_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_337_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_337_IE_REG_DPDA_PREG_337_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_337_IE_REG_DPDA_PREG_337_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_337_IE_REG_DPDA_PREG_337_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_337_IE_REG_ADDR (0x00055100u)
#define CSL_DFE_DPDA_DPDA_PREG_337_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_337_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_337_q : 23;
#else 
    Uint32 dpda_preg_337_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_337_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_337_Q_REG_DPDA_PREG_337_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_337_Q_REG_DPDA_PREG_337_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_337_Q_REG_DPDA_PREG_337_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_337_Q_REG_ADDR (0x00055104u)
#define CSL_DFE_DPDA_DPDA_PREG_337_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_338_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_338_ie : 31;
#else 
    Uint32 dpda_preg_338_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_338_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_338_IE_REG_DPDA_PREG_338_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_338_IE_REG_DPDA_PREG_338_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_338_IE_REG_DPDA_PREG_338_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_338_IE_REG_ADDR (0x00055200u)
#define CSL_DFE_DPDA_DPDA_PREG_338_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_338_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_338_q : 23;
#else 
    Uint32 dpda_preg_338_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_338_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_338_Q_REG_DPDA_PREG_338_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_338_Q_REG_DPDA_PREG_338_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_338_Q_REG_DPDA_PREG_338_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_338_Q_REG_ADDR (0x00055204u)
#define CSL_DFE_DPDA_DPDA_PREG_338_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_339_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_339_ie : 31;
#else 
    Uint32 dpda_preg_339_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_339_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_339_IE_REG_DPDA_PREG_339_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_339_IE_REG_DPDA_PREG_339_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_339_IE_REG_DPDA_PREG_339_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_339_IE_REG_ADDR (0x00055300u)
#define CSL_DFE_DPDA_DPDA_PREG_339_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_339_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_339_q : 23;
#else 
    Uint32 dpda_preg_339_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_339_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_339_Q_REG_DPDA_PREG_339_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_339_Q_REG_DPDA_PREG_339_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_339_Q_REG_DPDA_PREG_339_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_339_Q_REG_ADDR (0x00055304u)
#define CSL_DFE_DPDA_DPDA_PREG_339_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_340_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_340_ie : 31;
#else 
    Uint32 dpda_preg_340_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_340_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_340_IE_REG_DPDA_PREG_340_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_340_IE_REG_DPDA_PREG_340_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_340_IE_REG_DPDA_PREG_340_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_340_IE_REG_ADDR (0x00055400u)
#define CSL_DFE_DPDA_DPDA_PREG_340_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_340_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_340_q : 23;
#else 
    Uint32 dpda_preg_340_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_340_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_340_Q_REG_DPDA_PREG_340_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_340_Q_REG_DPDA_PREG_340_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_340_Q_REG_DPDA_PREG_340_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_340_Q_REG_ADDR (0x00055404u)
#define CSL_DFE_DPDA_DPDA_PREG_340_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_341_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_341_ie : 31;
#else 
    Uint32 dpda_preg_341_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_341_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_341_IE_REG_DPDA_PREG_341_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_341_IE_REG_DPDA_PREG_341_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_341_IE_REG_DPDA_PREG_341_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_341_IE_REG_ADDR (0x00055500u)
#define CSL_DFE_DPDA_DPDA_PREG_341_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_341_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_341_q : 23;
#else 
    Uint32 dpda_preg_341_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_341_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_341_Q_REG_DPDA_PREG_341_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_341_Q_REG_DPDA_PREG_341_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_341_Q_REG_DPDA_PREG_341_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_341_Q_REG_ADDR (0x00055504u)
#define CSL_DFE_DPDA_DPDA_PREG_341_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_342_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_342_ie : 31;
#else 
    Uint32 dpda_preg_342_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_342_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_342_IE_REG_DPDA_PREG_342_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_342_IE_REG_DPDA_PREG_342_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_342_IE_REG_DPDA_PREG_342_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_342_IE_REG_ADDR (0x00055600u)
#define CSL_DFE_DPDA_DPDA_PREG_342_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_342_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_342_q : 23;
#else 
    Uint32 dpda_preg_342_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_342_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_342_Q_REG_DPDA_PREG_342_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_342_Q_REG_DPDA_PREG_342_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_342_Q_REG_DPDA_PREG_342_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_342_Q_REG_ADDR (0x00055604u)
#define CSL_DFE_DPDA_DPDA_PREG_342_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_343_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_343_ie : 31;
#else 
    Uint32 dpda_preg_343_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_343_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_343_IE_REG_DPDA_PREG_343_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_343_IE_REG_DPDA_PREG_343_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_343_IE_REG_DPDA_PREG_343_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_343_IE_REG_ADDR (0x00055700u)
#define CSL_DFE_DPDA_DPDA_PREG_343_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_343_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_343_q : 23;
#else 
    Uint32 dpda_preg_343_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_343_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_343_Q_REG_DPDA_PREG_343_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_343_Q_REG_DPDA_PREG_343_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_343_Q_REG_DPDA_PREG_343_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_343_Q_REG_ADDR (0x00055704u)
#define CSL_DFE_DPDA_DPDA_PREG_343_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_344_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_344_ie : 31;
#else 
    Uint32 dpda_preg_344_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_344_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_344_IE_REG_DPDA_PREG_344_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_344_IE_REG_DPDA_PREG_344_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_344_IE_REG_DPDA_PREG_344_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_344_IE_REG_ADDR (0x00055800u)
#define CSL_DFE_DPDA_DPDA_PREG_344_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_344_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_344_q : 23;
#else 
    Uint32 dpda_preg_344_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_344_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_344_Q_REG_DPDA_PREG_344_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_344_Q_REG_DPDA_PREG_344_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_344_Q_REG_DPDA_PREG_344_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_344_Q_REG_ADDR (0x00055804u)
#define CSL_DFE_DPDA_DPDA_PREG_344_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_345_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_345_ie : 31;
#else 
    Uint32 dpda_preg_345_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_345_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_345_IE_REG_DPDA_PREG_345_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_345_IE_REG_DPDA_PREG_345_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_345_IE_REG_DPDA_PREG_345_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_345_IE_REG_ADDR (0x00055900u)
#define CSL_DFE_DPDA_DPDA_PREG_345_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_345_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_345_q : 23;
#else 
    Uint32 dpda_preg_345_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_345_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_345_Q_REG_DPDA_PREG_345_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_345_Q_REG_DPDA_PREG_345_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_345_Q_REG_DPDA_PREG_345_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_345_Q_REG_ADDR (0x00055904u)
#define CSL_DFE_DPDA_DPDA_PREG_345_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_346_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_346_ie : 31;
#else 
    Uint32 dpda_preg_346_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_346_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_346_IE_REG_DPDA_PREG_346_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_346_IE_REG_DPDA_PREG_346_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_346_IE_REG_DPDA_PREG_346_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_346_IE_REG_ADDR (0x00055A00u)
#define CSL_DFE_DPDA_DPDA_PREG_346_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_346_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_346_q : 23;
#else 
    Uint32 dpda_preg_346_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_346_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_346_Q_REG_DPDA_PREG_346_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_346_Q_REG_DPDA_PREG_346_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_346_Q_REG_DPDA_PREG_346_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_346_Q_REG_ADDR (0x00055A04u)
#define CSL_DFE_DPDA_DPDA_PREG_346_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_347_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_347_ie : 31;
#else 
    Uint32 dpda_preg_347_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_347_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_347_IE_REG_DPDA_PREG_347_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_347_IE_REG_DPDA_PREG_347_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_347_IE_REG_DPDA_PREG_347_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_347_IE_REG_ADDR (0x00055B00u)
#define CSL_DFE_DPDA_DPDA_PREG_347_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_347_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_347_q : 23;
#else 
    Uint32 dpda_preg_347_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_347_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_347_Q_REG_DPDA_PREG_347_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_347_Q_REG_DPDA_PREG_347_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_347_Q_REG_DPDA_PREG_347_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_347_Q_REG_ADDR (0x00055B04u)
#define CSL_DFE_DPDA_DPDA_PREG_347_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_348_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_348_ie : 31;
#else 
    Uint32 dpda_preg_348_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_348_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_348_IE_REG_DPDA_PREG_348_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_348_IE_REG_DPDA_PREG_348_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_348_IE_REG_DPDA_PREG_348_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_348_IE_REG_ADDR (0x00055C00u)
#define CSL_DFE_DPDA_DPDA_PREG_348_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_348_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_348_q : 23;
#else 
    Uint32 dpda_preg_348_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_348_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_348_Q_REG_DPDA_PREG_348_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_348_Q_REG_DPDA_PREG_348_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_348_Q_REG_DPDA_PREG_348_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_348_Q_REG_ADDR (0x00055C04u)
#define CSL_DFE_DPDA_DPDA_PREG_348_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_349_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_349_ie : 31;
#else 
    Uint32 dpda_preg_349_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_349_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_349_IE_REG_DPDA_PREG_349_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_349_IE_REG_DPDA_PREG_349_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_349_IE_REG_DPDA_PREG_349_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_349_IE_REG_ADDR (0x00055D00u)
#define CSL_DFE_DPDA_DPDA_PREG_349_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_349_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_349_q : 23;
#else 
    Uint32 dpda_preg_349_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_349_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_349_Q_REG_DPDA_PREG_349_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_349_Q_REG_DPDA_PREG_349_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_349_Q_REG_DPDA_PREG_349_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_349_Q_REG_ADDR (0x00055D04u)
#define CSL_DFE_DPDA_DPDA_PREG_349_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_350_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_350_ie : 31;
#else 
    Uint32 dpda_preg_350_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_350_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_350_IE_REG_DPDA_PREG_350_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_350_IE_REG_DPDA_PREG_350_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_350_IE_REG_DPDA_PREG_350_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_350_IE_REG_ADDR (0x00055E00u)
#define CSL_DFE_DPDA_DPDA_PREG_350_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_350_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_350_q : 23;
#else 
    Uint32 dpda_preg_350_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_350_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_350_Q_REG_DPDA_PREG_350_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_350_Q_REG_DPDA_PREG_350_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_350_Q_REG_DPDA_PREG_350_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_350_Q_REG_ADDR (0x00055E04u)
#define CSL_DFE_DPDA_DPDA_PREG_350_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_351_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_351_ie : 31;
#else 
    Uint32 dpda_preg_351_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_351_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_351_IE_REG_DPDA_PREG_351_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_351_IE_REG_DPDA_PREG_351_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_351_IE_REG_DPDA_PREG_351_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_351_IE_REG_ADDR (0x00055F00u)
#define CSL_DFE_DPDA_DPDA_PREG_351_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_351_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_351_q : 23;
#else 
    Uint32 dpda_preg_351_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_351_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_351_Q_REG_DPDA_PREG_351_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_351_Q_REG_DPDA_PREG_351_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_351_Q_REG_DPDA_PREG_351_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_351_Q_REG_ADDR (0x00055F04u)
#define CSL_DFE_DPDA_DPDA_PREG_351_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_352_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_352_ie : 31;
#else 
    Uint32 dpda_preg_352_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_352_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_352_IE_REG_DPDA_PREG_352_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_352_IE_REG_DPDA_PREG_352_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_352_IE_REG_DPDA_PREG_352_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_352_IE_REG_ADDR (0x00056000u)
#define CSL_DFE_DPDA_DPDA_PREG_352_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_352_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_352_q : 23;
#else 
    Uint32 dpda_preg_352_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_352_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_352_Q_REG_DPDA_PREG_352_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_352_Q_REG_DPDA_PREG_352_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_352_Q_REG_DPDA_PREG_352_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_352_Q_REG_ADDR (0x00056004u)
#define CSL_DFE_DPDA_DPDA_PREG_352_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_353_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_353_ie : 31;
#else 
    Uint32 dpda_preg_353_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_353_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_353_IE_REG_DPDA_PREG_353_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_353_IE_REG_DPDA_PREG_353_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_353_IE_REG_DPDA_PREG_353_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_353_IE_REG_ADDR (0x00056100u)
#define CSL_DFE_DPDA_DPDA_PREG_353_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_353_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_353_q : 23;
#else 
    Uint32 dpda_preg_353_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_353_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_353_Q_REG_DPDA_PREG_353_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_353_Q_REG_DPDA_PREG_353_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_353_Q_REG_DPDA_PREG_353_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_353_Q_REG_ADDR (0x00056104u)
#define CSL_DFE_DPDA_DPDA_PREG_353_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_354_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_354_ie : 31;
#else 
    Uint32 dpda_preg_354_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_354_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_354_IE_REG_DPDA_PREG_354_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_354_IE_REG_DPDA_PREG_354_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_354_IE_REG_DPDA_PREG_354_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_354_IE_REG_ADDR (0x00056200u)
#define CSL_DFE_DPDA_DPDA_PREG_354_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_354_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_354_q : 23;
#else 
    Uint32 dpda_preg_354_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_354_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_354_Q_REG_DPDA_PREG_354_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_354_Q_REG_DPDA_PREG_354_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_354_Q_REG_DPDA_PREG_354_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_354_Q_REG_ADDR (0x00056204u)
#define CSL_DFE_DPDA_DPDA_PREG_354_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_355_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_355_ie : 31;
#else 
    Uint32 dpda_preg_355_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_355_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_355_IE_REG_DPDA_PREG_355_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_355_IE_REG_DPDA_PREG_355_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_355_IE_REG_DPDA_PREG_355_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_355_IE_REG_ADDR (0x00056300u)
#define CSL_DFE_DPDA_DPDA_PREG_355_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_355_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_355_q : 23;
#else 
    Uint32 dpda_preg_355_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_355_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_355_Q_REG_DPDA_PREG_355_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_355_Q_REG_DPDA_PREG_355_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_355_Q_REG_DPDA_PREG_355_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_355_Q_REG_ADDR (0x00056304u)
#define CSL_DFE_DPDA_DPDA_PREG_355_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_356_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_356_ie : 31;
#else 
    Uint32 dpda_preg_356_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_356_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_356_IE_REG_DPDA_PREG_356_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_356_IE_REG_DPDA_PREG_356_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_356_IE_REG_DPDA_PREG_356_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_356_IE_REG_ADDR (0x00056400u)
#define CSL_DFE_DPDA_DPDA_PREG_356_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_356_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_356_q : 23;
#else 
    Uint32 dpda_preg_356_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_356_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_356_Q_REG_DPDA_PREG_356_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_356_Q_REG_DPDA_PREG_356_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_356_Q_REG_DPDA_PREG_356_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_356_Q_REG_ADDR (0x00056404u)
#define CSL_DFE_DPDA_DPDA_PREG_356_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_357_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_357_ie : 31;
#else 
    Uint32 dpda_preg_357_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_357_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_357_IE_REG_DPDA_PREG_357_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_357_IE_REG_DPDA_PREG_357_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_357_IE_REG_DPDA_PREG_357_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_357_IE_REG_ADDR (0x00056500u)
#define CSL_DFE_DPDA_DPDA_PREG_357_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_357_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_357_q : 23;
#else 
    Uint32 dpda_preg_357_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_357_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_357_Q_REG_DPDA_PREG_357_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_357_Q_REG_DPDA_PREG_357_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_357_Q_REG_DPDA_PREG_357_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_357_Q_REG_ADDR (0x00056504u)
#define CSL_DFE_DPDA_DPDA_PREG_357_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_358_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_358_ie : 31;
#else 
    Uint32 dpda_preg_358_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_358_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_358_IE_REG_DPDA_PREG_358_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_358_IE_REG_DPDA_PREG_358_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_358_IE_REG_DPDA_PREG_358_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_358_IE_REG_ADDR (0x00056600u)
#define CSL_DFE_DPDA_DPDA_PREG_358_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_358_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_358_q : 23;
#else 
    Uint32 dpda_preg_358_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_358_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_358_Q_REG_DPDA_PREG_358_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_358_Q_REG_DPDA_PREG_358_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_358_Q_REG_DPDA_PREG_358_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_358_Q_REG_ADDR (0x00056604u)
#define CSL_DFE_DPDA_DPDA_PREG_358_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_359_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_359_ie : 31;
#else 
    Uint32 dpda_preg_359_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_359_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_359_IE_REG_DPDA_PREG_359_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_359_IE_REG_DPDA_PREG_359_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_359_IE_REG_DPDA_PREG_359_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_359_IE_REG_ADDR (0x00056700u)
#define CSL_DFE_DPDA_DPDA_PREG_359_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_359_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_359_q : 23;
#else 
    Uint32 dpda_preg_359_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_359_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_359_Q_REG_DPDA_PREG_359_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_359_Q_REG_DPDA_PREG_359_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_359_Q_REG_DPDA_PREG_359_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_359_Q_REG_ADDR (0x00056704u)
#define CSL_DFE_DPDA_DPDA_PREG_359_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_360_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_360_ie : 31;
#else 
    Uint32 dpda_preg_360_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_360_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_360_IE_REG_DPDA_PREG_360_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_360_IE_REG_DPDA_PREG_360_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_360_IE_REG_DPDA_PREG_360_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_360_IE_REG_ADDR (0x00056800u)
#define CSL_DFE_DPDA_DPDA_PREG_360_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_360_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_360_q : 23;
#else 
    Uint32 dpda_preg_360_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_360_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_360_Q_REG_DPDA_PREG_360_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_360_Q_REG_DPDA_PREG_360_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_360_Q_REG_DPDA_PREG_360_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_360_Q_REG_ADDR (0x00056804u)
#define CSL_DFE_DPDA_DPDA_PREG_360_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_361_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_361_ie : 31;
#else 
    Uint32 dpda_preg_361_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_361_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_361_IE_REG_DPDA_PREG_361_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_361_IE_REG_DPDA_PREG_361_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_361_IE_REG_DPDA_PREG_361_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_361_IE_REG_ADDR (0x00056900u)
#define CSL_DFE_DPDA_DPDA_PREG_361_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_361_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_361_q : 23;
#else 
    Uint32 dpda_preg_361_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_361_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_361_Q_REG_DPDA_PREG_361_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_361_Q_REG_DPDA_PREG_361_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_361_Q_REG_DPDA_PREG_361_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_361_Q_REG_ADDR (0x00056904u)
#define CSL_DFE_DPDA_DPDA_PREG_361_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_362_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_362_ie : 31;
#else 
    Uint32 dpda_preg_362_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_362_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_362_IE_REG_DPDA_PREG_362_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_362_IE_REG_DPDA_PREG_362_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_362_IE_REG_DPDA_PREG_362_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_362_IE_REG_ADDR (0x00056A00u)
#define CSL_DFE_DPDA_DPDA_PREG_362_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_362_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_362_q : 23;
#else 
    Uint32 dpda_preg_362_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_362_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_362_Q_REG_DPDA_PREG_362_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_362_Q_REG_DPDA_PREG_362_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_362_Q_REG_DPDA_PREG_362_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_362_Q_REG_ADDR (0x00056A04u)
#define CSL_DFE_DPDA_DPDA_PREG_362_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_363_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_363_ie : 31;
#else 
    Uint32 dpda_preg_363_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_363_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_363_IE_REG_DPDA_PREG_363_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_363_IE_REG_DPDA_PREG_363_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_363_IE_REG_DPDA_PREG_363_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_363_IE_REG_ADDR (0x00056B00u)
#define CSL_DFE_DPDA_DPDA_PREG_363_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_363_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_363_q : 23;
#else 
    Uint32 dpda_preg_363_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_363_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_363_Q_REG_DPDA_PREG_363_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_363_Q_REG_DPDA_PREG_363_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_363_Q_REG_DPDA_PREG_363_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_363_Q_REG_ADDR (0x00056B04u)
#define CSL_DFE_DPDA_DPDA_PREG_363_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_364_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_364_ie : 31;
#else 
    Uint32 dpda_preg_364_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_364_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_364_IE_REG_DPDA_PREG_364_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_364_IE_REG_DPDA_PREG_364_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_364_IE_REG_DPDA_PREG_364_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_364_IE_REG_ADDR (0x00056C00u)
#define CSL_DFE_DPDA_DPDA_PREG_364_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_364_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_364_q : 23;
#else 
    Uint32 dpda_preg_364_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_364_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_364_Q_REG_DPDA_PREG_364_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_364_Q_REG_DPDA_PREG_364_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_364_Q_REG_DPDA_PREG_364_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_364_Q_REG_ADDR (0x00056C04u)
#define CSL_DFE_DPDA_DPDA_PREG_364_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_365_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_365_ie : 31;
#else 
    Uint32 dpda_preg_365_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_365_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_365_IE_REG_DPDA_PREG_365_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_365_IE_REG_DPDA_PREG_365_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_365_IE_REG_DPDA_PREG_365_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_365_IE_REG_ADDR (0x00056D00u)
#define CSL_DFE_DPDA_DPDA_PREG_365_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_365_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_365_q : 23;
#else 
    Uint32 dpda_preg_365_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_365_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_365_Q_REG_DPDA_PREG_365_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_365_Q_REG_DPDA_PREG_365_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_365_Q_REG_DPDA_PREG_365_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_365_Q_REG_ADDR (0x00056D04u)
#define CSL_DFE_DPDA_DPDA_PREG_365_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_366_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_366_ie : 31;
#else 
    Uint32 dpda_preg_366_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_366_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_366_IE_REG_DPDA_PREG_366_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_366_IE_REG_DPDA_PREG_366_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_366_IE_REG_DPDA_PREG_366_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_366_IE_REG_ADDR (0x00056E00u)
#define CSL_DFE_DPDA_DPDA_PREG_366_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_366_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_366_q : 23;
#else 
    Uint32 dpda_preg_366_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_366_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_366_Q_REG_DPDA_PREG_366_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_366_Q_REG_DPDA_PREG_366_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_366_Q_REG_DPDA_PREG_366_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_366_Q_REG_ADDR (0x00056E04u)
#define CSL_DFE_DPDA_DPDA_PREG_366_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_367_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_367_ie : 31;
#else 
    Uint32 dpda_preg_367_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_367_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_367_IE_REG_DPDA_PREG_367_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_367_IE_REG_DPDA_PREG_367_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_367_IE_REG_DPDA_PREG_367_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_367_IE_REG_ADDR (0x00056F00u)
#define CSL_DFE_DPDA_DPDA_PREG_367_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_367_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_367_q : 23;
#else 
    Uint32 dpda_preg_367_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_367_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_367_Q_REG_DPDA_PREG_367_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_367_Q_REG_DPDA_PREG_367_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_367_Q_REG_DPDA_PREG_367_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_367_Q_REG_ADDR (0x00056F04u)
#define CSL_DFE_DPDA_DPDA_PREG_367_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_368_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_368_ie : 31;
#else 
    Uint32 dpda_preg_368_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_368_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_368_IE_REG_DPDA_PREG_368_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_368_IE_REG_DPDA_PREG_368_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_368_IE_REG_DPDA_PREG_368_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_368_IE_REG_ADDR (0x00057000u)
#define CSL_DFE_DPDA_DPDA_PREG_368_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_368_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_368_q : 23;
#else 
    Uint32 dpda_preg_368_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_368_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_368_Q_REG_DPDA_PREG_368_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_368_Q_REG_DPDA_PREG_368_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_368_Q_REG_DPDA_PREG_368_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_368_Q_REG_ADDR (0x00057004u)
#define CSL_DFE_DPDA_DPDA_PREG_368_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_369_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_369_ie : 31;
#else 
    Uint32 dpda_preg_369_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_369_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_369_IE_REG_DPDA_PREG_369_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_369_IE_REG_DPDA_PREG_369_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_369_IE_REG_DPDA_PREG_369_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_369_IE_REG_ADDR (0x00057100u)
#define CSL_DFE_DPDA_DPDA_PREG_369_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_369_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_369_q : 23;
#else 
    Uint32 dpda_preg_369_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_369_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_369_Q_REG_DPDA_PREG_369_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_369_Q_REG_DPDA_PREG_369_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_369_Q_REG_DPDA_PREG_369_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_369_Q_REG_ADDR (0x00057104u)
#define CSL_DFE_DPDA_DPDA_PREG_369_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_370_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_370_ie : 31;
#else 
    Uint32 dpda_preg_370_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_370_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_370_IE_REG_DPDA_PREG_370_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_370_IE_REG_DPDA_PREG_370_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_370_IE_REG_DPDA_PREG_370_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_370_IE_REG_ADDR (0x00057200u)
#define CSL_DFE_DPDA_DPDA_PREG_370_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_370_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_370_q : 23;
#else 
    Uint32 dpda_preg_370_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_370_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_370_Q_REG_DPDA_PREG_370_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_370_Q_REG_DPDA_PREG_370_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_370_Q_REG_DPDA_PREG_370_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_370_Q_REG_ADDR (0x00057204u)
#define CSL_DFE_DPDA_DPDA_PREG_370_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_371_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_371_ie : 31;
#else 
    Uint32 dpda_preg_371_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_371_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_371_IE_REG_DPDA_PREG_371_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_371_IE_REG_DPDA_PREG_371_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_371_IE_REG_DPDA_PREG_371_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_371_IE_REG_ADDR (0x00057300u)
#define CSL_DFE_DPDA_DPDA_PREG_371_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_371_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_371_q : 23;
#else 
    Uint32 dpda_preg_371_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_371_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_371_Q_REG_DPDA_PREG_371_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_371_Q_REG_DPDA_PREG_371_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_371_Q_REG_DPDA_PREG_371_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_371_Q_REG_ADDR (0x00057304u)
#define CSL_DFE_DPDA_DPDA_PREG_371_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_372_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_372_ie : 31;
#else 
    Uint32 dpda_preg_372_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_372_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_372_IE_REG_DPDA_PREG_372_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_372_IE_REG_DPDA_PREG_372_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_372_IE_REG_DPDA_PREG_372_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_372_IE_REG_ADDR (0x00057400u)
#define CSL_DFE_DPDA_DPDA_PREG_372_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_372_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_372_q : 23;
#else 
    Uint32 dpda_preg_372_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_372_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_372_Q_REG_DPDA_PREG_372_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_372_Q_REG_DPDA_PREG_372_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_372_Q_REG_DPDA_PREG_372_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_372_Q_REG_ADDR (0x00057404u)
#define CSL_DFE_DPDA_DPDA_PREG_372_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_373_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_373_ie : 31;
#else 
    Uint32 dpda_preg_373_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_373_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_373_IE_REG_DPDA_PREG_373_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_373_IE_REG_DPDA_PREG_373_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_373_IE_REG_DPDA_PREG_373_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_373_IE_REG_ADDR (0x00057500u)
#define CSL_DFE_DPDA_DPDA_PREG_373_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_373_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_373_q : 23;
#else 
    Uint32 dpda_preg_373_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_373_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_373_Q_REG_DPDA_PREG_373_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_373_Q_REG_DPDA_PREG_373_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_373_Q_REG_DPDA_PREG_373_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_373_Q_REG_ADDR (0x00057504u)
#define CSL_DFE_DPDA_DPDA_PREG_373_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_374_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_374_ie : 31;
#else 
    Uint32 dpda_preg_374_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_374_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_374_IE_REG_DPDA_PREG_374_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_374_IE_REG_DPDA_PREG_374_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_374_IE_REG_DPDA_PREG_374_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_374_IE_REG_ADDR (0x00057600u)
#define CSL_DFE_DPDA_DPDA_PREG_374_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_374_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_374_q : 23;
#else 
    Uint32 dpda_preg_374_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_374_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_374_Q_REG_DPDA_PREG_374_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_374_Q_REG_DPDA_PREG_374_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_374_Q_REG_DPDA_PREG_374_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_374_Q_REG_ADDR (0x00057604u)
#define CSL_DFE_DPDA_DPDA_PREG_374_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_375_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_375_ie : 31;
#else 
    Uint32 dpda_preg_375_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_375_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_375_IE_REG_DPDA_PREG_375_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_375_IE_REG_DPDA_PREG_375_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_375_IE_REG_DPDA_PREG_375_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_375_IE_REG_ADDR (0x00057700u)
#define CSL_DFE_DPDA_DPDA_PREG_375_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_375_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_375_q : 23;
#else 
    Uint32 dpda_preg_375_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_375_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_375_Q_REG_DPDA_PREG_375_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_375_Q_REG_DPDA_PREG_375_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_375_Q_REG_DPDA_PREG_375_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_375_Q_REG_ADDR (0x00057704u)
#define CSL_DFE_DPDA_DPDA_PREG_375_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_376_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_376_ie : 31;
#else 
    Uint32 dpda_preg_376_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_376_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_376_IE_REG_DPDA_PREG_376_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_376_IE_REG_DPDA_PREG_376_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_376_IE_REG_DPDA_PREG_376_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_376_IE_REG_ADDR (0x00057800u)
#define CSL_DFE_DPDA_DPDA_PREG_376_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_376_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_376_q : 23;
#else 
    Uint32 dpda_preg_376_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_376_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_376_Q_REG_DPDA_PREG_376_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_376_Q_REG_DPDA_PREG_376_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_376_Q_REG_DPDA_PREG_376_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_376_Q_REG_ADDR (0x00057804u)
#define CSL_DFE_DPDA_DPDA_PREG_376_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_377_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_377_ie : 31;
#else 
    Uint32 dpda_preg_377_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_377_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_377_IE_REG_DPDA_PREG_377_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_377_IE_REG_DPDA_PREG_377_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_377_IE_REG_DPDA_PREG_377_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_377_IE_REG_ADDR (0x00057900u)
#define CSL_DFE_DPDA_DPDA_PREG_377_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_377_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_377_q : 23;
#else 
    Uint32 dpda_preg_377_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_377_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_377_Q_REG_DPDA_PREG_377_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_377_Q_REG_DPDA_PREG_377_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_377_Q_REG_DPDA_PREG_377_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_377_Q_REG_ADDR (0x00057904u)
#define CSL_DFE_DPDA_DPDA_PREG_377_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_378_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_378_ie : 31;
#else 
    Uint32 dpda_preg_378_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_378_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_378_IE_REG_DPDA_PREG_378_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_378_IE_REG_DPDA_PREG_378_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_378_IE_REG_DPDA_PREG_378_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_378_IE_REG_ADDR (0x00057A00u)
#define CSL_DFE_DPDA_DPDA_PREG_378_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_378_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_378_q : 23;
#else 
    Uint32 dpda_preg_378_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_378_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_378_Q_REG_DPDA_PREG_378_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_378_Q_REG_DPDA_PREG_378_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_378_Q_REG_DPDA_PREG_378_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_378_Q_REG_ADDR (0x00057A04u)
#define CSL_DFE_DPDA_DPDA_PREG_378_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_379_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_379_ie : 31;
#else 
    Uint32 dpda_preg_379_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_379_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_379_IE_REG_DPDA_PREG_379_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_379_IE_REG_DPDA_PREG_379_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_379_IE_REG_DPDA_PREG_379_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_379_IE_REG_ADDR (0x00057B00u)
#define CSL_DFE_DPDA_DPDA_PREG_379_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_379_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_379_q : 23;
#else 
    Uint32 dpda_preg_379_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_379_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_379_Q_REG_DPDA_PREG_379_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_379_Q_REG_DPDA_PREG_379_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_379_Q_REG_DPDA_PREG_379_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_379_Q_REG_ADDR (0x00057B04u)
#define CSL_DFE_DPDA_DPDA_PREG_379_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_380_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_380_ie : 31;
#else 
    Uint32 dpda_preg_380_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_380_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_380_IE_REG_DPDA_PREG_380_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_380_IE_REG_DPDA_PREG_380_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_380_IE_REG_DPDA_PREG_380_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_380_IE_REG_ADDR (0x00057C00u)
#define CSL_DFE_DPDA_DPDA_PREG_380_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_380_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_380_q : 23;
#else 
    Uint32 dpda_preg_380_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_380_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_380_Q_REG_DPDA_PREG_380_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_380_Q_REG_DPDA_PREG_380_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_380_Q_REG_DPDA_PREG_380_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_380_Q_REG_ADDR (0x00057C04u)
#define CSL_DFE_DPDA_DPDA_PREG_380_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_381_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_381_ie : 31;
#else 
    Uint32 dpda_preg_381_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_381_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_381_IE_REG_DPDA_PREG_381_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_381_IE_REG_DPDA_PREG_381_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_381_IE_REG_DPDA_PREG_381_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_381_IE_REG_ADDR (0x00057D00u)
#define CSL_DFE_DPDA_DPDA_PREG_381_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_381_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_381_q : 23;
#else 
    Uint32 dpda_preg_381_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_381_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_381_Q_REG_DPDA_PREG_381_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_381_Q_REG_DPDA_PREG_381_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_381_Q_REG_DPDA_PREG_381_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_381_Q_REG_ADDR (0x00057D04u)
#define CSL_DFE_DPDA_DPDA_PREG_381_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_382_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_382_ie : 31;
#else 
    Uint32 dpda_preg_382_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_382_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_382_IE_REG_DPDA_PREG_382_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_382_IE_REG_DPDA_PREG_382_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_382_IE_REG_DPDA_PREG_382_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_382_IE_REG_ADDR (0x00057E00u)
#define CSL_DFE_DPDA_DPDA_PREG_382_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_382_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_382_q : 23;
#else 
    Uint32 dpda_preg_382_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_382_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_382_Q_REG_DPDA_PREG_382_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_382_Q_REG_DPDA_PREG_382_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_382_Q_REG_DPDA_PREG_382_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_382_Q_REG_ADDR (0x00057E04u)
#define CSL_DFE_DPDA_DPDA_PREG_382_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_383_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_383_ie : 31;
#else 
    Uint32 dpda_preg_383_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_383_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_383_IE_REG_DPDA_PREG_383_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_383_IE_REG_DPDA_PREG_383_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_383_IE_REG_DPDA_PREG_383_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_383_IE_REG_ADDR (0x00057F00u)
#define CSL_DFE_DPDA_DPDA_PREG_383_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_383_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_383_q : 23;
#else 
    Uint32 dpda_preg_383_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_383_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_383_Q_REG_DPDA_PREG_383_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_383_Q_REG_DPDA_PREG_383_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_383_Q_REG_DPDA_PREG_383_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_383_Q_REG_ADDR (0x00057F04u)
#define CSL_DFE_DPDA_DPDA_PREG_383_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_384_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_384_ie : 31;
#else 
    Uint32 dpda_preg_384_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_384_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_384_IE_REG_DPDA_PREG_384_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_384_IE_REG_DPDA_PREG_384_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_384_IE_REG_DPDA_PREG_384_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_384_IE_REG_ADDR (0x00058000u)
#define CSL_DFE_DPDA_DPDA_PREG_384_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_384_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_384_q : 23;
#else 
    Uint32 dpda_preg_384_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_384_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_384_Q_REG_DPDA_PREG_384_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_384_Q_REG_DPDA_PREG_384_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_384_Q_REG_DPDA_PREG_384_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_384_Q_REG_ADDR (0x00058004u)
#define CSL_DFE_DPDA_DPDA_PREG_384_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_385_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_385_ie : 31;
#else 
    Uint32 dpda_preg_385_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_385_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_385_IE_REG_DPDA_PREG_385_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_385_IE_REG_DPDA_PREG_385_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_385_IE_REG_DPDA_PREG_385_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_385_IE_REG_ADDR (0x00058100u)
#define CSL_DFE_DPDA_DPDA_PREG_385_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_385_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_385_q : 23;
#else 
    Uint32 dpda_preg_385_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_385_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_385_Q_REG_DPDA_PREG_385_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_385_Q_REG_DPDA_PREG_385_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_385_Q_REG_DPDA_PREG_385_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_385_Q_REG_ADDR (0x00058104u)
#define CSL_DFE_DPDA_DPDA_PREG_385_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_386_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_386_ie : 31;
#else 
    Uint32 dpda_preg_386_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_386_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_386_IE_REG_DPDA_PREG_386_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_386_IE_REG_DPDA_PREG_386_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_386_IE_REG_DPDA_PREG_386_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_386_IE_REG_ADDR (0x00058200u)
#define CSL_DFE_DPDA_DPDA_PREG_386_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_386_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_386_q : 23;
#else 
    Uint32 dpda_preg_386_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_386_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_386_Q_REG_DPDA_PREG_386_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_386_Q_REG_DPDA_PREG_386_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_386_Q_REG_DPDA_PREG_386_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_386_Q_REG_ADDR (0x00058204u)
#define CSL_DFE_DPDA_DPDA_PREG_386_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_387_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_387_ie : 31;
#else 
    Uint32 dpda_preg_387_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_387_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_387_IE_REG_DPDA_PREG_387_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_387_IE_REG_DPDA_PREG_387_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_387_IE_REG_DPDA_PREG_387_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_387_IE_REG_ADDR (0x00058300u)
#define CSL_DFE_DPDA_DPDA_PREG_387_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_387_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_387_q : 23;
#else 
    Uint32 dpda_preg_387_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_387_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_387_Q_REG_DPDA_PREG_387_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_387_Q_REG_DPDA_PREG_387_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_387_Q_REG_DPDA_PREG_387_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_387_Q_REG_ADDR (0x00058304u)
#define CSL_DFE_DPDA_DPDA_PREG_387_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_388_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_388_ie : 31;
#else 
    Uint32 dpda_preg_388_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_388_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_388_IE_REG_DPDA_PREG_388_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_388_IE_REG_DPDA_PREG_388_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_388_IE_REG_DPDA_PREG_388_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_388_IE_REG_ADDR (0x00058400u)
#define CSL_DFE_DPDA_DPDA_PREG_388_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_388_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_388_q : 23;
#else 
    Uint32 dpda_preg_388_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_388_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_388_Q_REG_DPDA_PREG_388_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_388_Q_REG_DPDA_PREG_388_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_388_Q_REG_DPDA_PREG_388_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_388_Q_REG_ADDR (0x00058404u)
#define CSL_DFE_DPDA_DPDA_PREG_388_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_389_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_389_ie : 31;
#else 
    Uint32 dpda_preg_389_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_389_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_389_IE_REG_DPDA_PREG_389_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_389_IE_REG_DPDA_PREG_389_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_389_IE_REG_DPDA_PREG_389_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_389_IE_REG_ADDR (0x00058500u)
#define CSL_DFE_DPDA_DPDA_PREG_389_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_389_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_389_q : 23;
#else 
    Uint32 dpda_preg_389_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_389_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_389_Q_REG_DPDA_PREG_389_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_389_Q_REG_DPDA_PREG_389_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_389_Q_REG_DPDA_PREG_389_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_389_Q_REG_ADDR (0x00058504u)
#define CSL_DFE_DPDA_DPDA_PREG_389_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_390_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_390_ie : 31;
#else 
    Uint32 dpda_preg_390_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_390_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_390_IE_REG_DPDA_PREG_390_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_390_IE_REG_DPDA_PREG_390_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_390_IE_REG_DPDA_PREG_390_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_390_IE_REG_ADDR (0x00058600u)
#define CSL_DFE_DPDA_DPDA_PREG_390_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_390_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_390_q : 23;
#else 
    Uint32 dpda_preg_390_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_390_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_390_Q_REG_DPDA_PREG_390_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_390_Q_REG_DPDA_PREG_390_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_390_Q_REG_DPDA_PREG_390_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_390_Q_REG_ADDR (0x00058604u)
#define CSL_DFE_DPDA_DPDA_PREG_390_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_391_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_391_ie : 31;
#else 
    Uint32 dpda_preg_391_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_391_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_391_IE_REG_DPDA_PREG_391_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_391_IE_REG_DPDA_PREG_391_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_391_IE_REG_DPDA_PREG_391_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_391_IE_REG_ADDR (0x00058700u)
#define CSL_DFE_DPDA_DPDA_PREG_391_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_391_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_391_q : 23;
#else 
    Uint32 dpda_preg_391_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_391_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_391_Q_REG_DPDA_PREG_391_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_391_Q_REG_DPDA_PREG_391_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_391_Q_REG_DPDA_PREG_391_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_391_Q_REG_ADDR (0x00058704u)
#define CSL_DFE_DPDA_DPDA_PREG_391_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_392_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_392_ie : 31;
#else 
    Uint32 dpda_preg_392_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_392_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_392_IE_REG_DPDA_PREG_392_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_392_IE_REG_DPDA_PREG_392_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_392_IE_REG_DPDA_PREG_392_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_392_IE_REG_ADDR (0x00058800u)
#define CSL_DFE_DPDA_DPDA_PREG_392_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_392_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_392_q : 23;
#else 
    Uint32 dpda_preg_392_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_392_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_392_Q_REG_DPDA_PREG_392_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_392_Q_REG_DPDA_PREG_392_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_392_Q_REG_DPDA_PREG_392_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_392_Q_REG_ADDR (0x00058804u)
#define CSL_DFE_DPDA_DPDA_PREG_392_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_393_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_393_ie : 31;
#else 
    Uint32 dpda_preg_393_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_393_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_393_IE_REG_DPDA_PREG_393_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_393_IE_REG_DPDA_PREG_393_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_393_IE_REG_DPDA_PREG_393_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_393_IE_REG_ADDR (0x00058900u)
#define CSL_DFE_DPDA_DPDA_PREG_393_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_393_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_393_q : 23;
#else 
    Uint32 dpda_preg_393_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_393_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_393_Q_REG_DPDA_PREG_393_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_393_Q_REG_DPDA_PREG_393_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_393_Q_REG_DPDA_PREG_393_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_393_Q_REG_ADDR (0x00058904u)
#define CSL_DFE_DPDA_DPDA_PREG_393_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_394_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_394_ie : 31;
#else 
    Uint32 dpda_preg_394_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_394_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_394_IE_REG_DPDA_PREG_394_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_394_IE_REG_DPDA_PREG_394_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_394_IE_REG_DPDA_PREG_394_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_394_IE_REG_ADDR (0x00058A00u)
#define CSL_DFE_DPDA_DPDA_PREG_394_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_394_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_394_q : 23;
#else 
    Uint32 dpda_preg_394_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_394_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_394_Q_REG_DPDA_PREG_394_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_394_Q_REG_DPDA_PREG_394_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_394_Q_REG_DPDA_PREG_394_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_394_Q_REG_ADDR (0x00058A04u)
#define CSL_DFE_DPDA_DPDA_PREG_394_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_395_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_395_ie : 31;
#else 
    Uint32 dpda_preg_395_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_395_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_395_IE_REG_DPDA_PREG_395_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_395_IE_REG_DPDA_PREG_395_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_395_IE_REG_DPDA_PREG_395_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_395_IE_REG_ADDR (0x00058B00u)
#define CSL_DFE_DPDA_DPDA_PREG_395_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_395_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_395_q : 23;
#else 
    Uint32 dpda_preg_395_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_395_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_395_Q_REG_DPDA_PREG_395_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_395_Q_REG_DPDA_PREG_395_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_395_Q_REG_DPDA_PREG_395_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_395_Q_REG_ADDR (0x00058B04u)
#define CSL_DFE_DPDA_DPDA_PREG_395_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_396_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_396_ie : 31;
#else 
    Uint32 dpda_preg_396_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_396_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_396_IE_REG_DPDA_PREG_396_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_396_IE_REG_DPDA_PREG_396_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_396_IE_REG_DPDA_PREG_396_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_396_IE_REG_ADDR (0x00058C00u)
#define CSL_DFE_DPDA_DPDA_PREG_396_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_396_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_396_q : 23;
#else 
    Uint32 dpda_preg_396_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_396_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_396_Q_REG_DPDA_PREG_396_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_396_Q_REG_DPDA_PREG_396_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_396_Q_REG_DPDA_PREG_396_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_396_Q_REG_ADDR (0x00058C04u)
#define CSL_DFE_DPDA_DPDA_PREG_396_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_397_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_397_ie : 31;
#else 
    Uint32 dpda_preg_397_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_397_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_397_IE_REG_DPDA_PREG_397_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_397_IE_REG_DPDA_PREG_397_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_397_IE_REG_DPDA_PREG_397_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_397_IE_REG_ADDR (0x00058D00u)
#define CSL_DFE_DPDA_DPDA_PREG_397_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_397_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_397_q : 23;
#else 
    Uint32 dpda_preg_397_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_397_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_397_Q_REG_DPDA_PREG_397_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_397_Q_REG_DPDA_PREG_397_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_397_Q_REG_DPDA_PREG_397_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_397_Q_REG_ADDR (0x00058D04u)
#define CSL_DFE_DPDA_DPDA_PREG_397_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_398_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_398_ie : 31;
#else 
    Uint32 dpda_preg_398_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_398_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_398_IE_REG_DPDA_PREG_398_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_398_IE_REG_DPDA_PREG_398_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_398_IE_REG_DPDA_PREG_398_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_398_IE_REG_ADDR (0x00058E00u)
#define CSL_DFE_DPDA_DPDA_PREG_398_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_398_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_398_q : 23;
#else 
    Uint32 dpda_preg_398_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_398_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_398_Q_REG_DPDA_PREG_398_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_398_Q_REG_DPDA_PREG_398_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_398_Q_REG_DPDA_PREG_398_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_398_Q_REG_ADDR (0x00058E04u)
#define CSL_DFE_DPDA_DPDA_PREG_398_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_399_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_399_ie : 31;
#else 
    Uint32 dpda_preg_399_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_399_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_399_IE_REG_DPDA_PREG_399_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_399_IE_REG_DPDA_PREG_399_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_399_IE_REG_DPDA_PREG_399_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_399_IE_REG_ADDR (0x00058F00u)
#define CSL_DFE_DPDA_DPDA_PREG_399_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_399_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_399_q : 23;
#else 
    Uint32 dpda_preg_399_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_399_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_399_Q_REG_DPDA_PREG_399_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_399_Q_REG_DPDA_PREG_399_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_399_Q_REG_DPDA_PREG_399_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_399_Q_REG_ADDR (0x00058F04u)
#define CSL_DFE_DPDA_DPDA_PREG_399_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_400_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_400_ie : 31;
#else 
    Uint32 dpda_preg_400_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_400_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_400_IE_REG_DPDA_PREG_400_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_400_IE_REG_DPDA_PREG_400_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_400_IE_REG_DPDA_PREG_400_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_400_IE_REG_ADDR (0x00059000u)
#define CSL_DFE_DPDA_DPDA_PREG_400_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_400_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_400_q : 23;
#else 
    Uint32 dpda_preg_400_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_400_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_400_Q_REG_DPDA_PREG_400_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_400_Q_REG_DPDA_PREG_400_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_400_Q_REG_DPDA_PREG_400_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_400_Q_REG_ADDR (0x00059004u)
#define CSL_DFE_DPDA_DPDA_PREG_400_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_401_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_401_ie : 31;
#else 
    Uint32 dpda_preg_401_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_401_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_401_IE_REG_DPDA_PREG_401_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_401_IE_REG_DPDA_PREG_401_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_401_IE_REG_DPDA_PREG_401_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_401_IE_REG_ADDR (0x00059100u)
#define CSL_DFE_DPDA_DPDA_PREG_401_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_401_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_401_q : 23;
#else 
    Uint32 dpda_preg_401_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_401_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_401_Q_REG_DPDA_PREG_401_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_401_Q_REG_DPDA_PREG_401_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_401_Q_REG_DPDA_PREG_401_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_401_Q_REG_ADDR (0x00059104u)
#define CSL_DFE_DPDA_DPDA_PREG_401_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_402_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_402_ie : 31;
#else 
    Uint32 dpda_preg_402_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_402_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_402_IE_REG_DPDA_PREG_402_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_402_IE_REG_DPDA_PREG_402_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_402_IE_REG_DPDA_PREG_402_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_402_IE_REG_ADDR (0x00059200u)
#define CSL_DFE_DPDA_DPDA_PREG_402_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_402_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_402_q : 23;
#else 
    Uint32 dpda_preg_402_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_402_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_402_Q_REG_DPDA_PREG_402_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_402_Q_REG_DPDA_PREG_402_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_402_Q_REG_DPDA_PREG_402_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_402_Q_REG_ADDR (0x00059204u)
#define CSL_DFE_DPDA_DPDA_PREG_402_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_403_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_403_ie : 31;
#else 
    Uint32 dpda_preg_403_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_403_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_403_IE_REG_DPDA_PREG_403_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_403_IE_REG_DPDA_PREG_403_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_403_IE_REG_DPDA_PREG_403_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_403_IE_REG_ADDR (0x00059300u)
#define CSL_DFE_DPDA_DPDA_PREG_403_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_403_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_403_q : 23;
#else 
    Uint32 dpda_preg_403_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_403_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_403_Q_REG_DPDA_PREG_403_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_403_Q_REG_DPDA_PREG_403_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_403_Q_REG_DPDA_PREG_403_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_403_Q_REG_ADDR (0x00059304u)
#define CSL_DFE_DPDA_DPDA_PREG_403_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_404_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_404_ie : 31;
#else 
    Uint32 dpda_preg_404_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_404_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_404_IE_REG_DPDA_PREG_404_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_404_IE_REG_DPDA_PREG_404_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_404_IE_REG_DPDA_PREG_404_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_404_IE_REG_ADDR (0x00059400u)
#define CSL_DFE_DPDA_DPDA_PREG_404_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_404_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_404_q : 23;
#else 
    Uint32 dpda_preg_404_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_404_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_404_Q_REG_DPDA_PREG_404_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_404_Q_REG_DPDA_PREG_404_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_404_Q_REG_DPDA_PREG_404_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_404_Q_REG_ADDR (0x00059404u)
#define CSL_DFE_DPDA_DPDA_PREG_404_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_405_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_405_ie : 31;
#else 
    Uint32 dpda_preg_405_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_405_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_405_IE_REG_DPDA_PREG_405_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_405_IE_REG_DPDA_PREG_405_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_405_IE_REG_DPDA_PREG_405_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_405_IE_REG_ADDR (0x00059500u)
#define CSL_DFE_DPDA_DPDA_PREG_405_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_405_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_405_q : 23;
#else 
    Uint32 dpda_preg_405_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_405_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_405_Q_REG_DPDA_PREG_405_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_405_Q_REG_DPDA_PREG_405_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_405_Q_REG_DPDA_PREG_405_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_405_Q_REG_ADDR (0x00059504u)
#define CSL_DFE_DPDA_DPDA_PREG_405_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_406_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_406_ie : 31;
#else 
    Uint32 dpda_preg_406_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_406_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_406_IE_REG_DPDA_PREG_406_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_406_IE_REG_DPDA_PREG_406_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_406_IE_REG_DPDA_PREG_406_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_406_IE_REG_ADDR (0x00059600u)
#define CSL_DFE_DPDA_DPDA_PREG_406_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_406_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_406_q : 23;
#else 
    Uint32 dpda_preg_406_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_406_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_406_Q_REG_DPDA_PREG_406_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_406_Q_REG_DPDA_PREG_406_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_406_Q_REG_DPDA_PREG_406_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_406_Q_REG_ADDR (0x00059604u)
#define CSL_DFE_DPDA_DPDA_PREG_406_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_407_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_407_ie : 31;
#else 
    Uint32 dpda_preg_407_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_407_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_407_IE_REG_DPDA_PREG_407_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_407_IE_REG_DPDA_PREG_407_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_407_IE_REG_DPDA_PREG_407_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_407_IE_REG_ADDR (0x00059700u)
#define CSL_DFE_DPDA_DPDA_PREG_407_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_407_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_407_q : 23;
#else 
    Uint32 dpda_preg_407_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_407_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_407_Q_REG_DPDA_PREG_407_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_407_Q_REG_DPDA_PREG_407_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_407_Q_REG_DPDA_PREG_407_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_407_Q_REG_ADDR (0x00059704u)
#define CSL_DFE_DPDA_DPDA_PREG_407_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_408_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_408_ie : 31;
#else 
    Uint32 dpda_preg_408_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_408_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_408_IE_REG_DPDA_PREG_408_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_408_IE_REG_DPDA_PREG_408_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_408_IE_REG_DPDA_PREG_408_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_408_IE_REG_ADDR (0x00059800u)
#define CSL_DFE_DPDA_DPDA_PREG_408_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_408_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_408_q : 23;
#else 
    Uint32 dpda_preg_408_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_408_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_408_Q_REG_DPDA_PREG_408_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_408_Q_REG_DPDA_PREG_408_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_408_Q_REG_DPDA_PREG_408_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_408_Q_REG_ADDR (0x00059804u)
#define CSL_DFE_DPDA_DPDA_PREG_408_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_409_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_409_ie : 31;
#else 
    Uint32 dpda_preg_409_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_409_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_409_IE_REG_DPDA_PREG_409_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_409_IE_REG_DPDA_PREG_409_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_409_IE_REG_DPDA_PREG_409_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_409_IE_REG_ADDR (0x00059900u)
#define CSL_DFE_DPDA_DPDA_PREG_409_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_409_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_409_q : 23;
#else 
    Uint32 dpda_preg_409_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_409_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_409_Q_REG_DPDA_PREG_409_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_409_Q_REG_DPDA_PREG_409_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_409_Q_REG_DPDA_PREG_409_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_409_Q_REG_ADDR (0x00059904u)
#define CSL_DFE_DPDA_DPDA_PREG_409_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_410_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_410_ie : 31;
#else 
    Uint32 dpda_preg_410_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_410_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_410_IE_REG_DPDA_PREG_410_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_410_IE_REG_DPDA_PREG_410_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_410_IE_REG_DPDA_PREG_410_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_410_IE_REG_ADDR (0x00059A00u)
#define CSL_DFE_DPDA_DPDA_PREG_410_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_410_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_410_q : 23;
#else 
    Uint32 dpda_preg_410_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_410_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_410_Q_REG_DPDA_PREG_410_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_410_Q_REG_DPDA_PREG_410_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_410_Q_REG_DPDA_PREG_410_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_410_Q_REG_ADDR (0x00059A04u)
#define CSL_DFE_DPDA_DPDA_PREG_410_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_411_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_411_ie : 31;
#else 
    Uint32 dpda_preg_411_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_411_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_411_IE_REG_DPDA_PREG_411_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_411_IE_REG_DPDA_PREG_411_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_411_IE_REG_DPDA_PREG_411_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_411_IE_REG_ADDR (0x00059B00u)
#define CSL_DFE_DPDA_DPDA_PREG_411_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_411_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_411_q : 23;
#else 
    Uint32 dpda_preg_411_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_411_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_411_Q_REG_DPDA_PREG_411_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_411_Q_REG_DPDA_PREG_411_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_411_Q_REG_DPDA_PREG_411_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_411_Q_REG_ADDR (0x00059B04u)
#define CSL_DFE_DPDA_DPDA_PREG_411_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_412_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_412_ie : 31;
#else 
    Uint32 dpda_preg_412_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_412_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_412_IE_REG_DPDA_PREG_412_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_412_IE_REG_DPDA_PREG_412_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_412_IE_REG_DPDA_PREG_412_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_412_IE_REG_ADDR (0x00059C00u)
#define CSL_DFE_DPDA_DPDA_PREG_412_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_412_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_412_q : 23;
#else 
    Uint32 dpda_preg_412_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_412_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_412_Q_REG_DPDA_PREG_412_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_412_Q_REG_DPDA_PREG_412_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_412_Q_REG_DPDA_PREG_412_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_412_Q_REG_ADDR (0x00059C04u)
#define CSL_DFE_DPDA_DPDA_PREG_412_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_413_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_413_ie : 31;
#else 
    Uint32 dpda_preg_413_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_413_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_413_IE_REG_DPDA_PREG_413_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_413_IE_REG_DPDA_PREG_413_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_413_IE_REG_DPDA_PREG_413_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_413_IE_REG_ADDR (0x00059D00u)
#define CSL_DFE_DPDA_DPDA_PREG_413_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_413_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_413_q : 23;
#else 
    Uint32 dpda_preg_413_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_413_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_413_Q_REG_DPDA_PREG_413_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_413_Q_REG_DPDA_PREG_413_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_413_Q_REG_DPDA_PREG_413_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_413_Q_REG_ADDR (0x00059D04u)
#define CSL_DFE_DPDA_DPDA_PREG_413_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_414_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_414_ie : 31;
#else 
    Uint32 dpda_preg_414_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_414_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_414_IE_REG_DPDA_PREG_414_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_414_IE_REG_DPDA_PREG_414_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_414_IE_REG_DPDA_PREG_414_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_414_IE_REG_ADDR (0x00059E00u)
#define CSL_DFE_DPDA_DPDA_PREG_414_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_414_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_414_q : 23;
#else 
    Uint32 dpda_preg_414_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_414_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_414_Q_REG_DPDA_PREG_414_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_414_Q_REG_DPDA_PREG_414_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_414_Q_REG_DPDA_PREG_414_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_414_Q_REG_ADDR (0x00059E04u)
#define CSL_DFE_DPDA_DPDA_PREG_414_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_415_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_415_ie : 31;
#else 
    Uint32 dpda_preg_415_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_415_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_415_IE_REG_DPDA_PREG_415_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_415_IE_REG_DPDA_PREG_415_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_415_IE_REG_DPDA_PREG_415_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_415_IE_REG_ADDR (0x00059F00u)
#define CSL_DFE_DPDA_DPDA_PREG_415_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_415_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_415_q : 23;
#else 
    Uint32 dpda_preg_415_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_415_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_415_Q_REG_DPDA_PREG_415_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_415_Q_REG_DPDA_PREG_415_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_415_Q_REG_DPDA_PREG_415_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_415_Q_REG_ADDR (0x00059F04u)
#define CSL_DFE_DPDA_DPDA_PREG_415_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_416_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_416_ie : 31;
#else 
    Uint32 dpda_preg_416_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_416_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_416_IE_REG_DPDA_PREG_416_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_416_IE_REG_DPDA_PREG_416_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_416_IE_REG_DPDA_PREG_416_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_416_IE_REG_ADDR (0x0005A000u)
#define CSL_DFE_DPDA_DPDA_PREG_416_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_416_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_416_q : 23;
#else 
    Uint32 dpda_preg_416_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_416_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_416_Q_REG_DPDA_PREG_416_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_416_Q_REG_DPDA_PREG_416_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_416_Q_REG_DPDA_PREG_416_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_416_Q_REG_ADDR (0x0005A004u)
#define CSL_DFE_DPDA_DPDA_PREG_416_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_417_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_417_ie : 31;
#else 
    Uint32 dpda_preg_417_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_417_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_417_IE_REG_DPDA_PREG_417_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_417_IE_REG_DPDA_PREG_417_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_417_IE_REG_DPDA_PREG_417_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_417_IE_REG_ADDR (0x0005A100u)
#define CSL_DFE_DPDA_DPDA_PREG_417_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_417_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_417_q : 23;
#else 
    Uint32 dpda_preg_417_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_417_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_417_Q_REG_DPDA_PREG_417_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_417_Q_REG_DPDA_PREG_417_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_417_Q_REG_DPDA_PREG_417_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_417_Q_REG_ADDR (0x0005A104u)
#define CSL_DFE_DPDA_DPDA_PREG_417_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_418_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_418_ie : 31;
#else 
    Uint32 dpda_preg_418_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_418_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_418_IE_REG_DPDA_PREG_418_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_418_IE_REG_DPDA_PREG_418_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_418_IE_REG_DPDA_PREG_418_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_418_IE_REG_ADDR (0x0005A200u)
#define CSL_DFE_DPDA_DPDA_PREG_418_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_418_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_418_q : 23;
#else 
    Uint32 dpda_preg_418_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_418_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_418_Q_REG_DPDA_PREG_418_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_418_Q_REG_DPDA_PREG_418_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_418_Q_REG_DPDA_PREG_418_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_418_Q_REG_ADDR (0x0005A204u)
#define CSL_DFE_DPDA_DPDA_PREG_418_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_419_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_419_ie : 31;
#else 
    Uint32 dpda_preg_419_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_419_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_419_IE_REG_DPDA_PREG_419_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_419_IE_REG_DPDA_PREG_419_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_419_IE_REG_DPDA_PREG_419_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_419_IE_REG_ADDR (0x0005A300u)
#define CSL_DFE_DPDA_DPDA_PREG_419_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_419_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_419_q : 23;
#else 
    Uint32 dpda_preg_419_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_419_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_419_Q_REG_DPDA_PREG_419_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_419_Q_REG_DPDA_PREG_419_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_419_Q_REG_DPDA_PREG_419_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_419_Q_REG_ADDR (0x0005A304u)
#define CSL_DFE_DPDA_DPDA_PREG_419_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_420_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_420_ie : 31;
#else 
    Uint32 dpda_preg_420_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_420_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_420_IE_REG_DPDA_PREG_420_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_420_IE_REG_DPDA_PREG_420_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_420_IE_REG_DPDA_PREG_420_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_420_IE_REG_ADDR (0x0005A400u)
#define CSL_DFE_DPDA_DPDA_PREG_420_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_420_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_420_q : 23;
#else 
    Uint32 dpda_preg_420_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_420_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_420_Q_REG_DPDA_PREG_420_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_420_Q_REG_DPDA_PREG_420_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_420_Q_REG_DPDA_PREG_420_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_420_Q_REG_ADDR (0x0005A404u)
#define CSL_DFE_DPDA_DPDA_PREG_420_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_421_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_421_ie : 31;
#else 
    Uint32 dpda_preg_421_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_421_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_421_IE_REG_DPDA_PREG_421_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_421_IE_REG_DPDA_PREG_421_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_421_IE_REG_DPDA_PREG_421_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_421_IE_REG_ADDR (0x0005A500u)
#define CSL_DFE_DPDA_DPDA_PREG_421_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_421_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_421_q : 23;
#else 
    Uint32 dpda_preg_421_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_421_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_421_Q_REG_DPDA_PREG_421_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_421_Q_REG_DPDA_PREG_421_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_421_Q_REG_DPDA_PREG_421_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_421_Q_REG_ADDR (0x0005A504u)
#define CSL_DFE_DPDA_DPDA_PREG_421_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_422_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_422_ie : 31;
#else 
    Uint32 dpda_preg_422_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_422_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_422_IE_REG_DPDA_PREG_422_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_422_IE_REG_DPDA_PREG_422_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_422_IE_REG_DPDA_PREG_422_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_422_IE_REG_ADDR (0x0005A600u)
#define CSL_DFE_DPDA_DPDA_PREG_422_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_422_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_422_q : 23;
#else 
    Uint32 dpda_preg_422_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_422_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_422_Q_REG_DPDA_PREG_422_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_422_Q_REG_DPDA_PREG_422_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_422_Q_REG_DPDA_PREG_422_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_422_Q_REG_ADDR (0x0005A604u)
#define CSL_DFE_DPDA_DPDA_PREG_422_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_423_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_423_ie : 31;
#else 
    Uint32 dpda_preg_423_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_423_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_423_IE_REG_DPDA_PREG_423_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_423_IE_REG_DPDA_PREG_423_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_423_IE_REG_DPDA_PREG_423_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_423_IE_REG_ADDR (0x0005A700u)
#define CSL_DFE_DPDA_DPDA_PREG_423_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_423_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_423_q : 23;
#else 
    Uint32 dpda_preg_423_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_423_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_423_Q_REG_DPDA_PREG_423_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_423_Q_REG_DPDA_PREG_423_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_423_Q_REG_DPDA_PREG_423_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_423_Q_REG_ADDR (0x0005A704u)
#define CSL_DFE_DPDA_DPDA_PREG_423_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_424_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_424_ie : 31;
#else 
    Uint32 dpda_preg_424_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_424_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_424_IE_REG_DPDA_PREG_424_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_424_IE_REG_DPDA_PREG_424_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_424_IE_REG_DPDA_PREG_424_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_424_IE_REG_ADDR (0x0005A800u)
#define CSL_DFE_DPDA_DPDA_PREG_424_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_424_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_424_q : 23;
#else 
    Uint32 dpda_preg_424_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_424_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_424_Q_REG_DPDA_PREG_424_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_424_Q_REG_DPDA_PREG_424_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_424_Q_REG_DPDA_PREG_424_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_424_Q_REG_ADDR (0x0005A804u)
#define CSL_DFE_DPDA_DPDA_PREG_424_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_425_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_425_ie : 31;
#else 
    Uint32 dpda_preg_425_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_425_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_425_IE_REG_DPDA_PREG_425_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_425_IE_REG_DPDA_PREG_425_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_425_IE_REG_DPDA_PREG_425_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_425_IE_REG_ADDR (0x0005A900u)
#define CSL_DFE_DPDA_DPDA_PREG_425_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_425_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_425_q : 23;
#else 
    Uint32 dpda_preg_425_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_425_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_425_Q_REG_DPDA_PREG_425_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_425_Q_REG_DPDA_PREG_425_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_425_Q_REG_DPDA_PREG_425_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_425_Q_REG_ADDR (0x0005A904u)
#define CSL_DFE_DPDA_DPDA_PREG_425_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_426_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_426_ie : 31;
#else 
    Uint32 dpda_preg_426_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_426_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_426_IE_REG_DPDA_PREG_426_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_426_IE_REG_DPDA_PREG_426_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_426_IE_REG_DPDA_PREG_426_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_426_IE_REG_ADDR (0x0005AA00u)
#define CSL_DFE_DPDA_DPDA_PREG_426_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_426_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_426_q : 23;
#else 
    Uint32 dpda_preg_426_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_426_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_426_Q_REG_DPDA_PREG_426_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_426_Q_REG_DPDA_PREG_426_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_426_Q_REG_DPDA_PREG_426_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_426_Q_REG_ADDR (0x0005AA04u)
#define CSL_DFE_DPDA_DPDA_PREG_426_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_427_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_427_ie : 31;
#else 
    Uint32 dpda_preg_427_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_427_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_427_IE_REG_DPDA_PREG_427_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_427_IE_REG_DPDA_PREG_427_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_427_IE_REG_DPDA_PREG_427_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_427_IE_REG_ADDR (0x0005AB00u)
#define CSL_DFE_DPDA_DPDA_PREG_427_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_427_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_427_q : 23;
#else 
    Uint32 dpda_preg_427_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_427_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_427_Q_REG_DPDA_PREG_427_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_427_Q_REG_DPDA_PREG_427_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_427_Q_REG_DPDA_PREG_427_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_427_Q_REG_ADDR (0x0005AB04u)
#define CSL_DFE_DPDA_DPDA_PREG_427_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_428_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_428_ie : 31;
#else 
    Uint32 dpda_preg_428_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_428_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_428_IE_REG_DPDA_PREG_428_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_428_IE_REG_DPDA_PREG_428_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_428_IE_REG_DPDA_PREG_428_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_428_IE_REG_ADDR (0x0005AC00u)
#define CSL_DFE_DPDA_DPDA_PREG_428_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_428_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_428_q : 23;
#else 
    Uint32 dpda_preg_428_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_428_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_428_Q_REG_DPDA_PREG_428_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_428_Q_REG_DPDA_PREG_428_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_428_Q_REG_DPDA_PREG_428_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_428_Q_REG_ADDR (0x0005AC04u)
#define CSL_DFE_DPDA_DPDA_PREG_428_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_429_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_429_ie : 31;
#else 
    Uint32 dpda_preg_429_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_429_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_429_IE_REG_DPDA_PREG_429_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_429_IE_REG_DPDA_PREG_429_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_429_IE_REG_DPDA_PREG_429_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_429_IE_REG_ADDR (0x0005AD00u)
#define CSL_DFE_DPDA_DPDA_PREG_429_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_429_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_429_q : 23;
#else 
    Uint32 dpda_preg_429_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_429_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_429_Q_REG_DPDA_PREG_429_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_429_Q_REG_DPDA_PREG_429_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_429_Q_REG_DPDA_PREG_429_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_429_Q_REG_ADDR (0x0005AD04u)
#define CSL_DFE_DPDA_DPDA_PREG_429_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_430_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_430_ie : 31;
#else 
    Uint32 dpda_preg_430_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_430_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_430_IE_REG_DPDA_PREG_430_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_430_IE_REG_DPDA_PREG_430_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_430_IE_REG_DPDA_PREG_430_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_430_IE_REG_ADDR (0x0005AE00u)
#define CSL_DFE_DPDA_DPDA_PREG_430_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_430_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_430_q : 23;
#else 
    Uint32 dpda_preg_430_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_430_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_430_Q_REG_DPDA_PREG_430_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_430_Q_REG_DPDA_PREG_430_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_430_Q_REG_DPDA_PREG_430_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_430_Q_REG_ADDR (0x0005AE04u)
#define CSL_DFE_DPDA_DPDA_PREG_430_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_431_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_431_ie : 31;
#else 
    Uint32 dpda_preg_431_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_431_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_431_IE_REG_DPDA_PREG_431_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_431_IE_REG_DPDA_PREG_431_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_431_IE_REG_DPDA_PREG_431_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_431_IE_REG_ADDR (0x0005AF00u)
#define CSL_DFE_DPDA_DPDA_PREG_431_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_431_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_431_q : 23;
#else 
    Uint32 dpda_preg_431_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_431_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_431_Q_REG_DPDA_PREG_431_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_431_Q_REG_DPDA_PREG_431_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_431_Q_REG_DPDA_PREG_431_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_431_Q_REG_ADDR (0x0005AF04u)
#define CSL_DFE_DPDA_DPDA_PREG_431_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_432_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_432_ie : 31;
#else 
    Uint32 dpda_preg_432_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_432_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_432_IE_REG_DPDA_PREG_432_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_432_IE_REG_DPDA_PREG_432_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_432_IE_REG_DPDA_PREG_432_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_432_IE_REG_ADDR (0x0005B000u)
#define CSL_DFE_DPDA_DPDA_PREG_432_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_432_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_432_q : 23;
#else 
    Uint32 dpda_preg_432_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_432_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_432_Q_REG_DPDA_PREG_432_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_432_Q_REG_DPDA_PREG_432_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_432_Q_REG_DPDA_PREG_432_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_432_Q_REG_ADDR (0x0005B004u)
#define CSL_DFE_DPDA_DPDA_PREG_432_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_433_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_433_ie : 31;
#else 
    Uint32 dpda_preg_433_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_433_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_433_IE_REG_DPDA_PREG_433_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_433_IE_REG_DPDA_PREG_433_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_433_IE_REG_DPDA_PREG_433_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_433_IE_REG_ADDR (0x0005B100u)
#define CSL_DFE_DPDA_DPDA_PREG_433_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_433_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_433_q : 23;
#else 
    Uint32 dpda_preg_433_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_433_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_433_Q_REG_DPDA_PREG_433_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_433_Q_REG_DPDA_PREG_433_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_433_Q_REG_DPDA_PREG_433_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_433_Q_REG_ADDR (0x0005B104u)
#define CSL_DFE_DPDA_DPDA_PREG_433_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_434_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_434_ie : 31;
#else 
    Uint32 dpda_preg_434_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_434_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_434_IE_REG_DPDA_PREG_434_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_434_IE_REG_DPDA_PREG_434_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_434_IE_REG_DPDA_PREG_434_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_434_IE_REG_ADDR (0x0005B200u)
#define CSL_DFE_DPDA_DPDA_PREG_434_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_434_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_434_q : 23;
#else 
    Uint32 dpda_preg_434_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_434_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_434_Q_REG_DPDA_PREG_434_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_434_Q_REG_DPDA_PREG_434_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_434_Q_REG_DPDA_PREG_434_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_434_Q_REG_ADDR (0x0005B204u)
#define CSL_DFE_DPDA_DPDA_PREG_434_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_435_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_435_ie : 31;
#else 
    Uint32 dpda_preg_435_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_435_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_435_IE_REG_DPDA_PREG_435_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_435_IE_REG_DPDA_PREG_435_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_435_IE_REG_DPDA_PREG_435_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_435_IE_REG_ADDR (0x0005B300u)
#define CSL_DFE_DPDA_DPDA_PREG_435_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_435_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_435_q : 23;
#else 
    Uint32 dpda_preg_435_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_435_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_435_Q_REG_DPDA_PREG_435_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_435_Q_REG_DPDA_PREG_435_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_435_Q_REG_DPDA_PREG_435_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_435_Q_REG_ADDR (0x0005B304u)
#define CSL_DFE_DPDA_DPDA_PREG_435_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_436_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_436_ie : 31;
#else 
    Uint32 dpda_preg_436_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_436_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_436_IE_REG_DPDA_PREG_436_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_436_IE_REG_DPDA_PREG_436_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_436_IE_REG_DPDA_PREG_436_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_436_IE_REG_ADDR (0x0005B400u)
#define CSL_DFE_DPDA_DPDA_PREG_436_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_436_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_436_q : 23;
#else 
    Uint32 dpda_preg_436_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_436_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_436_Q_REG_DPDA_PREG_436_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_436_Q_REG_DPDA_PREG_436_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_436_Q_REG_DPDA_PREG_436_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_436_Q_REG_ADDR (0x0005B404u)
#define CSL_DFE_DPDA_DPDA_PREG_436_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_437_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_437_ie : 31;
#else 
    Uint32 dpda_preg_437_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_437_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_437_IE_REG_DPDA_PREG_437_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_437_IE_REG_DPDA_PREG_437_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_437_IE_REG_DPDA_PREG_437_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_437_IE_REG_ADDR (0x0005B500u)
#define CSL_DFE_DPDA_DPDA_PREG_437_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_437_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_437_q : 23;
#else 
    Uint32 dpda_preg_437_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_437_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_437_Q_REG_DPDA_PREG_437_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_437_Q_REG_DPDA_PREG_437_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_437_Q_REG_DPDA_PREG_437_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_437_Q_REG_ADDR (0x0005B504u)
#define CSL_DFE_DPDA_DPDA_PREG_437_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_438_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_438_ie : 31;
#else 
    Uint32 dpda_preg_438_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_438_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_438_IE_REG_DPDA_PREG_438_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_438_IE_REG_DPDA_PREG_438_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_438_IE_REG_DPDA_PREG_438_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_438_IE_REG_ADDR (0x0005B600u)
#define CSL_DFE_DPDA_DPDA_PREG_438_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_438_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_438_q : 23;
#else 
    Uint32 dpda_preg_438_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_438_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_438_Q_REG_DPDA_PREG_438_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_438_Q_REG_DPDA_PREG_438_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_438_Q_REG_DPDA_PREG_438_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_438_Q_REG_ADDR (0x0005B604u)
#define CSL_DFE_DPDA_DPDA_PREG_438_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_439_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_439_ie : 31;
#else 
    Uint32 dpda_preg_439_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_439_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_439_IE_REG_DPDA_PREG_439_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_439_IE_REG_DPDA_PREG_439_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_439_IE_REG_DPDA_PREG_439_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_439_IE_REG_ADDR (0x0005B700u)
#define CSL_DFE_DPDA_DPDA_PREG_439_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_439_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_439_q : 23;
#else 
    Uint32 dpda_preg_439_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_439_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_439_Q_REG_DPDA_PREG_439_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_439_Q_REG_DPDA_PREG_439_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_439_Q_REG_DPDA_PREG_439_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_439_Q_REG_ADDR (0x0005B704u)
#define CSL_DFE_DPDA_DPDA_PREG_439_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_440_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_440_ie : 31;
#else 
    Uint32 dpda_preg_440_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_440_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_440_IE_REG_DPDA_PREG_440_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_440_IE_REG_DPDA_PREG_440_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_440_IE_REG_DPDA_PREG_440_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_440_IE_REG_ADDR (0x0005B800u)
#define CSL_DFE_DPDA_DPDA_PREG_440_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_440_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_440_q : 23;
#else 
    Uint32 dpda_preg_440_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_440_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_440_Q_REG_DPDA_PREG_440_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_440_Q_REG_DPDA_PREG_440_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_440_Q_REG_DPDA_PREG_440_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_440_Q_REG_ADDR (0x0005B804u)
#define CSL_DFE_DPDA_DPDA_PREG_440_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_441_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_441_ie : 31;
#else 
    Uint32 dpda_preg_441_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_441_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_441_IE_REG_DPDA_PREG_441_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_441_IE_REG_DPDA_PREG_441_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_441_IE_REG_DPDA_PREG_441_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_441_IE_REG_ADDR (0x0005B900u)
#define CSL_DFE_DPDA_DPDA_PREG_441_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_441_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_441_q : 23;
#else 
    Uint32 dpda_preg_441_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_441_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_441_Q_REG_DPDA_PREG_441_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_441_Q_REG_DPDA_PREG_441_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_441_Q_REG_DPDA_PREG_441_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_441_Q_REG_ADDR (0x0005B904u)
#define CSL_DFE_DPDA_DPDA_PREG_441_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_442_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_442_ie : 31;
#else 
    Uint32 dpda_preg_442_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_442_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_442_IE_REG_DPDA_PREG_442_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_442_IE_REG_DPDA_PREG_442_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_442_IE_REG_DPDA_PREG_442_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_442_IE_REG_ADDR (0x0005BA00u)
#define CSL_DFE_DPDA_DPDA_PREG_442_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_442_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_442_q : 23;
#else 
    Uint32 dpda_preg_442_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_442_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_442_Q_REG_DPDA_PREG_442_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_442_Q_REG_DPDA_PREG_442_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_442_Q_REG_DPDA_PREG_442_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_442_Q_REG_ADDR (0x0005BA04u)
#define CSL_DFE_DPDA_DPDA_PREG_442_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_443_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_443_ie : 31;
#else 
    Uint32 dpda_preg_443_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_443_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_443_IE_REG_DPDA_PREG_443_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_443_IE_REG_DPDA_PREG_443_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_443_IE_REG_DPDA_PREG_443_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_443_IE_REG_ADDR (0x0005BB00u)
#define CSL_DFE_DPDA_DPDA_PREG_443_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_443_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_443_q : 23;
#else 
    Uint32 dpda_preg_443_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_443_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_443_Q_REG_DPDA_PREG_443_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_443_Q_REG_DPDA_PREG_443_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_443_Q_REG_DPDA_PREG_443_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_443_Q_REG_ADDR (0x0005BB04u)
#define CSL_DFE_DPDA_DPDA_PREG_443_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_444_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_444_ie : 31;
#else 
    Uint32 dpda_preg_444_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_444_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_444_IE_REG_DPDA_PREG_444_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_444_IE_REG_DPDA_PREG_444_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_444_IE_REG_DPDA_PREG_444_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_444_IE_REG_ADDR (0x0005BC00u)
#define CSL_DFE_DPDA_DPDA_PREG_444_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_444_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_444_q : 23;
#else 
    Uint32 dpda_preg_444_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_444_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_444_Q_REG_DPDA_PREG_444_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_444_Q_REG_DPDA_PREG_444_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_444_Q_REG_DPDA_PREG_444_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_444_Q_REG_ADDR (0x0005BC04u)
#define CSL_DFE_DPDA_DPDA_PREG_444_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_445_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_445_ie : 31;
#else 
    Uint32 dpda_preg_445_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_445_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_445_IE_REG_DPDA_PREG_445_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_445_IE_REG_DPDA_PREG_445_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_445_IE_REG_DPDA_PREG_445_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_445_IE_REG_ADDR (0x0005BD00u)
#define CSL_DFE_DPDA_DPDA_PREG_445_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_445_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_445_q : 23;
#else 
    Uint32 dpda_preg_445_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_445_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_445_Q_REG_DPDA_PREG_445_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_445_Q_REG_DPDA_PREG_445_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_445_Q_REG_DPDA_PREG_445_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_445_Q_REG_ADDR (0x0005BD04u)
#define CSL_DFE_DPDA_DPDA_PREG_445_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_446_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_446_ie : 31;
#else 
    Uint32 dpda_preg_446_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_446_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_446_IE_REG_DPDA_PREG_446_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_446_IE_REG_DPDA_PREG_446_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_446_IE_REG_DPDA_PREG_446_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_446_IE_REG_ADDR (0x0005BE00u)
#define CSL_DFE_DPDA_DPDA_PREG_446_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_446_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_446_q : 23;
#else 
    Uint32 dpda_preg_446_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_446_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_446_Q_REG_DPDA_PREG_446_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_446_Q_REG_DPDA_PREG_446_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_446_Q_REG_DPDA_PREG_446_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_446_Q_REG_ADDR (0x0005BE04u)
#define CSL_DFE_DPDA_DPDA_PREG_446_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_447_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_447_ie : 31;
#else 
    Uint32 dpda_preg_447_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_447_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_447_IE_REG_DPDA_PREG_447_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_447_IE_REG_DPDA_PREG_447_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_447_IE_REG_DPDA_PREG_447_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_447_IE_REG_ADDR (0x0005BF00u)
#define CSL_DFE_DPDA_DPDA_PREG_447_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_447_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_447_q : 23;
#else 
    Uint32 dpda_preg_447_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_447_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_447_Q_REG_DPDA_PREG_447_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_447_Q_REG_DPDA_PREG_447_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_447_Q_REG_DPDA_PREG_447_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_447_Q_REG_ADDR (0x0005BF04u)
#define CSL_DFE_DPDA_DPDA_PREG_447_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_448_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_448_ie : 31;
#else 
    Uint32 dpda_preg_448_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_448_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_448_IE_REG_DPDA_PREG_448_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_448_IE_REG_DPDA_PREG_448_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_448_IE_REG_DPDA_PREG_448_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_448_IE_REG_ADDR (0x0005C000u)
#define CSL_DFE_DPDA_DPDA_PREG_448_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_448_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_448_q : 23;
#else 
    Uint32 dpda_preg_448_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_448_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_448_Q_REG_DPDA_PREG_448_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_448_Q_REG_DPDA_PREG_448_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_448_Q_REG_DPDA_PREG_448_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_448_Q_REG_ADDR (0x0005C004u)
#define CSL_DFE_DPDA_DPDA_PREG_448_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_449_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_449_ie : 31;
#else 
    Uint32 dpda_preg_449_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_449_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_449_IE_REG_DPDA_PREG_449_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_449_IE_REG_DPDA_PREG_449_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_449_IE_REG_DPDA_PREG_449_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_449_IE_REG_ADDR (0x0005C100u)
#define CSL_DFE_DPDA_DPDA_PREG_449_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_449_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_449_q : 23;
#else 
    Uint32 dpda_preg_449_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_449_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_449_Q_REG_DPDA_PREG_449_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_449_Q_REG_DPDA_PREG_449_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_449_Q_REG_DPDA_PREG_449_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_449_Q_REG_ADDR (0x0005C104u)
#define CSL_DFE_DPDA_DPDA_PREG_449_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_450_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_450_ie : 31;
#else 
    Uint32 dpda_preg_450_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_450_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_450_IE_REG_DPDA_PREG_450_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_450_IE_REG_DPDA_PREG_450_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_450_IE_REG_DPDA_PREG_450_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_450_IE_REG_ADDR (0x0005C200u)
#define CSL_DFE_DPDA_DPDA_PREG_450_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_450_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_450_q : 23;
#else 
    Uint32 dpda_preg_450_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_450_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_450_Q_REG_DPDA_PREG_450_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_450_Q_REG_DPDA_PREG_450_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_450_Q_REG_DPDA_PREG_450_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_450_Q_REG_ADDR (0x0005C204u)
#define CSL_DFE_DPDA_DPDA_PREG_450_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_451_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_451_ie : 31;
#else 
    Uint32 dpda_preg_451_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_451_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_451_IE_REG_DPDA_PREG_451_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_451_IE_REG_DPDA_PREG_451_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_451_IE_REG_DPDA_PREG_451_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_451_IE_REG_ADDR (0x0005C300u)
#define CSL_DFE_DPDA_DPDA_PREG_451_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_451_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_451_q : 23;
#else 
    Uint32 dpda_preg_451_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_451_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_451_Q_REG_DPDA_PREG_451_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_451_Q_REG_DPDA_PREG_451_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_451_Q_REG_DPDA_PREG_451_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_451_Q_REG_ADDR (0x0005C304u)
#define CSL_DFE_DPDA_DPDA_PREG_451_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_452_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_452_ie : 31;
#else 
    Uint32 dpda_preg_452_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_452_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_452_IE_REG_DPDA_PREG_452_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_452_IE_REG_DPDA_PREG_452_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_452_IE_REG_DPDA_PREG_452_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_452_IE_REG_ADDR (0x0005C400u)
#define CSL_DFE_DPDA_DPDA_PREG_452_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_452_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_452_q : 23;
#else 
    Uint32 dpda_preg_452_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_452_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_452_Q_REG_DPDA_PREG_452_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_452_Q_REG_DPDA_PREG_452_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_452_Q_REG_DPDA_PREG_452_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_452_Q_REG_ADDR (0x0005C404u)
#define CSL_DFE_DPDA_DPDA_PREG_452_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_453_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_453_ie : 31;
#else 
    Uint32 dpda_preg_453_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_453_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_453_IE_REG_DPDA_PREG_453_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_453_IE_REG_DPDA_PREG_453_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_453_IE_REG_DPDA_PREG_453_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_453_IE_REG_ADDR (0x0005C500u)
#define CSL_DFE_DPDA_DPDA_PREG_453_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_453_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_453_q : 23;
#else 
    Uint32 dpda_preg_453_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_453_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_453_Q_REG_DPDA_PREG_453_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_453_Q_REG_DPDA_PREG_453_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_453_Q_REG_DPDA_PREG_453_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_453_Q_REG_ADDR (0x0005C504u)
#define CSL_DFE_DPDA_DPDA_PREG_453_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_454_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_454_ie : 31;
#else 
    Uint32 dpda_preg_454_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_454_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_454_IE_REG_DPDA_PREG_454_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_454_IE_REG_DPDA_PREG_454_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_454_IE_REG_DPDA_PREG_454_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_454_IE_REG_ADDR (0x0005C600u)
#define CSL_DFE_DPDA_DPDA_PREG_454_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_454_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_454_q : 23;
#else 
    Uint32 dpda_preg_454_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_454_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_454_Q_REG_DPDA_PREG_454_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_454_Q_REG_DPDA_PREG_454_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_454_Q_REG_DPDA_PREG_454_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_454_Q_REG_ADDR (0x0005C604u)
#define CSL_DFE_DPDA_DPDA_PREG_454_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_455_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_455_ie : 31;
#else 
    Uint32 dpda_preg_455_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_455_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_455_IE_REG_DPDA_PREG_455_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_455_IE_REG_DPDA_PREG_455_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_455_IE_REG_DPDA_PREG_455_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_455_IE_REG_ADDR (0x0005C700u)
#define CSL_DFE_DPDA_DPDA_PREG_455_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_455_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_455_q : 23;
#else 
    Uint32 dpda_preg_455_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_455_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_455_Q_REG_DPDA_PREG_455_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_455_Q_REG_DPDA_PREG_455_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_455_Q_REG_DPDA_PREG_455_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_455_Q_REG_ADDR (0x0005C704u)
#define CSL_DFE_DPDA_DPDA_PREG_455_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_456_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_456_ie : 31;
#else 
    Uint32 dpda_preg_456_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_456_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_456_IE_REG_DPDA_PREG_456_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_456_IE_REG_DPDA_PREG_456_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_456_IE_REG_DPDA_PREG_456_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_456_IE_REG_ADDR (0x0005C800u)
#define CSL_DFE_DPDA_DPDA_PREG_456_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_456_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_456_q : 23;
#else 
    Uint32 dpda_preg_456_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_456_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_456_Q_REG_DPDA_PREG_456_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_456_Q_REG_DPDA_PREG_456_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_456_Q_REG_DPDA_PREG_456_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_456_Q_REG_ADDR (0x0005C804u)
#define CSL_DFE_DPDA_DPDA_PREG_456_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_457_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_457_ie : 31;
#else 
    Uint32 dpda_preg_457_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_457_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_457_IE_REG_DPDA_PREG_457_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_457_IE_REG_DPDA_PREG_457_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_457_IE_REG_DPDA_PREG_457_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_457_IE_REG_ADDR (0x0005C900u)
#define CSL_DFE_DPDA_DPDA_PREG_457_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_457_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_457_q : 23;
#else 
    Uint32 dpda_preg_457_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_457_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_457_Q_REG_DPDA_PREG_457_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_457_Q_REG_DPDA_PREG_457_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_457_Q_REG_DPDA_PREG_457_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_457_Q_REG_ADDR (0x0005C904u)
#define CSL_DFE_DPDA_DPDA_PREG_457_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_458_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_458_ie : 31;
#else 
    Uint32 dpda_preg_458_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_458_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_458_IE_REG_DPDA_PREG_458_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_458_IE_REG_DPDA_PREG_458_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_458_IE_REG_DPDA_PREG_458_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_458_IE_REG_ADDR (0x0005CA00u)
#define CSL_DFE_DPDA_DPDA_PREG_458_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_458_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_458_q : 23;
#else 
    Uint32 dpda_preg_458_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_458_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_458_Q_REG_DPDA_PREG_458_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_458_Q_REG_DPDA_PREG_458_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_458_Q_REG_DPDA_PREG_458_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_458_Q_REG_ADDR (0x0005CA04u)
#define CSL_DFE_DPDA_DPDA_PREG_458_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_459_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_459_ie : 31;
#else 
    Uint32 dpda_preg_459_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_459_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_459_IE_REG_DPDA_PREG_459_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_459_IE_REG_DPDA_PREG_459_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_459_IE_REG_DPDA_PREG_459_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_459_IE_REG_ADDR (0x0005CB00u)
#define CSL_DFE_DPDA_DPDA_PREG_459_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_459_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_459_q : 23;
#else 
    Uint32 dpda_preg_459_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_459_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_459_Q_REG_DPDA_PREG_459_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_459_Q_REG_DPDA_PREG_459_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_459_Q_REG_DPDA_PREG_459_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_459_Q_REG_ADDR (0x0005CB04u)
#define CSL_DFE_DPDA_DPDA_PREG_459_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_460_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_460_ie : 31;
#else 
    Uint32 dpda_preg_460_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_460_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_460_IE_REG_DPDA_PREG_460_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_460_IE_REG_DPDA_PREG_460_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_460_IE_REG_DPDA_PREG_460_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_460_IE_REG_ADDR (0x0005CC00u)
#define CSL_DFE_DPDA_DPDA_PREG_460_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_460_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_460_q : 23;
#else 
    Uint32 dpda_preg_460_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_460_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_460_Q_REG_DPDA_PREG_460_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_460_Q_REG_DPDA_PREG_460_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_460_Q_REG_DPDA_PREG_460_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_460_Q_REG_ADDR (0x0005CC04u)
#define CSL_DFE_DPDA_DPDA_PREG_460_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_461_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_461_ie : 31;
#else 
    Uint32 dpda_preg_461_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_461_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_461_IE_REG_DPDA_PREG_461_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_461_IE_REG_DPDA_PREG_461_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_461_IE_REG_DPDA_PREG_461_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_461_IE_REG_ADDR (0x0005CD00u)
#define CSL_DFE_DPDA_DPDA_PREG_461_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_461_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_461_q : 23;
#else 
    Uint32 dpda_preg_461_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_461_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_461_Q_REG_DPDA_PREG_461_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_461_Q_REG_DPDA_PREG_461_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_461_Q_REG_DPDA_PREG_461_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_461_Q_REG_ADDR (0x0005CD04u)
#define CSL_DFE_DPDA_DPDA_PREG_461_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_462_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_462_ie : 31;
#else 
    Uint32 dpda_preg_462_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_462_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_462_IE_REG_DPDA_PREG_462_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_462_IE_REG_DPDA_PREG_462_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_462_IE_REG_DPDA_PREG_462_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_462_IE_REG_ADDR (0x0005CE00u)
#define CSL_DFE_DPDA_DPDA_PREG_462_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_462_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_462_q : 23;
#else 
    Uint32 dpda_preg_462_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_462_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_462_Q_REG_DPDA_PREG_462_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_462_Q_REG_DPDA_PREG_462_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_462_Q_REG_DPDA_PREG_462_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_462_Q_REG_ADDR (0x0005CE04u)
#define CSL_DFE_DPDA_DPDA_PREG_462_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_463_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_463_ie : 31;
#else 
    Uint32 dpda_preg_463_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_463_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_463_IE_REG_DPDA_PREG_463_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_463_IE_REG_DPDA_PREG_463_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_463_IE_REG_DPDA_PREG_463_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_463_IE_REG_ADDR (0x0005CF00u)
#define CSL_DFE_DPDA_DPDA_PREG_463_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_463_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_463_q : 23;
#else 
    Uint32 dpda_preg_463_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_463_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_463_Q_REG_DPDA_PREG_463_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_463_Q_REG_DPDA_PREG_463_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_463_Q_REG_DPDA_PREG_463_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_463_Q_REG_ADDR (0x0005CF04u)
#define CSL_DFE_DPDA_DPDA_PREG_463_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_464_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_464_ie : 31;
#else 
    Uint32 dpda_preg_464_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_464_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_464_IE_REG_DPDA_PREG_464_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_464_IE_REG_DPDA_PREG_464_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_464_IE_REG_DPDA_PREG_464_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_464_IE_REG_ADDR (0x0005D000u)
#define CSL_DFE_DPDA_DPDA_PREG_464_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_464_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_464_q : 23;
#else 
    Uint32 dpda_preg_464_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_464_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_464_Q_REG_DPDA_PREG_464_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_464_Q_REG_DPDA_PREG_464_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_464_Q_REG_DPDA_PREG_464_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_464_Q_REG_ADDR (0x0005D004u)
#define CSL_DFE_DPDA_DPDA_PREG_464_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_465_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_465_ie : 31;
#else 
    Uint32 dpda_preg_465_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_465_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_465_IE_REG_DPDA_PREG_465_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_465_IE_REG_DPDA_PREG_465_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_465_IE_REG_DPDA_PREG_465_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_465_IE_REG_ADDR (0x0005D100u)
#define CSL_DFE_DPDA_DPDA_PREG_465_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_465_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_465_q : 23;
#else 
    Uint32 dpda_preg_465_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_465_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_465_Q_REG_DPDA_PREG_465_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_465_Q_REG_DPDA_PREG_465_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_465_Q_REG_DPDA_PREG_465_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_465_Q_REG_ADDR (0x0005D104u)
#define CSL_DFE_DPDA_DPDA_PREG_465_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_466_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_466_ie : 31;
#else 
    Uint32 dpda_preg_466_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_466_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_466_IE_REG_DPDA_PREG_466_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_466_IE_REG_DPDA_PREG_466_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_466_IE_REG_DPDA_PREG_466_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_466_IE_REG_ADDR (0x0005D200u)
#define CSL_DFE_DPDA_DPDA_PREG_466_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_466_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_466_q : 23;
#else 
    Uint32 dpda_preg_466_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_466_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_466_Q_REG_DPDA_PREG_466_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_466_Q_REG_DPDA_PREG_466_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_466_Q_REG_DPDA_PREG_466_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_466_Q_REG_ADDR (0x0005D204u)
#define CSL_DFE_DPDA_DPDA_PREG_466_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_467_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_467_ie : 31;
#else 
    Uint32 dpda_preg_467_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_467_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_467_IE_REG_DPDA_PREG_467_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_467_IE_REG_DPDA_PREG_467_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_467_IE_REG_DPDA_PREG_467_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_467_IE_REG_ADDR (0x0005D300u)
#define CSL_DFE_DPDA_DPDA_PREG_467_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_467_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_467_q : 23;
#else 
    Uint32 dpda_preg_467_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_467_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_467_Q_REG_DPDA_PREG_467_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_467_Q_REG_DPDA_PREG_467_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_467_Q_REG_DPDA_PREG_467_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_467_Q_REG_ADDR (0x0005D304u)
#define CSL_DFE_DPDA_DPDA_PREG_467_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_468_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_468_ie : 31;
#else 
    Uint32 dpda_preg_468_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_468_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_468_IE_REG_DPDA_PREG_468_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_468_IE_REG_DPDA_PREG_468_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_468_IE_REG_DPDA_PREG_468_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_468_IE_REG_ADDR (0x0005D400u)
#define CSL_DFE_DPDA_DPDA_PREG_468_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_468_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_468_q : 23;
#else 
    Uint32 dpda_preg_468_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_468_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_468_Q_REG_DPDA_PREG_468_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_468_Q_REG_DPDA_PREG_468_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_468_Q_REG_DPDA_PREG_468_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_468_Q_REG_ADDR (0x0005D404u)
#define CSL_DFE_DPDA_DPDA_PREG_468_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_469_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_469_ie : 31;
#else 
    Uint32 dpda_preg_469_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_469_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_469_IE_REG_DPDA_PREG_469_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_469_IE_REG_DPDA_PREG_469_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_469_IE_REG_DPDA_PREG_469_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_469_IE_REG_ADDR (0x0005D500u)
#define CSL_DFE_DPDA_DPDA_PREG_469_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_469_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_469_q : 23;
#else 
    Uint32 dpda_preg_469_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_469_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_469_Q_REG_DPDA_PREG_469_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_469_Q_REG_DPDA_PREG_469_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_469_Q_REG_DPDA_PREG_469_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_469_Q_REG_ADDR (0x0005D504u)
#define CSL_DFE_DPDA_DPDA_PREG_469_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_470_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_470_ie : 31;
#else 
    Uint32 dpda_preg_470_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_470_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_470_IE_REG_DPDA_PREG_470_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_470_IE_REG_DPDA_PREG_470_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_470_IE_REG_DPDA_PREG_470_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_470_IE_REG_ADDR (0x0005D600u)
#define CSL_DFE_DPDA_DPDA_PREG_470_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_470_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_470_q : 23;
#else 
    Uint32 dpda_preg_470_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_470_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_470_Q_REG_DPDA_PREG_470_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_470_Q_REG_DPDA_PREG_470_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_470_Q_REG_DPDA_PREG_470_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_470_Q_REG_ADDR (0x0005D604u)
#define CSL_DFE_DPDA_DPDA_PREG_470_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_471_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_471_ie : 31;
#else 
    Uint32 dpda_preg_471_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_471_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_471_IE_REG_DPDA_PREG_471_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_471_IE_REG_DPDA_PREG_471_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_471_IE_REG_DPDA_PREG_471_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_471_IE_REG_ADDR (0x0005D700u)
#define CSL_DFE_DPDA_DPDA_PREG_471_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_471_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_471_q : 23;
#else 
    Uint32 dpda_preg_471_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_471_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_471_Q_REG_DPDA_PREG_471_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_471_Q_REG_DPDA_PREG_471_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_471_Q_REG_DPDA_PREG_471_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_471_Q_REG_ADDR (0x0005D704u)
#define CSL_DFE_DPDA_DPDA_PREG_471_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_472_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_472_ie : 31;
#else 
    Uint32 dpda_preg_472_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_472_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_472_IE_REG_DPDA_PREG_472_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_472_IE_REG_DPDA_PREG_472_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_472_IE_REG_DPDA_PREG_472_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_472_IE_REG_ADDR (0x0005D800u)
#define CSL_DFE_DPDA_DPDA_PREG_472_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_472_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_472_q : 23;
#else 
    Uint32 dpda_preg_472_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_472_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_472_Q_REG_DPDA_PREG_472_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_472_Q_REG_DPDA_PREG_472_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_472_Q_REG_DPDA_PREG_472_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_472_Q_REG_ADDR (0x0005D804u)
#define CSL_DFE_DPDA_DPDA_PREG_472_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_473_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_473_ie : 31;
#else 
    Uint32 dpda_preg_473_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_473_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_473_IE_REG_DPDA_PREG_473_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_473_IE_REG_DPDA_PREG_473_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_473_IE_REG_DPDA_PREG_473_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_473_IE_REG_ADDR (0x0005D900u)
#define CSL_DFE_DPDA_DPDA_PREG_473_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_473_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_473_q : 23;
#else 
    Uint32 dpda_preg_473_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_473_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_473_Q_REG_DPDA_PREG_473_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_473_Q_REG_DPDA_PREG_473_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_473_Q_REG_DPDA_PREG_473_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_473_Q_REG_ADDR (0x0005D904u)
#define CSL_DFE_DPDA_DPDA_PREG_473_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_474_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_474_ie : 31;
#else 
    Uint32 dpda_preg_474_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_474_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_474_IE_REG_DPDA_PREG_474_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_474_IE_REG_DPDA_PREG_474_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_474_IE_REG_DPDA_PREG_474_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_474_IE_REG_ADDR (0x0005DA00u)
#define CSL_DFE_DPDA_DPDA_PREG_474_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_474_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_474_q : 23;
#else 
    Uint32 dpda_preg_474_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_474_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_474_Q_REG_DPDA_PREG_474_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_474_Q_REG_DPDA_PREG_474_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_474_Q_REG_DPDA_PREG_474_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_474_Q_REG_ADDR (0x0005DA04u)
#define CSL_DFE_DPDA_DPDA_PREG_474_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_475_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_475_ie : 31;
#else 
    Uint32 dpda_preg_475_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_475_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_475_IE_REG_DPDA_PREG_475_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_475_IE_REG_DPDA_PREG_475_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_475_IE_REG_DPDA_PREG_475_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_475_IE_REG_ADDR (0x0005DB00u)
#define CSL_DFE_DPDA_DPDA_PREG_475_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_475_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_475_q : 23;
#else 
    Uint32 dpda_preg_475_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_475_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_475_Q_REG_DPDA_PREG_475_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_475_Q_REG_DPDA_PREG_475_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_475_Q_REG_DPDA_PREG_475_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_475_Q_REG_ADDR (0x0005DB04u)
#define CSL_DFE_DPDA_DPDA_PREG_475_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_476_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_476_ie : 31;
#else 
    Uint32 dpda_preg_476_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_476_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_476_IE_REG_DPDA_PREG_476_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_476_IE_REG_DPDA_PREG_476_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_476_IE_REG_DPDA_PREG_476_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_476_IE_REG_ADDR (0x0005DC00u)
#define CSL_DFE_DPDA_DPDA_PREG_476_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_476_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_476_q : 23;
#else 
    Uint32 dpda_preg_476_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_476_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_476_Q_REG_DPDA_PREG_476_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_476_Q_REG_DPDA_PREG_476_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_476_Q_REG_DPDA_PREG_476_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_476_Q_REG_ADDR (0x0005DC04u)
#define CSL_DFE_DPDA_DPDA_PREG_476_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_477_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_477_ie : 31;
#else 
    Uint32 dpda_preg_477_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_477_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_477_IE_REG_DPDA_PREG_477_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_477_IE_REG_DPDA_PREG_477_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_477_IE_REG_DPDA_PREG_477_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_477_IE_REG_ADDR (0x0005DD00u)
#define CSL_DFE_DPDA_DPDA_PREG_477_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_477_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_477_q : 23;
#else 
    Uint32 dpda_preg_477_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_477_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_477_Q_REG_DPDA_PREG_477_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_477_Q_REG_DPDA_PREG_477_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_477_Q_REG_DPDA_PREG_477_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_477_Q_REG_ADDR (0x0005DD04u)
#define CSL_DFE_DPDA_DPDA_PREG_477_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_478_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_478_ie : 31;
#else 
    Uint32 dpda_preg_478_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_478_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_478_IE_REG_DPDA_PREG_478_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_478_IE_REG_DPDA_PREG_478_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_478_IE_REG_DPDA_PREG_478_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_478_IE_REG_ADDR (0x0005DE00u)
#define CSL_DFE_DPDA_DPDA_PREG_478_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_478_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_478_q : 23;
#else 
    Uint32 dpda_preg_478_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_478_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_478_Q_REG_DPDA_PREG_478_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_478_Q_REG_DPDA_PREG_478_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_478_Q_REG_DPDA_PREG_478_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_478_Q_REG_ADDR (0x0005DE04u)
#define CSL_DFE_DPDA_DPDA_PREG_478_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_479_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_479_ie : 31;
#else 
    Uint32 dpda_preg_479_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_479_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_479_IE_REG_DPDA_PREG_479_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_479_IE_REG_DPDA_PREG_479_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_479_IE_REG_DPDA_PREG_479_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_479_IE_REG_ADDR (0x0005DF00u)
#define CSL_DFE_DPDA_DPDA_PREG_479_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_479_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_479_q : 23;
#else 
    Uint32 dpda_preg_479_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_479_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_479_Q_REG_DPDA_PREG_479_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_479_Q_REG_DPDA_PREG_479_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_479_Q_REG_DPDA_PREG_479_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_479_Q_REG_ADDR (0x0005DF04u)
#define CSL_DFE_DPDA_DPDA_PREG_479_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_480_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_480_ie : 31;
#else 
    Uint32 dpda_preg_480_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_480_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_480_IE_REG_DPDA_PREG_480_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_480_IE_REG_DPDA_PREG_480_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_480_IE_REG_DPDA_PREG_480_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_480_IE_REG_ADDR (0x0005E000u)
#define CSL_DFE_DPDA_DPDA_PREG_480_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_480_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_480_q : 23;
#else 
    Uint32 dpda_preg_480_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_480_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_480_Q_REG_DPDA_PREG_480_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_480_Q_REG_DPDA_PREG_480_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_480_Q_REG_DPDA_PREG_480_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_480_Q_REG_ADDR (0x0005E004u)
#define CSL_DFE_DPDA_DPDA_PREG_480_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_481_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_481_ie : 31;
#else 
    Uint32 dpda_preg_481_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_481_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_481_IE_REG_DPDA_PREG_481_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_481_IE_REG_DPDA_PREG_481_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_481_IE_REG_DPDA_PREG_481_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_481_IE_REG_ADDR (0x0005E100u)
#define CSL_DFE_DPDA_DPDA_PREG_481_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_481_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_481_q : 23;
#else 
    Uint32 dpda_preg_481_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_481_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_481_Q_REG_DPDA_PREG_481_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_481_Q_REG_DPDA_PREG_481_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_481_Q_REG_DPDA_PREG_481_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_481_Q_REG_ADDR (0x0005E104u)
#define CSL_DFE_DPDA_DPDA_PREG_481_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_482_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_482_ie : 31;
#else 
    Uint32 dpda_preg_482_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_482_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_482_IE_REG_DPDA_PREG_482_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_482_IE_REG_DPDA_PREG_482_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_482_IE_REG_DPDA_PREG_482_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_482_IE_REG_ADDR (0x0005E200u)
#define CSL_DFE_DPDA_DPDA_PREG_482_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_482_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_482_q : 23;
#else 
    Uint32 dpda_preg_482_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_482_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_482_Q_REG_DPDA_PREG_482_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_482_Q_REG_DPDA_PREG_482_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_482_Q_REG_DPDA_PREG_482_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_482_Q_REG_ADDR (0x0005E204u)
#define CSL_DFE_DPDA_DPDA_PREG_482_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_483_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_483_ie : 31;
#else 
    Uint32 dpda_preg_483_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_483_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_483_IE_REG_DPDA_PREG_483_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_483_IE_REG_DPDA_PREG_483_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_483_IE_REG_DPDA_PREG_483_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_483_IE_REG_ADDR (0x0005E300u)
#define CSL_DFE_DPDA_DPDA_PREG_483_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_483_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_483_q : 23;
#else 
    Uint32 dpda_preg_483_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_483_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_483_Q_REG_DPDA_PREG_483_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_483_Q_REG_DPDA_PREG_483_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_483_Q_REG_DPDA_PREG_483_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_483_Q_REG_ADDR (0x0005E304u)
#define CSL_DFE_DPDA_DPDA_PREG_483_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_484_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_484_ie : 31;
#else 
    Uint32 dpda_preg_484_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_484_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_484_IE_REG_DPDA_PREG_484_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_484_IE_REG_DPDA_PREG_484_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_484_IE_REG_DPDA_PREG_484_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_484_IE_REG_ADDR (0x0005E400u)
#define CSL_DFE_DPDA_DPDA_PREG_484_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_484_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_484_q : 23;
#else 
    Uint32 dpda_preg_484_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_484_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_484_Q_REG_DPDA_PREG_484_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_484_Q_REG_DPDA_PREG_484_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_484_Q_REG_DPDA_PREG_484_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_484_Q_REG_ADDR (0x0005E404u)
#define CSL_DFE_DPDA_DPDA_PREG_484_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_485_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_485_ie : 31;
#else 
    Uint32 dpda_preg_485_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_485_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_485_IE_REG_DPDA_PREG_485_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_485_IE_REG_DPDA_PREG_485_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_485_IE_REG_DPDA_PREG_485_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_485_IE_REG_ADDR (0x0005E500u)
#define CSL_DFE_DPDA_DPDA_PREG_485_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_485_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_485_q : 23;
#else 
    Uint32 dpda_preg_485_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_485_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_485_Q_REG_DPDA_PREG_485_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_485_Q_REG_DPDA_PREG_485_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_485_Q_REG_DPDA_PREG_485_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_485_Q_REG_ADDR (0x0005E504u)
#define CSL_DFE_DPDA_DPDA_PREG_485_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_486_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_486_ie : 31;
#else 
    Uint32 dpda_preg_486_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_486_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_486_IE_REG_DPDA_PREG_486_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_486_IE_REG_DPDA_PREG_486_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_486_IE_REG_DPDA_PREG_486_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_486_IE_REG_ADDR (0x0005E600u)
#define CSL_DFE_DPDA_DPDA_PREG_486_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_486_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_486_q : 23;
#else 
    Uint32 dpda_preg_486_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_486_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_486_Q_REG_DPDA_PREG_486_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_486_Q_REG_DPDA_PREG_486_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_486_Q_REG_DPDA_PREG_486_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_486_Q_REG_ADDR (0x0005E604u)
#define CSL_DFE_DPDA_DPDA_PREG_486_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_487_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_487_ie : 31;
#else 
    Uint32 dpda_preg_487_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_487_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_487_IE_REG_DPDA_PREG_487_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_487_IE_REG_DPDA_PREG_487_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_487_IE_REG_DPDA_PREG_487_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_487_IE_REG_ADDR (0x0005E700u)
#define CSL_DFE_DPDA_DPDA_PREG_487_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_487_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_487_q : 23;
#else 
    Uint32 dpda_preg_487_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_487_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_487_Q_REG_DPDA_PREG_487_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_487_Q_REG_DPDA_PREG_487_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_487_Q_REG_DPDA_PREG_487_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_487_Q_REG_ADDR (0x0005E704u)
#define CSL_DFE_DPDA_DPDA_PREG_487_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_488_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_488_ie : 31;
#else 
    Uint32 dpda_preg_488_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_488_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_488_IE_REG_DPDA_PREG_488_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_488_IE_REG_DPDA_PREG_488_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_488_IE_REG_DPDA_PREG_488_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_488_IE_REG_ADDR (0x0005E800u)
#define CSL_DFE_DPDA_DPDA_PREG_488_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_488_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_488_q : 23;
#else 
    Uint32 dpda_preg_488_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_488_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_488_Q_REG_DPDA_PREG_488_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_488_Q_REG_DPDA_PREG_488_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_488_Q_REG_DPDA_PREG_488_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_488_Q_REG_ADDR (0x0005E804u)
#define CSL_DFE_DPDA_DPDA_PREG_488_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_489_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_489_ie : 31;
#else 
    Uint32 dpda_preg_489_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_489_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_489_IE_REG_DPDA_PREG_489_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_489_IE_REG_DPDA_PREG_489_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_489_IE_REG_DPDA_PREG_489_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_489_IE_REG_ADDR (0x0005E900u)
#define CSL_DFE_DPDA_DPDA_PREG_489_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_489_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_489_q : 23;
#else 
    Uint32 dpda_preg_489_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_489_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_489_Q_REG_DPDA_PREG_489_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_489_Q_REG_DPDA_PREG_489_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_489_Q_REG_DPDA_PREG_489_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_489_Q_REG_ADDR (0x0005E904u)
#define CSL_DFE_DPDA_DPDA_PREG_489_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_490_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_490_ie : 31;
#else 
    Uint32 dpda_preg_490_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_490_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_490_IE_REG_DPDA_PREG_490_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_490_IE_REG_DPDA_PREG_490_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_490_IE_REG_DPDA_PREG_490_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_490_IE_REG_ADDR (0x0005EA00u)
#define CSL_DFE_DPDA_DPDA_PREG_490_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_490_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_490_q : 23;
#else 
    Uint32 dpda_preg_490_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_490_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_490_Q_REG_DPDA_PREG_490_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_490_Q_REG_DPDA_PREG_490_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_490_Q_REG_DPDA_PREG_490_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_490_Q_REG_ADDR (0x0005EA04u)
#define CSL_DFE_DPDA_DPDA_PREG_490_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_491_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_491_ie : 31;
#else 
    Uint32 dpda_preg_491_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_491_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_491_IE_REG_DPDA_PREG_491_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_491_IE_REG_DPDA_PREG_491_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_491_IE_REG_DPDA_PREG_491_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_491_IE_REG_ADDR (0x0005EB00u)
#define CSL_DFE_DPDA_DPDA_PREG_491_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_491_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_491_q : 23;
#else 
    Uint32 dpda_preg_491_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_491_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_491_Q_REG_DPDA_PREG_491_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_491_Q_REG_DPDA_PREG_491_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_491_Q_REG_DPDA_PREG_491_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_491_Q_REG_ADDR (0x0005EB04u)
#define CSL_DFE_DPDA_DPDA_PREG_491_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_492_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_492_ie : 31;
#else 
    Uint32 dpda_preg_492_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_492_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_492_IE_REG_DPDA_PREG_492_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_492_IE_REG_DPDA_PREG_492_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_492_IE_REG_DPDA_PREG_492_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_492_IE_REG_ADDR (0x0005EC00u)
#define CSL_DFE_DPDA_DPDA_PREG_492_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_492_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_492_q : 23;
#else 
    Uint32 dpda_preg_492_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_492_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_492_Q_REG_DPDA_PREG_492_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_492_Q_REG_DPDA_PREG_492_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_492_Q_REG_DPDA_PREG_492_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_492_Q_REG_ADDR (0x0005EC04u)
#define CSL_DFE_DPDA_DPDA_PREG_492_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_493_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_493_ie : 31;
#else 
    Uint32 dpda_preg_493_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_493_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_493_IE_REG_DPDA_PREG_493_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_493_IE_REG_DPDA_PREG_493_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_493_IE_REG_DPDA_PREG_493_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_493_IE_REG_ADDR (0x0005ED00u)
#define CSL_DFE_DPDA_DPDA_PREG_493_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_493_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_493_q : 23;
#else 
    Uint32 dpda_preg_493_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_493_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_493_Q_REG_DPDA_PREG_493_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_493_Q_REG_DPDA_PREG_493_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_493_Q_REG_DPDA_PREG_493_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_493_Q_REG_ADDR (0x0005ED04u)
#define CSL_DFE_DPDA_DPDA_PREG_493_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_494_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_494_ie : 31;
#else 
    Uint32 dpda_preg_494_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_494_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_494_IE_REG_DPDA_PREG_494_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_494_IE_REG_DPDA_PREG_494_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_494_IE_REG_DPDA_PREG_494_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_494_IE_REG_ADDR (0x0005EE00u)
#define CSL_DFE_DPDA_DPDA_PREG_494_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_494_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_494_q : 23;
#else 
    Uint32 dpda_preg_494_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_494_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_494_Q_REG_DPDA_PREG_494_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_494_Q_REG_DPDA_PREG_494_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_494_Q_REG_DPDA_PREG_494_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_494_Q_REG_ADDR (0x0005EE04u)
#define CSL_DFE_DPDA_DPDA_PREG_494_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_495_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_495_ie : 31;
#else 
    Uint32 dpda_preg_495_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_495_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_495_IE_REG_DPDA_PREG_495_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_495_IE_REG_DPDA_PREG_495_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_495_IE_REG_DPDA_PREG_495_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_495_IE_REG_ADDR (0x0005EF00u)
#define CSL_DFE_DPDA_DPDA_PREG_495_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_495_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_495_q : 23;
#else 
    Uint32 dpda_preg_495_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_495_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_495_Q_REG_DPDA_PREG_495_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_495_Q_REG_DPDA_PREG_495_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_495_Q_REG_DPDA_PREG_495_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_495_Q_REG_ADDR (0x0005EF04u)
#define CSL_DFE_DPDA_DPDA_PREG_495_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_496_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_496_ie : 31;
#else 
    Uint32 dpda_preg_496_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_496_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_496_IE_REG_DPDA_PREG_496_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_496_IE_REG_DPDA_PREG_496_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_496_IE_REG_DPDA_PREG_496_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_496_IE_REG_ADDR (0x0005F000u)
#define CSL_DFE_DPDA_DPDA_PREG_496_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_496_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_496_q : 23;
#else 
    Uint32 dpda_preg_496_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_496_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_496_Q_REG_DPDA_PREG_496_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_496_Q_REG_DPDA_PREG_496_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_496_Q_REG_DPDA_PREG_496_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_496_Q_REG_ADDR (0x0005F004u)
#define CSL_DFE_DPDA_DPDA_PREG_496_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_497_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_497_ie : 31;
#else 
    Uint32 dpda_preg_497_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_497_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_497_IE_REG_DPDA_PREG_497_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_497_IE_REG_DPDA_PREG_497_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_497_IE_REG_DPDA_PREG_497_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_497_IE_REG_ADDR (0x0005F100u)
#define CSL_DFE_DPDA_DPDA_PREG_497_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_497_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_497_q : 23;
#else 
    Uint32 dpda_preg_497_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_497_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_497_Q_REG_DPDA_PREG_497_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_497_Q_REG_DPDA_PREG_497_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_497_Q_REG_DPDA_PREG_497_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_497_Q_REG_ADDR (0x0005F104u)
#define CSL_DFE_DPDA_DPDA_PREG_497_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_498_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_498_ie : 31;
#else 
    Uint32 dpda_preg_498_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_498_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_498_IE_REG_DPDA_PREG_498_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_498_IE_REG_DPDA_PREG_498_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_498_IE_REG_DPDA_PREG_498_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_498_IE_REG_ADDR (0x0005F200u)
#define CSL_DFE_DPDA_DPDA_PREG_498_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_498_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_498_q : 23;
#else 
    Uint32 dpda_preg_498_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_498_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_498_Q_REG_DPDA_PREG_498_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_498_Q_REG_DPDA_PREG_498_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_498_Q_REG_DPDA_PREG_498_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_498_Q_REG_ADDR (0x0005F204u)
#define CSL_DFE_DPDA_DPDA_PREG_498_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_499_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_499_ie : 31;
#else 
    Uint32 dpda_preg_499_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_499_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_499_IE_REG_DPDA_PREG_499_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_499_IE_REG_DPDA_PREG_499_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_499_IE_REG_DPDA_PREG_499_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_499_IE_REG_ADDR (0x0005F300u)
#define CSL_DFE_DPDA_DPDA_PREG_499_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_499_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_499_q : 23;
#else 
    Uint32 dpda_preg_499_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_499_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_499_Q_REG_DPDA_PREG_499_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_499_Q_REG_DPDA_PREG_499_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_499_Q_REG_DPDA_PREG_499_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_499_Q_REG_ADDR (0x0005F304u)
#define CSL_DFE_DPDA_DPDA_PREG_499_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_500_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_500_ie : 31;
#else 
    Uint32 dpda_preg_500_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_500_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_500_IE_REG_DPDA_PREG_500_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_500_IE_REG_DPDA_PREG_500_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_500_IE_REG_DPDA_PREG_500_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_500_IE_REG_ADDR (0x0005F400u)
#define CSL_DFE_DPDA_DPDA_PREG_500_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_500_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_500_q : 23;
#else 
    Uint32 dpda_preg_500_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_500_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_500_Q_REG_DPDA_PREG_500_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_500_Q_REG_DPDA_PREG_500_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_500_Q_REG_DPDA_PREG_500_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_500_Q_REG_ADDR (0x0005F404u)
#define CSL_DFE_DPDA_DPDA_PREG_500_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_501_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_501_ie : 31;
#else 
    Uint32 dpda_preg_501_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_501_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_501_IE_REG_DPDA_PREG_501_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_501_IE_REG_DPDA_PREG_501_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_501_IE_REG_DPDA_PREG_501_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_501_IE_REG_ADDR (0x0005F500u)
#define CSL_DFE_DPDA_DPDA_PREG_501_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_501_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_501_q : 23;
#else 
    Uint32 dpda_preg_501_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_501_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_501_Q_REG_DPDA_PREG_501_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_501_Q_REG_DPDA_PREG_501_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_501_Q_REG_DPDA_PREG_501_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_501_Q_REG_ADDR (0x0005F504u)
#define CSL_DFE_DPDA_DPDA_PREG_501_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_502_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_502_ie : 31;
#else 
    Uint32 dpda_preg_502_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_502_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_502_IE_REG_DPDA_PREG_502_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_502_IE_REG_DPDA_PREG_502_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_502_IE_REG_DPDA_PREG_502_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_502_IE_REG_ADDR (0x0005F600u)
#define CSL_DFE_DPDA_DPDA_PREG_502_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_502_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_502_q : 23;
#else 
    Uint32 dpda_preg_502_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_502_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_502_Q_REG_DPDA_PREG_502_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_502_Q_REG_DPDA_PREG_502_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_502_Q_REG_DPDA_PREG_502_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_502_Q_REG_ADDR (0x0005F604u)
#define CSL_DFE_DPDA_DPDA_PREG_502_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_503_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_503_ie : 31;
#else 
    Uint32 dpda_preg_503_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_503_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_503_IE_REG_DPDA_PREG_503_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_503_IE_REG_DPDA_PREG_503_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_503_IE_REG_DPDA_PREG_503_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_503_IE_REG_ADDR (0x0005F700u)
#define CSL_DFE_DPDA_DPDA_PREG_503_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_503_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_503_q : 23;
#else 
    Uint32 dpda_preg_503_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_503_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_503_Q_REG_DPDA_PREG_503_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_503_Q_REG_DPDA_PREG_503_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_503_Q_REG_DPDA_PREG_503_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_503_Q_REG_ADDR (0x0005F704u)
#define CSL_DFE_DPDA_DPDA_PREG_503_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_504_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_504_ie : 31;
#else 
    Uint32 dpda_preg_504_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_504_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_504_IE_REG_DPDA_PREG_504_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_504_IE_REG_DPDA_PREG_504_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_504_IE_REG_DPDA_PREG_504_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_504_IE_REG_ADDR (0x0005F800u)
#define CSL_DFE_DPDA_DPDA_PREG_504_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_504_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_504_q : 23;
#else 
    Uint32 dpda_preg_504_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_504_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_504_Q_REG_DPDA_PREG_504_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_504_Q_REG_DPDA_PREG_504_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_504_Q_REG_DPDA_PREG_504_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_504_Q_REG_ADDR (0x0005F804u)
#define CSL_DFE_DPDA_DPDA_PREG_504_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_505_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_505_ie : 31;
#else 
    Uint32 dpda_preg_505_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_505_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_505_IE_REG_DPDA_PREG_505_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_505_IE_REG_DPDA_PREG_505_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_505_IE_REG_DPDA_PREG_505_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_505_IE_REG_ADDR (0x0005F900u)
#define CSL_DFE_DPDA_DPDA_PREG_505_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_505_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_505_q : 23;
#else 
    Uint32 dpda_preg_505_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_505_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_505_Q_REG_DPDA_PREG_505_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_505_Q_REG_DPDA_PREG_505_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_505_Q_REG_DPDA_PREG_505_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_505_Q_REG_ADDR (0x0005F904u)
#define CSL_DFE_DPDA_DPDA_PREG_505_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_506_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_506_ie : 31;
#else 
    Uint32 dpda_preg_506_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_506_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_506_IE_REG_DPDA_PREG_506_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_506_IE_REG_DPDA_PREG_506_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_506_IE_REG_DPDA_PREG_506_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_506_IE_REG_ADDR (0x0005FA00u)
#define CSL_DFE_DPDA_DPDA_PREG_506_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_506_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_506_q : 23;
#else 
    Uint32 dpda_preg_506_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_506_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_506_Q_REG_DPDA_PREG_506_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_506_Q_REG_DPDA_PREG_506_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_506_Q_REG_DPDA_PREG_506_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_506_Q_REG_ADDR (0x0005FA04u)
#define CSL_DFE_DPDA_DPDA_PREG_506_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_507_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_507_ie : 31;
#else 
    Uint32 dpda_preg_507_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_507_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_507_IE_REG_DPDA_PREG_507_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_507_IE_REG_DPDA_PREG_507_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_507_IE_REG_DPDA_PREG_507_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_507_IE_REG_ADDR (0x0005FB00u)
#define CSL_DFE_DPDA_DPDA_PREG_507_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_507_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_507_q : 23;
#else 
    Uint32 dpda_preg_507_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_507_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_507_Q_REG_DPDA_PREG_507_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_507_Q_REG_DPDA_PREG_507_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_507_Q_REG_DPDA_PREG_507_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_507_Q_REG_ADDR (0x0005FB04u)
#define CSL_DFE_DPDA_DPDA_PREG_507_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_508_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_508_ie : 31;
#else 
    Uint32 dpda_preg_508_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_508_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_508_IE_REG_DPDA_PREG_508_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_508_IE_REG_DPDA_PREG_508_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_508_IE_REG_DPDA_PREG_508_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_508_IE_REG_ADDR (0x0005FC00u)
#define CSL_DFE_DPDA_DPDA_PREG_508_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_508_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_508_q : 23;
#else 
    Uint32 dpda_preg_508_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_508_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_508_Q_REG_DPDA_PREG_508_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_508_Q_REG_DPDA_PREG_508_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_508_Q_REG_DPDA_PREG_508_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_508_Q_REG_ADDR (0x0005FC04u)
#define CSL_DFE_DPDA_DPDA_PREG_508_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_509_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_509_ie : 31;
#else 
    Uint32 dpda_preg_509_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_509_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_509_IE_REG_DPDA_PREG_509_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_509_IE_REG_DPDA_PREG_509_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_509_IE_REG_DPDA_PREG_509_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_509_IE_REG_ADDR (0x0005FD00u)
#define CSL_DFE_DPDA_DPDA_PREG_509_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_509_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_509_q : 23;
#else 
    Uint32 dpda_preg_509_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_509_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_509_Q_REG_DPDA_PREG_509_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_509_Q_REG_DPDA_PREG_509_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_509_Q_REG_DPDA_PREG_509_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_509_Q_REG_ADDR (0x0005FD04u)
#define CSL_DFE_DPDA_DPDA_PREG_509_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_510_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_510_ie : 31;
#else 
    Uint32 dpda_preg_510_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_510_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_510_IE_REG_DPDA_PREG_510_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_510_IE_REG_DPDA_PREG_510_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_510_IE_REG_DPDA_PREG_510_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_510_IE_REG_ADDR (0x0005FE00u)
#define CSL_DFE_DPDA_DPDA_PREG_510_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_510_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_510_q : 23;
#else 
    Uint32 dpda_preg_510_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_510_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_510_Q_REG_DPDA_PREG_510_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_510_Q_REG_DPDA_PREG_510_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_510_Q_REG_DPDA_PREG_510_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_510_Q_REG_ADDR (0x0005FE04u)
#define CSL_DFE_DPDA_DPDA_PREG_510_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_511_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_511_ie : 31;
#else 
    Uint32 dpda_preg_511_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_511_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_511_IE_REG_DPDA_PREG_511_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_511_IE_REG_DPDA_PREG_511_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_511_IE_REG_DPDA_PREG_511_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_511_IE_REG_ADDR (0x0005FF00u)
#define CSL_DFE_DPDA_DPDA_PREG_511_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_511_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_511_q : 23;
#else 
    Uint32 dpda_preg_511_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_511_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_511_Q_REG_DPDA_PREG_511_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_511_Q_REG_DPDA_PREG_511_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_511_Q_REG_DPDA_PREG_511_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_511_Q_REG_ADDR (0x0005FF04u)
#define CSL_DFE_DPDA_DPDA_PREG_511_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_512_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_512_ie : 31;
#else 
    Uint32 dpda_preg_512_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_512_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_512_IE_REG_DPDA_PREG_512_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_512_IE_REG_DPDA_PREG_512_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_512_IE_REG_DPDA_PREG_512_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_512_IE_REG_ADDR (0x00060000u)
#define CSL_DFE_DPDA_DPDA_PREG_512_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_512_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_512_q : 23;
#else 
    Uint32 dpda_preg_512_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_512_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_512_Q_REG_DPDA_PREG_512_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_512_Q_REG_DPDA_PREG_512_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_512_Q_REG_DPDA_PREG_512_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_512_Q_REG_ADDR (0x00060004u)
#define CSL_DFE_DPDA_DPDA_PREG_512_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_513_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_513_ie : 31;
#else 
    Uint32 dpda_preg_513_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_513_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_513_IE_REG_DPDA_PREG_513_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_513_IE_REG_DPDA_PREG_513_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_513_IE_REG_DPDA_PREG_513_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_513_IE_REG_ADDR (0x00060100u)
#define CSL_DFE_DPDA_DPDA_PREG_513_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_513_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_513_q : 23;
#else 
    Uint32 dpda_preg_513_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_513_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_513_Q_REG_DPDA_PREG_513_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_513_Q_REG_DPDA_PREG_513_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_513_Q_REG_DPDA_PREG_513_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_513_Q_REG_ADDR (0x00060104u)
#define CSL_DFE_DPDA_DPDA_PREG_513_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_514_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_514_ie : 31;
#else 
    Uint32 dpda_preg_514_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_514_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_514_IE_REG_DPDA_PREG_514_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_514_IE_REG_DPDA_PREG_514_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_514_IE_REG_DPDA_PREG_514_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_514_IE_REG_ADDR (0x00060200u)
#define CSL_DFE_DPDA_DPDA_PREG_514_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_514_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_514_q : 23;
#else 
    Uint32 dpda_preg_514_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_514_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_514_Q_REG_DPDA_PREG_514_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_514_Q_REG_DPDA_PREG_514_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_514_Q_REG_DPDA_PREG_514_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_514_Q_REG_ADDR (0x00060204u)
#define CSL_DFE_DPDA_DPDA_PREG_514_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_515_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_515_ie : 31;
#else 
    Uint32 dpda_preg_515_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_515_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_515_IE_REG_DPDA_PREG_515_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_515_IE_REG_DPDA_PREG_515_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_515_IE_REG_DPDA_PREG_515_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_515_IE_REG_ADDR (0x00060300u)
#define CSL_DFE_DPDA_DPDA_PREG_515_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_515_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_515_q : 23;
#else 
    Uint32 dpda_preg_515_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_515_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_515_Q_REG_DPDA_PREG_515_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_515_Q_REG_DPDA_PREG_515_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_515_Q_REG_DPDA_PREG_515_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_515_Q_REG_ADDR (0x00060304u)
#define CSL_DFE_DPDA_DPDA_PREG_515_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_516_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_516_ie : 31;
#else 
    Uint32 dpda_preg_516_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_516_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_516_IE_REG_DPDA_PREG_516_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_516_IE_REG_DPDA_PREG_516_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_516_IE_REG_DPDA_PREG_516_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_516_IE_REG_ADDR (0x00060400u)
#define CSL_DFE_DPDA_DPDA_PREG_516_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_516_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_516_q : 23;
#else 
    Uint32 dpda_preg_516_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_516_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_516_Q_REG_DPDA_PREG_516_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_516_Q_REG_DPDA_PREG_516_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_516_Q_REG_DPDA_PREG_516_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_516_Q_REG_ADDR (0x00060404u)
#define CSL_DFE_DPDA_DPDA_PREG_516_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_517_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_517_ie : 31;
#else 
    Uint32 dpda_preg_517_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_517_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_517_IE_REG_DPDA_PREG_517_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_517_IE_REG_DPDA_PREG_517_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_517_IE_REG_DPDA_PREG_517_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_517_IE_REG_ADDR (0x00060500u)
#define CSL_DFE_DPDA_DPDA_PREG_517_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_517_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_517_q : 23;
#else 
    Uint32 dpda_preg_517_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_517_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_517_Q_REG_DPDA_PREG_517_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_517_Q_REG_DPDA_PREG_517_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_517_Q_REG_DPDA_PREG_517_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_517_Q_REG_ADDR (0x00060504u)
#define CSL_DFE_DPDA_DPDA_PREG_517_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_518_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_518_ie : 31;
#else 
    Uint32 dpda_preg_518_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_518_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_518_IE_REG_DPDA_PREG_518_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_518_IE_REG_DPDA_PREG_518_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_518_IE_REG_DPDA_PREG_518_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_518_IE_REG_ADDR (0x00060600u)
#define CSL_DFE_DPDA_DPDA_PREG_518_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_518_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_518_q : 23;
#else 
    Uint32 dpda_preg_518_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_518_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_518_Q_REG_DPDA_PREG_518_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_518_Q_REG_DPDA_PREG_518_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_518_Q_REG_DPDA_PREG_518_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_518_Q_REG_ADDR (0x00060604u)
#define CSL_DFE_DPDA_DPDA_PREG_518_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_519_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_519_ie : 31;
#else 
    Uint32 dpda_preg_519_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_519_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_519_IE_REG_DPDA_PREG_519_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_519_IE_REG_DPDA_PREG_519_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_519_IE_REG_DPDA_PREG_519_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_519_IE_REG_ADDR (0x00060700u)
#define CSL_DFE_DPDA_DPDA_PREG_519_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_519_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_519_q : 23;
#else 
    Uint32 dpda_preg_519_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_519_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_519_Q_REG_DPDA_PREG_519_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_519_Q_REG_DPDA_PREG_519_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_519_Q_REG_DPDA_PREG_519_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_519_Q_REG_ADDR (0x00060704u)
#define CSL_DFE_DPDA_DPDA_PREG_519_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_520_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_520_ie : 31;
#else 
    Uint32 dpda_preg_520_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_520_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_520_IE_REG_DPDA_PREG_520_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_520_IE_REG_DPDA_PREG_520_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_520_IE_REG_DPDA_PREG_520_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_520_IE_REG_ADDR (0x00060800u)
#define CSL_DFE_DPDA_DPDA_PREG_520_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_520_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_520_q : 23;
#else 
    Uint32 dpda_preg_520_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_520_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_520_Q_REG_DPDA_PREG_520_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_520_Q_REG_DPDA_PREG_520_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_520_Q_REG_DPDA_PREG_520_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_520_Q_REG_ADDR (0x00060804u)
#define CSL_DFE_DPDA_DPDA_PREG_520_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_521_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_521_ie : 31;
#else 
    Uint32 dpda_preg_521_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_521_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_521_IE_REG_DPDA_PREG_521_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_521_IE_REG_DPDA_PREG_521_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_521_IE_REG_DPDA_PREG_521_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_521_IE_REG_ADDR (0x00060900u)
#define CSL_DFE_DPDA_DPDA_PREG_521_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_521_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_521_q : 23;
#else 
    Uint32 dpda_preg_521_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_521_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_521_Q_REG_DPDA_PREG_521_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_521_Q_REG_DPDA_PREG_521_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_521_Q_REG_DPDA_PREG_521_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_521_Q_REG_ADDR (0x00060904u)
#define CSL_DFE_DPDA_DPDA_PREG_521_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_522_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_522_ie : 31;
#else 
    Uint32 dpda_preg_522_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_522_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_522_IE_REG_DPDA_PREG_522_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_522_IE_REG_DPDA_PREG_522_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_522_IE_REG_DPDA_PREG_522_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_522_IE_REG_ADDR (0x00060A00u)
#define CSL_DFE_DPDA_DPDA_PREG_522_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_522_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_522_q : 23;
#else 
    Uint32 dpda_preg_522_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_522_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_522_Q_REG_DPDA_PREG_522_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_522_Q_REG_DPDA_PREG_522_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_522_Q_REG_DPDA_PREG_522_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_522_Q_REG_ADDR (0x00060A04u)
#define CSL_DFE_DPDA_DPDA_PREG_522_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_523_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_523_ie : 31;
#else 
    Uint32 dpda_preg_523_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_523_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_523_IE_REG_DPDA_PREG_523_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_523_IE_REG_DPDA_PREG_523_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_523_IE_REG_DPDA_PREG_523_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_523_IE_REG_ADDR (0x00060B00u)
#define CSL_DFE_DPDA_DPDA_PREG_523_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_523_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_523_q : 23;
#else 
    Uint32 dpda_preg_523_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_523_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_523_Q_REG_DPDA_PREG_523_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_523_Q_REG_DPDA_PREG_523_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_523_Q_REG_DPDA_PREG_523_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_523_Q_REG_ADDR (0x00060B04u)
#define CSL_DFE_DPDA_DPDA_PREG_523_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_524_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_524_ie : 31;
#else 
    Uint32 dpda_preg_524_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_524_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_524_IE_REG_DPDA_PREG_524_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_524_IE_REG_DPDA_PREG_524_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_524_IE_REG_DPDA_PREG_524_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_524_IE_REG_ADDR (0x00060C00u)
#define CSL_DFE_DPDA_DPDA_PREG_524_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_524_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_524_q : 23;
#else 
    Uint32 dpda_preg_524_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_524_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_524_Q_REG_DPDA_PREG_524_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_524_Q_REG_DPDA_PREG_524_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_524_Q_REG_DPDA_PREG_524_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_524_Q_REG_ADDR (0x00060C04u)
#define CSL_DFE_DPDA_DPDA_PREG_524_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_525_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_525_ie : 31;
#else 
    Uint32 dpda_preg_525_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_525_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_525_IE_REG_DPDA_PREG_525_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_525_IE_REG_DPDA_PREG_525_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_525_IE_REG_DPDA_PREG_525_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_525_IE_REG_ADDR (0x00060D00u)
#define CSL_DFE_DPDA_DPDA_PREG_525_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_525_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_525_q : 23;
#else 
    Uint32 dpda_preg_525_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_525_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_525_Q_REG_DPDA_PREG_525_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_525_Q_REG_DPDA_PREG_525_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_525_Q_REG_DPDA_PREG_525_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_525_Q_REG_ADDR (0x00060D04u)
#define CSL_DFE_DPDA_DPDA_PREG_525_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_526_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_526_ie : 31;
#else 
    Uint32 dpda_preg_526_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_526_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_526_IE_REG_DPDA_PREG_526_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_526_IE_REG_DPDA_PREG_526_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_526_IE_REG_DPDA_PREG_526_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_526_IE_REG_ADDR (0x00060E00u)
#define CSL_DFE_DPDA_DPDA_PREG_526_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_526_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_526_q : 23;
#else 
    Uint32 dpda_preg_526_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_526_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_526_Q_REG_DPDA_PREG_526_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_526_Q_REG_DPDA_PREG_526_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_526_Q_REG_DPDA_PREG_526_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_526_Q_REG_ADDR (0x00060E04u)
#define CSL_DFE_DPDA_DPDA_PREG_526_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_527_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_527_ie : 31;
#else 
    Uint32 dpda_preg_527_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_527_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_527_IE_REG_DPDA_PREG_527_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_527_IE_REG_DPDA_PREG_527_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_527_IE_REG_DPDA_PREG_527_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_527_IE_REG_ADDR (0x00060F00u)
#define CSL_DFE_DPDA_DPDA_PREG_527_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_527_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_527_q : 23;
#else 
    Uint32 dpda_preg_527_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_527_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_527_Q_REG_DPDA_PREG_527_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_527_Q_REG_DPDA_PREG_527_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_527_Q_REG_DPDA_PREG_527_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_527_Q_REG_ADDR (0x00060F04u)
#define CSL_DFE_DPDA_DPDA_PREG_527_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_528_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_528_ie : 31;
#else 
    Uint32 dpda_preg_528_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_528_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_528_IE_REG_DPDA_PREG_528_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_528_IE_REG_DPDA_PREG_528_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_528_IE_REG_DPDA_PREG_528_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_528_IE_REG_ADDR (0x00061000u)
#define CSL_DFE_DPDA_DPDA_PREG_528_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_528_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_528_q : 23;
#else 
    Uint32 dpda_preg_528_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_528_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_528_Q_REG_DPDA_PREG_528_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_528_Q_REG_DPDA_PREG_528_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_528_Q_REG_DPDA_PREG_528_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_528_Q_REG_ADDR (0x00061004u)
#define CSL_DFE_DPDA_DPDA_PREG_528_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_529_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_529_ie : 31;
#else 
    Uint32 dpda_preg_529_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_529_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_529_IE_REG_DPDA_PREG_529_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_529_IE_REG_DPDA_PREG_529_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_529_IE_REG_DPDA_PREG_529_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_529_IE_REG_ADDR (0x00061100u)
#define CSL_DFE_DPDA_DPDA_PREG_529_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_529_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_529_q : 23;
#else 
    Uint32 dpda_preg_529_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_529_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_529_Q_REG_DPDA_PREG_529_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_529_Q_REG_DPDA_PREG_529_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_529_Q_REG_DPDA_PREG_529_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_529_Q_REG_ADDR (0x00061104u)
#define CSL_DFE_DPDA_DPDA_PREG_529_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_530_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_530_ie : 31;
#else 
    Uint32 dpda_preg_530_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_530_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_530_IE_REG_DPDA_PREG_530_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_530_IE_REG_DPDA_PREG_530_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_530_IE_REG_DPDA_PREG_530_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_530_IE_REG_ADDR (0x00061200u)
#define CSL_DFE_DPDA_DPDA_PREG_530_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_530_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_530_q : 23;
#else 
    Uint32 dpda_preg_530_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_530_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_530_Q_REG_DPDA_PREG_530_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_530_Q_REG_DPDA_PREG_530_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_530_Q_REG_DPDA_PREG_530_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_530_Q_REG_ADDR (0x00061204u)
#define CSL_DFE_DPDA_DPDA_PREG_530_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_531_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_531_ie : 31;
#else 
    Uint32 dpda_preg_531_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_531_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_531_IE_REG_DPDA_PREG_531_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_531_IE_REG_DPDA_PREG_531_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_531_IE_REG_DPDA_PREG_531_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_531_IE_REG_ADDR (0x00061300u)
#define CSL_DFE_DPDA_DPDA_PREG_531_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_531_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_531_q : 23;
#else 
    Uint32 dpda_preg_531_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_531_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_531_Q_REG_DPDA_PREG_531_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_531_Q_REG_DPDA_PREG_531_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_531_Q_REG_DPDA_PREG_531_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_531_Q_REG_ADDR (0x00061304u)
#define CSL_DFE_DPDA_DPDA_PREG_531_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_532_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_532_ie : 31;
#else 
    Uint32 dpda_preg_532_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_532_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_532_IE_REG_DPDA_PREG_532_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_532_IE_REG_DPDA_PREG_532_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_532_IE_REG_DPDA_PREG_532_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_532_IE_REG_ADDR (0x00061400u)
#define CSL_DFE_DPDA_DPDA_PREG_532_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_532_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_532_q : 23;
#else 
    Uint32 dpda_preg_532_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_532_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_532_Q_REG_DPDA_PREG_532_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_532_Q_REG_DPDA_PREG_532_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_532_Q_REG_DPDA_PREG_532_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_532_Q_REG_ADDR (0x00061404u)
#define CSL_DFE_DPDA_DPDA_PREG_532_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_533_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_533_ie : 31;
#else 
    Uint32 dpda_preg_533_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_533_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_533_IE_REG_DPDA_PREG_533_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_533_IE_REG_DPDA_PREG_533_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_533_IE_REG_DPDA_PREG_533_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_533_IE_REG_ADDR (0x00061500u)
#define CSL_DFE_DPDA_DPDA_PREG_533_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_533_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_533_q : 23;
#else 
    Uint32 dpda_preg_533_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_533_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_533_Q_REG_DPDA_PREG_533_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_533_Q_REG_DPDA_PREG_533_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_533_Q_REG_DPDA_PREG_533_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_533_Q_REG_ADDR (0x00061504u)
#define CSL_DFE_DPDA_DPDA_PREG_533_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_534_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_534_ie : 31;
#else 
    Uint32 dpda_preg_534_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_534_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_534_IE_REG_DPDA_PREG_534_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_534_IE_REG_DPDA_PREG_534_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_534_IE_REG_DPDA_PREG_534_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_534_IE_REG_ADDR (0x00061600u)
#define CSL_DFE_DPDA_DPDA_PREG_534_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_534_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_534_q : 23;
#else 
    Uint32 dpda_preg_534_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_534_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_534_Q_REG_DPDA_PREG_534_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_534_Q_REG_DPDA_PREG_534_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_534_Q_REG_DPDA_PREG_534_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_534_Q_REG_ADDR (0x00061604u)
#define CSL_DFE_DPDA_DPDA_PREG_534_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_535_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_535_ie : 31;
#else 
    Uint32 dpda_preg_535_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_535_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_535_IE_REG_DPDA_PREG_535_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_535_IE_REG_DPDA_PREG_535_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_535_IE_REG_DPDA_PREG_535_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_535_IE_REG_ADDR (0x00061700u)
#define CSL_DFE_DPDA_DPDA_PREG_535_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_535_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_535_q : 23;
#else 
    Uint32 dpda_preg_535_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_535_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_535_Q_REG_DPDA_PREG_535_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_535_Q_REG_DPDA_PREG_535_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_535_Q_REG_DPDA_PREG_535_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_535_Q_REG_ADDR (0x00061704u)
#define CSL_DFE_DPDA_DPDA_PREG_535_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_536_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_536_ie : 31;
#else 
    Uint32 dpda_preg_536_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_536_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_536_IE_REG_DPDA_PREG_536_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_536_IE_REG_DPDA_PREG_536_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_536_IE_REG_DPDA_PREG_536_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_536_IE_REG_ADDR (0x00061800u)
#define CSL_DFE_DPDA_DPDA_PREG_536_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_536_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_536_q : 23;
#else 
    Uint32 dpda_preg_536_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_536_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_536_Q_REG_DPDA_PREG_536_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_536_Q_REG_DPDA_PREG_536_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_536_Q_REG_DPDA_PREG_536_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_536_Q_REG_ADDR (0x00061804u)
#define CSL_DFE_DPDA_DPDA_PREG_536_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_537_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_537_ie : 31;
#else 
    Uint32 dpda_preg_537_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_537_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_537_IE_REG_DPDA_PREG_537_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_537_IE_REG_DPDA_PREG_537_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_537_IE_REG_DPDA_PREG_537_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_537_IE_REG_ADDR (0x00061900u)
#define CSL_DFE_DPDA_DPDA_PREG_537_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_537_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_537_q : 23;
#else 
    Uint32 dpda_preg_537_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_537_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_537_Q_REG_DPDA_PREG_537_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_537_Q_REG_DPDA_PREG_537_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_537_Q_REG_DPDA_PREG_537_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_537_Q_REG_ADDR (0x00061904u)
#define CSL_DFE_DPDA_DPDA_PREG_537_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_538_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_538_ie : 31;
#else 
    Uint32 dpda_preg_538_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_538_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_538_IE_REG_DPDA_PREG_538_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_538_IE_REG_DPDA_PREG_538_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_538_IE_REG_DPDA_PREG_538_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_538_IE_REG_ADDR (0x00061A00u)
#define CSL_DFE_DPDA_DPDA_PREG_538_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_538_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_538_q : 23;
#else 
    Uint32 dpda_preg_538_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_538_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_538_Q_REG_DPDA_PREG_538_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_538_Q_REG_DPDA_PREG_538_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_538_Q_REG_DPDA_PREG_538_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_538_Q_REG_ADDR (0x00061A04u)
#define CSL_DFE_DPDA_DPDA_PREG_538_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_539_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_539_ie : 31;
#else 
    Uint32 dpda_preg_539_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_539_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_539_IE_REG_DPDA_PREG_539_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_539_IE_REG_DPDA_PREG_539_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_539_IE_REG_DPDA_PREG_539_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_539_IE_REG_ADDR (0x00061B00u)
#define CSL_DFE_DPDA_DPDA_PREG_539_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_539_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_539_q : 23;
#else 
    Uint32 dpda_preg_539_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_539_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_539_Q_REG_DPDA_PREG_539_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_539_Q_REG_DPDA_PREG_539_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_539_Q_REG_DPDA_PREG_539_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_539_Q_REG_ADDR (0x00061B04u)
#define CSL_DFE_DPDA_DPDA_PREG_539_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_540_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_540_ie : 31;
#else 
    Uint32 dpda_preg_540_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_540_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_540_IE_REG_DPDA_PREG_540_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_540_IE_REG_DPDA_PREG_540_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_540_IE_REG_DPDA_PREG_540_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_540_IE_REG_ADDR (0x00061C00u)
#define CSL_DFE_DPDA_DPDA_PREG_540_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_540_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_540_q : 23;
#else 
    Uint32 dpda_preg_540_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_540_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_540_Q_REG_DPDA_PREG_540_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_540_Q_REG_DPDA_PREG_540_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_540_Q_REG_DPDA_PREG_540_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_540_Q_REG_ADDR (0x00061C04u)
#define CSL_DFE_DPDA_DPDA_PREG_540_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_541_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_541_ie : 31;
#else 
    Uint32 dpda_preg_541_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_541_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_541_IE_REG_DPDA_PREG_541_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_541_IE_REG_DPDA_PREG_541_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_541_IE_REG_DPDA_PREG_541_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_541_IE_REG_ADDR (0x00061D00u)
#define CSL_DFE_DPDA_DPDA_PREG_541_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_541_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_541_q : 23;
#else 
    Uint32 dpda_preg_541_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_541_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_541_Q_REG_DPDA_PREG_541_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_541_Q_REG_DPDA_PREG_541_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_541_Q_REG_DPDA_PREG_541_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_541_Q_REG_ADDR (0x00061D04u)
#define CSL_DFE_DPDA_DPDA_PREG_541_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_542_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_542_ie : 31;
#else 
    Uint32 dpda_preg_542_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_542_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_542_IE_REG_DPDA_PREG_542_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_542_IE_REG_DPDA_PREG_542_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_542_IE_REG_DPDA_PREG_542_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_542_IE_REG_ADDR (0x00061E00u)
#define CSL_DFE_DPDA_DPDA_PREG_542_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_542_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_542_q : 23;
#else 
    Uint32 dpda_preg_542_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_542_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_542_Q_REG_DPDA_PREG_542_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_542_Q_REG_DPDA_PREG_542_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_542_Q_REG_DPDA_PREG_542_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_542_Q_REG_ADDR (0x00061E04u)
#define CSL_DFE_DPDA_DPDA_PREG_542_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_543_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_543_ie : 31;
#else 
    Uint32 dpda_preg_543_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_543_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_543_IE_REG_DPDA_PREG_543_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_543_IE_REG_DPDA_PREG_543_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_543_IE_REG_DPDA_PREG_543_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_543_IE_REG_ADDR (0x00061F00u)
#define CSL_DFE_DPDA_DPDA_PREG_543_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_543_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_543_q : 23;
#else 
    Uint32 dpda_preg_543_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_543_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_543_Q_REG_DPDA_PREG_543_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_543_Q_REG_DPDA_PREG_543_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_543_Q_REG_DPDA_PREG_543_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_543_Q_REG_ADDR (0x00061F04u)
#define CSL_DFE_DPDA_DPDA_PREG_543_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_544_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_544_ie : 31;
#else 
    Uint32 dpda_preg_544_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_544_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_544_IE_REG_DPDA_PREG_544_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_544_IE_REG_DPDA_PREG_544_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_544_IE_REG_DPDA_PREG_544_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_544_IE_REG_ADDR (0x00062000u)
#define CSL_DFE_DPDA_DPDA_PREG_544_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_544_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_544_q : 23;
#else 
    Uint32 dpda_preg_544_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_544_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_544_Q_REG_DPDA_PREG_544_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_544_Q_REG_DPDA_PREG_544_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_544_Q_REG_DPDA_PREG_544_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_544_Q_REG_ADDR (0x00062004u)
#define CSL_DFE_DPDA_DPDA_PREG_544_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_545_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_545_ie : 31;
#else 
    Uint32 dpda_preg_545_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_545_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_545_IE_REG_DPDA_PREG_545_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_545_IE_REG_DPDA_PREG_545_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_545_IE_REG_DPDA_PREG_545_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_545_IE_REG_ADDR (0x00062100u)
#define CSL_DFE_DPDA_DPDA_PREG_545_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_545_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_545_q : 23;
#else 
    Uint32 dpda_preg_545_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_545_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_545_Q_REG_DPDA_PREG_545_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_545_Q_REG_DPDA_PREG_545_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_545_Q_REG_DPDA_PREG_545_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_545_Q_REG_ADDR (0x00062104u)
#define CSL_DFE_DPDA_DPDA_PREG_545_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_546_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_546_ie : 31;
#else 
    Uint32 dpda_preg_546_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_546_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_546_IE_REG_DPDA_PREG_546_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_546_IE_REG_DPDA_PREG_546_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_546_IE_REG_DPDA_PREG_546_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_546_IE_REG_ADDR (0x00062200u)
#define CSL_DFE_DPDA_DPDA_PREG_546_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_546_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_546_q : 23;
#else 
    Uint32 dpda_preg_546_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_546_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_546_Q_REG_DPDA_PREG_546_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_546_Q_REG_DPDA_PREG_546_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_546_Q_REG_DPDA_PREG_546_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_546_Q_REG_ADDR (0x00062204u)
#define CSL_DFE_DPDA_DPDA_PREG_546_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_547_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_547_ie : 31;
#else 
    Uint32 dpda_preg_547_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_547_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_547_IE_REG_DPDA_PREG_547_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_547_IE_REG_DPDA_PREG_547_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_547_IE_REG_DPDA_PREG_547_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_547_IE_REG_ADDR (0x00062300u)
#define CSL_DFE_DPDA_DPDA_PREG_547_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_547_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_547_q : 23;
#else 
    Uint32 dpda_preg_547_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_547_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_547_Q_REG_DPDA_PREG_547_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_547_Q_REG_DPDA_PREG_547_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_547_Q_REG_DPDA_PREG_547_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_547_Q_REG_ADDR (0x00062304u)
#define CSL_DFE_DPDA_DPDA_PREG_547_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_548_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_548_ie : 31;
#else 
    Uint32 dpda_preg_548_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_548_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_548_IE_REG_DPDA_PREG_548_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_548_IE_REG_DPDA_PREG_548_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_548_IE_REG_DPDA_PREG_548_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_548_IE_REG_ADDR (0x00062400u)
#define CSL_DFE_DPDA_DPDA_PREG_548_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_548_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_548_q : 23;
#else 
    Uint32 dpda_preg_548_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_548_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_548_Q_REG_DPDA_PREG_548_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_548_Q_REG_DPDA_PREG_548_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_548_Q_REG_DPDA_PREG_548_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_548_Q_REG_ADDR (0x00062404u)
#define CSL_DFE_DPDA_DPDA_PREG_548_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_549_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_549_ie : 31;
#else 
    Uint32 dpda_preg_549_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_549_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_549_IE_REG_DPDA_PREG_549_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_549_IE_REG_DPDA_PREG_549_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_549_IE_REG_DPDA_PREG_549_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_549_IE_REG_ADDR (0x00062500u)
#define CSL_DFE_DPDA_DPDA_PREG_549_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_549_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_549_q : 23;
#else 
    Uint32 dpda_preg_549_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_549_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_549_Q_REG_DPDA_PREG_549_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_549_Q_REG_DPDA_PREG_549_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_549_Q_REG_DPDA_PREG_549_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_549_Q_REG_ADDR (0x00062504u)
#define CSL_DFE_DPDA_DPDA_PREG_549_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_550_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_550_ie : 31;
#else 
    Uint32 dpda_preg_550_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_550_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_550_IE_REG_DPDA_PREG_550_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_550_IE_REG_DPDA_PREG_550_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_550_IE_REG_DPDA_PREG_550_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_550_IE_REG_ADDR (0x00062600u)
#define CSL_DFE_DPDA_DPDA_PREG_550_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_550_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_550_q : 23;
#else 
    Uint32 dpda_preg_550_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_550_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_550_Q_REG_DPDA_PREG_550_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_550_Q_REG_DPDA_PREG_550_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_550_Q_REG_DPDA_PREG_550_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_550_Q_REG_ADDR (0x00062604u)
#define CSL_DFE_DPDA_DPDA_PREG_550_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_551_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_551_ie : 31;
#else 
    Uint32 dpda_preg_551_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_551_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_551_IE_REG_DPDA_PREG_551_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_551_IE_REG_DPDA_PREG_551_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_551_IE_REG_DPDA_PREG_551_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_551_IE_REG_ADDR (0x00062700u)
#define CSL_DFE_DPDA_DPDA_PREG_551_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_551_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_551_q : 23;
#else 
    Uint32 dpda_preg_551_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_551_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_551_Q_REG_DPDA_PREG_551_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_551_Q_REG_DPDA_PREG_551_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_551_Q_REG_DPDA_PREG_551_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_551_Q_REG_ADDR (0x00062704u)
#define CSL_DFE_DPDA_DPDA_PREG_551_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_552_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_552_ie : 31;
#else 
    Uint32 dpda_preg_552_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_552_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_552_IE_REG_DPDA_PREG_552_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_552_IE_REG_DPDA_PREG_552_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_552_IE_REG_DPDA_PREG_552_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_552_IE_REG_ADDR (0x00062800u)
#define CSL_DFE_DPDA_DPDA_PREG_552_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_552_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_552_q : 23;
#else 
    Uint32 dpda_preg_552_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_552_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_552_Q_REG_DPDA_PREG_552_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_552_Q_REG_DPDA_PREG_552_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_552_Q_REG_DPDA_PREG_552_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_552_Q_REG_ADDR (0x00062804u)
#define CSL_DFE_DPDA_DPDA_PREG_552_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_553_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_553_ie : 31;
#else 
    Uint32 dpda_preg_553_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_553_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_553_IE_REG_DPDA_PREG_553_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_553_IE_REG_DPDA_PREG_553_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_553_IE_REG_DPDA_PREG_553_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_553_IE_REG_ADDR (0x00062900u)
#define CSL_DFE_DPDA_DPDA_PREG_553_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_553_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_553_q : 23;
#else 
    Uint32 dpda_preg_553_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_553_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_553_Q_REG_DPDA_PREG_553_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_553_Q_REG_DPDA_PREG_553_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_553_Q_REG_DPDA_PREG_553_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_553_Q_REG_ADDR (0x00062904u)
#define CSL_DFE_DPDA_DPDA_PREG_553_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_554_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_554_ie : 31;
#else 
    Uint32 dpda_preg_554_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_554_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_554_IE_REG_DPDA_PREG_554_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_554_IE_REG_DPDA_PREG_554_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_554_IE_REG_DPDA_PREG_554_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_554_IE_REG_ADDR (0x00062A00u)
#define CSL_DFE_DPDA_DPDA_PREG_554_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_554_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_554_q : 23;
#else 
    Uint32 dpda_preg_554_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_554_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_554_Q_REG_DPDA_PREG_554_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_554_Q_REG_DPDA_PREG_554_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_554_Q_REG_DPDA_PREG_554_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_554_Q_REG_ADDR (0x00062A04u)
#define CSL_DFE_DPDA_DPDA_PREG_554_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_555_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_555_ie : 31;
#else 
    Uint32 dpda_preg_555_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_555_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_555_IE_REG_DPDA_PREG_555_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_555_IE_REG_DPDA_PREG_555_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_555_IE_REG_DPDA_PREG_555_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_555_IE_REG_ADDR (0x00062B00u)
#define CSL_DFE_DPDA_DPDA_PREG_555_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_555_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_555_q : 23;
#else 
    Uint32 dpda_preg_555_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_555_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_555_Q_REG_DPDA_PREG_555_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_555_Q_REG_DPDA_PREG_555_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_555_Q_REG_DPDA_PREG_555_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_555_Q_REG_ADDR (0x00062B04u)
#define CSL_DFE_DPDA_DPDA_PREG_555_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_556_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_556_ie : 31;
#else 
    Uint32 dpda_preg_556_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_556_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_556_IE_REG_DPDA_PREG_556_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_556_IE_REG_DPDA_PREG_556_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_556_IE_REG_DPDA_PREG_556_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_556_IE_REG_ADDR (0x00062C00u)
#define CSL_DFE_DPDA_DPDA_PREG_556_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_556_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_556_q : 23;
#else 
    Uint32 dpda_preg_556_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_556_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_556_Q_REG_DPDA_PREG_556_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_556_Q_REG_DPDA_PREG_556_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_556_Q_REG_DPDA_PREG_556_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_556_Q_REG_ADDR (0x00062C04u)
#define CSL_DFE_DPDA_DPDA_PREG_556_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_557_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_557_ie : 31;
#else 
    Uint32 dpda_preg_557_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_557_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_557_IE_REG_DPDA_PREG_557_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_557_IE_REG_DPDA_PREG_557_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_557_IE_REG_DPDA_PREG_557_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_557_IE_REG_ADDR (0x00062D00u)
#define CSL_DFE_DPDA_DPDA_PREG_557_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_557_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_557_q : 23;
#else 
    Uint32 dpda_preg_557_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_557_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_557_Q_REG_DPDA_PREG_557_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_557_Q_REG_DPDA_PREG_557_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_557_Q_REG_DPDA_PREG_557_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_557_Q_REG_ADDR (0x00062D04u)
#define CSL_DFE_DPDA_DPDA_PREG_557_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_558_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_558_ie : 31;
#else 
    Uint32 dpda_preg_558_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_558_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_558_IE_REG_DPDA_PREG_558_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_558_IE_REG_DPDA_PREG_558_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_558_IE_REG_DPDA_PREG_558_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_558_IE_REG_ADDR (0x00062E00u)
#define CSL_DFE_DPDA_DPDA_PREG_558_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_558_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_558_q : 23;
#else 
    Uint32 dpda_preg_558_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_558_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_558_Q_REG_DPDA_PREG_558_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_558_Q_REG_DPDA_PREG_558_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_558_Q_REG_DPDA_PREG_558_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_558_Q_REG_ADDR (0x00062E04u)
#define CSL_DFE_DPDA_DPDA_PREG_558_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_559_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_559_ie : 31;
#else 
    Uint32 dpda_preg_559_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_559_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_559_IE_REG_DPDA_PREG_559_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_559_IE_REG_DPDA_PREG_559_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_559_IE_REG_DPDA_PREG_559_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_559_IE_REG_ADDR (0x00062F00u)
#define CSL_DFE_DPDA_DPDA_PREG_559_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_559_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_559_q : 23;
#else 
    Uint32 dpda_preg_559_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_559_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_559_Q_REG_DPDA_PREG_559_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_559_Q_REG_DPDA_PREG_559_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_559_Q_REG_DPDA_PREG_559_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_559_Q_REG_ADDR (0x00062F04u)
#define CSL_DFE_DPDA_DPDA_PREG_559_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_560_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_560_ie : 31;
#else 
    Uint32 dpda_preg_560_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_560_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_560_IE_REG_DPDA_PREG_560_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_560_IE_REG_DPDA_PREG_560_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_560_IE_REG_DPDA_PREG_560_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_560_IE_REG_ADDR (0x00063000u)
#define CSL_DFE_DPDA_DPDA_PREG_560_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_560_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_560_q : 23;
#else 
    Uint32 dpda_preg_560_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_560_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_560_Q_REG_DPDA_PREG_560_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_560_Q_REG_DPDA_PREG_560_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_560_Q_REG_DPDA_PREG_560_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_560_Q_REG_ADDR (0x00063004u)
#define CSL_DFE_DPDA_DPDA_PREG_560_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_561_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_561_ie : 31;
#else 
    Uint32 dpda_preg_561_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_561_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_561_IE_REG_DPDA_PREG_561_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_561_IE_REG_DPDA_PREG_561_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_561_IE_REG_DPDA_PREG_561_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_561_IE_REG_ADDR (0x00063100u)
#define CSL_DFE_DPDA_DPDA_PREG_561_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_561_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_561_q : 23;
#else 
    Uint32 dpda_preg_561_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_561_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_561_Q_REG_DPDA_PREG_561_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_561_Q_REG_DPDA_PREG_561_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_561_Q_REG_DPDA_PREG_561_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_561_Q_REG_ADDR (0x00063104u)
#define CSL_DFE_DPDA_DPDA_PREG_561_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_562_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_562_ie : 31;
#else 
    Uint32 dpda_preg_562_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_562_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_562_IE_REG_DPDA_PREG_562_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_562_IE_REG_DPDA_PREG_562_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_562_IE_REG_DPDA_PREG_562_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_562_IE_REG_ADDR (0x00063200u)
#define CSL_DFE_DPDA_DPDA_PREG_562_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_562_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_562_q : 23;
#else 
    Uint32 dpda_preg_562_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_562_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_562_Q_REG_DPDA_PREG_562_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_562_Q_REG_DPDA_PREG_562_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_562_Q_REG_DPDA_PREG_562_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_562_Q_REG_ADDR (0x00063204u)
#define CSL_DFE_DPDA_DPDA_PREG_562_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_563_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_563_ie : 31;
#else 
    Uint32 dpda_preg_563_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_563_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_563_IE_REG_DPDA_PREG_563_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_563_IE_REG_DPDA_PREG_563_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_563_IE_REG_DPDA_PREG_563_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_563_IE_REG_ADDR (0x00063300u)
#define CSL_DFE_DPDA_DPDA_PREG_563_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_563_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_563_q : 23;
#else 
    Uint32 dpda_preg_563_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_563_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_563_Q_REG_DPDA_PREG_563_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_563_Q_REG_DPDA_PREG_563_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_563_Q_REG_DPDA_PREG_563_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_563_Q_REG_ADDR (0x00063304u)
#define CSL_DFE_DPDA_DPDA_PREG_563_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_564_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_564_ie : 31;
#else 
    Uint32 dpda_preg_564_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_564_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_564_IE_REG_DPDA_PREG_564_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_564_IE_REG_DPDA_PREG_564_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_564_IE_REG_DPDA_PREG_564_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_564_IE_REG_ADDR (0x00063400u)
#define CSL_DFE_DPDA_DPDA_PREG_564_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_564_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_564_q : 23;
#else 
    Uint32 dpda_preg_564_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_564_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_564_Q_REG_DPDA_PREG_564_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_564_Q_REG_DPDA_PREG_564_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_564_Q_REG_DPDA_PREG_564_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_564_Q_REG_ADDR (0x00063404u)
#define CSL_DFE_DPDA_DPDA_PREG_564_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_565_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_565_ie : 31;
#else 
    Uint32 dpda_preg_565_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_565_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_565_IE_REG_DPDA_PREG_565_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_565_IE_REG_DPDA_PREG_565_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_565_IE_REG_DPDA_PREG_565_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_565_IE_REG_ADDR (0x00063500u)
#define CSL_DFE_DPDA_DPDA_PREG_565_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_565_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_565_q : 23;
#else 
    Uint32 dpda_preg_565_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_565_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_565_Q_REG_DPDA_PREG_565_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_565_Q_REG_DPDA_PREG_565_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_565_Q_REG_DPDA_PREG_565_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_565_Q_REG_ADDR (0x00063504u)
#define CSL_DFE_DPDA_DPDA_PREG_565_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_566_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_566_ie : 31;
#else 
    Uint32 dpda_preg_566_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_566_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_566_IE_REG_DPDA_PREG_566_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_566_IE_REG_DPDA_PREG_566_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_566_IE_REG_DPDA_PREG_566_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_566_IE_REG_ADDR (0x00063600u)
#define CSL_DFE_DPDA_DPDA_PREG_566_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_566_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_566_q : 23;
#else 
    Uint32 dpda_preg_566_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_566_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_566_Q_REG_DPDA_PREG_566_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_566_Q_REG_DPDA_PREG_566_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_566_Q_REG_DPDA_PREG_566_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_566_Q_REG_ADDR (0x00063604u)
#define CSL_DFE_DPDA_DPDA_PREG_566_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_567_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_567_ie : 31;
#else 
    Uint32 dpda_preg_567_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_567_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_567_IE_REG_DPDA_PREG_567_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_567_IE_REG_DPDA_PREG_567_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_567_IE_REG_DPDA_PREG_567_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_567_IE_REG_ADDR (0x00063700u)
#define CSL_DFE_DPDA_DPDA_PREG_567_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_567_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_567_q : 23;
#else 
    Uint32 dpda_preg_567_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_567_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_567_Q_REG_DPDA_PREG_567_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_567_Q_REG_DPDA_PREG_567_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_567_Q_REG_DPDA_PREG_567_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_567_Q_REG_ADDR (0x00063704u)
#define CSL_DFE_DPDA_DPDA_PREG_567_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_568_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_568_ie : 31;
#else 
    Uint32 dpda_preg_568_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_568_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_568_IE_REG_DPDA_PREG_568_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_568_IE_REG_DPDA_PREG_568_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_568_IE_REG_DPDA_PREG_568_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_568_IE_REG_ADDR (0x00063800u)
#define CSL_DFE_DPDA_DPDA_PREG_568_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_568_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_568_q : 23;
#else 
    Uint32 dpda_preg_568_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_568_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_568_Q_REG_DPDA_PREG_568_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_568_Q_REG_DPDA_PREG_568_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_568_Q_REG_DPDA_PREG_568_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_568_Q_REG_ADDR (0x00063804u)
#define CSL_DFE_DPDA_DPDA_PREG_568_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_569_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_569_ie : 31;
#else 
    Uint32 dpda_preg_569_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_569_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_569_IE_REG_DPDA_PREG_569_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_569_IE_REG_DPDA_PREG_569_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_569_IE_REG_DPDA_PREG_569_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_569_IE_REG_ADDR (0x00063900u)
#define CSL_DFE_DPDA_DPDA_PREG_569_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_569_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_569_q : 23;
#else 
    Uint32 dpda_preg_569_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_569_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_569_Q_REG_DPDA_PREG_569_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_569_Q_REG_DPDA_PREG_569_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_569_Q_REG_DPDA_PREG_569_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_569_Q_REG_ADDR (0x00063904u)
#define CSL_DFE_DPDA_DPDA_PREG_569_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_570_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_570_ie : 31;
#else 
    Uint32 dpda_preg_570_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_570_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_570_IE_REG_DPDA_PREG_570_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_570_IE_REG_DPDA_PREG_570_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_570_IE_REG_DPDA_PREG_570_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_570_IE_REG_ADDR (0x00063A00u)
#define CSL_DFE_DPDA_DPDA_PREG_570_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_570_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_570_q : 23;
#else 
    Uint32 dpda_preg_570_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_570_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_570_Q_REG_DPDA_PREG_570_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_570_Q_REG_DPDA_PREG_570_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_570_Q_REG_DPDA_PREG_570_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_570_Q_REG_ADDR (0x00063A04u)
#define CSL_DFE_DPDA_DPDA_PREG_570_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_571_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_571_ie : 31;
#else 
    Uint32 dpda_preg_571_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_571_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_571_IE_REG_DPDA_PREG_571_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_571_IE_REG_DPDA_PREG_571_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_571_IE_REG_DPDA_PREG_571_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_571_IE_REG_ADDR (0x00063B00u)
#define CSL_DFE_DPDA_DPDA_PREG_571_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_571_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_571_q : 23;
#else 
    Uint32 dpda_preg_571_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_571_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_571_Q_REG_DPDA_PREG_571_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_571_Q_REG_DPDA_PREG_571_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_571_Q_REG_DPDA_PREG_571_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_571_Q_REG_ADDR (0x00063B04u)
#define CSL_DFE_DPDA_DPDA_PREG_571_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_572_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_572_ie : 31;
#else 
    Uint32 dpda_preg_572_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_572_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_572_IE_REG_DPDA_PREG_572_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_572_IE_REG_DPDA_PREG_572_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_572_IE_REG_DPDA_PREG_572_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_572_IE_REG_ADDR (0x00063C00u)
#define CSL_DFE_DPDA_DPDA_PREG_572_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_572_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_572_q : 23;
#else 
    Uint32 dpda_preg_572_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_572_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_572_Q_REG_DPDA_PREG_572_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_572_Q_REG_DPDA_PREG_572_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_572_Q_REG_DPDA_PREG_572_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_572_Q_REG_ADDR (0x00063C04u)
#define CSL_DFE_DPDA_DPDA_PREG_572_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_573_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_573_ie : 31;
#else 
    Uint32 dpda_preg_573_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_573_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_573_IE_REG_DPDA_PREG_573_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_573_IE_REG_DPDA_PREG_573_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_573_IE_REG_DPDA_PREG_573_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_573_IE_REG_ADDR (0x00063D00u)
#define CSL_DFE_DPDA_DPDA_PREG_573_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_573_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_573_q : 23;
#else 
    Uint32 dpda_preg_573_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_573_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_573_Q_REG_DPDA_PREG_573_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_573_Q_REG_DPDA_PREG_573_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_573_Q_REG_DPDA_PREG_573_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_573_Q_REG_ADDR (0x00063D04u)
#define CSL_DFE_DPDA_DPDA_PREG_573_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_574_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_574_ie : 31;
#else 
    Uint32 dpda_preg_574_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_574_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_574_IE_REG_DPDA_PREG_574_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_574_IE_REG_DPDA_PREG_574_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_574_IE_REG_DPDA_PREG_574_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_574_IE_REG_ADDR (0x00063E00u)
#define CSL_DFE_DPDA_DPDA_PREG_574_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_574_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_574_q : 23;
#else 
    Uint32 dpda_preg_574_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_574_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_574_Q_REG_DPDA_PREG_574_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_574_Q_REG_DPDA_PREG_574_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_574_Q_REG_DPDA_PREG_574_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_574_Q_REG_ADDR (0x00063E04u)
#define CSL_DFE_DPDA_DPDA_PREG_574_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_575_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_575_ie : 31;
#else 
    Uint32 dpda_preg_575_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_575_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_575_IE_REG_DPDA_PREG_575_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_575_IE_REG_DPDA_PREG_575_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_575_IE_REG_DPDA_PREG_575_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_575_IE_REG_ADDR (0x00063F00u)
#define CSL_DFE_DPDA_DPDA_PREG_575_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_575_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_575_q : 23;
#else 
    Uint32 dpda_preg_575_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_575_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_575_Q_REG_DPDA_PREG_575_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_575_Q_REG_DPDA_PREG_575_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_575_Q_REG_DPDA_PREG_575_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_575_Q_REG_ADDR (0x00063F04u)
#define CSL_DFE_DPDA_DPDA_PREG_575_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_576_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_576_ie : 31;
#else 
    Uint32 dpda_preg_576_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_576_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_576_IE_REG_DPDA_PREG_576_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_576_IE_REG_DPDA_PREG_576_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_576_IE_REG_DPDA_PREG_576_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_576_IE_REG_ADDR (0x00064000u)
#define CSL_DFE_DPDA_DPDA_PREG_576_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_576_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_576_q : 23;
#else 
    Uint32 dpda_preg_576_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_576_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_576_Q_REG_DPDA_PREG_576_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_576_Q_REG_DPDA_PREG_576_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_576_Q_REG_DPDA_PREG_576_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_576_Q_REG_ADDR (0x00064004u)
#define CSL_DFE_DPDA_DPDA_PREG_576_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_577_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_577_ie : 31;
#else 
    Uint32 dpda_preg_577_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_577_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_577_IE_REG_DPDA_PREG_577_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_577_IE_REG_DPDA_PREG_577_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_577_IE_REG_DPDA_PREG_577_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_577_IE_REG_ADDR (0x00064100u)
#define CSL_DFE_DPDA_DPDA_PREG_577_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_577_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_577_q : 23;
#else 
    Uint32 dpda_preg_577_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_577_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_577_Q_REG_DPDA_PREG_577_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_577_Q_REG_DPDA_PREG_577_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_577_Q_REG_DPDA_PREG_577_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_577_Q_REG_ADDR (0x00064104u)
#define CSL_DFE_DPDA_DPDA_PREG_577_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_578_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_578_ie : 31;
#else 
    Uint32 dpda_preg_578_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_578_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_578_IE_REG_DPDA_PREG_578_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_578_IE_REG_DPDA_PREG_578_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_578_IE_REG_DPDA_PREG_578_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_578_IE_REG_ADDR (0x00064200u)
#define CSL_DFE_DPDA_DPDA_PREG_578_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_578_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_578_q : 23;
#else 
    Uint32 dpda_preg_578_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_578_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_578_Q_REG_DPDA_PREG_578_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_578_Q_REG_DPDA_PREG_578_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_578_Q_REG_DPDA_PREG_578_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_578_Q_REG_ADDR (0x00064204u)
#define CSL_DFE_DPDA_DPDA_PREG_578_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_579_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_579_ie : 31;
#else 
    Uint32 dpda_preg_579_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_579_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_579_IE_REG_DPDA_PREG_579_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_579_IE_REG_DPDA_PREG_579_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_579_IE_REG_DPDA_PREG_579_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_579_IE_REG_ADDR (0x00064300u)
#define CSL_DFE_DPDA_DPDA_PREG_579_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_579_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_579_q : 23;
#else 
    Uint32 dpda_preg_579_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_579_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_579_Q_REG_DPDA_PREG_579_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_579_Q_REG_DPDA_PREG_579_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_579_Q_REG_DPDA_PREG_579_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_579_Q_REG_ADDR (0x00064304u)
#define CSL_DFE_DPDA_DPDA_PREG_579_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_580_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_580_ie : 31;
#else 
    Uint32 dpda_preg_580_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_580_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_580_IE_REG_DPDA_PREG_580_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_580_IE_REG_DPDA_PREG_580_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_580_IE_REG_DPDA_PREG_580_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_580_IE_REG_ADDR (0x00064400u)
#define CSL_DFE_DPDA_DPDA_PREG_580_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_580_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_580_q : 23;
#else 
    Uint32 dpda_preg_580_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_580_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_580_Q_REG_DPDA_PREG_580_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_580_Q_REG_DPDA_PREG_580_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_580_Q_REG_DPDA_PREG_580_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_580_Q_REG_ADDR (0x00064404u)
#define CSL_DFE_DPDA_DPDA_PREG_580_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_581_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_581_ie : 31;
#else 
    Uint32 dpda_preg_581_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_581_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_581_IE_REG_DPDA_PREG_581_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_581_IE_REG_DPDA_PREG_581_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_581_IE_REG_DPDA_PREG_581_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_581_IE_REG_ADDR (0x00064500u)
#define CSL_DFE_DPDA_DPDA_PREG_581_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_581_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_581_q : 23;
#else 
    Uint32 dpda_preg_581_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_581_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_581_Q_REG_DPDA_PREG_581_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_581_Q_REG_DPDA_PREG_581_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_581_Q_REG_DPDA_PREG_581_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_581_Q_REG_ADDR (0x00064504u)
#define CSL_DFE_DPDA_DPDA_PREG_581_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_582_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_582_ie : 31;
#else 
    Uint32 dpda_preg_582_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_582_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_582_IE_REG_DPDA_PREG_582_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_582_IE_REG_DPDA_PREG_582_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_582_IE_REG_DPDA_PREG_582_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_582_IE_REG_ADDR (0x00064600u)
#define CSL_DFE_DPDA_DPDA_PREG_582_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_582_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_582_q : 23;
#else 
    Uint32 dpda_preg_582_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_582_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_582_Q_REG_DPDA_PREG_582_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_582_Q_REG_DPDA_PREG_582_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_582_Q_REG_DPDA_PREG_582_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_582_Q_REG_ADDR (0x00064604u)
#define CSL_DFE_DPDA_DPDA_PREG_582_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_583_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_583_ie : 31;
#else 
    Uint32 dpda_preg_583_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_583_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_583_IE_REG_DPDA_PREG_583_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_583_IE_REG_DPDA_PREG_583_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_583_IE_REG_DPDA_PREG_583_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_583_IE_REG_ADDR (0x00064700u)
#define CSL_DFE_DPDA_DPDA_PREG_583_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_583_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_583_q : 23;
#else 
    Uint32 dpda_preg_583_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_583_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_583_Q_REG_DPDA_PREG_583_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_583_Q_REG_DPDA_PREG_583_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_583_Q_REG_DPDA_PREG_583_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_583_Q_REG_ADDR (0x00064704u)
#define CSL_DFE_DPDA_DPDA_PREG_583_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_584_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_584_ie : 31;
#else 
    Uint32 dpda_preg_584_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_584_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_584_IE_REG_DPDA_PREG_584_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_584_IE_REG_DPDA_PREG_584_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_584_IE_REG_DPDA_PREG_584_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_584_IE_REG_ADDR (0x00064800u)
#define CSL_DFE_DPDA_DPDA_PREG_584_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_584_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_584_q : 23;
#else 
    Uint32 dpda_preg_584_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_584_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_584_Q_REG_DPDA_PREG_584_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_584_Q_REG_DPDA_PREG_584_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_584_Q_REG_DPDA_PREG_584_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_584_Q_REG_ADDR (0x00064804u)
#define CSL_DFE_DPDA_DPDA_PREG_584_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_585_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_585_ie : 31;
#else 
    Uint32 dpda_preg_585_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_585_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_585_IE_REG_DPDA_PREG_585_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_585_IE_REG_DPDA_PREG_585_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_585_IE_REG_DPDA_PREG_585_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_585_IE_REG_ADDR (0x00064900u)
#define CSL_DFE_DPDA_DPDA_PREG_585_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_585_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_585_q : 23;
#else 
    Uint32 dpda_preg_585_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_585_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_585_Q_REG_DPDA_PREG_585_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_585_Q_REG_DPDA_PREG_585_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_585_Q_REG_DPDA_PREG_585_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_585_Q_REG_ADDR (0x00064904u)
#define CSL_DFE_DPDA_DPDA_PREG_585_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_586_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_586_ie : 31;
#else 
    Uint32 dpda_preg_586_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_586_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_586_IE_REG_DPDA_PREG_586_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_586_IE_REG_DPDA_PREG_586_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_586_IE_REG_DPDA_PREG_586_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_586_IE_REG_ADDR (0x00064A00u)
#define CSL_DFE_DPDA_DPDA_PREG_586_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_586_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_586_q : 23;
#else 
    Uint32 dpda_preg_586_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_586_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_586_Q_REG_DPDA_PREG_586_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_586_Q_REG_DPDA_PREG_586_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_586_Q_REG_DPDA_PREG_586_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_586_Q_REG_ADDR (0x00064A04u)
#define CSL_DFE_DPDA_DPDA_PREG_586_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_587_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_587_ie : 31;
#else 
    Uint32 dpda_preg_587_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_587_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_587_IE_REG_DPDA_PREG_587_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_587_IE_REG_DPDA_PREG_587_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_587_IE_REG_DPDA_PREG_587_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_587_IE_REG_ADDR (0x00064B00u)
#define CSL_DFE_DPDA_DPDA_PREG_587_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_587_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_587_q : 23;
#else 
    Uint32 dpda_preg_587_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_587_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_587_Q_REG_DPDA_PREG_587_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_587_Q_REG_DPDA_PREG_587_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_587_Q_REG_DPDA_PREG_587_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_587_Q_REG_ADDR (0x00064B04u)
#define CSL_DFE_DPDA_DPDA_PREG_587_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_588_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_588_ie : 31;
#else 
    Uint32 dpda_preg_588_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_588_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_588_IE_REG_DPDA_PREG_588_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_588_IE_REG_DPDA_PREG_588_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_588_IE_REG_DPDA_PREG_588_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_588_IE_REG_ADDR (0x00064C00u)
#define CSL_DFE_DPDA_DPDA_PREG_588_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_588_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_588_q : 23;
#else 
    Uint32 dpda_preg_588_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_588_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_588_Q_REG_DPDA_PREG_588_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_588_Q_REG_DPDA_PREG_588_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_588_Q_REG_DPDA_PREG_588_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_588_Q_REG_ADDR (0x00064C04u)
#define CSL_DFE_DPDA_DPDA_PREG_588_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_589_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_589_ie : 31;
#else 
    Uint32 dpda_preg_589_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_589_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_589_IE_REG_DPDA_PREG_589_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_589_IE_REG_DPDA_PREG_589_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_589_IE_REG_DPDA_PREG_589_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_589_IE_REG_ADDR (0x00064D00u)
#define CSL_DFE_DPDA_DPDA_PREG_589_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_589_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_589_q : 23;
#else 
    Uint32 dpda_preg_589_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_589_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_589_Q_REG_DPDA_PREG_589_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_589_Q_REG_DPDA_PREG_589_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_589_Q_REG_DPDA_PREG_589_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_589_Q_REG_ADDR (0x00064D04u)
#define CSL_DFE_DPDA_DPDA_PREG_589_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_590_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_590_ie : 31;
#else 
    Uint32 dpda_preg_590_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_590_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_590_IE_REG_DPDA_PREG_590_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_590_IE_REG_DPDA_PREG_590_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_590_IE_REG_DPDA_PREG_590_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_590_IE_REG_ADDR (0x00064E00u)
#define CSL_DFE_DPDA_DPDA_PREG_590_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_590_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_590_q : 23;
#else 
    Uint32 dpda_preg_590_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_590_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_590_Q_REG_DPDA_PREG_590_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_590_Q_REG_DPDA_PREG_590_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_590_Q_REG_DPDA_PREG_590_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_590_Q_REG_ADDR (0x00064E04u)
#define CSL_DFE_DPDA_DPDA_PREG_590_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_591_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_591_ie : 31;
#else 
    Uint32 dpda_preg_591_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_591_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_591_IE_REG_DPDA_PREG_591_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_591_IE_REG_DPDA_PREG_591_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_591_IE_REG_DPDA_PREG_591_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_591_IE_REG_ADDR (0x00064F00u)
#define CSL_DFE_DPDA_DPDA_PREG_591_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_591_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_591_q : 23;
#else 
    Uint32 dpda_preg_591_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_591_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_591_Q_REG_DPDA_PREG_591_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_591_Q_REG_DPDA_PREG_591_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_591_Q_REG_DPDA_PREG_591_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_591_Q_REG_ADDR (0x00064F04u)
#define CSL_DFE_DPDA_DPDA_PREG_591_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_592_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_592_ie : 31;
#else 
    Uint32 dpda_preg_592_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_592_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_592_IE_REG_DPDA_PREG_592_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_592_IE_REG_DPDA_PREG_592_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_592_IE_REG_DPDA_PREG_592_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_592_IE_REG_ADDR (0x00065000u)
#define CSL_DFE_DPDA_DPDA_PREG_592_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_592_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_592_q : 23;
#else 
    Uint32 dpda_preg_592_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_592_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_592_Q_REG_DPDA_PREG_592_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_592_Q_REG_DPDA_PREG_592_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_592_Q_REG_DPDA_PREG_592_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_592_Q_REG_ADDR (0x00065004u)
#define CSL_DFE_DPDA_DPDA_PREG_592_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_593_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_593_ie : 31;
#else 
    Uint32 dpda_preg_593_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_593_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_593_IE_REG_DPDA_PREG_593_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_593_IE_REG_DPDA_PREG_593_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_593_IE_REG_DPDA_PREG_593_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_593_IE_REG_ADDR (0x00065100u)
#define CSL_DFE_DPDA_DPDA_PREG_593_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_593_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_593_q : 23;
#else 
    Uint32 dpda_preg_593_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_593_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_593_Q_REG_DPDA_PREG_593_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_593_Q_REG_DPDA_PREG_593_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_593_Q_REG_DPDA_PREG_593_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_593_Q_REG_ADDR (0x00065104u)
#define CSL_DFE_DPDA_DPDA_PREG_593_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_594_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_594_ie : 31;
#else 
    Uint32 dpda_preg_594_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_594_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_594_IE_REG_DPDA_PREG_594_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_594_IE_REG_DPDA_PREG_594_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_594_IE_REG_DPDA_PREG_594_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_594_IE_REG_ADDR (0x00065200u)
#define CSL_DFE_DPDA_DPDA_PREG_594_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_594_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_594_q : 23;
#else 
    Uint32 dpda_preg_594_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_594_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_594_Q_REG_DPDA_PREG_594_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_594_Q_REG_DPDA_PREG_594_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_594_Q_REG_DPDA_PREG_594_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_594_Q_REG_ADDR (0x00065204u)
#define CSL_DFE_DPDA_DPDA_PREG_594_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_595_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_595_ie : 31;
#else 
    Uint32 dpda_preg_595_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_595_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_595_IE_REG_DPDA_PREG_595_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_595_IE_REG_DPDA_PREG_595_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_595_IE_REG_DPDA_PREG_595_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_595_IE_REG_ADDR (0x00065300u)
#define CSL_DFE_DPDA_DPDA_PREG_595_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_595_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_595_q : 23;
#else 
    Uint32 dpda_preg_595_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_595_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_595_Q_REG_DPDA_PREG_595_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_595_Q_REG_DPDA_PREG_595_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_595_Q_REG_DPDA_PREG_595_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_595_Q_REG_ADDR (0x00065304u)
#define CSL_DFE_DPDA_DPDA_PREG_595_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_596_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_596_ie : 31;
#else 
    Uint32 dpda_preg_596_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_596_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_596_IE_REG_DPDA_PREG_596_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_596_IE_REG_DPDA_PREG_596_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_596_IE_REG_DPDA_PREG_596_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_596_IE_REG_ADDR (0x00065400u)
#define CSL_DFE_DPDA_DPDA_PREG_596_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_596_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_596_q : 23;
#else 
    Uint32 dpda_preg_596_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_596_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_596_Q_REG_DPDA_PREG_596_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_596_Q_REG_DPDA_PREG_596_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_596_Q_REG_DPDA_PREG_596_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_596_Q_REG_ADDR (0x00065404u)
#define CSL_DFE_DPDA_DPDA_PREG_596_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_597_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_597_ie : 31;
#else 
    Uint32 dpda_preg_597_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_597_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_597_IE_REG_DPDA_PREG_597_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_597_IE_REG_DPDA_PREG_597_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_597_IE_REG_DPDA_PREG_597_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_597_IE_REG_ADDR (0x00065500u)
#define CSL_DFE_DPDA_DPDA_PREG_597_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_597_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_597_q : 23;
#else 
    Uint32 dpda_preg_597_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_597_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_597_Q_REG_DPDA_PREG_597_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_597_Q_REG_DPDA_PREG_597_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_597_Q_REG_DPDA_PREG_597_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_597_Q_REG_ADDR (0x00065504u)
#define CSL_DFE_DPDA_DPDA_PREG_597_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_598_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_598_ie : 31;
#else 
    Uint32 dpda_preg_598_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_598_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_598_IE_REG_DPDA_PREG_598_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_598_IE_REG_DPDA_PREG_598_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_598_IE_REG_DPDA_PREG_598_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_598_IE_REG_ADDR (0x00065600u)
#define CSL_DFE_DPDA_DPDA_PREG_598_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_598_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_598_q : 23;
#else 
    Uint32 dpda_preg_598_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_598_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_598_Q_REG_DPDA_PREG_598_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_598_Q_REG_DPDA_PREG_598_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_598_Q_REG_DPDA_PREG_598_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_598_Q_REG_ADDR (0x00065604u)
#define CSL_DFE_DPDA_DPDA_PREG_598_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_599_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_599_ie : 31;
#else 
    Uint32 dpda_preg_599_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_599_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_599_IE_REG_DPDA_PREG_599_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_599_IE_REG_DPDA_PREG_599_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_599_IE_REG_DPDA_PREG_599_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_599_IE_REG_ADDR (0x00065700u)
#define CSL_DFE_DPDA_DPDA_PREG_599_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_599_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_599_q : 23;
#else 
    Uint32 dpda_preg_599_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_599_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_599_Q_REG_DPDA_PREG_599_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_599_Q_REG_DPDA_PREG_599_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_599_Q_REG_DPDA_PREG_599_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_599_Q_REG_ADDR (0x00065704u)
#define CSL_DFE_DPDA_DPDA_PREG_599_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_600_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_600_ie : 31;
#else 
    Uint32 dpda_preg_600_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_600_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_600_IE_REG_DPDA_PREG_600_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_600_IE_REG_DPDA_PREG_600_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_600_IE_REG_DPDA_PREG_600_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_600_IE_REG_ADDR (0x00065800u)
#define CSL_DFE_DPDA_DPDA_PREG_600_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_600_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_600_q : 23;
#else 
    Uint32 dpda_preg_600_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_600_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_600_Q_REG_DPDA_PREG_600_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_600_Q_REG_DPDA_PREG_600_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_600_Q_REG_DPDA_PREG_600_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_600_Q_REG_ADDR (0x00065804u)
#define CSL_DFE_DPDA_DPDA_PREG_600_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_601_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_601_ie : 31;
#else 
    Uint32 dpda_preg_601_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_601_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_601_IE_REG_DPDA_PREG_601_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_601_IE_REG_DPDA_PREG_601_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_601_IE_REG_DPDA_PREG_601_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_601_IE_REG_ADDR (0x00065900u)
#define CSL_DFE_DPDA_DPDA_PREG_601_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_601_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_601_q : 23;
#else 
    Uint32 dpda_preg_601_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_601_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_601_Q_REG_DPDA_PREG_601_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_601_Q_REG_DPDA_PREG_601_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_601_Q_REG_DPDA_PREG_601_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_601_Q_REG_ADDR (0x00065904u)
#define CSL_DFE_DPDA_DPDA_PREG_601_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_602_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_602_ie : 31;
#else 
    Uint32 dpda_preg_602_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_602_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_602_IE_REG_DPDA_PREG_602_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_602_IE_REG_DPDA_PREG_602_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_602_IE_REG_DPDA_PREG_602_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_602_IE_REG_ADDR (0x00065A00u)
#define CSL_DFE_DPDA_DPDA_PREG_602_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_602_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_602_q : 23;
#else 
    Uint32 dpda_preg_602_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_602_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_602_Q_REG_DPDA_PREG_602_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_602_Q_REG_DPDA_PREG_602_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_602_Q_REG_DPDA_PREG_602_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_602_Q_REG_ADDR (0x00065A04u)
#define CSL_DFE_DPDA_DPDA_PREG_602_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_603_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_603_ie : 31;
#else 
    Uint32 dpda_preg_603_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_603_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_603_IE_REG_DPDA_PREG_603_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_603_IE_REG_DPDA_PREG_603_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_603_IE_REG_DPDA_PREG_603_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_603_IE_REG_ADDR (0x00065B00u)
#define CSL_DFE_DPDA_DPDA_PREG_603_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_603_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_603_q : 23;
#else 
    Uint32 dpda_preg_603_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_603_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_603_Q_REG_DPDA_PREG_603_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_603_Q_REG_DPDA_PREG_603_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_603_Q_REG_DPDA_PREG_603_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_603_Q_REG_ADDR (0x00065B04u)
#define CSL_DFE_DPDA_DPDA_PREG_603_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_604_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_604_ie : 31;
#else 
    Uint32 dpda_preg_604_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_604_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_604_IE_REG_DPDA_PREG_604_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_604_IE_REG_DPDA_PREG_604_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_604_IE_REG_DPDA_PREG_604_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_604_IE_REG_ADDR (0x00065C00u)
#define CSL_DFE_DPDA_DPDA_PREG_604_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_604_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_604_q : 23;
#else 
    Uint32 dpda_preg_604_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_604_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_604_Q_REG_DPDA_PREG_604_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_604_Q_REG_DPDA_PREG_604_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_604_Q_REG_DPDA_PREG_604_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_604_Q_REG_ADDR (0x00065C04u)
#define CSL_DFE_DPDA_DPDA_PREG_604_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_605_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_605_ie : 31;
#else 
    Uint32 dpda_preg_605_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_605_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_605_IE_REG_DPDA_PREG_605_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_605_IE_REG_DPDA_PREG_605_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_605_IE_REG_DPDA_PREG_605_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_605_IE_REG_ADDR (0x00065D00u)
#define CSL_DFE_DPDA_DPDA_PREG_605_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_605_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_605_q : 23;
#else 
    Uint32 dpda_preg_605_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_605_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_605_Q_REG_DPDA_PREG_605_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_605_Q_REG_DPDA_PREG_605_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_605_Q_REG_DPDA_PREG_605_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_605_Q_REG_ADDR (0x00065D04u)
#define CSL_DFE_DPDA_DPDA_PREG_605_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_606_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_606_ie : 31;
#else 
    Uint32 dpda_preg_606_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_606_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_606_IE_REG_DPDA_PREG_606_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_606_IE_REG_DPDA_PREG_606_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_606_IE_REG_DPDA_PREG_606_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_606_IE_REG_ADDR (0x00065E00u)
#define CSL_DFE_DPDA_DPDA_PREG_606_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_606_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_606_q : 23;
#else 
    Uint32 dpda_preg_606_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_606_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_606_Q_REG_DPDA_PREG_606_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_606_Q_REG_DPDA_PREG_606_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_606_Q_REG_DPDA_PREG_606_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_606_Q_REG_ADDR (0x00065E04u)
#define CSL_DFE_DPDA_DPDA_PREG_606_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_607_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_607_ie : 31;
#else 
    Uint32 dpda_preg_607_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_607_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_607_IE_REG_DPDA_PREG_607_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_607_IE_REG_DPDA_PREG_607_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_607_IE_REG_DPDA_PREG_607_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_607_IE_REG_ADDR (0x00065F00u)
#define CSL_DFE_DPDA_DPDA_PREG_607_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_607_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_607_q : 23;
#else 
    Uint32 dpda_preg_607_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_607_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_607_Q_REG_DPDA_PREG_607_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_607_Q_REG_DPDA_PREG_607_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_607_Q_REG_DPDA_PREG_607_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_607_Q_REG_ADDR (0x00065F04u)
#define CSL_DFE_DPDA_DPDA_PREG_607_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_608_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_608_ie : 31;
#else 
    Uint32 dpda_preg_608_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_608_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_608_IE_REG_DPDA_PREG_608_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_608_IE_REG_DPDA_PREG_608_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_608_IE_REG_DPDA_PREG_608_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_608_IE_REG_ADDR (0x00066000u)
#define CSL_DFE_DPDA_DPDA_PREG_608_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_608_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_608_q : 23;
#else 
    Uint32 dpda_preg_608_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_608_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_608_Q_REG_DPDA_PREG_608_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_608_Q_REG_DPDA_PREG_608_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_608_Q_REG_DPDA_PREG_608_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_608_Q_REG_ADDR (0x00066004u)
#define CSL_DFE_DPDA_DPDA_PREG_608_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_609_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_609_ie : 31;
#else 
    Uint32 dpda_preg_609_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_609_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_609_IE_REG_DPDA_PREG_609_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_609_IE_REG_DPDA_PREG_609_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_609_IE_REG_DPDA_PREG_609_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_609_IE_REG_ADDR (0x00066100u)
#define CSL_DFE_DPDA_DPDA_PREG_609_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_609_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_609_q : 23;
#else 
    Uint32 dpda_preg_609_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_609_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_609_Q_REG_DPDA_PREG_609_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_609_Q_REG_DPDA_PREG_609_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_609_Q_REG_DPDA_PREG_609_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_609_Q_REG_ADDR (0x00066104u)
#define CSL_DFE_DPDA_DPDA_PREG_609_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_610_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_610_ie : 31;
#else 
    Uint32 dpda_preg_610_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_610_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_610_IE_REG_DPDA_PREG_610_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_610_IE_REG_DPDA_PREG_610_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_610_IE_REG_DPDA_PREG_610_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_610_IE_REG_ADDR (0x00066200u)
#define CSL_DFE_DPDA_DPDA_PREG_610_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_610_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_610_q : 23;
#else 
    Uint32 dpda_preg_610_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_610_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_610_Q_REG_DPDA_PREG_610_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_610_Q_REG_DPDA_PREG_610_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_610_Q_REG_DPDA_PREG_610_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_610_Q_REG_ADDR (0x00066204u)
#define CSL_DFE_DPDA_DPDA_PREG_610_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_611_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_611_ie : 31;
#else 
    Uint32 dpda_preg_611_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_611_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_611_IE_REG_DPDA_PREG_611_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_611_IE_REG_DPDA_PREG_611_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_611_IE_REG_DPDA_PREG_611_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_611_IE_REG_ADDR (0x00066300u)
#define CSL_DFE_DPDA_DPDA_PREG_611_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_611_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_611_q : 23;
#else 
    Uint32 dpda_preg_611_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_611_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_611_Q_REG_DPDA_PREG_611_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_611_Q_REG_DPDA_PREG_611_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_611_Q_REG_DPDA_PREG_611_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_611_Q_REG_ADDR (0x00066304u)
#define CSL_DFE_DPDA_DPDA_PREG_611_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_612_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_612_ie : 31;
#else 
    Uint32 dpda_preg_612_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_612_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_612_IE_REG_DPDA_PREG_612_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_612_IE_REG_DPDA_PREG_612_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_612_IE_REG_DPDA_PREG_612_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_612_IE_REG_ADDR (0x00066400u)
#define CSL_DFE_DPDA_DPDA_PREG_612_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_612_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_612_q : 23;
#else 
    Uint32 dpda_preg_612_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_612_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_612_Q_REG_DPDA_PREG_612_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_612_Q_REG_DPDA_PREG_612_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_612_Q_REG_DPDA_PREG_612_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_612_Q_REG_ADDR (0x00066404u)
#define CSL_DFE_DPDA_DPDA_PREG_612_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_613_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_613_ie : 31;
#else 
    Uint32 dpda_preg_613_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_613_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_613_IE_REG_DPDA_PREG_613_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_613_IE_REG_DPDA_PREG_613_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_613_IE_REG_DPDA_PREG_613_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_613_IE_REG_ADDR (0x00066500u)
#define CSL_DFE_DPDA_DPDA_PREG_613_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_613_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_613_q : 23;
#else 
    Uint32 dpda_preg_613_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_613_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_613_Q_REG_DPDA_PREG_613_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_613_Q_REG_DPDA_PREG_613_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_613_Q_REG_DPDA_PREG_613_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_613_Q_REG_ADDR (0x00066504u)
#define CSL_DFE_DPDA_DPDA_PREG_613_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_614_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_614_ie : 31;
#else 
    Uint32 dpda_preg_614_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_614_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_614_IE_REG_DPDA_PREG_614_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_614_IE_REG_DPDA_PREG_614_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_614_IE_REG_DPDA_PREG_614_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_614_IE_REG_ADDR (0x00066600u)
#define CSL_DFE_DPDA_DPDA_PREG_614_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_614_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_614_q : 23;
#else 
    Uint32 dpda_preg_614_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_614_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_614_Q_REG_DPDA_PREG_614_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_614_Q_REG_DPDA_PREG_614_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_614_Q_REG_DPDA_PREG_614_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_614_Q_REG_ADDR (0x00066604u)
#define CSL_DFE_DPDA_DPDA_PREG_614_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_615_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_615_ie : 31;
#else 
    Uint32 dpda_preg_615_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_615_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_615_IE_REG_DPDA_PREG_615_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_615_IE_REG_DPDA_PREG_615_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_615_IE_REG_DPDA_PREG_615_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_615_IE_REG_ADDR (0x00066700u)
#define CSL_DFE_DPDA_DPDA_PREG_615_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_615_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_615_q : 23;
#else 
    Uint32 dpda_preg_615_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_615_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_615_Q_REG_DPDA_PREG_615_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_615_Q_REG_DPDA_PREG_615_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_615_Q_REG_DPDA_PREG_615_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_615_Q_REG_ADDR (0x00066704u)
#define CSL_DFE_DPDA_DPDA_PREG_615_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_616_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_616_ie : 31;
#else 
    Uint32 dpda_preg_616_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_616_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_616_IE_REG_DPDA_PREG_616_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_616_IE_REG_DPDA_PREG_616_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_616_IE_REG_DPDA_PREG_616_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_616_IE_REG_ADDR (0x00066800u)
#define CSL_DFE_DPDA_DPDA_PREG_616_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_616_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_616_q : 23;
#else 
    Uint32 dpda_preg_616_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_616_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_616_Q_REG_DPDA_PREG_616_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_616_Q_REG_DPDA_PREG_616_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_616_Q_REG_DPDA_PREG_616_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_616_Q_REG_ADDR (0x00066804u)
#define CSL_DFE_DPDA_DPDA_PREG_616_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_617_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_617_ie : 31;
#else 
    Uint32 dpda_preg_617_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_617_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_617_IE_REG_DPDA_PREG_617_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_617_IE_REG_DPDA_PREG_617_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_617_IE_REG_DPDA_PREG_617_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_617_IE_REG_ADDR (0x00066900u)
#define CSL_DFE_DPDA_DPDA_PREG_617_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_617_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_617_q : 23;
#else 
    Uint32 dpda_preg_617_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_617_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_617_Q_REG_DPDA_PREG_617_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_617_Q_REG_DPDA_PREG_617_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_617_Q_REG_DPDA_PREG_617_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_617_Q_REG_ADDR (0x00066904u)
#define CSL_DFE_DPDA_DPDA_PREG_617_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_618_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_618_ie : 31;
#else 
    Uint32 dpda_preg_618_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_618_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_618_IE_REG_DPDA_PREG_618_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_618_IE_REG_DPDA_PREG_618_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_618_IE_REG_DPDA_PREG_618_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_618_IE_REG_ADDR (0x00066A00u)
#define CSL_DFE_DPDA_DPDA_PREG_618_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_618_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_618_q : 23;
#else 
    Uint32 dpda_preg_618_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_618_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_618_Q_REG_DPDA_PREG_618_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_618_Q_REG_DPDA_PREG_618_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_618_Q_REG_DPDA_PREG_618_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_618_Q_REG_ADDR (0x00066A04u)
#define CSL_DFE_DPDA_DPDA_PREG_618_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_619_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_619_ie : 31;
#else 
    Uint32 dpda_preg_619_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_619_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_619_IE_REG_DPDA_PREG_619_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_619_IE_REG_DPDA_PREG_619_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_619_IE_REG_DPDA_PREG_619_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_619_IE_REG_ADDR (0x00066B00u)
#define CSL_DFE_DPDA_DPDA_PREG_619_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_619_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_619_q : 23;
#else 
    Uint32 dpda_preg_619_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_619_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_619_Q_REG_DPDA_PREG_619_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_619_Q_REG_DPDA_PREG_619_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_619_Q_REG_DPDA_PREG_619_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_619_Q_REG_ADDR (0x00066B04u)
#define CSL_DFE_DPDA_DPDA_PREG_619_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_620_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_620_ie : 31;
#else 
    Uint32 dpda_preg_620_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_620_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_620_IE_REG_DPDA_PREG_620_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_620_IE_REG_DPDA_PREG_620_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_620_IE_REG_DPDA_PREG_620_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_620_IE_REG_ADDR (0x00066C00u)
#define CSL_DFE_DPDA_DPDA_PREG_620_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_620_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_620_q : 23;
#else 
    Uint32 dpda_preg_620_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_620_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_620_Q_REG_DPDA_PREG_620_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_620_Q_REG_DPDA_PREG_620_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_620_Q_REG_DPDA_PREG_620_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_620_Q_REG_ADDR (0x00066C04u)
#define CSL_DFE_DPDA_DPDA_PREG_620_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_621_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_621_ie : 31;
#else 
    Uint32 dpda_preg_621_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_621_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_621_IE_REG_DPDA_PREG_621_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_621_IE_REG_DPDA_PREG_621_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_621_IE_REG_DPDA_PREG_621_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_621_IE_REG_ADDR (0x00066D00u)
#define CSL_DFE_DPDA_DPDA_PREG_621_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_621_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_621_q : 23;
#else 
    Uint32 dpda_preg_621_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_621_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_621_Q_REG_DPDA_PREG_621_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_621_Q_REG_DPDA_PREG_621_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_621_Q_REG_DPDA_PREG_621_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_621_Q_REG_ADDR (0x00066D04u)
#define CSL_DFE_DPDA_DPDA_PREG_621_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_622_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_622_ie : 31;
#else 
    Uint32 dpda_preg_622_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_622_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_622_IE_REG_DPDA_PREG_622_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_622_IE_REG_DPDA_PREG_622_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_622_IE_REG_DPDA_PREG_622_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_622_IE_REG_ADDR (0x00066E00u)
#define CSL_DFE_DPDA_DPDA_PREG_622_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_622_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_622_q : 23;
#else 
    Uint32 dpda_preg_622_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_622_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_622_Q_REG_DPDA_PREG_622_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_622_Q_REG_DPDA_PREG_622_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_622_Q_REG_DPDA_PREG_622_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_622_Q_REG_ADDR (0x00066E04u)
#define CSL_DFE_DPDA_DPDA_PREG_622_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_623_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_623_ie : 31;
#else 
    Uint32 dpda_preg_623_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_623_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_623_IE_REG_DPDA_PREG_623_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_623_IE_REG_DPDA_PREG_623_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_623_IE_REG_DPDA_PREG_623_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_623_IE_REG_ADDR (0x00066F00u)
#define CSL_DFE_DPDA_DPDA_PREG_623_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_623_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_623_q : 23;
#else 
    Uint32 dpda_preg_623_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_623_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_623_Q_REG_DPDA_PREG_623_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_623_Q_REG_DPDA_PREG_623_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_623_Q_REG_DPDA_PREG_623_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_623_Q_REG_ADDR (0x00066F04u)
#define CSL_DFE_DPDA_DPDA_PREG_623_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_624_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_624_ie : 31;
#else 
    Uint32 dpda_preg_624_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_624_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_624_IE_REG_DPDA_PREG_624_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_624_IE_REG_DPDA_PREG_624_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_624_IE_REG_DPDA_PREG_624_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_624_IE_REG_ADDR (0x00067000u)
#define CSL_DFE_DPDA_DPDA_PREG_624_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_624_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_624_q : 23;
#else 
    Uint32 dpda_preg_624_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_624_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_624_Q_REG_DPDA_PREG_624_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_624_Q_REG_DPDA_PREG_624_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_624_Q_REG_DPDA_PREG_624_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_624_Q_REG_ADDR (0x00067004u)
#define CSL_DFE_DPDA_DPDA_PREG_624_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_625_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_625_ie : 31;
#else 
    Uint32 dpda_preg_625_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_625_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_625_IE_REG_DPDA_PREG_625_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_625_IE_REG_DPDA_PREG_625_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_625_IE_REG_DPDA_PREG_625_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_625_IE_REG_ADDR (0x00067100u)
#define CSL_DFE_DPDA_DPDA_PREG_625_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_625_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_625_q : 23;
#else 
    Uint32 dpda_preg_625_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_625_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_625_Q_REG_DPDA_PREG_625_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_625_Q_REG_DPDA_PREG_625_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_625_Q_REG_DPDA_PREG_625_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_625_Q_REG_ADDR (0x00067104u)
#define CSL_DFE_DPDA_DPDA_PREG_625_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_626_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_626_ie : 31;
#else 
    Uint32 dpda_preg_626_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_626_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_626_IE_REG_DPDA_PREG_626_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_626_IE_REG_DPDA_PREG_626_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_626_IE_REG_DPDA_PREG_626_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_626_IE_REG_ADDR (0x00067200u)
#define CSL_DFE_DPDA_DPDA_PREG_626_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_626_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_626_q : 23;
#else 
    Uint32 dpda_preg_626_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_626_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_626_Q_REG_DPDA_PREG_626_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_626_Q_REG_DPDA_PREG_626_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_626_Q_REG_DPDA_PREG_626_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_626_Q_REG_ADDR (0x00067204u)
#define CSL_DFE_DPDA_DPDA_PREG_626_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_627_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_627_ie : 31;
#else 
    Uint32 dpda_preg_627_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_627_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_627_IE_REG_DPDA_PREG_627_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_627_IE_REG_DPDA_PREG_627_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_627_IE_REG_DPDA_PREG_627_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_627_IE_REG_ADDR (0x00067300u)
#define CSL_DFE_DPDA_DPDA_PREG_627_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_627_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_627_q : 23;
#else 
    Uint32 dpda_preg_627_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_627_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_627_Q_REG_DPDA_PREG_627_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_627_Q_REG_DPDA_PREG_627_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_627_Q_REG_DPDA_PREG_627_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_627_Q_REG_ADDR (0x00067304u)
#define CSL_DFE_DPDA_DPDA_PREG_627_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_628_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_628_ie : 31;
#else 
    Uint32 dpda_preg_628_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_628_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_628_IE_REG_DPDA_PREG_628_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_628_IE_REG_DPDA_PREG_628_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_628_IE_REG_DPDA_PREG_628_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_628_IE_REG_ADDR (0x00067400u)
#define CSL_DFE_DPDA_DPDA_PREG_628_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_628_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_628_q : 23;
#else 
    Uint32 dpda_preg_628_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_628_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_628_Q_REG_DPDA_PREG_628_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_628_Q_REG_DPDA_PREG_628_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_628_Q_REG_DPDA_PREG_628_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_628_Q_REG_ADDR (0x00067404u)
#define CSL_DFE_DPDA_DPDA_PREG_628_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_629_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_629_ie : 31;
#else 
    Uint32 dpda_preg_629_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_629_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_629_IE_REG_DPDA_PREG_629_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_629_IE_REG_DPDA_PREG_629_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_629_IE_REG_DPDA_PREG_629_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_629_IE_REG_ADDR (0x00067500u)
#define CSL_DFE_DPDA_DPDA_PREG_629_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_629_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_629_q : 23;
#else 
    Uint32 dpda_preg_629_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_629_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_629_Q_REG_DPDA_PREG_629_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_629_Q_REG_DPDA_PREG_629_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_629_Q_REG_DPDA_PREG_629_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_629_Q_REG_ADDR (0x00067504u)
#define CSL_DFE_DPDA_DPDA_PREG_629_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_630_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_630_ie : 31;
#else 
    Uint32 dpda_preg_630_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_630_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_630_IE_REG_DPDA_PREG_630_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_630_IE_REG_DPDA_PREG_630_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_630_IE_REG_DPDA_PREG_630_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_630_IE_REG_ADDR (0x00067600u)
#define CSL_DFE_DPDA_DPDA_PREG_630_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_630_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_630_q : 23;
#else 
    Uint32 dpda_preg_630_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_630_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_630_Q_REG_DPDA_PREG_630_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_630_Q_REG_DPDA_PREG_630_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_630_Q_REG_DPDA_PREG_630_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_630_Q_REG_ADDR (0x00067604u)
#define CSL_DFE_DPDA_DPDA_PREG_630_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_631_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_631_ie : 31;
#else 
    Uint32 dpda_preg_631_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_631_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_631_IE_REG_DPDA_PREG_631_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_631_IE_REG_DPDA_PREG_631_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_631_IE_REG_DPDA_PREG_631_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_631_IE_REG_ADDR (0x00067700u)
#define CSL_DFE_DPDA_DPDA_PREG_631_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_631_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_631_q : 23;
#else 
    Uint32 dpda_preg_631_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_631_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_631_Q_REG_DPDA_PREG_631_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_631_Q_REG_DPDA_PREG_631_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_631_Q_REG_DPDA_PREG_631_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_631_Q_REG_ADDR (0x00067704u)
#define CSL_DFE_DPDA_DPDA_PREG_631_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_632_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_632_ie : 31;
#else 
    Uint32 dpda_preg_632_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_632_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_632_IE_REG_DPDA_PREG_632_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_632_IE_REG_DPDA_PREG_632_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_632_IE_REG_DPDA_PREG_632_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_632_IE_REG_ADDR (0x00067800u)
#define CSL_DFE_DPDA_DPDA_PREG_632_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_632_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_632_q : 23;
#else 
    Uint32 dpda_preg_632_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_632_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_632_Q_REG_DPDA_PREG_632_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_632_Q_REG_DPDA_PREG_632_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_632_Q_REG_DPDA_PREG_632_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_632_Q_REG_ADDR (0x00067804u)
#define CSL_DFE_DPDA_DPDA_PREG_632_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_633_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_633_ie : 31;
#else 
    Uint32 dpda_preg_633_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_633_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_633_IE_REG_DPDA_PREG_633_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_633_IE_REG_DPDA_PREG_633_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_633_IE_REG_DPDA_PREG_633_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_633_IE_REG_ADDR (0x00067900u)
#define CSL_DFE_DPDA_DPDA_PREG_633_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_633_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_633_q : 23;
#else 
    Uint32 dpda_preg_633_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_633_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_633_Q_REG_DPDA_PREG_633_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_633_Q_REG_DPDA_PREG_633_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_633_Q_REG_DPDA_PREG_633_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_633_Q_REG_ADDR (0x00067904u)
#define CSL_DFE_DPDA_DPDA_PREG_633_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_634_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_634_ie : 31;
#else 
    Uint32 dpda_preg_634_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_634_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_634_IE_REG_DPDA_PREG_634_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_634_IE_REG_DPDA_PREG_634_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_634_IE_REG_DPDA_PREG_634_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_634_IE_REG_ADDR (0x00067A00u)
#define CSL_DFE_DPDA_DPDA_PREG_634_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_634_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_634_q : 23;
#else 
    Uint32 dpda_preg_634_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_634_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_634_Q_REG_DPDA_PREG_634_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_634_Q_REG_DPDA_PREG_634_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_634_Q_REG_DPDA_PREG_634_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_634_Q_REG_ADDR (0x00067A04u)
#define CSL_DFE_DPDA_DPDA_PREG_634_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_635_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_635_ie : 31;
#else 
    Uint32 dpda_preg_635_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_635_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_635_IE_REG_DPDA_PREG_635_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_635_IE_REG_DPDA_PREG_635_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_635_IE_REG_DPDA_PREG_635_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_635_IE_REG_ADDR (0x00067B00u)
#define CSL_DFE_DPDA_DPDA_PREG_635_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_635_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_635_q : 23;
#else 
    Uint32 dpda_preg_635_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_635_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_635_Q_REG_DPDA_PREG_635_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_635_Q_REG_DPDA_PREG_635_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_635_Q_REG_DPDA_PREG_635_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_635_Q_REG_ADDR (0x00067B04u)
#define CSL_DFE_DPDA_DPDA_PREG_635_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_636_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_636_ie : 31;
#else 
    Uint32 dpda_preg_636_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_636_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_636_IE_REG_DPDA_PREG_636_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_636_IE_REG_DPDA_PREG_636_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_636_IE_REG_DPDA_PREG_636_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_636_IE_REG_ADDR (0x00067C00u)
#define CSL_DFE_DPDA_DPDA_PREG_636_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_636_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_636_q : 23;
#else 
    Uint32 dpda_preg_636_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_636_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_636_Q_REG_DPDA_PREG_636_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_636_Q_REG_DPDA_PREG_636_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_636_Q_REG_DPDA_PREG_636_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_636_Q_REG_ADDR (0x00067C04u)
#define CSL_DFE_DPDA_DPDA_PREG_636_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_637_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_637_ie : 31;
#else 
    Uint32 dpda_preg_637_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_637_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_637_IE_REG_DPDA_PREG_637_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_637_IE_REG_DPDA_PREG_637_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_637_IE_REG_DPDA_PREG_637_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_637_IE_REG_ADDR (0x00067D00u)
#define CSL_DFE_DPDA_DPDA_PREG_637_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_637_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_637_q : 23;
#else 
    Uint32 dpda_preg_637_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_637_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_637_Q_REG_DPDA_PREG_637_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_637_Q_REG_DPDA_PREG_637_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_637_Q_REG_DPDA_PREG_637_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_637_Q_REG_ADDR (0x00067D04u)
#define CSL_DFE_DPDA_DPDA_PREG_637_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_638_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_638_ie : 31;
#else 
    Uint32 dpda_preg_638_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_638_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_638_IE_REG_DPDA_PREG_638_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_638_IE_REG_DPDA_PREG_638_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_638_IE_REG_DPDA_PREG_638_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_638_IE_REG_ADDR (0x00067E00u)
#define CSL_DFE_DPDA_DPDA_PREG_638_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_638_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_638_q : 23;
#else 
    Uint32 dpda_preg_638_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_638_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_638_Q_REG_DPDA_PREG_638_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_638_Q_REG_DPDA_PREG_638_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_638_Q_REG_DPDA_PREG_638_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_638_Q_REG_ADDR (0x00067E04u)
#define CSL_DFE_DPDA_DPDA_PREG_638_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_639_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_639_ie : 31;
#else 
    Uint32 dpda_preg_639_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_639_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_639_IE_REG_DPDA_PREG_639_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_639_IE_REG_DPDA_PREG_639_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_639_IE_REG_DPDA_PREG_639_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_639_IE_REG_ADDR (0x00067F00u)
#define CSL_DFE_DPDA_DPDA_PREG_639_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_639_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_639_q : 23;
#else 
    Uint32 dpda_preg_639_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_639_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_639_Q_REG_DPDA_PREG_639_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_639_Q_REG_DPDA_PREG_639_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_639_Q_REG_DPDA_PREG_639_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_639_Q_REG_ADDR (0x00067F04u)
#define CSL_DFE_DPDA_DPDA_PREG_639_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_640_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_640_ie : 31;
#else 
    Uint32 dpda_preg_640_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_640_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_640_IE_REG_DPDA_PREG_640_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_640_IE_REG_DPDA_PREG_640_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_640_IE_REG_DPDA_PREG_640_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_640_IE_REG_ADDR (0x00068000u)
#define CSL_DFE_DPDA_DPDA_PREG_640_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_640_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_640_q : 23;
#else 
    Uint32 dpda_preg_640_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_640_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_640_Q_REG_DPDA_PREG_640_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_640_Q_REG_DPDA_PREG_640_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_640_Q_REG_DPDA_PREG_640_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_640_Q_REG_ADDR (0x00068004u)
#define CSL_DFE_DPDA_DPDA_PREG_640_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_641_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_641_ie : 31;
#else 
    Uint32 dpda_preg_641_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_641_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_641_IE_REG_DPDA_PREG_641_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_641_IE_REG_DPDA_PREG_641_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_641_IE_REG_DPDA_PREG_641_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_641_IE_REG_ADDR (0x00068100u)
#define CSL_DFE_DPDA_DPDA_PREG_641_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_641_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_641_q : 23;
#else 
    Uint32 dpda_preg_641_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_641_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_641_Q_REG_DPDA_PREG_641_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_641_Q_REG_DPDA_PREG_641_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_641_Q_REG_DPDA_PREG_641_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_641_Q_REG_ADDR (0x00068104u)
#define CSL_DFE_DPDA_DPDA_PREG_641_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_642_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_642_ie : 31;
#else 
    Uint32 dpda_preg_642_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_642_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_642_IE_REG_DPDA_PREG_642_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_642_IE_REG_DPDA_PREG_642_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_642_IE_REG_DPDA_PREG_642_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_642_IE_REG_ADDR (0x00068200u)
#define CSL_DFE_DPDA_DPDA_PREG_642_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_642_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_642_q : 23;
#else 
    Uint32 dpda_preg_642_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_642_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_642_Q_REG_DPDA_PREG_642_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_642_Q_REG_DPDA_PREG_642_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_642_Q_REG_DPDA_PREG_642_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_642_Q_REG_ADDR (0x00068204u)
#define CSL_DFE_DPDA_DPDA_PREG_642_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_643_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_643_ie : 31;
#else 
    Uint32 dpda_preg_643_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_643_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_643_IE_REG_DPDA_PREG_643_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_643_IE_REG_DPDA_PREG_643_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_643_IE_REG_DPDA_PREG_643_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_643_IE_REG_ADDR (0x00068300u)
#define CSL_DFE_DPDA_DPDA_PREG_643_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_643_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_643_q : 23;
#else 
    Uint32 dpda_preg_643_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_643_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_643_Q_REG_DPDA_PREG_643_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_643_Q_REG_DPDA_PREG_643_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_643_Q_REG_DPDA_PREG_643_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_643_Q_REG_ADDR (0x00068304u)
#define CSL_DFE_DPDA_DPDA_PREG_643_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_644_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_644_ie : 31;
#else 
    Uint32 dpda_preg_644_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_644_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_644_IE_REG_DPDA_PREG_644_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_644_IE_REG_DPDA_PREG_644_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_644_IE_REG_DPDA_PREG_644_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_644_IE_REG_ADDR (0x00068400u)
#define CSL_DFE_DPDA_DPDA_PREG_644_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_644_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_644_q : 23;
#else 
    Uint32 dpda_preg_644_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_644_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_644_Q_REG_DPDA_PREG_644_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_644_Q_REG_DPDA_PREG_644_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_644_Q_REG_DPDA_PREG_644_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_644_Q_REG_ADDR (0x00068404u)
#define CSL_DFE_DPDA_DPDA_PREG_644_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_645_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_645_ie : 31;
#else 
    Uint32 dpda_preg_645_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_645_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_645_IE_REG_DPDA_PREG_645_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_645_IE_REG_DPDA_PREG_645_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_645_IE_REG_DPDA_PREG_645_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_645_IE_REG_ADDR (0x00068500u)
#define CSL_DFE_DPDA_DPDA_PREG_645_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_645_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_645_q : 23;
#else 
    Uint32 dpda_preg_645_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_645_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_645_Q_REG_DPDA_PREG_645_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_645_Q_REG_DPDA_PREG_645_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_645_Q_REG_DPDA_PREG_645_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_645_Q_REG_ADDR (0x00068504u)
#define CSL_DFE_DPDA_DPDA_PREG_645_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_646_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_646_ie : 31;
#else 
    Uint32 dpda_preg_646_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_646_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_646_IE_REG_DPDA_PREG_646_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_646_IE_REG_DPDA_PREG_646_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_646_IE_REG_DPDA_PREG_646_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_646_IE_REG_ADDR (0x00068600u)
#define CSL_DFE_DPDA_DPDA_PREG_646_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_646_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_646_q : 23;
#else 
    Uint32 dpda_preg_646_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_646_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_646_Q_REG_DPDA_PREG_646_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_646_Q_REG_DPDA_PREG_646_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_646_Q_REG_DPDA_PREG_646_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_646_Q_REG_ADDR (0x00068604u)
#define CSL_DFE_DPDA_DPDA_PREG_646_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_647_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_647_ie : 31;
#else 
    Uint32 dpda_preg_647_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_647_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_647_IE_REG_DPDA_PREG_647_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_647_IE_REG_DPDA_PREG_647_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_647_IE_REG_DPDA_PREG_647_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_647_IE_REG_ADDR (0x00068700u)
#define CSL_DFE_DPDA_DPDA_PREG_647_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_647_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_647_q : 23;
#else 
    Uint32 dpda_preg_647_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_647_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_647_Q_REG_DPDA_PREG_647_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_647_Q_REG_DPDA_PREG_647_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_647_Q_REG_DPDA_PREG_647_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_647_Q_REG_ADDR (0x00068704u)
#define CSL_DFE_DPDA_DPDA_PREG_647_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_648_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_648_ie : 31;
#else 
    Uint32 dpda_preg_648_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_648_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_648_IE_REG_DPDA_PREG_648_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_648_IE_REG_DPDA_PREG_648_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_648_IE_REG_DPDA_PREG_648_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_648_IE_REG_ADDR (0x00068800u)
#define CSL_DFE_DPDA_DPDA_PREG_648_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_648_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_648_q : 23;
#else 
    Uint32 dpda_preg_648_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_648_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_648_Q_REG_DPDA_PREG_648_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_648_Q_REG_DPDA_PREG_648_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_648_Q_REG_DPDA_PREG_648_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_648_Q_REG_ADDR (0x00068804u)
#define CSL_DFE_DPDA_DPDA_PREG_648_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_649_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_649_ie : 31;
#else 
    Uint32 dpda_preg_649_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_649_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_649_IE_REG_DPDA_PREG_649_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_649_IE_REG_DPDA_PREG_649_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_649_IE_REG_DPDA_PREG_649_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_649_IE_REG_ADDR (0x00068900u)
#define CSL_DFE_DPDA_DPDA_PREG_649_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_649_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_649_q : 23;
#else 
    Uint32 dpda_preg_649_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_649_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_649_Q_REG_DPDA_PREG_649_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_649_Q_REG_DPDA_PREG_649_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_649_Q_REG_DPDA_PREG_649_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_649_Q_REG_ADDR (0x00068904u)
#define CSL_DFE_DPDA_DPDA_PREG_649_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_650_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_650_ie : 31;
#else 
    Uint32 dpda_preg_650_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_650_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_650_IE_REG_DPDA_PREG_650_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_650_IE_REG_DPDA_PREG_650_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_650_IE_REG_DPDA_PREG_650_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_650_IE_REG_ADDR (0x00068A00u)
#define CSL_DFE_DPDA_DPDA_PREG_650_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_650_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_650_q : 23;
#else 
    Uint32 dpda_preg_650_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_650_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_650_Q_REG_DPDA_PREG_650_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_650_Q_REG_DPDA_PREG_650_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_650_Q_REG_DPDA_PREG_650_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_650_Q_REG_ADDR (0x00068A04u)
#define CSL_DFE_DPDA_DPDA_PREG_650_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_651_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_651_ie : 31;
#else 
    Uint32 dpda_preg_651_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_651_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_651_IE_REG_DPDA_PREG_651_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_651_IE_REG_DPDA_PREG_651_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_651_IE_REG_DPDA_PREG_651_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_651_IE_REG_ADDR (0x00068B00u)
#define CSL_DFE_DPDA_DPDA_PREG_651_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_651_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_651_q : 23;
#else 
    Uint32 dpda_preg_651_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_651_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_651_Q_REG_DPDA_PREG_651_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_651_Q_REG_DPDA_PREG_651_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_651_Q_REG_DPDA_PREG_651_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_651_Q_REG_ADDR (0x00068B04u)
#define CSL_DFE_DPDA_DPDA_PREG_651_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_652_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_652_ie : 31;
#else 
    Uint32 dpda_preg_652_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_652_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_652_IE_REG_DPDA_PREG_652_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_652_IE_REG_DPDA_PREG_652_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_652_IE_REG_DPDA_PREG_652_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_652_IE_REG_ADDR (0x00068C00u)
#define CSL_DFE_DPDA_DPDA_PREG_652_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_652_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_652_q : 23;
#else 
    Uint32 dpda_preg_652_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_652_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_652_Q_REG_DPDA_PREG_652_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_652_Q_REG_DPDA_PREG_652_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_652_Q_REG_DPDA_PREG_652_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_652_Q_REG_ADDR (0x00068C04u)
#define CSL_DFE_DPDA_DPDA_PREG_652_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_653_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_653_ie : 31;
#else 
    Uint32 dpda_preg_653_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_653_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_653_IE_REG_DPDA_PREG_653_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_653_IE_REG_DPDA_PREG_653_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_653_IE_REG_DPDA_PREG_653_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_653_IE_REG_ADDR (0x00068D00u)
#define CSL_DFE_DPDA_DPDA_PREG_653_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_653_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_653_q : 23;
#else 
    Uint32 dpda_preg_653_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_653_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_653_Q_REG_DPDA_PREG_653_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_653_Q_REG_DPDA_PREG_653_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_653_Q_REG_DPDA_PREG_653_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_653_Q_REG_ADDR (0x00068D04u)
#define CSL_DFE_DPDA_DPDA_PREG_653_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_654_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_654_ie : 31;
#else 
    Uint32 dpda_preg_654_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_654_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_654_IE_REG_DPDA_PREG_654_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_654_IE_REG_DPDA_PREG_654_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_654_IE_REG_DPDA_PREG_654_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_654_IE_REG_ADDR (0x00068E00u)
#define CSL_DFE_DPDA_DPDA_PREG_654_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_654_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_654_q : 23;
#else 
    Uint32 dpda_preg_654_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_654_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_654_Q_REG_DPDA_PREG_654_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_654_Q_REG_DPDA_PREG_654_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_654_Q_REG_DPDA_PREG_654_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_654_Q_REG_ADDR (0x00068E04u)
#define CSL_DFE_DPDA_DPDA_PREG_654_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_655_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_655_ie : 31;
#else 
    Uint32 dpda_preg_655_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_655_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_655_IE_REG_DPDA_PREG_655_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_655_IE_REG_DPDA_PREG_655_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_655_IE_REG_DPDA_PREG_655_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_655_IE_REG_ADDR (0x00068F00u)
#define CSL_DFE_DPDA_DPDA_PREG_655_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_655_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_655_q : 23;
#else 
    Uint32 dpda_preg_655_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_655_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_655_Q_REG_DPDA_PREG_655_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_655_Q_REG_DPDA_PREG_655_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_655_Q_REG_DPDA_PREG_655_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_655_Q_REG_ADDR (0x00068F04u)
#define CSL_DFE_DPDA_DPDA_PREG_655_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_656_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_656_ie : 31;
#else 
    Uint32 dpda_preg_656_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_656_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_656_IE_REG_DPDA_PREG_656_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_656_IE_REG_DPDA_PREG_656_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_656_IE_REG_DPDA_PREG_656_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_656_IE_REG_ADDR (0x00069000u)
#define CSL_DFE_DPDA_DPDA_PREG_656_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_656_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_656_q : 23;
#else 
    Uint32 dpda_preg_656_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_656_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_656_Q_REG_DPDA_PREG_656_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_656_Q_REG_DPDA_PREG_656_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_656_Q_REG_DPDA_PREG_656_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_656_Q_REG_ADDR (0x00069004u)
#define CSL_DFE_DPDA_DPDA_PREG_656_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_657_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_657_ie : 31;
#else 
    Uint32 dpda_preg_657_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_657_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_657_IE_REG_DPDA_PREG_657_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_657_IE_REG_DPDA_PREG_657_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_657_IE_REG_DPDA_PREG_657_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_657_IE_REG_ADDR (0x00069100u)
#define CSL_DFE_DPDA_DPDA_PREG_657_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_657_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_657_q : 23;
#else 
    Uint32 dpda_preg_657_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_657_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_657_Q_REG_DPDA_PREG_657_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_657_Q_REG_DPDA_PREG_657_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_657_Q_REG_DPDA_PREG_657_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_657_Q_REG_ADDR (0x00069104u)
#define CSL_DFE_DPDA_DPDA_PREG_657_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_658_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_658_ie : 31;
#else 
    Uint32 dpda_preg_658_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_658_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_658_IE_REG_DPDA_PREG_658_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_658_IE_REG_DPDA_PREG_658_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_658_IE_REG_DPDA_PREG_658_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_658_IE_REG_ADDR (0x00069200u)
#define CSL_DFE_DPDA_DPDA_PREG_658_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_658_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_658_q : 23;
#else 
    Uint32 dpda_preg_658_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_658_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_658_Q_REG_DPDA_PREG_658_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_658_Q_REG_DPDA_PREG_658_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_658_Q_REG_DPDA_PREG_658_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_658_Q_REG_ADDR (0x00069204u)
#define CSL_DFE_DPDA_DPDA_PREG_658_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_659_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_659_ie : 31;
#else 
    Uint32 dpda_preg_659_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_659_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_659_IE_REG_DPDA_PREG_659_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_659_IE_REG_DPDA_PREG_659_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_659_IE_REG_DPDA_PREG_659_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_659_IE_REG_ADDR (0x00069300u)
#define CSL_DFE_DPDA_DPDA_PREG_659_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_659_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_659_q : 23;
#else 
    Uint32 dpda_preg_659_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_659_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_659_Q_REG_DPDA_PREG_659_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_659_Q_REG_DPDA_PREG_659_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_659_Q_REG_DPDA_PREG_659_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_659_Q_REG_ADDR (0x00069304u)
#define CSL_DFE_DPDA_DPDA_PREG_659_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_660_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_660_ie : 31;
#else 
    Uint32 dpda_preg_660_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_660_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_660_IE_REG_DPDA_PREG_660_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_660_IE_REG_DPDA_PREG_660_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_660_IE_REG_DPDA_PREG_660_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_660_IE_REG_ADDR (0x00069400u)
#define CSL_DFE_DPDA_DPDA_PREG_660_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_660_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_660_q : 23;
#else 
    Uint32 dpda_preg_660_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_660_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_660_Q_REG_DPDA_PREG_660_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_660_Q_REG_DPDA_PREG_660_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_660_Q_REG_DPDA_PREG_660_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_660_Q_REG_ADDR (0x00069404u)
#define CSL_DFE_DPDA_DPDA_PREG_660_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_661_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_661_ie : 31;
#else 
    Uint32 dpda_preg_661_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_661_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_661_IE_REG_DPDA_PREG_661_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_661_IE_REG_DPDA_PREG_661_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_661_IE_REG_DPDA_PREG_661_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_661_IE_REG_ADDR (0x00069500u)
#define CSL_DFE_DPDA_DPDA_PREG_661_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_661_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_661_q : 23;
#else 
    Uint32 dpda_preg_661_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_661_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_661_Q_REG_DPDA_PREG_661_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_661_Q_REG_DPDA_PREG_661_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_661_Q_REG_DPDA_PREG_661_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_661_Q_REG_ADDR (0x00069504u)
#define CSL_DFE_DPDA_DPDA_PREG_661_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_662_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_662_ie : 31;
#else 
    Uint32 dpda_preg_662_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_662_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_662_IE_REG_DPDA_PREG_662_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_662_IE_REG_DPDA_PREG_662_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_662_IE_REG_DPDA_PREG_662_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_662_IE_REG_ADDR (0x00069600u)
#define CSL_DFE_DPDA_DPDA_PREG_662_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_662_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_662_q : 23;
#else 
    Uint32 dpda_preg_662_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_662_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_662_Q_REG_DPDA_PREG_662_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_662_Q_REG_DPDA_PREG_662_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_662_Q_REG_DPDA_PREG_662_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_662_Q_REG_ADDR (0x00069604u)
#define CSL_DFE_DPDA_DPDA_PREG_662_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_663_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_663_ie : 31;
#else 
    Uint32 dpda_preg_663_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_663_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_663_IE_REG_DPDA_PREG_663_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_663_IE_REG_DPDA_PREG_663_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_663_IE_REG_DPDA_PREG_663_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_663_IE_REG_ADDR (0x00069700u)
#define CSL_DFE_DPDA_DPDA_PREG_663_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_663_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_663_q : 23;
#else 
    Uint32 dpda_preg_663_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_663_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_663_Q_REG_DPDA_PREG_663_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_663_Q_REG_DPDA_PREG_663_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_663_Q_REG_DPDA_PREG_663_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_663_Q_REG_ADDR (0x00069704u)
#define CSL_DFE_DPDA_DPDA_PREG_663_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_664_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_664_ie : 31;
#else 
    Uint32 dpda_preg_664_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_664_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_664_IE_REG_DPDA_PREG_664_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_664_IE_REG_DPDA_PREG_664_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_664_IE_REG_DPDA_PREG_664_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_664_IE_REG_ADDR (0x00069800u)
#define CSL_DFE_DPDA_DPDA_PREG_664_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_664_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_664_q : 23;
#else 
    Uint32 dpda_preg_664_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_664_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_664_Q_REG_DPDA_PREG_664_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_664_Q_REG_DPDA_PREG_664_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_664_Q_REG_DPDA_PREG_664_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_664_Q_REG_ADDR (0x00069804u)
#define CSL_DFE_DPDA_DPDA_PREG_664_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_665_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_665_ie : 31;
#else 
    Uint32 dpda_preg_665_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_665_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_665_IE_REG_DPDA_PREG_665_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_665_IE_REG_DPDA_PREG_665_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_665_IE_REG_DPDA_PREG_665_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_665_IE_REG_ADDR (0x00069900u)
#define CSL_DFE_DPDA_DPDA_PREG_665_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_665_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_665_q : 23;
#else 
    Uint32 dpda_preg_665_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_665_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_665_Q_REG_DPDA_PREG_665_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_665_Q_REG_DPDA_PREG_665_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_665_Q_REG_DPDA_PREG_665_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_665_Q_REG_ADDR (0x00069904u)
#define CSL_DFE_DPDA_DPDA_PREG_665_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_666_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_666_ie : 31;
#else 
    Uint32 dpda_preg_666_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_666_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_666_IE_REG_DPDA_PREG_666_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_666_IE_REG_DPDA_PREG_666_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_666_IE_REG_DPDA_PREG_666_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_666_IE_REG_ADDR (0x00069A00u)
#define CSL_DFE_DPDA_DPDA_PREG_666_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_666_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_666_q : 23;
#else 
    Uint32 dpda_preg_666_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_666_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_666_Q_REG_DPDA_PREG_666_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_666_Q_REG_DPDA_PREG_666_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_666_Q_REG_DPDA_PREG_666_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_666_Q_REG_ADDR (0x00069A04u)
#define CSL_DFE_DPDA_DPDA_PREG_666_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_667_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_667_ie : 31;
#else 
    Uint32 dpda_preg_667_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_667_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_667_IE_REG_DPDA_PREG_667_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_667_IE_REG_DPDA_PREG_667_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_667_IE_REG_DPDA_PREG_667_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_667_IE_REG_ADDR (0x00069B00u)
#define CSL_DFE_DPDA_DPDA_PREG_667_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_667_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_667_q : 23;
#else 
    Uint32 dpda_preg_667_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_667_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_667_Q_REG_DPDA_PREG_667_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_667_Q_REG_DPDA_PREG_667_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_667_Q_REG_DPDA_PREG_667_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_667_Q_REG_ADDR (0x00069B04u)
#define CSL_DFE_DPDA_DPDA_PREG_667_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_668_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_668_ie : 31;
#else 
    Uint32 dpda_preg_668_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_668_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_668_IE_REG_DPDA_PREG_668_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_668_IE_REG_DPDA_PREG_668_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_668_IE_REG_DPDA_PREG_668_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_668_IE_REG_ADDR (0x00069C00u)
#define CSL_DFE_DPDA_DPDA_PREG_668_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_668_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_668_q : 23;
#else 
    Uint32 dpda_preg_668_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_668_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_668_Q_REG_DPDA_PREG_668_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_668_Q_REG_DPDA_PREG_668_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_668_Q_REG_DPDA_PREG_668_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_668_Q_REG_ADDR (0x00069C04u)
#define CSL_DFE_DPDA_DPDA_PREG_668_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_669_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_669_ie : 31;
#else 
    Uint32 dpda_preg_669_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_669_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_669_IE_REG_DPDA_PREG_669_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_669_IE_REG_DPDA_PREG_669_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_669_IE_REG_DPDA_PREG_669_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_669_IE_REG_ADDR (0x00069D00u)
#define CSL_DFE_DPDA_DPDA_PREG_669_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_669_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_669_q : 23;
#else 
    Uint32 dpda_preg_669_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_669_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_669_Q_REG_DPDA_PREG_669_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_669_Q_REG_DPDA_PREG_669_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_669_Q_REG_DPDA_PREG_669_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_669_Q_REG_ADDR (0x00069D04u)
#define CSL_DFE_DPDA_DPDA_PREG_669_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_670_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_670_ie : 31;
#else 
    Uint32 dpda_preg_670_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_670_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_670_IE_REG_DPDA_PREG_670_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_670_IE_REG_DPDA_PREG_670_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_670_IE_REG_DPDA_PREG_670_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_670_IE_REG_ADDR (0x00069E00u)
#define CSL_DFE_DPDA_DPDA_PREG_670_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_670_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_670_q : 23;
#else 
    Uint32 dpda_preg_670_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_670_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_670_Q_REG_DPDA_PREG_670_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_670_Q_REG_DPDA_PREG_670_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_670_Q_REG_DPDA_PREG_670_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_670_Q_REG_ADDR (0x00069E04u)
#define CSL_DFE_DPDA_DPDA_PREG_670_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_671_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_671_ie : 31;
#else 
    Uint32 dpda_preg_671_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_671_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_671_IE_REG_DPDA_PREG_671_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_671_IE_REG_DPDA_PREG_671_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_671_IE_REG_DPDA_PREG_671_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_671_IE_REG_ADDR (0x00069F00u)
#define CSL_DFE_DPDA_DPDA_PREG_671_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_671_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_671_q : 23;
#else 
    Uint32 dpda_preg_671_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_671_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_671_Q_REG_DPDA_PREG_671_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_671_Q_REG_DPDA_PREG_671_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_671_Q_REG_DPDA_PREG_671_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_671_Q_REG_ADDR (0x00069F04u)
#define CSL_DFE_DPDA_DPDA_PREG_671_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_672_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_672_ie : 31;
#else 
    Uint32 dpda_preg_672_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_672_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_672_IE_REG_DPDA_PREG_672_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_672_IE_REG_DPDA_PREG_672_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_672_IE_REG_DPDA_PREG_672_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_672_IE_REG_ADDR (0x0006A000u)
#define CSL_DFE_DPDA_DPDA_PREG_672_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_672_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_672_q : 23;
#else 
    Uint32 dpda_preg_672_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_672_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_672_Q_REG_DPDA_PREG_672_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_672_Q_REG_DPDA_PREG_672_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_672_Q_REG_DPDA_PREG_672_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_672_Q_REG_ADDR (0x0006A004u)
#define CSL_DFE_DPDA_DPDA_PREG_672_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_673_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_673_ie : 31;
#else 
    Uint32 dpda_preg_673_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_673_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_673_IE_REG_DPDA_PREG_673_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_673_IE_REG_DPDA_PREG_673_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_673_IE_REG_DPDA_PREG_673_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_673_IE_REG_ADDR (0x0006A100u)
#define CSL_DFE_DPDA_DPDA_PREG_673_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_673_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_673_q : 23;
#else 
    Uint32 dpda_preg_673_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_673_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_673_Q_REG_DPDA_PREG_673_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_673_Q_REG_DPDA_PREG_673_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_673_Q_REG_DPDA_PREG_673_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_673_Q_REG_ADDR (0x0006A104u)
#define CSL_DFE_DPDA_DPDA_PREG_673_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_674_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_674_ie : 31;
#else 
    Uint32 dpda_preg_674_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_674_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_674_IE_REG_DPDA_PREG_674_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_674_IE_REG_DPDA_PREG_674_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_674_IE_REG_DPDA_PREG_674_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_674_IE_REG_ADDR (0x0006A200u)
#define CSL_DFE_DPDA_DPDA_PREG_674_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_674_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_674_q : 23;
#else 
    Uint32 dpda_preg_674_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_674_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_674_Q_REG_DPDA_PREG_674_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_674_Q_REG_DPDA_PREG_674_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_674_Q_REG_DPDA_PREG_674_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_674_Q_REG_ADDR (0x0006A204u)
#define CSL_DFE_DPDA_DPDA_PREG_674_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_675_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_675_ie : 31;
#else 
    Uint32 dpda_preg_675_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_675_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_675_IE_REG_DPDA_PREG_675_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_675_IE_REG_DPDA_PREG_675_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_675_IE_REG_DPDA_PREG_675_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_675_IE_REG_ADDR (0x0006A300u)
#define CSL_DFE_DPDA_DPDA_PREG_675_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_675_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_675_q : 23;
#else 
    Uint32 dpda_preg_675_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_675_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_675_Q_REG_DPDA_PREG_675_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_675_Q_REG_DPDA_PREG_675_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_675_Q_REG_DPDA_PREG_675_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_675_Q_REG_ADDR (0x0006A304u)
#define CSL_DFE_DPDA_DPDA_PREG_675_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_676_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_676_ie : 31;
#else 
    Uint32 dpda_preg_676_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_676_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_676_IE_REG_DPDA_PREG_676_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_676_IE_REG_DPDA_PREG_676_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_676_IE_REG_DPDA_PREG_676_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_676_IE_REG_ADDR (0x0006A400u)
#define CSL_DFE_DPDA_DPDA_PREG_676_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_676_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_676_q : 23;
#else 
    Uint32 dpda_preg_676_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_676_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_676_Q_REG_DPDA_PREG_676_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_676_Q_REG_DPDA_PREG_676_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_676_Q_REG_DPDA_PREG_676_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_676_Q_REG_ADDR (0x0006A404u)
#define CSL_DFE_DPDA_DPDA_PREG_676_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_677_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_677_ie : 31;
#else 
    Uint32 dpda_preg_677_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_677_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_677_IE_REG_DPDA_PREG_677_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_677_IE_REG_DPDA_PREG_677_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_677_IE_REG_DPDA_PREG_677_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_677_IE_REG_ADDR (0x0006A500u)
#define CSL_DFE_DPDA_DPDA_PREG_677_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_677_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_677_q : 23;
#else 
    Uint32 dpda_preg_677_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_677_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_677_Q_REG_DPDA_PREG_677_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_677_Q_REG_DPDA_PREG_677_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_677_Q_REG_DPDA_PREG_677_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_677_Q_REG_ADDR (0x0006A504u)
#define CSL_DFE_DPDA_DPDA_PREG_677_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_678_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_678_ie : 31;
#else 
    Uint32 dpda_preg_678_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_678_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_678_IE_REG_DPDA_PREG_678_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_678_IE_REG_DPDA_PREG_678_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_678_IE_REG_DPDA_PREG_678_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_678_IE_REG_ADDR (0x0006A600u)
#define CSL_DFE_DPDA_DPDA_PREG_678_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_678_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_678_q : 23;
#else 
    Uint32 dpda_preg_678_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_678_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_678_Q_REG_DPDA_PREG_678_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_678_Q_REG_DPDA_PREG_678_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_678_Q_REG_DPDA_PREG_678_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_678_Q_REG_ADDR (0x0006A604u)
#define CSL_DFE_DPDA_DPDA_PREG_678_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_679_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_679_ie : 31;
#else 
    Uint32 dpda_preg_679_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_679_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_679_IE_REG_DPDA_PREG_679_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_679_IE_REG_DPDA_PREG_679_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_679_IE_REG_DPDA_PREG_679_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_679_IE_REG_ADDR (0x0006A700u)
#define CSL_DFE_DPDA_DPDA_PREG_679_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_679_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_679_q : 23;
#else 
    Uint32 dpda_preg_679_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_679_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_679_Q_REG_DPDA_PREG_679_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_679_Q_REG_DPDA_PREG_679_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_679_Q_REG_DPDA_PREG_679_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_679_Q_REG_ADDR (0x0006A704u)
#define CSL_DFE_DPDA_DPDA_PREG_679_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_680_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_680_ie : 31;
#else 
    Uint32 dpda_preg_680_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_680_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_680_IE_REG_DPDA_PREG_680_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_680_IE_REG_DPDA_PREG_680_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_680_IE_REG_DPDA_PREG_680_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_680_IE_REG_ADDR (0x0006A800u)
#define CSL_DFE_DPDA_DPDA_PREG_680_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_680_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_680_q : 23;
#else 
    Uint32 dpda_preg_680_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_680_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_680_Q_REG_DPDA_PREG_680_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_680_Q_REG_DPDA_PREG_680_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_680_Q_REG_DPDA_PREG_680_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_680_Q_REG_ADDR (0x0006A804u)
#define CSL_DFE_DPDA_DPDA_PREG_680_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_681_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_681_ie : 31;
#else 
    Uint32 dpda_preg_681_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_681_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_681_IE_REG_DPDA_PREG_681_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_681_IE_REG_DPDA_PREG_681_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_681_IE_REG_DPDA_PREG_681_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_681_IE_REG_ADDR (0x0006A900u)
#define CSL_DFE_DPDA_DPDA_PREG_681_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_681_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_681_q : 23;
#else 
    Uint32 dpda_preg_681_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_681_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_681_Q_REG_DPDA_PREG_681_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_681_Q_REG_DPDA_PREG_681_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_681_Q_REG_DPDA_PREG_681_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_681_Q_REG_ADDR (0x0006A904u)
#define CSL_DFE_DPDA_DPDA_PREG_681_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_682_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_682_ie : 31;
#else 
    Uint32 dpda_preg_682_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_682_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_682_IE_REG_DPDA_PREG_682_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_682_IE_REG_DPDA_PREG_682_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_682_IE_REG_DPDA_PREG_682_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_682_IE_REG_ADDR (0x0006AA00u)
#define CSL_DFE_DPDA_DPDA_PREG_682_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_682_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_682_q : 23;
#else 
    Uint32 dpda_preg_682_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_682_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_682_Q_REG_DPDA_PREG_682_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_682_Q_REG_DPDA_PREG_682_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_682_Q_REG_DPDA_PREG_682_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_682_Q_REG_ADDR (0x0006AA04u)
#define CSL_DFE_DPDA_DPDA_PREG_682_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_683_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_683_ie : 31;
#else 
    Uint32 dpda_preg_683_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_683_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_683_IE_REG_DPDA_PREG_683_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_683_IE_REG_DPDA_PREG_683_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_683_IE_REG_DPDA_PREG_683_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_683_IE_REG_ADDR (0x0006AB00u)
#define CSL_DFE_DPDA_DPDA_PREG_683_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_683_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_683_q : 23;
#else 
    Uint32 dpda_preg_683_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_683_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_683_Q_REG_DPDA_PREG_683_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_683_Q_REG_DPDA_PREG_683_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_683_Q_REG_DPDA_PREG_683_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_683_Q_REG_ADDR (0x0006AB04u)
#define CSL_DFE_DPDA_DPDA_PREG_683_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_684_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_684_ie : 31;
#else 
    Uint32 dpda_preg_684_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_684_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_684_IE_REG_DPDA_PREG_684_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_684_IE_REG_DPDA_PREG_684_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_684_IE_REG_DPDA_PREG_684_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_684_IE_REG_ADDR (0x0006AC00u)
#define CSL_DFE_DPDA_DPDA_PREG_684_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_684_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_684_q : 23;
#else 
    Uint32 dpda_preg_684_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_684_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_684_Q_REG_DPDA_PREG_684_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_684_Q_REG_DPDA_PREG_684_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_684_Q_REG_DPDA_PREG_684_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_684_Q_REG_ADDR (0x0006AC04u)
#define CSL_DFE_DPDA_DPDA_PREG_684_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_685_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_685_ie : 31;
#else 
    Uint32 dpda_preg_685_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_685_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_685_IE_REG_DPDA_PREG_685_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_685_IE_REG_DPDA_PREG_685_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_685_IE_REG_DPDA_PREG_685_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_685_IE_REG_ADDR (0x0006AD00u)
#define CSL_DFE_DPDA_DPDA_PREG_685_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_685_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_685_q : 23;
#else 
    Uint32 dpda_preg_685_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_685_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_685_Q_REG_DPDA_PREG_685_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_685_Q_REG_DPDA_PREG_685_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_685_Q_REG_DPDA_PREG_685_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_685_Q_REG_ADDR (0x0006AD04u)
#define CSL_DFE_DPDA_DPDA_PREG_685_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_686_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_686_ie : 31;
#else 
    Uint32 dpda_preg_686_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_686_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_686_IE_REG_DPDA_PREG_686_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_686_IE_REG_DPDA_PREG_686_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_686_IE_REG_DPDA_PREG_686_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_686_IE_REG_ADDR (0x0006AE00u)
#define CSL_DFE_DPDA_DPDA_PREG_686_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_686_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_686_q : 23;
#else 
    Uint32 dpda_preg_686_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_686_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_686_Q_REG_DPDA_PREG_686_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_686_Q_REG_DPDA_PREG_686_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_686_Q_REG_DPDA_PREG_686_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_686_Q_REG_ADDR (0x0006AE04u)
#define CSL_DFE_DPDA_DPDA_PREG_686_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_687_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_687_ie : 31;
#else 
    Uint32 dpda_preg_687_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_687_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_687_IE_REG_DPDA_PREG_687_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_687_IE_REG_DPDA_PREG_687_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_687_IE_REG_DPDA_PREG_687_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_687_IE_REG_ADDR (0x0006AF00u)
#define CSL_DFE_DPDA_DPDA_PREG_687_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_687_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_687_q : 23;
#else 
    Uint32 dpda_preg_687_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_687_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_687_Q_REG_DPDA_PREG_687_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_687_Q_REG_DPDA_PREG_687_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_687_Q_REG_DPDA_PREG_687_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_687_Q_REG_ADDR (0x0006AF04u)
#define CSL_DFE_DPDA_DPDA_PREG_687_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_688_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_688_ie : 31;
#else 
    Uint32 dpda_preg_688_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_688_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_688_IE_REG_DPDA_PREG_688_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_688_IE_REG_DPDA_PREG_688_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_688_IE_REG_DPDA_PREG_688_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_688_IE_REG_ADDR (0x0006B000u)
#define CSL_DFE_DPDA_DPDA_PREG_688_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_688_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_688_q : 23;
#else 
    Uint32 dpda_preg_688_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_688_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_688_Q_REG_DPDA_PREG_688_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_688_Q_REG_DPDA_PREG_688_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_688_Q_REG_DPDA_PREG_688_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_688_Q_REG_ADDR (0x0006B004u)
#define CSL_DFE_DPDA_DPDA_PREG_688_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_689_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_689_ie : 31;
#else 
    Uint32 dpda_preg_689_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_689_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_689_IE_REG_DPDA_PREG_689_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_689_IE_REG_DPDA_PREG_689_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_689_IE_REG_DPDA_PREG_689_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_689_IE_REG_ADDR (0x0006B100u)
#define CSL_DFE_DPDA_DPDA_PREG_689_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_689_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_689_q : 23;
#else 
    Uint32 dpda_preg_689_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_689_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_689_Q_REG_DPDA_PREG_689_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_689_Q_REG_DPDA_PREG_689_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_689_Q_REG_DPDA_PREG_689_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_689_Q_REG_ADDR (0x0006B104u)
#define CSL_DFE_DPDA_DPDA_PREG_689_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_690_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_690_ie : 31;
#else 
    Uint32 dpda_preg_690_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_690_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_690_IE_REG_DPDA_PREG_690_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_690_IE_REG_DPDA_PREG_690_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_690_IE_REG_DPDA_PREG_690_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_690_IE_REG_ADDR (0x0006B200u)
#define CSL_DFE_DPDA_DPDA_PREG_690_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_690_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_690_q : 23;
#else 
    Uint32 dpda_preg_690_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_690_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_690_Q_REG_DPDA_PREG_690_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_690_Q_REG_DPDA_PREG_690_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_690_Q_REG_DPDA_PREG_690_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_690_Q_REG_ADDR (0x0006B204u)
#define CSL_DFE_DPDA_DPDA_PREG_690_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_691_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_691_ie : 31;
#else 
    Uint32 dpda_preg_691_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_691_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_691_IE_REG_DPDA_PREG_691_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_691_IE_REG_DPDA_PREG_691_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_691_IE_REG_DPDA_PREG_691_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_691_IE_REG_ADDR (0x0006B300u)
#define CSL_DFE_DPDA_DPDA_PREG_691_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_691_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_691_q : 23;
#else 
    Uint32 dpda_preg_691_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_691_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_691_Q_REG_DPDA_PREG_691_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_691_Q_REG_DPDA_PREG_691_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_691_Q_REG_DPDA_PREG_691_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_691_Q_REG_ADDR (0x0006B304u)
#define CSL_DFE_DPDA_DPDA_PREG_691_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_692_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_692_ie : 31;
#else 
    Uint32 dpda_preg_692_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_692_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_692_IE_REG_DPDA_PREG_692_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_692_IE_REG_DPDA_PREG_692_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_692_IE_REG_DPDA_PREG_692_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_692_IE_REG_ADDR (0x0006B400u)
#define CSL_DFE_DPDA_DPDA_PREG_692_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_692_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_692_q : 23;
#else 
    Uint32 dpda_preg_692_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_692_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_692_Q_REG_DPDA_PREG_692_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_692_Q_REG_DPDA_PREG_692_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_692_Q_REG_DPDA_PREG_692_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_692_Q_REG_ADDR (0x0006B404u)
#define CSL_DFE_DPDA_DPDA_PREG_692_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_693_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_693_ie : 31;
#else 
    Uint32 dpda_preg_693_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_693_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_693_IE_REG_DPDA_PREG_693_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_693_IE_REG_DPDA_PREG_693_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_693_IE_REG_DPDA_PREG_693_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_693_IE_REG_ADDR (0x0006B500u)
#define CSL_DFE_DPDA_DPDA_PREG_693_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_693_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_693_q : 23;
#else 
    Uint32 dpda_preg_693_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_693_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_693_Q_REG_DPDA_PREG_693_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_693_Q_REG_DPDA_PREG_693_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_693_Q_REG_DPDA_PREG_693_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_693_Q_REG_ADDR (0x0006B504u)
#define CSL_DFE_DPDA_DPDA_PREG_693_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_694_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_694_ie : 31;
#else 
    Uint32 dpda_preg_694_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_694_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_694_IE_REG_DPDA_PREG_694_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_694_IE_REG_DPDA_PREG_694_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_694_IE_REG_DPDA_PREG_694_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_694_IE_REG_ADDR (0x0006B600u)
#define CSL_DFE_DPDA_DPDA_PREG_694_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_694_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_694_q : 23;
#else 
    Uint32 dpda_preg_694_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_694_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_694_Q_REG_DPDA_PREG_694_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_694_Q_REG_DPDA_PREG_694_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_694_Q_REG_DPDA_PREG_694_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_694_Q_REG_ADDR (0x0006B604u)
#define CSL_DFE_DPDA_DPDA_PREG_694_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_695_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_695_ie : 31;
#else 
    Uint32 dpda_preg_695_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_695_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_695_IE_REG_DPDA_PREG_695_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_695_IE_REG_DPDA_PREG_695_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_695_IE_REG_DPDA_PREG_695_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_695_IE_REG_ADDR (0x0006B700u)
#define CSL_DFE_DPDA_DPDA_PREG_695_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_695_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_695_q : 23;
#else 
    Uint32 dpda_preg_695_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_695_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_695_Q_REG_DPDA_PREG_695_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_695_Q_REG_DPDA_PREG_695_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_695_Q_REG_DPDA_PREG_695_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_695_Q_REG_ADDR (0x0006B704u)
#define CSL_DFE_DPDA_DPDA_PREG_695_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_696_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_696_ie : 31;
#else 
    Uint32 dpda_preg_696_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_696_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_696_IE_REG_DPDA_PREG_696_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_696_IE_REG_DPDA_PREG_696_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_696_IE_REG_DPDA_PREG_696_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_696_IE_REG_ADDR (0x0006B800u)
#define CSL_DFE_DPDA_DPDA_PREG_696_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_696_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_696_q : 23;
#else 
    Uint32 dpda_preg_696_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_696_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_696_Q_REG_DPDA_PREG_696_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_696_Q_REG_DPDA_PREG_696_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_696_Q_REG_DPDA_PREG_696_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_696_Q_REG_ADDR (0x0006B804u)
#define CSL_DFE_DPDA_DPDA_PREG_696_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_697_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_697_ie : 31;
#else 
    Uint32 dpda_preg_697_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_697_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_697_IE_REG_DPDA_PREG_697_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_697_IE_REG_DPDA_PREG_697_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_697_IE_REG_DPDA_PREG_697_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_697_IE_REG_ADDR (0x0006B900u)
#define CSL_DFE_DPDA_DPDA_PREG_697_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_697_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_697_q : 23;
#else 
    Uint32 dpda_preg_697_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_697_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_697_Q_REG_DPDA_PREG_697_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_697_Q_REG_DPDA_PREG_697_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_697_Q_REG_DPDA_PREG_697_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_697_Q_REG_ADDR (0x0006B904u)
#define CSL_DFE_DPDA_DPDA_PREG_697_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_698_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_698_ie : 31;
#else 
    Uint32 dpda_preg_698_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_698_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_698_IE_REG_DPDA_PREG_698_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_698_IE_REG_DPDA_PREG_698_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_698_IE_REG_DPDA_PREG_698_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_698_IE_REG_ADDR (0x0006BA00u)
#define CSL_DFE_DPDA_DPDA_PREG_698_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_698_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_698_q : 23;
#else 
    Uint32 dpda_preg_698_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_698_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_698_Q_REG_DPDA_PREG_698_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_698_Q_REG_DPDA_PREG_698_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_698_Q_REG_DPDA_PREG_698_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_698_Q_REG_ADDR (0x0006BA04u)
#define CSL_DFE_DPDA_DPDA_PREG_698_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_699_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_699_ie : 31;
#else 
    Uint32 dpda_preg_699_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_699_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_699_IE_REG_DPDA_PREG_699_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_699_IE_REG_DPDA_PREG_699_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_699_IE_REG_DPDA_PREG_699_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_699_IE_REG_ADDR (0x0006BB00u)
#define CSL_DFE_DPDA_DPDA_PREG_699_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_699_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_699_q : 23;
#else 
    Uint32 dpda_preg_699_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_699_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_699_Q_REG_DPDA_PREG_699_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_699_Q_REG_DPDA_PREG_699_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_699_Q_REG_DPDA_PREG_699_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_699_Q_REG_ADDR (0x0006BB04u)
#define CSL_DFE_DPDA_DPDA_PREG_699_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_700_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_700_ie : 31;
#else 
    Uint32 dpda_preg_700_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_700_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_700_IE_REG_DPDA_PREG_700_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_700_IE_REG_DPDA_PREG_700_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_700_IE_REG_DPDA_PREG_700_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_700_IE_REG_ADDR (0x0006BC00u)
#define CSL_DFE_DPDA_DPDA_PREG_700_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_700_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_700_q : 23;
#else 
    Uint32 dpda_preg_700_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_700_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_700_Q_REG_DPDA_PREG_700_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_700_Q_REG_DPDA_PREG_700_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_700_Q_REG_DPDA_PREG_700_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_700_Q_REG_ADDR (0x0006BC04u)
#define CSL_DFE_DPDA_DPDA_PREG_700_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_701_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_701_ie : 31;
#else 
    Uint32 dpda_preg_701_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_701_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_701_IE_REG_DPDA_PREG_701_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_701_IE_REG_DPDA_PREG_701_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_701_IE_REG_DPDA_PREG_701_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_701_IE_REG_ADDR (0x0006BD00u)
#define CSL_DFE_DPDA_DPDA_PREG_701_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_701_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_701_q : 23;
#else 
    Uint32 dpda_preg_701_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_701_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_701_Q_REG_DPDA_PREG_701_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_701_Q_REG_DPDA_PREG_701_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_701_Q_REG_DPDA_PREG_701_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_701_Q_REG_ADDR (0x0006BD04u)
#define CSL_DFE_DPDA_DPDA_PREG_701_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_702_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_702_ie : 31;
#else 
    Uint32 dpda_preg_702_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_702_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_702_IE_REG_DPDA_PREG_702_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_702_IE_REG_DPDA_PREG_702_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_702_IE_REG_DPDA_PREG_702_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_702_IE_REG_ADDR (0x0006BE00u)
#define CSL_DFE_DPDA_DPDA_PREG_702_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_702_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_702_q : 23;
#else 
    Uint32 dpda_preg_702_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_702_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_702_Q_REG_DPDA_PREG_702_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_702_Q_REG_DPDA_PREG_702_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_702_Q_REG_DPDA_PREG_702_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_702_Q_REG_ADDR (0x0006BE04u)
#define CSL_DFE_DPDA_DPDA_PREG_702_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_703_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_703_ie : 31;
#else 
    Uint32 dpda_preg_703_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_703_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_703_IE_REG_DPDA_PREG_703_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_703_IE_REG_DPDA_PREG_703_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_703_IE_REG_DPDA_PREG_703_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_703_IE_REG_ADDR (0x0006BF00u)
#define CSL_DFE_DPDA_DPDA_PREG_703_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_703_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_703_q : 23;
#else 
    Uint32 dpda_preg_703_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_703_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_703_Q_REG_DPDA_PREG_703_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_703_Q_REG_DPDA_PREG_703_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_703_Q_REG_DPDA_PREG_703_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_703_Q_REG_ADDR (0x0006BF04u)
#define CSL_DFE_DPDA_DPDA_PREG_703_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_704_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_704_ie : 31;
#else 
    Uint32 dpda_preg_704_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_704_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_704_IE_REG_DPDA_PREG_704_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_704_IE_REG_DPDA_PREG_704_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_704_IE_REG_DPDA_PREG_704_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_704_IE_REG_ADDR (0x0006C000u)
#define CSL_DFE_DPDA_DPDA_PREG_704_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_704_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_704_q : 23;
#else 
    Uint32 dpda_preg_704_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_704_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_704_Q_REG_DPDA_PREG_704_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_704_Q_REG_DPDA_PREG_704_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_704_Q_REG_DPDA_PREG_704_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_704_Q_REG_ADDR (0x0006C004u)
#define CSL_DFE_DPDA_DPDA_PREG_704_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_705_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_705_ie : 31;
#else 
    Uint32 dpda_preg_705_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_705_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_705_IE_REG_DPDA_PREG_705_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_705_IE_REG_DPDA_PREG_705_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_705_IE_REG_DPDA_PREG_705_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_705_IE_REG_ADDR (0x0006C100u)
#define CSL_DFE_DPDA_DPDA_PREG_705_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_705_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_705_q : 23;
#else 
    Uint32 dpda_preg_705_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_705_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_705_Q_REG_DPDA_PREG_705_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_705_Q_REG_DPDA_PREG_705_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_705_Q_REG_DPDA_PREG_705_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_705_Q_REG_ADDR (0x0006C104u)
#define CSL_DFE_DPDA_DPDA_PREG_705_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_706_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_706_ie : 31;
#else 
    Uint32 dpda_preg_706_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_706_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_706_IE_REG_DPDA_PREG_706_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_706_IE_REG_DPDA_PREG_706_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_706_IE_REG_DPDA_PREG_706_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_706_IE_REG_ADDR (0x0006C200u)
#define CSL_DFE_DPDA_DPDA_PREG_706_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_706_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_706_q : 23;
#else 
    Uint32 dpda_preg_706_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_706_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_706_Q_REG_DPDA_PREG_706_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_706_Q_REG_DPDA_PREG_706_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_706_Q_REG_DPDA_PREG_706_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_706_Q_REG_ADDR (0x0006C204u)
#define CSL_DFE_DPDA_DPDA_PREG_706_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_707_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_707_ie : 31;
#else 
    Uint32 dpda_preg_707_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_707_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_707_IE_REG_DPDA_PREG_707_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_707_IE_REG_DPDA_PREG_707_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_707_IE_REG_DPDA_PREG_707_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_707_IE_REG_ADDR (0x0006C300u)
#define CSL_DFE_DPDA_DPDA_PREG_707_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_707_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_707_q : 23;
#else 
    Uint32 dpda_preg_707_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_707_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_707_Q_REG_DPDA_PREG_707_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_707_Q_REG_DPDA_PREG_707_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_707_Q_REG_DPDA_PREG_707_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_707_Q_REG_ADDR (0x0006C304u)
#define CSL_DFE_DPDA_DPDA_PREG_707_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_708_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_708_ie : 31;
#else 
    Uint32 dpda_preg_708_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_708_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_708_IE_REG_DPDA_PREG_708_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_708_IE_REG_DPDA_PREG_708_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_708_IE_REG_DPDA_PREG_708_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_708_IE_REG_ADDR (0x0006C400u)
#define CSL_DFE_DPDA_DPDA_PREG_708_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_708_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_708_q : 23;
#else 
    Uint32 dpda_preg_708_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_708_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_708_Q_REG_DPDA_PREG_708_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_708_Q_REG_DPDA_PREG_708_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_708_Q_REG_DPDA_PREG_708_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_708_Q_REG_ADDR (0x0006C404u)
#define CSL_DFE_DPDA_DPDA_PREG_708_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_709_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_709_ie : 31;
#else 
    Uint32 dpda_preg_709_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_709_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_709_IE_REG_DPDA_PREG_709_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_709_IE_REG_DPDA_PREG_709_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_709_IE_REG_DPDA_PREG_709_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_709_IE_REG_ADDR (0x0006C500u)
#define CSL_DFE_DPDA_DPDA_PREG_709_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_709_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_709_q : 23;
#else 
    Uint32 dpda_preg_709_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_709_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_709_Q_REG_DPDA_PREG_709_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_709_Q_REG_DPDA_PREG_709_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_709_Q_REG_DPDA_PREG_709_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_709_Q_REG_ADDR (0x0006C504u)
#define CSL_DFE_DPDA_DPDA_PREG_709_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_710_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_710_ie : 31;
#else 
    Uint32 dpda_preg_710_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_710_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_710_IE_REG_DPDA_PREG_710_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_710_IE_REG_DPDA_PREG_710_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_710_IE_REG_DPDA_PREG_710_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_710_IE_REG_ADDR (0x0006C600u)
#define CSL_DFE_DPDA_DPDA_PREG_710_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_710_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_710_q : 23;
#else 
    Uint32 dpda_preg_710_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_710_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_710_Q_REG_DPDA_PREG_710_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_710_Q_REG_DPDA_PREG_710_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_710_Q_REG_DPDA_PREG_710_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_710_Q_REG_ADDR (0x0006C604u)
#define CSL_DFE_DPDA_DPDA_PREG_710_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_711_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_711_ie : 31;
#else 
    Uint32 dpda_preg_711_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_711_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_711_IE_REG_DPDA_PREG_711_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_711_IE_REG_DPDA_PREG_711_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_711_IE_REG_DPDA_PREG_711_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_711_IE_REG_ADDR (0x0006C700u)
#define CSL_DFE_DPDA_DPDA_PREG_711_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_711_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_711_q : 23;
#else 
    Uint32 dpda_preg_711_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_711_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_711_Q_REG_DPDA_PREG_711_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_711_Q_REG_DPDA_PREG_711_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_711_Q_REG_DPDA_PREG_711_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_711_Q_REG_ADDR (0x0006C704u)
#define CSL_DFE_DPDA_DPDA_PREG_711_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_712_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_712_ie : 31;
#else 
    Uint32 dpda_preg_712_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_712_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_712_IE_REG_DPDA_PREG_712_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_712_IE_REG_DPDA_PREG_712_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_712_IE_REG_DPDA_PREG_712_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_712_IE_REG_ADDR (0x0006C800u)
#define CSL_DFE_DPDA_DPDA_PREG_712_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_712_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_712_q : 23;
#else 
    Uint32 dpda_preg_712_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_712_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_712_Q_REG_DPDA_PREG_712_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_712_Q_REG_DPDA_PREG_712_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_712_Q_REG_DPDA_PREG_712_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_712_Q_REG_ADDR (0x0006C804u)
#define CSL_DFE_DPDA_DPDA_PREG_712_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_713_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_713_ie : 31;
#else 
    Uint32 dpda_preg_713_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_713_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_713_IE_REG_DPDA_PREG_713_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_713_IE_REG_DPDA_PREG_713_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_713_IE_REG_DPDA_PREG_713_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_713_IE_REG_ADDR (0x0006C900u)
#define CSL_DFE_DPDA_DPDA_PREG_713_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_713_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_713_q : 23;
#else 
    Uint32 dpda_preg_713_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_713_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_713_Q_REG_DPDA_PREG_713_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_713_Q_REG_DPDA_PREG_713_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_713_Q_REG_DPDA_PREG_713_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_713_Q_REG_ADDR (0x0006C904u)
#define CSL_DFE_DPDA_DPDA_PREG_713_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_714_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_714_ie : 31;
#else 
    Uint32 dpda_preg_714_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_714_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_714_IE_REG_DPDA_PREG_714_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_714_IE_REG_DPDA_PREG_714_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_714_IE_REG_DPDA_PREG_714_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_714_IE_REG_ADDR (0x0006CA00u)
#define CSL_DFE_DPDA_DPDA_PREG_714_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_714_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_714_q : 23;
#else 
    Uint32 dpda_preg_714_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_714_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_714_Q_REG_DPDA_PREG_714_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_714_Q_REG_DPDA_PREG_714_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_714_Q_REG_DPDA_PREG_714_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_714_Q_REG_ADDR (0x0006CA04u)
#define CSL_DFE_DPDA_DPDA_PREG_714_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_715_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_715_ie : 31;
#else 
    Uint32 dpda_preg_715_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_715_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_715_IE_REG_DPDA_PREG_715_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_715_IE_REG_DPDA_PREG_715_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_715_IE_REG_DPDA_PREG_715_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_715_IE_REG_ADDR (0x0006CB00u)
#define CSL_DFE_DPDA_DPDA_PREG_715_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_715_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_715_q : 23;
#else 
    Uint32 dpda_preg_715_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_715_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_715_Q_REG_DPDA_PREG_715_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_715_Q_REG_DPDA_PREG_715_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_715_Q_REG_DPDA_PREG_715_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_715_Q_REG_ADDR (0x0006CB04u)
#define CSL_DFE_DPDA_DPDA_PREG_715_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_716_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_716_ie : 31;
#else 
    Uint32 dpda_preg_716_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_716_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_716_IE_REG_DPDA_PREG_716_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_716_IE_REG_DPDA_PREG_716_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_716_IE_REG_DPDA_PREG_716_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_716_IE_REG_ADDR (0x0006CC00u)
#define CSL_DFE_DPDA_DPDA_PREG_716_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_716_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_716_q : 23;
#else 
    Uint32 dpda_preg_716_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_716_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_716_Q_REG_DPDA_PREG_716_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_716_Q_REG_DPDA_PREG_716_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_716_Q_REG_DPDA_PREG_716_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_716_Q_REG_ADDR (0x0006CC04u)
#define CSL_DFE_DPDA_DPDA_PREG_716_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_717_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_717_ie : 31;
#else 
    Uint32 dpda_preg_717_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_717_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_717_IE_REG_DPDA_PREG_717_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_717_IE_REG_DPDA_PREG_717_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_717_IE_REG_DPDA_PREG_717_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_717_IE_REG_ADDR (0x0006CD00u)
#define CSL_DFE_DPDA_DPDA_PREG_717_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_717_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_717_q : 23;
#else 
    Uint32 dpda_preg_717_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_717_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_717_Q_REG_DPDA_PREG_717_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_717_Q_REG_DPDA_PREG_717_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_717_Q_REG_DPDA_PREG_717_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_717_Q_REG_ADDR (0x0006CD04u)
#define CSL_DFE_DPDA_DPDA_PREG_717_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_718_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_718_ie : 31;
#else 
    Uint32 dpda_preg_718_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_718_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_718_IE_REG_DPDA_PREG_718_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_718_IE_REG_DPDA_PREG_718_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_718_IE_REG_DPDA_PREG_718_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_718_IE_REG_ADDR (0x0006CE00u)
#define CSL_DFE_DPDA_DPDA_PREG_718_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_718_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_718_q : 23;
#else 
    Uint32 dpda_preg_718_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_718_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_718_Q_REG_DPDA_PREG_718_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_718_Q_REG_DPDA_PREG_718_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_718_Q_REG_DPDA_PREG_718_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_718_Q_REG_ADDR (0x0006CE04u)
#define CSL_DFE_DPDA_DPDA_PREG_718_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_719_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_719_ie : 31;
#else 
    Uint32 dpda_preg_719_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_719_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_719_IE_REG_DPDA_PREG_719_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_719_IE_REG_DPDA_PREG_719_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_719_IE_REG_DPDA_PREG_719_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_719_IE_REG_ADDR (0x0006CF00u)
#define CSL_DFE_DPDA_DPDA_PREG_719_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_719_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_719_q : 23;
#else 
    Uint32 dpda_preg_719_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_719_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_719_Q_REG_DPDA_PREG_719_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_719_Q_REG_DPDA_PREG_719_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_719_Q_REG_DPDA_PREG_719_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_719_Q_REG_ADDR (0x0006CF04u)
#define CSL_DFE_DPDA_DPDA_PREG_719_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_720_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_720_ie : 31;
#else 
    Uint32 dpda_preg_720_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_720_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_720_IE_REG_DPDA_PREG_720_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_720_IE_REG_DPDA_PREG_720_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_720_IE_REG_DPDA_PREG_720_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_720_IE_REG_ADDR (0x0006D000u)
#define CSL_DFE_DPDA_DPDA_PREG_720_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_720_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_720_q : 23;
#else 
    Uint32 dpda_preg_720_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_720_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_720_Q_REG_DPDA_PREG_720_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_720_Q_REG_DPDA_PREG_720_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_720_Q_REG_DPDA_PREG_720_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_720_Q_REG_ADDR (0x0006D004u)
#define CSL_DFE_DPDA_DPDA_PREG_720_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_721_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_721_ie : 31;
#else 
    Uint32 dpda_preg_721_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_721_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_721_IE_REG_DPDA_PREG_721_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_721_IE_REG_DPDA_PREG_721_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_721_IE_REG_DPDA_PREG_721_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_721_IE_REG_ADDR (0x0006D100u)
#define CSL_DFE_DPDA_DPDA_PREG_721_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_721_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_721_q : 23;
#else 
    Uint32 dpda_preg_721_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_721_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_721_Q_REG_DPDA_PREG_721_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_721_Q_REG_DPDA_PREG_721_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_721_Q_REG_DPDA_PREG_721_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_721_Q_REG_ADDR (0x0006D104u)
#define CSL_DFE_DPDA_DPDA_PREG_721_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_722_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_722_ie : 31;
#else 
    Uint32 dpda_preg_722_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_722_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_722_IE_REG_DPDA_PREG_722_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_722_IE_REG_DPDA_PREG_722_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_722_IE_REG_DPDA_PREG_722_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_722_IE_REG_ADDR (0x0006D200u)
#define CSL_DFE_DPDA_DPDA_PREG_722_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_722_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_722_q : 23;
#else 
    Uint32 dpda_preg_722_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_722_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_722_Q_REG_DPDA_PREG_722_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_722_Q_REG_DPDA_PREG_722_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_722_Q_REG_DPDA_PREG_722_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_722_Q_REG_ADDR (0x0006D204u)
#define CSL_DFE_DPDA_DPDA_PREG_722_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_723_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_723_ie : 31;
#else 
    Uint32 dpda_preg_723_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_723_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_723_IE_REG_DPDA_PREG_723_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_723_IE_REG_DPDA_PREG_723_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_723_IE_REG_DPDA_PREG_723_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_723_IE_REG_ADDR (0x0006D300u)
#define CSL_DFE_DPDA_DPDA_PREG_723_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_723_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_723_q : 23;
#else 
    Uint32 dpda_preg_723_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_723_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_723_Q_REG_DPDA_PREG_723_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_723_Q_REG_DPDA_PREG_723_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_723_Q_REG_DPDA_PREG_723_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_723_Q_REG_ADDR (0x0006D304u)
#define CSL_DFE_DPDA_DPDA_PREG_723_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_724_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_724_ie : 31;
#else 
    Uint32 dpda_preg_724_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_724_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_724_IE_REG_DPDA_PREG_724_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_724_IE_REG_DPDA_PREG_724_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_724_IE_REG_DPDA_PREG_724_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_724_IE_REG_ADDR (0x0006D400u)
#define CSL_DFE_DPDA_DPDA_PREG_724_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_724_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_724_q : 23;
#else 
    Uint32 dpda_preg_724_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_724_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_724_Q_REG_DPDA_PREG_724_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_724_Q_REG_DPDA_PREG_724_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_724_Q_REG_DPDA_PREG_724_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_724_Q_REG_ADDR (0x0006D404u)
#define CSL_DFE_DPDA_DPDA_PREG_724_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_725_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_725_ie : 31;
#else 
    Uint32 dpda_preg_725_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_725_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_725_IE_REG_DPDA_PREG_725_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_725_IE_REG_DPDA_PREG_725_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_725_IE_REG_DPDA_PREG_725_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_725_IE_REG_ADDR (0x0006D500u)
#define CSL_DFE_DPDA_DPDA_PREG_725_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_725_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_725_q : 23;
#else 
    Uint32 dpda_preg_725_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_725_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_725_Q_REG_DPDA_PREG_725_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_725_Q_REG_DPDA_PREG_725_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_725_Q_REG_DPDA_PREG_725_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_725_Q_REG_ADDR (0x0006D504u)
#define CSL_DFE_DPDA_DPDA_PREG_725_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_726_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_726_ie : 31;
#else 
    Uint32 dpda_preg_726_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_726_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_726_IE_REG_DPDA_PREG_726_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_726_IE_REG_DPDA_PREG_726_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_726_IE_REG_DPDA_PREG_726_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_726_IE_REG_ADDR (0x0006D600u)
#define CSL_DFE_DPDA_DPDA_PREG_726_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_726_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_726_q : 23;
#else 
    Uint32 dpda_preg_726_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_726_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_726_Q_REG_DPDA_PREG_726_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_726_Q_REG_DPDA_PREG_726_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_726_Q_REG_DPDA_PREG_726_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_726_Q_REG_ADDR (0x0006D604u)
#define CSL_DFE_DPDA_DPDA_PREG_726_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_727_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_727_ie : 31;
#else 
    Uint32 dpda_preg_727_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_727_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_727_IE_REG_DPDA_PREG_727_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_727_IE_REG_DPDA_PREG_727_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_727_IE_REG_DPDA_PREG_727_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_727_IE_REG_ADDR (0x0006D700u)
#define CSL_DFE_DPDA_DPDA_PREG_727_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_727_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_727_q : 23;
#else 
    Uint32 dpda_preg_727_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_727_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_727_Q_REG_DPDA_PREG_727_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_727_Q_REG_DPDA_PREG_727_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_727_Q_REG_DPDA_PREG_727_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_727_Q_REG_ADDR (0x0006D704u)
#define CSL_DFE_DPDA_DPDA_PREG_727_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_728_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_728_ie : 31;
#else 
    Uint32 dpda_preg_728_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_728_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_728_IE_REG_DPDA_PREG_728_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_728_IE_REG_DPDA_PREG_728_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_728_IE_REG_DPDA_PREG_728_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_728_IE_REG_ADDR (0x0006D800u)
#define CSL_DFE_DPDA_DPDA_PREG_728_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_728_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_728_q : 23;
#else 
    Uint32 dpda_preg_728_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_728_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_728_Q_REG_DPDA_PREG_728_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_728_Q_REG_DPDA_PREG_728_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_728_Q_REG_DPDA_PREG_728_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_728_Q_REG_ADDR (0x0006D804u)
#define CSL_DFE_DPDA_DPDA_PREG_728_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_729_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_729_ie : 31;
#else 
    Uint32 dpda_preg_729_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_729_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_729_IE_REG_DPDA_PREG_729_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_729_IE_REG_DPDA_PREG_729_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_729_IE_REG_DPDA_PREG_729_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_729_IE_REG_ADDR (0x0006D900u)
#define CSL_DFE_DPDA_DPDA_PREG_729_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_729_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_729_q : 23;
#else 
    Uint32 dpda_preg_729_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_729_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_729_Q_REG_DPDA_PREG_729_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_729_Q_REG_DPDA_PREG_729_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_729_Q_REG_DPDA_PREG_729_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_729_Q_REG_ADDR (0x0006D904u)
#define CSL_DFE_DPDA_DPDA_PREG_729_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_730_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_730_ie : 31;
#else 
    Uint32 dpda_preg_730_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_730_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_730_IE_REG_DPDA_PREG_730_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_730_IE_REG_DPDA_PREG_730_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_730_IE_REG_DPDA_PREG_730_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_730_IE_REG_ADDR (0x0006DA00u)
#define CSL_DFE_DPDA_DPDA_PREG_730_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_730_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_730_q : 23;
#else 
    Uint32 dpda_preg_730_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_730_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_730_Q_REG_DPDA_PREG_730_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_730_Q_REG_DPDA_PREG_730_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_730_Q_REG_DPDA_PREG_730_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_730_Q_REG_ADDR (0x0006DA04u)
#define CSL_DFE_DPDA_DPDA_PREG_730_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_731_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_731_ie : 31;
#else 
    Uint32 dpda_preg_731_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_731_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_731_IE_REG_DPDA_PREG_731_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_731_IE_REG_DPDA_PREG_731_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_731_IE_REG_DPDA_PREG_731_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_731_IE_REG_ADDR (0x0006DB00u)
#define CSL_DFE_DPDA_DPDA_PREG_731_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_731_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_731_q : 23;
#else 
    Uint32 dpda_preg_731_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_731_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_731_Q_REG_DPDA_PREG_731_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_731_Q_REG_DPDA_PREG_731_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_731_Q_REG_DPDA_PREG_731_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_731_Q_REG_ADDR (0x0006DB04u)
#define CSL_DFE_DPDA_DPDA_PREG_731_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_732_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_732_ie : 31;
#else 
    Uint32 dpda_preg_732_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_732_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_732_IE_REG_DPDA_PREG_732_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_732_IE_REG_DPDA_PREG_732_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_732_IE_REG_DPDA_PREG_732_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_732_IE_REG_ADDR (0x0006DC00u)
#define CSL_DFE_DPDA_DPDA_PREG_732_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_732_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_732_q : 23;
#else 
    Uint32 dpda_preg_732_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_732_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_732_Q_REG_DPDA_PREG_732_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_732_Q_REG_DPDA_PREG_732_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_732_Q_REG_DPDA_PREG_732_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_732_Q_REG_ADDR (0x0006DC04u)
#define CSL_DFE_DPDA_DPDA_PREG_732_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_733_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_733_ie : 31;
#else 
    Uint32 dpda_preg_733_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_733_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_733_IE_REG_DPDA_PREG_733_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_733_IE_REG_DPDA_PREG_733_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_733_IE_REG_DPDA_PREG_733_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_733_IE_REG_ADDR (0x0006DD00u)
#define CSL_DFE_DPDA_DPDA_PREG_733_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_733_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_733_q : 23;
#else 
    Uint32 dpda_preg_733_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_733_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_733_Q_REG_DPDA_PREG_733_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_733_Q_REG_DPDA_PREG_733_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_733_Q_REG_DPDA_PREG_733_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_733_Q_REG_ADDR (0x0006DD04u)
#define CSL_DFE_DPDA_DPDA_PREG_733_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_734_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_734_ie : 31;
#else 
    Uint32 dpda_preg_734_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_734_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_734_IE_REG_DPDA_PREG_734_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_734_IE_REG_DPDA_PREG_734_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_734_IE_REG_DPDA_PREG_734_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_734_IE_REG_ADDR (0x0006DE00u)
#define CSL_DFE_DPDA_DPDA_PREG_734_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_734_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_734_q : 23;
#else 
    Uint32 dpda_preg_734_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_734_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_734_Q_REG_DPDA_PREG_734_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_734_Q_REG_DPDA_PREG_734_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_734_Q_REG_DPDA_PREG_734_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_734_Q_REG_ADDR (0x0006DE04u)
#define CSL_DFE_DPDA_DPDA_PREG_734_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_735_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_735_ie : 31;
#else 
    Uint32 dpda_preg_735_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_735_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_735_IE_REG_DPDA_PREG_735_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_735_IE_REG_DPDA_PREG_735_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_735_IE_REG_DPDA_PREG_735_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_735_IE_REG_ADDR (0x0006DF00u)
#define CSL_DFE_DPDA_DPDA_PREG_735_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_735_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_735_q : 23;
#else 
    Uint32 dpda_preg_735_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_735_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_735_Q_REG_DPDA_PREG_735_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_735_Q_REG_DPDA_PREG_735_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_735_Q_REG_DPDA_PREG_735_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_735_Q_REG_ADDR (0x0006DF04u)
#define CSL_DFE_DPDA_DPDA_PREG_735_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_736_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_736_ie : 31;
#else 
    Uint32 dpda_preg_736_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_736_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_736_IE_REG_DPDA_PREG_736_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_736_IE_REG_DPDA_PREG_736_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_736_IE_REG_DPDA_PREG_736_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_736_IE_REG_ADDR (0x0006E000u)
#define CSL_DFE_DPDA_DPDA_PREG_736_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_736_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_736_q : 23;
#else 
    Uint32 dpda_preg_736_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_736_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_736_Q_REG_DPDA_PREG_736_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_736_Q_REG_DPDA_PREG_736_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_736_Q_REG_DPDA_PREG_736_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_736_Q_REG_ADDR (0x0006E004u)
#define CSL_DFE_DPDA_DPDA_PREG_736_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_737_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_737_ie : 31;
#else 
    Uint32 dpda_preg_737_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_737_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_737_IE_REG_DPDA_PREG_737_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_737_IE_REG_DPDA_PREG_737_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_737_IE_REG_DPDA_PREG_737_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_737_IE_REG_ADDR (0x0006E100u)
#define CSL_DFE_DPDA_DPDA_PREG_737_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_737_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_737_q : 23;
#else 
    Uint32 dpda_preg_737_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_737_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_737_Q_REG_DPDA_PREG_737_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_737_Q_REG_DPDA_PREG_737_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_737_Q_REG_DPDA_PREG_737_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_737_Q_REG_ADDR (0x0006E104u)
#define CSL_DFE_DPDA_DPDA_PREG_737_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_738_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_738_ie : 31;
#else 
    Uint32 dpda_preg_738_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_738_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_738_IE_REG_DPDA_PREG_738_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_738_IE_REG_DPDA_PREG_738_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_738_IE_REG_DPDA_PREG_738_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_738_IE_REG_ADDR (0x0006E200u)
#define CSL_DFE_DPDA_DPDA_PREG_738_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_738_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_738_q : 23;
#else 
    Uint32 dpda_preg_738_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_738_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_738_Q_REG_DPDA_PREG_738_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_738_Q_REG_DPDA_PREG_738_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_738_Q_REG_DPDA_PREG_738_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_738_Q_REG_ADDR (0x0006E204u)
#define CSL_DFE_DPDA_DPDA_PREG_738_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_739_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_739_ie : 31;
#else 
    Uint32 dpda_preg_739_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_739_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_739_IE_REG_DPDA_PREG_739_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_739_IE_REG_DPDA_PREG_739_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_739_IE_REG_DPDA_PREG_739_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_739_IE_REG_ADDR (0x0006E300u)
#define CSL_DFE_DPDA_DPDA_PREG_739_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_739_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_739_q : 23;
#else 
    Uint32 dpda_preg_739_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_739_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_739_Q_REG_DPDA_PREG_739_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_739_Q_REG_DPDA_PREG_739_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_739_Q_REG_DPDA_PREG_739_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_739_Q_REG_ADDR (0x0006E304u)
#define CSL_DFE_DPDA_DPDA_PREG_739_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_740_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_740_ie : 31;
#else 
    Uint32 dpda_preg_740_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_740_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_740_IE_REG_DPDA_PREG_740_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_740_IE_REG_DPDA_PREG_740_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_740_IE_REG_DPDA_PREG_740_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_740_IE_REG_ADDR (0x0006E400u)
#define CSL_DFE_DPDA_DPDA_PREG_740_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_740_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_740_q : 23;
#else 
    Uint32 dpda_preg_740_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_740_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_740_Q_REG_DPDA_PREG_740_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_740_Q_REG_DPDA_PREG_740_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_740_Q_REG_DPDA_PREG_740_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_740_Q_REG_ADDR (0x0006E404u)
#define CSL_DFE_DPDA_DPDA_PREG_740_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_741_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_741_ie : 31;
#else 
    Uint32 dpda_preg_741_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_741_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_741_IE_REG_DPDA_PREG_741_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_741_IE_REG_DPDA_PREG_741_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_741_IE_REG_DPDA_PREG_741_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_741_IE_REG_ADDR (0x0006E500u)
#define CSL_DFE_DPDA_DPDA_PREG_741_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_741_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_741_q : 23;
#else 
    Uint32 dpda_preg_741_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_741_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_741_Q_REG_DPDA_PREG_741_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_741_Q_REG_DPDA_PREG_741_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_741_Q_REG_DPDA_PREG_741_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_741_Q_REG_ADDR (0x0006E504u)
#define CSL_DFE_DPDA_DPDA_PREG_741_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_742_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_742_ie : 31;
#else 
    Uint32 dpda_preg_742_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_742_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_742_IE_REG_DPDA_PREG_742_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_742_IE_REG_DPDA_PREG_742_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_742_IE_REG_DPDA_PREG_742_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_742_IE_REG_ADDR (0x0006E600u)
#define CSL_DFE_DPDA_DPDA_PREG_742_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_742_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_742_q : 23;
#else 
    Uint32 dpda_preg_742_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_742_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_742_Q_REG_DPDA_PREG_742_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_742_Q_REG_DPDA_PREG_742_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_742_Q_REG_DPDA_PREG_742_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_742_Q_REG_ADDR (0x0006E604u)
#define CSL_DFE_DPDA_DPDA_PREG_742_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_743_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_743_ie : 31;
#else 
    Uint32 dpda_preg_743_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_743_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_743_IE_REG_DPDA_PREG_743_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_743_IE_REG_DPDA_PREG_743_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_743_IE_REG_DPDA_PREG_743_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_743_IE_REG_ADDR (0x0006E700u)
#define CSL_DFE_DPDA_DPDA_PREG_743_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_743_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_743_q : 23;
#else 
    Uint32 dpda_preg_743_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_743_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_743_Q_REG_DPDA_PREG_743_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_743_Q_REG_DPDA_PREG_743_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_743_Q_REG_DPDA_PREG_743_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_743_Q_REG_ADDR (0x0006E704u)
#define CSL_DFE_DPDA_DPDA_PREG_743_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_744_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_744_ie : 31;
#else 
    Uint32 dpda_preg_744_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_744_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_744_IE_REG_DPDA_PREG_744_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_744_IE_REG_DPDA_PREG_744_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_744_IE_REG_DPDA_PREG_744_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_744_IE_REG_ADDR (0x0006E800u)
#define CSL_DFE_DPDA_DPDA_PREG_744_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_744_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_744_q : 23;
#else 
    Uint32 dpda_preg_744_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_744_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_744_Q_REG_DPDA_PREG_744_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_744_Q_REG_DPDA_PREG_744_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_744_Q_REG_DPDA_PREG_744_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_744_Q_REG_ADDR (0x0006E804u)
#define CSL_DFE_DPDA_DPDA_PREG_744_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_745_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_745_ie : 31;
#else 
    Uint32 dpda_preg_745_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_745_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_745_IE_REG_DPDA_PREG_745_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_745_IE_REG_DPDA_PREG_745_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_745_IE_REG_DPDA_PREG_745_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_745_IE_REG_ADDR (0x0006E900u)
#define CSL_DFE_DPDA_DPDA_PREG_745_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_745_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_745_q : 23;
#else 
    Uint32 dpda_preg_745_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_745_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_745_Q_REG_DPDA_PREG_745_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_745_Q_REG_DPDA_PREG_745_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_745_Q_REG_DPDA_PREG_745_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_745_Q_REG_ADDR (0x0006E904u)
#define CSL_DFE_DPDA_DPDA_PREG_745_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_746_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_746_ie : 31;
#else 
    Uint32 dpda_preg_746_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_746_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_746_IE_REG_DPDA_PREG_746_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_746_IE_REG_DPDA_PREG_746_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_746_IE_REG_DPDA_PREG_746_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_746_IE_REG_ADDR (0x0006EA00u)
#define CSL_DFE_DPDA_DPDA_PREG_746_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_746_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_746_q : 23;
#else 
    Uint32 dpda_preg_746_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_746_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_746_Q_REG_DPDA_PREG_746_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_746_Q_REG_DPDA_PREG_746_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_746_Q_REG_DPDA_PREG_746_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_746_Q_REG_ADDR (0x0006EA04u)
#define CSL_DFE_DPDA_DPDA_PREG_746_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_747_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_747_ie : 31;
#else 
    Uint32 dpda_preg_747_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_747_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_747_IE_REG_DPDA_PREG_747_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_747_IE_REG_DPDA_PREG_747_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_747_IE_REG_DPDA_PREG_747_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_747_IE_REG_ADDR (0x0006EB00u)
#define CSL_DFE_DPDA_DPDA_PREG_747_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_747_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_747_q : 23;
#else 
    Uint32 dpda_preg_747_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_747_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_747_Q_REG_DPDA_PREG_747_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_747_Q_REG_DPDA_PREG_747_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_747_Q_REG_DPDA_PREG_747_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_747_Q_REG_ADDR (0x0006EB04u)
#define CSL_DFE_DPDA_DPDA_PREG_747_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_748_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_748_ie : 31;
#else 
    Uint32 dpda_preg_748_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_748_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_748_IE_REG_DPDA_PREG_748_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_748_IE_REG_DPDA_PREG_748_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_748_IE_REG_DPDA_PREG_748_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_748_IE_REG_ADDR (0x0006EC00u)
#define CSL_DFE_DPDA_DPDA_PREG_748_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_748_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_748_q : 23;
#else 
    Uint32 dpda_preg_748_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_748_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_748_Q_REG_DPDA_PREG_748_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_748_Q_REG_DPDA_PREG_748_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_748_Q_REG_DPDA_PREG_748_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_748_Q_REG_ADDR (0x0006EC04u)
#define CSL_DFE_DPDA_DPDA_PREG_748_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_749_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_749_ie : 31;
#else 
    Uint32 dpda_preg_749_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_749_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_749_IE_REG_DPDA_PREG_749_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_749_IE_REG_DPDA_PREG_749_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_749_IE_REG_DPDA_PREG_749_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_749_IE_REG_ADDR (0x0006ED00u)
#define CSL_DFE_DPDA_DPDA_PREG_749_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_749_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_749_q : 23;
#else 
    Uint32 dpda_preg_749_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_749_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_749_Q_REG_DPDA_PREG_749_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_749_Q_REG_DPDA_PREG_749_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_749_Q_REG_DPDA_PREG_749_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_749_Q_REG_ADDR (0x0006ED04u)
#define CSL_DFE_DPDA_DPDA_PREG_749_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_750_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_750_ie : 31;
#else 
    Uint32 dpda_preg_750_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_750_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_750_IE_REG_DPDA_PREG_750_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_750_IE_REG_DPDA_PREG_750_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_750_IE_REG_DPDA_PREG_750_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_750_IE_REG_ADDR (0x0006EE00u)
#define CSL_DFE_DPDA_DPDA_PREG_750_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_750_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_750_q : 23;
#else 
    Uint32 dpda_preg_750_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_750_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_750_Q_REG_DPDA_PREG_750_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_750_Q_REG_DPDA_PREG_750_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_750_Q_REG_DPDA_PREG_750_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_750_Q_REG_ADDR (0x0006EE04u)
#define CSL_DFE_DPDA_DPDA_PREG_750_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_751_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_751_ie : 31;
#else 
    Uint32 dpda_preg_751_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_751_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_751_IE_REG_DPDA_PREG_751_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_751_IE_REG_DPDA_PREG_751_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_751_IE_REG_DPDA_PREG_751_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_751_IE_REG_ADDR (0x0006EF00u)
#define CSL_DFE_DPDA_DPDA_PREG_751_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_751_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_751_q : 23;
#else 
    Uint32 dpda_preg_751_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_751_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_751_Q_REG_DPDA_PREG_751_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_751_Q_REG_DPDA_PREG_751_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_751_Q_REG_DPDA_PREG_751_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_751_Q_REG_ADDR (0x0006EF04u)
#define CSL_DFE_DPDA_DPDA_PREG_751_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_752_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_752_ie : 31;
#else 
    Uint32 dpda_preg_752_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_752_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_752_IE_REG_DPDA_PREG_752_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_752_IE_REG_DPDA_PREG_752_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_752_IE_REG_DPDA_PREG_752_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_752_IE_REG_ADDR (0x0006F000u)
#define CSL_DFE_DPDA_DPDA_PREG_752_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_752_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_752_q : 23;
#else 
    Uint32 dpda_preg_752_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_752_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_752_Q_REG_DPDA_PREG_752_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_752_Q_REG_DPDA_PREG_752_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_752_Q_REG_DPDA_PREG_752_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_752_Q_REG_ADDR (0x0006F004u)
#define CSL_DFE_DPDA_DPDA_PREG_752_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_753_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_753_ie : 31;
#else 
    Uint32 dpda_preg_753_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_753_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_753_IE_REG_DPDA_PREG_753_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_753_IE_REG_DPDA_PREG_753_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_753_IE_REG_DPDA_PREG_753_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_753_IE_REG_ADDR (0x0006F100u)
#define CSL_DFE_DPDA_DPDA_PREG_753_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_753_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_753_q : 23;
#else 
    Uint32 dpda_preg_753_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_753_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_753_Q_REG_DPDA_PREG_753_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_753_Q_REG_DPDA_PREG_753_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_753_Q_REG_DPDA_PREG_753_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_753_Q_REG_ADDR (0x0006F104u)
#define CSL_DFE_DPDA_DPDA_PREG_753_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_754_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_754_ie : 31;
#else 
    Uint32 dpda_preg_754_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_754_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_754_IE_REG_DPDA_PREG_754_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_754_IE_REG_DPDA_PREG_754_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_754_IE_REG_DPDA_PREG_754_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_754_IE_REG_ADDR (0x0006F200u)
#define CSL_DFE_DPDA_DPDA_PREG_754_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_754_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_754_q : 23;
#else 
    Uint32 dpda_preg_754_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_754_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_754_Q_REG_DPDA_PREG_754_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_754_Q_REG_DPDA_PREG_754_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_754_Q_REG_DPDA_PREG_754_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_754_Q_REG_ADDR (0x0006F204u)
#define CSL_DFE_DPDA_DPDA_PREG_754_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_755_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_755_ie : 31;
#else 
    Uint32 dpda_preg_755_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_755_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_755_IE_REG_DPDA_PREG_755_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_755_IE_REG_DPDA_PREG_755_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_755_IE_REG_DPDA_PREG_755_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_755_IE_REG_ADDR (0x0006F300u)
#define CSL_DFE_DPDA_DPDA_PREG_755_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_755_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_755_q : 23;
#else 
    Uint32 dpda_preg_755_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_755_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_755_Q_REG_DPDA_PREG_755_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_755_Q_REG_DPDA_PREG_755_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_755_Q_REG_DPDA_PREG_755_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_755_Q_REG_ADDR (0x0006F304u)
#define CSL_DFE_DPDA_DPDA_PREG_755_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_756_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_756_ie : 31;
#else 
    Uint32 dpda_preg_756_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_756_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_756_IE_REG_DPDA_PREG_756_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_756_IE_REG_DPDA_PREG_756_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_756_IE_REG_DPDA_PREG_756_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_756_IE_REG_ADDR (0x0006F400u)
#define CSL_DFE_DPDA_DPDA_PREG_756_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_756_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_756_q : 23;
#else 
    Uint32 dpda_preg_756_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_756_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_756_Q_REG_DPDA_PREG_756_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_756_Q_REG_DPDA_PREG_756_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_756_Q_REG_DPDA_PREG_756_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_756_Q_REG_ADDR (0x0006F404u)
#define CSL_DFE_DPDA_DPDA_PREG_756_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_757_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_757_ie : 31;
#else 
    Uint32 dpda_preg_757_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_757_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_757_IE_REG_DPDA_PREG_757_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_757_IE_REG_DPDA_PREG_757_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_757_IE_REG_DPDA_PREG_757_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_757_IE_REG_ADDR (0x0006F500u)
#define CSL_DFE_DPDA_DPDA_PREG_757_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_757_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_757_q : 23;
#else 
    Uint32 dpda_preg_757_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_757_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_757_Q_REG_DPDA_PREG_757_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_757_Q_REG_DPDA_PREG_757_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_757_Q_REG_DPDA_PREG_757_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_757_Q_REG_ADDR (0x0006F504u)
#define CSL_DFE_DPDA_DPDA_PREG_757_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_758_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_758_ie : 31;
#else 
    Uint32 dpda_preg_758_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_758_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_758_IE_REG_DPDA_PREG_758_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_758_IE_REG_DPDA_PREG_758_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_758_IE_REG_DPDA_PREG_758_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_758_IE_REG_ADDR (0x0006F600u)
#define CSL_DFE_DPDA_DPDA_PREG_758_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_758_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_758_q : 23;
#else 
    Uint32 dpda_preg_758_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_758_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_758_Q_REG_DPDA_PREG_758_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_758_Q_REG_DPDA_PREG_758_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_758_Q_REG_DPDA_PREG_758_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_758_Q_REG_ADDR (0x0006F604u)
#define CSL_DFE_DPDA_DPDA_PREG_758_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_759_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_759_ie : 31;
#else 
    Uint32 dpda_preg_759_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_759_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_759_IE_REG_DPDA_PREG_759_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_759_IE_REG_DPDA_PREG_759_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_759_IE_REG_DPDA_PREG_759_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_759_IE_REG_ADDR (0x0006F700u)
#define CSL_DFE_DPDA_DPDA_PREG_759_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_759_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_759_q : 23;
#else 
    Uint32 dpda_preg_759_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_759_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_759_Q_REG_DPDA_PREG_759_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_759_Q_REG_DPDA_PREG_759_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_759_Q_REG_DPDA_PREG_759_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_759_Q_REG_ADDR (0x0006F704u)
#define CSL_DFE_DPDA_DPDA_PREG_759_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_760_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_760_ie : 31;
#else 
    Uint32 dpda_preg_760_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_760_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_760_IE_REG_DPDA_PREG_760_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_760_IE_REG_DPDA_PREG_760_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_760_IE_REG_DPDA_PREG_760_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_760_IE_REG_ADDR (0x0006F800u)
#define CSL_DFE_DPDA_DPDA_PREG_760_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_760_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_760_q : 23;
#else 
    Uint32 dpda_preg_760_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_760_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_760_Q_REG_DPDA_PREG_760_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_760_Q_REG_DPDA_PREG_760_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_760_Q_REG_DPDA_PREG_760_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_760_Q_REG_ADDR (0x0006F804u)
#define CSL_DFE_DPDA_DPDA_PREG_760_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_761_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_761_ie : 31;
#else 
    Uint32 dpda_preg_761_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_761_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_761_IE_REG_DPDA_PREG_761_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_761_IE_REG_DPDA_PREG_761_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_761_IE_REG_DPDA_PREG_761_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_761_IE_REG_ADDR (0x0006F900u)
#define CSL_DFE_DPDA_DPDA_PREG_761_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_761_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_761_q : 23;
#else 
    Uint32 dpda_preg_761_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_761_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_761_Q_REG_DPDA_PREG_761_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_761_Q_REG_DPDA_PREG_761_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_761_Q_REG_DPDA_PREG_761_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_761_Q_REG_ADDR (0x0006F904u)
#define CSL_DFE_DPDA_DPDA_PREG_761_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_762_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_762_ie : 31;
#else 
    Uint32 dpda_preg_762_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_762_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_762_IE_REG_DPDA_PREG_762_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_762_IE_REG_DPDA_PREG_762_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_762_IE_REG_DPDA_PREG_762_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_762_IE_REG_ADDR (0x0006FA00u)
#define CSL_DFE_DPDA_DPDA_PREG_762_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_762_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_762_q : 23;
#else 
    Uint32 dpda_preg_762_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_762_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_762_Q_REG_DPDA_PREG_762_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_762_Q_REG_DPDA_PREG_762_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_762_Q_REG_DPDA_PREG_762_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_762_Q_REG_ADDR (0x0006FA04u)
#define CSL_DFE_DPDA_DPDA_PREG_762_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_763_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_763_ie : 31;
#else 
    Uint32 dpda_preg_763_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_763_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_763_IE_REG_DPDA_PREG_763_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_763_IE_REG_DPDA_PREG_763_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_763_IE_REG_DPDA_PREG_763_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_763_IE_REG_ADDR (0x0006FB00u)
#define CSL_DFE_DPDA_DPDA_PREG_763_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_763_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_763_q : 23;
#else 
    Uint32 dpda_preg_763_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_763_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_763_Q_REG_DPDA_PREG_763_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_763_Q_REG_DPDA_PREG_763_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_763_Q_REG_DPDA_PREG_763_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_763_Q_REG_ADDR (0x0006FB04u)
#define CSL_DFE_DPDA_DPDA_PREG_763_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_764_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_764_ie : 31;
#else 
    Uint32 dpda_preg_764_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_764_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_764_IE_REG_DPDA_PREG_764_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_764_IE_REG_DPDA_PREG_764_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_764_IE_REG_DPDA_PREG_764_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_764_IE_REG_ADDR (0x0006FC00u)
#define CSL_DFE_DPDA_DPDA_PREG_764_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_764_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_764_q : 23;
#else 
    Uint32 dpda_preg_764_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_764_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_764_Q_REG_DPDA_PREG_764_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_764_Q_REG_DPDA_PREG_764_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_764_Q_REG_DPDA_PREG_764_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_764_Q_REG_ADDR (0x0006FC04u)
#define CSL_DFE_DPDA_DPDA_PREG_764_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_765_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_765_ie : 31;
#else 
    Uint32 dpda_preg_765_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_765_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_765_IE_REG_DPDA_PREG_765_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_765_IE_REG_DPDA_PREG_765_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_765_IE_REG_DPDA_PREG_765_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_765_IE_REG_ADDR (0x0006FD00u)
#define CSL_DFE_DPDA_DPDA_PREG_765_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_765_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_765_q : 23;
#else 
    Uint32 dpda_preg_765_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_765_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_765_Q_REG_DPDA_PREG_765_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_765_Q_REG_DPDA_PREG_765_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_765_Q_REG_DPDA_PREG_765_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_765_Q_REG_ADDR (0x0006FD04u)
#define CSL_DFE_DPDA_DPDA_PREG_765_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_766_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_766_ie : 31;
#else 
    Uint32 dpda_preg_766_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_766_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_766_IE_REG_DPDA_PREG_766_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_766_IE_REG_DPDA_PREG_766_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_766_IE_REG_DPDA_PREG_766_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_766_IE_REG_ADDR (0x0006FE00u)
#define CSL_DFE_DPDA_DPDA_PREG_766_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_766_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_766_q : 23;
#else 
    Uint32 dpda_preg_766_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_766_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_766_Q_REG_DPDA_PREG_766_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_766_Q_REG_DPDA_PREG_766_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_766_Q_REG_DPDA_PREG_766_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_766_Q_REG_ADDR (0x0006FE04u)
#define CSL_DFE_DPDA_DPDA_PREG_766_Q_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_767_IE */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 1;
    Uint32 dpda_preg_767_ie : 31;
#else 
    Uint32 dpda_preg_767_ie : 31;
    Uint32 rsvd0 : 1;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_767_IE_REG;

/* data[30:0] = {exp_common[7:0], mantissa_real_cfp[22:0]} for even addresses */
#define CSL_DFE_DPDA_DPDA_PREG_767_IE_REG_DPDA_PREG_767_IE_MASK (0x7FFFFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_767_IE_REG_DPDA_PREG_767_IE_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_767_IE_REG_DPDA_PREG_767_IE_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_767_IE_REG_ADDR (0x0006FF00u)
#define CSL_DFE_DPDA_DPDA_PREG_767_IE_REG_RESETVAL (0x00000000u)

/* DPDA_PREG_767_Q */
typedef struct 
{
#ifdef _BIG_ENDIAN
    Uint32 rsvd0 : 9;
    Uint32 dpda_preg_767_q : 23;
#else 
    Uint32 dpda_preg_767_q : 23;
    Uint32 rsvd0 : 9;
#endif 
} CSL_DFE_DPDA_DPDA_PREG_767_Q_REG;

/* data[22:0] = {mantissa_imag_cfp[22:0]} for odd addresses */
#define CSL_DFE_DPDA_DPDA_PREG_767_Q_REG_DPDA_PREG_767_Q_MASK (0x007FFFFFu)
#define CSL_DFE_DPDA_DPDA_PREG_767_Q_REG_DPDA_PREG_767_Q_SHIFT (0x00000000u)
#define CSL_DFE_DPDA_DPDA_PREG_767_Q_REG_DPDA_PREG_767_Q_RESETVAL (0x00000000u)

#define CSL_DFE_DPDA_DPDA_PREG_767_Q_REG_ADDR (0x0006FF04u)
#define CSL_DFE_DPDA_DPDA_PREG_767_Q_REG_RESETVAL (0x00000000u)

#endif /* CSLR_DFE_DPDA_H__ */