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cslr_cm3_nvic.h

cslr_cm3_nvic.h 167 KB
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
  1. /********************************************************************
    2. 

  2.  * Copyright (C) 2013-2014 Texas Instruments Incorporated.
    3. 

  3.  *
    4. 

  4.  *  Redistribution and use in source and binary forms, with or without
    5. 

  5.  *  modification, are permitted provided that the following conditions
    6. 

  6.  *  are met:
    7. 

  7.  *
    8. 

  8.  *    Redistributions of source code must retain the above copyright
    9. 

  9.  *    notice, this list of conditions and the following disclaimer.
    10. 

  10.  *
    11. 

  11.  *    Redistributions in binary form must reproduce the above copyright
    12. 

  12.  *    notice, this list of conditions and the following disclaimer in the
    13. 

  13.  *    documentation and/or other materials provided with the
    14. 

  14.  *    distribution.
    15. 

  15.  *
    16. 

  16.  *    Neither the name of Texas Instruments Incorporated nor the names of
    17. 

  17.  *    its contributors may be used to endorse or promote products derived
    18. 

  18.  *    from this software without specific prior written permission.
    19. 

  19.  *
    20. 

  20.  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    21. 

  21.  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    22. 

  22.  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    23. 

  23.  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    24. 

  24.  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    25. 

  25.  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    26. 

  26.  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    27. 

  27.  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    28. 

  28.  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    29. 

  29.  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    30. 

  30.  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31. 

  31.  *
    32. 

  32. */
    33. 

  33. #ifndef CSLR_CM3NVIC_H_
    34. 

  34. #define CSLR_CM3NVIC_H_
    35. 

  35. 

  36. #ifdef __cplusplus
    37. 

  37. extern "C"
    38. 

  38. {
    39. 

  39. #endif
    40. 

  40. #include <ti/csl/cslr.h>
    41. 

  41. #include <ti/csl/tistdtypes.h>
    42. 

  42. 

  43. 

  44. /**************************************************************************
    45. 

  45. * Register Overlay Structure for __ALL__
    46. 

  46. **************************************************************************/
    47. 

  47. typedef struct {
    48. 

  48.     volatile Uint32 INTERRUPT_CONTROLLER_TYPE;
    49. 

  49.     volatile Uint32 AUXILIARY_CONTROL;
    50. 

  50.     volatile Uint8  RSVD0[4];
    51. 

  51.     volatile Uint32 SYSTICK_CONTROL_AND_STATUS;
    52. 

  52.     volatile Uint32 SYSTICK_RELOAD_VALUE;
    53. 

  53.     volatile Uint32 SYSTICK_CURRENT_VALUE;
    54. 

  54.     volatile Uint32 SYSTICK_CALIBRATION_VALUE;
    55. 

  55.     volatile Uint8  RSVD1[224];
    56. 

  56.     volatile Uint32 EXTERNAL_INTERRUPT_SETEN_0_31;
    57. 

  57.     volatile Uint32 EXTERNAL_INTERRUPT_SETEN_32_63;
    58. 

  58.     volatile Uint32 EXTERNAL_INTERRUPT_SETEN_64_95;
    59. 

  59.     volatile Uint8  RSVD2[116];
    60. 

  60.     volatile Uint32 EXTERNAL_INTERRUPT_CLREN_0_31;
    61. 

  61.     volatile Uint32 EXTERNAL_INTERRUPT_CLREN_32_63;
    62. 

  62.     volatile Uint32 EXTERNAL_INTERRUPT_CLREN_64_95;
    63. 

  63.     volatile Uint8  RSVD3[116];
    64. 

  64.     volatile Uint32 EXTERNAL_INTERRUPT_SETPEND_0_31;
    65. 

  65.     volatile Uint32 EXTERNAL_INTERRUPT_SETPEND_32_63;
    66. 

  66.     volatile Uint32 EXTERNAL_INTERRUPT_SETPEND_64_95;
    67. 

  67.     volatile Uint8  RSVD4[116];
    68. 

  68.     volatile Uint32 EXTERNAL_INTERRUPT_CLRPEND_0_31;
    69. 

  69.     volatile Uint32 EXTERNAL_INTERRUPT_CLRPEND_32_63;
    70. 

  70.     volatile Uint32 EXTERNAL_INTERRUPT_CLRPEND_64_95;
    71. 

  71.     volatile Uint8  RSVD5[116];
    72. 

  72.     volatile Uint32 EXTERNAL_INTERRUPT_ACTIVE_0_31;
    73. 

  73.     volatile Uint32 EXTERNAL_INTERRUPT_ACTIVE_32_63;
    74. 

  74.     volatile Uint32 EXTERNAL_INTERRUPT_ACTIVE_64_95;
    75. 

  75.     volatile Uint8  RSVD6[244];
    76. 

  76.     volatile Uint32 EXTERNAL_INT_PRIORITY_LEVEL[16];
    77. 

  77.     volatile Uint8  RSVD7[2240];
    78. 

  78.     volatile Uint32 CPU_ID_BASE_REGISTER;
    79. 

  79.     volatile Uint32 INTERRUPT_CONTROL_AND_STATE;
    80. 

  80.     volatile Uint32 VECTOR_TABLE_OFFSET;
    81. 

  81.     volatile Uint32 APPLICATION_INT_AND_RESET_CONTROL;
    82. 

  82.     volatile Uint32 SYSTEM_CONTROL;
    83. 

  83.     volatile Uint32 CONFIGURATION_CONTROL;
    84. 

  84.     volatile Uint32 SYSTEM_EXCEPTION_PRIORITY_LEVEL[3];
    85. 

  85.     volatile Uint32 SYSTEM_HANDLER_CONTROL_AND_STATE;
    86. 

  86.     volatile Uint32 CONFIGURABLE_FAULT_STATUS;
    87. 

  87.     volatile Uint32 HARD_FAULT_STATUS;
    88. 

  88.     volatile Uint32 DEBUG_FAULT_STATUS;
    89. 

  89.     volatile Uint32 MEMORY_MANAGE_ADDRESS;
    90. 

  90.     volatile Uint32 BUS_FAULT_MANAGE_ADDRESS;
    91. 

  91.     volatile Uint32 AUXILIARY_FAULT_STATUS;
    92. 

  92.     volatile Uint8  RSVD8[80];
    93. 

  93.     volatile Uint32 MPU_TYPE;
    94. 

  94.     volatile Uint32 MPU_CONTROL;
    95. 

  95.     volatile Uint32 MPU_REGION_NUMBER;
    96. 

  96.     volatile Uint32 MPU_REGION_BASE_ADDRESS;
    97. 

  97.     volatile Uint32 MPU_REGION_BASE_ATTRIBUTE_AND_SIZE;
    98. 

  98.     volatile Uint32 MPU_ALIAS[6];
    99. 

  99.     volatile Uint8  RSVD9[52];
    100. 

  100.     volatile Uint32 DEBUG_HALTING_CONTROL_AND_STATUS;
    101. 

  101.     volatile Uint32 DEBUG_CORE_REGISTER_SELECTOR;
    102. 

  102.     volatile Uint32 DEBUG_CORE_REGISTER_DATA;
    103. 

  103.     volatile Uint32 DEBUG_EXCEPTION_AND_MONITOR_CONTROL;
    104. 

  104.     volatile Uint8  RSVD10[256];
    105. 

  105.     volatile Uint32 SOFTWARE_TRIGGER_INTERRUPT;
    106. 

  106.     volatile Uint8  RSVD11[204];
    107. 

  107.     volatile Uint32 NVIC_PERIPHERAL_ID_4;
    108. 

  108.     volatile Uint32 NVIC_PERIPHERAL_ID_5;
    109. 

  109.     volatile Uint32 NVIC_PERIPHERAL_ID_6;
    110. 

  110.     volatile Uint32 NVIC_PERIPHERAL_ID_7;
    111. 

  111.     volatile Uint32 NVIC_PERIPHERAL_ID_0;
    112. 

  112.     volatile Uint32 NVIC_PERIPHERAL_ID_1;
    113. 

  113.     volatile Uint32 NVIC_PERIPHERAL_ID_2;
    114. 

  114.     volatile Uint32 NVIC_PERIPHERAL_ID_3;
    115. 

  115.     volatile Uint32 NVIC_COMPONENT_ID_0;
    116. 

  116.     volatile Uint32 NVIC_COMPONENT_ID_1;
    117. 

  117.     volatile Uint32 NVIC_COMPONENT_ID_2;
    118. 

  118.     volatile Uint32 NVIC_COMPONENT_ID_3;
    119. 

  119. } CSL_Cm3NvicRegs;
    120. 

  120. 

  121. 

  122. /**************************************************************************
    123. 

  123. * Register Macros
    124. 

  124. **************************************************************************/
    125. 

  125. 

  126. /* Nber of interrupt inputs in step of 32: 0 =1 to 32 1 = 33 to 64 ... */
    127. 

  127. #define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE                   (0x4U)
    128. 

  128. 

  129. /* AUXILIARY_CONTROL */
    130. 

  130. #define CSL_CM3NVIC_AUXILIARY_CONTROL                           (0x8U)
    131. 

  131. 

  132. /* SYSTICK_CONTROL_AND_STATUS */
    133. 

  133. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS                  (0x10U)
    134. 

  134. 

  135. /* SYSTICK_RELOAD_VALUE */
    136. 

  136. #define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE                        (0x14U)
    137. 

  137. 

  138. /* SYSTICK_CURRENT_VALUE */
    139. 

  139. #define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE                       (0x18U)
    140. 

  140. 

  141. /* SYSTICK_CALIBRATION_VALUE */
    142. 

  142. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE                   (0x1CU)
    143. 

  143. 

  144. /* Interrupt set enable bits. For write operation: 1 = enable interrupt 0 = no
    145. 

  145.  * effect. For read operation: 1 = enable interrupt 0 = disable interrupt
    146. 

  146.  * Writing 0 to a SETENA bit has no effect. Reading the bit returns its
    147. 

  147.  * current enable state. Reset clears the SETENA fields. */
    148. 

  148. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31               (0x100U)
    149. 

  149. 

  150. /* Interrupt set enable bits. For write operation: 1 = enable interrupt 0 = no
    151. 

  151.  * effect. For read operation: 1 = enable interrupt 0 = disable interrupt
    152. 

  152.  * Writing 0 to a SETENA bit has no effect. Reading the bit returns its
    153. 

  153.  * current enable state. Reset clears the SETENA fields. */
    154. 

  154. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63              (0x104U)
    155. 

  155. 

  156. /* Interrupt set enable bits. For write operation: 1 = enable interrupt 0 = no
    157. 

  157.  * effect. For read operation: 1 = enable interrupt 0 = disable interrupt
    158. 

  158.  * Writing 0 to a SETENA bit has no effect. Reading the bit returns its
    159. 

  159.  * current enable state. Reset clears the SETENA fields. */
    160. 

  160. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95              (0x108U)
    161. 

  161. 

  162. /* Interrupt clear-enable bits. For write operation: 1 = disable interrupt 0 =
    163. 

  163.  * no effect. For read operation: 1 = enable interrupt 0 = disable interrupt.
    164. 

  164.  * Writing 0 to a CLRENA bit has no effect. Reading the bit returns its
    165. 

  165.  * current enable state. */
    166. 

  166. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31               (0x180U)
    167. 

  167. 

  168. /* Interrupt set enable bits. For write operation: 1 = enable interrupt 0 = no
    169. 

  169.  * effect. For read operation: 1 = enable interrupt 0 = disable interrupt
    170. 

  170.  * Writing 0 to a SETENA bit has no effect. Reading the bit returns its
    171. 

  171.  * current enable state. Reset clears the SETENA fields. */
    172. 

  172. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63              (0x184U)
    173. 

  173. 

  174. /* Interrupt clear-enable bits. For write operation: 1 = disable interrupt 0 =
    175. 

  175.  * no effect. For read operation: 1 = enable interrupt 0 = disable interrupt.
    176. 

  176.  * Writing 0 to a CLRENA bit has no effect. Reading the bit returns its
    177. 

  177.  * current enable state. */
    178. 

  178. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95              (0x188U)
    179. 

  179. 

  180. /* Interrupt set-pending bits: 1 = pend the corresponding interrupt 0 =
    181. 

  181.  * corresponding interrupt not pending. Writing 0 to a SETPEND bit has no
    182. 

  182.  * effect. Reading the bit returns its current state. */
    183. 

  183. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31             (0x200U)
    184. 

  184. 

  185. /* Interrupt set-pending bits: 1 = pend the corresponding interrupt 0 =
    186. 

  186.  * corresponding interrupt not pending. Writing 0 to a SETPEND bit has no
    187. 

  187.  * effect. Reading the bit returns its current state. */
    188. 

  188. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63            (0x204U)
    189. 

  189. 

  190. /* Interrupt set-pending bits: 1 = pend the corresponding interrupt 0 =
    191. 

  191.  * corresponding interrupt not pending. Writing 0 to a SETPEND bit has no
    192. 

  192.  * effect. Reading the bit returns its current state. */
    193. 

  193. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95            (0x208U)
    194. 

  194. 

  195. /* Interrupt clear-pending bits: 1 = clear pending interrupt 0 = do not clear
    196. 

  196.  * pending interrupt. Writing 0 to a CLRPEND bit has no effect. Reading the
    197. 

  197.  * bit returns its current state. */
    198. 

  198. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31             (0x280U)
    199. 

  199. 

  200. /* Interrupt clear-pending bits: 1 = clear pending interrupt 0 = do not clear
    201. 

  201.  * pending interrupt. Writing 0 to a CLRPEND bit has no effect. Reading the
    202. 

  202.  * bit returns its current state. */
    203. 

  203. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63            (0x284U)
    204. 

  204. 

  205. /* Interrupt clear-pending bits: 1 = clear pending interrupt 0 = do not clear
    206. 

  206.  * pending interrupt. Writing 0 to a CLRPEND bit has no effect. Reading the
    207. 

  207.  * bit returns its current state. */
    208. 

  208. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95            (0x288U)
    209. 

  209. 

  210. /* Interrupt active flags: 1 = interrupt active or pre-empted and stacked 0 =
    211. 

  211.  * interrupt not active or stacked. */
    212. 

  212. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31              (0x300U)
    213. 

  213. 

  214. /* Interrupt active flags: 1 = interrupt active or pre-empted and stacked 0 =
    215. 

  215.  * interrupt not active or stacked. */
    216. 

  216. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63             (0x304U)
    217. 

  217. 

  218. /* Interrupt active flags: 1 = interrupt active or pre-empted and stacked 0 =
    219. 

  219.  * interrupt not active or stacked. */
    220. 

  220. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95             (0x308U)
    221. 

  221. 

  222. /* Use the Interrupt Priority Registers to assign a priority from 0 to 255 to
    223. 

  223.  * each of the available interrupts. 0 is the highest priority, and 255 is the
    224. 

  224.  * lowest. The priority registers are stored with the Most Significant Bit
    225. 

  225.  * (MSB) first. This means that if there are four bits of priority, the
    226. 

  226.  * priority value is stored in bits [7:4] of the byte. However, if there are
    227. 

  227.  * three bits of priority, the priority value is stored in bits [7:5] of the
    228. 

  228.  * byte. This means that an application can work even if it does not know how
    229. 

  229.  * many priorities are possible. */
    230. 

  230. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL(i)              (0x400U + ((i) * (0x4U)))
    231. 

  231. 

  232. /* CPU_ID_BASE_REGISTER */
    233. 

  233. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER                        (0xD00U)
    234. 

  234. 

  235. /* INTERRUPT_CONTROL_AND_STATE */
    236. 

  236. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE                 (0xD04U)
    237. 

  237. 

  238. /* VECTOR_TABLE_OFFSET */
    239. 

  239. #define CSL_CM3NVIC_VECTOR_TABLE_OFFSET                         (0xD08U)
    240. 

  240. 

  241. /* APPLICATION_INT_AND_RESET_CONTROL */
    242. 

  242. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL           (0xD0CU)
    243. 

  243. 

  244. /* SYSTEM_CONTROL */
    245. 

  245. #define CSL_CM3NVIC_SYSTEM_CONTROL                              (0xD10U)
    246. 

  246. 

  247. /* CONFIGURATION_CONTROL */
    248. 

  248. #define CSL_CM3NVIC_CONFIGURATION_CONTROL                       (0xD14U)
    249. 

  249. 

  250. /* SYSTEM_EXCEPTION_PRIORITY_LEVEL */
    251. 

  251. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL(i)          (0xD18U + ((i) * (0x4U)))
    252. 

  252. 

  253. /* SYSTEM_HANDLER_CONTROL_AND_STATE */
    254. 

  254. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE            (0xD24U)
    255. 

  255. 

  256. /* CONFIGURABLE_FAULT_STATUS */
    257. 

  257. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS                   (0xD28U)
    258. 

  258. 

  259. /* HARD_FAULT_STATUS */
    260. 

  260. #define CSL_CM3NVIC_HARD_FAULT_STATUS                           (0xD2CU)
    261. 

  261. 

  262. /* DEBUG_FAULT_STATUS */
    263. 

  263. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS                          (0xD30U)
    264. 

  264. 

  265. /* MEMORY_MANAGE_ADDRESS */
    266. 

  266. #define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS                       (0xD34U)
    267. 

  267. 

  268. /* BUS_FAULT_MANAGE_ADDRESS */
    269. 

  269. #define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS                    (0xD38U)
    270. 

  270. 

  271. /* AUXILIARY_FAULT_STATUS */
    272. 

  272. #define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS                      (0xD3CU)
    273. 

  273. 

  274. /* MPU_TYPE */
    275. 

  275. #define CSL_CM3NVIC_MPU_TYPE                                    (0xD90U)
    276. 

  276. 

  277. /* MPU_CONTROL */
    278. 

  278. #define CSL_CM3NVIC_MPU_CONTROL                                 (0xD94U)
    279. 

  279. 

  280. /* MPU_REGION_NUMBER */
    281. 

  281. #define CSL_CM3NVIC_MPU_REGION_NUMBER                           (0xD98U)
    282. 

  282. 

  283. /* MPU_REGION_BASE_ADDRESS */
    284. 

  284. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS                     (0xD9CU)
    285. 

  285. 

  286. /* MPU_REGION_BASE_ATTRIBUTE_AND_SIZE */
    287. 

  287. #define CSL_CM3NVIC_MPU_REGION_BASE_ATTRIBUTE_AND_SIZE          (0xDA0U)
    288. 

  288. 

  289. /* MPU_ALIAS */
    290. 

  290. #define CSL_CM3NVIC_MPU_ALIAS(i)                                (0xDA4U + ((i) * (0x4U)))
    291. 

  291. 

  292. /* DEBUG_HALTING_CONTROL_AND_STATUS */
    293. 

  293. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS            (0xDF0U)
    294. 

  294. 

  295. /* DEBUG_CORE_REGISTER_SELECTOR */
    296. 

  296. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR                (0xDF4U)
    297. 

  297. 

  298. /* DEBUG_CORE_REGISTER_DATA */
    299. 

  299. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA                    (0xDF8U)
    300. 

  300. 

  301. /* DEBUG_EXCEPTION_AND_MONITOR_CONTROL */
    302. 

  302. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL         (0xDFCU)
    303. 

  303. 

  304. /* SOFTWARE_TRIGGER_INTERRUPT */
    305. 

  305. #define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT                  (0xF00U)
    306. 

  306. 

  307. /* NVIC_PERIPHERAL_ID_4 */
    308. 

  308. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4                        (0xFD0U)
    309. 

  309. 

  310. /* NVIC_PERIPHERAL_ID_5 */
    311. 

  311. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5                        (0xFD4U)
    312. 

  312. 

  313. /* NVIC_PERIPHERAL_ID_6 */
    314. 

  314. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6                        (0xFD8U)
    315. 

  315. 

  316. /* NVIC_PERIPHERAL_ID_7 */
    317. 

  317. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7                        (0xFDCU)
    318. 

  318. 

  319. /* NVIC_PERIPHERAL_ID_0 */
    320. 

  320. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0                        (0xFE0U)
    321. 

  321. 

  322. /* NVIC_PERIPHERAL_ID_1 */
    323. 

  323. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1                        (0xFE4U)
    324. 

  324. 

  325. /* NVIC_PERIPHERAL_ID_2 */
    326. 

  326. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2                        (0xFE8U)
    327. 

  327. 

  328. /* NVIC_PERIPHERAL_ID_3 */
    329. 

  329. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3                        (0xFECU)
    330. 

  330. 

  331. /* NVIC_COMPONENT_ID_0 */
    332. 

  332. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_0                         (0xFF0U)
    333. 

  333. 

  334. /* NVIC_COMPONENT_ID_1 */
    335. 

  335. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_1                         (0xFF4U)
    336. 

  336. 

  337. /* NVIC_COMPONENT_ID_2 */
    338. 

  338. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_2                         (0xFF8U)
    339. 

  339. 

  340. /* NVIC_COMPONENT_ID_3 */
    341. 

  341. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_3                         (0xFFCU)
    342. 

  342. 

  343. 

  344. /**************************************************************************
    345. 

  345. * Field Definition Macros
    346. 

  346. **************************************************************************/
    347. 

  347. 

  348. /* INTERRUPT_CONTROLLER_TYPE */
    349. 

  349. 

  350. #define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_INTLINESNUM_MASK  (0x0000001FU)
    351. 

  351. #define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_INTLINESNUM_SHIFT  (0U)
    352. 

  352. #define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_INTLINESNUM_RESETVAL  (0x00000003U)
    353. 

  353. #define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_INTLINESNUM_MAX   (0x0000001fU)
    354. 

  354. 

  355. #define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_RESETVAL          (0x00000003U)
    356. 

  356. 

  357. /* AUXILIARY_CONTROL */
    358. 

  358. 

  359. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISMCYCINT_MASK           (0x00000001U)
    360. 

  360. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISMCYCINT_SHIFT          (0U)
    361. 

  361. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISMCYCINT_RESETVAL       (0x00000000U)
    362. 

  362. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISMCYCINT_MAX            (0x00000001U)
    363. 

  363. 

  364. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISDEFWBUF_MASK           (0x00000002U)
    365. 

  365. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISDEFWBUF_SHIFT          (1U)
    366. 

  366. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISDEFWBUF_RESETVAL       (0x00000000U)
    367. 

  367. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISDEFWBUF_MAX            (0x00000001U)
    368. 

  368. 

  369. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISFOLD_MASK              (0x00000004U)
    370. 

  370. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISFOLD_SHIFT             (2U)
    371. 

  371. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISFOLD_RESETVAL          (0x00000000U)
    372. 

  372. #define CSL_CM3NVIC_AUXILIARY_CONTROL_DISFOLD_MAX               (0x00000001U)
    373. 

  373. 

  374. #define CSL_CM3NVIC_AUXILIARY_CONTROL_RESETVAL                  (0x00000000U)
    375. 

  375. 

  376. /* SYSTICK_CONTROL_AND_STATUS */
    377. 

  377. 

  378. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_ENABLE_MASK      (0x00000001U)
    379. 

  379. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_ENABLE_SHIFT     (0U)
    380. 

  380. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_ENABLE_RESETVAL  (0x00000000U)
    381. 

  381. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_ENABLE_MAX       (0x00000001U)
    382. 

  382. 

  383. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_TICKINT_MASK     (0x00000002U)
    384. 

  384. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_TICKINT_SHIFT    (1U)
    385. 

  385. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_TICKINT_RESETVAL  (0x00000000U)
    386. 

  386. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_TICKINT_MAX      (0x00000001U)
    387. 

  387. 

  388. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_CLKSOURCE_MASK   (0x00000004U)
    389. 

  389. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_CLKSOURCE_SHIFT  (2U)
    390. 

  390. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_CLKSOURCE_RESETVAL  (0x00000000U)
    391. 

  391. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_CLKSOURCE_MAX    (0x00000001U)
    392. 

  392. 

  393. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_COUNTFLAG_MASK   (0x00010000U)
    394. 

  394. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_COUNTFLAG_SHIFT  (16U)
    395. 

  395. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_COUNTFLAG_RESETVAL  (0x00000000U)
    396. 

  396. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_COUNTFLAG_MAX    (0x00000001U)
    397. 

  397. 

  398. #define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_RESETVAL         (0x00000000U)
    399. 

  399. 

  400. /* SYSTICK_RELOAD_VALUE */
    401. 

  401. 

  402. #define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RELOAD_MASK            (0x00FFFFFFU)
    403. 

  403. #define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RELOAD_SHIFT           (0U)
    404. 

  404. #define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RELOAD_RESETVAL        (0x00000000U)
    405. 

  405. #define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RELOAD_MAX             (0x00ffffffU)
    406. 

  406. 

  407. #define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RESETVAL               (0x00000000U)
    408. 

  408. 

  409. /* SYSTICK_CURRENT_VALUE */
    410. 

  410. 

  411. #define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_CURRENT_MASK          (0x00000001U)
    412. 

  412. #define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_CURRENT_SHIFT         (0U)
    413. 

  413. #define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_CURRENT_RESETVAL      (0x00000000U)
    414. 

  414. #define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_CURRENT_MAX           (0x00000001U)
    415. 

  415. 

  416. #define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_RESETVAL              (0x00000000U)
    417. 

  417. 

  418. /* SYSTICK_CALIBRATION_VALUE */
    419. 

  419. 

  420. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_TENMS_MASK        (0x00FFFFFFU)
    421. 

  421. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_TENMS_SHIFT       (0U)
    422. 

  422. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_TENMS_RESETVAL    (0x00000000U)
    423. 

  423. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_TENMS_MAX         (0x00ffffffU)
    424. 

  424. 

  425. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_NOREF_MASK        (0x80000000U)
    426. 

  426. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_NOREF_SHIFT       (31U)
    427. 

  427. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_NOREF_RESETVAL    (0x00000000U)
    428. 

  428. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_NOREF_MAX         (0x00000001U)
    429. 

  429. 

  430. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_SKEW_MASK         (0x40000000U)
    431. 

  431. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_SKEW_SHIFT        (30U)
    432. 

  432. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_SKEW_RESETVAL     (0x00000000U)
    433. 

  433. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_SKEW_MAX          (0x00000001U)
    434. 

  434. 

  435. #define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_RESETVAL          (0x00000000U)
    436. 

  436. 

  437. /* EXTERNAL_INTERRUPT_SETEN_0_31 */
    438. 

  438. 

  439. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA0_MASK  (0x00000001U)
    440. 

  440. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA0_SHIFT  (0U)
    441. 

  441. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA0_RESETVAL  (0x00000000U)
    442. 

  442. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA0_MAX   (0x00000001U)
    443. 

  443. 

  444. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA1_MASK  (0x00000002U)
    445. 

  445. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA1_SHIFT  (1U)
    446. 

  446. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA1_RESETVAL  (0x00000000U)
    447. 

  447. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA1_MAX   (0x00000001U)
    448. 

  448. 

  449. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA2_MASK  (0x00000004U)
    450. 

  450. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA2_SHIFT  (2U)
    451. 

  451. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA2_RESETVAL  (0x00000000U)
    452. 

  452. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA2_MAX   (0x00000001U)
    453. 

  453. 

  454. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA3_MASK  (0x00000008U)
    455. 

  455. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA3_SHIFT  (3U)
    456. 

  456. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA3_RESETVAL  (0x00000000U)
    457. 

  457. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA3_MAX   (0x00000001U)
    458. 

  458. 

  459. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA4_MASK  (0x00000010U)
    460. 

  460. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA4_SHIFT  (4U)
    461. 

  461. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA4_RESETVAL  (0x00000000U)
    462. 

  462. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA4_MAX   (0x00000001U)
    463. 

  463. 

  464. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA5_MASK  (0x00000020U)
    465. 

  465. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA5_SHIFT  (5U)
    466. 

  466. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA5_RESETVAL  (0x00000000U)
    467. 

  467. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA5_MAX   (0x00000001U)
    468. 

  468. 

  469. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA6_MASK  (0x00000040U)
    470. 

  470. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA6_SHIFT  (6U)
    471. 

  471. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA6_RESETVAL  (0x00000000U)
    472. 

  472. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA6_MAX   (0x00000001U)
    473. 

  473. 

  474. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA7_MASK  (0x00000080U)
    475. 

  475. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA7_SHIFT  (7U)
    476. 

  476. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA7_RESETVAL  (0x00000000U)
    477. 

  477. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA7_MAX   (0x00000001U)
    478. 

  478. 

  479. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA8_MASK  (0x00000100U)
    480. 

  480. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA8_SHIFT  (8U)
    481. 

  481. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA8_RESETVAL  (0x00000000U)
    482. 

  482. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA8_MAX   (0x00000001U)
    483. 

  483. 

  484. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA9_MASK  (0x00000200U)
    485. 

  485. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA9_SHIFT  (9U)
    486. 

  486. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA9_RESETVAL  (0x00000000U)
    487. 

  487. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA9_MAX   (0x00000001U)
    488. 

  488. 

  489. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA10_MASK  (0x00000400U)
    490. 

  490. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA10_SHIFT  (10U)
    491. 

  491. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA10_RESETVAL  (0x00000000U)
    492. 

  492. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA10_MAX  (0x00000001U)
    493. 

  493. 

  494. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA11_MASK  (0x00000800U)
    495. 

  495. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA11_SHIFT  (11U)
    496. 

  496. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA11_RESETVAL  (0x00000000U)
    497. 

  497. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA11_MAX  (0x00000001U)
    498. 

  498. 

  499. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA12_MASK  (0x00001000U)
    500. 

  500. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA12_SHIFT  (12U)
    501. 

  501. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA12_RESETVAL  (0x00000000U)
    502. 

  502. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA12_MAX  (0x00000001U)
    503. 

  503. 

  504. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA13_MASK  (0x00002000U)
    505. 

  505. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA13_SHIFT  (13U)
    506. 

  506. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA13_RESETVAL  (0x00000000U)
    507. 

  507. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA13_MAX  (0x00000001U)
    508. 

  508. 

  509. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA14_MASK  (0x00004000U)
    510. 

  510. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA14_SHIFT  (14U)
    511. 

  511. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA14_RESETVAL  (0x00000000U)
    512. 

  512. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA14_MAX  (0x00000001U)
    513. 

  513. 

  514. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA15_MASK  (0x00008000U)
    515. 

  515. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA15_SHIFT  (15U)
    516. 

  516. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA15_RESETVAL  (0x00000000U)
    517. 

  517. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA15_MAX  (0x00000001U)
    518. 

  518. 

  519. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA16_MASK  (0x00010000U)
    520. 

  520. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA16_SHIFT  (16U)
    521. 

  521. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA16_RESETVAL  (0x00000000U)
    522. 

  522. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA16_MAX  (0x00000001U)
    523. 

  523. 

  524. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA17_MASK  (0x00020000U)
    525. 

  525. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA17_SHIFT  (17U)
    526. 

  526. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA17_RESETVAL  (0x00000000U)
    527. 

  527. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA17_MAX  (0x00000001U)
    528. 

  528. 

  529. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA18_MASK  (0x00040000U)
    530. 

  530. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA18_SHIFT  (18U)
    531. 

  531. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA18_RESETVAL  (0x00000000U)
    532. 

  532. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA18_MAX  (0x00000001U)
    533. 

  533. 

  534. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA19_MASK  (0x00080000U)
    535. 

  535. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA19_SHIFT  (19U)
    536. 

  536. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA19_RESETVAL  (0x00000000U)
    537. 

  537. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA19_MAX  (0x00000001U)
    538. 

  538. 

  539. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA20_MASK  (0x00100000U)
    540. 

  540. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA20_SHIFT  (20U)
    541. 

  541. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA20_RESETVAL  (0x00000000U)
    542. 

  542. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA20_MAX  (0x00000001U)
    543. 

  543. 

  544. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA21_MASK  (0x00200000U)
    545. 

  545. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA21_SHIFT  (21U)
    546. 

  546. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA21_RESETVAL  (0x00000000U)
    547. 

  547. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA21_MAX  (0x00000001U)
    548. 

  548. 

  549. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA22_MASK  (0x00400000U)
    550. 

  550. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA22_SHIFT  (22U)
    551. 

  551. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA22_RESETVAL  (0x00000000U)
    552. 

  552. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA22_MAX  (0x00000001U)
    553. 

  553. 

  554. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA23_MASK  (0x00800000U)
    555. 

  555. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA23_SHIFT  (23U)
    556. 

  556. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA23_RESETVAL  (0x00000000U)
    557. 

  557. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA23_MAX  (0x00000001U)
    558. 

  558. 

  559. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA24_MASK  (0x01000000U)
    560. 

  560. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA24_SHIFT  (24U)
    561. 

  561. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA24_RESETVAL  (0x00000000U)
    562. 

  562. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA24_MAX  (0x00000001U)
    563. 

  563. 

  564. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA25_MASK  (0x02000000U)
    565. 

  565. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA25_SHIFT  (25U)
    566. 

  566. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA25_RESETVAL  (0x00000000U)
    567. 

  567. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA25_MAX  (0x00000001U)
    568. 

  568. 

  569. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA26_MASK  (0x04000000U)
    570. 

  570. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA26_SHIFT  (26U)
    571. 

  571. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA26_RESETVAL  (0x00000000U)
    572. 

  572. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA26_MAX  (0x00000001U)
    573. 

  573. 

  574. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA27_MASK  (0x08000000U)
    575. 

  575. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA27_SHIFT  (27U)
    576. 

  576. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA27_RESETVAL  (0x00000000U)
    577. 

  577. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA27_MAX  (0x00000001U)
    578. 

  578. 

  579. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA28_MASK  (0x10000000U)
    580. 

  580. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA28_SHIFT  (28U)
    581. 

  581. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA28_RESETVAL  (0x00000000U)
    582. 

  582. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA28_MAX  (0x00000001U)
    583. 

  583. 

  584. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA29_MASK  (0x20000000U)
    585. 

  585. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA29_SHIFT  (29U)
    586. 

  586. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA29_RESETVAL  (0x00000000U)
    587. 

  587. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA29_MAX  (0x00000001U)
    588. 

  588. 

  589. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA30_MASK  (0x40000000U)
    590. 

  590. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA30_SHIFT  (30U)
    591. 

  591. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA30_RESETVAL  (0x00000000U)
    592. 

  592. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA30_MAX  (0x00000001U)
    593. 

  593. 

  594. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA31_MASK  (0x80000000U)
    595. 

  595. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA31_SHIFT  (31U)
    596. 

  596. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA31_RESETVAL  (0x00000000U)
    597. 

  597. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA31_MAX  (0x00000001U)
    598. 

  598. 

  599. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_RESETVAL      (0x00000000U)
    600. 

  600. 

  601. /* EXTERNAL_INTERRUPT_SETEN_32_63 */
    602. 

  602. 

  603. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA32_MASK  (0x00000001U)
    604. 

  604. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA32_SHIFT  (0U)
    605. 

  605. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA32_RESETVAL  (0x00000000U)
    606. 

  606. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA32_MAX  (0x00000001U)
    607. 

  607. 

  608. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA33_MASK  (0x00000002U)
    609. 

  609. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA33_SHIFT  (1U)
    610. 

  610. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA33_RESETVAL  (0x00000000U)
    611. 

  611. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA33_MAX  (0x00000001U)
    612. 

  612. 

  613. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA34_MASK  (0x00000004U)
    614. 

  614. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA34_SHIFT  (2U)
    615. 

  615. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA34_RESETVAL  (0x00000000U)
    616. 

  616. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA34_MAX  (0x00000001U)
    617. 

  617. 

  618. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA35_MASK  (0x00000008U)
    619. 

  619. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA35_SHIFT  (3U)
    620. 

  620. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA35_RESETVAL  (0x00000000U)
    621. 

  621. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA35_MAX  (0x00000001U)
    622. 

  622. 

  623. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA36_MASK  (0x00000010U)
    624. 

  624. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA36_SHIFT  (4U)
    625. 

  625. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA36_RESETVAL  (0x00000000U)
    626. 

  626. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA36_MAX  (0x00000001U)
    627. 

  627. 

  628. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA37_MASK  (0x00000020U)
    629. 

  629. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA37_SHIFT  (5U)
    630. 

  630. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA37_RESETVAL  (0x00000000U)
    631. 

  631. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA37_MAX  (0x00000001U)
    632. 

  632. 

  633. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA38_MASK  (0x00000040U)
    634. 

  634. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA38_SHIFT  (6U)
    635. 

  635. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA38_RESETVAL  (0x00000000U)
    636. 

  636. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA38_MAX  (0x00000001U)
    637. 

  637. 

  638. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA39_MASK  (0x00000080U)
    639. 

  639. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA39_SHIFT  (7U)
    640. 

  640. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA39_RESETVAL  (0x00000000U)
    641. 

  641. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA39_MAX  (0x00000001U)
    642. 

  642. 

  643. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA40_MASK  (0x00000100U)
    644. 

  644. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA40_SHIFT  (8U)
    645. 

  645. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA40_RESETVAL  (0x00000000U)
    646. 

  646. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA40_MAX  (0x00000001U)
    647. 

  647. 

  648. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA41_MASK  (0x00000200U)
    649. 

  649. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA41_SHIFT  (9U)
    650. 

  650. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA41_RESETVAL  (0x00000000U)
    651. 

  651. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA41_MAX  (0x00000001U)
    652. 

  652. 

  653. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA42_MASK  (0x00000400U)
    654. 

  654. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA42_SHIFT  (10U)
    655. 

  655. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA42_RESETVAL  (0x00000000U)
    656. 

  656. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA42_MAX  (0x00000001U)
    657. 

  657. 

  658. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA43_MASK  (0x00000800U)
    659. 

  659. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA43_SHIFT  (11U)
    660. 

  660. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA43_RESETVAL  (0x00000000U)
    661. 

  661. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA43_MAX  (0x00000001U)
    662. 

  662. 

  663. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA44_MASK  (0x00001000U)
    664. 

  664. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA44_SHIFT  (12U)
    665. 

  665. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA44_RESETVAL  (0x00000000U)
    666. 

  666. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA44_MAX  (0x00000001U)
    667. 

  667. 

  668. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA45_MASK  (0x00002000U)
    669. 

  669. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA45_SHIFT  (13U)
    670. 

  670. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA45_RESETVAL  (0x00000000U)
    671. 

  671. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA45_MAX  (0x00000001U)
    672. 

  672. 

  673. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA46_MASK  (0x00004000U)
    674. 

  674. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA46_SHIFT  (14U)
    675. 

  675. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA46_RESETVAL  (0x00000000U)
    676. 

  676. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA46_MAX  (0x00000001U)
    677. 

  677. 

  678. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA47_MASK  (0x00008000U)
    679. 

  679. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA47_SHIFT  (15U)
    680. 

  680. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA47_RESETVAL  (0x00000000U)
    681. 

  681. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA47_MAX  (0x00000001U)
    682. 

  682. 

  683. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA48_MASK  (0x00010000U)
    684. 

  684. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA48_SHIFT  (16U)
    685. 

  685. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA48_RESETVAL  (0x00000000U)
    686. 

  686. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA48_MAX  (0x00000001U)
    687. 

  687. 

  688. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA49_MASK  (0x00020000U)
    689. 

  689. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA49_SHIFT  (17U)
    690. 

  690. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA49_RESETVAL  (0x00000000U)
    691. 

  691. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA49_MAX  (0x00000001U)
    692. 

  692. 

  693. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA50_MASK  (0x00040000U)
    694. 

  694. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA50_SHIFT  (18U)
    695. 

  695. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA50_RESETVAL  (0x00000000U)
    696. 

  696. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA50_MAX  (0x00000001U)
    697. 

  697. 

  698. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA51_MASK  (0x00080000U)
    699. 

  699. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA51_SHIFT  (19U)
    700. 

  700. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA51_RESETVAL  (0x00000000U)
    701. 

  701. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA51_MAX  (0x00000001U)
    702. 

  702. 

  703. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA52_MASK  (0x00100000U)
    704. 

  704. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA52_SHIFT  (20U)
    705. 

  705. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA52_RESETVAL  (0x00000000U)
    706. 

  706. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA52_MAX  (0x00000001U)
    707. 

  707. 

  708. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA53_MASK  (0x00200000U)
    709. 

  709. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA53_SHIFT  (21U)
    710. 

  710. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA53_RESETVAL  (0x00000000U)
    711. 

  711. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA53_MAX  (0x00000001U)
    712. 

  712. 

  713. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA54_MASK  (0x00400000U)
    714. 

  714. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA54_SHIFT  (22U)
    715. 

  715. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA54_RESETVAL  (0x00000000U)
    716. 

  716. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA54_MAX  (0x00000001U)
    717. 

  717. 

  718. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA55_MASK  (0x00800000U)
    719. 

  719. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA55_SHIFT  (23U)
    720. 

  720. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA55_RESETVAL  (0x00000000U)
    721. 

  721. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA55_MAX  (0x00000001U)
    722. 

  722. 

  723. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA56_MASK  (0x01000000U)
    724. 

  724. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA56_SHIFT  (24U)
    725. 

  725. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA56_RESETVAL  (0x00000000U)
    726. 

  726. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA56_MAX  (0x00000001U)
    727. 

  727. 

  728. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA57_MASK  (0x02000000U)
    729. 

  729. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA57_SHIFT  (25U)
    730. 

  730. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA57_RESETVAL  (0x00000000U)
    731. 

  731. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA57_MAX  (0x00000001U)
    732. 

  732. 

  733. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA58_MASK  (0x04000000U)
    734. 

  734. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA58_SHIFT  (26U)
    735. 

  735. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA58_RESETVAL  (0x00000000U)
    736. 

  736. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA58_MAX  (0x00000001U)
    737. 

  737. 

  738. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA59_MASK  (0x08000000U)
    739. 

  739. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA59_SHIFT  (27U)
    740. 

  740. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA59_RESETVAL  (0x00000000U)
    741. 

  741. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA59_MAX  (0x00000001U)
    742. 

  742. 

  743. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA60_MASK  (0x10000000U)
    744. 

  744. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA60_SHIFT  (28U)
    745. 

  745. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA60_RESETVAL  (0x00000000U)
    746. 

  746. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA60_MAX  (0x00000001U)
    747. 

  747. 

  748. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA61_MASK  (0x20000000U)
    749. 

  749. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA61_SHIFT  (29U)
    750. 

  750. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA61_RESETVAL  (0x00000000U)
    751. 

  751. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA61_MAX  (0x00000001U)
    752. 

  752. 

  753. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA62_MASK  (0x40000000U)
    754. 

  754. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA62_SHIFT  (30U)
    755. 

  755. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA62_RESETVAL  (0x00000000U)
    756. 

  756. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA62_MAX  (0x00000001U)
    757. 

  757. 

  758. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA63_MASK  (0x80000000U)
    759. 

  759. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA63_SHIFT  (31U)
    760. 

  760. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA63_RESETVAL  (0x00000000U)
    761. 

  761. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA63_MAX  (0x00000001U)
    762. 

  762. 

  763. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_RESETVAL     (0x00000000U)
    764. 

  764. 

  765. /* EXTERNAL_INTERRUPT_SETEN_64_95 */
    766. 

  766. 

  767. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_SETENA64_MASK  (0x00000001U)
    768. 

  768. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_SETENA64_SHIFT  (0U)
    769. 

  769. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_SETENA64_RESETVAL  (0x00000000U)
    770. 

  770. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_SETENA64_MAX  (0x00000001U)
    771. 

  771. 

  772. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_RESETVAL     (0x00000000U)
    773. 

  773. 

  774. /* EXTERNAL_INTERRUPT_CLREN_0_31 */
    775. 

  775. 

  776. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA0_MASK  (0x00000001U)
    777. 

  777. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA0_SHIFT  (0U)
    778. 

  778. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA0_RESETVAL  (0x00000000U)
    779. 

  779. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA0_MAX   (0x00000001U)
    780. 

  780. 

  781. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA1_MASK  (0x00000002U)
    782. 

  782. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA1_SHIFT  (1U)
    783. 

  783. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA1_RESETVAL  (0x00000000U)
    784. 

  784. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA1_MAX   (0x00000001U)
    785. 

  785. 

  786. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA2_MASK  (0x00000004U)
    787. 

  787. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA2_SHIFT  (2U)
    788. 

  788. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA2_RESETVAL  (0x00000000U)
    789. 

  789. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA2_MAX   (0x00000001U)
    790. 

  790. 

  791. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA3_MASK  (0x00000008U)
    792. 

  792. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA3_SHIFT  (3U)
    793. 

  793. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA3_RESETVAL  (0x00000000U)
    794. 

  794. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA3_MAX   (0x00000001U)
    795. 

  795. 

  796. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA4_MASK  (0x00000010U)
    797. 

  797. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA4_SHIFT  (4U)
    798. 

  798. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA4_RESETVAL  (0x00000000U)
    799. 

  799. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA4_MAX   (0x00000001U)
    800. 

  800. 

  801. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA5_MASK  (0x00000020U)
    802. 

  802. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA5_SHIFT  (5U)
    803. 

  803. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA5_RESETVAL  (0x00000000U)
    804. 

  804. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA5_MAX   (0x00000001U)
    805. 

  805. 

  806. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA6_MASK  (0x00000040U)
    807. 

  807. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA6_SHIFT  (6U)
    808. 

  808. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA6_RESETVAL  (0x00000000U)
    809. 

  809. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA6_MAX   (0x00000001U)
    810. 

  810. 

  811. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA7_MASK  (0x00000080U)
    812. 

  812. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA7_SHIFT  (7U)
    813. 

  813. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA7_RESETVAL  (0x00000000U)
    814. 

  814. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA7_MAX   (0x00000001U)
    815. 

  815. 

  816. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA8_MASK  (0x00000100U)
    817. 

  817. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA8_SHIFT  (8U)
    818. 

  818. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA8_RESETVAL  (0x00000000U)
    819. 

  819. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA8_MAX   (0x00000001U)
    820. 

  820. 

  821. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA9_MASK  (0x00000200U)
    822. 

  822. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA9_SHIFT  (9U)
    823. 

  823. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA9_RESETVAL  (0x00000000U)
    824. 

  824. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA9_MAX   (0x00000001U)
    825. 

  825. 

  826. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA10_MASK  (0x00000400U)
    827. 

  827. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA10_SHIFT  (10U)
    828. 

  828. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA10_RESETVAL  (0x00000000U)
    829. 

  829. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA10_MAX  (0x00000001U)
    830. 

  830. 

  831. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA11_MASK  (0x00000800U)
    832. 

  832. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA11_SHIFT  (11U)
    833. 

  833. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA11_RESETVAL  (0x00000000U)
    834. 

  834. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA11_MAX  (0x00000001U)
    835. 

  835. 

  836. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA12_MASK  (0x00001000U)
    837. 

  837. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA12_SHIFT  (12U)
    838. 

  838. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA12_RESETVAL  (0x00000000U)
    839. 

  839. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA12_MAX  (0x00000001U)
    840. 

  840. 

  841. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA13_MASK  (0x00002000U)
    842. 

  842. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA13_SHIFT  (13U)
    843. 

  843. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA13_RESETVAL  (0x00000000U)
    844. 

  844. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA13_MAX  (0x00000001U)
    845. 

  845. 

  846. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA14_MASK  (0x00004000U)
    847. 

  847. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA14_SHIFT  (14U)
    848. 

  848. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA14_RESETVAL  (0x00000000U)
    849. 

  849. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA14_MAX  (0x00000001U)
    850. 

  850. 

  851. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA15_MASK  (0x00008000U)
    852. 

  852. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA15_SHIFT  (15U)
    853. 

  853. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA15_RESETVAL  (0x00000000U)
    854. 

  854. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA15_MAX  (0x00000001U)
    855. 

  855. 

  856. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA16_MASK  (0x00010000U)
    857. 

  857. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA16_SHIFT  (16U)
    858. 

  858. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA16_RESETVAL  (0x00000000U)
    859. 

  859. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA16_MAX  (0x00000001U)
    860. 

  860. 

  861. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA17_MASK  (0x00020000U)
    862. 

  862. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA17_SHIFT  (17U)
    863. 

  863. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA17_RESETVAL  (0x00000000U)
    864. 

  864. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA17_MAX  (0x00000001U)
    865. 

  865. 

  866. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA18_MASK  (0x00040000U)
    867. 

  867. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA18_SHIFT  (18U)
    868. 

  868. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA18_RESETVAL  (0x00000000U)
    869. 

  869. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA18_MAX  (0x00000001U)
    870. 

  870. 

  871. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA19_MASK  (0x00080000U)
    872. 

  872. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA19_SHIFT  (19U)
    873. 

  873. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA19_RESETVAL  (0x00000000U)
    874. 

  874. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA19_MAX  (0x00000001U)
    875. 

  875. 

  876. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA20_MASK  (0x00100000U)
    877. 

  877. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA20_SHIFT  (20U)
    878. 

  878. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA20_RESETVAL  (0x00000000U)
    879. 

  879. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA20_MAX  (0x00000001U)
    880. 

  880. 

  881. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA21_MASK  (0x00200000U)
    882. 

  882. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA21_SHIFT  (21U)
    883. 

  883. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA21_RESETVAL  (0x00000000U)
    884. 

  884. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA21_MAX  (0x00000001U)
    885. 

  885. 

  886. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA22_MASK  (0x00400000U)
    887. 

  887. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA22_SHIFT  (22U)
    888. 

  888. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA22_RESETVAL  (0x00000000U)
    889. 

  889. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA22_MAX  (0x00000001U)
    890. 

  890. 

  891. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA23_MASK  (0x00800000U)
    892. 

  892. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA23_SHIFT  (23U)
    893. 

  893. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA23_RESETVAL  (0x00000000U)
    894. 

  894. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA23_MAX  (0x00000001U)
    895. 

  895. 

  896. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA24_MASK  (0x01000000U)
    897. 

  897. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA24_SHIFT  (24U)
    898. 

  898. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA24_RESETVAL  (0x00000000U)
    899. 

  899. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA24_MAX  (0x00000001U)
    900. 

  900. 

  901. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA25_MASK  (0x02000000U)
    902. 

  902. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA25_SHIFT  (25U)
    903. 

  903. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA25_RESETVAL  (0x00000000U)
    904. 

  904. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA25_MAX  (0x00000001U)
    905. 

  905. 

  906. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA26_MASK  (0x04000000U)
    907. 

  907. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA26_SHIFT  (26U)
    908. 

  908. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA26_RESETVAL  (0x00000000U)
    909. 

  909. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA26_MAX  (0x00000001U)
    910. 

  910. 

  911. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA27_MASK  (0x08000000U)
    912. 

  912. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA27_SHIFT  (27U)
    913. 

  913. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA27_RESETVAL  (0x00000000U)
    914. 

  914. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA27_MAX  (0x00000001U)
    915. 

  915. 

  916. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA28_MASK  (0x10000000U)
    917. 

  917. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA28_SHIFT  (28U)
    918. 

  918. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA28_RESETVAL  (0x00000000U)
    919. 

  919. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA28_MAX  (0x00000001U)
    920. 

  920. 

  921. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA29_MASK  (0x20000000U)
    922. 

  922. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA29_SHIFT  (29U)
    923. 

  923. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA29_RESETVAL  (0x00000000U)
    924. 

  924. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA29_MAX  (0x00000001U)
    925. 

  925. 

  926. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA30_MASK  (0x40000000U)
    927. 

  927. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA30_SHIFT  (30U)
    928. 

  928. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA30_RESETVAL  (0x00000000U)
    929. 

  929. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA30_MAX  (0x00000001U)
    930. 

  930. 

  931. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA31_MASK  (0x80000000U)
    932. 

  932. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA31_SHIFT  (31U)
    933. 

  933. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA31_RESETVAL  (0x00000000U)
    934. 

  934. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA31_MAX  (0x00000001U)
    935. 

  935. 

  936. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_RESETVAL      (0x00000000U)
    937. 

  937. 

  938. /* EXTERNAL_INTERRUPT_CLREN_32_63 */
    939. 

  939. 

  940. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA32_MASK  (0x00000001U)
    941. 

  941. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA32_SHIFT  (0U)
    942. 

  942. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA32_RESETVAL  (0x00000000U)
    943. 

  943. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA32_MAX  (0x00000001U)
    944. 

  944. 

  945. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA33_MASK  (0x00000002U)
    946. 

  946. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA33_SHIFT  (1U)
    947. 

  947. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA33_RESETVAL  (0x00000000U)
    948. 

  948. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA33_MAX  (0x00000001U)
    949. 

  949. 

  950. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA34_MASK  (0x00000004U)
    951. 

  951. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA34_SHIFT  (2U)
    952. 

  952. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA34_RESETVAL  (0x00000000U)
    953. 

  953. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA34_MAX  (0x00000001U)
    954. 

  954. 

  955. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA35_MASK  (0x00000008U)
    956. 

  956. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA35_SHIFT  (3U)
    957. 

  957. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA35_RESETVAL  (0x00000000U)
    958. 

  958. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA35_MAX  (0x00000001U)
    959. 

  959. 

  960. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA36_MASK  (0x00000010U)
    961. 

  961. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA36_SHIFT  (4U)
    962. 

  962. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA36_RESETVAL  (0x00000000U)
    963. 

  963. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA36_MAX  (0x00000001U)
    964. 

  964. 

  965. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA37_MASK  (0x00000020U)
    966. 

  966. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA37_SHIFT  (5U)
    967. 

  967. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA37_RESETVAL  (0x00000000U)
    968. 

  968. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA37_MAX  (0x00000001U)
    969. 

  969. 

  970. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA38_MASK  (0x00000040U)
    971. 

  971. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA38_SHIFT  (6U)
    972. 

  972. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA38_RESETVAL  (0x00000000U)
    973. 

  973. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA38_MAX  (0x00000001U)
    974. 

  974. 

  975. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA39_MASK  (0x00000080U)
    976. 

  976. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA39_SHIFT  (7U)
    977. 

  977. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA39_RESETVAL  (0x00000000U)
    978. 

  978. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA39_MAX  (0x00000001U)
    979. 

  979. 

  980. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA40_MASK  (0x00000100U)
    981. 

  981. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA40_SHIFT  (8U)
    982. 

  982. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA40_RESETVAL  (0x00000000U)
    983. 

  983. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA40_MAX  (0x00000001U)
    984. 

  984. 

  985. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA41_MASK  (0x00000200U)
    986. 

  986. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA41_SHIFT  (9U)
    987. 

  987. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA41_RESETVAL  (0x00000000U)
    988. 

  988. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA41_MAX  (0x00000001U)
    989. 

  989. 

  990. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA42_MASK  (0x00000400U)
    991. 

  991. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA42_SHIFT  (10U)
    992. 

  992. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA42_RESETVAL  (0x00000000U)
    993. 

  993. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA42_MAX  (0x00000001U)
    994. 

  994. 

  995. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA43_MASK  (0x00000800U)
    996. 

  996. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA43_SHIFT  (11U)
    997. 

  997. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA43_RESETVAL  (0x00000000U)
    998. 

  998. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA43_MAX  (0x00000001U)
    999. 

  999. 

  1000. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA44_MASK  (0x00001000U)
    1001. 

  1001. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA44_SHIFT  (12U)
    1002. 

  1002. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA44_RESETVAL  (0x00000000U)
    1003. 

  1003. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA44_MAX  (0x00000001U)
    1004. 

  1004. 

  1005. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA45_MASK  (0x00002000U)
    1006. 

  1006. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA45_SHIFT  (13U)
    1007. 

  1007. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA45_RESETVAL  (0x00000000U)
    1008. 

  1008. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA45_MAX  (0x00000001U)
    1009. 

  1009. 

  1010. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA46_MASK  (0x00004000U)
    1011. 

  1011. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA46_SHIFT  (14U)
    1012. 

  1012. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA46_RESETVAL  (0x00000000U)
    1013. 

  1013. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA46_MAX  (0x00000001U)
    1014. 

  1014. 

  1015. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA47_MASK  (0x00008000U)
    1016. 

  1016. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA47_SHIFT  (15U)
    1017. 

  1017. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA47_RESETVAL  (0x00000000U)
    1018. 

  1018. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA47_MAX  (0x00000001U)
    1019. 

  1019. 

  1020. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA48_MASK  (0x00010000U)
    1021. 

  1021. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA48_SHIFT  (16U)
    1022. 

  1022. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA48_RESETVAL  (0x00000000U)
    1023. 

  1023. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA48_MAX  (0x00000001U)
    1024. 

  1024. 

  1025. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA49_MASK  (0x00020000U)
    1026. 

  1026. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA49_SHIFT  (17U)
    1027. 

  1027. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA49_RESETVAL  (0x00000000U)
    1028. 

  1028. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA49_MAX  (0x00000001U)
    1029. 

  1029. 

  1030. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA50_MASK  (0x00040000U)
    1031. 

  1031. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA50_SHIFT  (18U)
    1032. 

  1032. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA50_RESETVAL  (0x00000000U)
    1033. 

  1033. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA50_MAX  (0x00000001U)
    1034. 

  1034. 

  1035. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA51_MASK  (0x00080000U)
    1036. 

  1036. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA51_SHIFT  (19U)
    1037. 

  1037. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA51_RESETVAL  (0x00000000U)
    1038. 

  1038. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA51_MAX  (0x00000001U)
    1039. 

  1039. 

  1040. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA52_MASK  (0x00100000U)
    1041. 

  1041. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA52_SHIFT  (20U)
    1042. 

  1042. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA52_RESETVAL  (0x00000000U)
    1043. 

  1043. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA52_MAX  (0x00000001U)
    1044. 

  1044. 

  1045. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA53_MASK  (0x00200000U)
    1046. 

  1046. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA53_SHIFT  (21U)
    1047. 

  1047. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA53_RESETVAL  (0x00000000U)
    1048. 

  1048. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA53_MAX  (0x00000001U)
    1049. 

  1049. 

  1050. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA54_MASK  (0x00400000U)
    1051. 

  1051. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA54_SHIFT  (22U)
    1052. 

  1052. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA54_RESETVAL  (0x00000000U)
    1053. 

  1053. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA54_MAX  (0x00000001U)
    1054. 

  1054. 

  1055. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA55_MASK  (0x00800000U)
    1056. 

  1056. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA55_SHIFT  (23U)
    1057. 

  1057. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA55_RESETVAL  (0x00000000U)
    1058. 

  1058. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA55_MAX  (0x00000001U)
    1059. 

  1059. 

  1060. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA56_MASK  (0x01000000U)
    1061. 

  1061. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA56_SHIFT  (24U)
    1062. 

  1062. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA56_RESETVAL  (0x00000000U)
    1063. 

  1063. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA56_MAX  (0x00000001U)
    1064. 

  1064. 

  1065. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA57_MASK  (0x02000000U)
    1066. 

  1066. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA57_SHIFT  (25U)
    1067. 

  1067. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA57_RESETVAL  (0x00000000U)
    1068. 

  1068. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA57_MAX  (0x00000001U)
    1069. 

  1069. 

  1070. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA58_MASK  (0x04000000U)
    1071. 

  1071. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA58_SHIFT  (26U)
    1072. 

  1072. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA58_RESETVAL  (0x00000000U)
    1073. 

  1073. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA58_MAX  (0x00000001U)
    1074. 

  1074. 

  1075. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA59_MASK  (0x08000000U)
    1076. 

  1076. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA59_SHIFT  (27U)
    1077. 

  1077. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA59_RESETVAL  (0x00000000U)
    1078. 

  1078. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA59_MAX  (0x00000001U)
    1079. 

  1079. 

  1080. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA60_MASK  (0x10000000U)
    1081. 

  1081. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA60_SHIFT  (28U)
    1082. 

  1082. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA60_RESETVAL  (0x00000000U)
    1083. 

  1083. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA60_MAX  (0x00000001U)
    1084. 

  1084. 

  1085. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA61_MASK  (0x20000000U)
    1086. 

  1086. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA61_SHIFT  (29U)
    1087. 

  1087. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA61_RESETVAL  (0x00000000U)
    1088. 

  1088. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA61_MAX  (0x00000001U)
    1089. 

  1089. 

  1090. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA62_MASK  (0x40000000U)
    1091. 

  1091. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA62_SHIFT  (30U)
    1092. 

  1092. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA62_RESETVAL  (0x00000000U)
    1093. 

  1093. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA62_MAX  (0x00000001U)
    1094. 

  1094. 

  1095. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA63_MASK  (0x80000000U)
    1096. 

  1096. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA63_SHIFT  (31U)
    1097. 

  1097. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA63_RESETVAL  (0x00000000U)
    1098. 

  1098. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA63_MAX  (0x00000001U)
    1099. 

  1099. 

  1100. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_RESETVAL     (0x00000000U)
    1101. 

  1101. 

  1102. /* EXTERNAL_INTERRUPT_CLREN_64_95 */
    1103. 

  1103. 

  1104. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_CLRENA64_MASK  (0x00000001U)
    1105. 

  1105. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_CLRENA64_SHIFT  (0U)
    1106. 

  1106. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_CLRENA64_RESETVAL  (0x00000000U)
    1107. 

  1107. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_CLRENA64_MAX  (0x00000001U)
    1108. 

  1108. 

  1109. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_RESETVAL     (0x00000000U)
    1110. 

  1110. 

  1111. /* EXTERNAL_INTERRUPT_SETPEND_0_31 */
    1112. 

  1112. 

  1113. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND0_MASK  (0x00000001U)
    1114. 

  1114. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND0_SHIFT  (0U)
    1115. 

  1115. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND0_RESETVAL  (0x00000000U)
    1116. 

  1116. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND0_MAX  (0x00000001U)
    1117. 

  1117. 

  1118. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND1_MASK  (0x00000002U)
    1119. 

  1119. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND1_SHIFT  (1U)
    1120. 

  1120. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND1_RESETVAL  (0x00000000U)
    1121. 

  1121. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND1_MAX  (0x00000001U)
    1122. 

  1122. 

  1123. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND2_MASK  (0x00000004U)
    1124. 

  1124. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND2_SHIFT  (2U)
    1125. 

  1125. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND2_RESETVAL  (0x00000000U)
    1126. 

  1126. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND2_MAX  (0x00000001U)
    1127. 

  1127. 

  1128. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND3_MASK  (0x00000008U)
    1129. 

  1129. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND3_SHIFT  (3U)
    1130. 

  1130. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND3_RESETVAL  (0x00000000U)
    1131. 

  1131. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND3_MAX  (0x00000001U)
    1132. 

  1132. 

  1133. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND4_MASK  (0x00000010U)
    1134. 

  1134. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND4_SHIFT  (4U)
    1135. 

  1135. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND4_RESETVAL  (0x00000000U)
    1136. 

  1136. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND4_MAX  (0x00000001U)
    1137. 

  1137. 

  1138. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND5_MASK  (0x00000020U)
    1139. 

  1139. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND5_SHIFT  (5U)
    1140. 

  1140. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND5_RESETVAL  (0x00000000U)
    1141. 

  1141. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND5_MAX  (0x00000001U)
    1142. 

  1142. 

  1143. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND6_MASK  (0x00000040U)
    1144. 

  1144. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND6_SHIFT  (6U)
    1145. 

  1145. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND6_RESETVAL  (0x00000000U)
    1146. 

  1146. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND6_MAX  (0x00000001U)
    1147. 

  1147. 

  1148. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND7_MASK  (0x00000080U)
    1149. 

  1149. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND7_SHIFT  (7U)
    1150. 

  1150. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND7_RESETVAL  (0x00000000U)
    1151. 

  1151. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND7_MAX  (0x00000001U)
    1152. 

  1152. 

  1153. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND8_MASK  (0x00000100U)
    1154. 

  1154. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND8_SHIFT  (8U)
    1155. 

  1155. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND8_RESETVAL  (0x00000000U)
    1156. 

  1156. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND8_MAX  (0x00000001U)
    1157. 

  1157. 

  1158. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND9_MASK  (0x00000200U)
    1159. 

  1159. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND9_SHIFT  (9U)
    1160. 

  1160. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND9_RESETVAL  (0x00000000U)
    1161. 

  1161. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND9_MAX  (0x00000001U)
    1162. 

  1162. 

  1163. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND10_MASK  (0x00000400U)
    1164. 

  1164. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND10_SHIFT  (10U)
    1165. 

  1165. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND10_RESETVAL  (0x00000000U)
    1166. 

  1166. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND10_MAX  (0x00000001U)
    1167. 

  1167. 

  1168. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND11_MASK  (0x00000800U)
    1169. 

  1169. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND11_SHIFT  (11U)
    1170. 

  1170. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND11_RESETVAL  (0x00000000U)
    1171. 

  1171. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND11_MAX  (0x00000001U)
    1172. 

  1172. 

  1173. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND12_MASK  (0x00001000U)
    1174. 

  1174. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND12_SHIFT  (12U)
    1175. 

  1175. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND12_RESETVAL  (0x00000000U)
    1176. 

  1176. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND12_MAX  (0x00000001U)
    1177. 

  1177. 

  1178. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND13_MASK  (0x00002000U)
    1179. 

  1179. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND13_SHIFT  (13U)
    1180. 

  1180. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND13_RESETVAL  (0x00000000U)
    1181. 

  1181. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND13_MAX  (0x00000001U)
    1182. 

  1182. 

  1183. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND14_MASK  (0x00004000U)
    1184. 

  1184. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND14_SHIFT  (14U)
    1185. 

  1185. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND14_RESETVAL  (0x00000000U)
    1186. 

  1186. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND14_MAX  (0x00000001U)
    1187. 

  1187. 

  1188. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND15_MASK  (0x00008000U)
    1189. 

  1189. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND15_SHIFT  (15U)
    1190. 

  1190. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND15_RESETVAL  (0x00000000U)
    1191. 

  1191. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND15_MAX  (0x00000001U)
    1192. 

  1192. 

  1193. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND16_MASK  (0x00010000U)
    1194. 

  1194. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND16_SHIFT  (16U)
    1195. 

  1195. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND16_RESETVAL  (0x00000000U)
    1196. 

  1196. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND16_MAX  (0x00000001U)
    1197. 

  1197. 

  1198. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND17_MASK  (0x00020000U)
    1199. 

  1199. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND17_SHIFT  (17U)
    1200. 

  1200. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND17_RESETVAL  (0x00000000U)
    1201. 

  1201. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND17_MAX  (0x00000001U)
    1202. 

  1202. 

  1203. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND18_MASK  (0x00040000U)
    1204. 

  1204. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND18_SHIFT  (18U)
    1205. 

  1205. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND18_RESETVAL  (0x00000000U)
    1206. 

  1206. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND18_MAX  (0x00000001U)
    1207. 

  1207. 

  1208. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND19_MASK  (0x00080000U)
    1209. 

  1209. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND19_SHIFT  (19U)
    1210. 

  1210. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND19_RESETVAL  (0x00000000U)
    1211. 

  1211. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND19_MAX  (0x00000001U)
    1212. 

  1212. 

  1213. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND20_MASK  (0x00100000U)
    1214. 

  1214. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND20_SHIFT  (20U)
    1215. 

  1215. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND20_RESETVAL  (0x00000000U)
    1216. 

  1216. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND20_MAX  (0x00000001U)
    1217. 

  1217. 

  1218. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND21_MASK  (0x00200000U)
    1219. 

  1219. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND21_SHIFT  (21U)
    1220. 

  1220. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND21_RESETVAL  (0x00000000U)
    1221. 

  1221. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND21_MAX  (0x00000001U)
    1222. 

  1222. 

  1223. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND22_MASK  (0x00400000U)
    1224. 

  1224. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND22_SHIFT  (22U)
    1225. 

  1225. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND22_RESETVAL  (0x00000000U)
    1226. 

  1226. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND22_MAX  (0x00000001U)
    1227. 

  1227. 

  1228. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND23_MASK  (0x00800000U)
    1229. 

  1229. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND23_SHIFT  (23U)
    1230. 

  1230. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND23_RESETVAL  (0x00000000U)
    1231. 

  1231. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND23_MAX  (0x00000001U)
    1232. 

  1232. 

  1233. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND24_MASK  (0x01000000U)
    1234. 

  1234. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND24_SHIFT  (24U)
    1235. 

  1235. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND24_RESETVAL  (0x00000000U)
    1236. 

  1236. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND24_MAX  (0x00000001U)
    1237. 

  1237. 

  1238. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND25_MASK  (0x02000000U)
    1239. 

  1239. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND25_SHIFT  (25U)
    1240. 

  1240. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND25_RESETVAL  (0x00000000U)
    1241. 

  1241. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND25_MAX  (0x00000001U)
    1242. 

  1242. 

  1243. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND26_MASK  (0x04000000U)
    1244. 

  1244. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND26_SHIFT  (26U)
    1245. 

  1245. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND26_RESETVAL  (0x00000000U)
    1246. 

  1246. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND26_MAX  (0x00000001U)
    1247. 

  1247. 

  1248. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND27_MASK  (0x08000000U)
    1249. 

  1249. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND27_SHIFT  (27U)
    1250. 

  1250. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND27_RESETVAL  (0x00000000U)
    1251. 

  1251. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND27_MAX  (0x00000001U)
    1252. 

  1252. 

  1253. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND28_MASK  (0x10000000U)
    1254. 

  1254. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND28_SHIFT  (28U)
    1255. 

  1255. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND28_RESETVAL  (0x00000000U)
    1256. 

  1256. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND28_MAX  (0x00000001U)
    1257. 

  1257. 

  1258. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND29_MASK  (0x20000000U)
    1259. 

  1259. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND29_SHIFT  (29U)
    1260. 

  1260. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND29_RESETVAL  (0x00000000U)
    1261. 

  1261. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND29_MAX  (0x00000001U)
    1262. 

  1262. 

  1263. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND30_MASK  (0x40000000U)
    1264. 

  1264. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND30_SHIFT  (30U)
    1265. 

  1265. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND30_RESETVAL  (0x00000000U)
    1266. 

  1266. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND30_MAX  (0x00000001U)
    1267. 

  1267. 

  1268. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND31_MASK  (0x80000000U)
    1269. 

  1269. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND31_SHIFT  (31U)
    1270. 

  1270. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND31_RESETVAL  (0x00000000U)
    1271. 

  1271. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND31_MAX  (0x00000001U)
    1272. 

  1272. 

  1273. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_RESETVAL    (0x00000000U)
    1274. 

  1274. 

  1275. /* EXTERNAL_INTERRUPT_SETPEND_32_63 */
    1276. 

  1276. 

  1277. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND32_MASK  (0x00000001U)
    1278. 

  1278. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND32_SHIFT  (0U)
    1279. 

  1279. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND32_RESETVAL  (0x00000000U)
    1280. 

  1280. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND32_MAX  (0x00000001U)
    1281. 

  1281. 

  1282. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND33_MASK  (0x00000002U)
    1283. 

  1283. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND33_SHIFT  (1U)
    1284. 

  1284. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND33_RESETVAL  (0x00000000U)
    1285. 

  1285. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND33_MAX  (0x00000001U)
    1286. 

  1286. 

  1287. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND34_MASK  (0x00000004U)
    1288. 

  1288. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND34_SHIFT  (2U)
    1289. 

  1289. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND34_RESETVAL  (0x00000000U)
    1290. 

  1290. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND34_MAX  (0x00000001U)
    1291. 

  1291. 

  1292. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND35_MASK  (0x00000008U)
    1293. 

  1293. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND35_SHIFT  (3U)
    1294. 

  1294. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND35_RESETVAL  (0x00000000U)
    1295. 

  1295. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND35_MAX  (0x00000001U)
    1296. 

  1296. 

  1297. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND36_MASK  (0x00000010U)
    1298. 

  1298. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND36_SHIFT  (4U)
    1299. 

  1299. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND36_RESETVAL  (0x00000000U)
    1300. 

  1300. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND36_MAX  (0x00000001U)
    1301. 

  1301. 

  1302. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND37_MASK  (0x00000020U)
    1303. 

  1303. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND37_SHIFT  (5U)
    1304. 

  1304. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND37_RESETVAL  (0x00000000U)
    1305. 

  1305. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND37_MAX  (0x00000001U)
    1306. 

  1306. 

  1307. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND38_MASK  (0x00000040U)
    1308. 

  1308. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND38_SHIFT  (6U)
    1309. 

  1309. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND38_RESETVAL  (0x00000000U)
    1310. 

  1310. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND38_MAX  (0x00000001U)
    1311. 

  1311. 

  1312. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND39_MASK  (0x00000080U)
    1313. 

  1313. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND39_SHIFT  (7U)
    1314. 

  1314. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND39_RESETVAL  (0x00000000U)
    1315. 

  1315. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND39_MAX  (0x00000001U)
    1316. 

  1316. 

  1317. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND40_MASK  (0x00000100U)
    1318. 

  1318. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND40_SHIFT  (8U)
    1319. 

  1319. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND40_RESETVAL  (0x00000000U)
    1320. 

  1320. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND40_MAX  (0x00000001U)
    1321. 

  1321. 

  1322. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND41_MASK  (0x00000200U)
    1323. 

  1323. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND41_SHIFT  (9U)
    1324. 

  1324. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND41_RESETVAL  (0x00000000U)
    1325. 

  1325. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND41_MAX  (0x00000001U)
    1326. 

  1326. 

  1327. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND42_MASK  (0x00000400U)
    1328. 

  1328. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND42_SHIFT  (10U)
    1329. 

  1329. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND42_RESETVAL  (0x00000000U)
    1330. 

  1330. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND42_MAX  (0x00000001U)
    1331. 

  1331. 

  1332. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND43_MASK  (0x00000800U)
    1333. 

  1333. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND43_SHIFT  (11U)
    1334. 

  1334. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND43_RESETVAL  (0x00000000U)
    1335. 

  1335. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND43_MAX  (0x00000001U)
    1336. 

  1336. 

  1337. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND44_MASK  (0x00001000U)
    1338. 

  1338. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND44_SHIFT  (12U)
    1339. 

  1339. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND44_RESETVAL  (0x00000000U)
    1340. 

  1340. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND44_MAX  (0x00000001U)
    1341. 

  1341. 

  1342. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND45_MASK  (0x00002000U)
    1343. 

  1343. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND45_SHIFT  (13U)
    1344. 

  1344. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND45_RESETVAL  (0x00000000U)
    1345. 

  1345. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND45_MAX  (0x00000001U)
    1346. 

  1346. 

  1347. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND46_MASK  (0x00004000U)
    1348. 

  1348. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND46_SHIFT  (14U)
    1349. 

  1349. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND46_RESETVAL  (0x00000000U)
    1350. 

  1350. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND46_MAX  (0x00000001U)
    1351. 

  1351. 

  1352. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND47_MASK  (0x00008000U)
    1353. 

  1353. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND47_SHIFT  (15U)
    1354. 

  1354. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND47_RESETVAL  (0x00000000U)
    1355. 

  1355. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND47_MAX  (0x00000001U)
    1356. 

  1356. 

  1357. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND48_MASK  (0x00010000U)
    1358. 

  1358. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND48_SHIFT  (16U)
    1359. 

  1359. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND48_RESETVAL  (0x00000000U)
    1360. 

  1360. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND48_MAX  (0x00000001U)
    1361. 

  1361. 

  1362. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND49_MASK  (0x00020000U)
    1363. 

  1363. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND49_SHIFT  (17U)
    1364. 

  1364. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND49_RESETVAL  (0x00000000U)
    1365. 

  1365. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND49_MAX  (0x00000001U)
    1366. 

  1366. 

  1367. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND50_MASK  (0x00040000U)
    1368. 

  1368. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND50_SHIFT  (18U)
    1369. 

  1369. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND50_RESETVAL  (0x00000000U)
    1370. 

  1370. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND50_MAX  (0x00000001U)
    1371. 

  1371. 

  1372. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND51_MASK  (0x00080000U)
    1373. 

  1373. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND51_SHIFT  (19U)
    1374. 

  1374. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND51_RESETVAL  (0x00000000U)
    1375. 

  1375. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND51_MAX  (0x00000001U)
    1376. 

  1376. 

  1377. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND52_MASK  (0x00100000U)
    1378. 

  1378. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND52_SHIFT  (20U)
    1379. 

  1379. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND52_RESETVAL  (0x00000000U)
    1380. 

  1380. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND52_MAX  (0x00000001U)
    1381. 

  1381. 

  1382. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND53_MASK  (0x00200000U)
    1383. 

  1383. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND53_SHIFT  (21U)
    1384. 

  1384. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND53_RESETVAL  (0x00000000U)
    1385. 

  1385. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND53_MAX  (0x00000001U)
    1386. 

  1386. 

  1387. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND54_MASK  (0x00400000U)
    1388. 

  1388. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND54_SHIFT  (22U)
    1389. 

  1389. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND54_RESETVAL  (0x00000000U)
    1390. 

  1390. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND54_MAX  (0x00000001U)
    1391. 

  1391. 

  1392. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND55_MASK  (0x00800000U)
    1393. 

  1393. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND55_SHIFT  (23U)
    1394. 

  1394. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND55_RESETVAL  (0x00000000U)
    1395. 

  1395. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND55_MAX  (0x00000001U)
    1396. 

  1396. 

  1397. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND56_MASK  (0x01000000U)
    1398. 

  1398. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND56_SHIFT  (24U)
    1399. 

  1399. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND56_RESETVAL  (0x00000000U)
    1400. 

  1400. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND56_MAX  (0x00000001U)
    1401. 

  1401. 

  1402. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND57_MASK  (0x02000000U)
    1403. 

  1403. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND57_SHIFT  (25U)
    1404. 

  1404. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND57_RESETVAL  (0x00000000U)
    1405. 

  1405. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND57_MAX  (0x00000001U)
    1406. 

  1406. 

  1407. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND58_MASK  (0x04000000U)
    1408. 

  1408. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND58_SHIFT  (26U)
    1409. 

  1409. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND58_RESETVAL  (0x00000000U)
    1410. 

  1410. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND58_MAX  (0x00000001U)
    1411. 

  1411. 

  1412. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND59_MASK  (0x08000000U)
    1413. 

  1413. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND59_SHIFT  (27U)
    1414. 

  1414. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND59_RESETVAL  (0x00000000U)
    1415. 

  1415. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND59_MAX  (0x00000001U)
    1416. 

  1416. 

  1417. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND60_MASK  (0x10000000U)
    1418. 

  1418. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND60_SHIFT  (28U)
    1419. 

  1419. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND60_RESETVAL  (0x00000000U)
    1420. 

  1420. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND60_MAX  (0x00000001U)
    1421. 

  1421. 

  1422. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND61_MASK  (0x20000000U)
    1423. 

  1423. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND61_SHIFT  (29U)
    1424. 

  1424. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND61_RESETVAL  (0x00000000U)
    1425. 

  1425. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND61_MAX  (0x00000001U)
    1426. 

  1426. 

  1427. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND62_MASK  (0x40000000U)
    1428. 

  1428. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND62_SHIFT  (30U)
    1429. 

  1429. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND62_RESETVAL  (0x00000000U)
    1430. 

  1430. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND62_MAX  (0x00000001U)
    1431. 

  1431. 

  1432. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND63_MASK  (0x80000000U)
    1433. 

  1433. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND63_SHIFT  (31U)
    1434. 

  1434. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND63_RESETVAL  (0x00000000U)
    1435. 

  1435. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND63_MAX  (0x00000001U)
    1436. 

  1436. 

  1437. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_RESETVAL   (0x00000000U)
    1438. 

  1438. 

  1439. /* EXTERNAL_INTERRUPT_SETPEND_64_95 */
    1440. 

  1440. 

  1441. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_SETPEND64_MASK  (0x00000001U)
    1442. 

  1442. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_SETPEND64_SHIFT  (0U)
    1443. 

  1443. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_SETPEND64_RESETVAL  (0x00000000U)
    1444. 

  1444. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_SETPEND64_MAX  (0x00000001U)
    1445. 

  1445. 

  1446. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_RESETVAL   (0x00000000U)
    1447. 

  1447. 

  1448. /* EXTERNAL_INTERRUPT_CLRPEND_0_31 */
    1449. 

  1449. 

  1450. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND0_MASK  (0x00000001U)
    1451. 

  1451. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND0_SHIFT  (0U)
    1452. 

  1452. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND0_RESETVAL  (0x00000000U)
    1453. 

  1453. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND0_MAX  (0x00000001U)
    1454. 

  1454. 

  1455. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND1_MASK  (0x00000002U)
    1456. 

  1456. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND1_SHIFT  (1U)
    1457. 

  1457. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND1_RESETVAL  (0x00000000U)
    1458. 

  1458. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND1_MAX  (0x00000001U)
    1459. 

  1459. 

  1460. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND2_MASK  (0x00000004U)
    1461. 

  1461. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND2_SHIFT  (2U)
    1462. 

  1462. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND2_RESETVAL  (0x00000000U)
    1463. 

  1463. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND2_MAX  (0x00000001U)
    1464. 

  1464. 

  1465. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND3_MASK  (0x00000008U)
    1466. 

  1466. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND3_SHIFT  (3U)
    1467. 

  1467. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND3_RESETVAL  (0x00000000U)
    1468. 

  1468. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND3_MAX  (0x00000001U)
    1469. 

  1469. 

  1470. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND4_MASK  (0x00000010U)
    1471. 

  1471. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND4_SHIFT  (4U)
    1472. 

  1472. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND4_RESETVAL  (0x00000000U)
    1473. 

  1473. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND4_MAX  (0x00000001U)
    1474. 

  1474. 

  1475. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND5_MASK  (0x00000020U)
    1476. 

  1476. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND5_SHIFT  (5U)
    1477. 

  1477. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND5_RESETVAL  (0x00000000U)
    1478. 

  1478. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND5_MAX  (0x00000001U)
    1479. 

  1479. 

  1480. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND6_MASK  (0x00000040U)
    1481. 

  1481. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND6_SHIFT  (6U)
    1482. 

  1482. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND6_RESETVAL  (0x00000000U)
    1483. 

  1483. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND6_MAX  (0x00000001U)
    1484. 

  1484. 

  1485. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND7_MASK  (0x00000080U)
    1486. 

  1486. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND7_SHIFT  (7U)
    1487. 

  1487. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND7_RESETVAL  (0x00000000U)
    1488. 

  1488. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND7_MAX  (0x00000001U)
    1489. 

  1489. 

  1490. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND8_MASK  (0x00000100U)
    1491. 

  1491. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND8_SHIFT  (8U)
    1492. 

  1492. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND8_RESETVAL  (0x00000000U)
    1493. 

  1493. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND8_MAX  (0x00000001U)
    1494. 

  1494. 

  1495. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND9_MASK  (0x00000200U)
    1496. 

  1496. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND9_SHIFT  (9U)
    1497. 

  1497. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND9_RESETVAL  (0x00000000U)
    1498. 

  1498. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND9_MAX  (0x00000001U)
    1499. 

  1499. 

  1500. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND10_MASK  (0x00000400U)
    1501. 

  1501. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND10_SHIFT  (10U)
    1502. 

  1502. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND10_RESETVAL  (0x00000000U)
    1503. 

  1503. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND10_MAX  (0x00000001U)
    1504. 

  1504. 

  1505. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND11_MASK  (0x00000800U)
    1506. 

  1506. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND11_SHIFT  (11U)
    1507. 

  1507. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND11_RESETVAL  (0x00000000U)
    1508. 

  1508. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND11_MAX  (0x00000001U)
    1509. 

  1509. 

  1510. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND12_MASK  (0x00001000U)
    1511. 

  1511. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND12_SHIFT  (12U)
    1512. 

  1512. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND12_RESETVAL  (0x00000000U)
    1513. 

  1513. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND12_MAX  (0x00000001U)
    1514. 

  1514. 

  1515. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND13_MASK  (0x00002000U)
    1516. 

  1516. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND13_SHIFT  (13U)
    1517. 

  1517. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND13_RESETVAL  (0x00000000U)
    1518. 

  1518. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND13_MAX  (0x00000001U)
    1519. 

  1519. 

  1520. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND14_MASK  (0x00004000U)
    1521. 

  1521. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND14_SHIFT  (14U)
    1522. 

  1522. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND14_RESETVAL  (0x00000000U)
    1523. 

  1523. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND14_MAX  (0x00000001U)
    1524. 

  1524. 

  1525. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND15_MASK  (0x00008000U)
    1526. 

  1526. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND15_SHIFT  (15U)
    1527. 

  1527. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND15_RESETVAL  (0x00000000U)
    1528. 

  1528. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND15_MAX  (0x00000001U)
    1529. 

  1529. 

  1530. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND16_MASK  (0x00010000U)
    1531. 

  1531. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND16_SHIFT  (16U)
    1532. 

  1532. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND16_RESETVAL  (0x00000000U)
    1533. 

  1533. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND16_MAX  (0x00000001U)
    1534. 

  1534. 

  1535. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND17_MASK  (0x00020000U)
    1536. 

  1536. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND17_SHIFT  (17U)
    1537. 

  1537. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND17_RESETVAL  (0x00000000U)
    1538. 

  1538. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND17_MAX  (0x00000001U)
    1539. 

  1539. 

  1540. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND18_MASK  (0x00040000U)
    1541. 

  1541. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND18_SHIFT  (18U)
    1542. 

  1542. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND18_RESETVAL  (0x00000000U)
    1543. 

  1543. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND18_MAX  (0x00000001U)
    1544. 

  1544. 

  1545. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND19_MASK  (0x00080000U)
    1546. 

  1546. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND19_SHIFT  (19U)
    1547. 

  1547. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND19_RESETVAL  (0x00000000U)
    1548. 

  1548. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND19_MAX  (0x00000001U)
    1549. 

  1549. 

  1550. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND20_MASK  (0x00100000U)
    1551. 

  1551. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND20_SHIFT  (20U)
    1552. 

  1552. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND20_RESETVAL  (0x00000000U)
    1553. 

  1553. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND20_MAX  (0x00000001U)
    1554. 

  1554. 

  1555. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND21_MASK  (0x00200000U)
    1556. 

  1556. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND21_SHIFT  (21U)
    1557. 

  1557. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND21_RESETVAL  (0x00000000U)
    1558. 

  1558. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND21_MAX  (0x00000001U)
    1559. 

  1559. 

  1560. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND22_MASK  (0x00400000U)
    1561. 

  1561. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND22_SHIFT  (22U)
    1562. 

  1562. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND22_RESETVAL  (0x00000000U)
    1563. 

  1563. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND22_MAX  (0x00000001U)
    1564. 

  1564. 

  1565. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND23_MASK  (0x00800000U)
    1566. 

  1566. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND23_SHIFT  (23U)
    1567. 

  1567. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND23_RESETVAL  (0x00000000U)
    1568. 

  1568. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND23_MAX  (0x00000001U)
    1569. 

  1569. 

  1570. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND24_MASK  (0x01000000U)
    1571. 

  1571. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND24_SHIFT  (24U)
    1572. 

  1572. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND24_RESETVAL  (0x00000000U)
    1573. 

  1573. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND24_MAX  (0x00000001U)
    1574. 

  1574. 

  1575. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND25_MASK  (0x02000000U)
    1576. 

  1576. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND25_SHIFT  (25U)
    1577. 

  1577. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND25_RESETVAL  (0x00000000U)
    1578. 

  1578. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND25_MAX  (0x00000001U)
    1579. 

  1579. 

  1580. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND26_MASK  (0x04000000U)
    1581. 

  1581. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND26_SHIFT  (26U)
    1582. 

  1582. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND26_RESETVAL  (0x00000000U)
    1583. 

  1583. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND26_MAX  (0x00000001U)
    1584. 

  1584. 

  1585. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND27_MASK  (0x08000000U)
    1586. 

  1586. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND27_SHIFT  (27U)
    1587. 

  1587. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND27_RESETVAL  (0x00000000U)
    1588. 

  1588. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND27_MAX  (0x00000001U)
    1589. 

  1589. 

  1590. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND28_MASK  (0x10000000U)
    1591. 

  1591. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND28_SHIFT  (28U)
    1592. 

  1592. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND28_RESETVAL  (0x00000000U)
    1593. 

  1593. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND28_MAX  (0x00000001U)
    1594. 

  1594. 

  1595. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND29_MASK  (0x20000000U)
    1596. 

  1596. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND29_SHIFT  (29U)
    1597. 

  1597. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND29_RESETVAL  (0x00000000U)
    1598. 

  1598. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND29_MAX  (0x00000001U)
    1599. 

  1599. 

  1600. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND30_MASK  (0x40000000U)
    1601. 

  1601. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND30_SHIFT  (30U)
    1602. 

  1602. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND30_RESETVAL  (0x00000000U)
    1603. 

  1603. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND30_MAX  (0x00000001U)
    1604. 

  1604. 

  1605. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND31_MASK  (0x80000000U)
    1606. 

  1606. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND31_SHIFT  (31U)
    1607. 

  1607. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND31_RESETVAL  (0x00000000U)
    1608. 

  1608. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND31_MAX  (0x00000001U)
    1609. 

  1609. 

  1610. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_RESETVAL    (0x00000000U)
    1611. 

  1611. 

  1612. /* EXTERNAL_INTERRUPT_CLRPEND_32_63 */
    1613. 

  1613. 

  1614. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND32_MASK  (0x00000001U)
    1615. 

  1615. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND32_SHIFT  (0U)
    1616. 

  1616. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND32_RESETVAL  (0x00000000U)
    1617. 

  1617. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND32_MAX  (0x00000001U)
    1618. 

  1618. 

  1619. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND33_MASK  (0x00000002U)
    1620. 

  1620. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND33_SHIFT  (1U)
    1621. 

  1621. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND33_RESETVAL  (0x00000000U)
    1622. 

  1622. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND33_MAX  (0x00000001U)
    1623. 

  1623. 

  1624. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND34_MASK  (0x00000004U)
    1625. 

  1625. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND34_SHIFT  (2U)
    1626. 

  1626. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND34_RESETVAL  (0x00000000U)
    1627. 

  1627. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND34_MAX  (0x00000001U)
    1628. 

  1628. 

  1629. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND35_MASK  (0x00000008U)
    1630. 

  1630. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND35_SHIFT  (3U)
    1631. 

  1631. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND35_RESETVAL  (0x00000000U)
    1632. 

  1632. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND35_MAX  (0x00000001U)
    1633. 

  1633. 

  1634. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND36_MASK  (0x00000010U)
    1635. 

  1635. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND36_SHIFT  (4U)
    1636. 

  1636. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND36_RESETVAL  (0x00000000U)
    1637. 

  1637. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND36_MAX  (0x00000001U)
    1638. 

  1638. 

  1639. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND37_MASK  (0x00000020U)
    1640. 

  1640. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND37_SHIFT  (5U)
    1641. 

  1641. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND37_RESETVAL  (0x00000000U)
    1642. 

  1642. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND37_MAX  (0x00000001U)
    1643. 

  1643. 

  1644. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND38_MASK  (0x00000040U)
    1645. 

  1645. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND38_SHIFT  (6U)
    1646. 

  1646. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND38_RESETVAL  (0x00000000U)
    1647. 

  1647. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND38_MAX  (0x00000001U)
    1648. 

  1648. 

  1649. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND39_MASK  (0x00000080U)
    1650. 

  1650. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND39_SHIFT  (7U)
    1651. 

  1651. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND39_RESETVAL  (0x00000000U)
    1652. 

  1652. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND39_MAX  (0x00000001U)
    1653. 

  1653. 

  1654. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND40_MASK  (0x00000100U)
    1655. 

  1655. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND40_SHIFT  (8U)
    1656. 

  1656. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND40_RESETVAL  (0x00000000U)
    1657. 

  1657. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND40_MAX  (0x00000001U)
    1658. 

  1658. 

  1659. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND41_MASK  (0x00000200U)
    1660. 

  1660. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND41_SHIFT  (9U)
    1661. 

  1661. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND41_RESETVAL  (0x00000000U)
    1662. 

  1662. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND41_MAX  (0x00000001U)
    1663. 

  1663. 

  1664. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND42_MASK  (0x00000400U)
    1665. 

  1665. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND42_SHIFT  (10U)
    1666. 

  1666. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND42_RESETVAL  (0x00000000U)
    1667. 

  1667. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND42_MAX  (0x00000001U)
    1668. 

  1668. 

  1669. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND43_MASK  (0x00000800U)
    1670. 

  1670. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND43_SHIFT  (11U)
    1671. 

  1671. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND43_RESETVAL  (0x00000000U)
    1672. 

  1672. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND43_MAX  (0x00000001U)
    1673. 

  1673. 

  1674. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND44_MASK  (0x00001000U)
    1675. 

  1675. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND44_SHIFT  (12U)
    1676. 

  1676. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND44_RESETVAL  (0x00000000U)
    1677. 

  1677. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND44_MAX  (0x00000001U)
    1678. 

  1678. 

  1679. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND45_MASK  (0x00002000U)
    1680. 

  1680. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND45_SHIFT  (13U)
    1681. 

  1681. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND45_RESETVAL  (0x00000000U)
    1682. 

  1682. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND45_MAX  (0x00000001U)
    1683. 

  1683. 

  1684. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND46_MASK  (0x00004000U)
    1685. 

  1685. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND46_SHIFT  (14U)
    1686. 

  1686. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND46_RESETVAL  (0x00000000U)
    1687. 

  1687. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND46_MAX  (0x00000001U)
    1688. 

  1688. 

  1689. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND47_MASK  (0x00008000U)
    1690. 

  1690. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND47_SHIFT  (15U)
    1691. 

  1691. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND47_RESETVAL  (0x00000000U)
    1692. 

  1692. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND47_MAX  (0x00000001U)
    1693. 

  1693. 

  1694. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND48_MASK  (0x00010000U)
    1695. 

  1695. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND48_SHIFT  (16U)
    1696. 

  1696. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND48_RESETVAL  (0x00000000U)
    1697. 

  1697. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND48_MAX  (0x00000001U)
    1698. 

  1698. 

  1699. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND49_MASK  (0x00020000U)
    1700. 

  1700. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND49_SHIFT  (17U)
    1701. 

  1701. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND49_RESETVAL  (0x00000000U)
    1702. 

  1702. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND49_MAX  (0x00000001U)
    1703. 

  1703. 

  1704. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND50_MASK  (0x00040000U)
    1705. 

  1705. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND50_SHIFT  (18U)
    1706. 

  1706. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND50_RESETVAL  (0x00000000U)
    1707. 

  1707. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND50_MAX  (0x00000001U)
    1708. 

  1708. 

  1709. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND51_MASK  (0x00080000U)
    1710. 

  1710. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND51_SHIFT  (19U)
    1711. 

  1711. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND51_RESETVAL  (0x00000000U)
    1712. 

  1712. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND51_MAX  (0x00000001U)
    1713. 

  1713. 

  1714. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND52_MASK  (0x00100000U)
    1715. 

  1715. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND52_SHIFT  (20U)
    1716. 

  1716. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND52_RESETVAL  (0x00000000U)
    1717. 

  1717. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND52_MAX  (0x00000001U)
    1718. 

  1718. 

  1719. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND53_MASK  (0x00200000U)
    1720. 

  1720. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND53_SHIFT  (21U)
    1721. 

  1721. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND53_RESETVAL  (0x00000000U)
    1722. 

  1722. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND53_MAX  (0x00000001U)
    1723. 

  1723. 

  1724. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND54_MASK  (0x00400000U)
    1725. 

  1725. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND54_SHIFT  (22U)
    1726. 

  1726. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND54_RESETVAL  (0x00000000U)
    1727. 

  1727. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND54_MAX  (0x00000001U)
    1728. 

  1728. 

  1729. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND55_MASK  (0x00800000U)
    1730. 

  1730. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND55_SHIFT  (23U)
    1731. 

  1731. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND55_RESETVAL  (0x00000000U)
    1732. 

  1732. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND55_MAX  (0x00000001U)
    1733. 

  1733. 

  1734. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND56_MASK  (0x01000000U)
    1735. 

  1735. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND56_SHIFT  (24U)
    1736. 

  1736. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND56_RESETVAL  (0x00000000U)
    1737. 

  1737. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND56_MAX  (0x00000001U)
    1738. 

  1738. 

  1739. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND57_MASK  (0x02000000U)
    1740. 

  1740. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND57_SHIFT  (25U)
    1741. 

  1741. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND57_RESETVAL  (0x00000000U)
    1742. 

  1742. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND57_MAX  (0x00000001U)
    1743. 

  1743. 

  1744. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND58_MASK  (0x04000000U)
    1745. 

  1745. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND58_SHIFT  (26U)
    1746. 

  1746. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND58_RESETVAL  (0x00000000U)
    1747. 

  1747. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND58_MAX  (0x00000001U)
    1748. 

  1748. 

  1749. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND59_MASK  (0x08000000U)
    1750. 

  1750. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND59_SHIFT  (27U)
    1751. 

  1751. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND59_RESETVAL  (0x00000000U)
    1752. 

  1752. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND59_MAX  (0x00000001U)
    1753. 

  1753. 

  1754. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND60_MASK  (0x10000000U)
    1755. 

  1755. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND60_SHIFT  (28U)
    1756. 

  1756. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND60_RESETVAL  (0x00000000U)
    1757. 

  1757. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND60_MAX  (0x00000001U)
    1758. 

  1758. 

  1759. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND61_MASK  (0x20000000U)
    1760. 

  1760. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND61_SHIFT  (29U)
    1761. 

  1761. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND61_RESETVAL  (0x00000000U)
    1762. 

  1762. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND61_MAX  (0x00000001U)
    1763. 

  1763. 

  1764. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND62_MASK  (0x40000000U)
    1765. 

  1765. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND62_SHIFT  (30U)
    1766. 

  1766. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND62_RESETVAL  (0x00000000U)
    1767. 

  1767. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND62_MAX  (0x00000001U)
    1768. 

  1768. 

  1769. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND63_MASK  (0x80000000U)
    1770. 

  1770. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND63_SHIFT  (31U)
    1771. 

  1771. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND63_RESETVAL  (0x00000000U)
    1772. 

  1772. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND63_MAX  (0x00000001U)
    1773. 

  1773. 

  1774. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_RESETVAL   (0x00000000U)
    1775. 

  1775. 

  1776. /* EXTERNAL_INTERRUPT_CLRPEND_64_95 */
    1777. 

  1777. 

  1778. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_CLRPEND64_MASK  (0x00000001U)
    1779. 

  1779. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_CLRPEND64_SHIFT  (0U)
    1780. 

  1780. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_CLRPEND64_RESETVAL  (0x00000000U)
    1781. 

  1781. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_CLRPEND64_MAX  (0x00000001U)
    1782. 

  1782. 

  1783. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_RESETVAL   (0x00000000U)
    1784. 

  1784. 

  1785. /* EXTERNAL_INTERRUPT_ACTIVE_0_31 */
    1786. 

  1786. 

  1787. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE0_MASK  (0x00000001U)
    1788. 

  1788. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE0_SHIFT  (0U)
    1789. 

  1789. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE0_RESETVAL  (0x00000000U)
    1790. 

  1790. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE0_MAX  (0x00000001U)
    1791. 

  1791. 

  1792. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE1_MASK  (0x00000002U)
    1793. 

  1793. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE1_SHIFT  (1U)
    1794. 

  1794. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE1_RESETVAL  (0x00000000U)
    1795. 

  1795. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE1_MAX  (0x00000001U)
    1796. 

  1796. 

  1797. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE2_MASK  (0x00000004U)
    1798. 

  1798. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE2_SHIFT  (2U)
    1799. 

  1799. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE2_RESETVAL  (0x00000000U)
    1800. 

  1800. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE2_MAX  (0x00000001U)
    1801. 

  1801. 

  1802. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE3_MASK  (0x00000008U)
    1803. 

  1803. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE3_SHIFT  (3U)
    1804. 

  1804. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE3_RESETVAL  (0x00000000U)
    1805. 

  1805. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE3_MAX  (0x00000001U)
    1806. 

  1806. 

  1807. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE4_MASK  (0x00000010U)
    1808. 

  1808. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE4_SHIFT  (4U)
    1809. 

  1809. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE4_RESETVAL  (0x00000000U)
    1810. 

  1810. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE4_MAX  (0x00000001U)
    1811. 

  1811. 

  1812. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE5_MASK  (0x00000020U)
    1813. 

  1813. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE5_SHIFT  (5U)
    1814. 

  1814. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE5_RESETVAL  (0x00000000U)
    1815. 

  1815. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE5_MAX  (0x00000001U)
    1816. 

  1816. 

  1817. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE6_MASK  (0x00000040U)
    1818. 

  1818. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE6_SHIFT  (6U)
    1819. 

  1819. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE6_RESETVAL  (0x00000000U)
    1820. 

  1820. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE6_MAX  (0x00000001U)
    1821. 

  1821. 

  1822. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE7_MASK  (0x00000080U)
    1823. 

  1823. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE7_SHIFT  (7U)
    1824. 

  1824. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE7_RESETVAL  (0x00000000U)
    1825. 

  1825. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE7_MAX  (0x00000001U)
    1826. 

  1826. 

  1827. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE8_MASK  (0x00000100U)
    1828. 

  1828. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE8_SHIFT  (8U)
    1829. 

  1829. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE8_RESETVAL  (0x00000000U)
    1830. 

  1830. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE8_MAX  (0x00000001U)
    1831. 

  1831. 

  1832. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE9_MASK  (0x00000200U)
    1833. 

  1833. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE9_SHIFT  (9U)
    1834. 

  1834. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE9_RESETVAL  (0x00000000U)
    1835. 

  1835. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE9_MAX  (0x00000001U)
    1836. 

  1836. 

  1837. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE10_MASK  (0x00000400U)
    1838. 

  1838. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE10_SHIFT  (10U)
    1839. 

  1839. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE10_RESETVAL  (0x00000000U)
    1840. 

  1840. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE10_MAX  (0x00000001U)
    1841. 

  1841. 

  1842. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE11_MASK  (0x00000800U)
    1843. 

  1843. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE11_SHIFT  (11U)
    1844. 

  1844. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE11_RESETVAL  (0x00000000U)
    1845. 

  1845. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE11_MAX  (0x00000001U)
    1846. 

  1846. 

  1847. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE12_MASK  (0x00001000U)
    1848. 

  1848. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE12_SHIFT  (12U)
    1849. 

  1849. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE12_RESETVAL  (0x00000000U)
    1850. 

  1850. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE12_MAX  (0x00000001U)
    1851. 

  1851. 

  1852. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE13_MASK  (0x00002000U)
    1853. 

  1853. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE13_SHIFT  (13U)
    1854. 

  1854. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE13_RESETVAL  (0x00000000U)
    1855. 

  1855. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE13_MAX  (0x00000001U)
    1856. 

  1856. 

  1857. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE14_MASK  (0x00004000U)
    1858. 

  1858. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE14_SHIFT  (14U)
    1859. 

  1859. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE14_RESETVAL  (0x00000000U)
    1860. 

  1860. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE14_MAX  (0x00000001U)
    1861. 

  1861. 

  1862. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE15_MASK  (0x00008000U)
    1863. 

  1863. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE15_SHIFT  (15U)
    1864. 

  1864. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE15_RESETVAL  (0x00000000U)
    1865. 

  1865. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE15_MAX  (0x00000001U)
    1866. 

  1866. 

  1867. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE16_MASK  (0x00010000U)
    1868. 

  1868. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE16_SHIFT  (16U)
    1869. 

  1869. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE16_RESETVAL  (0x00000000U)
    1870. 

  1870. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE16_MAX  (0x00000001U)
    1871. 

  1871. 

  1872. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE17_MASK  (0x00020000U)
    1873. 

  1873. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE17_SHIFT  (17U)
    1874. 

  1874. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE17_RESETVAL  (0x00000000U)
    1875. 

  1875. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE17_MAX  (0x00000001U)
    1876. 

  1876. 

  1877. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE18_MASK  (0x00040000U)
    1878. 

  1878. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE18_SHIFT  (18U)
    1879. 

  1879. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE18_RESETVAL  (0x00000000U)
    1880. 

  1880. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE18_MAX  (0x00000001U)
    1881. 

  1881. 

  1882. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE19_MASK  (0x00080000U)
    1883. 

  1883. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE19_SHIFT  (19U)
    1884. 

  1884. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE19_RESETVAL  (0x00000000U)
    1885. 

  1885. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE19_MAX  (0x00000001U)
    1886. 

  1886. 

  1887. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE20_MASK  (0x00100000U)
    1888. 

  1888. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE20_SHIFT  (20U)
    1889. 

  1889. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE20_RESETVAL  (0x00000000U)
    1890. 

  1890. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE20_MAX  (0x00000001U)
    1891. 

  1891. 

  1892. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE21_MASK  (0x00200000U)
    1893. 

  1893. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE21_SHIFT  (21U)
    1894. 

  1894. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE21_RESETVAL  (0x00000000U)
    1895. 

  1895. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE21_MAX  (0x00000001U)
    1896. 

  1896. 

  1897. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE22_MASK  (0x00400000U)
    1898. 

  1898. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE22_SHIFT  (22U)
    1899. 

  1899. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE22_RESETVAL  (0x00000000U)
    1900. 

  1900. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE22_MAX  (0x00000001U)
    1901. 

  1901. 

  1902. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE23_MASK  (0x00800000U)
    1903. 

  1903. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE23_SHIFT  (23U)
    1904. 

  1904. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE23_RESETVAL  (0x00000000U)
    1905. 

  1905. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE23_MAX  (0x00000001U)
    1906. 

  1906. 

  1907. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE24_MASK  (0x01000000U)
    1908. 

  1908. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE24_SHIFT  (24U)
    1909. 

  1909. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE24_RESETVAL  (0x00000000U)
    1910. 

  1910. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE24_MAX  (0x00000001U)
    1911. 

  1911. 

  1912. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE25_MASK  (0x02000000U)
    1913. 

  1913. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE25_SHIFT  (25U)
    1914. 

  1914. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE25_RESETVAL  (0x00000000U)
    1915. 

  1915. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE25_MAX  (0x00000001U)
    1916. 

  1916. 

  1917. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE26_MASK  (0x04000000U)
    1918. 

  1918. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE26_SHIFT  (26U)
    1919. 

  1919. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE26_RESETVAL  (0x00000000U)
    1920. 

  1920. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE26_MAX  (0x00000001U)
    1921. 

  1921. 

  1922. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE27_MASK  (0x08000000U)
    1923. 

  1923. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE27_SHIFT  (27U)
    1924. 

  1924. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE27_RESETVAL  (0x00000000U)
    1925. 

  1925. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE27_MAX  (0x00000001U)
    1926. 

  1926. 

  1927. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE28_MASK  (0x10000000U)
    1928. 

  1928. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE28_SHIFT  (28U)
    1929. 

  1929. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE28_RESETVAL  (0x00000000U)
    1930. 

  1930. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE28_MAX  (0x00000001U)
    1931. 

  1931. 

  1932. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE29_MASK  (0x20000000U)
    1933. 

  1933. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE29_SHIFT  (29U)
    1934. 

  1934. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE29_RESETVAL  (0x00000000U)
    1935. 

  1935. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE29_MAX  (0x00000001U)
    1936. 

  1936. 

  1937. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE30_MASK  (0x40000000U)
    1938. 

  1938. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE30_SHIFT  (30U)
    1939. 

  1939. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE30_RESETVAL  (0x00000000U)
    1940. 

  1940. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE30_MAX  (0x00000001U)
    1941. 

  1941. 

  1942. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE31_MASK  (0x80000000U)
    1943. 

  1943. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE31_SHIFT  (31U)
    1944. 

  1944. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE31_RESETVAL  (0x00000000U)
    1945. 

  1945. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE31_MAX  (0x00000001U)
    1946. 

  1946. 

  1947. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_RESETVAL     (0x00000000U)
    1948. 

  1948. 

  1949. /* EXTERNAL_INTERRUPT_ACTIVE_32_63 */
    1950. 

  1950. 

  1951. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE32_MASK  (0x00000001U)
    1952. 

  1952. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE32_SHIFT  (0U)
    1953. 

  1953. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE32_RESETVAL  (0x00000000U)
    1954. 

  1954. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE32_MAX  (0x00000001U)
    1955. 

  1955. 

  1956. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE33_MASK  (0x00000002U)
    1957. 

  1957. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE33_SHIFT  (1U)
    1958. 

  1958. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE33_RESETVAL  (0x00000000U)
    1959. 

  1959. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE33_MAX  (0x00000001U)
    1960. 

  1960. 

  1961. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE34_MASK  (0x00000004U)
    1962. 

  1962. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE34_SHIFT  (2U)
    1963. 

  1963. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE34_RESETVAL  (0x00000000U)
    1964. 

  1964. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE34_MAX  (0x00000001U)
    1965. 

  1965. 

  1966. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE35_MASK  (0x00000008U)
    1967. 

  1967. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE35_SHIFT  (3U)
    1968. 

  1968. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE35_RESETVAL  (0x00000000U)
    1969. 

  1969. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE35_MAX  (0x00000001U)
    1970. 

  1970. 

  1971. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE36_MASK  (0x00000010U)
    1972. 

  1972. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE36_SHIFT  (4U)
    1973. 

  1973. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE36_RESETVAL  (0x00000000U)
    1974. 

  1974. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE36_MAX  (0x00000001U)
    1975. 

  1975. 

  1976. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE37_MASK  (0x00000020U)
    1977. 

  1977. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE37_SHIFT  (5U)
    1978. 

  1978. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE37_RESETVAL  (0x00000000U)
    1979. 

  1979. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE37_MAX  (0x00000001U)
    1980. 

  1980. 

  1981. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE38_MASK  (0x00000040U)
    1982. 

  1982. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE38_SHIFT  (6U)
    1983. 

  1983. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE38_RESETVAL  (0x00000000U)
    1984. 

  1984. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE38_MAX  (0x00000001U)
    1985. 

  1985. 

  1986. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE39_MASK  (0x00000080U)
    1987. 

  1987. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE39_SHIFT  (7U)
    1988. 

  1988. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE39_RESETVAL  (0x00000000U)
    1989. 

  1989. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE39_MAX  (0x00000001U)
    1990. 

  1990. 

  1991. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE40_MASK  (0x00000100U)
    1992. 

  1992. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE40_SHIFT  (8U)
    1993. 

  1993. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE40_RESETVAL  (0x00000000U)
    1994. 

  1994. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE40_MAX  (0x00000001U)
    1995. 

  1995. 

  1996. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE41_MASK  (0x00000200U)
    1997. 

  1997. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE41_SHIFT  (9U)
    1998. 

  1998. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE41_RESETVAL  (0x00000000U)
    1999. 

  1999. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE41_MAX  (0x00000001U)
    2000. 

  2000. 

  2001. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE42_MASK  (0x00000400U)
    2002. 

  2002. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE42_SHIFT  (10U)
    2003. 

  2003. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE42_RESETVAL  (0x00000000U)
    2004. 

  2004. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE42_MAX  (0x00000001U)
    2005. 

  2005. 

  2006. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE43_MASK  (0x00000800U)
    2007. 

  2007. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE43_SHIFT  (11U)
    2008. 

  2008. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE43_RESETVAL  (0x00000000U)
    2009. 

  2009. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE43_MAX  (0x00000001U)
    2010. 

  2010. 

  2011. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE44_MASK  (0x00001000U)
    2012. 

  2012. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE44_SHIFT  (12U)
    2013. 

  2013. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE44_RESETVAL  (0x00000000U)
    2014. 

  2014. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE44_MAX  (0x00000001U)
    2015. 

  2015. 

  2016. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE45_MASK  (0x00002000U)
    2017. 

  2017. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE45_SHIFT  (13U)
    2018. 

  2018. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE45_RESETVAL  (0x00000000U)
    2019. 

  2019. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE45_MAX  (0x00000001U)
    2020. 

  2020. 

  2021. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE46_MASK  (0x00004000U)
    2022. 

  2022. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE46_SHIFT  (14U)
    2023. 

  2023. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE46_RESETVAL  (0x00000000U)
    2024. 

  2024. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE46_MAX  (0x00000001U)
    2025. 

  2025. 

  2026. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE47_MASK  (0x00008000U)
    2027. 

  2027. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE47_SHIFT  (15U)
    2028. 

  2028. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE47_RESETVAL  (0x00000000U)
    2029. 

  2029. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE47_MAX  (0x00000001U)
    2030. 

  2030. 

  2031. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE48_MASK  (0x00010000U)
    2032. 

  2032. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE48_SHIFT  (16U)
    2033. 

  2033. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE48_RESETVAL  (0x00000000U)
    2034. 

  2034. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE48_MAX  (0x00000001U)
    2035. 

  2035. 

  2036. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE49_MASK  (0x00020000U)
    2037. 

  2037. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE49_SHIFT  (17U)
    2038. 

  2038. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE49_RESETVAL  (0x00000000U)
    2039. 

  2039. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE49_MAX  (0x00000001U)
    2040. 

  2040. 

  2041. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE50_MASK  (0x00040000U)
    2042. 

  2042. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE50_SHIFT  (18U)
    2043. 

  2043. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE50_RESETVAL  (0x00000000U)
    2044. 

  2044. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE50_MAX  (0x00000001U)
    2045. 

  2045. 

  2046. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE51_MASK  (0x00080000U)
    2047. 

  2047. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE51_SHIFT  (19U)
    2048. 

  2048. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE51_RESETVAL  (0x00000000U)
    2049. 

  2049. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE51_MAX  (0x00000001U)
    2050. 

  2050. 

  2051. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE52_MASK  (0x00100000U)
    2052. 

  2052. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE52_SHIFT  (20U)
    2053. 

  2053. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE52_RESETVAL  (0x00000000U)
    2054. 

  2054. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE52_MAX  (0x00000001U)
    2055. 

  2055. 

  2056. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE53_MASK  (0x00200000U)
    2057. 

  2057. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE53_SHIFT  (21U)
    2058. 

  2058. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE53_RESETVAL  (0x00000000U)
    2059. 

  2059. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE53_MAX  (0x00000001U)
    2060. 

  2060. 

  2061. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE54_MASK  (0x00400000U)
    2062. 

  2062. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE54_SHIFT  (22U)
    2063. 

  2063. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE54_RESETVAL  (0x00000000U)
    2064. 

  2064. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE54_MAX  (0x00000001U)
    2065. 

  2065. 

  2066. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE55_MASK  (0x00800000U)
    2067. 

  2067. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE55_SHIFT  (23U)
    2068. 

  2068. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE55_RESETVAL  (0x00000000U)
    2069. 

  2069. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE55_MAX  (0x00000001U)
    2070. 

  2070. 

  2071. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE56_MASK  (0x01000000U)
    2072. 

  2072. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE56_SHIFT  (24U)
    2073. 

  2073. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE56_RESETVAL  (0x00000000U)
    2074. 

  2074. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE56_MAX  (0x00000001U)
    2075. 

  2075. 

  2076. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE57_MASK  (0x02000000U)
    2077. 

  2077. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE57_SHIFT  (25U)
    2078. 

  2078. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE57_RESETVAL  (0x00000000U)
    2079. 

  2079. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE57_MAX  (0x00000001U)
    2080. 

  2080. 

  2081. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE58_MASK  (0x04000000U)
    2082. 

  2082. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE58_SHIFT  (26U)
    2083. 

  2083. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE58_RESETVAL  (0x00000000U)
    2084. 

  2084. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE58_MAX  (0x00000001U)
    2085. 

  2085. 

  2086. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE59_MASK  (0x08000000U)
    2087. 

  2087. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE59_SHIFT  (27U)
    2088. 

  2088. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE59_RESETVAL  (0x00000000U)
    2089. 

  2089. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE59_MAX  (0x00000001U)
    2090. 

  2090. 

  2091. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE60_MASK  (0x10000000U)
    2092. 

  2092. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE60_SHIFT  (28U)
    2093. 

  2093. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE60_RESETVAL  (0x00000000U)
    2094. 

  2094. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE60_MAX  (0x00000001U)
    2095. 

  2095. 

  2096. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE61_MASK  (0x20000000U)
    2097. 

  2097. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE61_SHIFT  (29U)
    2098. 

  2098. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE61_RESETVAL  (0x00000000U)
    2099. 

  2099. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE61_MAX  (0x00000001U)
    2100. 

  2100. 

  2101. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE62_MASK  (0x40000000U)
    2102. 

  2102. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE62_SHIFT  (30U)
    2103. 

  2103. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE62_RESETVAL  (0x00000000U)
    2104. 

  2104. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE62_MAX  (0x00000001U)
    2105. 

  2105. 

  2106. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE63_MASK  (0x80000000U)
    2107. 

  2107. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE63_SHIFT  (31U)
    2108. 

  2108. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE63_RESETVAL  (0x00000000U)
    2109. 

  2109. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE63_MAX  (0x00000001U)
    2110. 

  2110. 

  2111. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_RESETVAL    (0x00000000U)
    2112. 

  2112. 

  2113. /* EXTERNAL_INTERRUPT_ACTIVE_64_95 */
    2114. 

  2114. 

  2115. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_ACTIVE64_MASK  (0x00000001U)
    2116. 

  2116. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_ACTIVE64_SHIFT  (0U)
    2117. 

  2117. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_ACTIVE64_RESETVAL  (0x00000000U)
    2118. 

  2118. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_ACTIVE64_MAX  (0x00000001U)
    2119. 

  2119. 

  2120. #define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_RESETVAL    (0x00000000U)
    2121. 

  2121. 

  2122. /* EXTERNAL_INT_PRIORITY_LEVEL */
    2123. 

  2123. 

  2124. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI0_MASK       (0x000000FFU)
    2125. 

  2125. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI0_SHIFT      (0U)
    2126. 

  2126. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI0_RESETVAL   (0x00000000U)
    2127. 

  2127. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI0_MAX        (0x000000ffU)
    2128. 

  2128. 

  2129. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI1_MASK       (0x0000FF00U)
    2130. 

  2130. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI1_SHIFT      (8U)
    2131. 

  2131. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI1_RESETVAL   (0x00000000U)
    2132. 

  2132. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI1_MAX        (0x000000ffU)
    2133. 

  2133. 

  2134. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI2_MASK       (0x00FF0000U)
    2135. 

  2135. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI2_SHIFT      (16U)
    2136. 

  2136. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI2_RESETVAL   (0x00000000U)
    2137. 

  2137. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI2_MAX        (0x000000ffU)
    2138. 

  2138. 

  2139. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI3_MASK       (0xFF000000U)
    2140. 

  2140. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI3_SHIFT      (24U)
    2141. 

  2141. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI3_RESETVAL   (0x00000000U)
    2142. 

  2142. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI3_MAX        (0x000000ffU)
    2143. 

  2143. 

  2144. #define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_RESETVAL        (0x00000000U)
    2145. 

  2145. 

  2146. /* CPU_ID_BASE_REGISTER */
    2147. 

  2147. 

  2148. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_REVISION_MASK          (0x0000000FU)
    2149. 

  2149. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_REVISION_SHIFT         (0U)
    2150. 

  2150. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_REVISION_RESETVAL      (0x00000000U)
    2151. 

  2151. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_REVISION_MAX           (0x0000000fU)
    2152. 

  2152. 

  2153. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_PARTNO_MASK            (0x0000FFF0U)
    2154. 

  2154. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_PARTNO_SHIFT           (4U)
    2155. 

  2155. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_PARTNO_RESETVAL        (0x00000c23U)
    2156. 

  2156. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_PARTNO_MAX             (0x00000fffU)
    2157. 

  2157. 

  2158. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_CONSTANT_MASK          (0x000F0000U)
    2159. 

  2159. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_CONSTANT_SHIFT         (16U)
    2160. 

  2160. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_CONSTANT_RESETVAL      (0x0000000fU)
    2161. 

  2161. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_CONSTANT_MAX           (0x0000000fU)
    2162. 

  2162. 

  2163. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_VARIANT_MASK           (0x00F00000U)
    2164. 

  2164. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_VARIANT_SHIFT          (20U)
    2165. 

  2165. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_VARIANT_RESETVAL       (0x00000002U)
    2166. 

  2166. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_VARIANT_MAX            (0x0000000fU)
    2167. 

  2167. 

  2168. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_IMPLEMENTER_MASK       (0xFF000000U)
    2169. 

  2169. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_IMPLEMENTER_SHIFT      (24U)
    2170. 

  2170. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_IMPLEMENTER_RESETVAL   (0x00000041U)
    2171. 

  2171. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_IMPLEMENTER_MAX        (0x000000ffU)
    2172. 

  2172. 

  2173. #define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_RESETVAL               (0x412fc230U)
    2174. 

  2174. 

  2175. /* INTERRUPT_CONTROL_AND_STATE */
    2176. 

  2176. 

  2177. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTACTIVE_MASK  (0x000003FFU)
    2178. 

  2178. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTACTIVE_SHIFT  (0U)
    2179. 

  2179. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTACTIVE_RESETVAL  (0x00000000U)
    2180. 

  2180. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTACTIVE_MAX  (0x000003ffU)
    2181. 

  2181. 

  2182. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RETTOBASE_MASK  (0x00000400U)
    2183. 

  2183. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RETTOBASE_SHIFT  (10U)
    2184. 

  2184. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RETTOBASE_RESETVAL  (0x00000000U)
    2185. 

  2185. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RETTOBASE_MAX   (0x00000001U)
    2186. 

  2186. 

  2187. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTPENDING_MASK  (0x003FF800U)
    2188. 

  2188. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTPENDING_SHIFT  (11U)
    2189. 

  2189. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTPENDING_RESETVAL  (0x00000000U)
    2190. 

  2190. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTPENDING_MAX  (0x000007ffU)
    2191. 

  2191. 

  2192. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPENDING_MASK  (0x00400000U)
    2193. 

  2193. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPENDING_SHIFT  (22U)
    2194. 

  2194. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPENDING_RESETVAL  (0x00000000U)
    2195. 

  2195. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPENDING_MAX  (0x00000001U)
    2196. 

  2196. 

  2197. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPREEMPT_MASK  (0x00800000U)
    2198. 

  2198. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPREEMPT_SHIFT  (23U)
    2199. 

  2199. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPREEMPT_RESETVAL  (0x00000000U)
    2200. 

  2200. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPREEMPT_MAX  (0x00000001U)
    2201. 

  2201. 

  2202. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTCLR_MASK  (0x02000000U)
    2203. 

  2203. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTCLR_SHIFT  (25U)
    2204. 

  2204. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTCLR_RESETVAL  (0x00000000U)
    2205. 

  2205. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTCLR_MAX   (0x00000001U)
    2206. 

  2206. 

  2207. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTSET_MASK  (0x04000000U)
    2208. 

  2208. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTSET_SHIFT  (26U)
    2209. 

  2209. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTSET_RESETVAL  (0x00000000U)
    2210. 

  2210. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTSET_MAX   (0x00000001U)
    2211. 

  2211. 

  2212. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVCLR_MASK  (0x08000000U)
    2213. 

  2213. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVCLR_SHIFT  (27U)
    2214. 

  2214. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVCLR_RESETVAL  (0x00000000U)
    2215. 

  2215. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVCLR_MAX   (0x00000001U)
    2216. 

  2216. 

  2217. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVSET_MASK  (0x10000000U)
    2218. 

  2218. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVSET_SHIFT  (28U)
    2219. 

  2219. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVSET_RESETVAL  (0x00000000U)
    2220. 

  2220. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVSET_MAX   (0x00000001U)
    2221. 

  2221. 

  2222. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_NMIPENDSET_MASK  (0x80000000U)
    2223. 

  2223. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_NMIPENDSET_SHIFT  (31U)
    2224. 

  2224. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_NMIPENDSET_RESETVAL  (0x00000000U)
    2225. 

  2225. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_NMIPENDSET_MAX  (0x00000001U)
    2226. 

  2226. 

  2227. #define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RESETVAL        (0x00000000U)
    2228. 

  2228. 

  2229. /* VECTOR_TABLE_OFFSET */
    2230. 

  2230. 

  2231. #define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_TBLOFF_MASK             (0xFFFFFF80U)
    2232. 

  2232. #define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_TBLOFF_SHIFT            (7U)
    2233. 

  2233. #define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_TBLOFF_RESETVAL         (0x00000000U)
    2234. 

  2234. #define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_TBLOFF_MAX              (0x01ffffffU)
    2235. 

  2235. 

  2236. #define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_RESETVAL                (0x00000000U)
    2237. 

  2237. 

  2238. /* APPLICATION_INT_AND_RESET_CONTROL */
    2239. 

  2239. 

  2240. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTRESET_MASK  (0x00000001U)
    2241. 

  2241. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTRESET_SHIFT  (0U)
    2242. 

  2242. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTRESET_RESETVAL  (0x00000000U)
    2243. 

  2243. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTRESET_MAX  (0x00000001U)
    2244. 

  2244. 

  2245. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTCLRACTIVE_MASK  (0x00000002U)
    2246. 

  2246. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTCLRACTIVE_SHIFT  (1U)
    2247. 

  2247. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTCLRACTIVE_RESETVAL  (0x00000000U)
    2248. 

  2248. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTCLRACTIVE_MAX  (0x00000001U)
    2249. 

  2249. 

  2250. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_SYSRESETREQ_MASK  (0x00000004U)
    2251. 

  2251. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_SYSRESETREQ_SHIFT  (2U)
    2252. 

  2252. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_SYSRESETREQ_RESETVAL  (0x00000000U)
    2253. 

  2253. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_SYSRESETREQ_MAX  (0x00000001U)
    2254. 

  2254. 

  2255. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_PRIGROUP_MASK  (0x00000700U)
    2256. 

  2256. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_PRIGROUP_SHIFT  (8U)
    2257. 

  2257. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_PRIGROUP_RESETVAL  (0x00000000U)
    2258. 

  2258. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_PRIGROUP_MAX  (0x00000007U)
    2259. 

  2259. 

  2260. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_ENDIANESS_MASK  (0x00008000U)
    2261. 

  2261. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_ENDIANESS_SHIFT  (15U)
    2262. 

  2262. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_ENDIANESS_RESETVAL  (0x00000000U)
    2263. 

  2263. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_ENDIANESS_MAX  (0x00000001U)
    2264. 

  2264. 

  2265. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTKEY_MASK  (0xFFFF0000U)
    2266. 

  2266. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTKEY_SHIFT  (16U)
    2267. 

  2267. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTKEY_RESETVAL  (0x00000000U)
    2268. 

  2268. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTKEY_MAX  (0x0000ffffU)
    2269. 

  2269. 

  2270. #define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_RESETVAL  (0x00000000U)
    2271. 

  2271. 

  2272. /* SYSTEM_CONTROL */
    2273. 

  2273. 

  2274. #define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPONEXIT_MASK             (0x00000002U)
    2275. 

  2275. #define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPONEXIT_SHIFT            (1U)
    2276. 

  2276. #define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPONEXIT_RESETVAL         (0x00000000U)
    2277. 

  2277. #define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPONEXIT_MAX              (0x00000001U)
    2278. 

  2278. 

  2279. #define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPDEEP_MASK               (0x00000004U)
    2280. 

  2280. #define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPDEEP_SHIFT              (2U)
    2281. 

  2281. #define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPDEEP_RESETVAL           (0x00000000U)
    2282. 

  2282. #define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPDEEP_MAX                (0x00000001U)
    2283. 

  2283. 

  2284. #define CSL_CM3NVIC_SYSTEM_CONTROL_SEVONPEND_MASK               (0x00000010U)
    2285. 

  2285. #define CSL_CM3NVIC_SYSTEM_CONTROL_SEVONPEND_SHIFT              (4U)
    2286. 

  2286. #define CSL_CM3NVIC_SYSTEM_CONTROL_SEVONPEND_RESETVAL           (0x00000000U)
    2287. 

  2287. #define CSL_CM3NVIC_SYSTEM_CONTROL_SEVONPEND_MAX                (0x00000001U)
    2288. 

  2288. 

  2289. #define CSL_CM3NVIC_SYSTEM_CONTROL_RESETVAL                     (0x00000000U)
    2290. 

  2290. 

  2291. /* CONFIGURATION_CONTROL */
    2292. 

  2292. 

  2293. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_NONBASETHRDENA_MASK   (0x00000001U)
    2294. 

  2294. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_NONBASETHRDENA_SHIFT  (0U)
    2295. 

  2295. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_NONBASETHRDENA_RESETVAL  (0x00000000U)
    2296. 

  2296. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_NONBASETHRDENA_MAX    (0x00000001U)
    2297. 

  2297. 

  2298. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_USERSETMPEND_MASK     (0x00000002U)
    2299. 

  2299. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_USERSETMPEND_SHIFT    (1U)
    2300. 

  2300. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_USERSETMPEND_RESETVAL  (0x00000000U)
    2301. 

  2301. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_USERSETMPEND_MAX      (0x00000001U)
    2302. 

  2302. 

  2303. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_UNALIGN_TRP_MASK      (0x00000008U)
    2304. 

  2304. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_UNALIGN_TRP_SHIFT     (3U)
    2305. 

  2305. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_UNALIGN_TRP_RESETVAL  (0x00000000U)
    2306. 

  2306. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_UNALIGN_TRP_MAX       (0x00000001U)
    2307. 

  2307. 

  2308. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_DIV_0_TRP_MASK        (0x00000010U)
    2309. 

  2309. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_DIV_0_TRP_SHIFT       (4U)
    2310. 

  2310. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_DIV_0_TRP_RESETVAL    (0x00000000U)
    2311. 

  2311. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_DIV_0_TRP_MAX         (0x00000001U)
    2312. 

  2312. 

  2313. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_BFHFNMIGN_MASK        (0x00000100U)
    2314. 

  2314. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_BFHFNMIGN_SHIFT       (8U)
    2315. 

  2315. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_BFHFNMIGN_RESETVAL    (0x00000000U)
    2316. 

  2316. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_BFHFNMIGN_MAX         (0x00000001U)
    2317. 

  2317. 

  2318. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_STKALIGN_MASK         (0x00000200U)
    2319. 

  2319. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_STKALIGN_SHIFT        (9U)
    2320. 

  2320. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_STKALIGN_RESETVAL     (0x00000000U)
    2321. 

  2321. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_STKALIGN_MAX          (0x00000001U)
    2322. 

  2322. 

  2323. #define CSL_CM3NVIC_CONFIGURATION_CONTROL_RESETVAL              (0x00000000U)
    2324. 

  2324. 

  2325. /* SYSTEM_EXCEPTION_PRIORITY_LEVEL */
    2326. 

  2326. 

  2327. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N_MASK  (0x000000FFU)
    2328. 

  2328. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N_SHIFT  (0U)
    2329. 

  2329. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N_RESETVAL  (0x00000000U)
    2330. 

  2330. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N_MAX   (0x000000ffU)
    2331. 

  2331. 

  2332. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N1_MASK  (0x0000FF00U)
    2333. 

  2333. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N1_SHIFT  (8U)
    2334. 

  2334. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N1_RESETVAL  (0x00000000U)
    2335. 

  2335. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N1_MAX  (0x000000ffU)
    2336. 

  2336. 

  2337. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N2_MASK  (0x00FF0000U)
    2338. 

  2338. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N2_SHIFT  (16U)
    2339. 

  2339. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N2_RESETVAL  (0x00000000U)
    2340. 

  2340. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N2_MAX  (0x000000ffU)
    2341. 

  2341. 

  2342. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N3_MASK  (0xFF000000U)
    2343. 

  2343. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N3_SHIFT  (24U)
    2344. 

  2344. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N3_RESETVAL  (0x00000000U)
    2345. 

  2345. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N3_MAX  (0x000000ffU)
    2346. 

  2346. 

  2347. #define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_RESETVAL    (0x00000000U)
    2348. 

  2348. 

  2349. /* SYSTEM_HANDLER_CONTROL_AND_STATE */
    2350. 

  2350. 

  2351. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTACT_MASK  (0x00000001U)
    2352. 

  2352. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTACT_SHIFT  (0U)
    2353. 

  2353. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTACT_RESETVAL  (0x00000000U)
    2354. 

  2354. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTACT_MAX  (0x00000001U)
    2355. 

  2355. 

  2356. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTACT_MASK  (0x00000002U)
    2357. 

  2357. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTACT_SHIFT  (1U)
    2358. 

  2358. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTACT_RESETVAL  (0x00000000U)
    2359. 

  2359. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTACT_MAX  (0x00000001U)
    2360. 

  2360. 

  2361. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTACT_MASK  (0x00000008U)
    2362. 

  2362. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTACT_SHIFT  (3U)
    2363. 

  2363. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTACT_RESETVAL  (0x00000000U)
    2364. 

  2364. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTACT_MAX  (0x00000001U)
    2365. 

  2365. 

  2366. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCFAULTACT_MASK  (0x00000080U)
    2367. 

  2367. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCFAULTACT_SHIFT  (7U)
    2368. 

  2368. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCFAULTACT_RESETVAL  (0x00000000U)
    2369. 

  2369. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCFAULTACT_MAX  (0x00000001U)
    2370. 

  2370. 

  2371. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MONITORACT_MASK  (0x00000100U)
    2372. 

  2372. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MONITORACT_SHIFT  (8U)
    2373. 

  2373. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MONITORACT_RESETVAL  (0x00000000U)
    2374. 

  2374. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MONITORACT_MAX  (0x00000001U)
    2375. 

  2375. 

  2376. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_PENDSVACT_MASK  (0x00000400U)
    2377. 

  2377. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_PENDSVACT_SHIFT  (10U)
    2378. 

  2378. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_PENDSVACT_RESETVAL  (0x00000000U)
    2379. 

  2379. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_PENDSVACT_MAX  (0x00000001U)
    2380. 

  2380. 

  2381. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SYSICKACT_MASK  (0x00000800U)
    2382. 

  2382. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SYSICKACT_SHIFT  (11U)
    2383. 

  2383. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SYSICKACT_RESETVAL  (0x00000000U)
    2384. 

  2384. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SYSICKACT_MAX  (0x00000001U)
    2385. 

  2385. 

  2386. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTPENDED_MASK  (0x00001000U)
    2387. 

  2387. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTPENDED_SHIFT  (12U)
    2388. 

  2388. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTPENDED_RESETVAL  (0x00000000U)
    2389. 

  2389. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTPENDED_MAX  (0x00000001U)
    2390. 

  2390. 

  2391. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTPENDED_MASK  (0x00002000U)
    2392. 

  2392. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTPENDED_SHIFT  (13U)
    2393. 

  2393. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTPENDED_RESETVAL  (0x00000000U)
    2394. 

  2394. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTPENDED_MAX  (0x00000001U)
    2395. 

  2395. 

  2396. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTPENDED_MASK  (0x00004000U)
    2397. 

  2397. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTPENDED_SHIFT  (14U)
    2398. 

  2398. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTPENDED_RESETVAL  (0x00000000U)
    2399. 

  2399. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTPENDED_MAX  (0x00000001U)
    2400. 

  2400. 

  2401. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCALLPENDED_MASK  (0x00008000U)
    2402. 

  2402. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCALLPENDED_SHIFT  (15U)
    2403. 

  2403. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCALLPENDED_RESETVAL  (0x00000000U)
    2404. 

  2404. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCALLPENDED_MAX  (0x00000001U)
    2405. 

  2405. 

  2406. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTENA_MASK  (0x00010000U)
    2407. 

  2407. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTENA_SHIFT  (16U)
    2408. 

  2408. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTENA_RESETVAL  (0x00000000U)
    2409. 

  2409. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTENA_MAX  (0x00000001U)
    2410. 

  2410. 

  2411. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTENA_MASK  (0x00020000U)
    2412. 

  2412. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTENA_SHIFT  (17U)
    2413. 

  2413. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTENA_RESETVAL  (0x00000000U)
    2414. 

  2414. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTENA_MAX  (0x00000001U)
    2415. 

  2415. 

  2416. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTENA_MASK  (0x00040000U)
    2417. 

  2417. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTENA_SHIFT  (18U)
    2418. 

  2418. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTENA_RESETVAL  (0x00000000U)
    2419. 

  2419. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTENA_MAX  (0x00000001U)
    2420. 

  2420. 

  2421. #define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_RESETVAL   (0x00000000U)
    2422. 

  2422. 

  2423. /* CONFIGURABLE_FAULT_STATUS */
    2424. 

  2424. 

  2425. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IACCVIOL_MASK     (0x00000001U)
    2426. 

  2426. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IACCVIOL_SHIFT    (0U)
    2427. 

  2427. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IACCVIOL_RESETVAL  (0x00000000U)
    2428. 

  2428. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IACCVIOL_MAX      (0x00000001U)
    2429. 

  2429. 

  2430. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DACCVIOL_MASK     (0x00000002U)
    2431. 

  2431. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DACCVIOL_SHIFT    (1U)
    2432. 

  2432. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DACCVIOL_RESETVAL  (0x00000000U)
    2433. 

  2433. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DACCVIOL_MAX      (0x00000001U)
    2434. 

  2434. 

  2435. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MUNSTKERR_MASK    (0x00000008U)
    2436. 

  2436. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MUNSTKERR_SHIFT   (3U)
    2437. 

  2437. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MUNSTKERR_RESETVAL  (0x00000000U)
    2438. 

  2438. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MUNSTKERR_MAX     (0x00000001U)
    2439. 

  2439. 

  2440. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MSTKERR_MASK      (0x00000010U)
    2441. 

  2441. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MSTKERR_SHIFT     (4U)
    2442. 

  2442. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MSTKERR_RESETVAL  (0x00000000U)
    2443. 

  2443. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MSTKERR_MAX       (0x00000001U)
    2444. 

  2444. 

  2445. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MMARVALID_MASK    (0x00000080U)
    2446. 

  2446. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MMARVALID_SHIFT   (7U)
    2447. 

  2447. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MMARVALID_RESETVAL  (0x00000000U)
    2448. 

  2448. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MMARVALID_MAX     (0x00000001U)
    2449. 

  2449. 

  2450. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IBUSERR_MASK      (0x00000100U)
    2451. 

  2451. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IBUSERR_SHIFT     (8U)
    2452. 

  2452. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IBUSERR_RESETVAL  (0x00000000U)
    2453. 

  2453. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IBUSERR_MAX       (0x00000001U)
    2454. 

  2454. 

  2455. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_PRECISERR_MASK    (0x00000200U)
    2456. 

  2456. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_PRECISERR_SHIFT   (9U)
    2457. 

  2457. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_PRECISERR_RESETVAL  (0x00000000U)
    2458. 

  2458. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_PRECISERR_MAX     (0x00000001U)
    2459. 

  2459. 

  2460. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IMPRECISERR_MASK  (0x00000400U)
    2461. 

  2461. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IMPRECISERR_SHIFT  (10U)
    2462. 

  2462. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IMPRECISERR_RESETVAL  (0x00000000U)
    2463. 

  2463. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IMPRECISERR_MAX   (0x00000001U)
    2464. 

  2464. 

  2465. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNSTKERR_MASK     (0x00000800U)
    2466. 

  2466. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNSTKERR_SHIFT    (11U)
    2467. 

  2467. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNSTKERR_RESETVAL  (0x00000000U)
    2468. 

  2468. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNSTKERR_MAX      (0x00000001U)
    2469. 

  2469. 

  2470. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_STKERR_MASK       (0x00001000U)
    2471. 

  2471. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_STKERR_SHIFT      (12U)
    2472. 

  2472. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_STKERR_RESETVAL   (0x00000000U)
    2473. 

  2473. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_STKERR_MAX        (0x00000001U)
    2474. 

  2474. 

  2475. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_BFARVALID_MASK    (0x00008000U)
    2476. 

  2476. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_BFARVALID_SHIFT   (15U)
    2477. 

  2477. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_BFARVALID_RESETVAL  (0x00000000U)
    2478. 

  2478. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_BFARVALID_MAX     (0x00000001U)
    2479. 

  2479. 

  2480. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNDEDINSTR_MASK   (0x00010000U)
    2481. 

  2481. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNDEDINSTR_SHIFT  (16U)
    2482. 

  2482. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNDEDINSTR_RESETVAL  (0x00000000U)
    2483. 

  2483. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNDEDINSTR_MAX    (0x00000001U)
    2484. 

  2484. 

  2485. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVSTATE_MASK     (0x00020000U)
    2486. 

  2486. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVSTATE_SHIFT    (17U)
    2487. 

  2487. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVSTATE_RESETVAL  (0x00000000U)
    2488. 

  2488. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVSTATE_MAX      (0x00000001U)
    2489. 

  2489. 

  2490. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVPC_MASK        (0x00040000U)
    2491. 

  2491. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVPC_SHIFT       (18U)
    2492. 

  2492. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVPC_RESETVAL    (0x00000000U)
    2493. 

  2493. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVPC_MAX         (0x00000001U)
    2494. 

  2494. 

  2495. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_NOCP_MASK         (0x00080000U)
    2496. 

  2496. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_NOCP_SHIFT        (19U)
    2497. 

  2497. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_NOCP_RESETVAL     (0x00000000U)
    2498. 

  2498. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_NOCP_MAX          (0x00000001U)
    2499. 

  2499. 

  2500. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNALIGNED_MASK    (0x01000000U)
    2501. 

  2501. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNALIGNED_SHIFT   (24U)
    2502. 

  2502. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNALIGNED_RESETVAL  (0x00000000U)
    2503. 

  2503. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNALIGNED_MAX     (0x00000001U)
    2504. 

  2504. 

  2505. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DIVBYZERO_MASK    (0x02000000U)
    2506. 

  2506. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DIVBYZERO_SHIFT   (25U)
    2507. 

  2507. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DIVBYZERO_RESETVAL  (0x00000000U)
    2508. 

  2508. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DIVBYZERO_MAX     (0x00000001U)
    2509. 

  2509. 

  2510. #define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_RESETVAL          (0x00000000U)
    2511. 

  2511. 

  2512. /* HARD_FAULT_STATUS */
    2513. 

  2513. 

  2514. #define CSL_CM3NVIC_HARD_FAULT_STATUS_VECTBL_MASK               (0x00000002U)
    2515. 

  2515. #define CSL_CM3NVIC_HARD_FAULT_STATUS_VECTBL_SHIFT              (1U)
    2516. 

  2516. #define CSL_CM3NVIC_HARD_FAULT_STATUS_VECTBL_RESETVAL           (0x00000000U)
    2517. 

  2517. #define CSL_CM3NVIC_HARD_FAULT_STATUS_VECTBL_MAX                (0x00000001U)
    2518. 

  2518. 

  2519. #define CSL_CM3NVIC_HARD_FAULT_STATUS_FORCED_MASK               (0x40000000U)
    2520. 

  2520. #define CSL_CM3NVIC_HARD_FAULT_STATUS_FORCED_SHIFT              (30U)
    2521. 

  2521. #define CSL_CM3NVIC_HARD_FAULT_STATUS_FORCED_RESETVAL           (0x00000000U)
    2522. 

  2522. #define CSL_CM3NVIC_HARD_FAULT_STATUS_FORCED_MAX                (0x00000001U)
    2523. 

  2523. 

  2524. #define CSL_CM3NVIC_HARD_FAULT_STATUS_DEBUGEVT_MASK             (0x80000000U)
    2525. 

  2525. #define CSL_CM3NVIC_HARD_FAULT_STATUS_DEBUGEVT_SHIFT            (31U)
    2526. 

  2526. #define CSL_CM3NVIC_HARD_FAULT_STATUS_DEBUGEVT_RESETVAL         (0x00000000U)
    2527. 

  2527. #define CSL_CM3NVIC_HARD_FAULT_STATUS_DEBUGEVT_MAX              (0x00000001U)
    2528. 

  2528. 

  2529. #define CSL_CM3NVIC_HARD_FAULT_STATUS_RESETVAL                  (0x00000000U)
    2530. 

  2530. 

  2531. /* DEBUG_FAULT_STATUS */
    2532. 

  2532. 

  2533. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_HALTED_MASK              (0x00000001U)
    2534. 

  2534. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_HALTED_SHIFT             (0U)
    2535. 

  2535. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_HALTED_RESETVAL          (0x00000000U)
    2536. 

  2536. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_HALTED_MAX               (0x00000001U)
    2537. 

  2537. 

  2538. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_BKPT_MASK                (0x00000002U)
    2539. 

  2539. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_BKPT_SHIFT               (1U)
    2540. 

  2540. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_BKPT_RESETVAL            (0x00000000U)
    2541. 

  2541. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_BKPT_MAX                 (0x00000001U)
    2542. 

  2542. 

  2543. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_DWTTRAP_MASK             (0x00000004U)
    2544. 

  2544. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_DWTTRAP_SHIFT            (2U)
    2545. 

  2545. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_DWTTRAP_RESETVAL         (0x00000000U)
    2546. 

  2546. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_DWTTRAP_MAX              (0x00000001U)
    2547. 

  2547. 

  2548. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_VCATCH_MASK              (0x00000008U)
    2549. 

  2549. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_VCATCH_SHIFT             (3U)
    2550. 

  2550. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_VCATCH_RESETVAL          (0x00000000U)
    2551. 

  2551. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_VCATCH_MAX               (0x00000001U)
    2552. 

  2552. 

  2553. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_EXTERNAL_MASK            (0x00000010U)
    2554. 

  2554. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_EXTERNAL_SHIFT           (4U)
    2555. 

  2555. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_EXTERNAL_RESETVAL        (0x00000000U)
    2556. 

  2556. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_EXTERNAL_MAX             (0x00000001U)
    2557. 

  2557. 

  2558. #define CSL_CM3NVIC_DEBUG_FAULT_STATUS_RESETVAL                 (0x00000000U)
    2559. 

  2559. 

  2560. /* MEMORY_MANAGE_ADDRESS */
    2561. 

  2561. 

  2562. #define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_MMAR_MASK             (0xFFFFFFFFU)
    2563. 

  2563. #define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_MMAR_SHIFT            (0U)
    2564. 

  2564. #define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_MMAR_RESETVAL         (0x00000000U)
    2565. 

  2565. #define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_MMAR_MAX              (0xffffffffU)
    2566. 

  2566. 

  2567. #define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_RESETVAL              (0x00000000U)
    2568. 

  2568. 

  2569. /* BUS_FAULT_MANAGE_ADDRESS */
    2570. 

  2570. 

  2571. #define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_BFAR_MASK          (0xFFFFFFFFU)
    2572. 

  2572. #define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_BFAR_SHIFT         (0U)
    2573. 

  2573. #define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_BFAR_RESETVAL      (0x00000000U)
    2574. 

  2574. #define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_BFAR_MAX           (0xffffffffU)
    2575. 

  2575. 

  2576. #define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_RESETVAL           (0x00000000U)
    2577. 

  2577. 

  2578. /* AUXILIARY_FAULT_STATUS */
    2579. 

  2579. 

  2580. #define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_IMPDEF_MASK          (0xFFFFFFFFU)
    2581. 

  2581. #define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_IMPDEF_SHIFT         (0U)
    2582. 

  2582. #define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_IMPDEF_RESETVAL      (0x00000000U)
    2583. 

  2583. #define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_IMPDEF_MAX           (0xffffffffU)
    2584. 

  2584. 

  2585. #define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_RESETVAL             (0x00000000U)
    2586. 

  2586. 

  2587. /* MPU_TYPE */
    2588. 

  2588. 

  2589. #define CSL_CM3NVIC_MPU_TYPE_SEPARATE_MASK                      (0x00000001U)
    2590. 

  2590. #define CSL_CM3NVIC_MPU_TYPE_SEPARATE_SHIFT                     (0U)
    2591. 

  2591. #define CSL_CM3NVIC_MPU_TYPE_SEPARATE_RESETVAL                  (0x00000000U)
    2592. 

  2592. #define CSL_CM3NVIC_MPU_TYPE_SEPARATE_MAX                       (0x00000001U)
    2593. 

  2593. 

  2594. #define CSL_CM3NVIC_MPU_TYPE_DREGION_MASK                       (0x0000FF00U)
    2595. 

  2595. #define CSL_CM3NVIC_MPU_TYPE_DREGION_SHIFT                      (8U)
    2596. 

  2596. #define CSL_CM3NVIC_MPU_TYPE_DREGION_RESETVAL                   (0x00000000U)
    2597. 

  2597. #define CSL_CM3NVIC_MPU_TYPE_DREGION_MAX                        (0x000000ffU)
    2598. 

  2598. 

  2599. #define CSL_CM3NVIC_MPU_TYPE_IREGION_MASK                       (0x00FF0000U)
    2600. 

  2600. #define CSL_CM3NVIC_MPU_TYPE_IREGION_SHIFT                      (16U)
    2601. 

  2601. #define CSL_CM3NVIC_MPU_TYPE_IREGION_RESETVAL                   (0x00000000U)
    2602. 

  2602. #define CSL_CM3NVIC_MPU_TYPE_IREGION_MAX                        (0x000000ffU)
    2603. 

  2603. 

  2604. #define CSL_CM3NVIC_MPU_TYPE_RESETVAL                           (0x00000000U)
    2605. 

  2605. 

  2606. /* MPU_CONTROL */
    2607. 

  2607. 

  2608. #define CSL_CM3NVIC_MPU_CONTROL_ENABLE_MASK                     (0x00000001U)
    2609. 

  2609. #define CSL_CM3NVIC_MPU_CONTROL_ENABLE_SHIFT                    (0U)
    2610. 

  2610. #define CSL_CM3NVIC_MPU_CONTROL_ENABLE_RESETVAL                 (0x00000000U)
    2611. 

  2611. #define CSL_CM3NVIC_MPU_CONTROL_ENABLE_MAX                      (0x00000001U)
    2612. 

  2612. 

  2613. #define CSL_CM3NVIC_MPU_CONTROL_HFNMIENA_MASK                   (0x00000002U)
    2614. 

  2614. #define CSL_CM3NVIC_MPU_CONTROL_HFNMIENA_SHIFT                  (1U)
    2615. 

  2615. #define CSL_CM3NVIC_MPU_CONTROL_HFNMIENA_RESETVAL               (0x00000000U)
    2616. 

  2616. #define CSL_CM3NVIC_MPU_CONTROL_HFNMIENA_MAX                    (0x00000001U)
    2617. 

  2617. 

  2618. #define CSL_CM3NVIC_MPU_CONTROL_PRIVDEFENA_MASK                 (0x00000004U)
    2619. 

  2619. #define CSL_CM3NVIC_MPU_CONTROL_PRIVDEFENA_SHIFT                (2U)
    2620. 

  2620. #define CSL_CM3NVIC_MPU_CONTROL_PRIVDEFENA_RESETVAL             (0x00000000U)
    2621. 

  2621. #define CSL_CM3NVIC_MPU_CONTROL_PRIVDEFENA_MAX                  (0x00000001U)
    2622. 

  2622. 

  2623. #define CSL_CM3NVIC_MPU_CONTROL_RESETVAL                        (0x00000000U)
    2624. 

  2624. 

  2625. /* MPU_REGION_NUMBER */
    2626. 

  2626. 

  2627. #define CSL_CM3NVIC_MPU_REGION_NUMBER_REGION_MASK               (0x000000FFU)
    2628. 

  2628. #define CSL_CM3NVIC_MPU_REGION_NUMBER_REGION_SHIFT              (0U)
    2629. 

  2629. #define CSL_CM3NVIC_MPU_REGION_NUMBER_REGION_RESETVAL           (0x00000000U)
    2630. 

  2630. #define CSL_CM3NVIC_MPU_REGION_NUMBER_REGION_MAX                (0x000000ffU)
    2631. 

  2631. 

  2632. #define CSL_CM3NVIC_MPU_REGION_NUMBER_RESETVAL                  (0x00000000U)
    2633. 

  2633. 

  2634. /* MPU_REGION_BASE_ADDRESS */
    2635. 

  2635. 

  2636. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_REGION_MASK         (0x0000000FU)
    2637. 

  2637. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_REGION_SHIFT        (0U)
    2638. 

  2638. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_REGION_RESETVAL     (0x00000000U)
    2639. 

  2639. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_REGION_MAX          (0x0000000fU)
    2640. 

  2640. 

  2641. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_VALID_MASK          (0x00000010U)
    2642. 

  2642. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_VALID_SHIFT         (4U)
    2643. 

  2643. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_VALID_RESETVAL      (0x00000000U)
    2644. 

  2644. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_VALID_MAX           (0x00000001U)
    2645. 

  2645. 

  2646. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_ADDR_MASK           (0xFFFFFF00U)
    2647. 

  2647. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_ADDR_SHIFT          (8U)
    2648. 

  2648. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_ADDR_RESETVAL       (0x00000000U)
    2649. 

  2649. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_ADDR_MAX            (0x00ffffffU)
    2650. 

  2650. 

  2651. #define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_RESETVAL            (0x00000000U)
    2652. 

  2652. 

  2653. /* MPU_REGION_BASE_ATTRIBUTE_AND_SIZE */
    2654. 

  2654. 

  2655. #define CSL_CM3NVIC_MPU_REGION_BASE_ATTRIBUTE_AND_SIZE_RESETVAL  (0x00000000U)
    2656. 

  2656. 

  2657. /* MPU_ALIAS */
    2658. 

  2658. 

  2659. #define CSL_CM3NVIC_MPU_ALIAS_RESETVAL                          (0x00000000U)
    2660. 

  2660. 

  2661. /* DEBUG_HALTING_CONTROL_AND_STATUS */
    2662. 

  2662. 

  2663. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_DEBUGEN_MASK  (0x00000001U)
    2664. 

  2664. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_DEBUGEN_SHIFT  (0U)
    2665. 

  2665. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_DEBUGEN_RESETVAL  (0x00000000U)
    2666. 

  2666. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_DEBUGEN_MAX  (0x00000001U)
    2667. 

  2667. 

  2668. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_HALT_MASK  (0x00000002U)
    2669. 

  2669. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_HALT_SHIFT  (1U)
    2670. 

  2670. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_HALT_RESETVAL  (0x00000000U)
    2671. 

  2671. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_HALT_MAX  (0x00000001U)
    2672. 

  2672. 

  2673. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_STEP_MASK  (0x00000004U)
    2674. 

  2674. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_STEP_SHIFT  (2U)
    2675. 

  2675. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_STEP_RESETVAL  (0x00000000U)
    2676. 

  2676. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_STEP_MAX  (0x00000001U)
    2677. 

  2677. 

  2678. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_MASKINTS_MASK  (0x00000008U)
    2679. 

  2679. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_MASKINTS_SHIFT  (3U)
    2680. 

  2680. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_MASKINTS_RESETVAL  (0x00000000U)
    2681. 

  2681. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_MASKINTS_MAX  (0x00000001U)
    2682. 

  2682. 

  2683. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_SNAPSTALL_MASK  (0x00000020U)
    2684. 

  2684. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_SNAPSTALL_SHIFT  (5U)
    2685. 

  2685. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_SNAPSTALL_RESETVAL  (0x00000000U)
    2686. 

  2686. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_SNAPSTALL_MAX  (0x00000001U)
    2687. 

  2687. 

  2688. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_REGRDY_MASK  (0x00010000U)
    2689. 

  2689. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_REGRDY_SHIFT  (16U)
    2690. 

  2690. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_REGRDY_RESETVAL  (0x00000000U)
    2691. 

  2691. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_REGRDY_MAX  (0x00000001U)
    2692. 

  2692. 

  2693. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_HALT_MASK  (0x00020000U)
    2694. 

  2694. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_HALT_SHIFT  (17U)
    2695. 

  2695. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_HALT_RESETVAL  (0x00000000U)
    2696. 

  2696. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_HALT_MAX  (0x00000001U)
    2697. 

  2697. 

  2698. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_SLEEP_MASK  (0x00040000U)
    2699. 

  2699. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_SLEEP_SHIFT  (18U)
    2700. 

  2700. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_SLEEP_RESETVAL  (0x00000000U)
    2701. 

  2701. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_SLEEP_MAX  (0x00000001U)
    2702. 

  2702. 

  2703. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_LOCKUP_MASK  (0x00080000U)
    2704. 

  2704. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_LOCKUP_SHIFT  (19U)
    2705. 

  2705. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_LOCKUP_RESETVAL  (0x00000000U)
    2706. 

  2706. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_LOCKUP_MAX  (0x00000001U)
    2707. 

  2707. 

  2708. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RETIRE_ST_MASK  (0x01000000U)
    2709. 

  2709. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RETIRE_ST_SHIFT  (24U)
    2710. 

  2710. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RETIRE_ST_RESETVAL  (0x00000000U)
    2711. 

  2711. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RETIRE_ST_MAX  (0x00000001U)
    2712. 

  2712. 

  2713. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RESET_ST_MASK  (0x02000000U)
    2714. 

  2714. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RESET_ST_SHIFT  (25U)
    2715. 

  2715. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RESET_ST_RESETVAL  (0x00000000U)
    2716. 

  2716. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RESET_ST_MAX  (0x00000001U)
    2717. 

  2717. 

  2718. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_KEY_MASK   (0xFC000000U)
    2719. 

  2719. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_KEY_SHIFT  (26U)
    2720. 

  2720. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_KEY_RESETVAL  (0x00000000U)
    2721. 

  2721. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_KEY_MAX    (0x0000003fU)
    2722. 

  2722. 

  2723. #define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_RESETVAL   (0x00000000U)
    2724. 

  2724. 

  2725. /* DEBUG_CORE_REGISTER_SELECTOR */
    2726. 

  2726. 

  2727. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGSEL_MASK    (0x0000001FU)
    2728. 

  2728. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGSEL_SHIFT   (0U)
    2729. 

  2729. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGSEL_RESETVAL  (0x00000000U)
    2730. 

  2730. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGSEL_MAX     (0x0000001fU)
    2731. 

  2731. 

  2732. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGWNR_MASK    (0x00010000U)
    2733. 

  2733. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGWNR_SHIFT   (16U)
    2734. 

  2734. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGWNR_RESETVAL  (0x00000000U)
    2735. 

  2735. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGWNR_MAX     (0x00000001U)
    2736. 

  2736. 

  2737. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_RESETVAL       (0x00000000U)
    2738. 

  2738. 

  2739. /* DEBUG_CORE_REGISTER_DATA */
    2740. 

  2740. 

  2741. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_DATA_MASK          (0xFFFFFFFFU)
    2742. 

  2742. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_DATA_SHIFT         (0U)
    2743. 

  2743. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_DATA_RESETVAL      (0x00000000U)
    2744. 

  2744. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_DATA_MAX           (0xffffffffU)
    2745. 

  2745. 

  2746. #define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_RESETVAL           (0x00000000U)
    2747. 

  2747. 

  2748. /* DEBUG_EXCEPTION_AND_MONITOR_CONTROL */
    2749. 

  2749. 

  2750. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CORERESET_MASK  (0x00000001U)
    2751. 

  2751. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CORERESET_SHIFT  (0U)
    2752. 

  2752. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CORERESET_RESETVAL  (0x00000000U)
    2753. 

  2753. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CORERESET_MAX  (0x00000001U)
    2754. 

  2754. 

  2755. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_MMERR_MASK  (0x00000010U)
    2756. 

  2756. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_MMERR_SHIFT  (4U)
    2757. 

  2757. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_MMERR_RESETVAL  (0x00000000U)
    2758. 

  2758. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_MMERR_MAX  (0x00000001U)
    2759. 

  2759. 

  2760. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_NOCPERR_MASK  (0x00000020U)
    2761. 

  2761. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_NOCPERR_SHIFT  (5U)
    2762. 

  2762. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_NOCPERR_RESETVAL  (0x00000000U)
    2763. 

  2763. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_NOCPERR_MAX  (0x00000001U)
    2764. 

  2764. 

  2765. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CHKERR_MASK  (0x00000040U)
    2766. 

  2766. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CHKERR_SHIFT  (6U)
    2767. 

  2767. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CHKERR_RESETVAL  (0x00000000U)
    2768. 

  2768. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CHKERR_MAX  (0x00000001U)
    2769. 

  2769. 

  2770. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_STATERR_MASK  (0x00000080U)
    2771. 

  2771. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_STATERR_SHIFT  (7U)
    2772. 

  2772. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_STATERR_RESETVAL  (0x00000000U)
    2773. 

  2773. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_STATERR_MAX  (0x00000001U)
    2774. 

  2774. 

  2775. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_BUSERR_MASK  (0x00000100U)
    2776. 

  2776. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_BUSERR_SHIFT  (8U)
    2777. 

  2777. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_BUSERR_RESETVAL  (0x00000000U)
    2778. 

  2778. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_BUSERR_MAX  (0x00000001U)
    2779. 

  2779. 

  2780. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_INTERR_MASK  (0x00000200U)
    2781. 

  2781. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_INTERR_SHIFT  (9U)
    2782. 

  2782. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_INTERR_RESETVAL  (0x00000000U)
    2783. 

  2783. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_INTERR_MAX  (0x00000001U)
    2784. 

  2784. 

  2785. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_HARDERR_MASK  (0x00000400U)
    2786. 

  2786. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_HARDERR_SHIFT  (10U)
    2787. 

  2787. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_HARDERR_RESETVAL  (0x00000000U)
    2788. 

  2788. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_HARDERR_MAX  (0x00000001U)
    2789. 

  2789. 

  2790. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_EN_MASK  (0x00010000U)
    2791. 

  2791. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_EN_SHIFT  (16U)
    2792. 

  2792. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_EN_RESETVAL  (0x00000000U)
    2793. 

  2793. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_EN_MAX  (0x00000001U)
    2794. 

  2794. 

  2795. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_PEND_MASK  (0x00020000U)
    2796. 

  2796. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_PEND_SHIFT  (17U)
    2797. 

  2797. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_PEND_RESETVAL  (0x00000000U)
    2798. 

  2798. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_PEND_MAX  (0x00000001U)
    2799. 

  2799. 

  2800. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_STEP_MASK  (0x00040000U)
    2801. 

  2801. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_STEP_SHIFT  (18U)
    2802. 

  2802. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_STEP_RESETVAL  (0x00000000U)
    2803. 

  2803. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_STEP_MAX  (0x00000001U)
    2804. 

  2804. 

  2805. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_REQ_MASK  (0x00080000U)
    2806. 

  2806. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_REQ_SHIFT  (19U)
    2807. 

  2807. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_REQ_RESETVAL  (0x00000000U)
    2808. 

  2808. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_REQ_MAX  (0x00000001U)
    2809. 

  2809. 

  2810. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_TRC_ENA_MASK  (0x01000000U)
    2811. 

  2811. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_TRC_ENA_SHIFT  (24U)
    2812. 

  2812. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_TRC_ENA_RESETVAL  (0x00000000U)
    2813. 

  2813. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_TRC_ENA_MAX  (0x00000001U)
    2814. 

  2814. 

  2815. #define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_RESETVAL  (0x00000000U)
    2816. 

  2816. 

  2817. /* SOFTWARE_TRIGGER_INTERRUPT */
    2818. 

  2818. 

  2819. #define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_INTID_MASK       (0x000001FFU)
    2820. 

  2820. #define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_INTID_SHIFT      (0U)
    2821. 

  2821. #define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_INTID_RESETVAL   (0x00000000U)
    2822. 

  2822. #define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_INTID_MAX        (0x000001ffU)
    2823. 

  2823. 

  2824. #define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_RESETVAL         (0x00000000U)
    2825. 

  2825. 

  2826. /* NVIC_PERIPHERAL_ID_4 */
    2827. 

  2827. 

  2828. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_PERIPHID4_MASK         (0x000000FFU)
    2829. 

  2829. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_PERIPHID4_SHIFT        (0U)
    2830. 

  2830. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_PERIPHID4_RESETVAL     (0x00000004U)
    2831. 

  2831. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_PERIPHID4_MAX          (0x000000ffU)
    2832. 

  2832. 

  2833. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_RESETVAL               (0x00000004U)
    2834. 

  2834. 

  2835. /* NVIC_PERIPHERAL_ID_5 */
    2836. 

  2836. 

  2837. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_PERIPHID5_MASK         (0x000000FFU)
    2838. 

  2838. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_PERIPHID5_SHIFT        (0U)
    2839. 

  2839. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_PERIPHID5_RESETVAL     (0x00000000U)
    2840. 

  2840. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_PERIPHID5_MAX          (0x000000ffU)
    2841. 

  2841. 

  2842. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_RESETVAL               (0x00000000U)
    2843. 

  2843. 

  2844. /* NVIC_PERIPHERAL_ID_6 */
    2845. 

  2845. 

  2846. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_PERIPHID6_MASK         (0x000000FFU)
    2847. 

  2847. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_PERIPHID6_SHIFT        (0U)
    2848. 

  2848. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_PERIPHID6_RESETVAL     (0x00000000U)
    2849. 

  2849. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_PERIPHID6_MAX          (0x000000ffU)
    2850. 

  2850. 

  2851. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_RESETVAL               (0x00000000U)
    2852. 

  2852. 

  2853. /* NVIC_PERIPHERAL_ID_7 */
    2854. 

  2854. 

  2855. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_PERIPHID7_MASK         (0x000000FFU)
    2856. 

  2856. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_PERIPHID7_SHIFT        (0U)
    2857. 

  2857. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_PERIPHID7_RESETVAL     (0x00000000U)
    2858. 

  2858. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_PERIPHID7_MAX          (0x000000ffU)
    2859. 

  2859. 

  2860. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_RESETVAL               (0x00000000U)
    2861. 

  2861. 

  2862. /* NVIC_PERIPHERAL_ID_0 */
    2863. 

  2863. 

  2864. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_PERIPHID0_MASK         (0x000000FFU)
    2865. 

  2865. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_PERIPHID0_SHIFT        (0U)
    2866. 

  2866. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_PERIPHID0_RESETVAL     (0x00000000U)
    2867. 

  2867. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_PERIPHID0_MAX          (0x000000ffU)
    2868. 

  2868. 

  2869. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_RESETVAL               (0x00000000U)
    2870. 

  2870. 

  2871. /* NVIC_PERIPHERAL_ID_1 */
    2872. 

  2872. 

  2873. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_PERIPHID1_MASK         (0x000000FFU)
    2874. 

  2874. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_PERIPHID1_SHIFT        (0U)
    2875. 

  2875. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_PERIPHID1_RESETVAL     (0x000000b0U)
    2876. 

  2876. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_PERIPHID1_MAX          (0x000000ffU)
    2877. 

  2877. 

  2878. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_RESETVAL               (0x000000b0U)
    2879. 

  2879. 

  2880. /* NVIC_PERIPHERAL_ID_2 */
    2881. 

  2881. 

  2882. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_PERIPHID2_MASK         (0x000000FFU)
    2883. 

  2883. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_PERIPHID2_SHIFT        (0U)
    2884. 

  2884. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_PERIPHID2_RESETVAL     (0x0000002bU)
    2885. 

  2885. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_PERIPHID2_MAX          (0x000000ffU)
    2886. 

  2886. 

  2887. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_RESETVAL               (0x0000002bU)
    2888. 

  2888. 

  2889. /* NVIC_PERIPHERAL_ID_3 */
    2890. 

  2890. 

  2891. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_PERIPHID3_MASK         (0x000000FFU)
    2892. 

  2892. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_PERIPHID3_SHIFT        (0U)
    2893. 

  2893. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_PERIPHID3_RESETVAL     (0x00000000U)
    2894. 

  2894. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_PERIPHID3_MAX          (0x000000ffU)
    2895. 

  2895. 

  2896. #define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_RESETVAL               (0x00000000U)
    2897. 

  2897. 

  2898. /* NVIC_COMPONENT_ID_0 */
    2899. 

  2899. 

  2900. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_PCELLID0_MASK           (0x000000FFU)
    2901. 

  2901. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_PCELLID0_SHIFT          (0U)
    2902. 

  2902. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_PCELLID0_RESETVAL       (0x0000000dU)
    2903. 

  2903. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_PCELLID0_MAX            (0x000000ffU)
    2904. 

  2904. 

  2905. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_RESETVAL                (0x0000000dU)
    2906. 

  2906. 

  2907. /* NVIC_COMPONENT_ID_1 */
    2908. 

  2908. 

  2909. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_PCELLID1_MASK           (0x000000FFU)
    2910. 

  2910. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_PCELLID1_SHIFT          (0U)
    2911. 

  2911. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_PCELLID1_RESETVAL       (0x000000e0U)
    2912. 

  2912. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_PCELLID1_MAX            (0x000000ffU)
    2913. 

  2913. 

  2914. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_RESETVAL                (0x000000e0U)
    2915. 

  2915. 

  2916. /* NVIC_COMPONENT_ID_2 */
    2917. 

  2917. 

  2918. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_PCELLID2_MASK           (0x000000FFU)
    2919. 

  2919. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_PCELLID2_SHIFT          (0U)
    2920. 

  2920. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_PCELLID2_RESETVAL       (0x00000005U)
    2921. 

  2921. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_PCELLID2_MAX            (0x000000ffU)
    2922. 

  2922. 

  2923. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_RESETVAL                (0x00000005U)
    2924. 

  2924. 

  2925. /* NVIC_COMPONENT_ID_3 */
    2926. 

  2926. 

  2927. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_PCELLID3_MASK           (0x000000FFU)
    2928. 

  2928. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_PCELLID3_SHIFT          (0U)
    2929. 

  2929. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_PCELLID3_RESETVAL       (0x000000b1U)
    2930. 

  2930. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_PCELLID3_MAX            (0x000000ffU)
    2931. 

  2931. 

  2932. #define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_RESETVAL                (0x000000b1U)
    2933. 

  2933. 

  2934. #ifdef __cplusplus
    2935. 

  2935. }
    2936. 

  2936. #endif
    2937. 

  2937. #endif
    2938.