csl_cpswAux.h 16 KB

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  1. /**
  2. * @file csl_cpsw_Aux.h
  3. *
  4. * @brief
  5. * API Auxilary header file for Ethernet switch module CSL.
  6. *
  7. * Contains the different control command and status query functions definations
  8. *
  9. * \par
  10. * ============================================================================
  11. * @n (C) Copyright 2009-2017, Texas Instruments, Inc.
  12. *
  13. * Redistribution and use in source and binary forms, with or without
  14. * modification, are permitted provided that the following conditions
  15. * are met:
  16. *
  17. * Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. *
  20. * Redistributions in binary form must reproduce the above copyright
  21. * notice, this list of conditions and the following disclaimer in the
  22. * documentation and/or other materials provided with the
  23. * distribution.
  24. *
  25. * Neither the name of Texas Instruments Incorporated nor the names of
  26. * its contributors may be used to endorse or promote products derived
  27. * from this software without specific prior written permission.
  28. *
  29. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40. *
  41. */
  42. #ifndef CSL_CPSW_AUX_H_
  43. #define CSL_CPSW_AUX_H_
  44. #ifdef __cplusplus
  45. extern "C" {
  46. #endif
  47. #include <ti/csl/cslr.h>
  48. #include <ti/csl/tistdtypes.h>
  49. #include <ti/csl/soc.h>
  50. /**
  51. @defgroup CSL_CPSW_SYMBOL CPSW Symbols Defined
  52. @ingroup CSL_CPSW_API
  53. */
  54. /**
  55. @defgroup CSL_CPSW_DATASTRUCT CPSW Data Structures
  56. @ingroup CSL_CPSW_API
  57. */
  58. /**
  59. @defgroup CSL_CPSW_FUNCTION CPSW Functions
  60. @ingroup CSL_CPSW_API
  61. */
  62. /**
  63. @defgroup CSL_CPSW_ENUM CPSW Enumerated Data Types
  64. @ingroup CSL_CPSW_API
  65. */
  66. /**
  67. @addtogroup CSL_CPSW_SYMBOL
  68. @{
  69. */
  70. /**
  71. @}
  72. */
  73. /** @addtogroup CSL_CPSW_DATASTRUCT
  74. @{ */
  75. /** @brief ALE control register configuration definitions */
  76. /** Enable Broadcast/Multicast rate limit */
  77. #define CSL_CPSW_ALECONTROL_RATELIMIT_EN (1 << 0u)
  78. /** MAC auhorization mode enable */
  79. #define CSL_CPSW_ALECONTROL_AUTHMODE_EN (1 << 1u)
  80. /** VLAN Aware Mode enable */
  81. #define CSL_CPSW_ALECONTROL_VLANAWARE_EN (1 << 2u)
  82. /** Tx rate limit enable */
  83. #define CSL_CPSW_ALECONTROL_RATELIMIT_TX_EN (1 << 3u)
  84. /** OUI deny enable */
  85. #define CSL_CPSW_ALECONTROL_OUIDENY_EN (1 << 5u)
  86. /** VID0 mode enable */
  87. #define CSL_CPSW_ALECONTROL_VID0MODE_EN (1 << 6u)
  88. /** Learn no VID enable */
  89. #define CSL_CPSW_ALECONTROL_LEARN_NO_VID_EN (1 << 7u)
  90. /** Age out now enable */
  91. #define CSL_CPSW_ALECONTROL_AGEOUT_NOW_EN (1 << 29u)
  92. /** Clear table enable */
  93. #define CSL_CPSW_ALECONTROL_CLRTABLE_EN (1 << 30u)
  94. /** ALE enable */
  95. #define CSL_CPSW_ALECONTROL_ALE_EN (1 << 31u)
  96. /** @brief Port Mask definitions */
  97. /** Port 0 Enable */
  98. #define CSL_CPSW_PORTMASK_PORT0_EN (1 << 0u)
  99. /** Port 1 Enable */
  100. #define CSL_CPSW_PORTMASK_PORT1_EN (1 << 1u)
  101. /** Port 2 Enable */
  102. #define CSL_CPSW_PORTMASK_PORT2_EN (1 << 2u)
  103. /** Port 3 Enable */
  104. #define CSL_CPSW_PORTMASK_PORT3_EN (1 << 3u)
  105. /** Port 4 Enable */
  106. #define CSL_CPSW_PORTMASK_PORT4_EN (1 << 4u)
  107. /** Port 5 Enable */
  108. #define CSL_CPSW_PORTMASK_PORT5_EN (1 << 5u)
  109. /** Port 6 Enable */
  110. #define CSL_CPSW_PORTMASK_PORT6_EN (1 << 6u)
  111. /** Port 7 Enable */
  112. #define CSL_CPSW_PORTMASK_PORT7_EN (1 << 7u)
  113. /** @brief
  114. *
  115. * Holds the Time sync submodule's version info.
  116. */
  117. typedef struct {
  118. /** Minor version value */
  119. Uint32 minorVer;
  120. /** Major version value */
  121. Uint32 majorVer;
  122. /** RTL version value */
  123. Uint32 rtlVer;
  124. /** Identification value */
  125. Uint32 id;
  126. } CSL_CPSW_VERSION;
  127. /** @brief
  128. *
  129. * Holds CPSW control register contents.
  130. */
  131. typedef struct {
  132. /** FIFO loopback mode */
  133. Uint32 fifoLb;
  134. /** Vlan aware mode */
  135. Uint32 vlanAware;
  136. /** Port 0 Enable */
  137. Uint32 p0Enable;
  138. /** Port 0 Pass Priority Tagged */
  139. Uint32 p0PassPriTag;
  140. /** Port 1 Pass Priority Tagged */
  141. Uint32 p1PassPriTag;
  142. /** Port 2 Pass Priority Tagged */
  143. Uint32 p2PassPriTag;
  144. /** Port 3 Pass Priority Tagged */
  145. Uint32 p3PassPriTag;
  146. /** Port 4 Pass Priority Tagged */
  147. Uint32 p4PassPriTag;
  148. /** Port 5 Pass Priority Tagged */
  149. Uint32 p5PassPriTag;
  150. /** Port 6 Pass Priority Tagged */
  151. Uint32 p6PassPriTag;
  152. /** Port 7 Pass Priority Tagged */
  153. Uint32 p7PassPriTag;
  154. /** Port 8 Pass Priority Tagged */
  155. Uint32 p8PassPriTag;
  156. /** Port 0 Transmit CRC remove */
  157. Uint32 p0TxCrcRemove;
  158. /** Port 0 Receive Short Packet Pad
  159. 0 - short packets are dropped
  160. 1 - short packets are padded to 64-bytes (with pad and added CRC)
  161. if the CRC is not passed in. Short packets are dropped if the CRC is
  162. passed (in the Info0 word).
  163. */
  164. Uint32 p0RxPad;
  165. /** Port 0 Pass Received CRC errors */
  166. Uint32 p0RxPassCrcErr;
  167. /** Energy Efficient Ethernet enable */
  168. Uint32 eeeEnable;
  169. } CSL_CPSW_CONTROL;
  170. /** @brief
  171. *
  172. * Holds Priority type register contents.
  173. */
  174. typedef struct {
  175. /** Escalate priority load value */
  176. Uint32 escPriLdVal;
  177. /** Port 0 Priority type escalate */
  178. Uint32 p0PtypeEsc;
  179. /** Port 1 Priority type escalate */
  180. Uint32 p1PtypeEsc;
  181. /** Port 2 Priority type escalate */
  182. Uint32 p2PtypeEsc;
  183. /** Port 3 Priority type escalate */
  184. Uint32 p3PtypeEsc;
  185. /** Port 4 Priority type escalate */
  186. Uint32 p4PtypeEsc;
  187. /** Port 5 Priority type escalate */
  188. Uint32 p5PtypeEsc;
  189. /** Port 6 Priority type escalate */
  190. Uint32 p6PtypeEsc;
  191. /** Port 7 Priority type escalate */
  192. Uint32 p7PtypeEsc;
  193. /** Port 8 Priority type escalate */
  194. Uint32 p8PtypeEsc;
  195. } CSL_CPSW_PTYPE;
  196. /** @brief
  197. *
  198. * Holds flow control register contents.
  199. */
  200. typedef struct {
  201. /** Port 0 flow control enable */
  202. Uint32 p0FlowEnable;
  203. /** Port 1 flow control enable */
  204. Uint32 p1FlowEnable;
  205. /** Port 2 flow control enable */
  206. Uint32 p2FlowEnable;
  207. /** Port 3 flow control enable */
  208. Uint32 p3FlowEnable;
  209. /** Port 4 flow control enable */
  210. Uint32 p4FlowEnable;
  211. /** Port 5 flow control enable */
  212. Uint32 p5FlowEnable;
  213. /** Port 6 flow control enable */
  214. Uint32 p6FlowEnable;
  215. /** Port 7 flow control enable */
  216. Uint32 p7FlowEnable;
  217. /** Port 8 flow control enable */
  218. Uint32 p8FlowEnable;
  219. } CSL_CPSW_FLOWCNTL;
  220. /** @brief
  221. *
  222. * Holds the ALE submodule's version info.
  223. */
  224. typedef struct {
  225. /** Minor version value */
  226. Uint32 minorVer;
  227. /** Major version value */
  228. Uint32 majorVer;
  229. /** RTL version value */
  230. Uint32 rtlVer;
  231. /** Identification value */
  232. Uint32 id;
  233. } CSL_CPSW_ALE_VERSION;
  234. /** @brief
  235. *
  236. * Defines ALE port states
  237. */
  238. typedef enum {
  239. ALE_PORTSTATE_DISABLED = 0,
  240. ALE_PORTSTATE_BLOCKED,
  241. ALE_PORTSTATE_LEARN,
  242. ALE_PORTSTATE_FORWARD
  243. } CSL_CPSW_ALE_PORTSTATE;
  244. /** @brief
  245. *
  246. * Holds the ALE Port control register info.
  247. */
  248. typedef struct {
  249. /** Port state */
  250. CSL_CPSW_ALE_PORTSTATE portState;
  251. /** Drop non-VLAN tagged ingress packets? */
  252. Uint32 dropUntaggedEnable;
  253. /** VLAN ID Ingress check enable */
  254. Uint32 vidIngressCheckEnable;
  255. /** No learn mode enable */
  256. Uint32 noLearnModeEnable;
  257. /** No Source Address Update enable */
  258. Uint32 noSaUpdateEnable;
  259. /** MAC only mode enable:
  260. * When set allows the port to be treated like
  261. * a Mac port for the host. All traffic received
  262. * is sent only to the host. The host must direct
  263. * traffic to this port as the lookup engine will
  264. * not send traffic to ports with macOnlyEnable
  265. * and noLearnModeEnable is set.
  266. * If macOnlyEnable is set and noLearnModeEnable
  267. * is not set, the host can send non-directed packets
  268. * to a lookup destination with macOnlyEnable set.
  269. * It is also possible that the host can broadcast
  270. * to all ports including Mac Only ports in this mode.
  271. */
  272. Uint32 macOnlyEnable;
  273. /** Disable MAC Authorization Mode for this port
  274. * @note: This field is only valid when CPSW
  275. * MAC authentication is enabled.
  276. */
  277. Uint32 macAuthDisable;
  278. /** Mac Only Copy All Frames:
  279. * Set: A Mac Only port will transfer all received
  280. * good frames to the host.
  281. * Clear: A Mac Only port will transfer packets to
  282. * the host based on ALE destination address
  283. * lookup operation.
  284. */
  285. Uint32 macOnlyCafEnable;
  286. /** Multicast packet rate limit */
  287. Uint32 mcastLimit;
  288. /** Broadcast packet rate limit */
  289. Uint32 bcastLimit;
  290. } CSL_CPSW_ALE_PORTCONTROL;
  291. /** @brief
  292. *
  293. * Defines ALE Table Entry types
  294. */
  295. typedef enum {
  296. ALE_ENTRYTYPE_FREE = 0,
  297. ALE_ENTRYTYPE_ADDRESS,
  298. ALE_ENTRYTYPE_VLAN,
  299. ALE_ENTRYTYPE_VLANADDRESS
  300. } CSL_CPSW_ALE_ENTRYTYPE;
  301. /** @brief
  302. *
  303. * ALE Table entry type: MAC ADDRESS
  304. */
  305. #define ALE_ENTRYTYPE_MAC_ADDR ALE_ENTRYTYPE_ADDRESS
  306. /** @brief
  307. *
  308. * ALE Table entry type: POLICER ENTRY
  309. */
  310. #define ALE_ENTRYTYPE_POLICER ALE_ENTRYTYPE_VLAN
  311. /** @brief
  312. *
  313. * Defines ALE Unicast types
  314. */
  315. typedef enum {
  316. ALE_UCASTTYPE_UCAST_NOAGE = 0,
  317. ALE_UCASTTYPE_UCAST_AGENOTOUCH,
  318. ALE_UCASTTYPE_UCAST_OUI,
  319. ALE_UCASTTYPE_UCAST_AGETOUCH
  320. } CSL_CPSW_ALE_UCASTTYPE;
  321. /** @brief
  322. *
  323. * Defines ALE Address types
  324. */
  325. typedef enum {
  326. ALE_ADDRTYPE_UCAST = 0,
  327. ALE_ADDRTYPE_MCAST,
  328. ALE_ADDRTYPE_OUI
  329. } CSL_CPSW_ALE_ADDRTYPE;
  330. /** @brief
  331. *
  332. * Defines ALE Policer Entry types
  333. */
  334. typedef enum {
  335. ALE_POLICER_ENTRYTYPE_VLAN = 0, /** VLAN or Inner VLAN */
  336. ALE_POLICER_ENTRYTYPE_OVLAN, /** Outer VLAN */
  337. ALE_POLICER_ENTRYTYPE_ETHERTYPE, /** Ethertype */
  338. ALE_POLICER_ENTRYTYPE_IPV4, /** IPv4 address */
  339. ALE_POLICER_ENTRYTYPE_IPV6 /** IPv6 address */
  340. } CSL_CPSW_ALE_POLICER_ENTRYTYPE;
  341. /** @brief
  342. *
  343. * Holds the ALE Multicast Address Table entry
  344. * configuration.
  345. */
  346. typedef struct {
  347. /** Multicast address */
  348. Uint8 macAddress [6];
  349. /** Multicast forward state */
  350. Uint32 mcastFwdState;
  351. /** Supervisory bit enable? */
  352. Uint32 superEnable;
  353. /** Port Mask. */
  354. Uint32 portMask;
  355. } CSL_CPSW_ALE_MCASTADDR_ENTRY;
  356. /** @brief
  357. *
  358. * Holds the ALE VLAN/Multicast Address Table entry
  359. * configuration.
  360. */
  361. typedef struct {
  362. /** Multicast address */
  363. Uint8 macAddress [6];
  364. /** VLAN Id */
  365. Uint32 vlanId;
  366. /** Multicast forward state */
  367. Uint32 mcastFwdState;
  368. /** Supervisory bit enable? */
  369. Uint32 superEnable;
  370. /** Port Mask. */
  371. Uint32 portMask;
  372. } CSL_CPSW_ALE_VLANMCASTADDR_ENTRY;
  373. /** @brief
  374. *
  375. * Holds the ALE Unicast Address Table entry
  376. * configuration.
  377. */
  378. typedef struct {
  379. /** Unicast address */
  380. Uint8 macAddress [6];
  381. /** Unicast type */
  382. CSL_CPSW_ALE_UCASTTYPE ucastType;
  383. /** Secure bit enable? */
  384. Uint32 secureEnable;
  385. /** Block bit enable? */
  386. Uint32 blockEnable;
  387. /** Port Number to forward matching packets to. */
  388. Uint32 portNumber;
  389. } CSL_CPSW_ALE_UNICASTADDR_ENTRY;
  390. /** @brief
  391. *
  392. * Holds the ALE OUI Unicast Address Table entry
  393. * configuration.
  394. */
  395. typedef struct {
  396. /** OUI Unicast address */
  397. Uint8 ouiAddress [3];
  398. /** Unicast type */
  399. CSL_CPSW_ALE_UCASTTYPE ucastType;
  400. } CSL_CPSW_ALE_OUIADDR_ENTRY;
  401. /** @brief
  402. *
  403. * Holds the ALE VLAN Unicast Address Table entry
  404. * configuration.
  405. */
  406. typedef struct {
  407. /** Unicast address */
  408. Uint8 macAddress [6];
  409. /** VLAN Id */
  410. Uint32 vlanId;
  411. /** Unicast type */
  412. CSL_CPSW_ALE_UCASTTYPE ucastType;
  413. /** Secure bit enable? */
  414. Uint32 secureEnable;
  415. /** Block bit enable? */
  416. Uint32 blockEnable;
  417. /** Port Number to forward matching packets to. */
  418. Uint32 portNumber;
  419. } CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY;
  420. /** @brief
  421. *
  422. * Holds the ALE (Inner) VLAN Table entry configuration.
  423. */
  424. typedef struct {
  425. /** VLAN Id */
  426. Uint32 vlanId;
  427. /** VLAN member list */
  428. Uint32 vlanMemList;
  429. /** Unregistered Multicast Flood mask */
  430. Uint32 unRegMcastFloodMask;
  431. /** Registered Multicast Flood mask */
  432. Uint32 regMcastFloodMask;
  433. /** Force Untagged Packet Egress. */
  434. Uint32 forceUntaggedEgress;
  435. } CSL_CPSW_ALE_VLAN_ENTRY;
  436. /** @brief
  437. *
  438. * Holds the ALE Outer VLAN Table entry configuration.
  439. */
  440. typedef struct {
  441. /** VLAN Id */
  442. Uint32 vlanId;
  443. } CSL_CPSW_ALE_OUTER_VLAN_ENTRY;
  444. /** @brief
  445. *
  446. * Holds the ALE Ethertype Table entry configuration.
  447. */
  448. typedef struct {
  449. /** Ethernet Type */
  450. Uint32 ethertype;
  451. } CSL_CPSW_ALE_ETHERTYPE_ENTRY;
  452. /** @brief
  453. *
  454. * Holds the ALE IPv4 Address Table entry
  455. * configuration.
  456. */
  457. typedef struct {
  458. /** IPv4 address */
  459. Uint8 address [4];
  460. } CSL_CPSW_ALE_IPv4_ENTRY;
  461. /** @brief
  462. *
  463. * Holds the ALE IPv6 Address Table entry
  464. * configuration.
  465. */
  466. typedef struct {
  467. /** IPv6 address */
  468. Uint8 address [16];
  469. } CSL_CPSW_ALE_IPv6_ENTRY;
  470. /** ============================================================================
  471. *
  472. * @defgroup CSL_CPSW_API Ethernet switch submodule (CPSW)
  473. * @ingroup CSL_CPSW_API
  474. *
  475. *
  476. * @subsection xxx Overview
  477. * CSL CPSW API has implementation for multiple SoCs with below SoC map
  478. * -# cpsw v0 - SOC_K2H/SOC_K2K
  479. * -# cpsw v1 - SOC_K2E/SOC_K2L
  480. * -# cpsw v2 - SOC_K2G
  481. * -# cpsw v3 - SOC_AM574x/SOC_AM572x/SOC_AM571x/SOC_DRA75X/SOC_DRA78X
  482. * -# cpsw v4 - SOC_C6678
  483. *
  484. * @note: there may not be any ip specific implementation for that soc, if it contains only cslr_* files
  485. *
  486. * ============================================================================
  487. */
  488. #if defined(SOC_K2K)
  489. #include <ti/csl/src/ip/cpsw/V0/csl_cpswAux.h>
  490. #elif defined(SOC_K2H)
  491. #include <ti/csl/src/ip/cpsw/V0/csl_cpswAux.h>
  492. #elif defined(SOC_K2E)
  493. #include <ti/csl/src/ip/cpsw/V1/csl_cpswAux.h>
  494. #elif defined(SOC_K2L)
  495. #include <ti/csl/src/ip/cpsw/V1/csl_cpswAux.h>
  496. #elif defined(SOC_K2G)
  497. #include <ti/csl/src/ip/cpsw/V2/csl_cpswAux.h>
  498. #elif defined(SOC_AM574x) || defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_DRA72x) || defined(SOC_DRA75x) || defined(SOC_DRA78x)
  499. #include <ti/csl/src/ip/cpsw/V3/csl_cpswAux.h>
  500. #elif defined(SOC_C6678)
  501. #include <ti/csl/src/ip/cpsw/V4/csl_cpswAux.h>
  502. #endif /* SOC_XXXXX */
  503. /**
  504. @}
  505. */
  506. #ifdef __cplusplus
  507. }
  508. #endif
  509. #endif
  510. /**
  511. @}
  512. */