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cris.h

cris.h 2.6 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2004 Hewlett-Packard Development Company, L.P.
    3. 

  3.  *
    4. 

  4.  * Permission is hereby granted, free of charge, to any person obtaining a copy
    5. 

  5.  * of this software and associated documentation files (the "Software"), to deal
    6. 

  6.  * in the Software without restriction, including without limitation the rights
    7. 

  7.  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    8. 

  8.  * copies of the Software, and to permit persons to whom the Software is
    9. 

  9.  * furnished to do so, subject to the following conditions:
    10. 

  10.  *
    11. 

  11.  * The above copyright notice and this permission notice shall be included in
    12. 

  12.  * all copies or substantial portions of the Software.
    13. 

  13.  *
    14. 

  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    15. 

  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    16. 

  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    17. 

  17.  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    18. 

  18.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    19. 

  19.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
    20. 

  20.  * SOFTWARE.
    21. 

  21.  */
    22. 

  22. 

  23. /* FIXME: seems to be untested.         */
    24. 

  24. 

  25. #include "../all_atomic_load_store.h"
    26. 

  26. 

  27. #include "../ordered.h"  /* There are no multiprocessor implementations. */
    28. 

  28. 

  29. #include "../test_and_set_t_is_ao_t.h"
    30. 

  30. 

  31. /*
    32. 

  32.  * The architecture apparently supports an "f" flag which is
    33. 

  33.  * set on preemption.  This essentially gives us load-locked,
    34. 

  34.  * store-conditional primitives, though I'm not quite sure how
    35. 

  35.  * this would work on a hypothetical multiprocessor.  -HB
    36. 

  36.  *
    37. 

  37.  * For details, see
    38. 

  38.  * http://developer.axis.com/doc/hardware/etrax100lx/prog_man/
    39. 

  39.  *      1_architectural_description.pdf
    40. 

  40.  *
    41. 

  41.  * Presumably many other primitives (notably CAS, including the double-
    42. 

  42.  * width versions) could be implemented in this manner, if someone got
    43. 

  43.  * around to it.
    44. 

  44.  */
    45. 

  45. 

  46. AO_INLINE AO_TS_VAL_t
    47. 

  47. AO_test_and_set_full(volatile AO_TS_t *addr) {
    48. 

  48.     /* Ripped from linuxthreads/sysdeps/cris/pt-machine.h */
    49. 

  49.     register unsigned long int ret;
    50. 

  50. 

  51.     /* Note the use of a dummy output of *addr to expose the write.  The
    52. 

  52.        memory barrier is to stop *other* writes being moved past this code.  */
    53. 

  53.       __asm__ __volatile__("clearf\n"
    54. 

  54.                            "0:\n\t"
    55. 

  55.                            "movu.b [%2],%0\n\t"
    56. 

  56.                            "ax\n\t"
    57. 

  57.                            "move.b %3,[%2]\n\t"
    58. 

  58.                            "bwf 0b\n\t"
    59. 

  59.                            "clearf"
    60. 

  60.                            : "=&r" (ret), "=m" (*addr)
    61. 

  61.                            : "r" (addr), "r" ((int) 1), "m" (*addr)
    62. 

  62.                            : "memory");
    63. 

  63.     return ret;
    64. 

  64. }
    65. 

  65. #define AO_HAVE_test_and_set_full
    66.