fsl_pmic.h 2.2 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  4. *
  5. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef __FSL_PMIC_H__
  10. #define __FSL_PMIC_H__
  11. /*
  12. * The registers of different PMIC has the same meaning
  13. * but the bit positions of the fields can differ or
  14. * some fields has a meaning only on some devices.
  15. * You have to check with the internal SPI bitmap
  16. * (see Freescale Documentation) to set the registers
  17. * for the device you are using
  18. */
  19. enum {
  20. REG_INT_STATUS0 = 0,
  21. REG_INT_MASK0,
  22. REG_INT_SENSE0,
  23. REG_INT_STATUS1,
  24. REG_INT_MASK1,
  25. REG_INT_SENSE1,
  26. REG_PU_MODE_S,
  27. REG_IDENTIFICATION,
  28. REG_UNUSED0,
  29. REG_ACC0,
  30. REG_ACC1, /*10 */
  31. REG_UNUSED1,
  32. REG_UNUSED2,
  33. REG_POWER_CTL0,
  34. REG_POWER_CTL1,
  35. REG_POWER_CTL2,
  36. REG_REGEN_ASSIGN,
  37. REG_UNUSED3,
  38. REG_MEM_A,
  39. REG_MEM_B,
  40. REG_RTC_TIME, /*20 */
  41. REG_RTC_ALARM,
  42. REG_RTC_DAY,
  43. REG_RTC_DAY_ALARM,
  44. REG_SW_0,
  45. REG_SW_1,
  46. REG_SW_2,
  47. REG_SW_3,
  48. REG_SW_4,
  49. REG_SW_5,
  50. REG_SETTING_0, /*30 */
  51. REG_SETTING_1,
  52. REG_MODE_0,
  53. REG_MODE_1,
  54. REG_POWER_MISC,
  55. REG_UNUSED4,
  56. REG_UNUSED5,
  57. REG_UNUSED6,
  58. REG_UNUSED7,
  59. REG_UNUSED8,
  60. REG_UNUSED9, /*40 */
  61. REG_UNUSED10,
  62. REG_UNUSED11,
  63. REG_ADC0,
  64. REG_ADC1,
  65. REG_ADC2,
  66. REG_ADC3,
  67. REG_ADC4,
  68. REG_CHARGE,
  69. REG_USB0,
  70. REG_USB1, /*50 */
  71. REG_LED_CTL0,
  72. REG_LED_CTL1,
  73. REG_LED_CTL2,
  74. REG_LED_CTL3,
  75. REG_UNUSED12,
  76. REG_UNUSED13,
  77. REG_TRIM0,
  78. REG_TRIM1,
  79. REG_TEST0,
  80. REG_TEST1, /*60 */
  81. REG_TEST2,
  82. REG_TEST3,
  83. REG_TEST4,
  84. PMIC_NUM_OF_REGS,
  85. };
  86. /* REG_POWER_MISC */
  87. #define GPO1EN (1 << 6)
  88. #define GPO1STBY (1 << 7)
  89. #define GPO2EN (1 << 8)
  90. #define GPO2STBY (1 << 9)
  91. #define GPO3EN (1 << 10)
  92. #define GPO3STBY (1 << 11)
  93. #define GPO4EN (1 << 12)
  94. #define GPO4STBY (1 << 13)
  95. #define PWGT1SPIEN (1 << 15)
  96. #define PWGT2SPIEN (1 << 16)
  97. #define PWUP (1 << 21)
  98. /* Power Control 0 */
  99. #define COINCHEN (1 << 23)
  100. #define BATTDETEN (1 << 19)
  101. /* Interrupt status 1 */
  102. #define RTCRSTI (1 << 7)
  103. /* MC34708 Definitions */
  104. #define SWx_VOLT_MASK_MC34708 0x3F
  105. #define SWx_1_250V_MC34708 0x30
  106. #define SWx_1_300V_MC34708 0x34
  107. #define TIMER_MASK_MC34708 0x300
  108. #define TIMER_4S_MC34708 0x100
  109. #define VUSBSEL_MC34708 (1 << 2)
  110. #define VUSBEN_MC34708 (1 << 3)
  111. #define SWBST_CTRL 31
  112. #define SWBST_AUTO 0x8
  113. #endif