ti_omap3_common.h 2.1 KB

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  1. /*
  2. * ti_omap3_common.h
  3. *
  4. * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. *
  8. * For more details, please see the technical documents listed at
  9. * http://www.ti.com/product/omap3530
  10. * http://www.ti.com/product/omap3630
  11. * http://www.ti.com/product/dm3730
  12. */
  13. #ifndef __CONFIG_TI_OMAP3_COMMON_H__
  14. #define __CONFIG_TI_OMAP3_COMMON_H__
  15. /*
  16. * High Level Configuration Options
  17. */
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/omap.h>
  20. /* Common ARM Erratas */
  21. #define CONFIG_ARM_ERRATA_454179
  22. #define CONFIG_ARM_ERRATA_430973
  23. #define CONFIG_ARM_ERRATA_621766
  24. /* The chip has SDRC controller */
  25. #define CONFIG_SDRC
  26. /* Clock Defines */
  27. #define V_OSCK 26000000 /* Clock output from T2 */
  28. #define V_SCLK (V_OSCK >> 1)
  29. /* NS16550 Configuration */
  30. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  31. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  32. #ifdef CONFIG_SPL_BUILD
  33. # define CONFIG_SYS_NS16550_SERIAL
  34. # define CONFIG_SYS_NS16550_REG_SIZE (-4)
  35. #endif
  36. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
  37. 115200}
  38. /* Select serial console configuration */
  39. #define CONFIG_CONS_INDEX 3
  40. #ifdef CONFIG_SPL_BUILD
  41. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  42. #define CONFIG_SERIAL3 3
  43. #endif
  44. /* Physical Memory Map */
  45. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  46. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  47. /*
  48. * OMAP3 has 12 GP timers, they can be driven by the system clock
  49. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  50. * This rate is divided by a local divisor.
  51. */
  52. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  53. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  54. /* TWL4030 */
  55. #define CONFIG_TWL4030_POWER
  56. /* SPL */
  57. #define CONFIG_SPL_TEXT_BASE 0x40200800
  58. #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
  59. #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
  60. (64 << 20))
  61. #ifdef CONFIG_NAND
  62. #define CONFIG_SPL_NAND_SIMPLE
  63. #define CONFIG_SYS_NAND_BASE 0x30000000
  64. #endif
  65. /* Now bring in the rest of the common code. */
  66. #include <configs/ti_armv7_omap.h>
  67. #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */