rk3288_common.h 3.0 KB

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  1. /*
  2. * (C) Copyright 2015 Google, Inc
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __CONFIG_RK3288_COMMON_H
  7. #define __CONFIG_RK3288_COMMON_H
  8. #include <asm/arch/hardware.h>
  9. #include "rockchip-common.h"
  10. #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  11. #define CONFIG_SYS_NO_FLASH
  12. #define CONFIG_NR_DRAM_BANKS 1
  13. #define CONFIG_ENV_SIZE 0x2000
  14. #define CONFIG_SYS_MAXARGS 16
  15. #define CONFIG_BAUDRATE 115200
  16. #define CONFIG_SYS_MALLOC_LEN (32 << 20)
  17. #define CONFIG_SYS_CBSIZE 1024
  18. #define CONFIG_SYS_THUMB_BUILD
  19. #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
  20. #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
  21. #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
  22. #define CONFIG_SPL_FRAMEWORK
  23. #define CONFIG_SYS_NS16550_MEM32
  24. #define CONFIG_SPL_BOARD_INIT
  25. #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
  26. /* Bootrom will load u-boot binary to 0x0 once return from SPL */
  27. #define CONFIG_SYS_TEXT_BASE 0x00000000
  28. #else
  29. #define CONFIG_SYS_TEXT_BASE 0x00100000
  30. #endif
  31. #define CONFIG_SYS_INIT_SP_ADDR 0x00100000
  32. #define CONFIG_SYS_LOAD_ADDR 0x00800800
  33. #define CONFIG_SPL_STACK 0xff718000
  34. #define CONFIG_SPL_TEXT_BASE 0xff704004
  35. /* MMC/SD IP block */
  36. #define CONFIG_GENERIC_MMC
  37. #define CONFIG_DWMMC
  38. #define CONFIG_BOUNCE_BUFFER
  39. #define CONFIG_FAT_WRITE
  40. #define CONFIG_PARTITION_UUIDS
  41. #define CONFIG_CMD_PART
  42. /* RAW SD card / eMMC locations. */
  43. #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
  44. /* FAT sd card locations. */
  45. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  46. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  47. #define CONFIG_SYS_SDRAM_BASE 0
  48. #define CONFIG_NR_DRAM_BANKS 1
  49. #define SDRAM_BANK_SIZE (2UL << 30)
  50. #define CONFIG_SPI_FLASH
  51. #define CONFIG_SPI
  52. #define CONFIG_SF_DEFAULT_SPEED 20000000
  53. #ifndef CONFIG_SPL_BUILD
  54. /* usb otg */
  55. #define CONFIG_USB_GADGET
  56. #define CONFIG_USB_GADGET_DUALSPEED
  57. #define CONFIG_USB_GADGET_DWC2_OTG
  58. #define CONFIG_ROCKCHIP_USB2_PHY
  59. #define CONFIG_USB_GADGET_VBUS_DRAW 0
  60. /* fastboot */
  61. #define CONFIG_CMD_FASTBOOT
  62. #define CONFIG_USB_FUNCTION_FASTBOOT
  63. #define CONFIG_FASTBOOT_FLASH
  64. #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */
  65. #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
  66. #define CONFIG_FASTBOOT_BUF_SIZE 0x08000000
  67. /* usb mass storage */
  68. #define CONFIG_USB_FUNCTION_MASS_STORAGE
  69. #define CONFIG_CMD_USB_MASS_STORAGE
  70. #define CONFIG_USB_GADGET_DOWNLOAD
  71. #define CONFIG_G_DNL_MANUFACTURER "Rockchip"
  72. #define CONFIG_G_DNL_VENDOR_NUM 0x2207
  73. #define CONFIG_G_DNL_PRODUCT_NUM 0x320a
  74. #define ENV_MEM_LAYOUT_SETTINGS \
  75. "scriptaddr=0x00000000\0" \
  76. "pxefile_addr_r=0x00100000\0" \
  77. "fdt_addr_r=0x01f00000\0" \
  78. "kernel_addr_r=0x02000000\0" \
  79. "ramdisk_addr_r=0x04000000\0"
  80. #include <config_distro_bootcmd.h>
  81. /* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so
  82. * limit the fdt reallocation to that */
  83. #define CONFIG_EXTRA_ENV_SETTINGS \
  84. "fdt_high=0x0fffffff\0" \
  85. "initrd_high=0x0fffffff\0" \
  86. "partitions=" PARTS_DEFAULT \
  87. ENV_MEM_LAYOUT_SETTINGS \
  88. ROCKCHIP_DEVICE_SETTINGS \
  89. BOOTENV
  90. #endif
  91. #define CONFIG_BOARD_LATE_INIT
  92. #define CONFIG_PREBOOT
  93. #endif