bur_am335x_common.h 4.2 KB

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  1. /*
  2. * bur_am335x_common.h
  3. *
  4. * common parts used by B&R AM335x based boards
  5. *
  6. * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
  7. * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #ifndef __BUR_AM335X_COMMON_H__
  12. #define __BUR_AM335X_COMMON_H__
  13. /* ------------------------------------------------------------------------- */
  14. #define CONFIG_AM33XX
  15. #define CONFIG_OMAP
  16. #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
  17. /* Timer information */
  18. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  19. #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
  20. #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */
  21. #define CONFIG_POWER_TPS65217
  22. #define CONFIG_SYS_NO_FLASH /* have no NOR-flash */
  23. #include <asm/arch/omap.h>
  24. /* NS16550 Configuration */
  25. #define CONFIG_SYS_NS16550_SERIAL
  26. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  27. #define CONFIG_SYS_NS16550_CLK 48000000
  28. #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
  29. #define CONFIG_BAUDRATE 115200
  30. /* Network defines */
  31. #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
  32. #define CONFIG_MII /* Required in net/eth.c */
  33. #define CONFIG_PHYLIB
  34. #define CONFIG_PHY_NATSEMI
  35. /*
  36. * SPL related defines. The Public RAM memory map the ROM defines the
  37. * area between 0x402F0400 and 0x4030B800 as a download area and
  38. * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
  39. * supports X-MODEM loading via UART, and we leverage this and then use
  40. * Y-MODEM to load u-boot.img, when booted over UART. We must also include
  41. * the scratch space that U-Boot uses in SRAM.
  42. */
  43. #define CONFIG_SPL_TEXT_BASE 0x402F0400
  44. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  45. CONFIG_SPL_TEXT_BASE)
  46. /*
  47. * Since SPL did pll and ddr initialization for us,
  48. * we don't need to do it twice.
  49. */
  50. #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
  51. #define CONFIG_SKIP_LOWLEVEL_INIT
  52. #endif /* !CONFIG_SPL_BUILD, ... */
  53. /*
  54. * Our DDR memory always starts at 0x80000000 and U-Boot shall have
  55. * relocated itself to higher in memory by the time this value is used.
  56. */
  57. #define CONFIG_SYS_LOAD_ADDR 0x80000000
  58. /*
  59. * ----------------------------------------------------------------------------
  60. * DDR information. We say (for simplicity) that we have 1 bank,
  61. * always, even when we have more. We always start at 0x80000000,
  62. * and we place the initial stack pointer in our SRAM.
  63. */
  64. #define CONFIG_NR_DRAM_BANKS 1
  65. #define CONFIG_SYS_SDRAM_BASE 0x80000000
  66. #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
  67. GENERATED_GBL_DATA_SIZE)
  68. /* I2C */
  69. #define CONFIG_SYS_I2C
  70. #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
  71. #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
  72. #define CONFIG_SYS_I2C_OMAP24XX
  73. /* GPIO */
  74. #define CONFIG_OMAP_GPIO
  75. /*
  76. * Our platforms make use of SPL to initalize the hardware (primarily
  77. * memory) enough for full U-Boot to be loaded. We also support Falcon
  78. * Mode so that the Linux kernel can be booted directly from SPL
  79. * instead, if desired. We make use of the general SPL framework found
  80. * under common/spl/. Given our generally common memory map, we set a
  81. * number of related defaults and sizes here.
  82. */
  83. #define CONFIG_SPL_FRAMEWORK
  84. /*
  85. * Place the image at the start of the ROM defined image space.
  86. * We limit our size to the ROM-defined downloaded image area, and use the
  87. * rest of the space for stack. We load U-Boot itself into memory at
  88. * 0x80800000 for legacy reasons (to not conflict with older SPLs). We
  89. * have our BSS be placed 1MiB after this, to allow for the default
  90. * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
  91. * We have the SPL malloc pool at the end of the BSS area.
  92. *
  93. * ----------------------------------------------------------------------------
  94. */
  95. #undef CONFIG_SYS_TEXT_BASE
  96. #define CONFIG_SYS_TEXT_BASE 0x80800000
  97. #define CONFIG_SPL_BSS_START_ADDR 0x80A00000
  98. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  99. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  100. CONFIG_SPL_BSS_MAX_SIZE)
  101. #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
  102. /* General parts of the framework, required. */
  103. #define CONFIG_SPL_BOARD_INIT
  104. #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
  105. #endif /* ! __BUR_AM335X_COMMON_H__ */