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u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04
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armcoremodule.h

armcoremodule.h 2.5 KB
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  1. /*
    2. 

  2.  * (C) Copyright 2005
    3. 

  3.  * ARM Ltd.
    4. 

  4.  * Peter Pearse, <Peter.Pearse@arm.com>
    5. 

  5.  * Configuration for ARM Core Modules.
    6. 

  6.  * No standalonw port yet available
    7. 

  7.  * - this file is included by both integratorap.h & integratorcp.h
    8. 

  8.  *
    9. 

  9.  * SPDX-License-Identifier:	GPL-2.0+
    10. 

  10.  */
    11. 

  11. 

  12. #ifndef __ARMCOREMODULE_H
    13. 

  13. #define __ARMCOREMODULE_H
    14. 

  14. 

  15. #define CM_BASE			0x10000000
    16. 

  16. 

  17. /* CM registers common to all CMs */
    18. 

  18. /* Note that observed values after reboot into the ARM Boot Monitor
    19. 

  19.    have been used as defaults, rather than the POR values */
    20. 

  20. #define OS_CTRL			0x0000000C
    21. 

  21. #define CMMASK_REMAP		0x00000005	/* set remap & led           */
    22. 

  22. #define CMMASK_RESET		0x00000008
    23. 

  23. #define OS_LOCK			0x00000014
    24. 

  24. #define CMVAL_LOCK1		0x0000A000	/* locking value             */
    25. 

  25. #define CMVAL_LOCK2		0x0000005F	/* locking value             */
    26. 

  26. #define CMVAL_UNLOCK		0x00000000	/* any value != CM_LOCKVAL   */
    27. 

  27. #define OS_SDRAM		0x00000020
    28. 

  28. #define OS_INIT			0x00000024
    29. 

  29. #define CMMASK_MAP_SIMPLE	0xFFFDFFFF	/* simple mapping */
    30. 

  30. #define CMMASK_TCRAM_DISABLE	0xFFFEFFFF	/* TCRAM disabled */
    31. 

  31. #define CMMASK_LOWVEC		0x00000000	/* vectors @ 0x00000000 */
    32. 

  32. #define CMMASK_LE		0xFFFFFFF7	/* little endian */
    33. 

  33. #define CMMASK_CMxx6_COMMON	0x00000013      /* Common value for CMxx6 */
    34. 

  34. 						/* - observed reset value of */
    35. 

  35. 						/*   CM926EJ-S */
    36. 

  36. 						/*   CM1136-EJ-S */
    37. 

  37. 

  38. #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
    39. 

  39. #define CMMASK_INIT_102	0x00000300		/* see CM102xx ref manual */
    40. 

  40. 						/* - PLL test clock bypassed */
    41. 

  41. 						/* - bus clock ratio 2 */
    42. 

  42. 						/* - little endian */
    43. 

  43. 						/* - vectors at zero */
    44. 

  44. #endif /* CM1022xx */
    45. 

  45. 

  46. /* Determine CM characteristics */
    47. 

  47. 

  48. #undef	CONFIG_CM_MULTIPLE_SSRAM
    49. 

  49. #undef	CONFIG_CM_SPD_DETECT
    50. 

  50. #undef	CONFIG_CM_REMAP
    51. 

  51. #undef	CONFIG_CM_INIT
    52. 

  52. #undef	CONFIG_CM_TCRAM
    53. 

  53. 

  54. #if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
    55. 

  55. #define	CONFIG_CM_MULTIPLE_SSRAM	/* CM has multiple SSRAM mapping */
    56. 

  56. #endif
    57. 

  57. 

  58. /* Excalibur core module has reduced functionality */
    59. 

  59. #ifndef	CONFIG_CM922T_XA10
    60. 

  60. #define CONFIG_CM_SPD_DETECT			/* CM supports SPD query      */
    61. 

  61. #define OS_SPD			0x00000100	/* Address of SPD data        */
    62. 

  62. #define CONFIG_CM_REMAP				/* CM supports remapping      */
    63. 

  63. #define CONFIG_CM_INIT				/* CM has initialization reg  */
    64. 

  64. #endif	/* NOT EXCALIBUR */
    65. 

  65. 

  66. #if defined(CONFIG_CM926EJ_S)   || defined (CONFIG_CM946E_S)	|| \
    67. 

  67.     defined(CONFIG_CM966E_S)    || defined (CONFIG_CM1026EJ_S)	|| \
    68. 

  68.     defined(CONFIG_CM1136JF_S)
    69. 

  69. #define CONFIG_CM_TCRAM				/* CM has TCRAM  */
    70. 

  70. #endif
    71. 

  71. 

  72. #ifdef CONFIG_CM_SPD_DETECT
    73. 

  73. #define OS_SPD		0x00000100	/* The SDRAM SPD data is copied here */
    74. 

  74. #endif
    75. 

  75. 

  76. #endif /* __ARMCOREMODULE_H */
    77.