Home Explore Help
Sign In
8516
/
Test
1
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Branch: master
Branches Tags
Test
/
board-support
/
u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04
/
drivers
/
usb
/
musb
/
blackfin_usb.h

blackfin_usb.h 1.7 KB
Permalink History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899 
  1. /*
    2. 

  2.  * Blackfin MUSB HCD (Host Controller Driver) for u-boot
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2008-2009 Analog Devices Inc.
    5. 

  5.  *
    6. 

  6.  * Licensed under the GPL-2 or later.
    7. 

  7.  */
    8. 

  8. 

  9. #ifndef __BLACKFIN_USB_H__
    10. 

  10. #define __BLACKFIN_USB_H__
    11. 

  11. 

  12. #include <linux/types.h>
    13. 

  13. 

  14. /* Every register is 32bit aligned, but only 16bits in size */
    15. 

  15. #define ureg(name) u16 name; u16 __pad_##name;
    16. 

  16. 

  17. #define musb_regs musb_regs
    18. 

  18. struct musb_regs {
    19. 

  19. 	/* common registers */
    20. 

  20. 	ureg(faddr)
    21. 

  21. 	ureg(power)
    22. 

  22. 	ureg(intrtx)
    23. 

  23. 	ureg(intrrx)
    24. 

  24. 	ureg(intrtxe)
    25. 

  25. 	ureg(intrrxe)
    26. 

  26. 	ureg(intrusb)
    27. 

  27. 	ureg(intrusbe)
    28. 

  28. 	ureg(frame)
    29. 

  29. 	ureg(index)
    30. 

  30. 	ureg(testmode)
    31. 

  31. 	ureg(globintr)
    32. 

  32. 	ureg(global_ctl)
    33. 

  33. 	u32	reserved0[3];
    34. 

  34. 	/* indexed registers */
    35. 

  35. 	ureg(txmaxp)
    36. 

  36. 	ureg(txcsr)
    37. 

  37. 	ureg(rxmaxp)
    38. 

  38. 	ureg(rxcsr)
    39. 

  39. 	ureg(rxcount)
    40. 

  40. 	ureg(txtype)
    41. 

  41. 	ureg(txinterval)
    42. 

  42. 	ureg(rxtype)
    43. 

  43. 	ureg(rxinterval)
    44. 

  44. 	u32	reserved1;
    45. 

  45. 	ureg(txcount)
    46. 

  46. 	u32	reserved2[5];
    47. 

  47. 	/* fifo */
    48. 

  48. 	u16	fifox[32];
    49. 

  49. 	/* OTG, dynamic FIFO, version & vendor registers */
    50. 

  50. 	u32	reserved3[16];
    51. 

  51. 	ureg(devctl)
    52. 

  52. 	ureg(vbus_irq)
    53. 

  53. 	ureg(vbus_mask)
    54. 

  54. 	u32 reserved4[15];
    55. 

  55. 	ureg(linkinfo)
    56. 

  56. 	ureg(vplen)
    57. 

  57. 	ureg(hseof1)
    58. 

  58. 	ureg(fseof1)
    59. 

  59. 	ureg(lseof1)
    60. 

  60. 	u32 reserved5[41];
    61. 

  61. 	/* target address registers */
    62. 

  62. 	struct musb_tar_regs {
    63. 

  63. 		ureg(txmaxp)
    64. 

  64. 		ureg(txcsr)
    65. 

  65. 		ureg(rxmaxp)
    66. 

  66. 		ureg(rxcsr)
    67. 

  67. 		ureg(rxcount)
    68. 

  68. 		ureg(txtype)
    69. 

  69. 		ureg(txinternal)
    70. 

  70. 		ureg(rxtype)
    71. 

  71. 		ureg(rxinternal)
    72. 

  72. 		u32	reserved6;
    73. 

  73. 		ureg(txcount)
    74. 

  74. 		u32 reserved7[5];
    75. 

  75. 	} tar[8];
    76. 

  76. } __attribute__((packed));
    77. 

  77. 

  78. struct bfin_musb_dma_regs {
    79. 

  79. 	ureg(interrupt);
    80. 

  80. 	ureg(control);
    81. 

  81. 	ureg(addr_low);
    82. 

  82. 	ureg(addr_high);
    83. 

  83. 	ureg(count_low);
    84. 

  84. 	ureg(count_high);
    85. 

  85. 	u32 reserved0[2];
    86. 

  86. };
    87. 

  87. 

  88. #undef ureg
    89. 

  89. 

  90. /* EP5-EP7 are the only ones with 1024 byte FIFOs which BULK really needs */
    91. 

  91. #define MUSB_BULK_EP 5
    92. 

  92. 

  93. /* Blackfin FIFO's are static */
    94. 

  94. #define MUSB_NO_DYNAMIC_FIFO
    95. 

  95. 

  96. /* No HUB support :( */
    97. 

  97. #define MUSB_NO_MULTIPOINT
    98. 

  98. 

  99. #endif
    100.