utmi-armada100.c 1.9 KB

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  1. /*
  2. * (C) Copyright 2012
  3. * eInfochips Ltd. <www.einfochips.com>
  4. * Written-by: Ajay Bhargav <contact@8051projects.net>
  5. *
  6. * (C) Copyright 2009
  7. * Marvell Semiconductor <www.marvell.com>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <common.h>
  12. #include <asm/io.h>
  13. #include <usb.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/armada100.h>
  16. #include <asm/arch/utmi-armada100.h>
  17. static int utmi_phy_init(void)
  18. {
  19. struct armd1usb_phy_reg *phy_regs =
  20. (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
  21. int timeout;
  22. setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
  23. udelay(1000);
  24. setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
  25. clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
  26. setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
  27. setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
  28. /* Calibrate pll */
  29. timeout = 10000;
  30. while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
  31. ;
  32. if (!timeout)
  33. return -1;
  34. udelay(200);
  35. setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
  36. udelay(400);
  37. clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
  38. udelay(200);
  39. setbits_le32(&phy_regs->utmi_tx, RCAL_START);
  40. udelay(400);
  41. clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
  42. timeout = 10000;
  43. while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
  44. ;
  45. if (!timeout)
  46. return -1;
  47. return 0;
  48. }
  49. /*
  50. * Initialize USB host controller's UTMI Physical interface
  51. */
  52. int utmi_init(void)
  53. {
  54. struct armd1mpmu_registers *mpmu_regs =
  55. (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
  56. struct armd1apmu_registers *apmu_regs =
  57. (struct armd1apmu_registers *)ARMD1_APMU_BASE;
  58. /* Turn on 26Mhz ref clock for UTMI PLL */
  59. setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
  60. /* USB Clock reset */
  61. writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
  62. writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
  63. /* Initialize UTMI transceiver */
  64. return utmi_phy_init();
  65. }