ohci-s3c24xx.c 43 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
  3. *
  4. * (C) Copyright 2003
  5. * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
  6. *
  7. * Note: Much of this code has been derived from Linux 2.4
  8. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  9. * (C) Copyright 2000-2002 David Brownell
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. /*
  14. * IMPORTANT NOTES
  15. * 1 - this driver is intended for use with USB Mass Storage Devices
  16. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  17. */
  18. #include <common.h>
  19. /* #include <pci.h> no PCI on the S3C24X0 */
  20. #if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
  21. #include <asm/arch/s3c24x0_cpu.h>
  22. #include <asm/io.h>
  23. #include <malloc.h>
  24. #include <usb.h>
  25. #include "ohci-s3c24xx.h"
  26. #define OHCI_USE_NPS /* force NoPowerSwitching mode */
  27. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  28. /* For initializing controller (mask in an HCFS mode too) */
  29. #define OHCI_CONTROL_INIT \
  30. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  31. #undef DEBUG
  32. #ifdef DEBUG
  33. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  34. #else
  35. #define dbg(format, arg...) do {} while(0)
  36. #endif /* DEBUG */
  37. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  38. #undef SHOW_INFO
  39. #ifdef SHOW_INFO
  40. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  41. #else
  42. #define info(format, arg...) do {} while(0)
  43. #endif
  44. #define m16_swap(x) swap_16(x)
  45. #define m32_swap(x) swap_32(x)
  46. /* global struct ohci */
  47. static struct ohci gohci;
  48. /* this must be aligned to a 256 byte boundary */
  49. struct ohci_hcca ghcca[1];
  50. /* a pointer to the aligned storage */
  51. struct ohci_hcca *phcca;
  52. /* this allocates EDs for all possible endpoints */
  53. struct ohci_device ohci_dev;
  54. /* urb_priv */
  55. struct urb_priv urb_priv;
  56. /* RHSC flag */
  57. int got_rhsc;
  58. /* device which was disconnected */
  59. struct usb_device *devgone;
  60. /* flag guarding URB transation */
  61. int urb_finished = 0;
  62. /*-------------------------------------------------------------------------*/
  63. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  64. * The erratum (#4) description is incorrect. AMD's workaround waits
  65. * till some bits (mostly reserved) are clear; ok for all revs.
  66. */
  67. #define OHCI_QUIRK_AMD756 0xabcd
  68. #define read_roothub(hc, register, mask) ({ \
  69. u32 temp = readl (&hc->regs->roothub.register); \
  70. if (hc->flags & OHCI_QUIRK_AMD756) \
  71. while (temp & mask) \
  72. temp = readl (&hc->regs->roothub.register); \
  73. temp; })
  74. static u32 roothub_a(struct ohci *hc)
  75. {
  76. return read_roothub(hc, a, 0xfc0fe000);
  77. }
  78. static inline u32 roothub_b(struct ohci *hc)
  79. {
  80. return readl(&hc->regs->roothub.b);
  81. }
  82. static inline u32 roothub_status(struct ohci *hc)
  83. {
  84. return readl(&hc->regs->roothub.status);
  85. }
  86. static u32 roothub_portstatus(struct ohci *hc, int i)
  87. {
  88. return read_roothub(hc, portstatus[i], 0xffe0fce0);
  89. }
  90. /* forward declaration */
  91. static int hc_interrupt(void);
  92. static void td_submit_job(struct usb_device *dev, unsigned long pipe,
  93. void *buffer, int transfer_len,
  94. struct devrequest *setup, struct urb_priv *urb,
  95. int interval);
  96. /*-------------------------------------------------------------------------*
  97. * URB support functions
  98. *-------------------------------------------------------------------------*/
  99. /* free HCD-private data associated with this URB */
  100. static void urb_free_priv(struct urb_priv *urb)
  101. {
  102. int i;
  103. int last;
  104. struct td *td;
  105. last = urb->length - 1;
  106. if (last >= 0) {
  107. for (i = 0; i <= last; i++) {
  108. td = urb->td[i];
  109. if (td) {
  110. td->usb_dev = NULL;
  111. urb->td[i] = NULL;
  112. }
  113. }
  114. }
  115. }
  116. /*-------------------------------------------------------------------------*/
  117. #ifdef DEBUG
  118. static int sohci_get_current_frame_number(struct usb_device *dev);
  119. /* debug| print the main components of an URB
  120. * small: 0) header + data packets 1) just header */
  121. static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
  122. int transfer_len, struct devrequest *setup, char *str,
  123. int small)
  124. {
  125. struct urb_priv *purb = &urb_priv;
  126. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  127. str,
  128. sohci_get_current_frame_number(dev),
  129. usb_pipedevice(pipe),
  130. usb_pipeendpoint(pipe),
  131. usb_pipeout(pipe) ? 'O' : 'I',
  132. usb_pipetype(pipe) < 2 ?
  133. (usb_pipeint(pipe) ? "INTR" : "ISOC") :
  134. (usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
  135. purb->actual_length, transfer_len, dev->status);
  136. #ifdef OHCI_VERBOSE_DEBUG
  137. if (!small) {
  138. int i, len;
  139. if (usb_pipecontrol(pipe)) {
  140. printf(__FILE__ ": cmd(8):");
  141. for (i = 0; i < 8; i++)
  142. printf(" %02x", ((__u8 *) setup)[i]);
  143. printf("\n");
  144. }
  145. if (transfer_len > 0 && buffer) {
  146. printf(__FILE__ ": data(%d/%d):",
  147. purb->actual_length, transfer_len);
  148. len = usb_pipeout(pipe) ?
  149. transfer_len : purb->actual_length;
  150. for (i = 0; i < 16 && i < len; i++)
  151. printf(" %02x", ((__u8 *) buffer)[i]);
  152. printf("%s\n", i < len ? "..." : "");
  153. }
  154. }
  155. #endif
  156. }
  157. /* just for debugging; prints non-empty branches of the
  158. int ed tree inclusive iso eds*/
  159. void ep_print_int_eds(struct ohci *ohci, char *str)
  160. {
  161. int i, j;
  162. __u32 *ed_p;
  163. for (i = 0; i < 32; i++) {
  164. j = 5;
  165. ed_p = &(ohci->hcca->int_table[i]);
  166. if (*ed_p == 0)
  167. continue;
  168. printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  169. while (*ed_p != 0 && j--) {
  170. struct ed *ed = (struct ed *) m32_swap(ed_p);
  171. printf(" ed: %4x;", ed->hwINFO);
  172. ed_p = &ed->hwNextED;
  173. }
  174. printf("\n");
  175. }
  176. }
  177. static void ohci_dump_intr_mask(char *label, __u32 mask)
  178. {
  179. dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  180. label,
  181. mask,
  182. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  183. (mask & OHCI_INTR_OC) ? " OC" : "",
  184. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  185. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  186. (mask & OHCI_INTR_UE) ? " UE" : "",
  187. (mask & OHCI_INTR_RD) ? " RD" : "",
  188. (mask & OHCI_INTR_SF) ? " SF" : "",
  189. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  190. (mask & OHCI_INTR_SO) ? " SO" : "");
  191. }
  192. static void maybe_print_eds(char *label, __u32 value)
  193. {
  194. struct ed *edp = (struct ed *) value;
  195. if (value) {
  196. dbg("%s %08x", label, value);
  197. dbg("%08x", edp->hwINFO);
  198. dbg("%08x", edp->hwTailP);
  199. dbg("%08x", edp->hwHeadP);
  200. dbg("%08x", edp->hwNextED);
  201. }
  202. }
  203. static char *hcfs2string(int state)
  204. {
  205. switch (state) {
  206. case OHCI_USB_RESET:
  207. return "reset";
  208. case OHCI_USB_RESUME:
  209. return "resume";
  210. case OHCI_USB_OPER:
  211. return "operational";
  212. case OHCI_USB_SUSPEND:
  213. return "suspend";
  214. }
  215. return "?";
  216. }
  217. /* dump control and status registers */
  218. static void ohci_dump_status(struct ohci *controller)
  219. {
  220. struct ohci_regs *regs = controller->regs;
  221. __u32 temp;
  222. temp = readl(&regs->revision) & 0xff;
  223. if (temp != 0x10)
  224. dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
  225. temp = readl(&regs->control);
  226. dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  227. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  228. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  229. (temp & OHCI_CTRL_IR) ? " IR" : "",
  230. hcfs2string(temp & OHCI_CTRL_HCFS),
  231. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  232. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  233. (temp & OHCI_CTRL_IE) ? " IE" : "",
  234. (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
  235. temp = readl(&regs->cmdstatus);
  236. dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  237. (temp & OHCI_SOC) >> 16,
  238. (temp & OHCI_OCR) ? " OCR" : "",
  239. (temp & OHCI_BLF) ? " BLF" : "",
  240. (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
  241. ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
  242. ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
  243. maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
  244. maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
  245. maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
  246. maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
  247. maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
  248. maybe_print_eds("donehead", readl(&regs->donehead));
  249. }
  250. static void ohci_dump_roothub(struct ohci *controller, int verbose)
  251. {
  252. __u32 temp, ndp, i;
  253. temp = roothub_a(controller);
  254. ndp = (temp & RH_A_NDP);
  255. if (verbose) {
  256. dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  257. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  258. (temp & RH_A_NOCP) ? " NOCP" : "",
  259. (temp & RH_A_OCPM) ? " OCPM" : "",
  260. (temp & RH_A_DT) ? " DT" : "",
  261. (temp & RH_A_NPS) ? " NPS" : "",
  262. (temp & RH_A_PSM) ? " PSM" : "", ndp);
  263. temp = roothub_b(controller);
  264. dbg("roothub.b: %08x PPCM=%04x DR=%04x",
  265. temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
  266. );
  267. temp = roothub_status(controller);
  268. dbg("roothub.status: %08x%s%s%s%s%s%s",
  269. temp,
  270. (temp & RH_HS_CRWE) ? " CRWE" : "",
  271. (temp & RH_HS_OCIC) ? " OCIC" : "",
  272. (temp & RH_HS_LPSC) ? " LPSC" : "",
  273. (temp & RH_HS_DRWE) ? " DRWE" : "",
  274. (temp & RH_HS_OCI) ? " OCI" : "",
  275. (temp & RH_HS_LPS) ? " LPS" : "");
  276. }
  277. for (i = 0; i < ndp; i++) {
  278. temp = roothub_portstatus(controller, i);
  279. dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  280. i,
  281. temp,
  282. (temp & RH_PS_PRSC) ? " PRSC" : "",
  283. (temp & RH_PS_OCIC) ? " OCIC" : "",
  284. (temp & RH_PS_PSSC) ? " PSSC" : "",
  285. (temp & RH_PS_PESC) ? " PESC" : "",
  286. (temp & RH_PS_CSC) ? " CSC" : "",
  287. (temp & RH_PS_LSDA) ? " LSDA" : "",
  288. (temp & RH_PS_PPS) ? " PPS" : "",
  289. (temp & RH_PS_PRS) ? " PRS" : "",
  290. (temp & RH_PS_POCI) ? " POCI" : "",
  291. (temp & RH_PS_PSS) ? " PSS" : "",
  292. (temp & RH_PS_PES) ? " PES" : "",
  293. (temp & RH_PS_CCS) ? " CCS" : "");
  294. }
  295. }
  296. static void ohci_dump(struct ohci *controller, int verbose)
  297. {
  298. dbg("OHCI controller usb-%s state", controller->slot_name);
  299. /* dumps some of the state we know about */
  300. ohci_dump_status(controller);
  301. if (verbose)
  302. ep_print_int_eds(controller, "hcca");
  303. dbg("hcca frame #%04x", controller->hcca->frame_no);
  304. ohci_dump_roothub(controller, 1);
  305. }
  306. #endif /* DEBUG */
  307. /*-------------------------------------------------------------------------*
  308. * Interface functions (URB)
  309. *-------------------------------------------------------------------------*/
  310. /* get a transfer request */
  311. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  312. int transfer_len, struct devrequest *setup, int interval)
  313. {
  314. struct ohci *ohci;
  315. struct ed *ed;
  316. struct urb_priv *purb_priv;
  317. int i, size = 0;
  318. ohci = &gohci;
  319. /* when controller's hung, permit only roothub cleanup attempts
  320. * such as powering down ports */
  321. if (ohci->disabled) {
  322. err("sohci_submit_job: EPIPE");
  323. return -1;
  324. }
  325. /* if we have an unfinished URB from previous transaction let's
  326. * fail and scream as quickly as possible so as not to corrupt
  327. * further communication */
  328. if (!urb_finished) {
  329. err("sohci_submit_job: URB NOT FINISHED");
  330. return -1;
  331. }
  332. /* we're about to begin a new transaction here
  333. so mark the URB unfinished */
  334. urb_finished = 0;
  335. /* every endpoint has a ed, locate and fill it */
  336. ed = ep_add_ed(dev, pipe);
  337. if (!ed) {
  338. err("sohci_submit_job: ENOMEM");
  339. return -1;
  340. }
  341. /* for the private part of the URB we need the number of TDs (size) */
  342. switch (usb_pipetype(pipe)) {
  343. case PIPE_BULK:
  344. /* one TD for every 4096 Byte */
  345. size = (transfer_len - 1) / 4096 + 1;
  346. break;
  347. case PIPE_CONTROL:
  348. /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  349. size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
  350. break;
  351. }
  352. if (size >= (N_URB_TD - 1)) {
  353. err("need %d TDs, only have %d", size, N_URB_TD);
  354. return -1;
  355. }
  356. purb_priv = &urb_priv;
  357. purb_priv->pipe = pipe;
  358. /* fill the private part of the URB */
  359. purb_priv->length = size;
  360. purb_priv->ed = ed;
  361. purb_priv->actual_length = 0;
  362. /* allocate the TDs */
  363. /* note that td[0] was allocated in ep_add_ed */
  364. for (i = 0; i < size; i++) {
  365. purb_priv->td[i] = td_alloc(dev);
  366. if (!purb_priv->td[i]) {
  367. purb_priv->length = i;
  368. urb_free_priv(purb_priv);
  369. err("sohci_submit_job: ENOMEM");
  370. return -1;
  371. }
  372. }
  373. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  374. urb_free_priv(purb_priv);
  375. err("sohci_submit_job: EINVAL");
  376. return -1;
  377. }
  378. /* link the ed into a chain if is not already */
  379. if (ed->state != ED_OPER)
  380. ep_link(ohci, ed);
  381. /* fill the TDs and link it to the ed */
  382. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
  383. interval);
  384. return 0;
  385. }
  386. /*-------------------------------------------------------------------------*/
  387. #ifdef DEBUG
  388. /* tell us the current USB frame number */
  389. static int sohci_get_current_frame_number(struct usb_device *usb_dev)
  390. {
  391. struct ohci *ohci = &gohci;
  392. return m16_swap(ohci->hcca->frame_no);
  393. }
  394. #endif
  395. /*-------------------------------------------------------------------------*
  396. * ED handling functions
  397. *-------------------------------------------------------------------------*/
  398. /* link an ed into one of the HC chains */
  399. static int ep_link(struct ohci *ohci, struct ed *edi)
  400. {
  401. struct ed *ed = edi;
  402. ed->state = ED_OPER;
  403. switch (ed->type) {
  404. case PIPE_CONTROL:
  405. ed->hwNextED = 0;
  406. if (ohci->ed_controltail == NULL) {
  407. writel((u32)ed, &ohci->regs->ed_controlhead);
  408. } else {
  409. ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
  410. }
  411. ed->ed_prev = ohci->ed_controltail;
  412. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  413. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  414. ohci->hc_control |= OHCI_CTRL_CLE;
  415. writel(ohci->hc_control, &ohci->regs->control);
  416. }
  417. ohci->ed_controltail = edi;
  418. break;
  419. case PIPE_BULK:
  420. ed->hwNextED = 0;
  421. if (ohci->ed_bulktail == NULL) {
  422. writel((u32)ed, &ohci->regs->ed_bulkhead);
  423. } else {
  424. ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
  425. }
  426. ed->ed_prev = ohci->ed_bulktail;
  427. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  428. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  429. ohci->hc_control |= OHCI_CTRL_BLE;
  430. writel(ohci->hc_control, &ohci->regs->control);
  431. }
  432. ohci->ed_bulktail = edi;
  433. break;
  434. }
  435. return 0;
  436. }
  437. /*-------------------------------------------------------------------------*/
  438. /* unlink an ed from one of the HC chains.
  439. * just the link to the ed is unlinked.
  440. * the link from the ed still points to another operational ed or 0
  441. * so the HC can eventually finish the processing of the unlinked ed */
  442. static int ep_unlink(struct ohci *ohci, struct ed *ed)
  443. {
  444. struct ed *next;
  445. ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
  446. switch (ed->type) {
  447. case PIPE_CONTROL:
  448. if (ed->ed_prev == NULL) {
  449. if (!ed->hwNextED) {
  450. ohci->hc_control &= ~OHCI_CTRL_CLE;
  451. writel(ohci->hc_control, &ohci->regs->control);
  452. }
  453. writel(m32_swap(*((__u32 *) &ed->hwNextED)),
  454. &ohci->regs->ed_controlhead);
  455. } else {
  456. ed->ed_prev->hwNextED = ed->hwNextED;
  457. }
  458. if (ohci->ed_controltail == ed) {
  459. ohci->ed_controltail = ed->ed_prev;
  460. } else {
  461. next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
  462. next->ed_prev = ed->ed_prev;
  463. }
  464. break;
  465. case PIPE_BULK:
  466. if (ed->ed_prev == NULL) {
  467. if (!ed->hwNextED) {
  468. ohci->hc_control &= ~OHCI_CTRL_BLE;
  469. writel(ohci->hc_control, &ohci->regs->control);
  470. }
  471. writel(m32_swap(*((__u32 *) &ed->hwNextED)),
  472. &ohci->regs->ed_bulkhead);
  473. } else {
  474. ed->ed_prev->hwNextED = ed->hwNextED;
  475. }
  476. if (ohci->ed_bulktail == ed) {
  477. ohci->ed_bulktail = ed->ed_prev;
  478. } else {
  479. next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
  480. next->ed_prev = ed->ed_prev;
  481. }
  482. break;
  483. }
  484. ed->state = ED_UNLINK;
  485. return 0;
  486. }
  487. /*-------------------------------------------------------------------------*/
  488. /* add/reinit an endpoint; this should be done once at the usb_set_configuration
  489. * command, but the USB stack is a little bit stateless so we do it at every
  490. * transaction. If the state of the ed is ED_NEW then a dummy td is added and
  491. * the state is changed to ED_UNLINK. In all other cases the state is left
  492. * unchanged. The ed info fields are setted anyway even though most of them
  493. * should not change */
  494. static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
  495. {
  496. struct td *td;
  497. struct ed *ed_ret;
  498. struct ed *ed;
  499. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
  500. (usb_pipecontrol(pipe) ? 0 :
  501. usb_pipeout(pipe))];
  502. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  503. err("ep_add_ed: pending delete");
  504. /* pending delete request */
  505. return NULL;
  506. }
  507. if (ed->state == ED_NEW) {
  508. ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */
  509. /* dummy td; end of td list for ed */
  510. td = td_alloc(usb_dev);
  511. ed->hwTailP = (__u32) m32_swap(td);
  512. ed->hwHeadP = ed->hwTailP;
  513. ed->state = ED_UNLINK;
  514. ed->type = usb_pipetype(pipe);
  515. ohci_dev.ed_cnt++;
  516. }
  517. ed->hwINFO = m32_swap(usb_pipedevice(pipe)
  518. | usb_pipeendpoint(pipe) << 7
  519. | (usb_pipeisoc(pipe) ? 0x8000 : 0)
  520. | (usb_pipecontrol(pipe) ? 0 :
  521. (usb_pipeout(pipe) ? 0x800 : 0x1000))
  522. | (usb_dev->speed == USB_SPEED_LOW) << 13 |
  523. usb_maxpacket(usb_dev, pipe) << 16);
  524. return ed_ret;
  525. }
  526. /*-------------------------------------------------------------------------*
  527. * TD handling functions
  528. *-------------------------------------------------------------------------*/
  529. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  530. static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len,
  531. struct usb_device *dev, int index,
  532. struct urb_priv *urb_priv)
  533. {
  534. struct td *td, *td_pt;
  535. #ifdef OHCI_FILL_TRACE
  536. int i;
  537. #endif
  538. if (index > urb_priv->length) {
  539. err("index > length");
  540. return;
  541. }
  542. /* use this td as the next dummy */
  543. td_pt = urb_priv->td[index];
  544. td_pt->hwNextTD = 0;
  545. /* fill the old dummy TD */
  546. td = urb_priv->td[index] =
  547. (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
  548. td->ed = urb_priv->ed;
  549. td->next_dl_td = NULL;
  550. td->index = index;
  551. td->data = (__u32) data;
  552. #ifdef OHCI_FILL_TRACE
  553. if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
  554. for (i = 0; i < len; i++)
  555. printf("td->data[%d] %#2x ", i,
  556. ((unsigned char *)td->data)[i]);
  557. printf("\n");
  558. }
  559. #endif
  560. if (!len)
  561. data = 0;
  562. td->hwINFO = (__u32) m32_swap(info);
  563. td->hwCBP = (__u32) m32_swap(data);
  564. if (data)
  565. td->hwBE = (__u32) m32_swap(data + len - 1);
  566. else
  567. td->hwBE = 0;
  568. td->hwNextTD = (__u32) m32_swap(td_pt);
  569. /* append to queue */
  570. td->ed->hwTailP = td->hwNextTD;
  571. }
  572. /*-------------------------------------------------------------------------*/
  573. /* prepare all TDs of a transfer */
  574. static void td_submit_job(struct usb_device *dev, unsigned long pipe,
  575. void *buffer, int transfer_len,
  576. struct devrequest *setup, struct urb_priv *urb,
  577. int interval)
  578. {
  579. struct ohci *ohci = &gohci;
  580. int data_len = transfer_len;
  581. void *data;
  582. int cnt = 0;
  583. __u32 info = 0;
  584. unsigned int toggle = 0;
  585. /* OHCI handles the DATA-toggles itself, we just
  586. use the USB-toggle bits for resetting */
  587. if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  588. toggle = TD_T_TOGGLE;
  589. } else {
  590. toggle = TD_T_DATA0;
  591. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
  592. 1);
  593. }
  594. urb->td_cnt = 0;
  595. if (data_len)
  596. data = buffer;
  597. else
  598. data = 0;
  599. switch (usb_pipetype(pipe)) {
  600. case PIPE_BULK:
  601. info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
  602. while (data_len > 4096) {
  603. td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
  604. 4096, dev, cnt, urb);
  605. data += 4096;
  606. data_len -= 4096;
  607. cnt++;
  608. }
  609. info = usb_pipeout(pipe) ?
  610. TD_CC | TD_DP_OUT :
  611. TD_CC | TD_R | TD_DP_IN;
  612. td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
  613. data_len, dev, cnt, urb);
  614. cnt++;
  615. if (!ohci->sleeping)
  616. /* start bulk list */
  617. writel(OHCI_BLF, &ohci->regs->cmdstatus);
  618. break;
  619. case PIPE_CONTROL:
  620. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  621. td_fill(ohci, info, setup, 8, dev, cnt++, urb);
  622. if (data_len > 0) {
  623. info = usb_pipeout(pipe) ?
  624. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
  625. TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  626. /* NOTE: mishandles transfers >8K, some >4K */
  627. td_fill(ohci, info, data, data_len, dev, cnt++, urb);
  628. }
  629. info = usb_pipeout(pipe) ?
  630. TD_CC | TD_DP_IN | TD_T_DATA1 :
  631. TD_CC | TD_DP_OUT | TD_T_DATA1;
  632. td_fill(ohci, info, data, 0, dev, cnt++, urb);
  633. if (!ohci->sleeping)
  634. /* start Control list */
  635. writel(OHCI_CLF, &ohci->regs->cmdstatus);
  636. break;
  637. }
  638. if (urb->length != cnt)
  639. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  640. }
  641. /*-------------------------------------------------------------------------*
  642. * Done List handling functions
  643. *-------------------------------------------------------------------------*/
  644. /* calculate the transfer length and update the urb */
  645. static void dl_transfer_length(struct td *td)
  646. {
  647. __u32 tdBE, tdCBP;
  648. struct urb_priv *lurb_priv = &urb_priv;
  649. tdBE = m32_swap(td->hwBE);
  650. tdCBP = m32_swap(td->hwCBP);
  651. if (!(usb_pipecontrol(lurb_priv->pipe) &&
  652. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  653. if (tdBE != 0) {
  654. if (td->hwCBP == 0)
  655. lurb_priv->actual_length += tdBE - td->data + 1;
  656. else
  657. lurb_priv->actual_length += tdCBP - td->data;
  658. }
  659. }
  660. }
  661. /*-------------------------------------------------------------------------*/
  662. /* replies to the request have to be on a FIFO basis so
  663. * we reverse the reversed done-list */
  664. static struct td *dl_reverse_done_list(struct ohci *ohci)
  665. {
  666. __u32 td_list_hc;
  667. __u32 tmp;
  668. struct td *td_rev = NULL;
  669. struct td *td_list = NULL;
  670. struct urb_priv *lurb_priv = NULL;
  671. td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
  672. ohci->hcca->done_head = 0;
  673. while (td_list_hc) {
  674. td_list = (struct td *) td_list_hc;
  675. if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
  676. lurb_priv = &urb_priv;
  677. dbg(" USB-error/status: %x : %p",
  678. TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
  679. if (td_list->ed->hwHeadP & m32_swap(0x1)) {
  680. if (lurb_priv &&
  681. ((td_list->index+1) < lurb_priv->length)) {
  682. tmp = lurb_priv->length - 1;
  683. td_list->ed->hwHeadP =
  684. (lurb_priv->td[tmp]->hwNextTD &
  685. m32_swap(0xfffffff0)) |
  686. (td_list->ed->hwHeadP &
  687. m32_swap(0x2));
  688. lurb_priv->td_cnt += lurb_priv->length -
  689. td_list->index - 1;
  690. } else
  691. td_list->ed->hwHeadP &=
  692. m32_swap(0xfffffff2);
  693. }
  694. }
  695. td_list->next_dl_td = td_rev;
  696. td_rev = td_list;
  697. td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
  698. }
  699. return td_list;
  700. }
  701. /*-------------------------------------------------------------------------*/
  702. /* td done list */
  703. static int dl_done_list(struct ohci *ohci, struct td *td_list)
  704. {
  705. struct td *td_list_next = NULL;
  706. struct ed *ed;
  707. int cc = 0;
  708. int stat = 0;
  709. /* urb_t *urb; */
  710. struct urb_priv *lurb_priv;
  711. __u32 tdINFO, edHeadP, edTailP;
  712. while (td_list) {
  713. td_list_next = td_list->next_dl_td;
  714. lurb_priv = &urb_priv;
  715. tdINFO = m32_swap(td_list->hwINFO);
  716. ed = td_list->ed;
  717. dl_transfer_length(td_list);
  718. /* error code of transfer */
  719. cc = TD_CC_GET(tdINFO);
  720. if (cc != 0) {
  721. dbg("ConditionCode %#x", cc);
  722. stat = cc_to_error[cc];
  723. }
  724. /* see if this done list makes for all TD's of current URB,
  725. * and mark the URB finished if so */
  726. if (++(lurb_priv->td_cnt) == lurb_priv->length) {
  727. if ((ed->state & (ED_OPER | ED_UNLINK)))
  728. urb_finished = 1;
  729. else
  730. dbg("dl_done_list: strange.., ED state %x, "
  731. "ed->state\n");
  732. } else
  733. dbg("dl_done_list: processing TD %x, len %x\n",
  734. lurb_priv->td_cnt, lurb_priv->length);
  735. if (ed->state != ED_NEW) {
  736. edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
  737. edTailP = m32_swap(ed->hwTailP);
  738. /* unlink eds if they are not busy */
  739. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  740. ep_unlink(ohci, ed);
  741. }
  742. td_list = td_list_next;
  743. }
  744. return stat;
  745. }
  746. /*-------------------------------------------------------------------------*
  747. * Virtual Root Hub
  748. *-------------------------------------------------------------------------*/
  749. #include <usbroothubdes.h>
  750. /* Hub class-specific descriptor is constructed dynamically */
  751. /*-------------------------------------------------------------------------*/
  752. #define OK(x) len = (x); break
  753. #ifdef DEBUG
  754. #define WR_RH_STAT(x) \
  755. { \
  756. info("WR:status %#8x", (x)); \
  757. writel((x), &gohci.regs->roothub.status); \
  758. }
  759. #define WR_RH_PORTSTAT(x) \
  760. { \
  761. info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \
  762. writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \
  763. }
  764. #else
  765. #define WR_RH_STAT(x) \
  766. writel((x), &gohci.regs->roothub.status)
  767. #define WR_RH_PORTSTAT(x)\
  768. writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  769. #endif
  770. #define RD_RH_STAT roothub_status(&gohci)
  771. #define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1)
  772. /* request to virtual root hub */
  773. int rh_check_port_status(struct ohci *controller)
  774. {
  775. __u32 temp, ndp, i;
  776. int res;
  777. res = -1;
  778. temp = roothub_a(controller);
  779. ndp = (temp & RH_A_NDP);
  780. for (i = 0; i < ndp; i++) {
  781. temp = roothub_portstatus(controller, i);
  782. /* check for a device disconnect */
  783. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  784. (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
  785. res = i;
  786. break;
  787. }
  788. }
  789. return res;
  790. }
  791. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  792. void *buffer, int transfer_len,
  793. struct devrequest *cmd)
  794. {
  795. void *data = buffer;
  796. int leni = transfer_len;
  797. int len = 0;
  798. int stat = 0;
  799. union {
  800. __u32 word[4];
  801. __u16 hword[8];
  802. __u8 byte[16];
  803. } datab;
  804. __u8 *data_buf = datab.byte;
  805. __u16 bmRType_bReq;
  806. __u16 wValue;
  807. __u16 wIndex;
  808. __u16 wLength;
  809. #ifdef DEBUG
  810. urb_priv.actual_length = 0;
  811. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
  812. usb_pipein(pipe));
  813. #else
  814. mdelay(1);
  815. #endif
  816. if (usb_pipeint(pipe)) {
  817. info("Root-Hub submit IRQ: NOT implemented");
  818. return 0;
  819. }
  820. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  821. wValue = m16_swap(cmd->value);
  822. wIndex = m16_swap(cmd->index);
  823. wLength = m16_swap(cmd->length);
  824. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  825. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  826. switch (bmRType_bReq) {
  827. /* Request Destination:
  828. without flags: Device,
  829. RH_INTERFACE: interface,
  830. RH_ENDPOINT: endpoint,
  831. RH_CLASS means HUB here,
  832. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  833. */
  834. case RH_GET_STATUS:
  835. datab.hword[0] = m16_swap(1);
  836. OK(2);
  837. case RH_GET_STATUS | RH_INTERFACE:
  838. datab.hword[0] = m16_swap(0);
  839. OK(2);
  840. case RH_GET_STATUS | RH_ENDPOINT:
  841. datab.hword[0] = m16_swap(0);
  842. OK(2);
  843. case RH_GET_STATUS | RH_CLASS:
  844. datab.word[0] =
  845. m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  846. OK(4);
  847. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  848. datab.word[0] = m32_swap(RD_RH_PORTSTAT);
  849. OK(4);
  850. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  851. switch (wValue) {
  852. case (RH_ENDPOINT_STALL):
  853. OK(0);
  854. }
  855. break;
  856. case RH_CLEAR_FEATURE | RH_CLASS:
  857. switch (wValue) {
  858. case RH_C_HUB_LOCAL_POWER:
  859. OK(0);
  860. case (RH_C_HUB_OVER_CURRENT):
  861. WR_RH_STAT(RH_HS_OCIC);
  862. OK(0);
  863. }
  864. break;
  865. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  866. switch (wValue) {
  867. case (RH_PORT_ENABLE):
  868. WR_RH_PORTSTAT(RH_PS_CCS);
  869. OK(0);
  870. case (RH_PORT_SUSPEND):
  871. WR_RH_PORTSTAT(RH_PS_POCI);
  872. OK(0);
  873. case (RH_PORT_POWER):
  874. WR_RH_PORTSTAT(RH_PS_LSDA);
  875. OK(0);
  876. case (RH_C_PORT_CONNECTION):
  877. WR_RH_PORTSTAT(RH_PS_CSC);
  878. OK(0);
  879. case (RH_C_PORT_ENABLE):
  880. WR_RH_PORTSTAT(RH_PS_PESC);
  881. OK(0);
  882. case (RH_C_PORT_SUSPEND):
  883. WR_RH_PORTSTAT(RH_PS_PSSC);
  884. OK(0);
  885. case (RH_C_PORT_OVER_CURRENT):
  886. WR_RH_PORTSTAT(RH_PS_OCIC);
  887. OK(0);
  888. case (RH_C_PORT_RESET):
  889. WR_RH_PORTSTAT(RH_PS_PRSC);
  890. OK(0);
  891. }
  892. break;
  893. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  894. switch (wValue) {
  895. case (RH_PORT_SUSPEND):
  896. WR_RH_PORTSTAT(RH_PS_PSS);
  897. OK(0);
  898. case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */
  899. if (RD_RH_PORTSTAT & RH_PS_CCS)
  900. WR_RH_PORTSTAT(RH_PS_PRS);
  901. OK(0);
  902. case (RH_PORT_POWER):
  903. WR_RH_PORTSTAT(RH_PS_PPS);
  904. OK(0);
  905. case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */
  906. if (RD_RH_PORTSTAT & RH_PS_CCS)
  907. WR_RH_PORTSTAT(RH_PS_PES);
  908. OK(0);
  909. }
  910. break;
  911. case RH_SET_ADDRESS:
  912. gohci.rh.devnum = wValue;
  913. OK(0);
  914. case RH_GET_DESCRIPTOR:
  915. switch ((wValue & 0xff00) >> 8) {
  916. case (0x01): /* device descriptor */
  917. len = min_t(unsigned int,
  918. leni,
  919. min_t(unsigned int,
  920. sizeof(root_hub_dev_des), wLength));
  921. data_buf = root_hub_dev_des;
  922. OK(len);
  923. case (0x02): /* configuration descriptor */
  924. len = min_t(unsigned int,
  925. leni,
  926. min_t(unsigned int,
  927. sizeof(root_hub_config_des),
  928. wLength));
  929. data_buf = root_hub_config_des;
  930. OK(len);
  931. case (0x03): /* string descriptors */
  932. if (wValue == 0x0300) {
  933. len = min_t(unsigned int,
  934. leni,
  935. min_t(unsigned int,
  936. sizeof(root_hub_str_index0),
  937. wLength));
  938. data_buf = root_hub_str_index0;
  939. OK(len);
  940. }
  941. if (wValue == 0x0301) {
  942. len = min_t(unsigned int,
  943. leni,
  944. min_t(unsigned int,
  945. sizeof(root_hub_str_index1),
  946. wLength));
  947. data_buf = root_hub_str_index1;
  948. OK(len);
  949. }
  950. default:
  951. stat = USB_ST_STALLED;
  952. }
  953. break;
  954. case RH_GET_DESCRIPTOR | RH_CLASS:
  955. {
  956. __u32 temp = roothub_a(&gohci);
  957. data_buf[0] = 9; /* min length; */
  958. data_buf[1] = 0x29;
  959. data_buf[2] = temp & RH_A_NDP;
  960. data_buf[3] = 0;
  961. if (temp & RH_A_PSM)
  962. /* per-port power switching? */
  963. data_buf[3] |= 0x1;
  964. if (temp & RH_A_NOCP)
  965. /* no overcurrent reporting? */
  966. data_buf[3] |= 0x10;
  967. else if (temp & RH_A_OCPM)
  968. /* per-port overcurrent reporting? */
  969. data_buf[3] |= 0x8;
  970. /* corresponds to data_buf[4-7] */
  971. datab.word[1] = 0;
  972. data_buf[5] = (temp & RH_A_POTPGT) >> 24;
  973. temp = roothub_b(&gohci);
  974. data_buf[7] = temp & RH_B_DR;
  975. if (data_buf[2] < 7) {
  976. data_buf[8] = 0xff;
  977. } else {
  978. data_buf[0] += 2;
  979. data_buf[8] = (temp & RH_B_DR) >> 8;
  980. data_buf[10] = data_buf[9] = 0xff;
  981. }
  982. len = min_t(unsigned int, leni,
  983. min_t(unsigned int, data_buf[0], wLength));
  984. OK(len);
  985. }
  986. case RH_GET_CONFIGURATION:
  987. *(__u8 *) data_buf = 0x01;
  988. OK(1);
  989. case RH_SET_CONFIGURATION:
  990. WR_RH_STAT(0x10000);
  991. OK(0);
  992. default:
  993. dbg("unsupported root hub command");
  994. stat = USB_ST_STALLED;
  995. }
  996. #ifdef DEBUG
  997. ohci_dump_roothub(&gohci, 1);
  998. #else
  999. mdelay(1);
  1000. #endif
  1001. len = min_t(int, len, leni);
  1002. if (data != data_buf)
  1003. memcpy(data, data_buf, len);
  1004. dev->act_len = len;
  1005. dev->status = stat;
  1006. #ifdef DEBUG
  1007. if (transfer_len)
  1008. urb_priv.actual_length = transfer_len;
  1009. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
  1010. 0 /*usb_pipein(pipe) */);
  1011. #else
  1012. mdelay(1);
  1013. #endif
  1014. return stat;
  1015. }
  1016. /*-------------------------------------------------------------------------*/
  1017. /* common code for handling submit messages - used for all but root hub */
  1018. /* accesses. */
  1019. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1020. int transfer_len, struct devrequest *setup, int interval)
  1021. {
  1022. int stat = 0;
  1023. int maxsize = usb_maxpacket(dev, pipe);
  1024. int timeout;
  1025. /* device pulled? Shortcut the action. */
  1026. if (devgone == dev) {
  1027. dev->status = USB_ST_CRC_ERR;
  1028. return 0;
  1029. }
  1030. #ifdef DEBUG
  1031. urb_priv.actual_length = 0;
  1032. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
  1033. usb_pipein(pipe));
  1034. #else
  1035. mdelay(1);
  1036. #endif
  1037. if (!maxsize) {
  1038. err("submit_common_message: pipesize for pipe %lx is zero",
  1039. pipe);
  1040. return -1;
  1041. }
  1042. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
  1043. 0) {
  1044. err("sohci_submit_job failed");
  1045. return -1;
  1046. }
  1047. mdelay(10);
  1048. /* ohci_dump_status(&gohci); */
  1049. /* allow more time for a BULK device to react - some are slow */
  1050. #define BULK_TO 5000 /* timeout in milliseconds */
  1051. if (usb_pipebulk(pipe))
  1052. timeout = BULK_TO;
  1053. else
  1054. timeout = 100;
  1055. /* wait for it to complete */
  1056. for (;;) {
  1057. /* check whether the controller is done */
  1058. stat = hc_interrupt();
  1059. if (stat < 0) {
  1060. stat = USB_ST_CRC_ERR;
  1061. break;
  1062. }
  1063. /* NOTE: since we are not interrupt driven in U-Boot and always
  1064. * handle only one URB at a time, we cannot assume the
  1065. * transaction finished on the first successful return from
  1066. * hc_interrupt().. unless the flag for current URB is set,
  1067. * meaning that all TD's to/from device got actually
  1068. * transferred and processed. If the current URB is not
  1069. * finished we need to re-iterate this loop so as
  1070. * hc_interrupt() gets called again as there needs to be some
  1071. * more TD's to process still */
  1072. if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
  1073. /* 0xff is returned for an SF-interrupt */
  1074. break;
  1075. }
  1076. if (--timeout) {
  1077. mdelay(1);
  1078. if (!urb_finished)
  1079. dbg("\%");
  1080. } else {
  1081. err("CTL:TIMEOUT ");
  1082. dbg("submit_common_msg: TO status %x\n", stat);
  1083. stat = USB_ST_CRC_ERR;
  1084. urb_finished = 1;
  1085. break;
  1086. }
  1087. }
  1088. #if 0
  1089. /* we got an Root Hub Status Change interrupt */
  1090. if (got_rhsc) {
  1091. #ifdef DEBUG
  1092. ohci_dump_roothub(&gohci, 1);
  1093. #endif
  1094. got_rhsc = 0;
  1095. /* abuse timeout */
  1096. timeout = rh_check_port_status(&gohci);
  1097. if (timeout >= 0) {
  1098. #if 0 /* this does nothing useful, but leave it here
  1099. in case that changes */
  1100. /* the called routine adds 1 to the passed value */
  1101. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1102. #endif
  1103. /*
  1104. * XXX
  1105. * This is potentially dangerous because it assumes
  1106. * that only one device is ever plugged in!
  1107. */
  1108. devgone = dev;
  1109. }
  1110. }
  1111. #endif
  1112. dev->status = stat;
  1113. dev->act_len = transfer_len;
  1114. #ifdef DEBUG
  1115. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
  1116. usb_pipein(pipe));
  1117. #else
  1118. mdelay(1);
  1119. #endif
  1120. /* free TDs in urb_priv */
  1121. urb_free_priv(&urb_priv);
  1122. return 0;
  1123. }
  1124. /* submit routines called from usb.c */
  1125. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1126. int transfer_len)
  1127. {
  1128. info("submit_bulk_msg");
  1129. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1130. }
  1131. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1132. int transfer_len, struct devrequest *setup)
  1133. {
  1134. int maxsize = usb_maxpacket(dev, pipe);
  1135. info("submit_control_msg");
  1136. #ifdef DEBUG
  1137. urb_priv.actual_length = 0;
  1138. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
  1139. usb_pipein(pipe));
  1140. #else
  1141. mdelay(1);
  1142. #endif
  1143. if (!maxsize) {
  1144. err("submit_control_message: pipesize for pipe %lx is zero",
  1145. pipe);
  1146. return -1;
  1147. }
  1148. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1149. gohci.rh.dev = dev;
  1150. /* root hub - redirect */
  1151. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1152. setup);
  1153. }
  1154. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1155. }
  1156. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1157. int transfer_len, int interval)
  1158. {
  1159. info("submit_int_msg");
  1160. return -1;
  1161. }
  1162. /*-------------------------------------------------------------------------*
  1163. * HC functions
  1164. *-------------------------------------------------------------------------*/
  1165. /* reset the HC and BUS */
  1166. static int hc_reset(struct ohci *ohci)
  1167. {
  1168. int timeout = 30;
  1169. int smm_timeout = 50; /* 0,5 sec */
  1170. if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
  1171. /* SMM owns the HC - request ownership */
  1172. writel(OHCI_OCR, &ohci->regs->cmdstatus);
  1173. info("USB HC TakeOver from SMM");
  1174. while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
  1175. mdelay(10);
  1176. if (--smm_timeout == 0) {
  1177. err("USB HC TakeOver failed!");
  1178. return -1;
  1179. }
  1180. }
  1181. }
  1182. /* Disable HC interrupts */
  1183. writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1184. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
  1185. ohci->slot_name, readl(&ohci->regs->control));
  1186. /* Reset USB (needed by some controllers) */
  1187. writel(0, &ohci->regs->control);
  1188. /* HC Reset requires max 10 us delay */
  1189. writel(OHCI_HCR, &ohci->regs->cmdstatus);
  1190. while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1191. if (--timeout == 0) {
  1192. err("USB HC reset timed out!");
  1193. return -1;
  1194. }
  1195. udelay(1);
  1196. }
  1197. return 0;
  1198. }
  1199. /*-------------------------------------------------------------------------*/
  1200. /* Start an OHCI controller, set the BUS operational
  1201. * enable interrupts
  1202. * connect the virtual root hub */
  1203. static int hc_start(struct ohci *ohci)
  1204. {
  1205. __u32 mask;
  1206. unsigned int fminterval;
  1207. ohci->disabled = 1;
  1208. /* Tell the controller where the control and bulk lists are
  1209. * The lists are empty now. */
  1210. writel(0, &ohci->regs->ed_controlhead);
  1211. writel(0, &ohci->regs->ed_bulkhead);
  1212. /* a reset clears this */
  1213. writel((__u32) ohci->hcca, &ohci->regs->hcca);
  1214. fminterval = 0x2edf;
  1215. writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1216. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1217. writel(fminterval, &ohci->regs->fminterval);
  1218. writel(0x628, &ohci->regs->lsthresh);
  1219. /* start controller operations */
  1220. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1221. ohci->disabled = 0;
  1222. writel(ohci->hc_control, &ohci->regs->control);
  1223. /* disable all interrupts */
  1224. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1225. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1226. OHCI_INTR_OC | OHCI_INTR_MIE);
  1227. writel(mask, &ohci->regs->intrdisable);
  1228. /* clear all interrupts */
  1229. mask &= ~OHCI_INTR_MIE;
  1230. writel(mask, &ohci->regs->intrstatus);
  1231. /* Choose the interrupts we care about now - but w/o MIE */
  1232. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1233. writel(mask, &ohci->regs->intrenable);
  1234. #ifdef OHCI_USE_NPS
  1235. /* required for AMD-756 and some Mac platforms */
  1236. writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
  1237. &ohci->regs->roothub.a);
  1238. writel(RH_HS_LPSC, &ohci->regs->roothub.status);
  1239. #endif /* OHCI_USE_NPS */
  1240. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1241. mdelay((roothub_a(ohci) >> 23) & 0x1fe);
  1242. /* connect the virtual root hub */
  1243. ohci->rh.devnum = 0;
  1244. return 0;
  1245. }
  1246. /*-------------------------------------------------------------------------*/
  1247. /* an interrupt happens */
  1248. static int hc_interrupt(void)
  1249. {
  1250. struct ohci *ohci = &gohci;
  1251. struct ohci_regs *regs = ohci->regs;
  1252. int ints;
  1253. int stat = -1;
  1254. if ((ohci->hcca->done_head != 0) &&
  1255. !(m32_swap(ohci->hcca->done_head) & 0x01)) {
  1256. ints = OHCI_INTR_WDH;
  1257. } else {
  1258. ints = readl(&regs->intrstatus);
  1259. if (ints == ~(u32) 0) {
  1260. ohci->disabled++;
  1261. err("%s device removed!", ohci->slot_name);
  1262. return -1;
  1263. }
  1264. ints &= readl(&regs->intrenable);
  1265. if (ints == 0) {
  1266. dbg("hc_interrupt: returning..\n");
  1267. return 0xff;
  1268. }
  1269. }
  1270. /* dbg("Interrupt: %x frame: %x", ints,
  1271. le16_to_cpu(ohci->hcca->frame_no)); */
  1272. if (ints & OHCI_INTR_RHSC) {
  1273. got_rhsc = 1;
  1274. stat = 0xff;
  1275. }
  1276. if (ints & OHCI_INTR_UE) {
  1277. ohci->disabled++;
  1278. err("OHCI Unrecoverable Error, controller usb-%s disabled",
  1279. ohci->slot_name);
  1280. /* e.g. due to PCI Master/Target Abort */
  1281. #ifdef DEBUG
  1282. ohci_dump(ohci, 1);
  1283. #else
  1284. mdelay(1);
  1285. #endif
  1286. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1287. /* Make some non-interrupt context restart the controller. */
  1288. /* Count and limit the retries though; either hardware or */
  1289. /* software errors can go forever... */
  1290. hc_reset(ohci);
  1291. return -1;
  1292. }
  1293. if (ints & OHCI_INTR_WDH) {
  1294. mdelay(1);
  1295. writel(OHCI_INTR_WDH, &regs->intrdisable);
  1296. stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
  1297. writel(OHCI_INTR_WDH, &regs->intrenable);
  1298. }
  1299. if (ints & OHCI_INTR_SO) {
  1300. dbg("USB Schedule overrun\n");
  1301. writel(OHCI_INTR_SO, &regs->intrenable);
  1302. stat = -1;
  1303. }
  1304. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1305. if (ints & OHCI_INTR_SF) {
  1306. unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
  1307. mdelay(1);
  1308. writel(OHCI_INTR_SF, &regs->intrdisable);
  1309. if (ohci->ed_rm_list[frame] != NULL)
  1310. writel(OHCI_INTR_SF, &regs->intrenable);
  1311. stat = 0xff;
  1312. }
  1313. writel(ints, &regs->intrstatus);
  1314. return stat;
  1315. }
  1316. /*-------------------------------------------------------------------------*/
  1317. /*-------------------------------------------------------------------------*/
  1318. /* De-allocate all resources.. */
  1319. static void hc_release_ohci(struct ohci *ohci)
  1320. {
  1321. dbg("USB HC release ohci usb-%s", ohci->slot_name);
  1322. if (!ohci->disabled)
  1323. hc_reset(ohci);
  1324. }
  1325. /*-------------------------------------------------------------------------*/
  1326. /*
  1327. * low level initalisation routine, called from usb.c
  1328. */
  1329. static char ohci_inited = 0;
  1330. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1331. {
  1332. struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  1333. struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  1334. /*
  1335. * Set the 48 MHz UPLL clocking. Values are taken from
  1336. * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
  1337. */
  1338. clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
  1339. gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */
  1340. /*
  1341. * Enable USB host clock.
  1342. */
  1343. clk_power->clkcon |= (1 << 4);
  1344. memset(&gohci, 0, sizeof(struct ohci));
  1345. memset(&urb_priv, 0, sizeof(struct urb_priv));
  1346. /* align the storage */
  1347. if ((__u32) &ghcca[0] & 0xff) {
  1348. err("HCCA not aligned!!");
  1349. return -1;
  1350. }
  1351. phcca = &ghcca[0];
  1352. info("aligned ghcca %p", phcca);
  1353. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1354. if ((__u32) &ohci_dev.ed[0] & 0x7) {
  1355. err("EDs not aligned!!");
  1356. return -1;
  1357. }
  1358. memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1));
  1359. if ((__u32) gtd & 0x7) {
  1360. err("TDs not aligned!!");
  1361. return -1;
  1362. }
  1363. ptd = gtd;
  1364. gohci.hcca = phcca;
  1365. memset(phcca, 0, sizeof(struct ohci_hcca));
  1366. gohci.disabled = 1;
  1367. gohci.sleeping = 0;
  1368. gohci.irq = -1;
  1369. gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
  1370. gohci.flags = 0;
  1371. gohci.slot_name = "s3c2400";
  1372. if (hc_reset(&gohci) < 0) {
  1373. hc_release_ohci(&gohci);
  1374. /* Initialization failed */
  1375. clk_power->clkcon &= ~(1 << 4);
  1376. return -1;
  1377. }
  1378. /* FIXME this is a second HC reset; why?? */
  1379. gohci.hc_control = OHCI_USB_RESET;
  1380. writel(gohci.hc_control, &gohci.regs->control);
  1381. mdelay(10);
  1382. if (hc_start(&gohci) < 0) {
  1383. err("can't start usb-%s", gohci.slot_name);
  1384. hc_release_ohci(&gohci);
  1385. /* Initialization failed */
  1386. clk_power->clkcon &= ~(1 << 4);
  1387. return -1;
  1388. }
  1389. #ifdef DEBUG
  1390. ohci_dump(&gohci, 1);
  1391. #else
  1392. mdelay(1);
  1393. #endif
  1394. ohci_inited = 1;
  1395. urb_finished = 1;
  1396. return 0;
  1397. }
  1398. int usb_lowlevel_stop(int index)
  1399. {
  1400. struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  1401. /* this gets called really early - before the controller has */
  1402. /* even been initialized! */
  1403. if (!ohci_inited)
  1404. return 0;
  1405. /* TODO release any interrupts, etc. */
  1406. /* call hc_release_ohci() here ? */
  1407. hc_reset(&gohci);
  1408. /* may not want to do this */
  1409. clk_power->clkcon &= ~(1 << 4);
  1410. return 0;
  1411. }
  1412. #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
  1413. #if defined(CONFIG_USB_OHCI_NEW) && \
  1414. defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
  1415. defined(CONFIG_S3C24X0)
  1416. int usb_cpu_init(void)
  1417. {
  1418. struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  1419. struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  1420. /*
  1421. * Set the 48 MHz UPLL clocking. Values are taken from
  1422. * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
  1423. */
  1424. writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
  1425. /* 1 = use pads related USB for USB host */
  1426. writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
  1427. /*
  1428. * Enable USB host clock.
  1429. */
  1430. writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
  1431. return 0;
  1432. }
  1433. int usb_cpu_stop(void)
  1434. {
  1435. struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  1436. /* may not want to do this */
  1437. writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
  1438. return 0;
  1439. }
  1440. int usb_cpu_init_fail(void)
  1441. {
  1442. struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  1443. writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
  1444. return 0;
  1445. }
  1446. #endif /* defined(CONFIG_USB_OHCI_NEW) && \
  1447. defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
  1448. defined(CONFIG_S3C24X0) */