ehci-mxc.c 6.2 KB

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  1. /*
  2. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <usb.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <usb/ehci-ci.h>
  11. #include <errno.h>
  12. #include "ehci.h"
  13. #define USBCTRL_OTGBASE_OFFSET 0x600
  14. #define MX25_OTG_SIC_SHIFT 29
  15. #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
  16. #define MX25_OTG_PM_BIT (1 << 24)
  17. #define MX25_OTG_PP_BIT (1 << 11)
  18. #define MX25_OTG_OCPOL_BIT (1 << 3)
  19. #define MX25_H1_SIC_SHIFT 21
  20. #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
  21. #define MX25_H1_PP_BIT (1 << 18)
  22. #define MX25_H1_PM_BIT (1 << 16)
  23. #define MX25_H1_IPPUE_UP_BIT (1 << 7)
  24. #define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
  25. #define MX25_H1_TLL_BIT (1 << 5)
  26. #define MX25_H1_USBTE_BIT (1 << 4)
  27. #define MX25_H1_OCPOL_BIT (1 << 2)
  28. #define MX31_OTG_SIC_SHIFT 29
  29. #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
  30. #define MX31_OTG_PM_BIT (1 << 24)
  31. #define MX31_H2_SIC_SHIFT 21
  32. #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
  33. #define MX31_H2_PM_BIT (1 << 16)
  34. #define MX31_H2_DT_BIT (1 << 5)
  35. #define MX31_H1_SIC_SHIFT 13
  36. #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
  37. #define MX31_H1_PM_BIT (1 << 8)
  38. #define MX31_H1_DT_BIT (1 << 4)
  39. #define MX35_OTG_SIC_SHIFT 29
  40. #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
  41. #define MX35_OTG_PM_BIT (1 << 24)
  42. #define MX35_OTG_PP_BIT (1 << 11)
  43. #define MX35_OTG_OCPOL_BIT (1 << 3)
  44. #define MX35_H1_SIC_SHIFT 21
  45. #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
  46. #define MX35_H1_PP_BIT (1 << 18)
  47. #define MX35_H1_PM_BIT (1 << 16)
  48. #define MX35_H1_IPPUE_UP_BIT (1 << 7)
  49. #define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
  50. #define MX35_H1_TLL_BIT (1 << 5)
  51. #define MX35_H1_USBTE_BIT (1 << 4)
  52. #define MX35_H1_OCPOL_BIT (1 << 2)
  53. static int mxc_set_usbcontrol(int port, unsigned int flags)
  54. {
  55. unsigned int v;
  56. v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
  57. #if defined(CONFIG_MX25)
  58. switch (port) {
  59. case 0: /* OTG port */
  60. v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
  61. MX25_OTG_OCPOL_BIT);
  62. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
  63. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  64. v |= MX25_OTG_PM_BIT;
  65. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  66. v |= MX25_OTG_PP_BIT;
  67. if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  68. v |= MX25_OTG_OCPOL_BIT;
  69. break;
  70. case 1: /* H1 port */
  71. v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
  72. MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
  73. MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
  74. MX25_H1_IPPUE_UP_BIT);
  75. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
  76. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  77. v |= MX25_H1_PM_BIT;
  78. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  79. v |= MX25_H1_PP_BIT;
  80. if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  81. v |= MX25_H1_OCPOL_BIT;
  82. if (!(flags & MXC_EHCI_TTL_ENABLED))
  83. v |= MX25_H1_TLL_BIT;
  84. if (flags & MXC_EHCI_INTERNAL_PHY)
  85. v |= MX25_H1_USBTE_BIT;
  86. if (flags & MXC_EHCI_IPPUE_DOWN)
  87. v |= MX25_H1_IPPUE_DOWN_BIT;
  88. if (flags & MXC_EHCI_IPPUE_UP)
  89. v |= MX25_H1_IPPUE_UP_BIT;
  90. break;
  91. default:
  92. return -EINVAL;
  93. }
  94. #elif defined(CONFIG_MX31)
  95. switch (port) {
  96. case 0: /* OTG port */
  97. v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
  98. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
  99. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  100. v |= MX31_OTG_PM_BIT;
  101. break;
  102. case 1: /* H1 port */
  103. v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
  104. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
  105. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  106. v |= MX31_H1_PM_BIT;
  107. if (!(flags & MXC_EHCI_TTL_ENABLED))
  108. v |= MX31_H1_DT_BIT;
  109. break;
  110. case 2: /* H2 port */
  111. v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
  112. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
  113. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  114. v |= MX31_H2_PM_BIT;
  115. if (!(flags & MXC_EHCI_TTL_ENABLED))
  116. v |= MX31_H2_DT_BIT;
  117. break;
  118. default:
  119. return -EINVAL;
  120. }
  121. #elif defined(CONFIG_MX35)
  122. switch (port) {
  123. case 0: /* OTG port */
  124. v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
  125. MX35_OTG_OCPOL_BIT);
  126. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
  127. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  128. v |= MX35_OTG_PM_BIT;
  129. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  130. v |= MX35_OTG_PP_BIT;
  131. if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  132. v |= MX35_OTG_OCPOL_BIT;
  133. break;
  134. case 1: /* H1 port */
  135. v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
  136. MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
  137. MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
  138. MX35_H1_IPPUE_UP_BIT);
  139. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
  140. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  141. v |= MX35_H1_PM_BIT;
  142. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  143. v |= MX35_H1_PP_BIT;
  144. if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  145. v |= MX35_H1_OCPOL_BIT;
  146. if (!(flags & MXC_EHCI_TTL_ENABLED))
  147. v |= MX35_H1_TLL_BIT;
  148. if (flags & MXC_EHCI_INTERNAL_PHY)
  149. v |= MX35_H1_USBTE_BIT;
  150. if (flags & MXC_EHCI_IPPUE_DOWN)
  151. v |= MX35_H1_IPPUE_DOWN_BIT;
  152. if (flags & MXC_EHCI_IPPUE_UP)
  153. v |= MX35_H1_IPPUE_UP_BIT;
  154. break;
  155. default:
  156. return -EINVAL;
  157. }
  158. #else
  159. #error MXC EHCI USB driver not supported on this platform
  160. #endif
  161. writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
  162. return 0;
  163. }
  164. int ehci_hcd_init(int index, enum usb_init_type init,
  165. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  166. {
  167. struct usb_ehci *ehci;
  168. #ifdef CONFIG_MX31
  169. struct clock_control_regs *sc_regs =
  170. (struct clock_control_regs *)CCM_BASE;
  171. __raw_readl(&sc_regs->ccmr);
  172. __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
  173. #endif
  174. udelay(80);
  175. ehci = (struct usb_ehci *)(IMX_USB_BASE +
  176. IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
  177. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  178. *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
  179. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  180. setbits_le32(&ehci->usbmode, CM_HOST);
  181. __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  182. mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
  183. #ifdef CONFIG_MX35
  184. /* Workaround for ENGcm11601 */
  185. __raw_writel(0, &ehci->sbuscfg);
  186. #endif
  187. udelay(10000);
  188. return 0;
  189. }
  190. /*
  191. * Destroy the appropriate control structures corresponding
  192. * the the EHCI host controller.
  193. */
  194. int ehci_hcd_stop(int index)
  195. {
  196. return 0;
  197. }