fotg210.c 22 KB

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  1. /*
  2. * Faraday USB 2.0 OTG Controller
  3. *
  4. * (C) Copyright 2010 Faraday Technology
  5. * Dante Su <dantesu@faraday-tech.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <command.h>
  11. #include <config.h>
  12. #include <net.h>
  13. #include <malloc.h>
  14. #include <asm/io.h>
  15. #include <linux/errno.h>
  16. #include <linux/types.h>
  17. #include <linux/usb/ch9.h>
  18. #include <linux/usb/gadget.h>
  19. #include <usb/fotg210.h>
  20. #define CFG_NUM_ENDPOINTS 4
  21. #define CFG_EP0_MAX_PACKET_SIZE 64
  22. #define CFG_EPX_MAX_PACKET_SIZE 512
  23. #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
  24. struct fotg210_chip;
  25. struct fotg210_ep {
  26. struct usb_ep ep;
  27. uint maxpacket;
  28. uint id;
  29. uint stopped;
  30. struct list_head queue;
  31. struct fotg210_chip *chip;
  32. const struct usb_endpoint_descriptor *desc;
  33. };
  34. struct fotg210_request {
  35. struct usb_request req;
  36. struct list_head queue;
  37. struct fotg210_ep *ep;
  38. };
  39. struct fotg210_chip {
  40. struct usb_gadget gadget;
  41. struct usb_gadget_driver *driver;
  42. struct fotg210_regs *regs;
  43. uint8_t irq;
  44. uint16_t addr;
  45. int pullup;
  46. enum usb_device_state state;
  47. struct fotg210_ep ep[1 + CFG_NUM_ENDPOINTS];
  48. };
  49. static struct usb_endpoint_descriptor ep0_desc = {
  50. .bLength = sizeof(struct usb_endpoint_descriptor),
  51. .bDescriptorType = USB_DT_ENDPOINT,
  52. .bEndpointAddress = USB_DIR_IN,
  53. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  54. };
  55. static inline int fifo_to_ep(struct fotg210_chip *chip, int id, int in)
  56. {
  57. return (id < 0) ? 0 : ((id & 0x03) + 1);
  58. }
  59. static inline int ep_to_fifo(struct fotg210_chip *chip, int id)
  60. {
  61. return (id <= 0) ? -1 : ((id - 1) & 0x03);
  62. }
  63. static inline int ep_reset(struct fotg210_chip *chip, uint8_t ep_addr)
  64. {
  65. int ep = ep_addr & USB_ENDPOINT_NUMBER_MASK;
  66. struct fotg210_regs *regs = chip->regs;
  67. if (ep_addr & USB_DIR_IN) {
  68. /* reset endpoint */
  69. setbits_le32(&regs->iep[ep - 1], IEP_RESET);
  70. mdelay(1);
  71. clrbits_le32(&regs->iep[ep - 1], IEP_RESET);
  72. /* clear endpoint stall */
  73. clrbits_le32(&regs->iep[ep - 1], IEP_STALL);
  74. } else {
  75. /* reset endpoint */
  76. setbits_le32(&regs->oep[ep - 1], OEP_RESET);
  77. mdelay(1);
  78. clrbits_le32(&regs->oep[ep - 1], OEP_RESET);
  79. /* clear endpoint stall */
  80. clrbits_le32(&regs->oep[ep - 1], OEP_STALL);
  81. }
  82. return 0;
  83. }
  84. static int fotg210_reset(struct fotg210_chip *chip)
  85. {
  86. struct fotg210_regs *regs = chip->regs;
  87. uint32_t i;
  88. chip->state = USB_STATE_POWERED;
  89. /* chip enable */
  90. writel(DEVCTRL_EN, &regs->dev_ctrl);
  91. /* device address reset */
  92. chip->addr = 0;
  93. writel(0, &regs->dev_addr);
  94. /* set idle counter to 7ms */
  95. writel(7, &regs->idle);
  96. /* disable all interrupts */
  97. writel(IMR_MASK, &regs->imr);
  98. writel(GIMR_MASK, &regs->gimr);
  99. writel(GIMR0_MASK, &regs->gimr0);
  100. writel(GIMR1_MASK, &regs->gimr1);
  101. writel(GIMR2_MASK, &regs->gimr2);
  102. /* clear interrupts */
  103. writel(ISR_MASK, &regs->isr);
  104. writel(0, &regs->gisr);
  105. writel(0, &regs->gisr0);
  106. writel(0, &regs->gisr1);
  107. writel(0, &regs->gisr2);
  108. /* chip reset */
  109. setbits_le32(&regs->dev_ctrl, DEVCTRL_RESET);
  110. mdelay(10);
  111. if (readl(&regs->dev_ctrl) & DEVCTRL_RESET) {
  112. printf("fotg210: chip reset failed\n");
  113. return -1;
  114. }
  115. /* CX FIFO reset */
  116. setbits_le32(&regs->cxfifo, CXFIFO_CXFIFOCLR);
  117. mdelay(10);
  118. if (readl(&regs->cxfifo) & CXFIFO_CXFIFOCLR) {
  119. printf("fotg210: ep0 fifo reset failed\n");
  120. return -1;
  121. }
  122. /* create static ep-fifo map (EP1 <-> FIFO0, EP2 <-> FIFO1 ...) */
  123. writel(EPMAP14_DEFAULT, &regs->epmap14);
  124. writel(EPMAP58_DEFAULT, &regs->epmap58);
  125. writel(FIFOMAP_DEFAULT, &regs->fifomap);
  126. writel(0, &regs->fifocfg);
  127. for (i = 0; i < 8; ++i) {
  128. writel(CFG_EPX_MAX_PACKET_SIZE, &regs->iep[i]);
  129. writel(CFG_EPX_MAX_PACKET_SIZE, &regs->oep[i]);
  130. }
  131. /* FIFO reset */
  132. for (i = 0; i < 4; ++i) {
  133. writel(FIFOCSR_RESET, &regs->fifocsr[i]);
  134. mdelay(10);
  135. if (readl(&regs->fifocsr[i]) & FIFOCSR_RESET) {
  136. printf("fotg210: fifo%d reset failed\n", i);
  137. return -1;
  138. }
  139. }
  140. /* enable only device interrupt and triggered at level-high */
  141. writel(IMR_IRQLH | IMR_HOST | IMR_OTG, &regs->imr);
  142. writel(ISR_MASK, &regs->isr);
  143. /* disable EP0 IN/OUT interrupt */
  144. writel(GIMR0_CXOUT | GIMR0_CXIN, &regs->gimr0);
  145. /* disable EPX IN+SPK+OUT interrupts */
  146. writel(GIMR1_MASK, &regs->gimr1);
  147. /* disable wakeup+idle+dma+zlp interrupts */
  148. writel(GIMR2_WAKEUP | GIMR2_IDLE | GIMR2_DMAERR | GIMR2_DMAFIN
  149. | GIMR2_ZLPRX | GIMR2_ZLPTX, &regs->gimr2);
  150. /* enable all group interrupt */
  151. writel(0, &regs->gimr);
  152. /* suspend delay = 3 ms */
  153. writel(3, &regs->idle);
  154. /* turn-on device interrupts */
  155. setbits_le32(&regs->dev_ctrl, DEVCTRL_GIRQ_EN);
  156. return 0;
  157. }
  158. static inline int fotg210_cxwait(struct fotg210_chip *chip, uint32_t mask)
  159. {
  160. struct fotg210_regs *regs = chip->regs;
  161. int ret = -1;
  162. ulong ts;
  163. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  164. if ((readl(&regs->cxfifo) & mask) != mask)
  165. continue;
  166. ret = 0;
  167. break;
  168. }
  169. if (ret)
  170. printf("fotg210: cx/ep0 timeout\n");
  171. return ret;
  172. }
  173. static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req)
  174. {
  175. struct fotg210_chip *chip = ep->chip;
  176. struct fotg210_regs *regs = chip->regs;
  177. uint32_t tmp, ts;
  178. uint8_t *buf = req->req.buf + req->req.actual;
  179. uint32_t len = req->req.length - req->req.actual;
  180. int fifo = ep_to_fifo(chip, ep->id);
  181. int ret = -EBUSY;
  182. /* 1. init dma buffer */
  183. if (len > ep->maxpacket)
  184. len = ep->maxpacket;
  185. /* 2. wait for dma ready (hardware) */
  186. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  187. if (!(readl(&regs->dma_ctrl) & DMACTRL_START)) {
  188. ret = 0;
  189. break;
  190. }
  191. }
  192. if (ret) {
  193. printf("fotg210: dma busy\n");
  194. req->req.status = ret;
  195. return ret;
  196. }
  197. /* 3. DMA target setup */
  198. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  199. flush_dcache_range((ulong)buf, (ulong)buf + len);
  200. else
  201. invalidate_dcache_range((ulong)buf, (ulong)buf + len);
  202. writel(virt_to_phys(buf), &regs->dma_addr);
  203. if (ep->desc->bEndpointAddress & USB_DIR_IN) {
  204. if (ep->id == 0) {
  205. /* Wait until cx/ep0 fifo empty */
  206. fotg210_cxwait(chip, CXFIFO_CXFIFOE);
  207. udelay(1);
  208. writel(DMAFIFO_CX, &regs->dma_fifo);
  209. } else {
  210. /* Wait until epx fifo empty */
  211. fotg210_cxwait(chip, CXFIFO_FIFOE(fifo));
  212. writel(DMAFIFO_FIFO(fifo), &regs->dma_fifo);
  213. }
  214. writel(DMACTRL_LEN(len) | DMACTRL_MEM2FIFO, &regs->dma_ctrl);
  215. } else {
  216. uint32_t blen;
  217. if (ep->id == 0) {
  218. writel(DMAFIFO_CX, &regs->dma_fifo);
  219. do {
  220. blen = CXFIFO_BYTES(readl(&regs->cxfifo));
  221. } while (blen < len);
  222. } else {
  223. writel(DMAFIFO_FIFO(fifo), &regs->dma_fifo);
  224. blen = FIFOCSR_BYTES(readl(&regs->fifocsr[fifo]));
  225. }
  226. len = (len < blen) ? len : blen;
  227. writel(DMACTRL_LEN(len) | DMACTRL_FIFO2MEM, &regs->dma_ctrl);
  228. }
  229. /* 4. DMA start */
  230. setbits_le32(&regs->dma_ctrl, DMACTRL_START);
  231. /* 5. DMA wait */
  232. ret = -EBUSY;
  233. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  234. tmp = readl(&regs->gisr2);
  235. /* DMA complete */
  236. if (tmp & GISR2_DMAFIN) {
  237. ret = 0;
  238. break;
  239. }
  240. /* DMA error */
  241. if (tmp & GISR2_DMAERR) {
  242. printf("fotg210: dma error\n");
  243. break;
  244. }
  245. /* resume, suspend, reset */
  246. if (tmp & (GISR2_RESUME | GISR2_SUSPEND | GISR2_RESET)) {
  247. printf("fotg210: dma reset by host\n");
  248. break;
  249. }
  250. }
  251. /* 7. DMA target reset */
  252. if (ret)
  253. writel(DMACTRL_ABORT | DMACTRL_CLRFF, &regs->dma_ctrl);
  254. writel(0, &regs->gisr2);
  255. writel(0, &regs->dma_fifo);
  256. req->req.status = ret;
  257. if (!ret)
  258. req->req.actual += len;
  259. else
  260. printf("fotg210: ep%d dma error(code=%d)\n", ep->id, ret);
  261. return len;
  262. }
  263. /*
  264. * result of setup packet
  265. */
  266. #define CX_IDLE 0
  267. #define CX_FINISH 1
  268. #define CX_STALL 2
  269. static void fotg210_setup(struct fotg210_chip *chip)
  270. {
  271. int id, ret = CX_IDLE;
  272. uint32_t tmp[2];
  273. struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)tmp;
  274. struct fotg210_regs *regs = chip->regs;
  275. /*
  276. * If this is the first Cx 8 byte command,
  277. * we can now query USB mode (high/full speed; USB 2.0/USB 1.0)
  278. */
  279. if (chip->state == USB_STATE_POWERED) {
  280. chip->state = USB_STATE_DEFAULT;
  281. if (readl(&regs->otgcsr) & OTGCSR_DEV_B) {
  282. /* Mini-B */
  283. if (readl(&regs->dev_ctrl) & DEVCTRL_HS) {
  284. puts("fotg210: HS\n");
  285. chip->gadget.speed = USB_SPEED_HIGH;
  286. /* SOF mask timer = 1100 ticks */
  287. writel(SOFMTR_TMR(1100), &regs->sof_mtr);
  288. } else {
  289. puts("fotg210: FS\n");
  290. chip->gadget.speed = USB_SPEED_FULL;
  291. /* SOF mask timer = 10000 ticks */
  292. writel(SOFMTR_TMR(10000), &regs->sof_mtr);
  293. }
  294. } else {
  295. printf("fotg210: mini-A?\n");
  296. }
  297. }
  298. /* switch data port to ep0 */
  299. writel(DMAFIFO_CX, &regs->dma_fifo);
  300. /* fetch 8 bytes setup packet */
  301. tmp[0] = readl(&regs->ep0_data);
  302. tmp[1] = readl(&regs->ep0_data);
  303. /* release data port */
  304. writel(0, &regs->dma_fifo);
  305. if (req->bRequestType & USB_DIR_IN)
  306. ep0_desc.bEndpointAddress = USB_DIR_IN;
  307. else
  308. ep0_desc.bEndpointAddress = USB_DIR_OUT;
  309. ret = CX_IDLE;
  310. if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  311. switch (req->bRequest) {
  312. case USB_REQ_SET_CONFIGURATION:
  313. debug("fotg210: set_cfg(%d)\n", req->wValue & 0x00FF);
  314. if (!(req->wValue & 0x00FF)) {
  315. chip->state = USB_STATE_ADDRESS;
  316. writel(chip->addr, &regs->dev_addr);
  317. } else {
  318. chip->state = USB_STATE_CONFIGURED;
  319. writel(chip->addr | DEVADDR_CONF,
  320. &regs->dev_addr);
  321. }
  322. ret = CX_IDLE;
  323. break;
  324. case USB_REQ_SET_ADDRESS:
  325. debug("fotg210: set_addr(0x%04X)\n", req->wValue);
  326. chip->state = USB_STATE_ADDRESS;
  327. chip->addr = req->wValue & DEVADDR_ADDR_MASK;
  328. ret = CX_FINISH;
  329. writel(chip->addr, &regs->dev_addr);
  330. break;
  331. case USB_REQ_CLEAR_FEATURE:
  332. debug("fotg210: clr_feature(%d, %d)\n",
  333. req->bRequestType & 0x03, req->wValue);
  334. switch (req->wValue) {
  335. case 0: /* [Endpoint] halt */
  336. ep_reset(chip, req->wIndex);
  337. ret = CX_FINISH;
  338. break;
  339. case 1: /* [Device] remote wake-up */
  340. case 2: /* [Device] test mode */
  341. default:
  342. ret = CX_STALL;
  343. break;
  344. }
  345. break;
  346. case USB_REQ_SET_FEATURE:
  347. debug("fotg210: set_feature(%d, %d)\n",
  348. req->wValue, req->wIndex & 0xf);
  349. switch (req->wValue) {
  350. case 0: /* Endpoint Halt */
  351. id = req->wIndex & 0xf;
  352. setbits_le32(&regs->iep[id - 1], IEP_STALL);
  353. setbits_le32(&regs->oep[id - 1], OEP_STALL);
  354. ret = CX_FINISH;
  355. break;
  356. case 1: /* Remote Wakeup */
  357. case 2: /* Test Mode */
  358. default:
  359. ret = CX_STALL;
  360. break;
  361. }
  362. break;
  363. case USB_REQ_GET_STATUS:
  364. debug("fotg210: get_status\n");
  365. ret = CX_STALL;
  366. break;
  367. case USB_REQ_SET_DESCRIPTOR:
  368. debug("fotg210: set_descriptor\n");
  369. ret = CX_STALL;
  370. break;
  371. case USB_REQ_SYNCH_FRAME:
  372. debug("fotg210: sync frame\n");
  373. ret = CX_STALL;
  374. break;
  375. }
  376. } /* if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) */
  377. if (ret == CX_IDLE && chip->driver->setup) {
  378. if (chip->driver->setup(&chip->gadget, req) < 0)
  379. ret = CX_STALL;
  380. else
  381. ret = CX_FINISH;
  382. }
  383. switch (ret) {
  384. case CX_FINISH:
  385. setbits_le32(&regs->cxfifo, CXFIFO_CXFIN);
  386. break;
  387. case CX_STALL:
  388. setbits_le32(&regs->cxfifo, CXFIFO_CXSTALL | CXFIFO_CXFIN);
  389. printf("fotg210: cx_stall!\n");
  390. break;
  391. case CX_IDLE:
  392. debug("fotg210: cx_idle?\n");
  393. default:
  394. break;
  395. }
  396. }
  397. /*
  398. * fifo - FIFO id
  399. * zlp - zero length packet
  400. */
  401. static void fotg210_recv(struct fotg210_chip *chip, int ep_id)
  402. {
  403. struct fotg210_regs *regs = chip->regs;
  404. struct fotg210_ep *ep = chip->ep + ep_id;
  405. struct fotg210_request *req;
  406. int len;
  407. if (ep->stopped || (ep->desc->bEndpointAddress & USB_DIR_IN)) {
  408. printf("fotg210: ep%d recv, invalid!\n", ep->id);
  409. return;
  410. }
  411. if (list_empty(&ep->queue)) {
  412. printf("fotg210: ep%d recv, drop!\n", ep->id);
  413. return;
  414. }
  415. req = list_first_entry(&ep->queue, struct fotg210_request, queue);
  416. len = fotg210_dma(ep, req);
  417. if (len < ep->ep.maxpacket || req->req.length <= req->req.actual) {
  418. list_del_init(&req->queue);
  419. if (req->req.complete)
  420. req->req.complete(&ep->ep, &req->req);
  421. }
  422. if (ep->id > 0 && list_empty(&ep->queue)) {
  423. setbits_le32(&regs->gimr1,
  424. GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id)));
  425. }
  426. }
  427. /*
  428. * USB Gadget Layer
  429. */
  430. static int fotg210_ep_enable(
  431. struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  432. {
  433. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  434. struct fotg210_chip *chip = ep->chip;
  435. struct fotg210_regs *regs = chip->regs;
  436. int id = ep_to_fifo(chip, ep->id);
  437. int in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0;
  438. if (!_ep || !desc
  439. || desc->bDescriptorType != USB_DT_ENDPOINT
  440. || le16_to_cpu(desc->wMaxPacketSize) == 0) {
  441. printf("fotg210: bad ep or descriptor\n");
  442. return -EINVAL;
  443. }
  444. ep->desc = desc;
  445. ep->stopped = 0;
  446. if (in)
  447. setbits_le32(&regs->fifomap, FIFOMAP(id, FIFOMAP_IN));
  448. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  449. case USB_ENDPOINT_XFER_CONTROL:
  450. return -EINVAL;
  451. case USB_ENDPOINT_XFER_ISOC:
  452. setbits_le32(&regs->fifocfg,
  453. FIFOCFG(id, FIFOCFG_EN | FIFOCFG_ISOC));
  454. break;
  455. case USB_ENDPOINT_XFER_BULK:
  456. setbits_le32(&regs->fifocfg,
  457. FIFOCFG(id, FIFOCFG_EN | FIFOCFG_BULK));
  458. break;
  459. case USB_ENDPOINT_XFER_INT:
  460. setbits_le32(&regs->fifocfg,
  461. FIFOCFG(id, FIFOCFG_EN | FIFOCFG_INTR));
  462. break;
  463. }
  464. return 0;
  465. }
  466. static int fotg210_ep_disable(struct usb_ep *_ep)
  467. {
  468. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  469. struct fotg210_chip *chip = ep->chip;
  470. struct fotg210_regs *regs = chip->regs;
  471. int id = ep_to_fifo(chip, ep->id);
  472. ep->desc = NULL;
  473. ep->stopped = 1;
  474. clrbits_le32(&regs->fifocfg, FIFOCFG(id, FIFOCFG_CFG_MASK));
  475. clrbits_le32(&regs->fifomap, FIFOMAP(id, FIFOMAP_DIR_MASK));
  476. return 0;
  477. }
  478. static struct usb_request *fotg210_ep_alloc_request(
  479. struct usb_ep *_ep, gfp_t gfp_flags)
  480. {
  481. struct fotg210_request *req = malloc(sizeof(*req));
  482. if (req) {
  483. memset(req, 0, sizeof(*req));
  484. INIT_LIST_HEAD(&req->queue);
  485. }
  486. return &req->req;
  487. }
  488. static void fotg210_ep_free_request(
  489. struct usb_ep *_ep, struct usb_request *_req)
  490. {
  491. struct fotg210_request *req;
  492. req = container_of(_req, struct fotg210_request, req);
  493. free(req);
  494. }
  495. static int fotg210_ep_queue(
  496. struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  497. {
  498. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  499. struct fotg210_chip *chip = ep->chip;
  500. struct fotg210_regs *regs = chip->regs;
  501. struct fotg210_request *req;
  502. req = container_of(_req, struct fotg210_request, req);
  503. if (!_req || !_req->complete || !_req->buf
  504. || !list_empty(&req->queue)) {
  505. printf("fotg210: invalid request to ep%d\n", ep->id);
  506. return -EINVAL;
  507. }
  508. if (!chip || chip->state == USB_STATE_SUSPENDED) {
  509. printf("fotg210: request while chip suspended\n");
  510. return -EINVAL;
  511. }
  512. req->req.actual = 0;
  513. req->req.status = -EINPROGRESS;
  514. if (req->req.length == 0) {
  515. req->req.status = 0;
  516. if (req->req.complete)
  517. req->req.complete(&ep->ep, &req->req);
  518. return 0;
  519. }
  520. if (ep->id == 0) {
  521. do {
  522. int len = fotg210_dma(ep, req);
  523. if (len < ep->ep.maxpacket)
  524. break;
  525. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  526. udelay(100);
  527. } while (req->req.length > req->req.actual);
  528. } else {
  529. if (ep->desc->bEndpointAddress & USB_DIR_IN) {
  530. do {
  531. int len = fotg210_dma(ep, req);
  532. if (len < ep->ep.maxpacket)
  533. break;
  534. } while (req->req.length > req->req.actual);
  535. } else {
  536. list_add_tail(&req->queue, &ep->queue);
  537. clrbits_le32(&regs->gimr1,
  538. GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id)));
  539. }
  540. }
  541. if (ep->id == 0 || (ep->desc->bEndpointAddress & USB_DIR_IN)) {
  542. if (req->req.complete)
  543. req->req.complete(&ep->ep, &req->req);
  544. }
  545. return 0;
  546. }
  547. static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  548. {
  549. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  550. struct fotg210_request *req;
  551. /* make sure it's actually queued on this endpoint */
  552. list_for_each_entry(req, &ep->queue, queue) {
  553. if (&req->req == _req)
  554. break;
  555. }
  556. if (&req->req != _req)
  557. return -EINVAL;
  558. /* remove the request */
  559. list_del_init(&req->queue);
  560. /* update status & invoke complete callback */
  561. if (req->req.status == -EINPROGRESS) {
  562. req->req.status = -ECONNRESET;
  563. if (req->req.complete)
  564. req->req.complete(_ep, &req->req);
  565. }
  566. return 0;
  567. }
  568. static int fotg210_ep_halt(struct usb_ep *_ep, int halt)
  569. {
  570. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  571. struct fotg210_chip *chip = ep->chip;
  572. struct fotg210_regs *regs = chip->regs;
  573. int ret = -1;
  574. debug("fotg210: ep%d halt=%d\n", ep->id, halt);
  575. /* Endpoint STALL */
  576. if (ep->id > 0 && ep->id <= CFG_NUM_ENDPOINTS) {
  577. if (halt) {
  578. /* wait until all ep fifo empty */
  579. fotg210_cxwait(chip, 0xf00);
  580. /* stall */
  581. if (ep->desc->bEndpointAddress & USB_DIR_IN) {
  582. setbits_le32(&regs->iep[ep->id - 1],
  583. IEP_STALL);
  584. } else {
  585. setbits_le32(&regs->oep[ep->id - 1],
  586. OEP_STALL);
  587. }
  588. } else {
  589. if (ep->desc->bEndpointAddress & USB_DIR_IN) {
  590. clrbits_le32(&regs->iep[ep->id - 1],
  591. IEP_STALL);
  592. } else {
  593. clrbits_le32(&regs->oep[ep->id - 1],
  594. OEP_STALL);
  595. }
  596. }
  597. ret = 0;
  598. }
  599. return ret;
  600. }
  601. /*
  602. * activate/deactivate link with host.
  603. */
  604. static void pullup(struct fotg210_chip *chip, int is_on)
  605. {
  606. struct fotg210_regs *regs = chip->regs;
  607. if (is_on) {
  608. if (!chip->pullup) {
  609. chip->state = USB_STATE_POWERED;
  610. chip->pullup = 1;
  611. /* enable the chip */
  612. setbits_le32(&regs->dev_ctrl, DEVCTRL_EN);
  613. /* clear unplug bit (BIT0) */
  614. clrbits_le32(&regs->phy_tmsr, PHYTMSR_UNPLUG);
  615. }
  616. } else {
  617. chip->state = USB_STATE_NOTATTACHED;
  618. chip->pullup = 0;
  619. chip->addr = 0;
  620. writel(chip->addr, &regs->dev_addr);
  621. /* set unplug bit (BIT0) */
  622. setbits_le32(&regs->phy_tmsr, PHYTMSR_UNPLUG);
  623. /* disable the chip */
  624. clrbits_le32(&regs->dev_ctrl, DEVCTRL_EN);
  625. }
  626. }
  627. static int fotg210_pullup(struct usb_gadget *_gadget, int is_on)
  628. {
  629. struct fotg210_chip *chip;
  630. chip = container_of(_gadget, struct fotg210_chip, gadget);
  631. debug("fotg210: pullup=%d\n", is_on);
  632. pullup(chip, is_on);
  633. return 0;
  634. }
  635. static int fotg210_get_frame(struct usb_gadget *_gadget)
  636. {
  637. struct fotg210_chip *chip;
  638. struct fotg210_regs *regs;
  639. chip = container_of(_gadget, struct fotg210_chip, gadget);
  640. regs = chip->regs;
  641. return SOFFNR_FNR(readl(&regs->sof_fnr));
  642. }
  643. static struct usb_gadget_ops fotg210_gadget_ops = {
  644. .get_frame = fotg210_get_frame,
  645. .pullup = fotg210_pullup,
  646. };
  647. static struct usb_ep_ops fotg210_ep_ops = {
  648. .enable = fotg210_ep_enable,
  649. .disable = fotg210_ep_disable,
  650. .queue = fotg210_ep_queue,
  651. .dequeue = fotg210_ep_dequeue,
  652. .set_halt = fotg210_ep_halt,
  653. .alloc_request = fotg210_ep_alloc_request,
  654. .free_request = fotg210_ep_free_request,
  655. };
  656. static struct fotg210_chip controller = {
  657. .regs = (void __iomem *)CONFIG_FOTG210_BASE,
  658. .gadget = {
  659. .name = "fotg210_udc",
  660. .ops = &fotg210_gadget_ops,
  661. .ep0 = &controller.ep[0].ep,
  662. .speed = USB_SPEED_UNKNOWN,
  663. .is_dualspeed = 1,
  664. .is_otg = 0,
  665. .is_a_peripheral = 0,
  666. .b_hnp_enable = 0,
  667. .a_hnp_support = 0,
  668. .a_alt_hnp_support = 0,
  669. },
  670. .ep[0] = {
  671. .id = 0,
  672. .ep = {
  673. .name = "ep0",
  674. .ops = &fotg210_ep_ops,
  675. },
  676. .desc = &ep0_desc,
  677. .chip = &controller,
  678. .maxpacket = CFG_EP0_MAX_PACKET_SIZE,
  679. },
  680. .ep[1] = {
  681. .id = 1,
  682. .ep = {
  683. .name = "ep1",
  684. .ops = &fotg210_ep_ops,
  685. },
  686. .chip = &controller,
  687. .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
  688. },
  689. .ep[2] = {
  690. .id = 2,
  691. .ep = {
  692. .name = "ep2",
  693. .ops = &fotg210_ep_ops,
  694. },
  695. .chip = &controller,
  696. .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
  697. },
  698. .ep[3] = {
  699. .id = 3,
  700. .ep = {
  701. .name = "ep3",
  702. .ops = &fotg210_ep_ops,
  703. },
  704. .chip = &controller,
  705. .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
  706. },
  707. .ep[4] = {
  708. .id = 4,
  709. .ep = {
  710. .name = "ep4",
  711. .ops = &fotg210_ep_ops,
  712. },
  713. .chip = &controller,
  714. .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
  715. },
  716. };
  717. int usb_gadget_handle_interrupts(int index)
  718. {
  719. struct fotg210_chip *chip = &controller;
  720. struct fotg210_regs *regs = chip->regs;
  721. uint32_t id, st, isr, gisr;
  722. isr = readl(&regs->isr) & (~readl(&regs->imr));
  723. gisr = readl(&regs->gisr) & (~readl(&regs->gimr));
  724. if (!(isr & ISR_DEV) || !gisr)
  725. return 0;
  726. writel(ISR_DEV, &regs->isr);
  727. /* CX interrupts */
  728. if (gisr & GISR_GRP0) {
  729. st = readl(&regs->gisr0);
  730. /*
  731. * Write 1 and then 0 works for both W1C & RW.
  732. *
  733. * HW v1.11.0+: It's a W1C register (write 1 clear)
  734. * HW v1.10.0-: It's a R/W register (write 0 clear)
  735. */
  736. writel(st & GISR0_CXABORT, &regs->gisr0);
  737. writel(0, &regs->gisr0);
  738. if (st & GISR0_CXERR)
  739. printf("fotg210: cmd error\n");
  740. if (st & GISR0_CXABORT)
  741. printf("fotg210: cmd abort\n");
  742. if (st & GISR0_CXSETUP) /* setup */
  743. fotg210_setup(chip);
  744. else if (st & GISR0_CXEND) /* command finish */
  745. setbits_le32(&regs->cxfifo, CXFIFO_CXFIN);
  746. }
  747. /* FIFO interrupts */
  748. if (gisr & GISR_GRP1) {
  749. st = readl(&regs->gisr1);
  750. for (id = 0; id < 4; ++id) {
  751. if (st & GISR1_RX_FIFO(id))
  752. fotg210_recv(chip, fifo_to_ep(chip, id, 0));
  753. }
  754. }
  755. /* Device Status Interrupts */
  756. if (gisr & GISR_GRP2) {
  757. st = readl(&regs->gisr2);
  758. /*
  759. * Write 1 and then 0 works for both W1C & RW.
  760. *
  761. * HW v1.11.0+: It's a W1C register (write 1 clear)
  762. * HW v1.10.0-: It's a R/W register (write 0 clear)
  763. */
  764. writel(st, &regs->gisr2);
  765. writel(0, &regs->gisr2);
  766. if (st & GISR2_RESET)
  767. printf("fotg210: reset by host\n");
  768. else if (st & GISR2_SUSPEND)
  769. printf("fotg210: suspend/removed\n");
  770. else if (st & GISR2_RESUME)
  771. printf("fotg210: resume\n");
  772. /* Errors */
  773. if (st & GISR2_ISOCERR)
  774. printf("fotg210: iso error\n");
  775. if (st & GISR2_ISOCABT)
  776. printf("fotg210: iso abort\n");
  777. if (st & GISR2_DMAERR)
  778. printf("fotg210: dma error\n");
  779. }
  780. return 0;
  781. }
  782. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  783. {
  784. int i, ret = 0;
  785. struct fotg210_chip *chip = &controller;
  786. if (!driver || !driver->bind || !driver->setup) {
  787. puts("fotg210: bad parameter.\n");
  788. return -EINVAL;
  789. }
  790. INIT_LIST_HEAD(&chip->gadget.ep_list);
  791. for (i = 0; i < CFG_NUM_ENDPOINTS + 1; ++i) {
  792. struct fotg210_ep *ep = chip->ep + i;
  793. ep->ep.maxpacket = ep->maxpacket;
  794. INIT_LIST_HEAD(&ep->queue);
  795. if (ep->id == 0) {
  796. ep->stopped = 0;
  797. } else {
  798. ep->stopped = 1;
  799. list_add_tail(&ep->ep.ep_list, &chip->gadget.ep_list);
  800. }
  801. }
  802. if (fotg210_reset(chip)) {
  803. puts("fotg210: reset failed.\n");
  804. return -EINVAL;
  805. }
  806. ret = driver->bind(&chip->gadget);
  807. if (ret) {
  808. debug("fotg210: driver->bind() returned %d\n", ret);
  809. return ret;
  810. }
  811. chip->driver = driver;
  812. return ret;
  813. }
  814. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  815. {
  816. struct fotg210_chip *chip = &controller;
  817. driver->unbind(&chip->gadget);
  818. chip->driver = NULL;
  819. pullup(chip, 0);
  820. return 0;
  821. }