smsc95xx.c 26 KB

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  1. /*
  2. * Copyright (c) 2015 Google, Inc
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * Copyright (C) 2009 NVIDIA, Corporation
  5. * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <malloc.h>
  13. #include <memalign.h>
  14. #include <usb.h>
  15. #include <asm/unaligned.h>
  16. #include <linux/mii.h>
  17. #include "usb_ether.h"
  18. /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
  19. /* LED defines */
  20. #define LED_GPIO_CFG (0x24)
  21. #define LED_GPIO_CFG_SPD_LED (0x01000000)
  22. #define LED_GPIO_CFG_LNK_LED (0x00100000)
  23. #define LED_GPIO_CFG_FDX_LED (0x00010000)
  24. /* Tx command words */
  25. #define TX_CMD_A_FIRST_SEG_ 0x00002000
  26. #define TX_CMD_A_LAST_SEG_ 0x00001000
  27. /* Rx status word */
  28. #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
  29. #define RX_STS_ES_ 0x00008000 /* Error Summary */
  30. /* SCSRs */
  31. #define ID_REV 0x00
  32. #define INT_STS 0x08
  33. #define TX_CFG 0x10
  34. #define TX_CFG_ON_ 0x00000004
  35. #define HW_CFG 0x14
  36. #define HW_CFG_BIR_ 0x00001000
  37. #define HW_CFG_RXDOFF_ 0x00000600
  38. #define HW_CFG_MEF_ 0x00000020
  39. #define HW_CFG_BCE_ 0x00000002
  40. #define HW_CFG_LRST_ 0x00000008
  41. #define PM_CTRL 0x20
  42. #define PM_CTL_PHY_RST_ 0x00000010
  43. #define AFC_CFG 0x2C
  44. /*
  45. * Hi watermark = 15.5Kb (~10 mtu pkts)
  46. * low watermark = 3k (~2 mtu pkts)
  47. * backpressure duration = ~ 350us
  48. * Apply FC on any frame.
  49. */
  50. #define AFC_CFG_DEFAULT 0x00F830A1
  51. #define E2P_CMD 0x30
  52. #define E2P_CMD_BUSY_ 0x80000000
  53. #define E2P_CMD_READ_ 0x00000000
  54. #define E2P_CMD_TIMEOUT_ 0x00000400
  55. #define E2P_CMD_LOADED_ 0x00000200
  56. #define E2P_CMD_ADDR_ 0x000001FF
  57. #define E2P_DATA 0x34
  58. #define BURST_CAP 0x38
  59. #define INT_EP_CTL 0x68
  60. #define INT_EP_CTL_PHY_INT_ 0x00008000
  61. #define BULK_IN_DLY 0x6C
  62. /* MAC CSRs */
  63. #define MAC_CR 0x100
  64. #define MAC_CR_MCPAS_ 0x00080000
  65. #define MAC_CR_PRMS_ 0x00040000
  66. #define MAC_CR_HPFILT_ 0x00002000
  67. #define MAC_CR_TXEN_ 0x00000008
  68. #define MAC_CR_RXEN_ 0x00000004
  69. #define ADDRH 0x104
  70. #define ADDRL 0x108
  71. #define MII_ADDR 0x114
  72. #define MII_WRITE_ 0x02
  73. #define MII_BUSY_ 0x01
  74. #define MII_READ_ 0x00 /* ~of MII Write bit */
  75. #define MII_DATA 0x118
  76. #define FLOW 0x11C
  77. #define VLAN1 0x120
  78. #define COE_CR 0x130
  79. #define Tx_COE_EN_ 0x00010000
  80. #define Rx_COE_EN_ 0x00000001
  81. /* Vendor-specific PHY Definitions */
  82. #define PHY_INT_SRC 29
  83. #define PHY_INT_MASK 30
  84. #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
  85. #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
  86. #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
  87. PHY_INT_MASK_LINK_DOWN_)
  88. /* USB Vendor Requests */
  89. #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
  90. #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
  91. /* Some extra defines */
  92. #define HS_USB_PKT_SIZE 512
  93. #define FS_USB_PKT_SIZE 64
  94. /* 5/33 is lower limit for BURST_CAP to work */
  95. #define DEFAULT_HS_BURST_CAP_SIZE (5 * HS_USB_PKT_SIZE)
  96. #define DEFAULT_FS_BURST_CAP_SIZE (33 * FS_USB_PKT_SIZE)
  97. #define DEFAULT_BULK_IN_DELAY 0x00002000
  98. #define MAX_SINGLE_PACKET_SIZE 2048
  99. #define EEPROM_MAC_OFFSET 0x01
  100. #define SMSC95XX_INTERNAL_PHY_ID 1
  101. #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
  102. /* local defines */
  103. #define SMSC95XX_BASE_NAME "sms"
  104. #define USB_CTRL_SET_TIMEOUT 5000
  105. #define USB_CTRL_GET_TIMEOUT 5000
  106. #define USB_BULK_SEND_TIMEOUT 5000
  107. #define USB_BULK_RECV_TIMEOUT 5000
  108. #define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE
  109. #define PHY_CONNECT_TIMEOUT 5000
  110. #define TURBO_MODE
  111. #ifndef CONFIG_DM_ETH
  112. /* local vars */
  113. static int curr_eth_dev; /* index for name of next device detected */
  114. #endif
  115. /* driver private */
  116. struct smsc95xx_private {
  117. #ifdef CONFIG_DM_ETH
  118. struct ueth_data ueth;
  119. #endif
  120. size_t rx_urb_size; /* maximum USB URB size */
  121. u32 mac_cr; /* MAC control register value */
  122. int have_hwaddr; /* 1 if we have a hardware MAC address */
  123. };
  124. /*
  125. * Smsc95xx infrastructure commands
  126. */
  127. static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
  128. {
  129. int len;
  130. ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
  131. cpu_to_le32s(&data);
  132. tmpbuf[0] = data;
  133. len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
  134. USB_VENDOR_REQUEST_WRITE_REGISTER,
  135. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  136. 0, index, tmpbuf, sizeof(data),
  137. USB_CTRL_SET_TIMEOUT);
  138. if (len != sizeof(data)) {
  139. debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
  140. index, data, len);
  141. return -EIO;
  142. }
  143. return 0;
  144. }
  145. static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
  146. {
  147. int len;
  148. ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
  149. len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
  150. USB_VENDOR_REQUEST_READ_REGISTER,
  151. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  152. 0, index, tmpbuf, sizeof(*data),
  153. USB_CTRL_GET_TIMEOUT);
  154. *data = tmpbuf[0];
  155. if (len != sizeof(*data)) {
  156. debug("smsc95xx_read_reg failed: index=%d, len=%d",
  157. index, len);
  158. return -EIO;
  159. }
  160. le32_to_cpus(data);
  161. return 0;
  162. }
  163. /* Loop until the read is completed with timeout */
  164. static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
  165. {
  166. unsigned long start_time = get_timer(0);
  167. u32 val;
  168. do {
  169. smsc95xx_read_reg(udev, MII_ADDR, &val);
  170. if (!(val & MII_BUSY_))
  171. return 0;
  172. } while (get_timer(start_time) < 1000);
  173. return -ETIMEDOUT;
  174. }
  175. static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
  176. {
  177. u32 val, addr;
  178. /* confirm MII not busy */
  179. if (smsc95xx_phy_wait_not_busy(udev)) {
  180. debug("MII is busy in smsc95xx_mdio_read\n");
  181. return -ETIMEDOUT;
  182. }
  183. /* set the address, index & direction (read from PHY) */
  184. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  185. smsc95xx_write_reg(udev, MII_ADDR, addr);
  186. if (smsc95xx_phy_wait_not_busy(udev)) {
  187. debug("Timed out reading MII reg %02X\n", idx);
  188. return -ETIMEDOUT;
  189. }
  190. smsc95xx_read_reg(udev, MII_DATA, &val);
  191. return (u16)(val & 0xFFFF);
  192. }
  193. static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
  194. int regval)
  195. {
  196. u32 val, addr;
  197. /* confirm MII not busy */
  198. if (smsc95xx_phy_wait_not_busy(udev)) {
  199. debug("MII is busy in smsc95xx_mdio_write\n");
  200. return;
  201. }
  202. val = regval;
  203. smsc95xx_write_reg(udev, MII_DATA, val);
  204. /* set the address, index & direction (write to PHY) */
  205. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  206. smsc95xx_write_reg(udev, MII_ADDR, addr);
  207. if (smsc95xx_phy_wait_not_busy(udev))
  208. debug("Timed out writing MII reg %02X\n", idx);
  209. }
  210. static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
  211. {
  212. unsigned long start_time = get_timer(0);
  213. u32 val;
  214. do {
  215. smsc95xx_read_reg(udev, E2P_CMD, &val);
  216. if (!(val & E2P_CMD_BUSY_))
  217. return 0;
  218. udelay(40);
  219. } while (get_timer(start_time) < 1 * 1000 * 1000);
  220. debug("EEPROM is busy\n");
  221. return -ETIMEDOUT;
  222. }
  223. static int smsc95xx_wait_eeprom(struct usb_device *udev)
  224. {
  225. unsigned long start_time = get_timer(0);
  226. u32 val;
  227. do {
  228. smsc95xx_read_reg(udev, E2P_CMD, &val);
  229. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  230. break;
  231. udelay(40);
  232. } while (get_timer(start_time) < 1 * 1000 * 1000);
  233. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  234. debug("EEPROM read operation timeout\n");
  235. return -ETIMEDOUT;
  236. }
  237. return 0;
  238. }
  239. static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
  240. u8 *data)
  241. {
  242. u32 val;
  243. int i, ret;
  244. ret = smsc95xx_eeprom_confirm_not_busy(udev);
  245. if (ret)
  246. return ret;
  247. for (i = 0; i < length; i++) {
  248. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  249. smsc95xx_write_reg(udev, E2P_CMD, val);
  250. ret = smsc95xx_wait_eeprom(udev);
  251. if (ret < 0)
  252. return ret;
  253. smsc95xx_read_reg(udev, E2P_DATA, &val);
  254. data[i] = val & 0xFF;
  255. offset++;
  256. }
  257. return 0;
  258. }
  259. /*
  260. * mii_nway_restart - restart NWay (autonegotiation) for this interface
  261. *
  262. * Returns 0 on success, negative on error.
  263. */
  264. static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
  265. {
  266. int bmcr;
  267. int r = -1;
  268. /* if autoneg is off, it's an error */
  269. bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
  270. if (bmcr & BMCR_ANENABLE) {
  271. bmcr |= BMCR_ANRESTART;
  272. smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
  273. r = 0;
  274. }
  275. return r;
  276. }
  277. static int smsc95xx_phy_initialize(struct usb_device *udev,
  278. struct ueth_data *dev)
  279. {
  280. smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
  281. smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
  282. ADVERTISE_ALL | ADVERTISE_CSMA |
  283. ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  284. /* read to clear */
  285. smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
  286. smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
  287. PHY_INT_MASK_DEFAULT_);
  288. mii_nway_restart(udev, dev);
  289. debug("phy initialised succesfully\n");
  290. return 0;
  291. }
  292. static int smsc95xx_init_mac_address(unsigned char *enetaddr,
  293. struct usb_device *udev)
  294. {
  295. int ret;
  296. /* try reading mac address from EEPROM */
  297. ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
  298. if (ret)
  299. return ret;
  300. if (is_valid_ethaddr(enetaddr)) {
  301. /* eeprom values are valid so use them */
  302. debug("MAC address read from EEPROM\n");
  303. return 0;
  304. }
  305. /*
  306. * No eeprom, or eeprom values are invalid. Generating a random MAC
  307. * address is not safe. Just return an error.
  308. */
  309. debug("Invalid MAC address read from EEPROM\n");
  310. return -ENXIO;
  311. }
  312. static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
  313. struct smsc95xx_private *priv,
  314. unsigned char *enetaddr)
  315. {
  316. u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
  317. u32 addr_hi = get_unaligned_le16(&enetaddr[4]);
  318. int ret;
  319. /* set hardware address */
  320. debug("** %s()\n", __func__);
  321. ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
  322. if (ret < 0)
  323. return ret;
  324. ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
  325. if (ret < 0)
  326. return ret;
  327. debug("MAC %pM\n", enetaddr);
  328. priv->have_hwaddr = 1;
  329. return 0;
  330. }
  331. /* Enable or disable Tx & Rx checksum offload engines */
  332. static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
  333. int use_rx_csum)
  334. {
  335. u32 read_buf;
  336. int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
  337. if (ret < 0)
  338. return ret;
  339. if (use_tx_csum)
  340. read_buf |= Tx_COE_EN_;
  341. else
  342. read_buf &= ~Tx_COE_EN_;
  343. if (use_rx_csum)
  344. read_buf |= Rx_COE_EN_;
  345. else
  346. read_buf &= ~Rx_COE_EN_;
  347. ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
  348. if (ret < 0)
  349. return ret;
  350. debug("COE_CR = 0x%08x\n", read_buf);
  351. return 0;
  352. }
  353. static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
  354. {
  355. /* No multicast in u-boot */
  356. priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  357. }
  358. /* starts the TX path */
  359. static void smsc95xx_start_tx_path(struct usb_device *udev,
  360. struct smsc95xx_private *priv)
  361. {
  362. u32 reg_val;
  363. /* Enable Tx at MAC */
  364. priv->mac_cr |= MAC_CR_TXEN_;
  365. smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
  366. /* Enable Tx at SCSRs */
  367. reg_val = TX_CFG_ON_;
  368. smsc95xx_write_reg(udev, TX_CFG, reg_val);
  369. }
  370. /* Starts the Receive path */
  371. static void smsc95xx_start_rx_path(struct usb_device *udev,
  372. struct smsc95xx_private *priv)
  373. {
  374. priv->mac_cr |= MAC_CR_RXEN_;
  375. smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
  376. }
  377. static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
  378. struct smsc95xx_private *priv,
  379. unsigned char *enetaddr)
  380. {
  381. int ret;
  382. u32 write_buf;
  383. u32 read_buf;
  384. u32 burst_cap;
  385. int timeout;
  386. #define TIMEOUT_RESOLUTION 50 /* ms */
  387. int link_detected;
  388. debug("** %s()\n", __func__);
  389. dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
  390. write_buf = HW_CFG_LRST_;
  391. ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
  392. if (ret < 0)
  393. return ret;
  394. timeout = 0;
  395. do {
  396. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  397. if (ret < 0)
  398. return ret;
  399. udelay(10 * 1000);
  400. timeout++;
  401. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  402. if (timeout >= 100) {
  403. debug("timeout waiting for completion of Lite Reset\n");
  404. return -ETIMEDOUT;
  405. }
  406. write_buf = PM_CTL_PHY_RST_;
  407. ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
  408. if (ret < 0)
  409. return ret;
  410. timeout = 0;
  411. do {
  412. ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
  413. if (ret < 0)
  414. return ret;
  415. udelay(10 * 1000);
  416. timeout++;
  417. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  418. if (timeout >= 100) {
  419. debug("timeout waiting for PHY Reset\n");
  420. return -ETIMEDOUT;
  421. }
  422. #ifndef CONFIG_DM_ETH
  423. if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
  424. 0)
  425. priv->have_hwaddr = 1;
  426. #endif
  427. if (!priv->have_hwaddr) {
  428. puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
  429. return -EADDRNOTAVAIL;
  430. }
  431. ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
  432. if (ret < 0)
  433. return ret;
  434. #ifdef TURBO_MODE
  435. if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
  436. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  437. priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  438. } else {
  439. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  440. priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  441. }
  442. #else
  443. burst_cap = 0;
  444. priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  445. #endif
  446. debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
  447. ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
  448. if (ret < 0)
  449. return ret;
  450. ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
  451. if (ret < 0)
  452. return ret;
  453. debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
  454. read_buf = DEFAULT_BULK_IN_DELAY;
  455. ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
  456. if (ret < 0)
  457. return ret;
  458. ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
  459. if (ret < 0)
  460. return ret;
  461. debug("Read Value from BULK_IN_DLY after writing: "
  462. "0x%08x\n", read_buf);
  463. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  464. if (ret < 0)
  465. return ret;
  466. debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
  467. #ifdef TURBO_MODE
  468. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  469. #endif
  470. read_buf &= ~HW_CFG_RXDOFF_;
  471. #define NET_IP_ALIGN 0
  472. read_buf |= NET_IP_ALIGN << 9;
  473. ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
  474. if (ret < 0)
  475. return ret;
  476. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  477. if (ret < 0)
  478. return ret;
  479. debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  480. write_buf = 0xFFFFFFFF;
  481. ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
  482. if (ret < 0)
  483. return ret;
  484. ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
  485. if (ret < 0)
  486. return ret;
  487. debug("ID_REV = 0x%08x\n", read_buf);
  488. /* Configure GPIO pins as LED outputs */
  489. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  490. LED_GPIO_CFG_FDX_LED;
  491. ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
  492. if (ret < 0)
  493. return ret;
  494. debug("LED_GPIO_CFG set\n");
  495. /* Init Tx */
  496. write_buf = 0;
  497. ret = smsc95xx_write_reg(udev, FLOW, write_buf);
  498. if (ret < 0)
  499. return ret;
  500. read_buf = AFC_CFG_DEFAULT;
  501. ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
  502. if (ret < 0)
  503. return ret;
  504. ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
  505. if (ret < 0)
  506. return ret;
  507. /* Init Rx. Set Vlan */
  508. write_buf = (u32)ETH_P_8021Q;
  509. ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
  510. if (ret < 0)
  511. return ret;
  512. /* Disable checksum offload engines */
  513. ret = smsc95xx_set_csums(udev, 0, 0);
  514. if (ret < 0) {
  515. debug("Failed to set csum offload: %d\n", ret);
  516. return ret;
  517. }
  518. smsc95xx_set_multicast(priv);
  519. ret = smsc95xx_phy_initialize(udev, dev);
  520. if (ret < 0)
  521. return ret;
  522. ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
  523. if (ret < 0)
  524. return ret;
  525. /* enable PHY interrupts */
  526. read_buf |= INT_EP_CTL_PHY_INT_;
  527. ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
  528. if (ret < 0)
  529. return ret;
  530. smsc95xx_start_tx_path(udev, priv);
  531. smsc95xx_start_rx_path(udev, priv);
  532. timeout = 0;
  533. do {
  534. link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
  535. & BMSR_LSTATUS;
  536. if (!link_detected) {
  537. if (timeout == 0)
  538. printf("Waiting for Ethernet connection... ");
  539. udelay(TIMEOUT_RESOLUTION * 1000);
  540. timeout += TIMEOUT_RESOLUTION;
  541. }
  542. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  543. if (link_detected) {
  544. if (timeout != 0)
  545. printf("done.\n");
  546. } else {
  547. printf("unable to connect.\n");
  548. return -EIO;
  549. }
  550. return 0;
  551. }
  552. static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
  553. {
  554. int err;
  555. int actual_len;
  556. u32 tx_cmd_a;
  557. u32 tx_cmd_b;
  558. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
  559. PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
  560. debug("** %s(), len %d, buf %#x\n", __func__, length,
  561. (unsigned int)(ulong)msg);
  562. if (length > PKTSIZE)
  563. return -ENOSPC;
  564. tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  565. tx_cmd_b = (u32)length;
  566. cpu_to_le32s(&tx_cmd_a);
  567. cpu_to_le32s(&tx_cmd_b);
  568. /* prepend cmd_a and cmd_b */
  569. memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
  570. memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
  571. memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
  572. length);
  573. err = usb_bulk_msg(dev->pusb_dev,
  574. usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
  575. (void *)msg,
  576. length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
  577. &actual_len,
  578. USB_BULK_SEND_TIMEOUT);
  579. debug("Tx: len = %u, actual = %u, err = %d\n",
  580. (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)),
  581. (unsigned int)actual_len, err);
  582. return err;
  583. }
  584. #ifndef CONFIG_DM_ETH
  585. /*
  586. * Smsc95xx callbacks
  587. */
  588. static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
  589. {
  590. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  591. struct usb_device *udev = dev->pusb_dev;
  592. struct smsc95xx_private *priv =
  593. (struct smsc95xx_private *)dev->dev_priv;
  594. return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
  595. }
  596. static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
  597. {
  598. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  599. return smsc95xx_send_common(dev, packet, length);
  600. }
  601. static int smsc95xx_recv(struct eth_device *eth)
  602. {
  603. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  604. DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
  605. unsigned char *buf_ptr;
  606. int err;
  607. int actual_len;
  608. u32 packet_len;
  609. int cur_buf_align;
  610. debug("** %s()\n", __func__);
  611. err = usb_bulk_msg(dev->pusb_dev,
  612. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  613. (void *)recv_buf, RX_URB_SIZE, &actual_len,
  614. USB_BULK_RECV_TIMEOUT);
  615. debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
  616. actual_len, err);
  617. if (err != 0) {
  618. debug("Rx: failed to receive\n");
  619. return -err;
  620. }
  621. if (actual_len > RX_URB_SIZE) {
  622. debug("Rx: received too many bytes %d\n", actual_len);
  623. return -ENOSPC;
  624. }
  625. buf_ptr = recv_buf;
  626. while (actual_len > 0) {
  627. /*
  628. * 1st 4 bytes contain the length of the actual data plus error
  629. * info. Extract data length.
  630. */
  631. if (actual_len < sizeof(packet_len)) {
  632. debug("Rx: incomplete packet length\n");
  633. return -EIO;
  634. }
  635. memcpy(&packet_len, buf_ptr, sizeof(packet_len));
  636. le32_to_cpus(&packet_len);
  637. if (packet_len & RX_STS_ES_) {
  638. debug("Rx: Error header=%#x", packet_len);
  639. return -EIO;
  640. }
  641. packet_len = ((packet_len & RX_STS_FL_) >> 16);
  642. if (packet_len > actual_len - sizeof(packet_len)) {
  643. debug("Rx: too large packet: %d\n", packet_len);
  644. return -EIO;
  645. }
  646. /* Notify net stack */
  647. net_process_received_packet(buf_ptr + sizeof(packet_len),
  648. packet_len - 4);
  649. /* Adjust for next iteration */
  650. actual_len -= sizeof(packet_len) + packet_len;
  651. buf_ptr += sizeof(packet_len) + packet_len;
  652. cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf;
  653. if (cur_buf_align & 0x03) {
  654. int align = 4 - (cur_buf_align & 0x03);
  655. actual_len -= align;
  656. buf_ptr += align;
  657. }
  658. }
  659. return err;
  660. }
  661. static void smsc95xx_halt(struct eth_device *eth)
  662. {
  663. debug("** %s()\n", __func__);
  664. }
  665. static int smsc95xx_write_hwaddr(struct eth_device *eth)
  666. {
  667. struct ueth_data *dev = eth->priv;
  668. struct usb_device *udev = dev->pusb_dev;
  669. struct smsc95xx_private *priv = dev->dev_priv;
  670. return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
  671. }
  672. /*
  673. * SMSC probing functions
  674. */
  675. void smsc95xx_eth_before_probe(void)
  676. {
  677. curr_eth_dev = 0;
  678. }
  679. struct smsc95xx_dongle {
  680. unsigned short vendor;
  681. unsigned short product;
  682. };
  683. static const struct smsc95xx_dongle smsc95xx_dongles[] = {
  684. { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
  685. { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
  686. { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
  687. { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
  688. { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
  689. { 0x0000, 0x0000 } /* END - Do not remove */
  690. };
  691. /* Probe to see if a new device is actually an SMSC device */
  692. int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
  693. struct ueth_data *ss)
  694. {
  695. struct usb_interface *iface;
  696. struct usb_interface_descriptor *iface_desc;
  697. int i;
  698. /* let's examine the device now */
  699. iface = &dev->config.if_desc[ifnum];
  700. iface_desc = &dev->config.if_desc[ifnum].desc;
  701. for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
  702. if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
  703. dev->descriptor.idProduct == smsc95xx_dongles[i].product)
  704. /* Found a supported dongle */
  705. break;
  706. }
  707. if (smsc95xx_dongles[i].vendor == 0)
  708. return 0;
  709. /* At this point, we know we've got a live one */
  710. debug("\n\nUSB Ethernet device detected\n");
  711. memset(ss, '\0', sizeof(struct ueth_data));
  712. /* Initialize the ueth_data structure with some useful info */
  713. ss->ifnum = ifnum;
  714. ss->pusb_dev = dev;
  715. ss->subclass = iface_desc->bInterfaceSubClass;
  716. ss->protocol = iface_desc->bInterfaceProtocol;
  717. /*
  718. * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
  719. * We will ignore any others.
  720. */
  721. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  722. /* is it an BULK endpoint? */
  723. if ((iface->ep_desc[i].bmAttributes &
  724. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
  725. if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
  726. ss->ep_in =
  727. iface->ep_desc[i].bEndpointAddress &
  728. USB_ENDPOINT_NUMBER_MASK;
  729. else
  730. ss->ep_out =
  731. iface->ep_desc[i].bEndpointAddress &
  732. USB_ENDPOINT_NUMBER_MASK;
  733. }
  734. /* is it an interrupt endpoint? */
  735. if ((iface->ep_desc[i].bmAttributes &
  736. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  737. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  738. USB_ENDPOINT_NUMBER_MASK;
  739. ss->irqinterval = iface->ep_desc[i].bInterval;
  740. }
  741. }
  742. debug("Endpoints In %d Out %d Int %d\n",
  743. ss->ep_in, ss->ep_out, ss->ep_int);
  744. /* Do some basic sanity checks, and bail if we find a problem */
  745. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  746. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  747. debug("Problems with device\n");
  748. return 0;
  749. }
  750. dev->privptr = (void *)ss;
  751. /* alloc driver private */
  752. ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
  753. if (!ss->dev_priv)
  754. return 0;
  755. return 1;
  756. }
  757. int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  758. struct eth_device *eth)
  759. {
  760. debug("** %s()\n", __func__);
  761. if (!eth) {
  762. debug("%s: missing parameter.\n", __func__);
  763. return 0;
  764. }
  765. sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
  766. eth->init = smsc95xx_init;
  767. eth->send = smsc95xx_send;
  768. eth->recv = smsc95xx_recv;
  769. eth->halt = smsc95xx_halt;
  770. eth->write_hwaddr = smsc95xx_write_hwaddr;
  771. eth->priv = ss;
  772. return 1;
  773. }
  774. #endif /* !CONFIG_DM_ETH */
  775. #ifdef CONFIG_DM_ETH
  776. static int smsc95xx_eth_start(struct udevice *dev)
  777. {
  778. struct usb_device *udev = dev_get_parent_priv(dev);
  779. struct smsc95xx_private *priv = dev_get_priv(dev);
  780. struct eth_pdata *pdata = dev_get_platdata(dev);
  781. /* Driver-model Ethernet ensures we have this */
  782. priv->have_hwaddr = 1;
  783. return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
  784. }
  785. void smsc95xx_eth_stop(struct udevice *dev)
  786. {
  787. debug("** %s()\n", __func__);
  788. }
  789. int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
  790. {
  791. struct smsc95xx_private *priv = dev_get_priv(dev);
  792. return smsc95xx_send_common(&priv->ueth, packet, length);
  793. }
  794. int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  795. {
  796. struct smsc95xx_private *priv = dev_get_priv(dev);
  797. struct ueth_data *ueth = &priv->ueth;
  798. uint8_t *ptr;
  799. int ret, len;
  800. u32 packet_len;
  801. len = usb_ether_get_rx_bytes(ueth, &ptr);
  802. debug("%s: first try, len=%d\n", __func__, len);
  803. if (!len) {
  804. if (!(flags & ETH_RECV_CHECK_DEVICE))
  805. return -EAGAIN;
  806. ret = usb_ether_receive(ueth, RX_URB_SIZE);
  807. if (ret == -EAGAIN)
  808. return ret;
  809. len = usb_ether_get_rx_bytes(ueth, &ptr);
  810. debug("%s: second try, len=%d\n", __func__, len);
  811. }
  812. /*
  813. * 1st 4 bytes contain the length of the actual data plus error info.
  814. * Extract data length.
  815. */
  816. if (len < sizeof(packet_len)) {
  817. debug("Rx: incomplete packet length\n");
  818. goto err;
  819. }
  820. memcpy(&packet_len, ptr, sizeof(packet_len));
  821. le32_to_cpus(&packet_len);
  822. if (packet_len & RX_STS_ES_) {
  823. debug("Rx: Error header=%#x", packet_len);
  824. goto err;
  825. }
  826. packet_len = ((packet_len & RX_STS_FL_) >> 16);
  827. if (packet_len > len - sizeof(packet_len)) {
  828. debug("Rx: too large packet: %d\n", packet_len);
  829. goto err;
  830. }
  831. *packetp = ptr + sizeof(packet_len);
  832. return packet_len;
  833. err:
  834. usb_ether_advance_rxbuf(ueth, -1);
  835. return -EINVAL;
  836. }
  837. static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
  838. {
  839. struct smsc95xx_private *priv = dev_get_priv(dev);
  840. packet_len = ALIGN(packet_len, 4);
  841. usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
  842. return 0;
  843. }
  844. int smsc95xx_write_hwaddr(struct udevice *dev)
  845. {
  846. struct usb_device *udev = dev_get_parent_priv(dev);
  847. struct eth_pdata *pdata = dev_get_platdata(dev);
  848. struct smsc95xx_private *priv = dev_get_priv(dev);
  849. return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
  850. }
  851. int smsc95xx_read_rom_hwaddr(struct udevice *dev)
  852. {
  853. struct usb_device *udev = dev_get_parent_priv(dev);
  854. struct eth_pdata *pdata = dev_get_platdata(dev);
  855. int ret;
  856. ret = smsc95xx_init_mac_address(pdata->enetaddr, udev);
  857. if (ret)
  858. memset(pdata->enetaddr, 0, 6);
  859. return 0;
  860. }
  861. static int smsc95xx_eth_probe(struct udevice *dev)
  862. {
  863. struct smsc95xx_private *priv = dev_get_priv(dev);
  864. struct ueth_data *ueth = &priv->ueth;
  865. return usb_ether_register(dev, ueth, RX_URB_SIZE);
  866. }
  867. static const struct eth_ops smsc95xx_eth_ops = {
  868. .start = smsc95xx_eth_start,
  869. .send = smsc95xx_eth_send,
  870. .recv = smsc95xx_eth_recv,
  871. .free_pkt = smsc95xx_free_pkt,
  872. .stop = smsc95xx_eth_stop,
  873. .write_hwaddr = smsc95xx_write_hwaddr,
  874. .read_rom_hwaddr = smsc95xx_read_rom_hwaddr,
  875. };
  876. U_BOOT_DRIVER(smsc95xx_eth) = {
  877. .name = "smsc95xx_eth",
  878. .id = UCLASS_ETH,
  879. .probe = smsc95xx_eth_probe,
  880. .ops = &smsc95xx_eth_ops,
  881. .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
  882. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  883. };
  884. static const struct usb_device_id smsc95xx_eth_id_table[] = {
  885. { USB_DEVICE(0x05ac, 0x1402) },
  886. { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
  887. { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
  888. { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
  889. { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
  890. { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
  891. { } /* Terminating entry */
  892. };
  893. U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
  894. #endif