r8152.c 39 KB

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  1. /*
  2. * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. *
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <malloc.h>
  11. #include <memalign.h>
  12. #include <usb.h>
  13. #include <usb/lin_gadget_compat.h>
  14. #include <linux/mii.h>
  15. #include <linux/bitops.h>
  16. #include "usb_ether.h"
  17. #include "r8152.h"
  18. #ifndef CONFIG_DM_ETH
  19. /* local vars */
  20. static int curr_eth_dev; /* index for name of next device detected */
  21. struct r8152_dongle {
  22. unsigned short vendor;
  23. unsigned short product;
  24. };
  25. static const struct r8152_dongle const r8152_dongles[] = {
  26. /* Realtek */
  27. { 0x0bda, 0x8050 },
  28. { 0x0bda, 0x8152 },
  29. { 0x0bda, 0x8153 },
  30. /* Samsung */
  31. { 0x04e8, 0xa101 },
  32. /* Lenovo */
  33. { 0x17ef, 0x304f },
  34. { 0x17ef, 0x3052 },
  35. { 0x17ef, 0x3054 },
  36. { 0x17ef, 0x3057 },
  37. { 0x17ef, 0x7205 },
  38. { 0x17ef, 0x720a },
  39. { 0x17ef, 0x720b },
  40. { 0x17ef, 0x720c },
  41. /* TP-LINK */
  42. { 0x2357, 0x0601 },
  43. /* Nvidia */
  44. { 0x0955, 0x09ff },
  45. };
  46. #endif
  47. struct r8152_version {
  48. unsigned short tcr;
  49. unsigned short version;
  50. bool gmii;
  51. };
  52. static const struct r8152_version const r8152_versions[] = {
  53. { 0x4c00, RTL_VER_01, 0 },
  54. { 0x4c10, RTL_VER_02, 0 },
  55. { 0x5c00, RTL_VER_03, 1 },
  56. { 0x5c10, RTL_VER_04, 1 },
  57. { 0x5c20, RTL_VER_05, 1 },
  58. { 0x5c30, RTL_VER_06, 1 },
  59. { 0x4800, RTL_VER_07, 0 },
  60. };
  61. static
  62. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  63. {
  64. ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
  65. int ret;
  66. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  67. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  68. value, index, tmp, size, 500);
  69. memcpy(data, tmp, size);
  70. return ret;
  71. }
  72. static
  73. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  74. {
  75. ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
  76. memcpy(tmp, data, size);
  77. return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  78. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  79. value, index, tmp, size, 500);
  80. }
  81. int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  82. void *data, u16 type)
  83. {
  84. u16 burst_size = 64;
  85. int ret;
  86. int txsize;
  87. /* both size and index must be 4 bytes align */
  88. if ((size & 3) || !size || (index & 3) || !data)
  89. return -EINVAL;
  90. if (index + size > 0xffff)
  91. return -EINVAL;
  92. while (size) {
  93. txsize = min(size, burst_size);
  94. ret = get_registers(tp, index, type, txsize, data);
  95. if (ret < 0)
  96. break;
  97. index += txsize;
  98. data += txsize;
  99. size -= txsize;
  100. }
  101. return ret;
  102. }
  103. int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  104. u16 size, void *data, u16 type)
  105. {
  106. int ret;
  107. u16 byteen_start, byteen_end, byte_en_to_hw;
  108. u16 burst_size = 512;
  109. int txsize;
  110. /* both size and index must be 4 bytes align */
  111. if ((size & 3) || !size || (index & 3) || !data)
  112. return -EINVAL;
  113. if (index + size > 0xffff)
  114. return -EINVAL;
  115. byteen_start = byteen & BYTE_EN_START_MASK;
  116. byteen_end = byteen & BYTE_EN_END_MASK;
  117. byte_en_to_hw = byteen_start | (byteen_start << 4);
  118. ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
  119. if (ret < 0)
  120. return ret;
  121. index += 4;
  122. data += 4;
  123. size -= 4;
  124. if (size) {
  125. size -= 4;
  126. while (size) {
  127. txsize = min(size, burst_size);
  128. ret = set_registers(tp, index,
  129. type | BYTE_EN_DWORD,
  130. txsize, data);
  131. if (ret < 0)
  132. return ret;
  133. index += txsize;
  134. data += txsize;
  135. size -= txsize;
  136. }
  137. byte_en_to_hw = byteen_end | (byteen_end >> 4);
  138. ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
  139. if (ret < 0)
  140. return ret;
  141. }
  142. return ret;
  143. }
  144. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  145. {
  146. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  147. }
  148. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  149. {
  150. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  151. }
  152. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  153. {
  154. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  155. }
  156. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  157. {
  158. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  159. }
  160. u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  161. {
  162. __le32 data;
  163. generic_ocp_read(tp, index, sizeof(data), &data, type);
  164. return __le32_to_cpu(data);
  165. }
  166. void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  167. {
  168. __le32 tmp = __cpu_to_le32(data);
  169. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  170. }
  171. u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  172. {
  173. u32 data;
  174. __le32 tmp;
  175. u8 shift = index & 2;
  176. index &= ~3;
  177. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  178. data = __le32_to_cpu(tmp);
  179. data >>= (shift * 8);
  180. data &= 0xffff;
  181. return data;
  182. }
  183. void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  184. {
  185. u32 mask = 0xffff;
  186. __le32 tmp;
  187. u16 byen = BYTE_EN_WORD;
  188. u8 shift = index & 2;
  189. data &= mask;
  190. if (index & 2) {
  191. byen <<= shift;
  192. mask <<= (shift * 8);
  193. data <<= (shift * 8);
  194. index &= ~3;
  195. }
  196. tmp = __cpu_to_le32(data);
  197. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  198. }
  199. u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  200. {
  201. u32 data;
  202. __le32 tmp;
  203. u8 shift = index & 3;
  204. index &= ~3;
  205. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  206. data = __le32_to_cpu(tmp);
  207. data >>= (shift * 8);
  208. data &= 0xff;
  209. return data;
  210. }
  211. void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  212. {
  213. u32 mask = 0xff;
  214. __le32 tmp;
  215. u16 byen = BYTE_EN_BYTE;
  216. u8 shift = index & 3;
  217. data &= mask;
  218. if (index & 3) {
  219. byen <<= shift;
  220. mask <<= (shift * 8);
  221. data <<= (shift * 8);
  222. index &= ~3;
  223. }
  224. tmp = __cpu_to_le32(data);
  225. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  226. }
  227. u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  228. {
  229. u16 ocp_base, ocp_index;
  230. ocp_base = addr & 0xf000;
  231. if (ocp_base != tp->ocp_base) {
  232. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  233. tp->ocp_base = ocp_base;
  234. }
  235. ocp_index = (addr & 0x0fff) | 0xb000;
  236. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  237. }
  238. void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  239. {
  240. u16 ocp_base, ocp_index;
  241. ocp_base = addr & 0xf000;
  242. if (ocp_base != tp->ocp_base) {
  243. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  244. tp->ocp_base = ocp_base;
  245. }
  246. ocp_index = (addr & 0x0fff) | 0xb000;
  247. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  248. }
  249. static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  250. {
  251. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  252. }
  253. static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  254. {
  255. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  256. }
  257. void sram_write(struct r8152 *tp, u16 addr, u16 data)
  258. {
  259. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  260. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  261. }
  262. int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
  263. const u32 mask, bool set, unsigned int timeout)
  264. {
  265. u32 val;
  266. while (--timeout) {
  267. if (ocp_reg)
  268. val = ocp_reg_read(tp, index);
  269. else
  270. val = ocp_read_dword(tp, type, index);
  271. if (!set)
  272. val = ~val;
  273. if ((val & mask) == mask)
  274. return 0;
  275. mdelay(1);
  276. }
  277. debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
  278. __func__, index, mask, timeout);
  279. return -ETIMEDOUT;
  280. }
  281. static void r8152b_reset_packet_filter(struct r8152 *tp)
  282. {
  283. u32 ocp_data;
  284. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  285. ocp_data &= ~FMC_FCR_MCU_EN;
  286. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  287. ocp_data |= FMC_FCR_MCU_EN;
  288. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  289. }
  290. static void rtl8152_wait_fifo_empty(struct r8152 *tp)
  291. {
  292. int ret;
  293. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
  294. PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
  295. if (ret)
  296. debug("Timeout waiting for FIFO empty\n");
  297. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
  298. TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
  299. if (ret)
  300. debug("Timeout waiting for TX empty\n");
  301. }
  302. static void rtl8152_nic_reset(struct r8152 *tp)
  303. {
  304. int ret;
  305. u32 ocp_data;
  306. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
  307. ocp_data |= BIST_CTRL_SW_RESET;
  308. ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
  309. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
  310. BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
  311. if (ret)
  312. debug("Timeout waiting for NIC reset\n");
  313. }
  314. static u8 rtl8152_get_speed(struct r8152 *tp)
  315. {
  316. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  317. }
  318. static void rtl_set_eee_plus(struct r8152 *tp)
  319. {
  320. u32 ocp_data;
  321. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  322. ocp_data &= ~EEEP_CR_EEEP_TX;
  323. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  324. }
  325. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  326. {
  327. u32 ocp_data;
  328. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  329. if (enable)
  330. ocp_data |= RXDY_GATED_EN;
  331. else
  332. ocp_data &= ~RXDY_GATED_EN;
  333. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  334. }
  335. static void rtl8152_set_rx_mode(struct r8152 *tp)
  336. {
  337. u32 ocp_data;
  338. __le32 tmp[2];
  339. tmp[0] = 0xffffffff;
  340. tmp[1] = 0xffffffff;
  341. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  342. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  343. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  344. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  345. }
  346. static int rtl_enable(struct r8152 *tp)
  347. {
  348. u32 ocp_data;
  349. r8152b_reset_packet_filter(tp);
  350. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  351. ocp_data |= PLA_CR_RE | PLA_CR_TE;
  352. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  353. rxdy_gated_en(tp, false);
  354. rtl8152_set_rx_mode(tp);
  355. return 0;
  356. }
  357. static int rtl8152_enable(struct r8152 *tp)
  358. {
  359. rtl_set_eee_plus(tp);
  360. return rtl_enable(tp);
  361. }
  362. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  363. {
  364. u32 ocp_data = tp->coalesce / 8;
  365. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  366. }
  367. static void r8153_set_rx_early_size(struct r8152 *tp)
  368. {
  369. u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4;
  370. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  371. }
  372. static int rtl8153_enable(struct r8152 *tp)
  373. {
  374. rtl_set_eee_plus(tp);
  375. r8153_set_rx_early_timeout(tp);
  376. r8153_set_rx_early_size(tp);
  377. return rtl_enable(tp);
  378. }
  379. static void rtl_disable(struct r8152 *tp)
  380. {
  381. u32 ocp_data;
  382. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  383. ocp_data &= ~RCR_ACPT_ALL;
  384. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  385. rxdy_gated_en(tp, true);
  386. rtl8152_wait_fifo_empty(tp);
  387. rtl8152_nic_reset(tp);
  388. }
  389. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  390. {
  391. u32 ocp_data;
  392. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  393. if (enable)
  394. ocp_data |= POWER_CUT;
  395. else
  396. ocp_data &= ~POWER_CUT;
  397. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  398. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  399. ocp_data &= ~RESUME_INDICATE;
  400. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  401. }
  402. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  403. {
  404. u32 ocp_data;
  405. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  406. if (enable)
  407. ocp_data |= CPCR_RX_VLAN;
  408. else
  409. ocp_data &= ~CPCR_RX_VLAN;
  410. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  411. }
  412. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  413. {
  414. u8 u1u2[8];
  415. if (enable)
  416. memset(u1u2, 0xff, sizeof(u1u2));
  417. else
  418. memset(u1u2, 0x00, sizeof(u1u2));
  419. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  420. }
  421. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  422. {
  423. u32 ocp_data;
  424. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  425. if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
  426. ocp_data |= U2P3_ENABLE;
  427. else
  428. ocp_data &= ~U2P3_ENABLE;
  429. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  430. }
  431. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  432. {
  433. u32 ocp_data;
  434. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  435. if (enable)
  436. ocp_data |= PWR_EN | PHASE2_EN;
  437. else
  438. ocp_data &= ~(PWR_EN | PHASE2_EN);
  439. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  440. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  441. ocp_data &= ~PCUT_STATUS;
  442. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  443. }
  444. static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
  445. {
  446. int ret;
  447. unsigned char enetaddr[8] = {0};
  448. ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
  449. if (ret < 0)
  450. return ret;
  451. memcpy(macaddr, enetaddr, ETH_ALEN);
  452. return 0;
  453. }
  454. static void r8152b_disable_aldps(struct r8152 *tp)
  455. {
  456. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  457. mdelay(20);
  458. }
  459. static void r8152b_enable_aldps(struct r8152 *tp)
  460. {
  461. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  462. LINKENA | DIS_SDSAVE);
  463. }
  464. static void rtl8152_disable(struct r8152 *tp)
  465. {
  466. r8152b_disable_aldps(tp);
  467. rtl_disable(tp);
  468. r8152b_enable_aldps(tp);
  469. }
  470. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  471. {
  472. u16 data;
  473. data = r8152_mdio_read(tp, MII_BMCR);
  474. if (data & BMCR_PDOWN) {
  475. data &= ~BMCR_PDOWN;
  476. r8152_mdio_write(tp, MII_BMCR, data);
  477. }
  478. r8152b_firmware(tp);
  479. }
  480. static void rtl8152_reinit_ll(struct r8152 *tp)
  481. {
  482. u32 ocp_data;
  483. int ret;
  484. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
  485. PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
  486. if (ret)
  487. debug("Timeout waiting for link list ready\n");
  488. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  489. ocp_data |= RE_INIT_LL;
  490. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  491. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
  492. PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
  493. if (ret)
  494. debug("Timeout waiting for link list ready\n");
  495. }
  496. static void r8152b_exit_oob(struct r8152 *tp)
  497. {
  498. u32 ocp_data;
  499. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  500. ocp_data &= ~RCR_ACPT_ALL;
  501. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  502. rxdy_gated_en(tp, true);
  503. r8152b_hw_phy_cfg(tp);
  504. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  505. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  506. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  507. ocp_data &= ~NOW_IS_OOB;
  508. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  509. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  510. ocp_data &= ~MCU_BORW_EN;
  511. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  512. rtl8152_reinit_ll(tp);
  513. rtl8152_nic_reset(tp);
  514. /* rx share fifo credit full threshold */
  515. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  516. if (tp->udev->speed == USB_SPEED_FULL ||
  517. tp->udev->speed == USB_SPEED_LOW) {
  518. /* rx share fifo credit near full threshold */
  519. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  520. RXFIFO_THR2_FULL);
  521. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  522. RXFIFO_THR3_FULL);
  523. } else {
  524. /* rx share fifo credit near full threshold */
  525. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  526. RXFIFO_THR2_HIGH);
  527. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  528. RXFIFO_THR3_HIGH);
  529. }
  530. /* TX share fifo free credit full threshold */
  531. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  532. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  533. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  534. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  535. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  536. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  537. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  538. ocp_data |= TCR0_AUTO_FIFO;
  539. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  540. }
  541. static void r8152b_enter_oob(struct r8152 *tp)
  542. {
  543. u32 ocp_data;
  544. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  545. ocp_data &= ~NOW_IS_OOB;
  546. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  547. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  548. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  549. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  550. rtl_disable(tp);
  551. rtl8152_reinit_ll(tp);
  552. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  553. rtl_rx_vlan_en(tp, false);
  554. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  555. ocp_data |= ALDPS_PROXY_MODE;
  556. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  557. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  558. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  559. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  560. rxdy_gated_en(tp, false);
  561. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  562. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  563. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  564. }
  565. static void r8153_hw_phy_cfg(struct r8152 *tp)
  566. {
  567. u32 ocp_data;
  568. u16 data;
  569. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  570. tp->version == RTL_VER_05)
  571. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  572. data = r8152_mdio_read(tp, MII_BMCR);
  573. if (data & BMCR_PDOWN) {
  574. data &= ~BMCR_PDOWN;
  575. r8152_mdio_write(tp, MII_BMCR, data);
  576. }
  577. r8153_firmware(tp);
  578. if (tp->version == RTL_VER_03) {
  579. data = ocp_reg_read(tp, OCP_EEE_CFG);
  580. data &= ~CTAP_SHORT_EN;
  581. ocp_reg_write(tp, OCP_EEE_CFG, data);
  582. }
  583. data = ocp_reg_read(tp, OCP_POWER_CFG);
  584. data |= EEE_CLKDIV_EN;
  585. ocp_reg_write(tp, OCP_POWER_CFG, data);
  586. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  587. data |= EN_10M_BGOFF;
  588. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  589. data = ocp_reg_read(tp, OCP_POWER_CFG);
  590. data |= EN_10M_PLLOFF;
  591. ocp_reg_write(tp, OCP_POWER_CFG, data);
  592. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  593. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  594. ocp_data |= PFM_PWM_SWITCH;
  595. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  596. /* Enable LPF corner auto tune */
  597. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  598. /* Adjust 10M Amplitude */
  599. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  600. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  601. }
  602. static void r8153_first_init(struct r8152 *tp)
  603. {
  604. u32 ocp_data;
  605. rxdy_gated_en(tp, true);
  606. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  607. ocp_data &= ~RCR_ACPT_ALL;
  608. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  609. r8153_hw_phy_cfg(tp);
  610. rtl8152_nic_reset(tp);
  611. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  612. ocp_data &= ~NOW_IS_OOB;
  613. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  614. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  615. ocp_data &= ~MCU_BORW_EN;
  616. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  617. rtl8152_reinit_ll(tp);
  618. rtl_rx_vlan_en(tp, false);
  619. ocp_data = RTL8153_RMS;
  620. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
  621. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  622. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  623. ocp_data |= TCR0_AUTO_FIFO;
  624. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  625. rtl8152_nic_reset(tp);
  626. /* rx share fifo credit full threshold */
  627. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  628. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  629. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  630. /* TX share fifo free credit full threshold */
  631. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  632. /* rx aggregation */
  633. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  634. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  635. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  636. }
  637. static void r8153_enter_oob(struct r8152 *tp)
  638. {
  639. u32 ocp_data;
  640. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  641. ocp_data &= ~NOW_IS_OOB;
  642. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  643. rtl_disable(tp);
  644. rtl8152_reinit_ll(tp);
  645. ocp_data = RTL8153_RMS;
  646. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
  647. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  648. ocp_data &= ~TEREDO_WAKE_MASK;
  649. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  650. rtl_rx_vlan_en(tp, false);
  651. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  652. ocp_data |= ALDPS_PROXY_MODE;
  653. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  654. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  655. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  656. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  657. rxdy_gated_en(tp, false);
  658. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  659. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  660. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  661. }
  662. static void r8153_disable_aldps(struct r8152 *tp)
  663. {
  664. u16 data;
  665. data = ocp_reg_read(tp, OCP_POWER_CFG);
  666. data &= ~EN_ALDPS;
  667. ocp_reg_write(tp, OCP_POWER_CFG, data);
  668. mdelay(20);
  669. }
  670. static void rtl8153_disable(struct r8152 *tp)
  671. {
  672. r8153_disable_aldps(tp);
  673. rtl_disable(tp);
  674. }
  675. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  676. {
  677. u16 bmcr, anar, gbcr;
  678. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  679. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  680. ADVERTISE_100HALF | ADVERTISE_100FULL);
  681. if (tp->supports_gmii) {
  682. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  683. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  684. } else {
  685. gbcr = 0;
  686. }
  687. if (autoneg == AUTONEG_DISABLE) {
  688. if (speed == SPEED_10) {
  689. bmcr = 0;
  690. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  691. } else if (speed == SPEED_100) {
  692. bmcr = BMCR_SPEED100;
  693. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  694. } else if (speed == SPEED_1000 && tp->supports_gmii) {
  695. bmcr = BMCR_SPEED1000;
  696. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  697. } else {
  698. return -EINVAL;
  699. }
  700. if (duplex == DUPLEX_FULL)
  701. bmcr |= BMCR_FULLDPLX;
  702. } else {
  703. if (speed == SPEED_10) {
  704. if (duplex == DUPLEX_FULL)
  705. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  706. else
  707. anar |= ADVERTISE_10HALF;
  708. } else if (speed == SPEED_100) {
  709. if (duplex == DUPLEX_FULL) {
  710. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  711. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  712. } else {
  713. anar |= ADVERTISE_10HALF;
  714. anar |= ADVERTISE_100HALF;
  715. }
  716. } else if (speed == SPEED_1000 && tp->supports_gmii) {
  717. if (duplex == DUPLEX_FULL) {
  718. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  719. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  720. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  721. } else {
  722. anar |= ADVERTISE_10HALF;
  723. anar |= ADVERTISE_100HALF;
  724. gbcr |= ADVERTISE_1000HALF;
  725. }
  726. } else {
  727. return -EINVAL;
  728. }
  729. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  730. }
  731. if (tp->supports_gmii)
  732. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  733. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  734. r8152_mdio_write(tp, MII_BMCR, bmcr);
  735. return 0;
  736. }
  737. static void rtl8152_up(struct r8152 *tp)
  738. {
  739. r8152b_disable_aldps(tp);
  740. r8152b_exit_oob(tp);
  741. r8152b_enable_aldps(tp);
  742. }
  743. static void rtl8152_down(struct r8152 *tp)
  744. {
  745. r8152_power_cut_en(tp, false);
  746. r8152b_disable_aldps(tp);
  747. r8152b_enter_oob(tp);
  748. r8152b_enable_aldps(tp);
  749. }
  750. static void rtl8153_up(struct r8152 *tp)
  751. {
  752. r8153_u1u2en(tp, false);
  753. r8153_disable_aldps(tp);
  754. r8153_first_init(tp);
  755. r8153_u2p3en(tp, false);
  756. }
  757. static void rtl8153_down(struct r8152 *tp)
  758. {
  759. r8153_u1u2en(tp, false);
  760. r8153_u2p3en(tp, false);
  761. r8153_power_cut_en(tp, false);
  762. r8153_disable_aldps(tp);
  763. r8153_enter_oob(tp);
  764. }
  765. static void r8152b_get_version(struct r8152 *tp)
  766. {
  767. u32 ocp_data;
  768. u16 tcr;
  769. int i;
  770. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  771. tcr = (u16)(ocp_data & VERSION_MASK);
  772. for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
  773. if (tcr == r8152_versions[i].tcr) {
  774. /* Found a supported version */
  775. tp->version = r8152_versions[i].version;
  776. tp->supports_gmii = r8152_versions[i].gmii;
  777. break;
  778. }
  779. }
  780. if (tp->version == RTL_VER_UNKNOWN)
  781. debug("r8152 Unknown tcr version 0x%04x\n", tcr);
  782. }
  783. static void r8152b_enable_fc(struct r8152 *tp)
  784. {
  785. u16 anar;
  786. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  787. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  788. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  789. }
  790. static void rtl_tally_reset(struct r8152 *tp)
  791. {
  792. u32 ocp_data;
  793. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  794. ocp_data |= TALLY_RESET;
  795. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  796. }
  797. static void r8152b_init(struct r8152 *tp)
  798. {
  799. u32 ocp_data;
  800. r8152b_disable_aldps(tp);
  801. if (tp->version == RTL_VER_01) {
  802. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  803. ocp_data &= ~LED_MODE_MASK;
  804. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  805. }
  806. r8152_power_cut_en(tp, false);
  807. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  808. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  809. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  810. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  811. ocp_data &= ~MCU_CLK_RATIO_MASK;
  812. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  813. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  814. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  815. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  816. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  817. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
  818. ocp_data |= BIT(15);
  819. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
  820. ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
  821. ocp_data &= ~BIT(15);
  822. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
  823. r8152b_enable_fc(tp);
  824. rtl_tally_reset(tp);
  825. /* enable rx aggregation */
  826. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  827. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  828. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  829. }
  830. static void r8153_init(struct r8152 *tp)
  831. {
  832. int i;
  833. u32 ocp_data;
  834. r8153_disable_aldps(tp);
  835. r8153_u1u2en(tp, false);
  836. r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
  837. AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
  838. for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
  839. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  840. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  841. break;
  842. mdelay(1);
  843. }
  844. r8153_u2p3en(tp, false);
  845. if (tp->version == RTL_VER_04) {
  846. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  847. ocp_data &= ~pwd_dn_scale_mask;
  848. ocp_data |= pwd_dn_scale(96);
  849. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  850. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  851. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  852. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  853. } else if (tp->version == RTL_VER_05) {
  854. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  855. ocp_data &= ~ECM_ALDPS;
  856. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  857. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  858. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  859. ocp_data &= ~DYNAMIC_BURST;
  860. else
  861. ocp_data |= DYNAMIC_BURST;
  862. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  863. } else if (tp->version == RTL_VER_06) {
  864. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  865. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  866. ocp_data &= ~DYNAMIC_BURST;
  867. else
  868. ocp_data |= DYNAMIC_BURST;
  869. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  870. }
  871. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  872. ocp_data |= EP4_FULL_FC;
  873. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  874. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  875. ocp_data &= ~TIMER11_EN;
  876. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  877. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  878. ocp_data &= ~LED_MODE_MASK;
  879. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  880. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  881. if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
  882. ocp_data |= LPM_TIMER_500MS;
  883. else
  884. ocp_data |= LPM_TIMER_500US;
  885. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  886. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  887. ocp_data &= ~SEN_VAL_MASK;
  888. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  889. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  890. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  891. r8153_power_cut_en(tp, false);
  892. r8152b_enable_fc(tp);
  893. rtl_tally_reset(tp);
  894. }
  895. static void rtl8152_unload(struct r8152 *tp)
  896. {
  897. if (tp->version != RTL_VER_01)
  898. r8152_power_cut_en(tp, true);
  899. }
  900. static void rtl8153_unload(struct r8152 *tp)
  901. {
  902. r8153_power_cut_en(tp, false);
  903. }
  904. static int rtl_ops_init(struct r8152 *tp)
  905. {
  906. struct rtl_ops *ops = &tp->rtl_ops;
  907. int ret = 0;
  908. switch (tp->version) {
  909. case RTL_VER_01:
  910. case RTL_VER_02:
  911. case RTL_VER_07:
  912. ops->init = r8152b_init;
  913. ops->enable = rtl8152_enable;
  914. ops->disable = rtl8152_disable;
  915. ops->up = rtl8152_up;
  916. ops->down = rtl8152_down;
  917. ops->unload = rtl8152_unload;
  918. break;
  919. case RTL_VER_03:
  920. case RTL_VER_04:
  921. case RTL_VER_05:
  922. case RTL_VER_06:
  923. ops->init = r8153_init;
  924. ops->enable = rtl8153_enable;
  925. ops->disable = rtl8153_disable;
  926. ops->up = rtl8153_up;
  927. ops->down = rtl8153_down;
  928. ops->unload = rtl8153_unload;
  929. break;
  930. default:
  931. ret = -ENODEV;
  932. printf("r8152 Unknown Device\n");
  933. break;
  934. }
  935. return ret;
  936. }
  937. static int r8152_init_common(struct r8152 *tp)
  938. {
  939. u8 speed;
  940. int timeout = 0;
  941. int link_detected;
  942. debug("** %s()\n", __func__);
  943. do {
  944. speed = rtl8152_get_speed(tp);
  945. link_detected = speed & LINK_STATUS;
  946. if (!link_detected) {
  947. if (timeout == 0)
  948. printf("Waiting for Ethernet connection... ");
  949. mdelay(TIMEOUT_RESOLUTION);
  950. timeout += TIMEOUT_RESOLUTION;
  951. }
  952. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  953. if (link_detected) {
  954. tp->rtl_ops.enable(tp);
  955. if (timeout != 0)
  956. printf("done.\n");
  957. } else {
  958. printf("unable to connect.\n");
  959. }
  960. return 0;
  961. }
  962. static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
  963. {
  964. struct usb_device *udev = ueth->pusb_dev;
  965. u32 opts1, opts2 = 0;
  966. int err;
  967. int actual_len;
  968. ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg,
  969. PKTSIZE + sizeof(struct tx_desc));
  970. struct tx_desc *tx_desc = (struct tx_desc *)msg;
  971. debug("** %s(), len %d\n", __func__, length);
  972. opts1 = length | TX_FS | TX_LS;
  973. tx_desc->opts2 = cpu_to_le32(opts2);
  974. tx_desc->opts1 = cpu_to_le32(opts1);
  975. memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
  976. err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out),
  977. (void *)msg, length + sizeof(struct tx_desc),
  978. &actual_len, USB_BULK_SEND_TIMEOUT);
  979. debug("Tx: len = %zu, actual = %u, err = %d\n",
  980. length + sizeof(struct tx_desc), actual_len, err);
  981. return err;
  982. }
  983. #ifndef CONFIG_DM_ETH
  984. static int r8152_init(struct eth_device *eth, bd_t *bd)
  985. {
  986. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  987. struct r8152 *tp = (struct r8152 *)dev->dev_priv;
  988. return r8152_init_common(tp);
  989. }
  990. static int r8152_send(struct eth_device *eth, void *packet, int length)
  991. {
  992. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  993. return r8152_send_common(dev, packet, length);
  994. }
  995. static int r8152_recv(struct eth_device *eth)
  996. {
  997. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  998. ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ);
  999. unsigned char *pkt_ptr;
  1000. int err;
  1001. int actual_len;
  1002. u16 packet_len;
  1003. u32 bytes_process = 0;
  1004. struct rx_desc *rx_desc;
  1005. debug("** %s()\n", __func__);
  1006. err = usb_bulk_msg(dev->pusb_dev,
  1007. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  1008. (void *)recv_buf,
  1009. RTL8152_AGG_BUF_SZ,
  1010. &actual_len,
  1011. USB_BULK_RECV_TIMEOUT);
  1012. debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
  1013. actual_len, err);
  1014. if (err != 0) {
  1015. debug("Rx: failed to receive\n");
  1016. return -1;
  1017. }
  1018. if (actual_len > RTL8152_AGG_BUF_SZ) {
  1019. debug("Rx: received too many bytes %d\n", actual_len);
  1020. return -1;
  1021. }
  1022. while (bytes_process < actual_len) {
  1023. rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
  1024. pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
  1025. packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1026. packet_len -= CRC_SIZE;
  1027. net_process_received_packet(pkt_ptr, packet_len);
  1028. bytes_process +=
  1029. (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
  1030. if (bytes_process % 8)
  1031. bytes_process = bytes_process + 8 - (bytes_process % 8);
  1032. }
  1033. return 0;
  1034. }
  1035. static void r8152_halt(struct eth_device *eth)
  1036. {
  1037. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  1038. struct r8152 *tp = (struct r8152 *)dev->dev_priv;
  1039. debug("** %s()\n", __func__);
  1040. tp->rtl_ops.disable(tp);
  1041. }
  1042. static int r8152_write_hwaddr(struct eth_device *eth)
  1043. {
  1044. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  1045. struct r8152 *tp = (struct r8152 *)dev->dev_priv;
  1046. unsigned char enetaddr[8] = {0};
  1047. memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
  1048. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1049. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
  1050. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1051. debug("MAC %pM\n", eth->enetaddr);
  1052. return 0;
  1053. }
  1054. void r8152_eth_before_probe(void)
  1055. {
  1056. curr_eth_dev = 0;
  1057. }
  1058. /* Probe to see if a new device is actually an realtek device */
  1059. int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
  1060. struct ueth_data *ss)
  1061. {
  1062. struct usb_interface *iface;
  1063. struct usb_interface_descriptor *iface_desc;
  1064. int ep_in_found = 0, ep_out_found = 0;
  1065. int i;
  1066. struct r8152 *tp;
  1067. /* let's examine the device now */
  1068. iface = &dev->config.if_desc[ifnum];
  1069. iface_desc = &dev->config.if_desc[ifnum].desc;
  1070. for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
  1071. if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
  1072. dev->descriptor.idProduct == r8152_dongles[i].product)
  1073. /* Found a supported dongle */
  1074. break;
  1075. }
  1076. if (i == ARRAY_SIZE(r8152_dongles))
  1077. return 0;
  1078. memset(ss, 0, sizeof(struct ueth_data));
  1079. /* At this point, we know we've got a live one */
  1080. debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
  1081. dev->descriptor.idVendor, dev->descriptor.idProduct);
  1082. /* Initialize the ueth_data structure with some useful info */
  1083. ss->ifnum = ifnum;
  1084. ss->pusb_dev = dev;
  1085. ss->subclass = iface_desc->bInterfaceSubClass;
  1086. ss->protocol = iface_desc->bInterfaceProtocol;
  1087. /* alloc driver private */
  1088. ss->dev_priv = calloc(1, sizeof(struct r8152));
  1089. if (!ss->dev_priv)
  1090. return 0;
  1091. /*
  1092. * We are expecting a minimum of 3 endpoints - in, out (bulk), and
  1093. * int. We will ignore any others.
  1094. */
  1095. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  1096. /* is it an BULK endpoint? */
  1097. if ((iface->ep_desc[i].bmAttributes &
  1098. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
  1099. u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
  1100. if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
  1101. ss->ep_in = ep_addr &
  1102. USB_ENDPOINT_NUMBER_MASK;
  1103. ep_in_found = 1;
  1104. } else {
  1105. if (!ep_out_found) {
  1106. ss->ep_out = ep_addr &
  1107. USB_ENDPOINT_NUMBER_MASK;
  1108. ep_out_found = 1;
  1109. }
  1110. }
  1111. }
  1112. /* is it an interrupt endpoint? */
  1113. if ((iface->ep_desc[i].bmAttributes &
  1114. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  1115. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  1116. USB_ENDPOINT_NUMBER_MASK;
  1117. ss->irqinterval = iface->ep_desc[i].bInterval;
  1118. }
  1119. }
  1120. debug("Endpoints In %d Out %d Int %d\n",
  1121. ss->ep_in, ss->ep_out, ss->ep_int);
  1122. /* Do some basic sanity checks, and bail if we find a problem */
  1123. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  1124. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  1125. debug("Problems with device\n");
  1126. return 0;
  1127. }
  1128. dev->privptr = (void *)ss;
  1129. tp = ss->dev_priv;
  1130. tp->udev = dev;
  1131. tp->intf = iface;
  1132. r8152b_get_version(tp);
  1133. if (rtl_ops_init(tp))
  1134. return 0;
  1135. tp->rtl_ops.init(tp);
  1136. tp->rtl_ops.up(tp);
  1137. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  1138. tp->supports_gmii ? SPEED_1000 : SPEED_100,
  1139. DUPLEX_FULL);
  1140. return 1;
  1141. }
  1142. int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  1143. struct eth_device *eth)
  1144. {
  1145. if (!eth) {
  1146. debug("%s: missing parameter.\n", __func__);
  1147. return 0;
  1148. }
  1149. sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
  1150. eth->init = r8152_init;
  1151. eth->send = r8152_send;
  1152. eth->recv = r8152_recv;
  1153. eth->halt = r8152_halt;
  1154. eth->write_hwaddr = r8152_write_hwaddr;
  1155. eth->priv = ss;
  1156. /* Get the MAC address */
  1157. if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
  1158. return 0;
  1159. debug("MAC %pM\n", eth->enetaddr);
  1160. return 1;
  1161. }
  1162. #endif /* !CONFIG_DM_ETH */
  1163. #ifdef CONFIG_DM_ETH
  1164. static int r8152_eth_start(struct udevice *dev)
  1165. {
  1166. struct r8152 *tp = dev_get_priv(dev);
  1167. debug("** %s (%d)\n", __func__, __LINE__);
  1168. return r8152_init_common(tp);
  1169. }
  1170. void r8152_eth_stop(struct udevice *dev)
  1171. {
  1172. struct r8152 *tp = dev_get_priv(dev);
  1173. debug("** %s (%d)\n", __func__, __LINE__);
  1174. tp->rtl_ops.disable(tp);
  1175. }
  1176. int r8152_eth_send(struct udevice *dev, void *packet, int length)
  1177. {
  1178. struct r8152 *tp = dev_get_priv(dev);
  1179. return r8152_send_common(&tp->ueth, packet, length);
  1180. }
  1181. int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  1182. {
  1183. struct r8152 *tp = dev_get_priv(dev);
  1184. struct ueth_data *ueth = &tp->ueth;
  1185. uint8_t *ptr;
  1186. int ret, len;
  1187. struct rx_desc *rx_desc;
  1188. u16 packet_len;
  1189. len = usb_ether_get_rx_bytes(ueth, &ptr);
  1190. debug("%s: first try, len=%d\n", __func__, len);
  1191. if (!len) {
  1192. if (!(flags & ETH_RECV_CHECK_DEVICE))
  1193. return -EAGAIN;
  1194. ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ);
  1195. if (ret)
  1196. return ret;
  1197. len = usb_ether_get_rx_bytes(ueth, &ptr);
  1198. debug("%s: second try, len=%d\n", __func__, len);
  1199. }
  1200. rx_desc = (struct rx_desc *)ptr;
  1201. packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1202. packet_len -= CRC_SIZE;
  1203. if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) {
  1204. debug("Rx: too large packet: %d\n", packet_len);
  1205. goto err;
  1206. }
  1207. *packetp = ptr + sizeof(struct rx_desc);
  1208. return packet_len;
  1209. err:
  1210. usb_ether_advance_rxbuf(ueth, -1);
  1211. return -ENOSPC;
  1212. }
  1213. static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
  1214. {
  1215. struct r8152 *tp = dev_get_priv(dev);
  1216. packet_len += sizeof(struct rx_desc) + CRC_SIZE;
  1217. packet_len = ALIGN(packet_len, 8);
  1218. usb_ether_advance_rxbuf(&tp->ueth, packet_len);
  1219. return 0;
  1220. }
  1221. static int r8152_write_hwaddr(struct udevice *dev)
  1222. {
  1223. struct eth_pdata *pdata = dev_get_platdata(dev);
  1224. struct r8152 *tp = dev_get_priv(dev);
  1225. unsigned char enetaddr[8] = { 0 };
  1226. debug("** %s (%d)\n", __func__, __LINE__);
  1227. memcpy(enetaddr, pdata->enetaddr, ETH_ALEN);
  1228. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1229. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
  1230. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1231. debug("MAC %pM\n", pdata->enetaddr);
  1232. return 0;
  1233. }
  1234. int r8152_read_rom_hwaddr(struct udevice *dev)
  1235. {
  1236. struct eth_pdata *pdata = dev_get_platdata(dev);
  1237. struct r8152 *tp = dev_get_priv(dev);
  1238. debug("** %s (%d)\n", __func__, __LINE__);
  1239. r8152_read_mac(tp, pdata->enetaddr);
  1240. return 0;
  1241. }
  1242. static int r8152_eth_probe(struct udevice *dev)
  1243. {
  1244. struct usb_device *udev = dev_get_parent_priv(dev);
  1245. struct eth_pdata *pdata = dev_get_platdata(dev);
  1246. struct r8152 *tp = dev_get_priv(dev);
  1247. struct ueth_data *ueth = &tp->ueth;
  1248. int ret;
  1249. tp->udev = udev;
  1250. r8152_read_mac(tp, pdata->enetaddr);
  1251. r8152b_get_version(tp);
  1252. ret = rtl_ops_init(tp);
  1253. if (ret)
  1254. return ret;
  1255. tp->rtl_ops.init(tp);
  1256. tp->rtl_ops.up(tp);
  1257. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  1258. tp->supports_gmii ? SPEED_1000 : SPEED_100,
  1259. DUPLEX_FULL);
  1260. return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ);
  1261. }
  1262. static const struct eth_ops r8152_eth_ops = {
  1263. .start = r8152_eth_start,
  1264. .send = r8152_eth_send,
  1265. .recv = r8152_eth_recv,
  1266. .free_pkt = r8152_free_pkt,
  1267. .stop = r8152_eth_stop,
  1268. .write_hwaddr = r8152_write_hwaddr,
  1269. .read_rom_hwaddr = r8152_read_rom_hwaddr,
  1270. };
  1271. U_BOOT_DRIVER(r8152_eth) = {
  1272. .name = "r8152_eth",
  1273. .id = UCLASS_ETH,
  1274. .probe = r8152_eth_probe,
  1275. .ops = &r8152_eth_ops,
  1276. .priv_auto_alloc_size = sizeof(struct r8152),
  1277. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1278. };
  1279. static const struct usb_device_id r8152_eth_id_table[] = {
  1280. /* Realtek */
  1281. { USB_DEVICE(0x0bda, 0x8050) },
  1282. { USB_DEVICE(0x0bda, 0x8152) },
  1283. { USB_DEVICE(0x0bda, 0x8153) },
  1284. /* Samsung */
  1285. { USB_DEVICE(0x04e8, 0xa101) },
  1286. /* Lenovo */
  1287. { USB_DEVICE(0x17ef, 0x304f) },
  1288. { USB_DEVICE(0x17ef, 0x3052) },
  1289. { USB_DEVICE(0x17ef, 0x3054) },
  1290. { USB_DEVICE(0x17ef, 0x3057) },
  1291. { USB_DEVICE(0x17ef, 0x7205) },
  1292. { USB_DEVICE(0x17ef, 0x720a) },
  1293. { USB_DEVICE(0x17ef, 0x720b) },
  1294. { USB_DEVICE(0x17ef, 0x720c) },
  1295. /* TP-LINK */
  1296. { USB_DEVICE(0x2357, 0x0601) },
  1297. /* Nvidia */
  1298. { USB_DEVICE(0x0955, 0x09ff) },
  1299. { } /* Terminating entry */
  1300. };
  1301. U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
  1302. #endif /* CONFIG_DM_ETH */