asix88179.c 23 KB

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  1. /*
  2. * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
  3. * based on the U-Boot Asix driver as well as information
  4. * from the Linux AX88179_178a driver
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <usb.h>
  11. #include <net.h>
  12. #include <linux/mii.h>
  13. #include "usb_ether.h"
  14. #include <malloc.h>
  15. #include <memalign.h>
  16. #include <errno.h>
  17. /* ASIX AX88179 based USB 3.0 Ethernet Devices */
  18. #define AX88179_PHY_ID 0x03
  19. #define AX_EEPROM_LEN 0x100
  20. #define AX88179_EEPROM_MAGIC 0x17900b95
  21. #define AX_MCAST_FLTSIZE 8
  22. #define AX_MAX_MCAST 64
  23. #define AX_INT_PPLS_LINK (1 << 16)
  24. #define AX_RXHDR_L4_TYPE_MASK 0x1c
  25. #define AX_RXHDR_L4_TYPE_UDP 4
  26. #define AX_RXHDR_L4_TYPE_TCP 16
  27. #define AX_RXHDR_L3CSUM_ERR 2
  28. #define AX_RXHDR_L4CSUM_ERR 1
  29. #define AX_RXHDR_CRC_ERR (1 << 29)
  30. #define AX_RXHDR_DROP_ERR (1 << 31)
  31. #define AX_ENDPOINT_INT 0x01
  32. #define AX_ENDPOINT_IN 0x02
  33. #define AX_ENDPOINT_OUT 0x03
  34. #define AX_ACCESS_MAC 0x01
  35. #define AX_ACCESS_PHY 0x02
  36. #define AX_ACCESS_EEPROM 0x04
  37. #define AX_ACCESS_EFUS 0x05
  38. #define AX_PAUSE_WATERLVL_HIGH 0x54
  39. #define AX_PAUSE_WATERLVL_LOW 0x55
  40. #define PHYSICAL_LINK_STATUS 0x02
  41. #define AX_USB_SS (1 << 2)
  42. #define AX_USB_HS (1 << 1)
  43. #define GENERAL_STATUS 0x03
  44. #define AX_SECLD (1 << 2)
  45. #define AX_SROM_ADDR 0x07
  46. #define AX_SROM_CMD 0x0a
  47. #define EEP_RD (1 << 2)
  48. #define EEP_BUSY (1 << 4)
  49. #define AX_SROM_DATA_LOW 0x08
  50. #define AX_SROM_DATA_HIGH 0x09
  51. #define AX_RX_CTL 0x0b
  52. #define AX_RX_CTL_DROPCRCERR (1 << 8)
  53. #define AX_RX_CTL_IPE (1 << 9)
  54. #define AX_RX_CTL_START (1 << 7)
  55. #define AX_RX_CTL_AP (1 << 5)
  56. #define AX_RX_CTL_AM (1 << 4)
  57. #define AX_RX_CTL_AB (1 << 3)
  58. #define AX_RX_CTL_AMALL (1 << 1)
  59. #define AX_RX_CTL_PRO (1 << 0)
  60. #define AX_RX_CTL_STOP 0
  61. #define AX_NODE_ID 0x10
  62. #define AX_MULFLTARY 0x16
  63. #define AX_MEDIUM_STATUS_MODE 0x22
  64. #define AX_MEDIUM_GIGAMODE (1 << 0)
  65. #define AX_MEDIUM_FULL_DUPLEX (1 << 1)
  66. #define AX_MEDIUM_EN_125MHZ (1 << 3)
  67. #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4)
  68. #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5)
  69. #define AX_MEDIUM_RECEIVE_EN (1 << 8)
  70. #define AX_MEDIUM_PS (1 << 9)
  71. #define AX_MEDIUM_JUMBO_EN 0x8040
  72. #define AX_MONITOR_MOD 0x24
  73. #define AX_MONITOR_MODE_RWLC (1 << 1)
  74. #define AX_MONITOR_MODE_RWMP (1 << 2)
  75. #define AX_MONITOR_MODE_PMEPOL (1 << 5)
  76. #define AX_MONITOR_MODE_PMETYPE (1 << 6)
  77. #define AX_GPIO_CTRL 0x25
  78. #define AX_GPIO_CTRL_GPIO3EN (1 << 7)
  79. #define AX_GPIO_CTRL_GPIO2EN (1 << 6)
  80. #define AX_GPIO_CTRL_GPIO1EN (1 << 5)
  81. #define AX_PHYPWR_RSTCTL 0x26
  82. #define AX_PHYPWR_RSTCTL_BZ (1 << 4)
  83. #define AX_PHYPWR_RSTCTL_IPRL (1 << 5)
  84. #define AX_PHYPWR_RSTCTL_AT (1 << 12)
  85. #define AX_RX_BULKIN_QCTRL 0x2e
  86. #define AX_CLK_SELECT 0x33
  87. #define AX_CLK_SELECT_BCS (1 << 0)
  88. #define AX_CLK_SELECT_ACS (1 << 1)
  89. #define AX_CLK_SELECT_ULR (1 << 3)
  90. #define AX_RXCOE_CTL 0x34
  91. #define AX_RXCOE_IP (1 << 0)
  92. #define AX_RXCOE_TCP (1 << 1)
  93. #define AX_RXCOE_UDP (1 << 2)
  94. #define AX_RXCOE_TCPV6 (1 << 5)
  95. #define AX_RXCOE_UDPV6 (1 << 6)
  96. #define AX_TXCOE_CTL 0x35
  97. #define AX_TXCOE_IP (1 << 0)
  98. #define AX_TXCOE_TCP (1 << 1)
  99. #define AX_TXCOE_UDP (1 << 2)
  100. #define AX_TXCOE_TCPV6 (1 << 5)
  101. #define AX_TXCOE_UDPV6 (1 << 6)
  102. #define AX_LEDCTRL 0x73
  103. #define GMII_PHY_PHYSR 0x11
  104. #define GMII_PHY_PHYSR_SMASK 0xc000
  105. #define GMII_PHY_PHYSR_GIGA (1 << 15)
  106. #define GMII_PHY_PHYSR_100 (1 << 14)
  107. #define GMII_PHY_PHYSR_FULL (1 << 13)
  108. #define GMII_PHY_PHYSR_LINK (1 << 10)
  109. #define GMII_LED_ACT 0x1a
  110. #define GMII_LED_ACTIVE_MASK 0xff8f
  111. #define GMII_LED0_ACTIVE (1 << 4)
  112. #define GMII_LED1_ACTIVE (1 << 5)
  113. #define GMII_LED2_ACTIVE (1 << 6)
  114. #define GMII_LED_LINK 0x1c
  115. #define GMII_LED_LINK_MASK 0xf888
  116. #define GMII_LED0_LINK_10 (1 << 0)
  117. #define GMII_LED0_LINK_100 (1 << 1)
  118. #define GMII_LED0_LINK_1000 (1 << 2)
  119. #define GMII_LED1_LINK_10 (1 << 4)
  120. #define GMII_LED1_LINK_100 (1 << 5)
  121. #define GMII_LED1_LINK_1000 (1 << 6)
  122. #define GMII_LED2_LINK_10 (1 << 8)
  123. #define GMII_LED2_LINK_100 (1 << 9)
  124. #define GMII_LED2_LINK_1000 (1 << 10)
  125. #define LED0_ACTIVE (1 << 0)
  126. #define LED0_LINK_10 (1 << 1)
  127. #define LED0_LINK_100 (1 << 2)
  128. #define LED0_LINK_1000 (1 << 3)
  129. #define LED0_FD (1 << 4)
  130. #define LED0_USB3_MASK 0x001f
  131. #define LED1_ACTIVE (1 << 5)
  132. #define LED1_LINK_10 (1 << 6)
  133. #define LED1_LINK_100 (1 << 7)
  134. #define LED1_LINK_1000 (1 << 8)
  135. #define LED1_FD (1 << 9)
  136. #define LED1_USB3_MASK 0x03e0
  137. #define LED2_ACTIVE (1 << 10)
  138. #define LED2_LINK_1000 (1 << 13)
  139. #define LED2_LINK_100 (1 << 12)
  140. #define LED2_LINK_10 (1 << 11)
  141. #define LED2_FD (1 << 14)
  142. #define LED_VALID (1 << 15)
  143. #define LED2_USB3_MASK 0x7c00
  144. #define GMII_PHYPAGE 0x1e
  145. #define GMII_PHY_PAGE_SELECT 0x1f
  146. #define GMII_PHY_PGSEL_EXT 0x0007
  147. #define GMII_PHY_PGSEL_PAGE0 0x0000
  148. /* local defines */
  149. #define ASIX_BASE_NAME "axg"
  150. #define USB_CTRL_SET_TIMEOUT 5000
  151. #define USB_CTRL_GET_TIMEOUT 5000
  152. #define USB_BULK_SEND_TIMEOUT 5000
  153. #define USB_BULK_RECV_TIMEOUT 5000
  154. #define AX_RX_URB_SIZE 1024 * 0x12
  155. #define BLK_FRAME_SIZE 0x200
  156. #define PHY_CONNECT_TIMEOUT 5000
  157. #define TIMEOUT_RESOLUTION 50 /* ms */
  158. #define FLAG_NONE 0
  159. #define FLAG_TYPE_AX88179 (1U << 0)
  160. #define FLAG_TYPE_AX88178a (1U << 1)
  161. #define FLAG_TYPE_DLINK_DUB1312 (1U << 2)
  162. #define FLAG_TYPE_SITECOM (1U << 3)
  163. #define FLAG_TYPE_SAMSUNG (1U << 4)
  164. #define FLAG_TYPE_LENOVO (1U << 5)
  165. #define FLAG_TYPE_GX3 (1U << 6)
  166. /* local vars */
  167. static const struct {
  168. unsigned char ctrl, timer_l, timer_h, size, ifg;
  169. } AX88179_BULKIN_SIZE[] = {
  170. {7, 0x4f, 0, 0x02, 0xff},
  171. {7, 0x20, 3, 0x03, 0xff},
  172. {7, 0xae, 7, 0x04, 0xff},
  173. {7, 0xcc, 0x4c, 0x04, 8},
  174. };
  175. #ifndef CONFIG_DM_ETH
  176. static int curr_eth_dev; /* index for name of next device detected */
  177. #endif
  178. /* driver private */
  179. struct asix_private {
  180. #ifdef CONFIG_DM_ETH
  181. struct ueth_data ueth;
  182. unsigned pkt_cnt;
  183. uint8_t *pkt_data;
  184. uint32_t *pkt_hdr;
  185. #endif
  186. int flags;
  187. int rx_urb_size;
  188. int maxpacketsize;
  189. };
  190. /*
  191. * Asix infrastructure commands
  192. */
  193. static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
  194. u16 size, void *data)
  195. {
  196. int len;
  197. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
  198. debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
  199. cmd, value, index, size);
  200. memcpy(buf, data, size);
  201. len = usb_control_msg(
  202. dev->pusb_dev,
  203. usb_sndctrlpipe(dev->pusb_dev, 0),
  204. cmd,
  205. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  206. value,
  207. index,
  208. buf,
  209. size,
  210. USB_CTRL_SET_TIMEOUT);
  211. return len == size ? 0 : ECOMM;
  212. }
  213. static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
  214. u16 size, void *data)
  215. {
  216. int len;
  217. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
  218. debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
  219. cmd, value, index, size);
  220. len = usb_control_msg(
  221. dev->pusb_dev,
  222. usb_rcvctrlpipe(dev->pusb_dev, 0),
  223. cmd,
  224. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  225. value,
  226. index,
  227. buf,
  228. size,
  229. USB_CTRL_GET_TIMEOUT);
  230. memcpy(data, buf, size);
  231. return len == size ? 0 : ECOMM;
  232. }
  233. static int asix_read_mac(struct ueth_data *dev, uint8_t *enetaddr)
  234. {
  235. int ret;
  236. ret = asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, enetaddr);
  237. if (ret < 0)
  238. debug("Failed to read MAC address: %02x\n", ret);
  239. return ret;
  240. }
  241. static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr)
  242. {
  243. int ret;
  244. ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  245. ETH_ALEN, enetaddr);
  246. if (ret < 0)
  247. debug("Failed to set MAC address: %02x\n", ret);
  248. return ret;
  249. }
  250. static int asix_basic_reset(struct ueth_data *dev,
  251. struct asix_private *dev_priv)
  252. {
  253. u8 buf[5];
  254. u16 *tmp16;
  255. u8 *tmp;
  256. tmp16 = (u16 *)buf;
  257. tmp = (u8 *)buf;
  258. /* Power up ethernet PHY */
  259. *tmp16 = 0;
  260. asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  261. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  262. asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  263. mdelay(200);
  264. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  265. asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  266. mdelay(200);
  267. /* RX bulk configuration */
  268. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  269. asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  270. dev_priv->rx_urb_size = 128 * 20;
  271. /* Water Level configuration */
  272. *tmp = 0x34;
  273. asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  274. *tmp = 0x52;
  275. asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp);
  276. /* Enable checksum offload */
  277. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  278. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  279. asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  280. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  281. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  282. asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  283. /* Configure RX control register => start operation */
  284. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  285. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  286. asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  287. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  288. AX_MONITOR_MODE_RWMP;
  289. asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  290. /* Configure default medium type => giga */
  291. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  292. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
  293. AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
  294. asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
  295. u16 adv = 0;
  296. adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK |
  297. ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
  298. asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
  299. adv = ADVERTISE_1000FULL;
  300. asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
  301. return 0;
  302. }
  303. static int asix_wait_link(struct ueth_data *dev)
  304. {
  305. int timeout = 0;
  306. int link_detected;
  307. u8 buf[2];
  308. u16 *tmp16;
  309. tmp16 = (u16 *)buf;
  310. do {
  311. asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  312. MII_BMSR, 2, buf);
  313. link_detected = *tmp16 & BMSR_LSTATUS;
  314. if (!link_detected) {
  315. if (timeout == 0)
  316. printf("Waiting for Ethernet connection... ");
  317. mdelay(TIMEOUT_RESOLUTION);
  318. timeout += TIMEOUT_RESOLUTION;
  319. }
  320. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  321. if (link_detected) {
  322. if (timeout > 0)
  323. printf("done.\n");
  324. return 0;
  325. } else {
  326. printf("unable to connect.\n");
  327. return -ENETUNREACH;
  328. }
  329. }
  330. static int asix_init_common(struct ueth_data *dev,
  331. struct asix_private *dev_priv)
  332. {
  333. u8 buf[2], tmp[5], link_sts;
  334. u16 *tmp16, mode;
  335. tmp16 = (u16 *)buf;
  336. debug("** %s()\n", __func__);
  337. /* Configure RX control register => start operation */
  338. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  339. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  340. if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0)
  341. goto out_err;
  342. if (asix_wait_link(dev) != 0) {
  343. /*reset device and try again*/
  344. printf("Reset Ethernet Device\n");
  345. asix_basic_reset(dev, dev_priv);
  346. if (asix_wait_link(dev) != 0)
  347. goto out_err;
  348. }
  349. /* Configure link */
  350. mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  351. AX_MEDIUM_RXFLOW_CTRLEN;
  352. asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
  353. 1, 1, &link_sts);
  354. asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  355. GMII_PHY_PHYSR, 2, tmp16);
  356. if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) {
  357. return 0;
  358. } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
  359. mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ |
  360. AX_MEDIUM_JUMBO_EN;
  361. if (link_sts & AX_USB_SS)
  362. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  363. else if (link_sts & AX_USB_HS)
  364. memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
  365. else
  366. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  367. } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
  368. mode |= AX_MEDIUM_PS;
  369. if (link_sts & (AX_USB_SS | AX_USB_HS))
  370. memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
  371. else
  372. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  373. } else {
  374. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  375. }
  376. /* RX bulk configuration */
  377. asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  378. dev_priv->rx_urb_size = (1024 * (tmp[3] + 2));
  379. if (*tmp16 & GMII_PHY_PHYSR_FULL)
  380. mode |= AX_MEDIUM_FULL_DUPLEX;
  381. asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  382. 2, 2, &mode);
  383. return 0;
  384. out_err:
  385. return -1;
  386. }
  387. static int asix_send_common(struct ueth_data *dev,
  388. struct asix_private *dev_priv,
  389. void *packet, int length)
  390. {
  391. int err;
  392. u32 packet_len, tx_hdr2;
  393. int actual_len, framesize;
  394. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
  395. PKTSIZE + (2 * sizeof(packet_len)));
  396. debug("** %s(), len %d\n", __func__, length);
  397. packet_len = length;
  398. cpu_to_le32s(&packet_len);
  399. memcpy(msg, &packet_len, sizeof(packet_len));
  400. framesize = dev_priv->maxpacketsize;
  401. tx_hdr2 = 0;
  402. if (((length + 8) % framesize) == 0)
  403. tx_hdr2 |= 0x80008000; /* Enable padding */
  404. cpu_to_le32s(&tx_hdr2);
  405. memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2));
  406. memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2),
  407. (void *)packet, length);
  408. err = usb_bulk_msg(dev->pusb_dev,
  409. usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
  410. (void *)msg,
  411. length + sizeof(packet_len) + sizeof(tx_hdr2),
  412. &actual_len,
  413. USB_BULK_SEND_TIMEOUT);
  414. debug("Tx: len = %zu, actual = %u, err = %d\n",
  415. length + sizeof(packet_len), actual_len, err);
  416. return err;
  417. }
  418. #ifndef CONFIG_DM_ETH
  419. /*
  420. * Asix callbacks
  421. */
  422. static int asix_init(struct eth_device *eth, bd_t *bd)
  423. {
  424. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  425. struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
  426. return asix_init_common(dev, dev_priv);
  427. }
  428. static int asix_write_hwaddr(struct eth_device *eth)
  429. {
  430. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  431. return asix_write_mac(dev, eth->enetaddr);
  432. }
  433. static int asix_send(struct eth_device *eth, void *packet, int length)
  434. {
  435. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  436. struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
  437. return asix_send_common(dev, dev_priv, packet, length);
  438. }
  439. static int asix_recv(struct eth_device *eth)
  440. {
  441. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  442. struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
  443. u16 frame_pos;
  444. int err;
  445. int actual_len;
  446. int pkt_cnt;
  447. u32 rx_hdr;
  448. u16 hdr_off;
  449. u32 *pkt_hdr;
  450. ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size);
  451. actual_len = -1;
  452. debug("** %s()\n", __func__);
  453. err = usb_bulk_msg(dev->pusb_dev,
  454. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  455. (void *)recv_buf,
  456. dev_priv->rx_urb_size,
  457. &actual_len,
  458. USB_BULK_RECV_TIMEOUT);
  459. debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size,
  460. actual_len, err);
  461. if (err != 0) {
  462. debug("Rx: failed to receive\n");
  463. return -ECOMM;
  464. }
  465. if (actual_len > dev_priv->rx_urb_size) {
  466. debug("Rx: received too many bytes %d\n", actual_len);
  467. return -EMSGSIZE;
  468. }
  469. rx_hdr = *(u32 *)(recv_buf + actual_len - 4);
  470. le32_to_cpus(&rx_hdr);
  471. pkt_cnt = (u16)rx_hdr;
  472. hdr_off = (u16)(rx_hdr >> 16);
  473. pkt_hdr = (u32 *)(recv_buf + hdr_off);
  474. frame_pos = 0;
  475. while (pkt_cnt--) {
  476. u16 pkt_len;
  477. le32_to_cpus(pkt_hdr);
  478. pkt_len = (*pkt_hdr >> 16) & 0x1fff;
  479. frame_pos += 2;
  480. net_process_received_packet(recv_buf + frame_pos, pkt_len);
  481. pkt_hdr++;
  482. frame_pos += ((pkt_len + 7) & 0xFFF8)-2;
  483. if (pkt_cnt == 0)
  484. return 0;
  485. }
  486. return err;
  487. }
  488. static void asix_halt(struct eth_device *eth)
  489. {
  490. debug("** %s()\n", __func__);
  491. }
  492. /*
  493. * Asix probing functions
  494. */
  495. void ax88179_eth_before_probe(void)
  496. {
  497. curr_eth_dev = 0;
  498. }
  499. struct asix_dongle {
  500. unsigned short vendor;
  501. unsigned short product;
  502. int flags;
  503. };
  504. static const struct asix_dongle asix_dongles[] = {
  505. { 0x0b95, 0x1790, FLAG_TYPE_AX88179 },
  506. { 0x0b95, 0x178a, FLAG_TYPE_AX88178a },
  507. { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 },
  508. { 0x0df6, 0x0072, FLAG_TYPE_SITECOM },
  509. { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG },
  510. { 0x17ef, 0x304b, FLAG_TYPE_LENOVO },
  511. { 0x04b4, 0x3610, FLAG_TYPE_GX3 },
  512. { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
  513. };
  514. /* Probe to see if a new device is actually an asix device */
  515. int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
  516. struct ueth_data *ss)
  517. {
  518. struct usb_interface *iface;
  519. struct usb_interface_descriptor *iface_desc;
  520. struct asix_private *dev_priv;
  521. int ep_in_found = 0, ep_out_found = 0;
  522. int i;
  523. /* let's examine the device now */
  524. iface = &dev->config.if_desc[ifnum];
  525. iface_desc = &dev->config.if_desc[ifnum].desc;
  526. for (i = 0; asix_dongles[i].vendor != 0; i++) {
  527. if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
  528. dev->descriptor.idProduct == asix_dongles[i].product)
  529. /* Found a supported dongle */
  530. break;
  531. }
  532. if (asix_dongles[i].vendor == 0)
  533. return 0;
  534. memset(ss, 0, sizeof(struct ueth_data));
  535. /* At this point, we know we've got a live one */
  536. debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
  537. dev->descriptor.idVendor, dev->descriptor.idProduct);
  538. /* Initialize the ueth_data structure with some useful info */
  539. ss->ifnum = ifnum;
  540. ss->pusb_dev = dev;
  541. ss->subclass = iface_desc->bInterfaceSubClass;
  542. ss->protocol = iface_desc->bInterfaceProtocol;
  543. /* alloc driver private */
  544. ss->dev_priv = calloc(1, sizeof(struct asix_private));
  545. if (!ss->dev_priv)
  546. return 0;
  547. dev_priv = ss->dev_priv;
  548. dev_priv->flags = asix_dongles[i].flags;
  549. /*
  550. * We are expecting a minimum of 3 endpoints - in, out (bulk), and
  551. * int. We will ignore any others.
  552. */
  553. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  554. /* is it an interrupt endpoint? */
  555. if ((iface->ep_desc[i].bmAttributes &
  556. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  557. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  558. USB_ENDPOINT_NUMBER_MASK;
  559. ss->irqinterval = iface->ep_desc[i].bInterval;
  560. continue;
  561. }
  562. /* is it an BULK endpoint? */
  563. if (!((iface->ep_desc[i].bmAttributes &
  564. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
  565. continue;
  566. u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
  567. if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
  568. ss->ep_in = ep_addr &
  569. USB_ENDPOINT_NUMBER_MASK;
  570. ep_in_found = 1;
  571. }
  572. if (!(ep_addr & USB_DIR_IN) && !ep_out_found) {
  573. ss->ep_out = ep_addr &
  574. USB_ENDPOINT_NUMBER_MASK;
  575. dev_priv->maxpacketsize =
  576. dev->epmaxpacketout[AX_ENDPOINT_OUT];
  577. ep_out_found = 1;
  578. }
  579. }
  580. debug("Endpoints In %d Out %d Int %d\n",
  581. ss->ep_in, ss->ep_out, ss->ep_int);
  582. /* Do some basic sanity checks, and bail if we find a problem */
  583. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  584. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  585. debug("Problems with device\n");
  586. return 0;
  587. }
  588. dev->privptr = (void *)ss;
  589. return 1;
  590. }
  591. int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  592. struct eth_device *eth)
  593. {
  594. struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv;
  595. if (!eth) {
  596. debug("%s: missing parameter.\n", __func__);
  597. return 0;
  598. }
  599. sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
  600. eth->init = asix_init;
  601. eth->send = asix_send;
  602. eth->recv = asix_recv;
  603. eth->halt = asix_halt;
  604. eth->write_hwaddr = asix_write_hwaddr;
  605. eth->priv = ss;
  606. if (asix_basic_reset(ss, dev_priv))
  607. return 0;
  608. /* Get the MAC address */
  609. if (asix_read_mac(ss, eth->enetaddr))
  610. return 0;
  611. debug("MAC %pM\n", eth->enetaddr);
  612. return 1;
  613. }
  614. #else /* !CONFIG_DM_ETH */
  615. static int ax88179_eth_start(struct udevice *dev)
  616. {
  617. struct asix_private *priv = dev_get_priv(dev);
  618. return asix_init_common(&priv->ueth, priv);
  619. }
  620. void ax88179_eth_stop(struct udevice *dev)
  621. {
  622. struct asix_private *priv = dev_get_priv(dev);
  623. struct ueth_data *ueth = &priv->ueth;
  624. debug("** %s()\n", __func__);
  625. usb_ether_advance_rxbuf(ueth, -1);
  626. priv->pkt_cnt = 0;
  627. priv->pkt_data = NULL;
  628. priv->pkt_hdr = NULL;
  629. }
  630. int ax88179_eth_send(struct udevice *dev, void *packet, int length)
  631. {
  632. struct asix_private *priv = dev_get_priv(dev);
  633. return asix_send_common(&priv->ueth, priv, packet, length);
  634. }
  635. int ax88179_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  636. {
  637. struct asix_private *priv = dev_get_priv(dev);
  638. struct ueth_data *ueth = &priv->ueth;
  639. int ret, len;
  640. u16 pkt_len;
  641. /* No packet left, get a new one */
  642. if (priv->pkt_cnt == 0) {
  643. uint8_t *ptr;
  644. u16 pkt_cnt;
  645. u16 hdr_off;
  646. u32 rx_hdr;
  647. len = usb_ether_get_rx_bytes(ueth, &ptr);
  648. debug("%s: first try, len=%d\n", __func__, len);
  649. if (!len) {
  650. if (!(flags & ETH_RECV_CHECK_DEVICE))
  651. return -EAGAIN;
  652. ret = usb_ether_receive(ueth, priv->rx_urb_size);
  653. if (ret < 0)
  654. return ret;
  655. len = usb_ether_get_rx_bytes(ueth, &ptr);
  656. debug("%s: second try, len=%d\n", __func__, len);
  657. }
  658. if (len < 4) {
  659. usb_ether_advance_rxbuf(ueth, -1);
  660. return -EMSGSIZE;
  661. }
  662. rx_hdr = *(u32 *)(ptr + len - 4);
  663. le32_to_cpus(&rx_hdr);
  664. pkt_cnt = (u16)rx_hdr;
  665. if (pkt_cnt == 0) {
  666. usb_ether_advance_rxbuf(ueth, -1);
  667. return 0;
  668. }
  669. hdr_off = (u16)(rx_hdr >> 16);
  670. if (hdr_off > len - 4) {
  671. usb_ether_advance_rxbuf(ueth, -1);
  672. return -EIO;
  673. }
  674. priv->pkt_cnt = pkt_cnt;
  675. priv->pkt_data = ptr;
  676. priv->pkt_hdr = (u32 *)(ptr + hdr_off);
  677. debug("%s: %d packets received, pkt header at %d\n",
  678. __func__, (int)priv->pkt_cnt, (int)hdr_off);
  679. }
  680. le32_to_cpus(priv->pkt_hdr);
  681. pkt_len = (*priv->pkt_hdr >> 16) & 0x1fff;
  682. *packetp = priv->pkt_data + 2;
  683. priv->pkt_data += (pkt_len + 7) & 0xFFF8;
  684. priv->pkt_cnt--;
  685. priv->pkt_hdr++;
  686. debug("%s: return packet of %d bytes (%d packets left)\n",
  687. __func__, (int)pkt_len, priv->pkt_cnt);
  688. return pkt_len;
  689. }
  690. static int ax88179_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
  691. {
  692. struct asix_private *priv = dev_get_priv(dev);
  693. struct ueth_data *ueth = &priv->ueth;
  694. if (priv->pkt_cnt == 0)
  695. usb_ether_advance_rxbuf(ueth, -1);
  696. return 0;
  697. }
  698. int ax88179_write_hwaddr(struct udevice *dev)
  699. {
  700. struct eth_pdata *pdata = dev_get_platdata(dev);
  701. struct asix_private *priv = dev_get_priv(dev);
  702. struct ueth_data *ueth = &priv->ueth;
  703. return asix_write_mac(ueth, pdata->enetaddr);
  704. }
  705. static int ax88179_eth_probe(struct udevice *dev)
  706. {
  707. struct eth_pdata *pdata = dev_get_platdata(dev);
  708. struct asix_private *priv = dev_get_priv(dev);
  709. struct usb_device *usb_dev;
  710. int ret;
  711. priv->flags = dev->driver_data;
  712. ret = usb_ether_register(dev, &priv->ueth, AX_RX_URB_SIZE);
  713. if (ret)
  714. return ret;
  715. usb_dev = priv->ueth.pusb_dev;
  716. priv->maxpacketsize = usb_dev->epmaxpacketout[AX_ENDPOINT_OUT];
  717. /* Get the MAC address */
  718. ret = asix_read_mac(&priv->ueth, pdata->enetaddr);
  719. if (ret)
  720. return ret;
  721. debug("MAC %pM\n", pdata->enetaddr);
  722. return 0;
  723. }
  724. static const struct eth_ops ax88179_eth_ops = {
  725. .start = ax88179_eth_start,
  726. .send = ax88179_eth_send,
  727. .recv = ax88179_eth_recv,
  728. .free_pkt = ax88179_free_pkt,
  729. .stop = ax88179_eth_stop,
  730. .write_hwaddr = ax88179_write_hwaddr,
  731. };
  732. U_BOOT_DRIVER(ax88179_eth) = {
  733. .name = "ax88179_eth",
  734. .id = UCLASS_ETH,
  735. .probe = ax88179_eth_probe,
  736. .ops = &ax88179_eth_ops,
  737. .priv_auto_alloc_size = sizeof(struct asix_private),
  738. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  739. };
  740. static const struct usb_device_id ax88179_eth_id_table[] = {
  741. { USB_DEVICE(0x0b95, 0x1790), .driver_info = FLAG_TYPE_AX88179 },
  742. { USB_DEVICE(0x0b95, 0x178a), .driver_info = FLAG_TYPE_AX88178a },
  743. { USB_DEVICE(0x2001, 0x4a00), .driver_info = FLAG_TYPE_DLINK_DUB1312 },
  744. { USB_DEVICE(0x0df6, 0x0072), .driver_info = FLAG_TYPE_SITECOM },
  745. { USB_DEVICE(0x04e8, 0xa100), .driver_info = FLAG_TYPE_SAMSUNG },
  746. { USB_DEVICE(0x17ef, 0x304b), .driver_info = FLAG_TYPE_LENOVO },
  747. { USB_DEVICE(0x04b4, 0x3610), .driver_info = FLAG_TYPE_GX3 },
  748. { } /* Terminating entry */
  749. };
  750. U_BOOT_USB_DEVICE(ax88179_eth, ax88179_eth_id_table);
  751. #endif /* !CONFIG_DM_ETH */