Kconfig 6.6 KB

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  1. menu "SPI Support"
  2. config DM_SPI
  3. bool "Enable Driver Model for SPI drivers"
  4. depends on DM
  5. help
  6. Enable driver model for SPI. The SPI slave interface
  7. (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
  8. the SPI uclass. Drivers provide methods to access the SPI
  9. buses that they control. The uclass interface is defined in
  10. include/spi.h. The existing spi_slave structure is attached
  11. as 'parent data' to every slave on each bus. Slaves
  12. typically use driver-private data instead of extending the
  13. spi_slave structure.
  14. if DM_SPI
  15. config ALTERA_SPI
  16. bool "Altera SPI driver"
  17. help
  18. Enable the Altera SPI driver. This driver can be used to
  19. access the SPI NOR flash on platforms embedding this Altera
  20. IP core. Please find details on the "Embedded Peripherals IP
  21. User Guide" of Altera.
  22. config ATH79_SPI
  23. bool "Atheros SPI driver"
  24. depends on ARCH_ATH79
  25. help
  26. Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
  27. to access SPI NOR flash and other SPI peripherals. This driver
  28. uses driver model and requires a device tree binding to operate.
  29. please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
  30. config ATMEL_SPI
  31. bool "Atmel SPI driver"
  32. depends on ARCH_AT91
  33. help
  34. This enables driver for the Atmel SPI Controller, present on
  35. many AT32 (AVR32) and AT91 (ARM) chips. This driver can be
  36. used to access the SPI Flash, such as AT25DF321.
  37. config CADENCE_QSPI
  38. bool "Cadence QSPI driver"
  39. help
  40. Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
  41. used to access the SPI NOR flash on platforms embedding this
  42. Cadence IP core.
  43. config DESIGNWARE_SPI
  44. bool "Designware SPI driver"
  45. help
  46. Enable the Designware SPI driver. This driver can be used to
  47. access the SPI NOR flash on platforms embedding this Designware
  48. IP core.
  49. config EXYNOS_SPI
  50. bool "Samsung Exynos SPI driver"
  51. help
  52. Enable the Samsung Exynos SPI driver. This driver can be used to
  53. access the SPI NOR flash on platforms embedding this Samsung
  54. Exynos IP core.
  55. config FSL_DSPI
  56. bool "Freescale DSPI driver"
  57. help
  58. Enable the Freescale DSPI driver. This driver can be used to
  59. access the SPI NOR flash and SPI Data flash on platforms embedding
  60. this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
  61. use this driver.
  62. config ICH_SPI
  63. bool "Intel ICH SPI driver"
  64. help
  65. Enable the Intel ICH SPI driver. This driver can be used to
  66. access the SPI NOR flash on platforms embedding this Intel
  67. ICH IP core.
  68. config MVEBU_A3700_SPI
  69. bool "Marvell Armada 3700 SPI driver"
  70. help
  71. Enable the Marvell Armada 3700 SPI driver. This driver can be
  72. used to access the SPI NOR flash on platforms embedding this
  73. Marvell IP core.
  74. config PIC32_SPI
  75. bool "Microchip PIC32 SPI driver"
  76. depends on MACH_PIC32
  77. help
  78. Enable the Microchip PIC32 SPI driver. This driver can be used
  79. to access the SPI NOR flash, MMC-over-SPI on platforms based on
  80. Microchip PIC32 family devices.
  81. config ROCKCHIP_SPI
  82. bool "Rockchip SPI driver"
  83. help
  84. Enable the Rockchip SPI driver, used to access SPI NOR flash and
  85. other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
  86. This uses driver model and requires a device tree binding to
  87. operate.
  88. config SANDBOX_SPI
  89. bool "Sandbox SPI driver"
  90. depends on SANDBOX && DM
  91. help
  92. Enable SPI support for sandbox. This is an emulation of a real SPI
  93. bus. Devices can be attached to the bus using the device tree
  94. which specifies the driver to use. As an example, see this device
  95. tree fragment from sandbox.dts. It shows that the SPI bus has a
  96. single flash device on chip select 0 which is emulated by the driver
  97. for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
  98. spi@0 {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. reg = <0>;
  102. compatible = "sandbox,spi";
  103. cs-gpios = <0>, <&gpio_a 0>;
  104. flash@0 {
  105. reg = <0>;
  106. compatible = "spansion,m25p16", "sandbox,spi-flash";
  107. spi-max-frequency = <40000000>;
  108. sandbox,filename = "spi.bin";
  109. };
  110. };
  111. config TEGRA114_SPI
  112. bool "nVidia Tegra114 SPI driver"
  113. help
  114. Enable the nVidia Tegra114 SPI driver. This driver can be used to
  115. access the SPI NOR flash on platforms embedding this nVidia Tegra114
  116. IP core.
  117. This controller is different than the older SoCs SPI controller and
  118. also register interface get changed with this controller.
  119. config TEGRA20_SFLASH
  120. bool "nVidia Tegra20 Serial Flash controller driver"
  121. help
  122. Enable the nVidia Tegra20 Serial Flash controller driver. This driver
  123. can be used to access the SPI NOR flash on platforms embedding this
  124. nVidia Tegra20 IP core.
  125. config TEGRA20_SLINK
  126. bool "nVidia Tegra20/Tegra30 SLINK driver"
  127. help
  128. Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
  129. be used to access the SPI NOR flash on platforms embedding this
  130. nVidia Tegra20/Tegra30 IP cores.
  131. config TEGRA210_QSPI
  132. bool "nVidia Tegra210 QSPI driver"
  133. help
  134. Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver
  135. be used to access SPI chips on platforms embedding this
  136. NVIDIA Tegra210 IP core.
  137. config XILINX_SPI
  138. bool "Xilinx SPI driver"
  139. help
  140. Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
  141. controller support 8 bit SPI transfers only, with or w/o FIFO.
  142. For more info on Xilinx SPI Register Definitions and Overview
  143. see driver file - drivers/spi/xilinx_spi.c
  144. config ZYNQ_SPI
  145. bool "Zynq SPI driver"
  146. depends on ARCH_ZYNQ || ARCH_ZYNQMP
  147. help
  148. Enable the Zynq SPI driver. This driver can be used to
  149. access the SPI NOR flash on platforms embedding this Zynq
  150. SPI IP core.
  151. config ZYNQ_QSPI
  152. bool "Zynq QSPI driver"
  153. depends on ARCH_ZYNQ
  154. help
  155. Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
  156. used to access the SPI NOR flash on platforms embedding this
  157. Zynq QSPI IP core. This IP is used to connect the flash in
  158. 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
  159. config OMAP3_SPI
  160. bool "McSPI driver for OMAP"
  161. help
  162. SPI master controller for OMAP24XX and later Multichannel SPI
  163. (McSPI). This driver be used to access SPI chips on platforms
  164. embedding this OMAP3 McSPI IP core.
  165. endif # if DM_SPI
  166. config FSL_ESPI
  167. bool "Freescale eSPI driver"
  168. help
  169. Enable the Freescale eSPI driver. This driver can be used to
  170. access the SPI interface and SPI NOR flash on platforms embedding
  171. this Freescale eSPI IP core.
  172. config FSL_QSPI
  173. bool "Freescale QSPI driver"
  174. help
  175. Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
  176. used to access the SPI NOR flash on platforms embedding this
  177. Freescale IP core.
  178. config TI_QSPI
  179. bool "TI QSPI driver"
  180. help
  181. Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
  182. This driver support spi flash single, quad and memory reads.
  183. endmenu # menu "SPI Support"