ds1337.c 5.1 KB

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  1. /*
  2. * (C) Copyright 2001-2008
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. * Keith Outwater, keith_outwater@mvis.com`
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. /*
  9. * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
  10. * DS1337 Real Time Clock (RTC).
  11. */
  12. #include <common.h>
  13. #include <command.h>
  14. #include <rtc.h>
  15. #include <i2c.h>
  16. #if defined(CONFIG_CMD_DATE)
  17. /*
  18. * RTC register addresses
  19. */
  20. #if defined CONFIG_RTC_DS1337
  21. #define RTC_SEC_REG_ADDR 0x0
  22. #define RTC_MIN_REG_ADDR 0x1
  23. #define RTC_HR_REG_ADDR 0x2
  24. #define RTC_DAY_REG_ADDR 0x3
  25. #define RTC_DATE_REG_ADDR 0x4
  26. #define RTC_MON_REG_ADDR 0x5
  27. #define RTC_YR_REG_ADDR 0x6
  28. #define RTC_CTL_REG_ADDR 0x0e
  29. #define RTC_STAT_REG_ADDR 0x0f
  30. #define RTC_TC_REG_ADDR 0x10
  31. #elif defined CONFIG_RTC_DS1388
  32. #define RTC_SEC_REG_ADDR 0x1
  33. #define RTC_MIN_REG_ADDR 0x2
  34. #define RTC_HR_REG_ADDR 0x3
  35. #define RTC_DAY_REG_ADDR 0x4
  36. #define RTC_DATE_REG_ADDR 0x5
  37. #define RTC_MON_REG_ADDR 0x6
  38. #define RTC_YR_REG_ADDR 0x7
  39. #define RTC_CTL_REG_ADDR 0x0c
  40. #define RTC_STAT_REG_ADDR 0x0b
  41. #define RTC_TC_REG_ADDR 0x0a
  42. #endif
  43. /*
  44. * RTC control register bits
  45. */
  46. #define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
  47. #define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
  48. #define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
  49. #define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
  50. #define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
  51. #define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
  52. /*
  53. * RTC status register bits
  54. */
  55. #define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
  56. #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
  57. #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
  58. static uchar rtc_read (uchar reg);
  59. static void rtc_write (uchar reg, uchar val);
  60. /*
  61. * Get the current time from the RTC
  62. */
  63. int rtc_get (struct rtc_time *tmp)
  64. {
  65. int rel = 0;
  66. uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
  67. control = rtc_read (RTC_CTL_REG_ADDR);
  68. status = rtc_read (RTC_STAT_REG_ADDR);
  69. sec = rtc_read (RTC_SEC_REG_ADDR);
  70. min = rtc_read (RTC_MIN_REG_ADDR);
  71. hour = rtc_read (RTC_HR_REG_ADDR);
  72. wday = rtc_read (RTC_DAY_REG_ADDR);
  73. mday = rtc_read (RTC_DATE_REG_ADDR);
  74. mon_cent = rtc_read (RTC_MON_REG_ADDR);
  75. year = rtc_read (RTC_YR_REG_ADDR);
  76. /* No century bit, assume year 2000 */
  77. #ifdef CONFIG_RTC_DS1388
  78. mon_cent |= 0x80;
  79. #endif
  80. debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
  81. "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
  82. year, mon_cent, mday, wday, hour, min, sec, control, status);
  83. if (status & RTC_STAT_BIT_OSF) {
  84. printf ("### Warning: RTC oscillator has stopped\n");
  85. /* clear the OSF flag */
  86. rtc_write (RTC_STAT_REG_ADDR,
  87. rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
  88. rel = -1;
  89. }
  90. tmp->tm_sec = bcd2bin (sec & 0x7F);
  91. tmp->tm_min = bcd2bin (min & 0x7F);
  92. tmp->tm_hour = bcd2bin (hour & 0x3F);
  93. tmp->tm_mday = bcd2bin (mday & 0x3F);
  94. tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
  95. tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
  96. tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
  97. tmp->tm_yday = 0;
  98. tmp->tm_isdst= 0;
  99. debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  100. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  101. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  102. return rel;
  103. }
  104. /*
  105. * Set the RTC
  106. */
  107. int rtc_set (struct rtc_time *tmp)
  108. {
  109. uchar century;
  110. debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  111. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  112. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  113. rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
  114. century = (tmp->tm_year >= 2000) ? 0x80 : 0;
  115. rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
  116. rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
  117. rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
  118. rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
  119. rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
  120. rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
  121. return 0;
  122. }
  123. /*
  124. * Reset the RTC. We also enable the oscillator output on the
  125. * SQW/INTB* pin and program it for 32,768 Hz output. Note that
  126. * according to the datasheet, turning on the square wave output
  127. * increases the current drain on the backup battery from about
  128. * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
  129. * off the OSC output.
  130. */
  131. #ifdef CONFIG_SYS_RTC_DS1337_NOOSC
  132. #define RTC_DS1337_RESET_VAL \
  133. (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
  134. #else
  135. #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
  136. #endif
  137. void rtc_reset (void)
  138. {
  139. #ifdef CONFIG_SYS_RTC_DS1337
  140. rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
  141. #elif defined CONFIG_SYS_RTC_DS1388
  142. rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
  143. #endif
  144. #ifdef CONFIG_SYS_DS1339_TCR_VAL
  145. rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
  146. #endif
  147. #ifdef CONFIG_SYS_DS1388_TCR_VAL
  148. rtc_write(RTC_TC_REG_ADDR, CONFIG_SYS_DS1388_TCR_VAL);
  149. #endif
  150. }
  151. /*
  152. * Helper functions
  153. */
  154. static
  155. uchar rtc_read (uchar reg)
  156. {
  157. return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
  158. }
  159. static void rtc_write (uchar reg, uchar val)
  160. {
  161. i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
  162. }
  163. #endif