rk_pwm.c 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. /*
  2. * Copyright (c) 2016 Google, Inc
  3. * Written by Simon Glass <sjg@chromium.org>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <div64.h>
  10. #include <dm.h>
  11. #include <pwm.h>
  12. #include <regmap.h>
  13. #include <syscon.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/pwm.h>
  16. #include <power/regulator.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. struct rk_pwm_priv {
  19. struct rk3288_pwm *regs;
  20. ulong freq;
  21. };
  22. static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
  23. uint duty_ns)
  24. {
  25. struct rk_pwm_priv *priv = dev_get_priv(dev);
  26. struct rk3288_pwm *regs = priv->regs;
  27. unsigned long period, duty;
  28. debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  29. writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
  30. PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
  31. RK_PWM_DISABLE,
  32. &regs->ctrl);
  33. period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
  34. duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
  35. writel(period, &regs->period_hpr);
  36. writel(duty, &regs->duty_lpr);
  37. debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
  38. return 0;
  39. }
  40. static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  41. {
  42. struct rk_pwm_priv *priv = dev_get_priv(dev);
  43. struct rk3288_pwm *regs = priv->regs;
  44. debug("%s: Enable '%s'\n", __func__, dev->name);
  45. clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
  46. return 0;
  47. }
  48. static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
  49. {
  50. struct rk_pwm_priv *priv = dev_get_priv(dev);
  51. priv->regs = (struct rk3288_pwm *)dev_get_addr(dev);
  52. return 0;
  53. }
  54. static int rk_pwm_probe(struct udevice *dev)
  55. {
  56. struct rk_pwm_priv *priv = dev_get_priv(dev);
  57. struct clk clk;
  58. int ret = 0;
  59. ret = clk_get_by_index(dev, 0, &clk);
  60. if (ret < 0) {
  61. debug("%s get clock fail!\n", __func__);
  62. return -EINVAL;
  63. }
  64. priv->freq = clk_get_rate(&clk);
  65. return 0;
  66. }
  67. static const struct pwm_ops rk_pwm_ops = {
  68. .set_config = rk_pwm_set_config,
  69. .set_enable = rk_pwm_set_enable,
  70. };
  71. static const struct udevice_id rk_pwm_ids[] = {
  72. { .compatible = "rockchip,rk3288-pwm" },
  73. { }
  74. };
  75. U_BOOT_DRIVER(rk_pwm) = {
  76. .name = "rk_pwm",
  77. .id = UCLASS_PWM,
  78. .of_match = rk_pwm_ids,
  79. .ops = &rk_pwm_ops,
  80. .ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
  81. .probe = rk_pwm_probe,
  82. .priv_auto_alloc_size = sizeof(struct rk_pwm_priv),
  83. };