s5m8767.c 6.6 KB

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  1. /*
  2. * Copyright (C) 2015 Google, Inc
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <fdtdec.h>
  8. #include <errno.h>
  9. #include <dm.h>
  10. #include <i2c.h>
  11. #include <power/pmic.h>
  12. #include <power/regulator.h>
  13. #include <power/s5m8767.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. static const struct sec_voltage_desc buck_v1 = {
  16. .max = 2225000,
  17. .min = 650000,
  18. .step = 6250,
  19. };
  20. static const struct sec_voltage_desc buck_v2 = {
  21. .max = 1600000,
  22. .min = 600000,
  23. .step = 6250,
  24. };
  25. static const struct sec_voltage_desc buck_v3 = {
  26. .max = 3000000,
  27. .min = 750000,
  28. .step = 12500,
  29. };
  30. static const struct sec_voltage_desc ldo_v1 = {
  31. .max = 3950000,
  32. .min = 800000,
  33. .step = 50000,
  34. };
  35. static const struct sec_voltage_desc ldo_v2 = {
  36. .max = 2375000,
  37. .min = 800000,
  38. .step = 25000,
  39. };
  40. static const struct s5m8767_para buck_param[] = {
  41. /*
  42. * | voltage ----| | enable -| voltage
  43. * regnum addr bpos mask addr on desc
  44. */
  45. {S5M8767_BUCK1, 0x33, 0x0, 0xff, 0x32, 0x3, &buck_v1},
  46. {S5M8767_BUCK2, 0x35, 0x0, 0xff, 0x34, 0x1, &buck_v2},
  47. {S5M8767_BUCK3, 0x3e, 0x0, 0xff, 0x3d, 0x1, &buck_v2},
  48. {S5M8767_BUCK4, 0x47, 0x0, 0xff, 0x46, 0x1, &buck_v2},
  49. {S5M8767_BUCK5, 0x50, 0x0, 0xff, 0x4f, 0x3, &buck_v1},
  50. {S5M8767_BUCK6, 0x55, 0x0, 0xff, 0x54, 0x3, &buck_v1},
  51. {S5M8767_BUCK7, 0x57, 0x0, 0xff, 0x56, 0x3, &buck_v3},
  52. {S5M8767_BUCK8, 0x59, 0x0, 0xff, 0x58, 0x3, &buck_v3},
  53. {S5M8767_BUCK9, 0x5b, 0x0, 0xff, 0x5a, 0x3, &buck_v3},
  54. };
  55. static const struct s5m8767_para ldo_param[] = {
  56. {S5M8767_LDO1, 0x5c, 0x0, 0x3f, 0x5c, 0x3, &ldo_v2},
  57. {S5M8767_LDO2, 0x5d, 0x0, 0x3f, 0x5d, 0x1, &ldo_v2},
  58. {S5M8767_LDO3, 0x61, 0x0, 0x3f, 0x61, 0x3, &ldo_v1},
  59. {S5M8767_LDO4, 0x62, 0x0, 0x3f, 0x62, 0x3, &ldo_v1},
  60. {S5M8767_LDO5, 0x63, 0x0, 0x3f, 0x63, 0x3, &ldo_v1},
  61. {S5M8767_LDO6, 0x64, 0x0, 0x3f, 0x64, 0x1, &ldo_v2},
  62. {S5M8767_LDO7, 0x65, 0x0, 0x3f, 0x65, 0x1, &ldo_v2},
  63. {S5M8767_LDO8, 0x66, 0x0, 0x3f, 0x66, 0x1, &ldo_v2},
  64. {S5M8767_LDO9, 0x67, 0x0, 0x3f, 0x67, 0x3, &ldo_v1},
  65. {S5M8767_LDO10, 0x68, 0x0, 0x3f, 0x68, 0x1, &ldo_v1},
  66. {S5M8767_LDO11, 0x69, 0x0, 0x3f, 0x69, 0x1, &ldo_v1},
  67. {S5M8767_LDO12, 0x6a, 0x0, 0x3f, 0x6a, 0x1, &ldo_v1},
  68. {S5M8767_LDO13, 0x6b, 0x0, 0x3f, 0x6b, 0x3, &ldo_v1},
  69. {S5M8767_LDO14, 0x6c, 0x0, 0x3f, 0x6c, 0x1, &ldo_v1},
  70. {S5M8767_LDO15, 0x6d, 0x0, 0x3f, 0x6d, 0x1, &ldo_v2},
  71. {S5M8767_LDO16, 0x6e, 0x0, 0x3f, 0x6e, 0x1, &ldo_v1},
  72. {S5M8767_LDO17, 0x6f, 0x0, 0x3f, 0x6f, 0x3, &ldo_v1},
  73. {S5M8767_LDO18, 0x70, 0x0, 0x3f, 0x70, 0x3, &ldo_v1},
  74. {S5M8767_LDO19, 0x71, 0x0, 0x3f, 0x71, 0x3, &ldo_v1},
  75. {S5M8767_LDO20, 0x72, 0x0, 0x3f, 0x72, 0x3, &ldo_v1},
  76. {S5M8767_LDO21, 0x73, 0x0, 0x3f, 0x73, 0x3, &ldo_v1},
  77. {S5M8767_LDO22, 0x74, 0x0, 0x3f, 0x74, 0x3, &ldo_v1},
  78. {S5M8767_LDO23, 0x75, 0x0, 0x3f, 0x75, 0x3, &ldo_v1},
  79. {S5M8767_LDO24, 0x76, 0x0, 0x3f, 0x76, 0x3, &ldo_v1},
  80. {S5M8767_LDO25, 0x77, 0x0, 0x3f, 0x77, 0x3, &ldo_v1},
  81. {S5M8767_LDO26, 0x78, 0x0, 0x3f, 0x78, 0x3, &ldo_v1},
  82. {S5M8767_LDO27, 0x79, 0x0, 0x3f, 0x79, 0x3, &ldo_v1},
  83. {S5M8767_LDO28, 0x7a, 0x0, 0x3f, 0x7a, 0x3, &ldo_v1},
  84. };
  85. enum {
  86. ENABLE_SHIFT = 6,
  87. ENABLE_MASK = 3,
  88. };
  89. static int reg_get_value(struct udevice *dev, const struct s5m8767_para *param)
  90. {
  91. const struct sec_voltage_desc *desc;
  92. int ret, uv, val;
  93. ret = pmic_reg_read(dev->parent, param->vol_addr);
  94. if (ret < 0)
  95. return ret;
  96. desc = param->vol;
  97. val = (ret >> param->vol_bitpos) & param->vol_bitmask;
  98. uv = desc->min + val * desc->step;
  99. return uv;
  100. }
  101. static int reg_set_value(struct udevice *dev, const struct s5m8767_para *param,
  102. int uv)
  103. {
  104. const struct sec_voltage_desc *desc;
  105. int ret, val;
  106. desc = param->vol;
  107. if (uv < desc->min || uv > desc->max)
  108. return -EINVAL;
  109. val = (uv - desc->min) / desc->step;
  110. val = (val & param->vol_bitmask) << param->vol_bitpos;
  111. ret = pmic_clrsetbits(dev->parent, param->vol_addr,
  112. param->vol_bitmask << param->vol_bitpos,
  113. val);
  114. return ret;
  115. }
  116. static int s5m8767_ldo_probe(struct udevice *dev)
  117. {
  118. struct dm_regulator_uclass_platdata *uc_pdata;
  119. uc_pdata = dev_get_uclass_platdata(dev);
  120. uc_pdata->type = REGULATOR_TYPE_LDO;
  121. uc_pdata->mode_count = 0;
  122. return 0;
  123. }
  124. static int ldo_get_value(struct udevice *dev)
  125. {
  126. int ldo = dev->driver_data;
  127. return reg_get_value(dev, &ldo_param[ldo]);
  128. }
  129. static int ldo_set_value(struct udevice *dev, int uv)
  130. {
  131. int ldo = dev->driver_data;
  132. return reg_set_value(dev, &ldo_param[ldo], uv);
  133. }
  134. static int reg_get_enable(struct udevice *dev, const struct s5m8767_para *param)
  135. {
  136. bool enable;
  137. int ret;
  138. ret = pmic_reg_read(dev->parent, param->reg_enaddr);
  139. if (ret < 0)
  140. return ret;
  141. enable = (ret >> ENABLE_SHIFT) & ENABLE_MASK;
  142. return enable;
  143. }
  144. static int reg_set_enable(struct udevice *dev, const struct s5m8767_para *param,
  145. bool enable)
  146. {
  147. int ret;
  148. ret = pmic_reg_read(dev->parent, param->reg_enaddr);
  149. if (ret < 0)
  150. return ret;
  151. ret = pmic_clrsetbits(dev->parent, param->reg_enaddr,
  152. ENABLE_MASK << ENABLE_SHIFT,
  153. enable ? param->reg_enbiton << ENABLE_SHIFT : 0);
  154. return ret;
  155. }
  156. static bool ldo_get_enable(struct udevice *dev)
  157. {
  158. int ldo = dev->driver_data;
  159. return reg_get_enable(dev, &ldo_param[ldo]);
  160. }
  161. static int ldo_set_enable(struct udevice *dev, bool enable)
  162. {
  163. int ldo = dev->driver_data;
  164. return reg_set_enable(dev, &ldo_param[ldo], enable);
  165. }
  166. static int s5m8767_buck_probe(struct udevice *dev)
  167. {
  168. struct dm_regulator_uclass_platdata *uc_pdata;
  169. uc_pdata = dev_get_uclass_platdata(dev);
  170. uc_pdata->type = REGULATOR_TYPE_BUCK;
  171. uc_pdata->mode_count = 0;
  172. return 0;
  173. }
  174. static int buck_get_value(struct udevice *dev)
  175. {
  176. int buck = dev->driver_data;
  177. return reg_get_value(dev, &buck_param[buck]);
  178. }
  179. static int buck_set_value(struct udevice *dev, int uv)
  180. {
  181. int buck = dev->driver_data;
  182. return reg_set_value(dev, &buck_param[buck], uv);
  183. }
  184. static bool buck_get_enable(struct udevice *dev)
  185. {
  186. int buck = dev->driver_data;
  187. return reg_get_enable(dev, &buck_param[buck]);
  188. }
  189. static int buck_set_enable(struct udevice *dev, bool enable)
  190. {
  191. int buck = dev->driver_data;
  192. return reg_set_enable(dev, &buck_param[buck], enable);
  193. }
  194. static const struct dm_regulator_ops s5m8767_ldo_ops = {
  195. .get_value = ldo_get_value,
  196. .set_value = ldo_set_value,
  197. .get_enable = ldo_get_enable,
  198. .set_enable = ldo_set_enable,
  199. };
  200. U_BOOT_DRIVER(s5m8767_ldo) = {
  201. .name = S5M8767_LDO_DRIVER,
  202. .id = UCLASS_REGULATOR,
  203. .ops = &s5m8767_ldo_ops,
  204. .probe = s5m8767_ldo_probe,
  205. };
  206. static const struct dm_regulator_ops s5m8767_buck_ops = {
  207. .get_value = buck_get_value,
  208. .set_value = buck_set_value,
  209. .get_enable = buck_get_enable,
  210. .set_enable = buck_set_enable,
  211. };
  212. U_BOOT_DRIVER(s5m8767_buck) = {
  213. .name = S5M8767_BUCK_DRIVER,
  214. .id = UCLASS_REGULATOR,
  215. .ops = &s5m8767_buck_ops,
  216. .probe = s5m8767_buck_probe,
  217. };