fsl_pci_init.c 25 KB

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  1. /*
  2. * Copyright 2007-2012 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <malloc.h>
  8. #include <asm/fsl_serdes.h>
  9. DECLARE_GLOBAL_DATA_PTR;
  10. /*
  11. * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  12. *
  13. * Initialize controller and call the common driver/pci pci_hose_scan to
  14. * scan for bridges and devices.
  15. *
  16. * Hose fields which need to be pre-initialized by board specific code:
  17. * regions[]
  18. * first_busno
  19. *
  20. * Fields updated:
  21. * last_busno
  22. */
  23. #include <pci.h>
  24. #include <asm/io.h>
  25. #include <asm/fsl_pci.h>
  26. #ifndef CONFIG_SYS_PCI_MEMORY_BUS
  27. #define CONFIG_SYS_PCI_MEMORY_BUS 0
  28. #endif
  29. #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
  30. #define CONFIG_SYS_PCI_MEMORY_PHYS 0
  31. #endif
  32. #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
  33. #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
  34. #endif
  35. /* Setup one inbound ATMU window.
  36. *
  37. * We let the caller decide what the window size should be
  38. */
  39. static void set_inbound_window(volatile pit_t *pi,
  40. struct pci_region *r,
  41. u64 size)
  42. {
  43. u32 sz = (__ilog2_u64(size) - 1);
  44. #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
  45. u32 flag = 0;
  46. #else
  47. u32 flag = PIWAR_LOCAL;
  48. #endif
  49. flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  50. out_be32(&pi->pitar, r->phys_start >> 12);
  51. out_be32(&pi->piwbar, r->bus_start >> 12);
  52. #ifdef CONFIG_SYS_PCI_64BIT
  53. out_be32(&pi->piwbear, r->bus_start >> 44);
  54. #else
  55. out_be32(&pi->piwbear, 0);
  56. #endif
  57. if (r->flags & PCI_REGION_PREFETCH)
  58. flag |= PIWAR_PF;
  59. out_be32(&pi->piwar, flag | sz);
  60. }
  61. int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
  62. {
  63. volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
  64. /* Reset hose to make sure its in a clean state */
  65. memset(hose, 0, sizeof(struct pci_controller));
  66. pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
  67. return fsl_is_pci_agent(hose);
  68. }
  69. static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
  70. u64 out_lo, u8 pcie_cap,
  71. volatile pit_t *pi)
  72. {
  73. struct pci_region *r = hose->regions + hose->region_count;
  74. u64 sz = min((u64)gd->ram_size, (1ull << 32));
  75. phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  76. pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  77. pci_size_t pci_sz;
  78. /* we have no space available for inbound memory mapping */
  79. if (bus_start > out_lo) {
  80. printf ("no space for inbound mapping of memory\n");
  81. return 0;
  82. }
  83. /* limit size */
  84. if ((bus_start + sz) > out_lo) {
  85. sz = out_lo - bus_start;
  86. debug ("limiting size to %llx\n", sz);
  87. }
  88. pci_sz = 1ull << __ilog2_u64(sz);
  89. /*
  90. * we can overlap inbound/outbound windows on PCI-E since RX & TX
  91. * links a separate
  92. */
  93. if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
  94. debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
  95. (u64)bus_start, (u64)phys_start, (u64)sz);
  96. pci_set_region(r, bus_start, phys_start, sz,
  97. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  98. PCI_REGION_PREFETCH);
  99. /* if we aren't an exact power of two match, pci_sz is smaller
  100. * round it up to the next power of two. We report the actual
  101. * size to pci region tracking.
  102. */
  103. if (pci_sz != sz)
  104. sz = 2ull << __ilog2_u64(sz);
  105. set_inbound_window(pi--, r++, sz);
  106. sz = 0; /* make sure we dont set the R2 window */
  107. } else {
  108. debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
  109. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  110. pci_set_region(r, bus_start, phys_start, pci_sz,
  111. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  112. PCI_REGION_PREFETCH);
  113. set_inbound_window(pi--, r++, pci_sz);
  114. sz -= pci_sz;
  115. bus_start += pci_sz;
  116. phys_start += pci_sz;
  117. pci_sz = 1ull << __ilog2_u64(sz);
  118. if (sz) {
  119. debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
  120. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  121. pci_set_region(r, bus_start, phys_start, pci_sz,
  122. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  123. PCI_REGION_PREFETCH);
  124. set_inbound_window(pi--, r++, pci_sz);
  125. sz -= pci_sz;
  126. bus_start += pci_sz;
  127. phys_start += pci_sz;
  128. }
  129. }
  130. #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  131. /*
  132. * On 64-bit capable systems, set up a mapping for all of DRAM
  133. * in high pci address space.
  134. */
  135. pci_sz = 1ull << __ilog2_u64(gd->ram_size);
  136. /* round up to the next largest power of two */
  137. if (gd->ram_size > pci_sz)
  138. pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
  139. debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
  140. (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
  141. (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
  142. (u64)pci_sz);
  143. pci_set_region(r,
  144. CONFIG_SYS_PCI64_MEMORY_BUS,
  145. CONFIG_SYS_PCI_MEMORY_PHYS,
  146. pci_sz,
  147. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  148. PCI_REGION_PREFETCH);
  149. set_inbound_window(pi--, r++, pci_sz);
  150. #else
  151. pci_sz = 1ull << __ilog2_u64(sz);
  152. if (sz) {
  153. debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
  154. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  155. pci_set_region(r, bus_start, phys_start, pci_sz,
  156. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  157. PCI_REGION_PREFETCH);
  158. sz -= pci_sz;
  159. bus_start += pci_sz;
  160. phys_start += pci_sz;
  161. set_inbound_window(pi--, r++, pci_sz);
  162. }
  163. #endif
  164. #ifdef CONFIG_PHYS_64BIT
  165. if (sz && (((u64)gd->ram_size) < (1ull << 32)))
  166. printf("Was not able to map all of memory via "
  167. "inbound windows -- %lld remaining\n", sz);
  168. #endif
  169. hose->region_count = r - hose->regions;
  170. return 1;
  171. }
  172. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  173. static void fsl_pcie_boot_master(pit_t *pi)
  174. {
  175. /* configure inbound window for slave's u-boot image */
  176. debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
  177. "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
  178. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  179. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
  180. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  181. struct pci_region r_inbound;
  182. u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
  183. - 1;
  184. pci_set_region(&r_inbound,
  185. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
  186. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  187. sz_inbound,
  188. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  189. set_inbound_window(pi--, &r_inbound,
  190. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  191. /* configure inbound window for slave's u-boot image */
  192. debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
  193. "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
  194. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  195. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
  196. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  197. pci_set_region(&r_inbound,
  198. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
  199. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  200. sz_inbound,
  201. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  202. set_inbound_window(pi--, &r_inbound,
  203. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  204. /* configure inbound window for slave's ucode and ENV */
  205. debug("PCIEBOOT - MASTER: Inbound window for slave's "
  206. "ucode and ENV; "
  207. "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
  208. (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
  209. (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
  210. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
  211. sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
  212. - 1;
  213. pci_set_region(&r_inbound,
  214. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
  215. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
  216. sz_inbound,
  217. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  218. set_inbound_window(pi--, &r_inbound,
  219. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
  220. }
  221. static void fsl_pcie_boot_master_release_slave(int port)
  222. {
  223. unsigned long release_addr;
  224. /* now release slave's core 0 */
  225. switch (port) {
  226. case 1:
  227. release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
  228. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
  229. break;
  230. #ifdef CONFIG_SYS_PCIE2_MEM_VIRT
  231. case 2:
  232. release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
  233. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
  234. break;
  235. #endif
  236. #ifdef CONFIG_SYS_PCIE3_MEM_VIRT
  237. case 3:
  238. release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
  239. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
  240. break;
  241. #endif
  242. default:
  243. release_addr = 0;
  244. break;
  245. }
  246. if (release_addr != 0) {
  247. out_be32((void *)release_addr,
  248. CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
  249. debug("PCIEBOOT - MASTER: "
  250. "Release slave successfully! Now the slave should start up!\n");
  251. } else {
  252. debug("PCIEBOOT - MASTER: "
  253. "Release slave failed!\n");
  254. }
  255. }
  256. #endif
  257. void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
  258. {
  259. u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
  260. u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
  261. u16 temp16;
  262. u32 temp32;
  263. u32 block_rev;
  264. int enabled, r, inbound = 0;
  265. u16 ltssm;
  266. u8 temp8, pcie_cap;
  267. int pcie_cap_pos;
  268. int pci_dcr;
  269. int pci_dsr;
  270. int pci_lsr;
  271. #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
  272. int pci_lcr;
  273. #endif
  274. volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
  275. struct pci_region *reg = hose->regions + hose->region_count;
  276. pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
  277. /* Initialize ATMU registers based on hose regions and flags */
  278. volatile pot_t *po = &pci->pot[1]; /* skip 0 */
  279. volatile pit_t *pi;
  280. u64 out_hi = 0, out_lo = -1ULL;
  281. u32 pcicsrbar, pcicsrbar_sz;
  282. pci_setup_indirect(hose, cfg_addr, cfg_data);
  283. block_rev = in_be32(&pci->block_rev1);
  284. if (PEX_IP_BLK_REV_2_2 <= block_rev) {
  285. pi = &pci->pit[2]; /* 0xDC0 */
  286. } else {
  287. pi = &pci->pit[3]; /* 0xDE0 */
  288. }
  289. /* Handle setup of outbound windows first */
  290. for (r = 0; r < hose->region_count; r++) {
  291. unsigned long flags = hose->regions[r].flags;
  292. u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
  293. flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
  294. if (flags != PCI_REGION_SYS_MEMORY) {
  295. u64 start = hose->regions[r].bus_start;
  296. u64 end = start + hose->regions[r].size;
  297. out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
  298. out_be32(&po->potar, start >> 12);
  299. #ifdef CONFIG_SYS_PCI_64BIT
  300. out_be32(&po->potear, start >> 44);
  301. #else
  302. out_be32(&po->potear, 0);
  303. #endif
  304. if (hose->regions[r].flags & PCI_REGION_IO) {
  305. out_be32(&po->powar, POWAR_EN | sz |
  306. POWAR_IO_READ | POWAR_IO_WRITE);
  307. } else {
  308. out_be32(&po->powar, POWAR_EN | sz |
  309. POWAR_MEM_READ | POWAR_MEM_WRITE);
  310. out_lo = min(start, out_lo);
  311. out_hi = max(end, out_hi);
  312. }
  313. po++;
  314. }
  315. }
  316. debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
  317. /* setup PCSRBAR/PEXCSRBAR */
  318. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
  319. pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
  320. pcicsrbar_sz = ~pcicsrbar_sz + 1;
  321. if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
  322. (out_lo > 0x100000000ull))
  323. pcicsrbar = 0x100000000ull - pcicsrbar_sz;
  324. else
  325. pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
  326. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
  327. out_lo = min(out_lo, (u64)pcicsrbar);
  328. debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
  329. pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
  330. pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
  331. hose->region_count++;
  332. /* see if we are a PCIe or PCI controller */
  333. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  334. pci_dcr = pcie_cap_pos + 0x08;
  335. pci_dsr = pcie_cap_pos + 0x0a;
  336. pci_lsr = pcie_cap_pos + 0x12;
  337. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  338. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  339. /* boot from PCIE --master */
  340. char *s = getenv("bootmaster");
  341. char pcie[6];
  342. sprintf(pcie, "PCIE%d", pci_info->pci_num);
  343. if (s && (strcmp(s, pcie) == 0)) {
  344. debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
  345. pci_info->pci_num);
  346. fsl_pcie_boot_master((pit_t *)pi);
  347. } else {
  348. /* inbound */
  349. inbound = fsl_pci_setup_inbound_windows(hose,
  350. out_lo, pcie_cap, pi);
  351. }
  352. #else
  353. /* inbound */
  354. inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
  355. #endif
  356. for (r = 0; r < hose->region_count; r++)
  357. debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
  358. (u64)hose->regions[r].phys_start,
  359. (u64)hose->regions[r].bus_start,
  360. (u64)hose->regions[r].size,
  361. hose->regions[r].flags);
  362. pci_register_hose(hose);
  363. pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
  364. hose->current_busno = hose->first_busno;
  365. out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
  366. out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
  367. * - Master abort (pci)
  368. * - Master PERR (pci)
  369. * - ICCA (PCIe)
  370. */
  371. pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
  372. temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
  373. pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
  374. #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
  375. pci_lcr = pcie_cap_pos + 0x10;
  376. temp32 = 0;
  377. pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
  378. temp32 &= ~0x03; /* Disable ASPM */
  379. pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
  380. udelay(1);
  381. #endif
  382. if (pcie_cap == PCI_CAP_ID_EXP) {
  383. if (block_rev >= PEX_IP_BLK_REV_3_0) {
  384. #define PEX_CSR0_LTSSM_MASK 0xFC
  385. #define PEX_CSR0_LTSSM_SHIFT 2
  386. ltssm = (in_be32(&pci->pex_csr0)
  387. & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
  388. enabled = (ltssm == 0x11) ? 1 : 0;
  389. #ifdef CONFIG_FSL_PCIE_RESET
  390. int i;
  391. /* assert PCIe reset */
  392. setbits_be32(&pci->pdb_stat, 0x08000000);
  393. (void) in_be32(&pci->pdb_stat);
  394. udelay(1000);
  395. /* clear PCIe reset */
  396. clrbits_be32(&pci->pdb_stat, 0x08000000);
  397. asm("sync;isync");
  398. for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
  399. pci_hose_read_config_word(hose, dev, PCI_LTSSM,
  400. &ltssm);
  401. udelay(1000);
  402. }
  403. #endif
  404. } else {
  405. /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
  406. /* enabled = ltssm >= PCI_LTSSM_L0; */
  407. pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
  408. enabled = ltssm >= PCI_LTSSM_L0;
  409. #ifdef CONFIG_FSL_PCIE_RESET
  410. if (ltssm == 1) {
  411. int i;
  412. debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
  413. /* assert PCIe reset */
  414. setbits_be32(&pci->pdb_stat, 0x08000000);
  415. (void) in_be32(&pci->pdb_stat);
  416. udelay(100);
  417. debug(" Asserting PCIe reset @%p = %x\n",
  418. &pci->pdb_stat, in_be32(&pci->pdb_stat));
  419. /* clear PCIe reset */
  420. clrbits_be32(&pci->pdb_stat, 0x08000000);
  421. asm("sync;isync");
  422. for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
  423. pci_hose_read_config_word(hose, dev, PCI_LTSSM,
  424. &ltssm);
  425. udelay(1000);
  426. debug("....PCIe link error. "
  427. "LTSSM=0x%02x.\n", ltssm);
  428. }
  429. enabled = ltssm >= PCI_LTSSM_L0;
  430. /* we need to re-write the bar0 since a reset will
  431. * clear it
  432. */
  433. pci_hose_write_config_dword(hose, dev,
  434. PCI_BASE_ADDRESS_0, pcicsrbar);
  435. }
  436. #endif
  437. }
  438. #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  439. if (enabled == 0) {
  440. serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  441. temp32 = in_be32(&srds_regs->srdspccr0);
  442. if ((temp32 >> 28) == 3) {
  443. int i;
  444. out_be32(&srds_regs->srdspccr0, 2 << 28);
  445. setbits_be32(&pci->pdb_stat, 0x08000000);
  446. in_be32(&pci->pdb_stat);
  447. udelay(100);
  448. clrbits_be32(&pci->pdb_stat, 0x08000000);
  449. asm("sync;isync");
  450. for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
  451. pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
  452. udelay(1000);
  453. }
  454. enabled = ltssm >= PCI_LTSSM_L0;
  455. }
  456. }
  457. #endif
  458. if (!enabled) {
  459. /* Let the user know there's no PCIe link for root
  460. * complex. for endpoint, the link may not setup, so
  461. * print undetermined.
  462. */
  463. if (fsl_is_pci_agent(hose))
  464. printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
  465. else
  466. printf("no link, regs @ 0x%lx\n", pci_info->regs);
  467. hose->last_busno = hose->first_busno;
  468. return;
  469. }
  470. out_be32(&pci->pme_msg_det, 0xffffffff);
  471. out_be32(&pci->pme_msg_int_en, 0xffffffff);
  472. /* Print the negotiated PCIe link width */
  473. pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
  474. printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
  475. (temp16 & 0xf), pci_info->regs);
  476. hose->current_busno++; /* Start scan with secondary */
  477. pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
  478. }
  479. /* Use generic setup_device to initialize standard pci regs,
  480. * but do not allocate any windows since any BAR found (such
  481. * as PCSRBAR) is not in this cpu's memory space.
  482. */
  483. pciauto_setup_device(hose, dev, 0, hose->pci_mem,
  484. hose->pci_prefetch, hose->pci_io);
  485. if (inbound) {
  486. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
  487. pci_hose_write_config_word(hose, dev, PCI_COMMAND,
  488. temp16 | PCI_COMMAND_MEMORY);
  489. }
  490. #ifndef CONFIG_PCI_NOSCAN
  491. if (!fsl_is_pci_agent(hose)) {
  492. debug(" Scanning PCI bus %02x\n",
  493. hose->current_busno);
  494. hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
  495. } else {
  496. debug(" Not scanning PCI bus %02x. PI=%x\n",
  497. hose->current_busno, temp8);
  498. hose->last_busno = hose->current_busno;
  499. }
  500. /* if we are PCIe - update limit regs and subordinate busno
  501. * for the virtual P2P bridge
  502. */
  503. if (pcie_cap == PCI_CAP_ID_EXP) {
  504. pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
  505. }
  506. #else
  507. hose->last_busno = hose->current_busno;
  508. #endif
  509. /* Clear all error indications */
  510. if (pcie_cap == PCI_CAP_ID_EXP)
  511. out_be32(&pci->pme_msg_det, 0xffffffff);
  512. out_be32(&pci->pedr, 0xffffffff);
  513. pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
  514. if (temp16) {
  515. pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
  516. }
  517. pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
  518. if (temp16) {
  519. pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
  520. }
  521. }
  522. int fsl_is_pci_agent(struct pci_controller *hose)
  523. {
  524. int pcie_cap_pos;
  525. u8 pcie_cap;
  526. pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
  527. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  528. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  529. if (pcie_cap == PCI_CAP_ID_EXP) {
  530. u8 header_type;
  531. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
  532. &header_type);
  533. return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
  534. } else {
  535. u8 prog_if;
  536. pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
  537. /* Programming Interface (PCI_CLASS_PROG)
  538. * 0 == pci host or pcie root-complex,
  539. * 1 == pci agent or pcie end-point
  540. */
  541. return (prog_if == FSL_PROG_IF_AGENT);
  542. }
  543. }
  544. int fsl_pci_init_port(struct fsl_pci_info *pci_info,
  545. struct pci_controller *hose, int busno)
  546. {
  547. volatile ccsr_fsl_pci_t *pci;
  548. struct pci_region *r;
  549. pci_dev_t dev = PCI_BDF(busno,0,0);
  550. int pcie_cap_pos;
  551. u8 pcie_cap;
  552. pci = (ccsr_fsl_pci_t *) pci_info->regs;
  553. /* on non-PCIe controllers we don't have pme_msg_det so this code
  554. * should do nothing since the read will return 0
  555. */
  556. if (in_be32(&pci->pme_msg_det)) {
  557. out_be32(&pci->pme_msg_det, 0xffffffff);
  558. debug (" with errors. Clearing. Now 0x%08x",
  559. pci->pme_msg_det);
  560. }
  561. r = hose->regions + hose->region_count;
  562. /* outbound memory */
  563. pci_set_region(r++,
  564. pci_info->mem_bus,
  565. pci_info->mem_phys,
  566. pci_info->mem_size,
  567. PCI_REGION_MEM);
  568. /* outbound io */
  569. pci_set_region(r++,
  570. pci_info->io_bus,
  571. pci_info->io_phys,
  572. pci_info->io_size,
  573. PCI_REGION_IO);
  574. hose->region_count = r - hose->regions;
  575. hose->first_busno = busno;
  576. fsl_pci_init(hose, pci_info);
  577. if (fsl_is_pci_agent(hose)) {
  578. fsl_pci_config_unlock(hose);
  579. hose->last_busno = hose->first_busno;
  580. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  581. } else {
  582. /* boot from PCIE --master releases slave's core 0 */
  583. char *s = getenv("bootmaster");
  584. char pcie[6];
  585. sprintf(pcie, "PCIE%d", pci_info->pci_num);
  586. if (s && (strcmp(s, pcie) == 0))
  587. fsl_pcie_boot_master_release_slave(pci_info->pci_num);
  588. #endif
  589. }
  590. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  591. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  592. printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
  593. "e" : "", pci_info->pci_num,
  594. hose->first_busno, hose->last_busno);
  595. return(hose->last_busno + 1);
  596. }
  597. /* Enable inbound PCI config cycles for agent/endpoint interface */
  598. void fsl_pci_config_unlock(struct pci_controller *hose)
  599. {
  600. pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
  601. int pcie_cap_pos;
  602. u8 pcie_cap;
  603. u16 pbfr;
  604. if (!fsl_is_pci_agent(hose))
  605. return;
  606. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  607. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  608. if (pcie_cap != 0x0) {
  609. ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
  610. u32 block_rev = in_be32(&pci->block_rev1);
  611. /* PCIe - set CFG_READY bit of Configuration Ready Register */
  612. if (block_rev >= PEX_IP_BLK_REV_3_0)
  613. setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
  614. else
  615. pci_hose_write_config_byte(hose, dev,
  616. FSL_PCIE_CFG_RDY, 0x1);
  617. } else {
  618. /* PCI - clear ACL bit of PBFR */
  619. pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
  620. pbfr &= ~0x20;
  621. pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
  622. }
  623. }
  624. #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
  625. defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
  626. int fsl_configure_pcie(struct fsl_pci_info *info,
  627. struct pci_controller *hose,
  628. const char *connected, int busno)
  629. {
  630. int is_endpoint;
  631. set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
  632. set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
  633. is_endpoint = fsl_setup_hose(hose, info->regs);
  634. printf("PCIe%u: %s", info->pci_num,
  635. is_endpoint ? "Endpoint" : "Root Complex");
  636. if (connected)
  637. printf(" of %s", connected);
  638. puts(", ");
  639. return fsl_pci_init_port(info, hose, busno);
  640. }
  641. #if defined(CONFIG_FSL_CORENET)
  642. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  643. #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
  644. #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
  645. #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
  646. #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
  647. #else
  648. #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
  649. #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
  650. #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
  651. #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
  652. #endif
  653. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
  654. #elif defined(CONFIG_MPC85xx)
  655. #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
  656. #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
  657. #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
  658. #define _DEVDISR_PCIE4 0
  659. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
  660. #elif defined(CONFIG_MPC86xx)
  661. #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
  662. #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
  663. #define _DEVDISR_PCIE3 0
  664. #define _DEVDISR_PCIE4 0
  665. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
  666. (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
  667. #else
  668. #error "No defines for DEVDISR_PCIE"
  669. #endif
  670. /* Implement a dummy function for those platforms w/o SERDES */
  671. static const char *__board_serdes_name(enum srds_prtcl device)
  672. {
  673. switch (device) {
  674. #ifdef CONFIG_SYS_PCIE1_NAME
  675. case PCIE1:
  676. return CONFIG_SYS_PCIE1_NAME;
  677. #endif
  678. #ifdef CONFIG_SYS_PCIE2_NAME
  679. case PCIE2:
  680. return CONFIG_SYS_PCIE2_NAME;
  681. #endif
  682. #ifdef CONFIG_SYS_PCIE3_NAME
  683. case PCIE3:
  684. return CONFIG_SYS_PCIE3_NAME;
  685. #endif
  686. #ifdef CONFIG_SYS_PCIE4_NAME
  687. case PCIE4:
  688. return CONFIG_SYS_PCIE4_NAME;
  689. #endif
  690. default:
  691. return NULL;
  692. }
  693. return NULL;
  694. }
  695. __attribute__((weak, alias("__board_serdes_name"))) const char *
  696. board_serdes_name(enum srds_prtcl device);
  697. static u32 devdisr_mask[] = {
  698. _DEVDISR_PCIE1,
  699. _DEVDISR_PCIE2,
  700. _DEVDISR_PCIE3,
  701. _DEVDISR_PCIE4,
  702. };
  703. int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
  704. struct fsl_pci_info *pci_info)
  705. {
  706. struct pci_controller *hose;
  707. int num = dev - PCIE1;
  708. hose = calloc(1, sizeof(struct pci_controller));
  709. if (!hose)
  710. return busno;
  711. if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
  712. busno = fsl_configure_pcie(pci_info, hose,
  713. board_serdes_name(dev), busno);
  714. } else {
  715. printf("PCIe%d: disabled\n", num + 1);
  716. }
  717. return busno;
  718. }
  719. int fsl_pcie_init_board(int busno)
  720. {
  721. struct fsl_pci_info pci_info;
  722. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
  723. u32 devdisr;
  724. u32 *addr;
  725. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  726. addr = &gur->devdisr3;
  727. #else
  728. addr = &gur->devdisr;
  729. #endif
  730. devdisr = in_be32(addr);
  731. #ifdef CONFIG_PCIE1
  732. SET_STD_PCIE_INFO(pci_info, 1);
  733. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
  734. #else
  735. setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
  736. #endif
  737. #ifdef CONFIG_PCIE2
  738. SET_STD_PCIE_INFO(pci_info, 2);
  739. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
  740. #else
  741. setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
  742. #endif
  743. #ifdef CONFIG_PCIE3
  744. SET_STD_PCIE_INFO(pci_info, 3);
  745. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
  746. #else
  747. setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
  748. #endif
  749. #ifdef CONFIG_PCIE4
  750. SET_STD_PCIE_INFO(pci_info, 4);
  751. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
  752. #else
  753. setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
  754. #endif
  755. return busno;
  756. }
  757. #else
  758. int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
  759. struct fsl_pci_info *pci_info)
  760. {
  761. return busno;
  762. }
  763. int fsl_pcie_init_board(int busno)
  764. {
  765. return busno;
  766. }
  767. #endif
  768. #ifdef CONFIG_OF_BOARD_SETUP
  769. #include <libfdt.h>
  770. #include <fdt_support.h>
  771. void ft_fsl_pci_setup(void *blob, const char *pci_compat,
  772. unsigned long ctrl_addr)
  773. {
  774. int off;
  775. u32 bus_range[2];
  776. phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
  777. struct pci_controller *hose;
  778. hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
  779. /* convert ctrl_addr to true physical address */
  780. p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
  781. p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
  782. off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
  783. if (off < 0)
  784. return;
  785. /* We assume a cfg_addr not being set means we didn't setup the controller */
  786. if ((hose == NULL) || (hose->cfg_addr == NULL)) {
  787. fdt_del_node(blob, off);
  788. } else {
  789. bus_range[0] = 0;
  790. bus_range[1] = hose->last_busno - hose->first_busno;
  791. fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
  792. fdt_pci_dma_ranges(blob, off, hose);
  793. }
  794. }
  795. #endif