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t1040.c

t1040.c 1.9 KB
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  1. /*
    2. 

  2.  * Copyright 2013 Freescale Semiconductor, Inc.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier:	GPL-2.0+
    5. 

  5.  */
    6. 

  6. #include <common.h>
    7. 

  7. #include <phy.h>
    8. 

  8. #include <fm_eth.h>
    9. 

  9. #include <asm/io.h>
    10. 

  10. #include <asm/immap_85xx.h>
    11. 

  11. #include <asm/fsl_serdes.h>
    12. 

  12. 

  13. phy_interface_t fman_port_enet_if(enum fm_port port)
    14. 

  14. {
    15. 

  15. 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
    16. 

  16. 	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
    17. 

  17. 

  18. 	/* handle RGMII first */
    19. 

  19. 	if ((port == FM1_DTSEC2) &&
    20. 

  20. 	    ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
    21. 

  21. 			FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) {
    22. 

  22. 		if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
    23. 

  23. 				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
    24. 

  24. 			return PHY_INTERFACE_MODE_RGMII;
    25. 

  25. 		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
    26. 

  26. 				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
    27. 

  27. 			return PHY_INTERFACE_MODE_MII;
    28. 

  28. 	}
    29. 

  29. 

  30. 	if ((port == FM1_DTSEC4) &&
    31. 

  31. 	    ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
    32. 

  32. 			FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) {
    33. 

  33. 		if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
    34. 

  34. 				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
    35. 

  35. 			return PHY_INTERFACE_MODE_RGMII;
    36. 

  36. 		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
    37. 

  37. 				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
    38. 

  38. 			return PHY_INTERFACE_MODE_MII;
    39. 

  39. 	}
    40. 

  40. 

  41. 	if (port == FM1_DTSEC5) {
    42. 

  42. 		if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
    43. 

  43. 				FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
    44. 

  44. 			return PHY_INTERFACE_MODE_RGMII;
    45. 

  45. 		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
    46. 

  46. 				FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
    47. 

  47. 			return PHY_INTERFACE_MODE_MII;
    48. 

  48. 	}
    49. 

  49. 

  50. 	switch (port) {
    51. 

  51. 	case FM1_DTSEC1:
    52. 

  52. 	case FM1_DTSEC2:
    53. 

  53. 		if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) ||
    54. 

  54. 		    is_serdes_configured(SGMII_SW1_MAC1  + port - FM1_DTSEC1))
    55. 

  55. 			return PHY_INTERFACE_MODE_QSGMII;
    56. 

  56. 	case FM1_DTSEC3:
    57. 

  57. 	case FM1_DTSEC4:
    58. 

  58. 	case FM1_DTSEC5:
    59. 

  59. 		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
    60. 

  60. 			return PHY_INTERFACE_MODE_SGMII;
    61. 

  61. 		break;
    62. 

  62. 	default:
    63. 

  63. 		return PHY_INTERFACE_MODE_NONE;
    64. 

  64. 	}
    65. 

  65. 

  66. 	return PHY_INTERFACE_MODE_NONE;
    67. 

  67. }
    68.